From patchwork Fri Jul 9 04:31:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24C25C07E99 for ; Fri, 9 Jul 2021 04:31:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F42E6144F for ; Fri, 9 Jul 2021 04:31:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229762AbhGIEec (ORCPT ); Fri, 9 Jul 2021 00:34:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229804AbhGIEeZ (ORCPT ); Fri, 9 Jul 2021 00:34:25 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24FE6C061766 for ; Thu, 8 Jul 2021 21:31:41 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 11so1905134ljv.1 for ; Thu, 08 Jul 2021 21:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=sParuvrSW3yxOcQImsE/pSCTQsOWei74sYLKne+13T8AGuPpPTPGmK5tqJ4t/huvC5 JqLDLskOrOsSFTCiWSPOnOYtGMF4nepGfge0N7s3Hc2mQCV92Y5FnUvfk0avW1wP+c/O zzNNICJ5cPLJvz5M4slRZs6w+pZrJ2ssyQW6qzU7Zf7w27OyOE2+MuwolUJ6dxR/tcoq vY/bsMKFBI5LVvmLS9I2oRBAiazKiG3T7ow9wMDWwo8URO7kgblsJCAbCSFsR5eFXJjI OyANlUpiTCdH4cosnKXw09vr+OuDE0MVDu62o3ozIoT9t05f2bPckUVb+Wn8gGPc1hu4 5xMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=e8Wg5ES3yaOYu21baKFlO2D64chCqzgb4/IRhmeiddzLce3mpl1vAZjCyKc2Y+EKAw dJleTG5W4HPmyHqPjQisK1Xu/Qd4wBe9P46j87a/3Qv3Yj4GSkBYw0yYsvhGD8cXEd+U Q2RXZ3Y8YhwBK3hVpdzzdc4Z9WdWTz2v1bMLqLes/IlyeTst8MKKfs5uQOmmWxAtPczL SUsNo+NR+4PkFmyBo7/hNuTQGJc9vUpugYgl3wv/QMBKyCky2/gOk3q7nZ+FTGujEtJt 65q0T4ITRaPvp80GSWRHxZtz584QQrpwc1gwCA5LVWQSOK3k5TDH4npCFkJ2ycNJIU9d uodQ== X-Gm-Message-State: AOAM5323dKoAb+MtWB08dyp5TPW1nGk1SakRetlhyYUsBjzk9UMsenyM FWfmcaFkNVRrGNvkqmUTdQLsGQ== X-Google-Smtp-Source: ABdhPJzC7Z+xZjYcUQMVMQp4Gm4Y3ui0lhahHrsnQGoO/Uq+qBwQl2gqLJ7mDclck5qgW7HBdX0rhQ== X-Received: by 2002:a2e:a54a:: with SMTP id e10mr27331977ljn.120.1625805099320; Thu, 08 Jul 2021 21:31:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 1/7] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Fri, 9 Jul 2021 07:31:30 +0300 Message-Id: <20210709043136.533205-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..d5c4fed56b6e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -55,6 +55,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -69,6 +74,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -89,5 +95,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... From patchwork Fri Jul 9 04:31:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE96C07E9C for ; Fri, 9 Jul 2021 04:31:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCFCC61451 for ; Fri, 9 Jul 2021 04:31:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229719AbhGIEeb (ORCPT ); Fri, 9 Jul 2021 00:34:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229908AbhGIEe0 (ORCPT ); Fri, 9 Jul 2021 00:34:26 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E51DDC06175F for ; Thu, 8 Jul 2021 21:31:41 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id r16so5928170ljk.9 for ; Thu, 08 Jul 2021 21:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+l6RNZfO6t53h33tKaqwIC7dbp1+6FXvY3b6ZyHCbIM=; b=WlwvwLrQoeElCrOz8khcG1qUMUEX4LRnDzheKeTWgD0s/tDz3fm1rN5TCIGDvNLuWo VCeygJMIaI/e0Mx4OmU4mn7CbsYP+a2twV4vfJ1QwL1CbFLkihZ1ers+wr1iLTyzN6hI rVEyAGniCLt28C3LKq5xbcM0+urmeCV3MuGXUggWspmcLEXOKDmV/IMYZnkFONNhqa8D NMfMfVYJdp2WVsQ30HIsoUniSnmW1SERAu5uRkjqzYBJknZIlFVxMESm+QpmKsmvE5t2 E7nyWENWm9fzwvquITAraHwHDC8DFgOtwlP9nr/T+YzFL2Lgpe5g8QXOeZDOrZeuk45/ 0kNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+l6RNZfO6t53h33tKaqwIC7dbp1+6FXvY3b6ZyHCbIM=; b=NldGMSgAKEpCcQhcHeUasgR7UJTScW70Ey5cTPhGGOQaeasvrUrnUWlkejgMBb3/aA +rV2Vb7zIjvM+I09pek9MZrb6WC3d+ysmtuvmnyj1S3vqDMNkhEfHexrZ69c3vHddWr5 VR5L7rZvxZPMdaNKYvO1BjLi+WuJ2H/O5DTERN/FS1eqI0E2/3XtIsAvLp3rCWq50l2x Y8gMzI0zmceRdgOTj+7L2mVfMu0Wavw3wGrV6PrrpBeU0f8wd8rlIZlqvyZL1Ry5Rs8Z /p/hKQsLQU8FAVdUow8tSCiiUVF1zdACBVRkIFPb1BvyrcNq8lyHX1HCXebPlhVVWmTp 9XcQ== X-Gm-Message-State: AOAM533TpRNIRlIfSwCvGWt9SnCoeLeI0yz/0OuzMWAYQPNsfagFVUPn waiCF7BfHfOUhAZHQRoj3i/DeA== X-Google-Smtp-Source: ABdhPJzJ2+kFilhrLt7SsXBip2dwdXrJIpKz5q8WYP9kQ47A3T9krwTqZFcblwqNnP6Hh6jPrB0U8w== X-Received: by 2002:a2e:9c84:: with SMTP id x4mr22464773lji.161.1625805100191; Thu, 08 Jul 2021 21:31:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:39 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 2/7] dt-bindings: clock: qcom, videocc: add mmcx power domain Date: Fri, 9 Jul 2021 07:31:31 +0300 Message-Id: <20210709043136.533205-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..db4ada6acf27 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -61,6 +66,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -69,5 +75,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... 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[23.128.96.18]) by mx.google.com with ESMTP id b20si5191506jat.60.2021.07.08.21.32.16; Thu, 08 Jul 2021 21:32:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AJP+QloJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229707AbhGIEea (ORCPT + 17 others); Fri, 9 Jul 2021 00:34:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbhGIEe0 (ORCPT ); Fri, 9 Jul 2021 00:34:26 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C474AC061762 for ; Thu, 8 Jul 2021 21:31:42 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 8so8963738lfp.9 for ; Thu, 08 Jul 2021 21:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wyfQ/AaQKOiokX60V253WPiUw+AOPKvuwfW4bIOFEAY=; b=AJP+QloJmqmzs+VJU10kG5J/rkfgBe3Tio+qlCxt/ubsoyKjmKRrEWZIMKq+ccRYWl ojA1gund8aY9+Q+hLyNNhB/XeZGWHRnT/sD+Pa4wIyWeed5z6MQ4xn4N9gr3DR7Yir5V JcBzKcGTVVy5YhnAWqDsch8bhfwqDN6ZJLInvUtRr+fxkBI4ngrofr5A9ceIOn8IjXc0 itswHZhQLN/eIAqeW99pbsrQWw0nfloAfJMNA6uzpWqVEOGCwz4ScuLhIrTj8GmEOeZx riMWmZ1I7Dld/D91a57dMk+nmG9JCW8aBvdaB2ut4RYYyxRajF3smG6HAYMs8sYza1kx 0uJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wyfQ/AaQKOiokX60V253WPiUw+AOPKvuwfW4bIOFEAY=; b=pvr7dkzHDP+lbGo7br6VcUNxLgWJ3v2FhJXiuwdsGCQaIRMAUbW9KfoL05nv2PeOzL AVusjLeGXCnQXsXiiQzc4jQmgqjXHw4cOVJQAHIv+r0wYIUSYniotLNqJYgdEki3EGP5 ilumGMNmLTb3vSKozPa3jGAfSVlhSnax8jy1GQIDV3r74wA63w71dLcBAsZDygc0wovQ OCFOiOmPtLOCubhwcyy5pWjyCH25D8IkPMq7PoX8FvSlBWk8JwZhkLV8+/ZIn+Tc5EvX GN7g/JhXgtBvwKAIkO1BFdAcAlHlnd5vvpyvmgqgeC47ZutqbHr3ROgUenG+UHf8csQ1 Mvyg== X-Gm-Message-State: AOAM530pXKY9d2NXbST1iZk+rpbbT1sbbeaSLAmVqYog0HJ057a3MSzc mfzsp2OzQQVWflURJWqi0gv1zg== X-Received: by 2002:a19:e04a:: with SMTP id g10mr27341156lfj.561.1625805101114; Thu, 08 Jul 2021 21:31:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 3/7] PM: domains: Add support for runtime PM Date: Fri, 9 Jul 2021 07:31:32 +0300 Message-Id: <20210709043136.533205-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Registers for some genpds can be located in the SoC area, powered up by another power domain. To enabled access to those registers, respective domain should be turned on. This patch adds basic infrastructure to the genpd code to allow implementing drivers for such genpd. PM domain can provide the parent device through the genpd->dev.parent pointer. If its provided at the pm_genpd_init() call time and if it is pm-enabled, genpd power_on and power_off operations will call pm_runtime_get_sync() before powering up the domain and pm_runtime_put_sync() after powering it down. Signed-off-by: Dmitry Baryshkov --- drivers/base/power/domain.c | 33 +++++++++++++++++++++++++++++++++ include/linux/pm_domain.h | 6 ++++++ 2 files changed, 39 insertions(+) -- 2.30.2 diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index e5d97174c254..7d49531c9731 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -482,6 +482,30 @@ void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next) } EXPORT_SYMBOL_GPL(dev_pm_genpd_set_next_wakeup); +static int _genpd_pm_runtime_get(struct generic_pm_domain *genpd) +{ + int ret; + + if (!(genpd->flags & _GENPD_FLAG_RPM_ENABLED)) + return 0; + + ret = pm_runtime_get_sync(genpd->dev.parent); + if (ret < 0) { + pm_runtime_put_noidle(genpd->dev.parent); + return ret; + } + + return 0; +} + +static void _genpd_pm_runtime_put(struct generic_pm_domain *genpd) +{ + if (!(genpd->flags & _GENPD_FLAG_RPM_ENABLED)) + return; + + pm_runtime_put_sync(genpd->dev.parent); +} + static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) { unsigned int state_idx = genpd->state_idx; @@ -497,6 +521,10 @@ static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) if (ret) return ret; + ret = _genpd_pm_runtime_get(genpd); + if (ret) + return ret; + if (!genpd->power_on) goto out; @@ -526,6 +554,7 @@ static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) raw_notifier_call_chain(&genpd->power_notifiers, GENPD_NOTIFY_ON, NULL); return 0; err: + _genpd_pm_runtime_put(genpd); raw_notifier_call_chain(&genpd->power_notifiers, GENPD_NOTIFY_OFF, NULL); return ret; @@ -572,6 +601,7 @@ static int _genpd_power_off(struct generic_pm_domain *genpd, bool timed) genpd->name, "off", elapsed_ns); out: + _genpd_pm_runtime_put(genpd); raw_notifier_call_chain(&genpd->power_notifiers, GENPD_NOTIFY_OFF, NULL); return 0; @@ -1986,6 +2016,9 @@ int pm_genpd_init(struct generic_pm_domain *genpd, genpd->domain.ops.complete = genpd_complete; genpd->domain.start = genpd_dev_pm_start; + if (genpd->dev.parent && pm_runtime_enabled(genpd->dev.parent)) + genpd->flags |= _GENPD_FLAG_RPM_ENABLED; + if (genpd->flags & GENPD_FLAG_PM_CLK) { genpd->dev_ops.stop = pm_clk_suspend; genpd->dev_ops.start = pm_clk_resume; diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 21a0577305ef..e86cd7cfc9ec 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -60,6 +60,10 @@ * GENPD_FLAG_MIN_RESIDENCY: Enable the genpd governor to consider its * components' next wakeup when determining the * optimal idle state. + * + * _GENPD_FLAG_RPM_ENABLED: Use genpd's parent dev for runtime power + * management. There is no need to set this flag, + * it will be detected automatically. */ #define GENPD_FLAG_PM_CLK (1U << 0) #define GENPD_FLAG_IRQ_SAFE (1U << 1) @@ -69,6 +73,8 @@ #define GENPD_FLAG_RPM_ALWAYS_ON (1U << 5) #define GENPD_FLAG_MIN_RESIDENCY (1U << 6) +#define _GENPD_FLAG_RPM_ENABLED (1U << 31) + enum gpd_status { GENPD_STATE_ON = 0, /* PM domain is on */ GENPD_STATE_OFF, /* PM domain is off */ From patchwork Fri Jul 9 04:31:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471770 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp944824jao; Thu, 8 Jul 2021 21:32:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMb+YZZRmqTHercUt8NQDBYNzRDJA+2HeRwM34/xUf4Yj5nGcsv9hHZq5Tdmd9M50Hi+ff X-Received: by 2002:a92:de0a:: with SMTP id x10mr1294525ilm.215.1625805139728; Thu, 08 Jul 2021 21:32:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625805139; cv=none; d=google.com; s=arc-20160816; b=KrroKQO0j/4hUr6P7rF+KY8mIbmEXQ4QnMIUrwSWyYJIRHCwDu+Cbc3p09EY+eEqq3 ZPvw+twVjLlcLocNOyMwQfEpnypN0Qd1n5eXv5sOxm4dVjSfWzkX4uMSCfFcT+CcBQjK vIH6HGyEmueM7UX34kl9yGOqMZF7zsATijOilZK6fn00/SbnsA3ff62k3G4FdQmjz6GQ PsBgFx427I1SVcfTDxPAusO7pAIYEWobgOSnGlXP5K/R1QynxR+dHqfurWbAmv2ifJsn c7DNs1So0eH7iSgiIuAtJHeg9bRwFcTuYc5vBEKCqSdxHO7w9ZXZ3aldmqlk0tbOAqjb 0p3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=89M3kJH8Z+ezz3X5xX4Jb+p6yEZY6o3ZbKwB3aRtLuw=; b=M9ICZTHo53aO69Fhia/Y619KHz0CCF4BsicXZ+/8WkUdUkGs4H81UY67fuuaRDawQL iApF3CXDMijnFitB83w7Gj/0/HrreuRaxUlY1teBaEqMoZiRDwi4G2y4aIiGuSs+Mt+S pcBqmmhUbsCEUpEZtVl4LfcCVDXx9laivNCYFiX/zcqaGqdXJIAZ2n1tUfchgKuyWBby n0a8ToKJygGFuOMxJMfJudtPNnjygJVcQiILxDO4JY7ZoFtKveKgOJ6yfknZDM46hUb7 FooztTtgFiTpwE2P2dVtQx/6R8YwkxkrSknKbc2zj8G1G7deWMMwSb3O1Wg6iaUBWzCx 6jBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pq6G2lRN; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Currently we used a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Teach Qualcomm clock controller code about setting up power domains and using them for gdsc control. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/common.c | 37 +++++++++++++++++++++++++++++++------ drivers/clk/qcom/gdsc.c | 5 +++++ 2 files changed, 36 insertions(+), 6 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 60d2a78d1395..43d8f8feeb3c 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "common.h" #include "clk-rcg.h" @@ -224,6 +225,11 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } +static void qcom_cc_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -241,6 +247,18 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (!cc) return -ENOMEM; + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; + } + + ret = devm_add_action_or_reset(dev, qcom_cc_pm_runtime_disable, dev); + if (ret) + goto err; + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -251,7 +269,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_reset_controller_register(dev, &reset->rcdev); if (ret) - return ret; + goto err; if (desc->gdscs && desc->num_gdscs) { scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); @@ -262,11 +280,11 @@ int qcom_cc_really_probe(struct platform_device *pdev, scd->num = desc->num_gdscs; ret = gdsc_register(scd, &reset->rcdev, regmap); if (ret) - return ret; + goto err; ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, scd); if (ret) - return ret; + goto err; } cc->rclks = rclks; @@ -277,7 +295,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, for (i = 0; i < num_clk_hws; i++) { ret = devm_clk_hw_register(dev, clk_hws[i]); if (ret) - return ret; + goto err; } for (i = 0; i < num_clks; i++) { @@ -286,14 +304,21 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_clk_register_regmap(dev, rclks[i]); if (ret) - return ret; + goto err; } ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); if (ret) - return ret; + goto err; + + pm_runtime_put(dev); return 0; + +err: + pm_runtime_put(dev); + + return ret; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 51ed640e527b..9401d01533c8 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -427,6 +427,7 @@ int gdsc_register(struct gdsc_desc *desc, continue; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; + scs[i]->pd.dev.parent = desc->dev; ret = gdsc_init(scs[i]); if (ret) return ret; @@ -439,6 +440,8 @@ int gdsc_register(struct gdsc_desc *desc, continue; if (scs[i]->parent) pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } return of_genpd_add_provider_onecell(dev->of_node, data); @@ -457,6 +460,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } of_genpd_del_provider(dev->of_node); } From patchwork Fri Jul 9 04:31:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAB0CC11F69 for ; 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Thu, 08 Jul 2021 21:31:42 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 5/7] arm64: dts: qcom: sm8250: remove mmcx regulator Date: Fri, 9 Jul 2021 07:31:34 +0300 Message-Id: <20210709043136.533205-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch dispcc and videocc into using MMCX domain directly. Drop the now unused mmcx regulator. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..2a468b85dc09 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -271,13 +271,6 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - mmcx_reg: mmcx-reg { - compatible = "regulator-fixed-domain"; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - regulator-name = "MMCX"; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2362,7 +2355,7 @@ videocc: clock-controller@abf0000 { clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; @@ -2627,7 +2620,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Fri Jul 9 04:31:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6710C07E9B for ; Fri, 9 Jul 2021 04:32:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8FFA56144C for ; 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Thu, 08 Jul 2021 21:31:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 6/7] clk: qcom: dispcc-sm8250: stop using mmcx regulator Date: Fri, 9 Jul 2021 07:31:35 +0300 Message-Id: <20210709043136.533205-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdsc. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index de09cd5c209f..dfbfe64b12f6 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -955,7 +955,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Fri Jul 9 04:31:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471772 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp944893jao; Thu, 8 Jul 2021 21:32:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxNJ0cjZ1oI7x8ESXVRJy07XMHntS4jjT5mKBsWhmW26SlqqL7qkg+M3MHBQODZqlKaIWNa X-Received: by 2002:a05:6638:380b:: with SMTP id i11mr30113764jav.57.1625805148307; Thu, 08 Jul 2021 21:32:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625805148; cv=none; d=google.com; s=arc-20160816; b=EK1CEwdniIYcCmtCcn+lVa1O2WxteTuaKyBz9w3bJnWIvoxUf+YR6K4z8UwwjxiEHM Pmr2+63sSA2GD4C9mNLKSUoi80MhsQtD3O7MG1IuuLBX0wuf20ATGRXqYb7skHIUBNjg j11mXgYGFo7/RsCD6p9G2W5+p4QLQpFvghjX0XWWMZGaZb2q51uf2rsgoG1BPFMlaBBW RzPxfY4KPwvvSTgmcmEN9shjdhHMh4XFzGHrXmTD3dFE91DW75SN5MCGDmBeK/8xiyuw iVfOGj7UAETc7/PpJfbzx7hXBA0+wEbbBIMLNbazMocLfqYkZlbmJkVffhAUuSyX6LvC k4wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OW6r9Ztak14Z94NLN85hpavnPWferFff+9qy6SUKk4g=; b=YQiBv9mkY4Tl2Ag6kiltRhpKTdGWwt8D7OXueWQu6OyJN17iKlqnZmclE3HrL4bSQY Goo+dmHvhXbrLNMXPRZjNzWQW6TlfMkH8f76frRAF/6L0u+hEfyCtLjDT3LVIgZlsfIm QE/PShqD/r+lXKDyfNcKe6uqD/hU0u2AAfexylBLG2kSotZ/m2sBM4f44YzwAPaBgI3V 28bTVzVWuYtBQl8NwnCMSO7JqjXpDYQ+4klgzIDzh/0MXNpTH3kFAA1Kas8dWb+qNAps r0vl4AQiaExIyRM4Sf08XDK2L6PL4L2EAgm/CoiP/qPtZz21+2111nAG9YeQa5Il7nW3 z2Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UvGi1B+e; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/videocc-sm8250.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 7b435a1c2c4b..eedef85d90e5 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -276,7 +276,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -286,7 +285,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -296,7 +294,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -306,7 +303,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = {