From patchwork Fri Jul 9 04:31:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471768 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp944811jao; Thu, 8 Jul 2021 21:32:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjD4lND+2kg2mX9aPQeC9WXRaQpY1f4KRme7xIlFtSCVyq6XoNk7w2Rb95XjwPtUjLm16f X-Received: by 2002:a02:6382:: with SMTP id j124mr30348687jac.72.1625805138167; Thu, 08 Jul 2021 21:32:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625805138; cv=none; d=google.com; s=arc-20160816; b=A1rKCeblExoEbwXf9Woc7rYw+g94klLPRB7SFLJPzsYU/uK12sz8Cv5e/ow58+mjym kezVfbvPsEjyQt91mGgU1Oci6RmMOlrowLQzWLO0ugNVWZhqqSDm1V/JAP5hy9gq3oEu KUX3Pvq1+NS7L6AEqRKleICweUOsLF1k82EJgzQVG4NcAEmbpW8MZBwkLB3oysCg9cQW YBsiu3QkSvCWU67+8rW+3pMqLEf8e61U3mWxGKb2oNjgHp9kv0D+M0j5YF0WlJqBM3eG iva1ZG/AgYOoaedmRnC6CiKhV8DR1mCMpAokbj/oii2BH7bWQgkohChf+ADgqc5DE9x5 jHEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=Qu4yaWdXuGtoZEWRYlHjK6rRxBnyjsJw3yIjQ9fb5Uzlq0fqsU0q8dKr50MhUkTpXU TyaUF3DgJdyynDrXxyhT7oBXtMiazhH68w+WtIo85OR77RImxNPW/TJqo1LqNX6Yu4gl sYztvp37JuYjbid/wjVCO+ub2OCFsLcUNggMv3inD1US+4eWGN1NM6lIFdla1SexwRys 9sK3s0C+MCXJqQwlZ3PdkDestkTm4JVJkGnvDqTohg+DFRvtTwSOnHJu5H8s5aAoFfbR HjSRaDRNfENgLdMm7Nzu4N4V+ewq2ikOBrWIn8U0hv64m/W4zVZWVgMrlLl7GM0Smv3h hR8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sParuvrS; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b20si5191506jat.60.2021.07.08.21.32.18; Thu, 08 Jul 2021 21:32:18 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sParuvrS; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231279AbhGIEeb (ORCPT + 7 others); Fri, 9 Jul 2021 00:34:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229765AbhGIEeZ (ORCPT ); Fri, 9 Jul 2021 00:34:25 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 001D8C061764 for ; Thu, 8 Jul 2021 21:31:40 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id z9so5961339ljm.2 for ; Thu, 08 Jul 2021 21:31:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=sParuvrSW3yxOcQImsE/pSCTQsOWei74sYLKne+13T8AGuPpPTPGmK5tqJ4t/huvC5 JqLDLskOrOsSFTCiWSPOnOYtGMF4nepGfge0N7s3Hc2mQCV92Y5FnUvfk0avW1wP+c/O zzNNICJ5cPLJvz5M4slRZs6w+pZrJ2ssyQW6qzU7Zf7w27OyOE2+MuwolUJ6dxR/tcoq vY/bsMKFBI5LVvmLS9I2oRBAiazKiG3T7ow9wMDWwo8URO7kgblsJCAbCSFsR5eFXJjI OyANlUpiTCdH4cosnKXw09vr+OuDE0MVDu62o3ozIoT9t05f2bPckUVb+Wn8gGPc1hu4 5xMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=kXuQMPq1ODoKOg3fSa9Zp04qRG5HM6uY924WoR39ThmbZTZg1l+b0LWcyVJ8A1Potk INmxLvCgIWN4PLWKklIxzuoRgS/ZJ3HJP759AMGGJn460eJsSkE5t50STevQMk05SBF+ L34fFm7LK4o/TFqtC8TyF2m/cAFV0N7bfr2HQzei3QCSSN6SfBXMpA/ShEvFBFbBit6W yJLLAFqiwADl11p/ufLwQyV+UOyXoaQThwrpxu6RwG0OqoxcgV17OLL3hGjdj/swZzZc DEpKRCFlsMGOJC3KxsG9trybh8R40uPWZvARUIpY5JMlDiCpNj/Gk6p0sI1sQfAgEfDK fgWg== X-Gm-Message-State: AOAM530MU4ht8tOJe6l9prCNv2kuDg/5Ojyh8IZAPNy4PALnWuNVFYky poPDq7cZXw3awDAaY5SdzFauoA== X-Received: by 2002:a2e:a54a:: with SMTP id e10mr27331977ljn.120.1625805099320; Thu, 08 Jul 2021 21:31:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 1/7] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Fri, 9 Jul 2021 07:31:30 +0300 Message-Id: <20210709043136.533205-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..d5c4fed56b6e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -55,6 +55,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -69,6 +74,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -89,5 +95,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... 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For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..db4ada6acf27 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -61,6 +66,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -69,5 +75,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... From patchwork Fri Jul 9 04:31:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92177C07E9E for ; Fri, 9 Jul 2021 04:31:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C7C561467 for ; Fri, 9 Jul 2021 04:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229618AbhGIEea (ORCPT ); Fri, 9 Jul 2021 00:34:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229937AbhGIEe0 (ORCPT ); Fri, 9 Jul 2021 00:34:26 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C40A6C061760 for ; Thu, 8 Jul 2021 21:31:42 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id u18so10926361lfl.2 for ; Thu, 08 Jul 2021 21:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wyfQ/AaQKOiokX60V253WPiUw+AOPKvuwfW4bIOFEAY=; b=AJP+QloJmqmzs+VJU10kG5J/rkfgBe3Tio+qlCxt/ubsoyKjmKRrEWZIMKq+ccRYWl ojA1gund8aY9+Q+hLyNNhB/XeZGWHRnT/sD+Pa4wIyWeed5z6MQ4xn4N9gr3DR7Yir5V JcBzKcGTVVy5YhnAWqDsch8bhfwqDN6ZJLInvUtRr+fxkBI4ngrofr5A9ceIOn8IjXc0 itswHZhQLN/eIAqeW99pbsrQWw0nfloAfJMNA6uzpWqVEOGCwz4ScuLhIrTj8GmEOeZx riMWmZ1I7Dld/D91a57dMk+nmG9JCW8aBvdaB2ut4RYYyxRajF3smG6HAYMs8sYza1kx 0uJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wyfQ/AaQKOiokX60V253WPiUw+AOPKvuwfW4bIOFEAY=; b=Z7jUnO5pqhi5UQoWXwIbNeIwl/sa2lAfONJLPorzb/0o5/UQc8JLGLmjLl9o9ab7Of eS5wjbsCkpgMEeOxMW8AdnXmvvLsghHewbOawGqEz7QOLoABnWpuvwMpwIDWPLjRFwxZ vgdtC9MOub+l0fHMkXiJAf1jHb8hr9sNaKG/mEcnN/aIv2MNxXKKGtXm/zAwVD3cikgM +Co+O2MpoLeNdR4IvMadLOxzDcPXE4WjTp7VtniCXjn95MgLADp6mOj3nnx9udHmBsUy rz4/tXki1Xd7HM8gEaQs39tZUpL7u6mFaiSdFvD0n8FgppMBgBV//hrx0Obuo6/Cl7i/ 21qg== X-Gm-Message-State: AOAM531qFWua+E1dIpdlWo5zopJJcWzCXXPcWhY+NbO8Dw07QGq9szNk 6ngJ5vFW0Jz1iUkPxJB2t5zFyw== X-Google-Smtp-Source: ABdhPJxwjk6BNwns0NH2xy/EkGCWutIfDZLODxwpg2CXf5/Z2PIoir1JE6Sv1yjRfPjTh/NpraIc4w== X-Received: by 2002:a19:e04a:: with SMTP id g10mr27341156lfj.561.1625805101114; Thu, 08 Jul 2021 21:31:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 3/7] PM: domains: Add support for runtime PM Date: Fri, 9 Jul 2021 07:31:32 +0300 Message-Id: <20210709043136.533205-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Registers for some genpds can be located in the SoC area, powered up by another power domain. To enabled access to those registers, respective domain should be turned on. This patch adds basic infrastructure to the genpd code to allow implementing drivers for such genpd. PM domain can provide the parent device through the genpd->dev.parent pointer. If its provided at the pm_genpd_init() call time and if it is pm-enabled, genpd power_on and power_off operations will call pm_runtime_get_sync() before powering up the domain and pm_runtime_put_sync() after powering it down. Signed-off-by: Dmitry Baryshkov --- drivers/base/power/domain.c | 33 +++++++++++++++++++++++++++++++++ include/linux/pm_domain.h | 6 ++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index e5d97174c254..7d49531c9731 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -482,6 +482,30 @@ void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next) } EXPORT_SYMBOL_GPL(dev_pm_genpd_set_next_wakeup); +static int _genpd_pm_runtime_get(struct generic_pm_domain *genpd) +{ + int ret; + + if (!(genpd->flags & _GENPD_FLAG_RPM_ENABLED)) + return 0; + + ret = pm_runtime_get_sync(genpd->dev.parent); + if (ret < 0) { + pm_runtime_put_noidle(genpd->dev.parent); + return ret; + } + + return 0; +} + +static void _genpd_pm_runtime_put(struct generic_pm_domain *genpd) +{ + if (!(genpd->flags & _GENPD_FLAG_RPM_ENABLED)) + return; + + pm_runtime_put_sync(genpd->dev.parent); +} + static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) { unsigned int state_idx = genpd->state_idx; @@ -497,6 +521,10 @@ static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) if (ret) return ret; + ret = _genpd_pm_runtime_get(genpd); + if (ret) + return ret; + if (!genpd->power_on) goto out; @@ -526,6 +554,7 @@ static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) raw_notifier_call_chain(&genpd->power_notifiers, GENPD_NOTIFY_ON, NULL); return 0; err: + _genpd_pm_runtime_put(genpd); raw_notifier_call_chain(&genpd->power_notifiers, GENPD_NOTIFY_OFF, NULL); return ret; @@ -572,6 +601,7 @@ static int _genpd_power_off(struct generic_pm_domain *genpd, bool timed) genpd->name, "off", elapsed_ns); out: + _genpd_pm_runtime_put(genpd); raw_notifier_call_chain(&genpd->power_notifiers, GENPD_NOTIFY_OFF, NULL); return 0; @@ -1986,6 +2016,9 @@ int pm_genpd_init(struct generic_pm_domain *genpd, genpd->domain.ops.complete = genpd_complete; genpd->domain.start = genpd_dev_pm_start; + if (genpd->dev.parent && pm_runtime_enabled(genpd->dev.parent)) + genpd->flags |= _GENPD_FLAG_RPM_ENABLED; + if (genpd->flags & GENPD_FLAG_PM_CLK) { genpd->dev_ops.stop = pm_clk_suspend; genpd->dev_ops.start = pm_clk_resume; diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 21a0577305ef..e86cd7cfc9ec 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -60,6 +60,10 @@ * GENPD_FLAG_MIN_RESIDENCY: Enable the genpd governor to consider its * components' next wakeup when determining the * optimal idle state. + * + * _GENPD_FLAG_RPM_ENABLED: Use genpd's parent dev for runtime power + * management. There is no need to set this flag, + * it will be detected automatically. */ #define GENPD_FLAG_PM_CLK (1U << 0) #define GENPD_FLAG_IRQ_SAFE (1U << 1) @@ -69,6 +73,8 @@ #define GENPD_FLAG_RPM_ALWAYS_ON (1U << 5) #define GENPD_FLAG_MIN_RESIDENCY (1U << 6) +#define _GENPD_FLAG_RPM_ENABLED (1U << 31) + enum gpd_status { GENPD_STATE_ON = 0, /* PM domain is on */ GENPD_STATE_OFF, /* PM domain is off */ From patchwork Fri Jul 9 04:31:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9612EC07E9E for ; Fri, 9 Jul 2021 04:31:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 835C86144C for ; Fri, 9 Jul 2021 04:31:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231234AbhGIEee (ORCPT ); Fri, 9 Jul 2021 00:34:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231226AbhGIEe2 (ORCPT ); Fri, 9 Jul 2021 00:34:28 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D316C061574 for ; Thu, 8 Jul 2021 21:31:44 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id c28so20135287lfp.11 for ; Thu, 08 Jul 2021 21:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=89M3kJH8Z+ezz3X5xX4Jb+p6yEZY6o3ZbKwB3aRtLuw=; b=Pq6G2lRNhxw2vUhHwwMP5b3OyWgTa/hegNC+tgzuvNtJVP2KQi1yzBsVU/T9DkgCm9 2lzKbNs2lCbjDaCqwJYxG3Lug+E/uCOEzEX3+uAj8maq3ApVt+FkTix5La9N0KDdV+n4 rOxQHIVNw2hdhCLEN03XQtZb7ra7c3BNNhZlZwUhy69u8mwrwRtkdeW5wlp6bB+79FpC SQLmjZNW8ueVUTAwdDOeWMOEN6M6qt2rG86Sz7hhxRsjEsqMsDFDYiR4+57Iep8Xzsg5 nxJlBAqu1l6w7vfo6ilFZPZFYcbe/W5WrNYliWhOkKgjmTnPNz1U9AH9L48oaAOHIHhR aGGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=89M3kJH8Z+ezz3X5xX4Jb+p6yEZY6o3ZbKwB3aRtLuw=; b=NhgXRGPOQz+jIt6moh7L8k/HqZLM3XVC8YqrcXBZCw8hLxbvdcMl+dS1pU7oEz6ni3 ZzM1qGdEc8tBeqWa5MN5dSMPmwPcdRlqX1velr+Ok67YWa6ypWXmcjkwIYATLF0bi7st Ilb2XoNDW/0yTFnGqHa4dof7ih6c+1CZtTt19T4+uaBx9DBu2uURbNTvZAJBhLvmkGIQ yOEICY0gy80C0PKuBf3YUFrcK3mJnQMs9Yhtt5P1Wv/0YxslJy/rzh+eeb6LUKufBHQP M7wAdJubfyMhDGtXdW6KBEInsCNPVqShp217eSeTviNPtWb952oeMsDWDNpJ+n7hJiwH 2lBw== X-Gm-Message-State: AOAM533bFqh54nZ5pw5DaedZPnXRFWmaiLbwAPTDZ+0zyGDhfaVNATRT TUhhZmEg/I2SUZE6+Y7s/yjmCQ== X-Google-Smtp-Source: ABdhPJxjr4KOVW/vv2+NJuenHFEE/zVGc85kBiQOrraHkR6yx60M/RGbz/Un+Am7IUgnNnrrl+IC6g== X-Received: by 2002:ac2:4d37:: with SMTP id h23mr22176135lfk.177.1625805102035; Thu, 08 Jul 2021 21:31:42 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:41 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 4/7] clk: qcom: gdsc: enable optional power domain support Date: Fri, 9 Jul 2021 07:31:33 +0300 Message-Id: <20210709043136.533205-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we used a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Teach Qualcomm clock controller code about setting up power domains and using them for gdsc control. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/common.c | 37 +++++++++++++++++++++++++++++++------ drivers/clk/qcom/gdsc.c | 5 +++++ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 60d2a78d1395..43d8f8feeb3c 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "common.h" #include "clk-rcg.h" @@ -224,6 +225,11 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } +static void qcom_cc_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -241,6 +247,18 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (!cc) return -ENOMEM; + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; + } + + ret = devm_add_action_or_reset(dev, qcom_cc_pm_runtime_disable, dev); + if (ret) + goto err; + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -251,7 +269,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_reset_controller_register(dev, &reset->rcdev); if (ret) - return ret; + goto err; if (desc->gdscs && desc->num_gdscs) { scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); @@ -262,11 +280,11 @@ int qcom_cc_really_probe(struct platform_device *pdev, scd->num = desc->num_gdscs; ret = gdsc_register(scd, &reset->rcdev, regmap); if (ret) - return ret; + goto err; ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, scd); if (ret) - return ret; + goto err; } cc->rclks = rclks; @@ -277,7 +295,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, for (i = 0; i < num_clk_hws; i++) { ret = devm_clk_hw_register(dev, clk_hws[i]); if (ret) - return ret; + goto err; } for (i = 0; i < num_clks; i++) { @@ -286,14 +304,21 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_clk_register_regmap(dev, rclks[i]); if (ret) - return ret; + goto err; } ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); if (ret) - return ret; + goto err; + + pm_runtime_put(dev); return 0; + +err: + pm_runtime_put(dev); + + return ret; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 51ed640e527b..9401d01533c8 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -427,6 +427,7 @@ int gdsc_register(struct gdsc_desc *desc, continue; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; + scs[i]->pd.dev.parent = desc->dev; ret = gdsc_init(scs[i]); if (ret) return ret; @@ -439,6 +440,8 @@ int gdsc_register(struct gdsc_desc *desc, continue; if (scs[i]->parent) pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } return of_genpd_add_provider_onecell(dev->of_node, data); @@ -457,6 +460,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } of_genpd_del_provider(dev->of_node); } From patchwork Fri Jul 9 04:31:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471769 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp944816jao; Thu, 8 Jul 2021 21:32:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzhYkuR4cHZDSaAp/toywCoTHxjW6E+rjXcL9WVxlyb56/++9P0Fuir52XX5R3BUXPoLPNb X-Received: by 2002:a92:3009:: with SMTP id x9mr24198065ile.49.1625805138880; Thu, 08 Jul 2021 21:32:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625805138; cv=none; d=google.com; s=arc-20160816; b=UFN7iA4rR28ZKqvLPyBMfRun3l+IAklfwyDr6KBs/+pBywXDC6dV2zUWewJAhI2dko Obt09TOnke+19vy+PHsqzxV5cK/jHQ9ShcSgj7jxKe8rCOfdcFo4TdVjMwvqM84HmJ3A 1eTmtBQmVB4YdxUG733SHxiZ0s/wB9gWRlB9llIvRzvkBscWNLc9OnpXA/Q2GweLlG48 ShlB5irhZk7IMp2CsjISQztISIuxlldCqKEsKWxFpQyAuM/WiATHqL7BXPFxOL6XlVXy fdGcKf2wshRGxJj/gmj7l9Ri+fFI36t16HM9ctZRiVseC909HMjD6sT9DUN6hQE+Qwdt i3zQ== ARC-Message-Signature: i=1; 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Drop the now unused mmcx regulator. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..2a468b85dc09 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -271,13 +271,6 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - mmcx_reg: mmcx-reg { - compatible = "regulator-fixed-domain"; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - regulator-name = "MMCX"; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2362,7 +2355,7 @@ videocc: clock-controller@abf0000 { clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; @@ -2627,7 +2620,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Fri Jul 9 04:31:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471771 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp944874jao; Thu, 8 Jul 2021 21:32:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzyIQ1UYsTpvwMcFiud+8wF1Ekoldgkzv+hiLVkjkTewkDXQGk74jsPPcT80Razjubg7P8Z X-Received: by 2002:a5e:8612:: with SMTP id z18mr10243148ioj.38.1625805146510; Thu, 08 Jul 2021 21:32:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625805146; cv=none; d=google.com; s=arc-20160816; b=LWakKj9nTHoKWLlSvoRJevQMbA6nzsdKTcMQpEstfwFsU5lBRcdClIypewJatIPMfx WbNody7JcNoKo8vLmB3kmiDMZpuYw3uQC6tOmCQfWVT0HUT3mqndxx6Rex99NkMD8m6/ Y7BlmpdfzIqQrMPZWCOZueY7qfiJpwjJeW471U2Lc5wfYhyl5UrsycSb4TvaK7NYKxPl 63qr/kW4koqOUKpKLiUG4Q4t6N5bxEXO9QEiuvr3F3GzXpN9PDqHA0IJV5Slk2rU6UNk tZ4fnthuqknk2TDRomc0SYmg5aDi+VSNibhrX31pkigLtSki55IXyixxk/sFQBnTuexT zc6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f0ldkE5j34OXHAqh3I/xyyl0k1n40wAos/+0qzuAEic=; b=xVjXZUpCb/iJ+xICx8OExUtJP+qWmYkd1xJR17VBmOseneIKw3c6UFtZ5ivKeQ6MRh uXd58w/TV6DQdw64HWyYPj9u5rK/HHLIFOEfvjQZMScwKZcmi8ZhRX/R1Voop11GXEZO VVQe5pWCA9Ea62f4oaI+UP0j7kR6DCii6XREQzsRl/EXrxq/ioXPoZ3675oYuGsIwjuX BoDrE1/rGujTKcSYKtKEUf7OFCOCh9DDC6+57klTWTRcJdJwELsZIqo3ZbxwNODkdFP6 UITBtEeUx30W6xrJ0/6Q6l/bJVA5W3OJnPjAfbYINeoK8OxONTn05sTMRjvKTrZmXiie lw5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evja71V+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b20si5191506jat.60.2021.07.08.21.32.26; Thu, 08 Jul 2021 21:32:26 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=evja71V+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230506AbhGIEef (ORCPT + 7 others); Fri, 9 Jul 2021 00:34:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231246AbhGIEe3 (ORCPT ); Fri, 9 Jul 2021 00:34:29 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 931F8C0613DB for ; Thu, 8 Jul 2021 21:31:45 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id p1so20583339lfr.12 for ; Thu, 08 Jul 2021 21:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f0ldkE5j34OXHAqh3I/xyyl0k1n40wAos/+0qzuAEic=; b=evja71V+pcmqd6EmSv+Kg5ZvqKs56bvDZjR9SCjtxVgotJ6idANj1ATscxqed8yhrH BqZTpJzJV8b2/mRGTTUw/C87V0Ub/9ljyKAib/5HmOck6HhDX9xbtcYfIDoh6B/YRcFO FvHhKQEyAUsy4q66QaZtOlUhXFfULRgLI0Yh1LDLF19WJqfLFoD0DGuokdd5v0YC1Yw6 nACS2JKBe1KaPMWI2WkDogCGf5h7LS/kMaTVUidb/nitQziDHKrtzOHhImfuus0axEJE ViuhFR3ovCswl+VA/6QiXst+hy99HD96ktL4Qv7YVQa/qw+Dof8NNthKI1nTf9NqFV3+ XJTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f0ldkE5j34OXHAqh3I/xyyl0k1n40wAos/+0qzuAEic=; b=e94oYo3yUSrIMb3+pfEoV59fGHXGqa+Nxmrs1TSylnhh7yQ+uAtZWmvOH2+tkAyMgO Fz5LmdZJvGExB9vJQapyaaETZDjxTDGSHgJdcSSMXW7SSgA3CJy14zkv3FGS+atyC+LT dyDx+MPoN7m8R2H36H59Pb1ngjFMpsZEem6RfavT1iczo7BJMOTmHBAeP/qOGRy/HXKs QlYZ+kNZfr/tfJKwZ/TGsM1xKMSmrcLI59b9rPBNWIWgz88eduNKkUR2AA0/6U1XpnmC +BUyP2tJxCWwXV8KClb9kRjist6pUMAfGPmidG6/zSi9xro1Q0zwUTucDQjEuIJsmzJk aV+A== X-Gm-Message-State: AOAM531wVJjPVjsPy2fVIe0iPmTy98Bjq9IjkCCv6G0+UOz7SKXJYLLB ww9noUOB4TL8+qkT1SkDzRVJ5g== X-Received: by 2002:a19:408c:: with SMTP id n134mr26254126lfa.329.1625805103973; Thu, 08 Jul 2021 21:31:43 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 6/7] clk: qcom: dispcc-sm8250: stop using mmcx regulator Date: Fri, 9 Jul 2021 07:31:35 +0300 Message-Id: <20210709043136.533205-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdsc. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) -- 2.30.2 diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index de09cd5c209f..dfbfe64b12f6 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -955,7 +955,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Fri Jul 9 04:31:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EC02C07E99 for ; Fri, 9 Jul 2021 04:32:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B2D56144A for ; Fri, 9 Jul 2021 04:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231237AbhGIEeh (ORCPT ); Fri, 9 Jul 2021 00:34:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231254AbhGIEe3 (ORCPT ); Fri, 9 Jul 2021 00:34:29 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81614C061760 for ; Thu, 8 Jul 2021 21:31:46 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id b40so5905692ljf.12 for ; Thu, 08 Jul 2021 21:31:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OW6r9Ztak14Z94NLN85hpavnPWferFff+9qy6SUKk4g=; b=UvGi1B+es3fCaDxmJpGeewLmLB8C2VxxdjqqEEtrzFv0O0YZAolKlF756ouyrJpI2/ fY58oGEn7/X9Y0nAPmv0ScmYyuXiAwRTIXpbMMSsy3KmpFYPdYDg1hs/Xmv6cEngQ00W gDrrrmODv6Sg1V7A1keQiN0XEBDXoTVvhSdXjWAvgBpuEOwDF2XdumPevBMFw29rfxHS r3xkD6To+3liLwf4z+QeiiT/BX8mVtxJyeZ2BdpS6cOgLwozikH84JZ1KCpHwGlc+HkM E5RZgZz7GZHGYnGfg8jPZwzKoepOd9ankKqCplBpO6fTlLs7AzIrDIjbJJsEY7xQVP86 SHBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OW6r9Ztak14Z94NLN85hpavnPWferFff+9qy6SUKk4g=; b=Aap2P1SBJ0PFIys7oDvQ/oBrLXs0W1Hyi0sUdDMp92b9MLV2WatFeGJYlBEWHXCW/W lH/uEc4t9JSbWbne9GvL5pZlnDc6tRJcJ5rc9oJBnqDqQyppwgWgjp81VnAJD4EmxNyx E96uUceQ3C5jDiG3tRUeu3JhzcZg60RkjnPu/cmw9ZSZ95wSsHy2R0FtmAhgXWPcfbs7 o6DRCUcQutkfsUblinxke+mZy5YuQCLEQFOdp+7lEwrebjQ7SC+RHTdKMPkwaMGUocBD YHYlmoquILvQRTQMCT1XKZLPtw4u/QE1yI5VyIfph2ER627weAXN8s2kzu3iTh0G4/kc HmOw== X-Gm-Message-State: AOAM532s7+LwCiN2yHxdi4rSWtJQop+EN54cJRwQZMJSuvkh6WKVraoh fL//ZW9c/Lvjg4/HQEIEdt4GNA== X-Google-Smtp-Source: ABdhPJyY7ngGsTRiOotvZgAIDUFql0+KdrxnztkmsKdBzpgq9oLFTrwe/YXta5EHMcKPW9w4HgfmDA== X-Received: by 2002:a2e:9b46:: with SMTP id o6mr21455694ljj.501.1625805104909; Thu, 08 Jul 2021 21:31:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h1sm13028lft.174.2021.07.08.21.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 21:31:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 7/7] clk: qcom: videocc-sm8250: stop using mmcx regulator Date: Fri, 9 Jul 2021 07:31:36 +0300 Message-Id: <20210709043136.533205-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> References: <20210709043136.533205-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdscs. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/videocc-sm8250.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 7b435a1c2c4b..eedef85d90e5 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -276,7 +276,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -286,7 +285,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -296,7 +294,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -306,7 +303,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = {