From patchwork Thu Jul 8 12:06:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 471608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0113C11F6E for ; Thu, 8 Jul 2021 12:07:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 87B13614A5 for ; Thu, 8 Jul 2021 12:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbhGHMJq (ORCPT ); Thu, 8 Jul 2021 08:09:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231773AbhGHMJp (ORCPT ); Thu, 8 Jul 2021 08:09:45 -0400 Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FB3DC061766 for ; Thu, 8 Jul 2021 05:07:02 -0700 (PDT) Received: by mail-qt1-x834.google.com with SMTP id z12so4629994qtj.3 for ; Thu, 08 Jul 2021 05:07:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rZoZEqyfgIdTo8A7XW1CRS+nO4NmaGJyQkY5P5vIXU0=; b=mkU9sDTGZHmmBoAwf0kVKy6TGoZrKU+zFlMb8EdmHDslxRaS/5a2VUHjfRFdmPvqX/ uqaxN3kzlMwZ10UgEyUhf1q3xKvK6lZAYs959m/HlERaY7J+0gWmscao+l+vgI+HB8c7 cAfHLMGO0OSFWaosSFaktckHVZXZdrlYbIq4bepTyffFCas2qxWcOm5mWWcslbROKXZm lIWiROvDwiiOdC+BXtWc5HK0D/41pkcKVXipK69q3oEM8iZZbZRD26J82dxCKF0HXLCB sUaM+QlldnxDCMnV/g3dv/XnPbFRHJLESCM/66lMG1Fbcdl0fjNEaIxJPaILObcWXFT1 kWzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rZoZEqyfgIdTo8A7XW1CRS+nO4NmaGJyQkY5P5vIXU0=; b=Z/cpdf/rFv7KqnQncdGfi3HryZawSWejsow1ZE2baqavOSzmRvOtRuNrz7ckPsiKIU R0zYe9ih1kXa7H8RityxaRnKGzSpOiHBjtOHgF30w3ax44BXgPe5V1qVpl7tBfPAZaIf TIxryAc+Zqwh14grwIeWUEaqBWrkB+N/RCwL/yuuhMGksDnuzpUPNL16pMVvGtGW17ZI 406U3g3GsUIH9FcluRGwn2Pu8BPgHuzTcuBBWVno7ypJgJnCOi5fSuqfAI1EolahSm+S Jj6+xdL/vnIlDhkAgTyWKkEJWM0MIv/kbYvi0tqkW9Krgmdcj1yCvHpg3PBvqr0iVzId Tvwg== X-Gm-Message-State: AOAM531ioc4sOmWAAWPDNWosCtsw1+VUkv1e7cLD06kSSs6RE48enEnh AmjxFgGu6xb5GaP1Nwn9Y+38iw== X-Google-Smtp-Source: ABdhPJxsR/qIIaFhjYYt7Bo5zG7tTqBU9+dBdoFzrvbjWiiyTWSNExtbid9Y1s7Q0NmuExaEXSEA2g== X-Received: by 2002:ac8:6716:: with SMTP id e22mr10392070qtp.58.1625746021705; Thu, 08 Jul 2021 05:07:01 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id i2sm912541qko.43.2021.07.08.05.07.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 05:07:01 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v3 4/6] arm64: boot: dts: qcom: sdm45: Add support for LMh node Date: Thu, 8 Jul 2021 08:06:54 -0400 Message-Id: <20210708120656.663851-5-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708120656.663851-1-thara.gopinath@linaro.org> References: <20210708120656.663851-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Signed-off-by: Thara Gopinath Reviewed-by: Bjorn Andersson --- v2->v3: - Changed the LMh low and high trip to 94500 and 95000 mC from 74500 and 75000 mC. This was a bug that got introduced in v2. v1->v2: - Dropped dt property qcom,support-lmh as per Bjorn's review comments. - Changed lmh compatible from generic to platform specific. - Introduced properties specifying arm, low and high temp thresholds for LMh as per Daniel's suggestion. arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d..4da6b8f3dd7b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3646,6 +3646,30 @@ swm: swm@c85 { }; }; + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x4>; + qcom,lmh-temperature-arm = <65000>; + qcom,lmh-temperature-low = <94500>; + qcom,lmh-temperature-high = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x0>; + qcom,lmh-temperature-arm = <65000>; + qcom,lmh-temperature-low = <94500>; + qcom,lmh-temperature-high = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + sound: sound { }; @@ -4911,6 +4935,8 @@ cpufreq_hw: cpufreq@17d43000 { reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; From patchwork Thu Jul 8 12:06:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 471221 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp215468jao; Thu, 8 Jul 2021 05:07:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygMJRIj6PLFTFK2EcXO/fVE+qQhyn/lK4KPii7RgLxhp8nd4sdpkrvIaApTq4Rb7Fjhh5B X-Received: by 2002:a5d:96cb:: with SMTP id r11mr9037339iol.53.1625746030960; Thu, 08 Jul 2021 05:07:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625746030; cv=none; d=google.com; s=arc-20160816; b=0zmTvJaiEkAErzDCQJEVfKAtCQYhS8tPrRIIau5NsfyqltSbB5KXD0EM4UCKHEBBOc DA92qImId5Jb+oOukML1015bCF7F5r7rqePDiiBWxlELJi+JbOf65SeC6kYYNsz/v9hr V9OCx3REc6k24lRYsUMpGF3IAyvah7ILVtmMGXj59IlCA7aJbpS52ROCTBkdDCsP9hZy nnH6EScGdQzgrijkVtue5FPspNaORC9AlV5hShijbfC51JCCPTof4Hno1Gah32xCCt1i BG0ls4w/uxToMmcPgrbuC7we5IpuqRO36ZnkpzqBiIT8zfc8CneO68ZNc89cTOgKnl1x EpOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2T81iWIL1908Vl2QtcUP1A5GcmnGaJTNEI2g+BHElzU=; b=GDa9OxjTwm3HVYMn2E/AzSPXkKSVUmAW5gCdU0RHpqyGc8Gl0qMxAtQ/XY+2w81FQJ 6EZn5EXn9yaUlGErLTlRC4+y/y6WXZ80qtKCfOrBAAMexw10BkpT90tl4AosKQc4omE9 M+1qkJhr1s5CMN9RYE/PmndC2b8NQzy1f5YpG+WsmdKI5S2ymHuXaoNpA5bfod9mf5wA J9mB78cmJWYAhTXHUSinlakfx3QiGO6AriFup+tf2L02Ll/rZkBKtzalQEawcGFSL7Yj 8CHRshhFxdDvLt6JuhzYKOCb9Ac4gTAqxBHijktBqIbz/RP87af3RHA+6wm2u/xm7G/9 NgWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u11BqaH8; spf=pass (google.com: domain of linux-pm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[71.163.245.5]) by smtp.googlemail.com with ESMTPSA id i2sm912541qko.43.2021.07.08.05.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 05:07:02 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v3 5/6] arm64: boot: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones Date: Thu, 8 Jul 2021 08:06:55 -0400 Message-Id: <20210708120656.663851-6-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708120656.663851-1-thara.gopinath@linaro.org> References: <20210708120656.663851-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Now that Limits h/w is enabled to monitor thermal events around cpus and throttle the cpu frequencies, remove cpufreq cooling device for the CPU thermal zones which does software throttling of cpu frequencies. Signed-off-by: Thara Gopinath --- v2->v3: - Improved the subject header and descrption to better reflect the patch as per Matthias's review comments. v1->v2: Removing only cooling maps for cpu specific thermal zones keeping the trip point definitions intact as per Daniel's suggestion. This is to ensure that thermal zone temparature and trip violation information is available to any userspace daemon monitoring these zones. arch/arm64/boot/dts/qcom/sdm845.dtsi | 136 --------------------------- 1 file changed, 136 deletions(-) -- 2.25.1 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 4da6b8f3dd7b..6185fff8859a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4994,23 +4994,6 @@ cpu0_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu1-thermal { @@ -5038,23 +5021,6 @@ cpu1_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu2-thermal { @@ -5082,23 +5048,6 @@ cpu2_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu3-thermal { @@ -5126,23 +5075,6 @@ cpu3_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu4-thermal { @@ -5170,23 +5102,6 @@ cpu4_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu5-thermal { @@ -5214,23 +5129,6 @@ cpu5_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu6-thermal { @@ -5258,23 +5156,6 @@ cpu6_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu7-thermal { @@ -5302,23 +5183,6 @@ cpu7_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; aoss0-thermal { From patchwork Thu Jul 8 12:06:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 471222 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp215487jao; Thu, 8 Jul 2021 05:07:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTzw3ocizcErL2X3jT6zmU1siGotgUe/DYnta7xSjtMTpoAQtPMk75sGFqRhQdN7BH0gj7 X-Received: by 2002:a92:c56d:: with SMTP id b13mr21819330ilj.169.1625746032070; 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[71.163.245.5]) by smtp.googlemail.com with ESMTPSA id i2sm912541qko.43.2021.07.08.05.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 05:07:03 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v3 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh Date: Thu, 8 Jul 2021 08:06:56 -0400 Message-Id: <20210708120656.663851-7-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708120656.663851-1-thara.gopinath@linaro.org> References: <20210708120656.663851-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add dt binding documentation to describe Qualcomm Limits Management Hardware node. Signed-off-by: Thara Gopinath --- .../devicetree/bindings/thermal/qcom-lmh.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml -- 2.25.1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml new file mode 100644 index 000000000000..7f62bd3d543d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Limits Management Hardware(LMh) + +maintainers: + - Thara Gopinath + +description: + Limits Management Hardware(LMh) is a hardware infrastructure on some + Qualcomm SoCs that can enforce temperature and current limits as + programmed by software for certain IPs like CPU. + +properties: + compatible: + enum: + - qcom,sdm845-lmh + + reg: + items: + - description: core registers + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + qcom,lmh-cpu-id: + description: + CPU id of the first cpu in the LMh cluster + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,lmh-temperature-arm: + description: + An integer expressing temperature threshold in millicelsius at which + the LMh thermal FSM is engaged. + $ref: /schemas/types.yaml#/definitions/int32 + + qcom,lmh-temperature-low: + description: + An integer expressing temperature threshold in millicelsius at which + the LMh thermal FSM is engaged. + $ref: /schemas/types.yaml#/definitions/int32 + + qcom,lmh-temperature-high: + description: + An integer expressing temperature threshold in millicelsius at which + the LMh thermal FSM is engaged. + $ref: /schemas/types.yaml#/definitions/int32 + +required: + - compatible + - reg + - interrupts + - #interrupt-cells + - interrupt-controller + - qcom,lmh-cpu-id + - qcom,lmh-temperature-arm + - qcom,lmh-temperature-low + - qcom,lmh-temperature-high + +additionalProperties: false + +examples: + - | + #include + #include + #include + + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x4>; + qcom,lmh-temperature-arm = <65000>; + qcom,lmh-temperature-low = <94500>; + qcom,lmh-temperature-high = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + - | + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x0>; + qcom,lmh-temperature-arm = <65000>; + qcom,lmh-temperature-low = <94500>; + qcom,lmh-temperature-high = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + - |