From patchwork Mon Jul 5 03:57:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunsheng Lin X-Patchwork-Id: 470410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB7E9C07E9B for ; Mon, 5 Jul 2021 03:58:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDF2B61283 for ; Mon, 5 Jul 2021 03:58:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229733AbhGEEAw (ORCPT ); Mon, 5 Jul 2021 00:00:52 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6046 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229495AbhGEEAt (ORCPT ); Mon, 5 Jul 2021 00:00:49 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4GJBbc069ZzXpVb; Mon, 5 Jul 2021 11:52:44 +0800 (CST) Received: from dggpemm500005.china.huawei.com (7.185.36.74) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 5 Jul 2021 11:58:09 +0800 Received: from localhost.localdomain (10.69.192.56) by dggpemm500005.china.huawei.com (7.185.36.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 5 Jul 2021 11:58:09 +0800 From: Yunsheng Lin To: , , , CC: , , , , , , , , , , , Subject: [PATCH net-next 1/2] tools: add missing infrastructure for building ptr_ring.h Date: Mon, 5 Jul 2021 11:57:34 +0800 Message-ID: <1625457455-4667-2-git-send-email-linyunsheng@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625457455-4667-1-git-send-email-linyunsheng@huawei.com> References: <1625457455-4667-1-git-send-email-linyunsheng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To dggpemm500005.china.huawei.com (7.185.36.74) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org In order to build ptr_ring.h in userspace, the cacheline aligning, cpu_relax() and slab related infrastructure is needed, so add them in this patch. As L1_CACHE_BYTES may be different for different arch, which is mostly defined in include/generated/autoconf.h, so user may need to do "make defconfig" before building a tool using the API in linux/cache.h. Also "linux/lockdep.h" is not added in "tools/include" yet, so remove it in "linux/spinlock.h", and the only place using "linux/spinlock.h" is tools/testing/radix-tree, removing that does not break radix-tree testing. Signed-off-by: Yunsheng Lin --- tools/include/asm/cache.h | 56 ++++++++++++++++++++++++ tools/include/asm/processor.h | 36 ++++++++++++++++ tools/include/generated/autoconf.h | 1 + tools/include/linux/align.h | 15 +++++++ tools/include/linux/cache.h | 87 ++++++++++++++++++++++++++++++++++++++ tools/include/linux/gfp.h | 4 ++ tools/include/linux/slab.h | 46 ++++++++++++++++++++ tools/include/linux/spinlock.h | 2 - 8 files changed, 245 insertions(+), 2 deletions(-) create mode 100644 tools/include/asm/cache.h create mode 100644 tools/include/asm/processor.h create mode 100644 tools/include/generated/autoconf.h create mode 100644 tools/include/linux/align.h create mode 100644 tools/include/linux/cache.h create mode 100644 tools/include/linux/slab.h diff --git a/tools/include/asm/cache.h b/tools/include/asm/cache.h new file mode 100644 index 0000000..071e310 --- /dev/null +++ b/tools/include/asm/cache.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TOOLS_LINUX_ASM_CACHE_H +#define __TOOLS_LINUX_ASM_CACHE_H + +#include + +#if defined(__i386__) || defined(__x86_64__) +#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) +#elif defined(__arm__) +#define L1_CACHE_SHIFT (CONFIG_ARM_L1_CACHE_SHIFT) +#elif defined(__aarch64__) +#define L1_CACHE_SHIFT (6) +#elif defined(__powerpc__) + +/* bytes per L1 cache line */ +#if defined(CONFIG_PPC_8xx) +#define L1_CACHE_SHIFT 4 +#elif defined(CONFIG_PPC_E500MC) +#define L1_CACHE_SHIFT 6 +#elif defined(CONFIG_PPC32) +#if defined(CONFIG_PPC_47x) +#define L1_CACHE_SHIFT 7 +#else +#define L1_CACHE_SHIFT 5 +#endif +#else /* CONFIG_PPC64 */ +#define L1_CACHE_SHIFT 7 +#endif + +#elif defined(__sparc__) +#define L1_CACHE_SHIFT 5 +#elif defined(__alpha__) + +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6) +#define L1_CACHE_SHIFT 6 +#else +/* Both EV4 and EV5 are write-through, read-allocate, + direct-mapped, physical. +*/ +#define L1_CACHE_SHIFT 5 +#endif + +#elif defined(__mips__) +#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT +#elif defined(__ia64__) +#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT +#elif defined(__nds32__) +#define L1_CACHE_SHIFT 5 +#else +#define L1_CACHE_SHIFT 5 +#endif + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#endif diff --git a/tools/include/asm/processor.h b/tools/include/asm/processor.h new file mode 100644 index 0000000..3198ad6 --- /dev/null +++ b/tools/include/asm/processor.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TOOLS_LINUX_ASM_PROCESSOR_H +#define __TOOLS_LINUX_ASM_PROCESSOR_H + +#include + +#if defined(__i386__) || defined(__x86_64__) +#include "../../arch/x86/include/asm/vdso/processor.h" +#elif defined(__arm__) +#include "../../arch/arm/include/asm/vdso/processor.h" +#elif defined(__aarch64__) +#include "../../arch/arm64/include/asm/vdso/processor.h" +#elif defined(__powerpc__) +#include "../../arch/powerpc/include/vdso/processor.h" +#elif defined(__s390__) +#include "../../arch/s390/include/vdso/processor.h" +#elif defined(__sh__) +#include "../../arch/sh/include/asm/processor.h" +#elif defined(__sparc__) +#include "../../arch/sparc/include/asm/processor.h" +#elif defined(__alpha__) +#include "../../arch/alpha/include/asm/processor.h" +#elif defined(__mips__) +#include "../../arch/mips/include/asm/vdso/processor.h" +#elif defined(__ia64__) +#include "../../arch/ia64/include/asm/processor.h" +#elif defined(__xtensa__) +#include "../../arch/xtensa/include/asm/processor.h" +#elif defined(__nds32__) +#include "../../arch/nds32/include/asm/processor.h" +#else +#define cpu_relax() sched_yield() +#endif + +#endif diff --git a/tools/include/generated/autoconf.h b/tools/include/generated/autoconf.h new file mode 100644 index 0000000..c588a2f --- /dev/null +++ b/tools/include/generated/autoconf.h @@ -0,0 +1 @@ +#include "../../../include/generated/autoconf.h" diff --git a/tools/include/linux/align.h b/tools/include/linux/align.h new file mode 100644 index 0000000..4e82cdf --- /dev/null +++ b/tools/include/linux/align.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __TOOLS_LINUX_ALIGN_H +#define __TOOLS_LINUX_ALIGN_H + +#include + +/* @a is a power of 2 value */ +#define ALIGN(x, a) __ALIGN_KERNEL((x), (a)) +#define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) +#define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define PTR_ALIGN_DOWN(p, a) ((typeof(p))ALIGN_DOWN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#endif /* _LINUX_ALIGN_H */ diff --git a/tools/include/linux/cache.h b/tools/include/linux/cache.h new file mode 100644 index 0000000..8f86b1b --- /dev/null +++ b/tools/include/linux/cache.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __TOOLS_LINUX__CACHE_H +#define __TOOLS_LINUX__CACHE_H + +#include + +#ifndef L1_CACHE_ALIGN +#define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES) +#endif + +#ifndef SMP_CACHE_BYTES +#define SMP_CACHE_BYTES L1_CACHE_BYTES +#endif + +/* + * __read_mostly is used to keep rarely changing variables out of frequently + * updated cachelines. Its use should be reserved for data that is used + * frequently in hot paths. Performance traces can help decide when to use + * this. You want __read_mostly data to be tightly packed, so that in the + * best case multiple frequently read variables for a hot path will be next + * to each other in order to reduce the number of cachelines needed to + * execute a critical path. We should be mindful and selective of its use. + * ie: if you're going to use it please supply a *good* justification in your + * commit log + */ +#ifndef __read_mostly +#define __read_mostly +#endif + +/* + * __ro_after_init is used to mark things that are read-only after init (i.e. + * after mark_rodata_ro() has been called). These are effectively read-only, + * but may get written to during init, so can't live in .rodata (via "const"). + */ +#ifndef __ro_after_init +#define __ro_after_init __section(".data..ro_after_init") +#endif + +#ifndef ____cacheline_aligned +#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) +#endif + +#ifndef ____cacheline_aligned_in_smp +#ifdef CONFIG_SMP +#define ____cacheline_aligned_in_smp ____cacheline_aligned +#else +#define ____cacheline_aligned_in_smp +#endif /* CONFIG_SMP */ +#endif + +#ifndef __cacheline_aligned +#define __cacheline_aligned \ + __attribute__((__aligned__(SMP_CACHE_BYTES), \ + __section__(".data..cacheline_aligned"))) +#endif /* __cacheline_aligned */ + +#ifndef __cacheline_aligned_in_smp +#ifdef CONFIG_SMP +#define __cacheline_aligned_in_smp __cacheline_aligned +#else +#define __cacheline_aligned_in_smp +#endif /* CONFIG_SMP */ +#endif + +/* + * The maximum alignment needed for some critical structures + * These could be inter-node cacheline sizes/L3 cacheline + * size etc. Define this in asm/cache.h for your arch + */ +#ifndef INTERNODE_CACHE_SHIFT +#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT +#endif + +#if !defined(____cacheline_internodealigned_in_smp) +#if defined(CONFIG_SMP) +#define ____cacheline_internodealigned_in_smp \ + __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT)))) +#else +#define ____cacheline_internodealigned_in_smp +#endif +#endif + +#ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE +#define cache_line_size() L1_CACHE_BYTES +#endif + +#endif /* __LINUX_CACHE_H */ diff --git a/tools/include/linux/gfp.h b/tools/include/linux/gfp.h index 2203075..d7041c0 100644 --- a/tools/include/linux/gfp.h +++ b/tools/include/linux/gfp.h @@ -1,4 +1,8 @@ #ifndef _TOOLS_INCLUDE_LINUX_GFP_H #define _TOOLS_INCLUDE_LINUX_GFP_H +#include + +#define __GFP_ZERO 0x100u + #endif /* _TOOLS_INCLUDE_LINUX_GFP_H */ diff --git a/tools/include/linux/slab.h b/tools/include/linux/slab.h new file mode 100644 index 0000000..f0b7da6 --- /dev/null +++ b/tools/include/linux/slab.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __TOOLS_LINUX_SLAB_H +#define __TOOLS_LINUX_SLAB_H + +#include +#include + +static inline void *kmalloc(size_t size, gfp_t gfp) +{ + void *p; + + p = memalign(SMP_CACHE_BYTES, size); + if (!p) + return p; + + if (gfp & __GFP_ZERO) + memset(p, 0, size); + + return p; +} + +static inline void *kzalloc(size_t size, gfp_t flags) +{ + return kmalloc(size, flags | __GFP_ZERO); +} + +static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) +{ + return kmalloc(n * size, flags); +} + +static inline void *kcalloc(size_t n, size_t size, gfp_t flags) +{ + return kmalloc_array(n, size, flags | __GFP_ZERO); +} + +static inline void kfree(void *p) +{ + free(p); +} + +#define kvmalloc_array kmalloc_array +#define kvfree kfree +#define KMALLOC_MAX_SIZE SIZE_MAX + +#endif diff --git a/tools/include/linux/spinlock.h b/tools/include/linux/spinlock.h index c934572..622266b 100644 --- a/tools/include/linux/spinlock.h +++ b/tools/include/linux/spinlock.h @@ -37,6 +37,4 @@ static inline bool arch_spin_is_locked(arch_spinlock_t *mutex) return true; } -#include - #endif From patchwork Mon Jul 5 03:57:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunsheng Lin X-Patchwork-Id: 470759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92593C07E98 for ; Mon, 5 Jul 2021 03:58:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71B4561283 for ; Mon, 5 Jul 2021 03:58:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbhGEEAu (ORCPT ); Mon, 5 Jul 2021 00:00:50 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6045 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229447AbhGEEAt (ORCPT ); Mon, 5 Jul 2021 00:00:49 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4GJBbc1S69zXnMc; Mon, 5 Jul 2021 11:52:44 +0800 (CST) Received: from dggpemm500005.china.huawei.com (7.185.36.74) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 5 Jul 2021 11:58:10 +0800 Received: from localhost.localdomain (10.69.192.56) by dggpemm500005.china.huawei.com (7.185.36.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 5 Jul 2021 11:58:09 +0800 From: Yunsheng Lin To: , , , CC: , , , , , , , , , , , Subject: [PATCH net-next 2/2] tools/virtio: use common infrastructure to build ptr_ring.h Date: Mon, 5 Jul 2021 11:57:35 +0800 Message-ID: <1625457455-4667-3-git-send-email-linyunsheng@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625457455-4667-1-git-send-email-linyunsheng@huawei.com> References: <1625457455-4667-1-git-send-email-linyunsheng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To dggpemm500005.china.huawei.com (7.185.36.74) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Use the common infrastructure in tools/include to build ptr_ring.h in user space. Signed-off-by: Yunsheng Lin --- tools/virtio/ringtest/Makefile | 2 +- tools/virtio/ringtest/main.h | 100 +++----------------------------------- tools/virtio/ringtest/ptr_ring.c | 102 ++------------------------------------- 3 files changed, 12 insertions(+), 192 deletions(-) diff --git a/tools/virtio/ringtest/Makefile b/tools/virtio/ringtest/Makefile index 85c98c2..89fc024 100644 --- a/tools/virtio/ringtest/Makefile +++ b/tools/virtio/ringtest/Makefile @@ -3,7 +3,7 @@ all: all: ring virtio_ring_0_9 virtio_ring_poll virtio_ring_inorder ptr_ring noring -CFLAGS += -Wall +CFLAGS += -Wall -I../../include CFLAGS += -pthread -O2 -ggdb -flto -fwhole-program LDFLAGS += -pthread -O2 -ggdb -flto -fwhole-program diff --git a/tools/virtio/ringtest/main.h b/tools/virtio/ringtest/main.h index 6d1fccd..95ea050 100644 --- a/tools/virtio/ringtest/main.h +++ b/tools/virtio/ringtest/main.h @@ -10,6 +10,13 @@ #include +#include +#include +#include + +#define smp_acquire smp_rmb +#define smp_release smp_wmb + extern int param; extern bool do_exit; @@ -87,18 +94,6 @@ void wait_for_call(void); extern unsigned ring_size; -/* Compiler barrier - similar to what Linux uses */ -#define barrier() asm volatile("" ::: "memory") - -/* Is there a portable way to do this? */ -#if defined(__x86_64__) || defined(__i386__) -#define cpu_relax() asm ("rep; nop" ::: "memory") -#elif defined(__s390x__) -#define cpu_relax() barrier() -#else -#define cpu_relax() assert(0) -#endif - extern bool do_relax; static inline void busy_wait(void) @@ -110,85 +105,4 @@ static inline void busy_wait(void) barrier(); } -#if defined(__x86_64__) || defined(__i386__) -#define smp_mb() asm volatile("lock; addl $0,-132(%%rsp)" ::: "memory", "cc") -#else -/* - * Not using __ATOMIC_SEQ_CST since gcc docs say they are only synchronized - * with other __ATOMIC_SEQ_CST calls. - */ -#define smp_mb() __sync_synchronize() -#endif - -/* - * This abuses the atomic builtins for thread fences, and - * adds a compiler barrier. - */ -#define smp_release() do { \ - barrier(); \ - __atomic_thread_fence(__ATOMIC_RELEASE); \ -} while (0) - -#define smp_acquire() do { \ - __atomic_thread_fence(__ATOMIC_ACQUIRE); \ - barrier(); \ -} while (0) - -#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) -#define smp_wmb() barrier() -#else -#define smp_wmb() smp_release() -#endif - -#ifdef __alpha__ -#define smp_read_barrier_depends() smp_acquire() -#else -#define smp_read_barrier_depends() do {} while(0) -#endif - -static __always_inline -void __read_once_size(const volatile void *p, void *res, int size) -{ - switch (size) { \ - case 1: *(unsigned char *)res = *(volatile unsigned char *)p; break; \ - case 2: *(unsigned short *)res = *(volatile unsigned short *)p; break; \ - case 4: *(unsigned int *)res = *(volatile unsigned int *)p; break; \ - case 8: *(unsigned long long *)res = *(volatile unsigned long long *)p; break; \ - default: \ - barrier(); \ - __builtin_memcpy((void *)res, (const void *)p, size); \ - barrier(); \ - } \ -} - -static __always_inline void __write_once_size(volatile void *p, void *res, int size) -{ - switch (size) { - case 1: *(volatile unsigned char *)p = *(unsigned char *)res; break; - case 2: *(volatile unsigned short *)p = *(unsigned short *)res; break; - case 4: *(volatile unsigned int *)p = *(unsigned int *)res; break; - case 8: *(volatile unsigned long long *)p = *(unsigned long long *)res; break; - default: - barrier(); - __builtin_memcpy((void *)p, (const void *)res, size); - barrier(); - } -} - -#define READ_ONCE(x) \ -({ \ - union { typeof(x) __val; char __c[1]; } __u; \ - __read_once_size(&(x), __u.__c, sizeof(x)); \ - smp_read_barrier_depends(); /* Enforce dependency ordering from x */ \ - __u.__val; \ -}) - -#define WRITE_ONCE(x, val) \ -({ \ - union { typeof(x) __val; char __c[1]; } __u = \ - { .__val = (typeof(x)) (val) }; \ - __write_once_size(&(x), __u.__c, sizeof(x)); \ - __u.__val; \ -}) - #endif diff --git a/tools/virtio/ringtest/ptr_ring.c b/tools/virtio/ringtest/ptr_ring.c index c9b2633..e058874 100644 --- a/tools/virtio/ringtest/ptr_ring.c +++ b/tools/virtio/ringtest/ptr_ring.c @@ -10,104 +10,10 @@ #include #include -#define SMP_CACHE_BYTES 64 -#define cache_line_size() SMP_CACHE_BYTES -#define ____cacheline_aligned_in_smp __attribute__ ((aligned (SMP_CACHE_BYTES))) -#define unlikely(x) (__builtin_expect(!!(x), 0)) -#define likely(x) (__builtin_expect(!!(x), 1)) -#define ALIGN(x, a) (((x) + (a) - 1) / (a) * (a)) -#define SIZE_MAX (~(size_t)0) -#define KMALLOC_MAX_SIZE SIZE_MAX - -typedef pthread_spinlock_t spinlock_t; - -typedef int gfp_t; -#define __GFP_ZERO 0x1 - -static void *kmalloc(unsigned size, gfp_t gfp) -{ - void *p = memalign(64, size); - if (!p) - return p; - - if (gfp & __GFP_ZERO) - memset(p, 0, size); - return p; -} - -static inline void *kzalloc(unsigned size, gfp_t flags) -{ - return kmalloc(size, flags | __GFP_ZERO); -} - -static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) -{ - if (size != 0 && n > SIZE_MAX / size) - return NULL; - return kmalloc(n * size, flags); -} - -static inline void *kcalloc(size_t n, size_t size, gfp_t flags) -{ - return kmalloc_array(n, size, flags | __GFP_ZERO); -} - -static void kfree(void *p) -{ - if (p) - free(p); -} - -#define kvmalloc_array kmalloc_array -#define kvfree kfree - -static void spin_lock_init(spinlock_t *lock) -{ - int r = pthread_spin_init(lock, 0); - assert(!r); -} - -static void spin_lock(spinlock_t *lock) -{ - int ret = pthread_spin_lock(lock); - assert(!ret); -} - -static void spin_unlock(spinlock_t *lock) -{ - int ret = pthread_spin_unlock(lock); - assert(!ret); -} - -static void spin_lock_bh(spinlock_t *lock) -{ - spin_lock(lock); -} - -static void spin_unlock_bh(spinlock_t *lock) -{ - spin_unlock(lock); -} - -static void spin_lock_irq(spinlock_t *lock) -{ - spin_lock(lock); -} - -static void spin_unlock_irq(spinlock_t *lock) -{ - spin_unlock(lock); -} - -static void spin_lock_irqsave(spinlock_t *lock, unsigned long f) -{ - spin_lock(lock); -} - -static void spin_unlock_irqrestore(spinlock_t *lock, unsigned long f) -{ - spin_unlock(lock); -} +#include +#include +#include +#include #include "../../../include/linux/ptr_ring.h"