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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id g17sm9394624pgh.61.2021.07.03.19.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Jul 2021 19:40:46 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH v2 1/4] clk: qcom: apcs-msm8916: Flag a53mux instead of a53pll as critical Date: Sun, 4 Jul 2021 10:40:29 +0800 Message-Id: <20210704024032.11559-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210704024032.11559-1-shawn.guo@linaro.org> References: <20210704024032.11559-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock source for MSM8916 cpu cores is like below. |\ a53pll --------| \ a53mux +------+ | |------------| cpus | gpll0_vote --------| / +------+ |/ So a53mux rather than a53pll is actually the parent clock of cpu cores. It makes more sense to flag a53mux as critical instead, so that when either a53pll or gpll0_vote is used by cpu cores, the clock will be kept enabled while the other can be disabled. Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 1 - drivers/clk/qcom/apcs-msm8916.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index af6ac17c7dae..d6756bd777ce 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -70,7 +70,6 @@ static int qcom_a53pll_probe(struct platform_device *pdev) init.parent_names = (const char *[]){ "xo" }; init.num_parents = 1; init.ops = &clk_pll_sr2_ops; - init.flags = CLK_IS_CRITICAL; pll->clkr.hw.init = &init; ret = devm_clk_register_regmap(dev, &pll->clkr); diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index cf69a97d0439..d7ac6d6b15b6 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -65,7 +65,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) init.parent_data = pdata; init.num_parents = ARRAY_SIZE(pdata); init.ops = &clk_regmap_mux_div_ops; - init.flags = CLK_SET_RATE_PARENT; + init.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT; a53cc->clkr.hw.init = &init; a53cc->clkr.regmap = regmap; From patchwork Sun Jul 4 02:40:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 470030 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2785034jao; Sat, 3 Jul 2021 19:40:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwALRa3WuRROdklXzwoT/BTqFkTppIkx3fznESkKGUZrf0Y6VJ01SS50UekyLB8Ulo3hsfY X-Received: by 2002:a17:906:cb93:: with SMTP id mf19mr4955347ejb.427.1625366454568; Sat, 03 Jul 2021 19:40:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625366454; cv=none; d=google.com; s=arc-20160816; b=Y/VEZL+yJEjcng11X8yoM+yaT37w+iXj7888r8I5c8wPs+XymTohGu1l5VpNDjcD2i t+3XLVJBTMIk468VgL3QChKF/x8udNA57bU5k6cHVsxdKH4zQOethUUm2gkeYVDXTWSi ITRxA1+9znAWmWgZgAPsYpa7mfFlkydedC8u+Lv0sYdysGsA+BEhPX8EEX5goHDU5IxV pGRrSKZeq3ZvoG04VGBTOL50qvhiMS3TaQFhSNoHfFyThSnTgtQLxHAVfKXPHQRAvXUl gnyRVb28my4t3KyEMAujMRW8QrE63u+SEhdFIOYRn1K1YB/xkXKVg7zsy7UnDUoLx+Pi t6aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=SJ6mWKBojJfVdE79tK2x9bM0KQ+BiVthSv3BXWqHjkA=; b=r905Oy461Z9RchEf5gXemyYVkMYen6/mxLpltzBaLkiD+U15/a167kYAN26Qv0I3iV YCI6p/o3flxcyxQ8/iXldxeiZ34+fbFoJOeE4SUEInjdJU5sptgm7gjtqf/jn5UKoApO ggFFFHbuH9HyHScDj1B3qWqelhNU5JVnfgC3jtga0m5olmFu0DUAV/jM+gkvyoEhXeDQ SZTesI3grqBCewOMaYeAcPTK6O+FQAe/0NkN08dW6+NG8IxeQBvbsyIBXVgHknE0THPL +n67Nib6pxn8y+M5LCd0T8ccpiUsTEizR4PgpEzlOrHqAtSnHLOy5WVf8JD4uglxqfQo c6mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aCFrfva8; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id g17sm9394624pgh.61.2021.07.03.19.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Jul 2021 19:40:49 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH v2 2/4] clk: qcom: a53pll/mux: Use unique clock name Date: Sun, 4 Jul 2021 10:40:30 +0800 Message-Id: <20210704024032.11559-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210704024032.11559-1-shawn.guo@linaro.org> References: <20210704024032.11559-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). That said, a53pll/mux clock needs to be named uniquely. Append @unit-address of device node to the clock name, so that a53pll/mux will be named like below on MSM8939. a53pll@b016000 a53pll@b116000 a53pll@b1d0000 a53mux@b1d1000 a53mux@b011000 a53mux@b111000 Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 8 +++++++- drivers/clk/qcom/apcs-msm8916.c | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index d6756bd777ce..96a118be912d 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -37,6 +37,7 @@ static const struct regmap_config a53pll_regmap_config = { static int qcom_a53pll_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct regmap *regmap; struct resource *res; struct clk_pll *pll; @@ -66,7 +67,12 @@ static int qcom_a53pll_probe(struct platform_device *pdev) pll->status_bit = 16; pll->freq_tbl = a53pll_freq; - init.name = "a53pll"; + /* Use an unique name by appending @unit-address */ + init.name = devm_kasprintf(dev, GFP_KERNEL, "a53pll%s", + strchrnul(np->full_name, '@')); + if (!init.name) + return -ENOMEM; + init.parent_names = (const char *[]){ "xo" }; init.num_parents = 1; init.ops = &clk_pll_sr2_ops; diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index d7ac6d6b15b6..89e0730810ac 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -46,6 +46,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device *parent = dev->parent; + struct device_node *np = parent->of_node; struct clk_regmap_mux_div *a53cc; struct regmap *regmap; struct clk_init_data init = { }; @@ -61,7 +62,12 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) if (!a53cc) return -ENOMEM; - init.name = "a53mux"; + /* Use an unique name by appending parent's @unit-address */ + init.name = devm_kasprintf(dev, GFP_KERNEL, "a53mux%s", + strchrnul(np->full_name, '@')); + if (!init.name) + return -ENOMEM; + init.parent_data = pdata; init.num_parents = ARRAY_SIZE(pdata); init.ops = &clk_regmap_mux_div_ops; From patchwork Sun Jul 4 02:40:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 470031 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2785053jao; Sat, 3 Jul 2021 19:40:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyTYPKhxZ+E0MWw/wKTFuaEhG8/cxaGmJpNSUByF0NK/S9zk5v42dXW69zHllhxtCxIEsIg X-Received: by 2002:a17:906:b0d4:: with SMTP id bk20mr6722635ejb.535.1625366456702; Sat, 03 Jul 2021 19:40:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625366456; cv=none; d=google.com; s=arc-20160816; b=FgxNvtWJWc/Bi6pSRf5/ZKfKmVjPE5w9mJSHZNiIIWCJ7K8ThQQ26bux3+l+GUExPD 56+amGRfSeSfeBIK6uTgllcfweVFhw4x/Gl1DdRPdxSZanCRpqVLEp5e+p0N3UPA1Tve DZS3vs/w7jIkt9IYN1CAsOT4pXCdXER0BjO8PyMe7JTPCOx3cuttTE/bXKJ4vV680AOX NZqf4y6EXlyz9yl4XInx93B3hHAcpf+u842GuCGgE8YYzcl375KfzpTfpHq6PGTobqSB Azterr1VdGC/Z+AijMjTt7XaMjW75Sj7G1/ieeZ03mZ+fgIr+HYEB0eWKz2eW2UPKTE4 xKEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=EI7/NQoCGJxDIiM6o8K9wW0libMiYZLN48mcVrvQP9c=; b=TF7ifjCDUQE2uONtoCV6yS3ELdi3tA+fVAeTNAH+gryWYcnYc61ZakznLi5/WppwQn FlFksmHudgrXS4g1i7pqL+DV3XBo5jbVu6Y70LoCliRcQ/ABXJHGalaGUz4q9wR0bSOH 5LjMsx2niqfzV0KvNd3T261H2eDNgTcq+251RHlqVnddP5oHM8+Mfpy9ym0MCw4SFdH1 Jc1FkLD4KMKIfpicElCcsoOC/uXcRzuT/XbuT3pwS6I67y+vJ3LeZ2uvxDdw/uD6gp0Z FoI4u4FFo9BNhV4SN99309fDz1kTUq2krJGFhXFPDEWon9XKWbE5bEKUy8uCgBEva783 xfNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X3nGaSDH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id g17sm9394624pgh.61.2021.07.03.19.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Jul 2021 19:40:51 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH v2 3/4] dt-bindings: clock: Update qcom, a53pll bindings for MSM8939 support Date: Sun, 4 Jul 2021 10:40:31 +0800 Message-Id: <20210704024032.11559-4-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210704024032.11559-1-shawn.guo@linaro.org> References: <20210704024032.11559-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update qcom,a53pll bindings for MSM8939 support: - Add optional operating-points-v2 property - Add MSM8939 specific compatible Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml index db3d0ea6bc7a..fbd758470b88 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,ipq6018-a53pll - qcom,msm8916-a53pll + - qcom,msm8939-a53pll reg: maxItems: 1 @@ -33,6 +34,8 @@ properties: items: - const: xo + operating-points-v2: true + required: - compatible - reg From patchwork Sun Jul 4 02:40:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 470032 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2785061jao; Sat, 3 Jul 2021 19:40:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyibZlS2helwpJ6M8TYzzHLHqTUFJqWb0/0DFiWM2M+gFeZLULdo9csN1uYoPJlY906/0ke X-Received: by 2002:a17:907:2bd1:: with SMTP id gv17mr6901542ejc.15.1625366457885; Sat, 03 Jul 2021 19:40:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625366457; cv=none; d=google.com; s=arc-20160816; b=WAp6/5blA+1rciOB2UV0ovXNq3Fk6uKd8bkP2KXdfbI42G6eJfeVcNmjolWr69j3sN FM4rRNSf8qy9KWIGoargkMF4Om/0JAmswywUpucdGzhFwP4M+SOVYccdm9OpY0+iA1tE 3Cs5mGBtFBupmjtrQ2Y8rE8yCS19mhwtWS7KLOfwfglCRsqO6Gun140rThyB/GJWBALJ hpyuyTZs2zqeAnFyB2gFZAnY3Nsv69vCutnolL+Nf18GPPcI2Bmm7o5rPQTTTQzZxfP3 C3qzRZ97VBfqfNte8tyVpMExLT2+h+Dr2PP9BMa9YDGwK3Bo6H0/8gay0yPvUE+Eo95D NP/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=d8JSTZ8+AJaTgMTmOHganaZdhQwLLSMBu10AnlPFiu8=; b=W6G7QRgaNnIscFtcSc/z5M1AMgAyd4X+2qCctdC9i/sXaOQZpVjJC4bdv2RxCtzfd2 ny1Pgqo4Z17w3jXPphvOYegqIZK0XNvxSzwzldxCUIo5aBsY3wgPj7MR1KL+8ryApgEn NweSLy62yyyC57I/Lu7BBvJnC1+FKy5oqssl3/CRoahompoXvp8Ivu5JGN7Dzfz1HL2i f1cmJb5N/wYQ0NEO83GfAg389dChsvNsoWRxpnYnRW1NpztLRJqN2iIk1OJIs2dI/JTG JmB7645nWFvKLpyNJEPv1XS3Rr9qyo+Xlaty/s5TZp8dT7i+FH+A72lBROFEeo0EZ+Nc bVrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="PnY/ZDSC"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id g17sm9394624pgh.61.2021.07.03.19.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Jul 2021 19:40:54 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH v2 4/4] clk: qcom: a53-pll: Add MSM8939 a53pll support Date: Sun, 4 Jul 2021 10:40:32 +0800 Message-Id: <20210704024032.11559-5-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210704024032.11559-1-shawn.guo@linaro.org> References: <20210704024032.11559-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MSM8939 has 3 a53pll clocks with different frequency table for Cluster0, Cluster1 and CCI. It adds function qcom_a53pll_get_freq_tbl() to create pll_freq_tbl from OPP, so that those a53pll frequencies can be defined in DT with operating-points-v2 bindings rather than being coded in the driver. In this case, one compatible rather than three would be needed for these 3 a53pll clocks. Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 59 +++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index 96a118be912d..9e6decb9c26f 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -6,9 +6,11 @@ * Author: Georgi Djakov */ +#include #include #include #include +#include #include #include @@ -34,6 +36,55 @@ static const struct regmap_config a53pll_regmap_config = { .fast_io = true, }; +static struct pll_freq_tbl *qcom_a53pll_get_freq_tbl(struct device *dev) +{ + struct pll_freq_tbl *freq_tbl; + unsigned long xo_freq; + unsigned long freq; + struct clk *xo_clk; + int count; + int ret; + int i; + + xo_clk = devm_clk_get(dev, "xo"); + if (IS_ERR(xo_clk)) + return NULL; + + xo_freq = clk_get_rate(xo_clk); + + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return NULL; + + count = dev_pm_opp_get_opp_count(dev); + if (count <= 0) + return NULL; + + freq_tbl = devm_kcalloc(dev, count + 1, sizeof(*freq_tbl), GFP_KERNEL); + if (!freq_tbl) + return NULL; + + for (i = 0, freq = 0; i < count; i++, freq++) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_ceil(dev, &freq); + if (IS_ERR(opp)) + return NULL; + + /* Skip the freq that is not divisible */ + if (freq % xo_freq) + continue; + + freq_tbl[i].freq = freq; + freq_tbl[i].l = freq / xo_freq; + freq_tbl[i].n = 1; + + dev_pm_opp_put(opp); + } + + return freq_tbl; +} + static int qcom_a53pll_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -65,7 +116,12 @@ static int qcom_a53pll_probe(struct platform_device *pdev) pll->mode_reg = 0x00; pll->status_reg = 0x1c; pll->status_bit = 16; - pll->freq_tbl = a53pll_freq; + + pll->freq_tbl = qcom_a53pll_get_freq_tbl(dev); + if (!pll->freq_tbl) { + /* Fall on a53pll_freq if no freq_tbl is found from OPP */ + pll->freq_tbl = a53pll_freq; + } /* Use an unique name by appending @unit-address */ init.name = devm_kasprintf(dev, GFP_KERNEL, "a53pll%s", @@ -96,6 +152,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev) static const struct of_device_id qcom_a53pll_match_table[] = { { .compatible = "qcom,msm8916-a53pll" }, + { .compatible = "qcom,msm8939-a53pll" }, { } }; MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);