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Fri, 2 Jul 2021 08:55:31 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, aford173@gmail.com, Dong Aisheng , stable@vger.kernel.org Subject: [PATCH 1/1] clk: imx6q: fix uart earlycon unwork Date: Fri, 2 Jul 2021 16:54:38 +0800 Message-Id: <20210702085438.1988087-1-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR02CA0087.apcprd02.prod.outlook.com (2603:1096:4:90::27) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR02CA0087.apcprd02.prod.outlook.com (2603:1096:4:90::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.22 via Frontend Transport; Fri, 2 Jul 2021 08:55:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f45c68e2-4e70-4deb-af22-08d93d372576 X-MS-TrafficTypeDiagnostic: DU2PR04MB8680: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:510; 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There're actually two uart clocks (ipg, per) on MX6QDL, but the 'Fixes' commit change to register only one which means another clock may be disabled during booting phase and result in the earlycon unwork. Cc: stable@vger.kernel.org # v5.10+ Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout") Signed-off-by: Dong Aisheng Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 496900de0b0b..de36f58d551c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -974,6 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); } - imx_register_uart_clocks(1); + imx_register_uart_clocks(2); } CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);