From patchwork Wed Jun 30 13:31:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 469214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B081C11F72 for ; Wed, 30 Jun 2021 13:32:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 37CC761621 for ; Wed, 30 Jun 2021 13:32:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234877AbhF3Ne2 (ORCPT ); Wed, 30 Jun 2021 09:34:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235018AbhF3Ne0 (ORCPT ); Wed, 30 Jun 2021 09:34:26 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A5ADC0617A8 for ; Wed, 30 Jun 2021 06:31:54 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id q18so5118882lfc.7 for ; Wed, 30 Jun 2021 06:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nNBOq0bo15wva/D2WTCq88A/17ZeZyPRomS/LrNe0ts=; b=dgIY7sK4bnZntJsFdKeuX3JSXJijisPf4DrByhje8LZyHq2IWlhKVP9ku1xgZUzpAf sJWmXN80L2edOpoIl0L+D9g1zNv3tkeyos/BqwQa07bx+5RrBdGrTiOa/TebxsbQNiv6 /NZPnfZS/AuQAyccnvHLFdjQIBN8dUXq1/waUmbVrAhiJjUClWN0IbU9EXh0dcvp3esK AUbTUloBr+crrte1LDaHE0hBUOciBT092e8iikvHXYMEHuWY8KlzOydsxPF2hfhs86id RLc2NT9iscm5unOzaEBluXFP0UbvZukVXIZDho2VFUVs7AmsMf1uin/zQ33PQw+K4oFp qXUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nNBOq0bo15wva/D2WTCq88A/17ZeZyPRomS/LrNe0ts=; b=poYhtp1K1o9T28DEn2s8stwjnXG0ZGsqYrnh7ZoJHURE1EN4g35HWr+cwLC5KnpRHb S+OR7NmH325TrUasdJbHjzwxc7Ew2QUibh+aenzeTSJ5JewOftS5LcTeB2WqLyhAMQEz T3M6j/noWFWPi4ZY/8MlJeMpaop4HXGnQ4AJ/dfjWYFQjyrKM2r8cL2UEudpzmDpz0wx kxX2pq/Mc/EMzNtTiMJSNtyI7zGvhs5NkYfqLa6tsioDOZZGHnEh/rdoei60H/8FJGFu 1w5WF22bHEgVAVQ13MdqiTLBZFpmRHjx4FmBI49tjAzNEEJh1NXsC4AoKowjUS5OhVgn S8Sw== X-Gm-Message-State: AOAM531xImKeOI0O5Qvbc8xEuhpI/lmq1k22Bk2TxftlbxSRLRB/lYEz xZVczFw5uKQwZqqCv+Gb5aGW4QIpocjCmA== X-Google-Smtp-Source: ABdhPJzdmU+WJzwkad4YSPbt5INjxwDGUwStMVsVt49AZYkHTIMCGR6hXow3w1TJOc0Tf4F3l08Gcg== X-Received: by 2002:ac2:546b:: with SMTP id e11mr28134650lfn.282.1625059912401; Wed, 30 Jun 2021 06:31:52 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x20sm1578098lfd.128.2021.06.30.06.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jun 2021 06:31:51 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Wed, 30 Jun 2021 16:31:44 +0300 Message-Id: <20210630133149.3204290-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210630133149.3204290-1-dmitry.baryshkov@linaro.org> References: <20210630133149.3204290-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..48d86fb34fa7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -55,6 +55,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + Performance state to use for MMCX to enable register access. + maxItems: 1 + required: - compatible - reg @@ -64,6 +74,15 @@ required: - '#reset-cells' - '#power-domain-cells' +# Either both properties are present or both are absent +dependencies: + power-domains: + required: + - required-opps + required-opps: + required: + - power-domains + additionalProperties: false examples: From patchwork Wed Jun 30 13:31:45 2021 Content-Type: text/plain; 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Wed, 30 Jun 2021 06:31:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: clock: qcom, videocc: add mmcx power domain Date: Wed, 30 Jun 2021 16:31:45 +0300 Message-Id: <20210630133149.3204290-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210630133149.3204290-1-dmitry.baryshkov@linaro.org> References: <20210630133149.3204290-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,videocc.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..22421173e1ca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + Performance state to use for MMCX to enable register access. + maxItems: 1 + required: - compatible - reg @@ -56,6 +66,15 @@ required: - '#reset-cells' - '#power-domain-cells' +# Either both properties are present or both are absent +dependencies: + power-domains: + required: + - required-opps + required-opps: + required: + - power-domains + additionalProperties: false examples: From patchwork Wed Jun 30 13:31:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 468694 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp354428jao; Wed, 30 Jun 2021 06:32:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXHYOqxd7Ms8dAML0am3r24QAVVZ4hKu622xjMlsbAnFM3pEFQtxpZ/3m98goS2fP/wPZb X-Received: by 2002:a05:6e02:1b8f:: with SMTP id h15mr26678452ili.151.1625059925917; Wed, 30 Jun 2021 06:32:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625059925; cv=none; d=google.com; s=arc-20160816; b=Ik9WoTiYucVYZrSWpIir2o103fzDxCo62f7r9wcO+8+Iy7GvfYtSP/SE99GN02LoFe HTZnYB24ztMOAWGJHSmadF8psleCPIbl9Ndxqs9pSF5JDP1RfoyjhnGzODvBoOUzjp/7 RtnU8dBkRSlLOHect/YIpIgSHRZ/HFKpAhqK4ptA2UxJh3fExc7M3cCrj6Q+jYiUxuZi XjBBu3HhQ6BM5eGTX/OYim2dxgltqbNlChDr8Vn1B++diiFIQ/1N3I1abUg+YUXGPs+T ffWip0+WhYWlMj+r2jTltMt1XOH3UEevTO6CvBI6Y1NWBHX5aRWgh+LNHQcly9jYXC1K rRew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Tl387mt4MjPWYSU9zDyMRbXy2Bncp1nuQ43d/RB/LnM=; b=J5PRJkJPzjRuuRaLFkRrdjffl86sjphwocEQS+Gm/iukw45L+NW3aIqv+fM33AsmFb AJdZRf8dhFDWtOY9eV61kS21/JQaDDICO8nL8j6jaI2msa/8pzjedb6rSkSe/LHwqxsv ERhqxL5QUr/FjApufRP5dXTLYODZ3t5Cl6xb+TNUD+IB1XcaGC54sH8LEzJg2bmH7HUX PxhEM2nBnyTo/AgPBSjkbMt1tC4kKOJsbqFvnigAmoFn8z0XSZD5dJHJgzvy7+0LIWY6 J0xbLYoleOJsDpTbQoJZDtn2oLexBBmmlflHAfdA4SkPXC+PrrXHuMBVtoIo9exC4zdj 0EUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JduIj8fm; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Currently we used a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Teach Qualcomm clock controller code about setting up power domains and using them for gdsc control. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/common.c | 55 ++++++++++++++++++++++++++++++++++----- drivers/clk/qcom/gdsc.c | 6 +++++ 2 files changed, 55 insertions(+), 6 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 60d2a78d1395..eeb5b8c93032 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include "common.h" #include "clk-rcg.h" @@ -76,6 +78,16 @@ qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) struct resource *res; struct device *dev = &pdev->dev; + if (of_find_property(dev->of_node, "required-opps", NULL)) { + int pd_opp; + + pd_opp = of_get_required_opp_performance_state(dev->of_node, 0); + if (pd_opp < 0) + return ERR_PTR(pd_opp); + + dev_pm_genpd_set_performance_state(dev, pd_opp); + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) @@ -224,6 +236,11 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } +static void qcom_cc_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -236,11 +253,28 @@ int qcom_cc_really_probe(struct platform_device *pdev, struct clk_regmap **rclks = desc->clks; size_t num_clk_hws = desc->num_clk_hws; struct clk_hw **clk_hws = desc->clk_hws; + bool use_pm = false; cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); if (!cc) return -ENOMEM; + if (of_find_property(dev->of_node, "required-opps", NULL)) { + use_pm = true; + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; + } + + ret = devm_add_action_or_reset(dev, qcom_cc_pm_runtime_disable, dev); + if (ret) + return ret; + } + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -251,7 +285,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_reset_controller_register(dev, &reset->rcdev); if (ret) - return ret; + goto err; if (desc->gdscs && desc->num_gdscs) { scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); @@ -262,11 +296,11 @@ int qcom_cc_really_probe(struct platform_device *pdev, scd->num = desc->num_gdscs; ret = gdsc_register(scd, &reset->rcdev, regmap); if (ret) - return ret; + goto err; ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, scd); if (ret) - return ret; + goto err; } cc->rclks = rclks; @@ -277,7 +311,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, for (i = 0; i < num_clk_hws; i++) { ret = devm_clk_hw_register(dev, clk_hws[i]); if (ret) - return ret; + goto err; } for (i = 0; i < num_clks; i++) { @@ -286,14 +320,23 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_clk_register_regmap(dev, rclks[i]); if (ret) - return ret; + goto err; } ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); if (ret) - return ret; + goto err; + + if (use_pm) + pm_runtime_put(dev); return 0; + +err: + if (use_pm) + pm_runtime_put(dev); + + return ret; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 51ed640e527b..40c384bda4fc 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -237,6 +238,8 @@ static int gdsc_enable(struct generic_pm_domain *domain) struct gdsc *sc = domain_to_gdsc(domain); int ret; + pm_runtime_get_sync(domain->dev.parent); + if (sc->pwrsts == PWRSTS_ON) return gdsc_deassert_reset(sc); @@ -326,6 +329,8 @@ static int gdsc_disable(struct generic_pm_domain *domain) if (sc->flags & CLAMP_IO) gdsc_assert_clamp_io(sc); + pm_runtime_put(domain->dev.parent); + return 0; } @@ -427,6 +432,7 @@ int gdsc_register(struct gdsc_desc *desc, continue; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; + scs[i]->pd.dev.parent = desc->dev; ret = gdsc_init(scs[i]); if (ret) return ret; From patchwork Wed Jun 30 13:31:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 468693 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp354401jao; 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Drop the now unused mmcx regulator. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..1c8478d1247d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -271,13 +271,6 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - mmcx_reg: mmcx-reg { - compatible = "regulator-fixed-domain"; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - regulator-name = "MMCX"; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2362,7 +2355,8 @@ videocc: clock-controller@abf0000 { clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; @@ -2627,7 +2621,8 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Wed Jun 30 13:31:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 468810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 653FEC11F6A for ; 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Wed, 30 Jun 2021 06:31:56 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x20sm1578098lfd.128.2021.06.30.06.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jun 2021 06:31:56 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH 5/6] clk: qcom: dispcc-sm8250: stop using mmcx regulator Date: Wed, 30 Jun 2021 16:31:48 +0300 Message-Id: <20210630133149.3204290-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210630133149.3204290-1-dmitry.baryshkov@linaro.org> References: <20210630133149.3204290-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdsc. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index de09cd5c209f..dfbfe64b12f6 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -955,7 +955,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Wed Jun 30 13:31:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 468695 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp354460jao; Wed, 30 Jun 2021 06:32:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytSAylQFT5wrkg3SadudoaLemEHiZmU+HaQQWLTFBdr8KDdImwAC745nGotzyPosQqkxyN X-Received: by 2002:a5d:9acb:: with SMTP id x11mr7880454ion.133.1625059927716; Wed, 30 Jun 2021 06:32:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625059927; cv=none; d=google.com; s=arc-20160816; b=QDF06iMCdluqvqJpALog6yS26sCM3GJq+ibwAUQiWmOjqjeFJniJT8plB18fnOOeBB 6QWAAAlTllJ5p/wrelgaYYLEBREEuxcNCZgfhB0bcuc6Y8f/hi0CvAD5ZlGQjji3SfPd YRZh5TEp9ThzZVC4hBDG6mODhLzQvSb8NqA0UgEnwyS8G8FImjrgfLVPpDtlgHY2gRzB a5CrTaXck31skcNlvl8h526hBiWlgwQa3lJHEQb2N7Zn2/8ROJDcZ/FBUqhyw77uhvgu yPvWG6KrVp6AqqnAuwhGVal3m8OfPomx63dExdfa/0tqEfiSHfqy+dVoV4dX6Lu3ndNX KQOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OW6r9Ztak14Z94NLN85hpavnPWferFff+9qy6SUKk4g=; b=fdKuDe8JgtO6qplp4zdC3IxlPYUQQgRDh+8MBibg9nkkcEBDMaTDr/kpXeajH59hIC SRTXcyl1+WbAIHvH5lxTU53Q8JDg3QPyN0xeIce1LfrDqX6K6a6d0g6ga3k3GkVGmUvc CBmdZsJ3xNY/khB8eJRr2ZGIoajFhkyescrZc8oHR1YkeadIl2K7GKpSSWYrLYjnVdUo jPa6AXmnrDeYPOCrKAx3aZwAiiIsXV+2jv+rxU5RMTvANYEh5j2qhu6ztjcc50Zoi8N+ c+tKal4KCMCtqDYvRk/jvEb7gv0wiakekbPN5oxhWMClPQVv4065JzSd3I1zgRsd6QVA MFfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iGjCMoZA; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/videocc-sm8250.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.30.2 Reviewed-by: Bjorn Andersson diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 7b435a1c2c4b..eedef85d90e5 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -276,7 +276,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -286,7 +285,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -296,7 +294,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -306,7 +303,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = {