From patchwork Sat May 13 09:47:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 99742 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp700132qge; Sat, 13 May 2017 02:52:05 -0700 (PDT) X-Received: by 10.98.34.22 with SMTP id i22mr7841916pfi.103.1494669125400; Sat, 13 May 2017 02:52:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494669125; cv=none; d=google.com; s=arc-20160816; b=Gvd50BT+J6MgnN2f/H/KWsJbrGVXXsBTgO0qW4iLXILGPgX0rWjVO/E4rcj19WMWfZ a3Y29dmSRq9VHlqJRlXyVrXe0Hpv/M85qRz7UZN+Xm9Txoa/oC6xdqMoT4/zsgp/WQKM dX+t/pfzntiwGxNc+XmnoMgXkHkFrq9iFOP/Vdv6vAl+7KSKVyn6bw2/v0UAOhcOwVG5 klmj1S4RkHOU4CeuoKWa+6FsK9lbT/Qf5+reCbXRZyaYv06fnRovmufrRI9YdwAu8L6b POlCSwdwf9JP6aynloBjiIO8vTsrWM/2WTZPTbyEcJTl8l3dks5t0w4uetc+TaZS6IjE HfQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=+bg9oKN4CfLrBSrVj4H6qoJsn8z643IisdZhlSDz3S8=; b=hJfjOsD7H3S97FxvgTlH6SiLyeyxsUT+Pt3UjisMIh+1tkl01wdYLkOWxIyfhGB3eR FT8vl3OeVdTNaCbmjq0xEWdbhPYFmGGmhdetBdafK/S+M3LBpzk56HbpGuE6C1NcKZwE 2VqaHDJQNLftmeI/devhe3xZjK5W6OSV4jFI9yyKGxjCPB19VZAjC+nL1xBKb3UlrcAO 4FZIUfPCBtO3nYDcr/zPtl2dQIDbinu3iqvBBMMioNVdmRBkXx2BK7ZmPuWLfW/cUOan DKAHUuspBbumiZoUQGabJrg2l9d97OrSH9f7z0uBI0IPOCem0bGPCA2QR5QWkzfZGRmW DyCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s184si5787295pfb.65.2017.05.13.02.52.05; Sat, 13 May 2017 02:52:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752240AbdEMJwB (ORCPT + 7 others); Sat, 13 May 2017 05:52:01 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:5944 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751885AbdEMJwB (ORCPT ); Sat, 13 May 2017 05:52:01 -0400 Received: from 172.30.72.54 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.54]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ANM88405; Sat, 13 May 2017 17:51:24 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.91.84) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Sat, 13 May 2017 17:50:56 +0800 From: shameer To: , , , , CC: , , , , , , , , , , shameer Subject: [RFC v1 2/7] iommu/arm-smmu-v3: Add erratum framework functions Date: Sat, 13 May 2017 10:47:26 +0100 Message-ID: <20170513094731.3676-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> References: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.91.84] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5916D71C.011E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b23a9c723fbcb97cfe65d31edb629bd8 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This will provide a way to replace the existing skip_prefetch_cmd erratum using the new framework. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 58 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index a166590..f20d5d5 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -664,16 +664,72 @@ enum smmu_erratum_match_type { se_match_dt, }; +void erratum_skip_prefetch_cmd(struct arm_smmu_device *smmu, void *arg) +{ + smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; +} + struct smmu_erratum_workaround { enum smmu_erratum_match_type match_type; const void *id; /* Indicate the Erratum ID */ const char *desc_str; + void (*enable)(struct arm_smmu_device *, void *); }; static const struct smmu_erratum_workaround smmu_workarounds[] = { }; +typedef bool (*se_match_fn_t)(const struct smmu_erratum_workaround *, + const void *); +static +bool smmu_check_dt_erratum(const struct smmu_erratum_workaround *wa, + const void *arg) +{ + const struct device_node *np = arg; + + return of_property_read_bool(np, wa->id); +} + +static void smmu_enable_errata(struct arm_smmu_device *smmu, + enum smmu_erratum_match_type type, + se_match_fn_t match_fn, + void *arg) +{ + const struct smmu_erratum_workaround *wa = smmu_workarounds; + + for (; wa->desc_str; wa++) { + if (wa->match_type != type) + continue; + + if (match_fn(wa, arg)) { + if (wa->enable) { + wa->enable(smmu, arg); + dev_info(smmu->dev, + "Enabling workaround for %s\n", + wa->desc_str); + } + } + } +} + + +static void smmu_check_workarounds(struct arm_smmu_device *smmu, + enum smmu_erratum_match_type type, + void *arg) +{ + se_match_fn_t match_fn = NULL; + + switch (type) { + case se_match_dt: + match_fn = smmu_check_dt_erratum; + break; + } + + smmu_enable_errata(smmu, type, match_fn, arg); + +} + static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) { return container_of(dom, struct arm_smmu_domain, domain); @@ -2641,6 +2697,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, parse_driver_options(smmu); + smmu_check_workarounds(smmu, se_match_dt, dev->of_node); + if (of_dma_is_coherent(dev->of_node)) smmu->features |= ARM_SMMU_FEAT_COHERENCY; From patchwork Sat May 13 09:47:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 99745 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp700484qge; Sat, 13 May 2017 02:53:38 -0700 (PDT) X-Received: by 10.99.127.73 with SMTP id p9mr8163981pgn.169.1494669218459; Sat, 13 May 2017 02:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494669218; cv=none; d=google.com; s=arc-20160816; b=UlBoCqkBnIW3DyM0j+4V1EUyAg1lAwLsLpC4NHY/7dgNIluMGp+7guKdIDODlnkWPM /SSqAm1SK1FwZ4fXgRu2Lgc26Nkr2k9IFkTWyAmiIeg2XzQ/bQvXzq5WYmCgpKyQsIhb heROShpe6uYtC7JKuTqL/eahTDoGEnwIlD3SB9H3NiypVi1thAAQKNhgcz/Otk7J4qfM u+SNuXrSSFUa422k5GkoiKVvO80JoQAOwNXFA6IvCWjLpF4qeXuhySU42gELnAtgXwA8 LofpnfzTrBg8X9gdZkSbMO2quV6YXfeEOD64r9+3xmIMYZmriALvbhaoi//vmeQcuyNv g1Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=SeFWzkoKKMI+F83xR6VwukpJUL+CKf4fg3GMsKZn71Y=; b=BcBS/dQ/C62QWe7XfS1imGBe+QD1fAUm+9slvtcEv22plbXaTvrwD74J/d7HGefDvI wgmhAH239y15LqKWovYySZ0bpy2Opb4vgoMuykbUpVcYnFhQCiYhe6vzggup1zxswfqA VndMAF8bMSCI20NgA3PmZ7xy/Qju2jL0ppfdUvcSs1S5f0QZ6egQE9/vP/hKKa2oFRhk /7i0kt+O8rhYkwGwldfgxYkmvw/vYe1aUzWxGyvUaXMpCWBlYhrFWQQjc9MRL8cRo/xX tN+IuRVY2u679Ph4Jgt1jc9DK4W9zLM4QvL/89u9Sd3gVeybRc9oR/qOCJxOsVU7/dc4 b3Cg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c26si5622017pfl.163.2017.05.13.02.53.38; Sat, 13 May 2017 02:53:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752676AbdEMJxh (ORCPT + 7 others); Sat, 13 May 2017 05:53:37 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6286 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751885AbdEMJxg (ORCPT ); Sat, 13 May 2017 05:53:36 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOL14083; Sat, 13 May 2017 17:53:04 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.91.84) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Sat, 13 May 2017 17:51:06 +0800 From: shameer To: , , , , CC: , , , , , , , , , , shameer Subject: [RFC v1 4/7] iommu/arm-smmu-v3: Enable HiSilicon erratum 161010701 Date: Sat, 13 May 2017 10:47:28 +0100 Message-ID: <20170513094731.3676-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> References: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.91.84] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5916D783.003A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9a45a414b2a43475240e69b4981d090d Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This replaces the existing broken_prefetch_cmd quirk using the new erratum framework. Signed-off-by: shameer --- arch/arm64/Kconfig | 10 +++++++++- drivers/iommu/arm-smmu-v3.c | 36 ++++++++++-------------------------- 2 files changed, 19 insertions(+), 27 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a39029b..21d61ff 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -508,8 +508,16 @@ config QCOM_FALKOR_ERRATUM_1009 If unsure, say Y. -endmenu +config HISILICON_ERRATUM_161010701 + bool "HiSilicon erratum 161010701: Skip SMMU Prefetch Cmd" + default y + help + On HiSilicon Hip06/Hip07 platforms, the SMMU v3 doesn't support the + CMD_PREFETCH_CFG. This will skip the prefetch cmd usage. + If unsure, say Y. + +endmenu choice prompt "Page size" diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index f20d5d5..14538cb 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -650,16 +650,6 @@ struct arm_smmu_domain { struct iommu_domain domain; }; -struct arm_smmu_option_prop { - u32 opt; - const char *prop; -}; - -static struct arm_smmu_option_prop arm_smmu_options[] = { - { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, - { 0, NULL}, -}; - enum smmu_erratum_match_type { se_match_dt, }; @@ -677,7 +667,17 @@ struct smmu_erratum_workaround { }; static const struct smmu_erratum_workaround smmu_workarounds[] = { +#ifdef CONFIG_HISILICON_ERRATUM_161010701 + { + .match_type = se_match_dt, + .id = "hisilicon,erratum-161010701", + .desc_str = "HiSilicon erratum 161010701", + .enable = erratum_skip_prefetch_cmd, + }, +#endif + { + }, }; typedef bool (*se_match_fn_t)(const struct smmu_erratum_workaround *, @@ -735,20 +735,6 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) return container_of(dom, struct arm_smmu_domain, domain); } -static void parse_driver_options(struct arm_smmu_device *smmu) -{ - int i = 0; - - do { - if (of_property_read_bool(smmu->dev->of_node, - arm_smmu_options[i].prop)) { - smmu->options |= arm_smmu_options[i].opt; - dev_notice(smmu->dev, "option %s\n", - arm_smmu_options[i].prop); - } - } while (arm_smmu_options[++i].opt); -} - /* Low-level queue manipulation functions */ static bool queue_full(struct arm_smmu_queue *q) { @@ -2695,8 +2681,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, else ret = 0; - parse_driver_options(smmu); - smmu_check_workarounds(smmu, se_match_dt, dev->of_node); if (of_dma_is_coherent(dev->of_node)) From patchwork Sat May 13 09:47:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 99747 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp700528qge; Sat, 13 May 2017 02:53:51 -0700 (PDT) X-Received: by 10.98.73.9 with SMTP id w9mr9078265pfa.218.1494669231112; Sat, 13 May 2017 02:53:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494669231; cv=none; d=google.com; s=arc-20160816; b=GC6750qHYmfRJ6aOXFYQMTH4aa9JMuOwDfJpLBH/p/McwXfuuSg/gHXK3Z1radAlFQ RGeIZ7mRjyIZx4oDY05KS082BzzreNl8xgNL6zk3dgjcoDN+EX14vwwojRVkJQYCLZpK Uaol7GBpS/ojcXtda/oL3JXyDsLfulQCEvLj8WKb3KSXt3WsaOMRz21NzTQnbSWDeign ejX9duHGdixjgSxlKqHB4ffXA6O0P4Ma076BHX0VAGwa30cgtXuHcZvxvUIt2WfA8YJy Hg3UwZAvmOHLt7wY2l78JA7KDPenOwO5puMkeYFQj7VuBzy+F26PQQgOqoC6iwQkuGXy frcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rm8hN/zAt7ZYgQww3WS7eTy9aUsI+rorCyzkwsJah2U=; b=QHEBCeeXGjAozlztaeHWm6dGxQXF8MhblRODTQoZc2FW/v/5vya+DRV9pkixChjxom mvb4pyNCcDtzBw5YuaqPtp3FbG04ZMIhKNtSNXAHqgRCJu3Eb/qIN4ch2yW8TNU40HRH +1re07EI2y/4SQHStBlEECeNE3b1lNcHByanzwVffI/lmpnJJqz/dV6PwtGrNs7UEKwZ L+5x1A2DotipOMMr5l73Nt9A2txQnecjyuS6c2eVCnxgBfe+wnCCRU+uzZAsxb0c9qIO cZQD4RSvuiiR+38vE+lDOJDk/Q7WrZ5qQfhkAFP8S4/G3ciQIu0mOJJIUFCvYnJcpbsQ 367A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c26si5622017pfl.163.2017.05.13.02.53.50; Sat, 13 May 2017 02:53:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751885AbdEMJxt (ORCPT + 7 others); Sat, 13 May 2017 05:53:49 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6288 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752699AbdEMJxs (ORCPT ); Sat, 13 May 2017 05:53:48 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOL14085; Sat, 13 May 2017 17:53:04 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.91.84) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Sat, 13 May 2017 17:51:11 +0800 From: shameer To: , , , , CC: , , , , , , , , , , shameer Subject: [RFC v1 5/7] iommu/arm-smmu-v3: Enable ACPI based HiSilicon erratum 161010701 Date: Sat, 13 May 2017 10:47:29 +0100 Message-ID: <20170513094731.3676-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> References: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.91.84] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5916D782.00E7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2249c3c04c0b13ae77a256d479371668 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This uses the ACPI IORT model number to enable the erratum. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 14538cb..770cc9e 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -652,6 +652,7 @@ struct arm_smmu_domain { enum smmu_erratum_match_type { se_match_dt, + se_match_acpi_iort_model, }; void erratum_skip_prefetch_cmd(struct arm_smmu_device *smmu, void *arg) @@ -674,6 +675,13 @@ static const struct smmu_erratum_workaround smmu_workarounds[] = { .desc_str = "HiSilicon erratum 161010701", .enable = erratum_skip_prefetch_cmd, }, + { + .match_type = se_match_acpi_iort_model, + .id = (void *)ACPI_IORT_SMMU_HISILICON_HI161X, + .desc_str = "HiSilicon erratum 161010701", + .enable = erratum_skip_prefetch_cmd, + }, + #endif { @@ -691,6 +699,15 @@ bool smmu_check_dt_erratum(const struct smmu_erratum_workaround *wa, return of_property_read_bool(np, wa->id); } +static +bool smmu_check_acpi_iort_erratum(const struct smmu_erratum_workaround *wa, + const void *arg) +{ + const struct acpi_iort_smmu_v3 *iort_smmu = arg; + + return (iort_smmu->model == *(u32 *)(&wa->id)) ? true : false; +} + static void smmu_enable_errata(struct arm_smmu_device *smmu, enum smmu_erratum_match_type type, se_match_fn_t match_fn, @@ -724,6 +741,9 @@ static void smmu_check_workarounds(struct arm_smmu_device *smmu, case se_match_dt: match_fn = smmu_check_dt_erratum; break; + case se_match_acpi_iort_model: + match_fn = smmu_check_acpi_iort_erratum; + break; } smmu_enable_errata(smmu, type, match_fn, arg); @@ -2654,6 +2674,8 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, /* Retrieve SMMUv3 specific data */ iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; + smmu_check_workarounds(smmu, se_match_acpi_iort_model, iort_smmu); + if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE) smmu->features |= ARM_SMMU_FEAT_COHERENCY; From patchwork Sat May 13 09:47:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 99748 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp700543qge; Sat, 13 May 2017 02:53:54 -0700 (PDT) X-Received: by 10.98.57.212 with SMTP id u81mr9065037pfj.9.1494669234507; Sat, 13 May 2017 02:53:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494669234; cv=none; d=google.com; s=arc-20160816; b=G58HZT5j5L3p6B/mJ2GHsJxFLHp+2bzUvrEUYEO3x5Dnofd5LeZZ//8YM2PxI8rSNX 6Hehp57ZV1Uz5kIvpWyUR1pK4hsOdamwgqhgxxp3qTbzu1phL8Ks6GM9wTiGrm39jPRn bb2AgXa/3OkxyPhdgshhUAXaSfLfZnRce2XjqIAhlOcMGbskEOKStFxFvyQAAL+/y4Yv 8TSYb3hiNvi/8Ymr969PC29gnHbVWS4x6+v/dso6nK4SRALcs0HOhO9GAy+O3QW7zRjU d1lnzuDqRMJcteNrYmMaw/WlrdIokGdZdJTH7m92Eux0oEPKyIWrdhevlfIaUGeYeNFu lxsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=y2V1hB9MRJrBOp8GRgw7mDHjgVK2MIQwmY4rRsdTVd8=; b=wElGVj2pKfStr2BT5zu3t7sJOPDNdX5Zh0OAFmHGmNCzwopfe7lD9MDLs7yIlGYiGU a3ndWa3nrl78nJUY64pPo2+sDB5+9Y5C2SJkQsFg1/cv8JCwrJt/JQcl8UHnTuUJ49mV XqzlfR5fRfnQbJuzhLkrP3S2E2jyII/JaHYOIq82wIMReyl8MPkRuHVtRSH3a2leWIKw fjctKJ6fuwCs5dpicFfMujeMMeJZ4yv3YTh9Nbbjbz4lQLJnkq4VxoLzZK4inG16Qxu+ SXBU6thfAaWJCXWbGJqEQQAmhm/KGCOIZk2Xz/IVYEjbmJvF+hdWtwh1wXc8u/N+406Z opRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c26si5622017pfl.163.2017.05.13.02.53.54; Sat, 13 May 2017 02:53:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752741AbdEMJxx (ORCPT + 7 others); Sat, 13 May 2017 05:53:53 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6289 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752699AbdEMJxw (ORCPT ); Sat, 13 May 2017 05:53:52 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOL14087; Sat, 13 May 2017 17:53:05 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.91.84) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Sat, 13 May 2017 17:51:22 +0800 From: shameer To: , , , , CC: , , , , , , , , , , shameer Subject: [RFC v1 7/7] iommu/arm-smmu-v3: Enable ACPI based HiSilicon erratum 161010801 Date: Sat, 13 May 2017 10:47:31 +0100 Message-ID: <20170513094731.3676-8-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> References: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.91.84] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5916D783.002F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 65e8041c8d29091637ee01567c3f9a69 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. ACPI CSRT vendor specific blobs are used to pass the reserve address region info on these platforms. HiSilicon CSRT table contains a resource group whose device Id matches with the SMMU device model id defined in the IORT spec. This SMMU group will not have the optional Resource group shared info. typedef struct { UINT32 Length; UINT32 VendorId; UINT32 SubvendorId; UINT16 DeviceId; ---->Set to IORT SMMU Model number. UINT16 SubdeviceId; UINT16 Revision; UINT8 Reserved[2]; UINT32 SharedInfoLength; ---->Set to zero. ACPI_CSRT_RESOURCE_DESCRIPTOR RsrcDesc; } ACPI_CSRT_RESOURCE_GROUP; The resource descriptor associated with this group will have the vendor specific section populated to represent the MSI region as below. typedef struct { UINT32 Length; UINT16 ResourceType; UINT16 ResourceSubtype; UINT32 UID; /* Vendor defined info */ UINT64 Base; -->Corresponding SMMU node base address. UINT64 MSIResvStart; -----> HW MSI reserve start address. UINT32 MSIResvLen; -------> HW MSI reserve len. } ACPI_CSRT_RESOURCE_DESCRIPTOR; Signed-off-by: shameer --- arch/arm64/Kconfig | 10 ++++++ drivers/iommu/arm-smmu-v3.c | 75 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 21d61ff..e7ebd97 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -516,6 +516,16 @@ config HISILICON_ERRATUM_161010701 CMD_PREFETCH_CFG. This will skip the prefetch cmd usage. If unsure, say Y. +config HISILICON_ERRATUM_161010801 + bool "HiSilicon erratum 161010801: Reserve HW MSI regions" + default y + help + On HiSilicon Hip06/Hip07 platforms, the SMMU v3 has to bypass the + GIC ITS doorbel msi address regions. This will make sure that ITS + doorbell address regions are reserved and excluded from iova + allocations. + + If unsure, say Y. endmenu diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e7a8a50..a33e339 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -663,6 +663,73 @@ void erratum_skip_prefetch_cmd(struct arm_smmu_device *smmu, void *arg) smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; } +#ifdef CONFIG_HISILICON_ERRATUM_161010801 +static void parse_hisi_csrt_msi(struct arm_smmu_device *smmu, + const struct acpi_iort_smmu_v3 *iort) + +{ + struct acpi_csrt_group *grp, *end; + struct acpi_table_csrt *csrt; + acpi_status status; + + status = acpi_get_table(ACPI_SIG_CSRT, 0, + (struct acpi_table_header **)&csrt); + if (ACPI_FAILURE(status)) { + dev_warn(smmu->dev, "HiSi CSRT table get failed: 0x%x\n", + status); + return; + } + + grp = (struct acpi_csrt_group *)(csrt + 1); + end = (struct acpi_csrt_group *)((void *)csrt + csrt->header.length); + + while (grp < end) { + if (grp->device_id == iort->model) { + /* + * We don't have the optional shared info for this grp + * and has only one resource descriptor with vendor + * defined msi region for this group. Go straight to + * vendor defined info. + */ + struct acpi_csrt_descriptor *desc = + (struct acpi_csrt_descriptor *)&grp[1]; + + /* + * HiSilicon CSRT vendor info. First 8 bytes gives smmu + * node base addr, next 8 bytes HW MSI reserve region + * addr and the remaining 4 byte the len. + */ + void *vendor = &desc[1]; + u64 base = (*(u64 *)vendor); + + if (base == iort->base_address && smmu->msi_region) { + /* Replace the default SW msi with HW msi */ + + smmu->msi_region->start = + *((u64 *)((u64 *)vendor+1)); + smmu->msi_region->length = + *((u32 *)((u64 *)vendor+2)); + smmu->msi_region->type = IOMMU_RESV_MSI; + dev_info(smmu->dev, + "HiSi msi addr 0x%pa size 0x%zx\n", + &smmu->msi_region->start, + smmu->msi_region->length); + return; + } + } + + grp = (struct acpi_csrt_group *)((void *)grp + grp->length); + } + +} +void erratum_hisi_resv_hw_msi(struct arm_smmu_device *smmu, void *arg) +{ + const struct acpi_iort_smmu_v3 *iort_smmu = arg; + + parse_hisi_csrt_msi(smmu, iort_smmu); +} +#endif + struct smmu_erratum_workaround { enum smmu_erratum_match_type match_type; const void *id; /* Indicate the Erratum ID */ @@ -686,6 +753,14 @@ static const struct smmu_erratum_workaround smmu_workarounds[] = { }, #endif +#ifdef CONFIG_HISILICON_ERRATUM_161010801 + { + .match_type = se_match_acpi_iort_model, + .id = (void *)ACPI_IORT_SMMU_HISILICON_HI161X, + .desc_str = "HiSilicon erratum 161010801", + .enable = erratum_hisi_resv_hw_msi, + }, +#endif { },