From patchwork Mon Jun 28 18:20:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1707C11F6B for ; Mon, 28 Jun 2021 18:21:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9E6F61C82 for ; Mon, 28 Jun 2021 18:21:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234318AbhF1SXY (ORCPT ); Mon, 28 Jun 2021 14:23:24 -0400 Received: from out28-195.mail.aliyun.com ([115.124.28.195]:58649 "EHLO out28-195.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233444AbhF1SXU (ORCPT ); Mon, 28 Jun 2021 14:23:20 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09420402|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00745146-0.000210352-0.992338; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:50 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 01/11] clk: JZ4780: Add function for disable the second core. Date: Tue, 29 Jun 2021 02:20:34 +0800 Message-Id: <1624904444-2618-2-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add "jz4780_core1_disable()" for disable the second core of JZ4780, prepare for later commits. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil --- Notes: v1->v2: Add Paul Cercueil's Reviewed-by. v2->v3: No change. v3->v4: No change. v4->v5: No change. drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index 0268d23..dcca74e 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw) return 0; } +static void jz4780_core1_disable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + unsigned long flags; + u32 lcr, clkgr1; + + spin_lock_irqsave(&cgu->lock, flags); + + lcr = readl(cgu->base + CGU_REG_LCR); + lcr |= LCR_PD_SCPU; + writel(lcr, cgu->base + CGU_REG_LCR); + + clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); + clkgr1 |= CLKGR1_CORE1; + writel(clkgr1, cgu->base + CGU_REG_CLKGR1); + + spin_unlock_irqrestore(&cgu->lock, flags); +} + static const struct clk_ops jz4780_core1_ops = { .enable = jz4780_core1_enable, + .disable = jz4780_core1_disable, }; static const s8 pll_od_encoding[16] = { From patchwork Mon Jun 28 18:20:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66C7BC11F65 for ; Mon, 28 Jun 2021 18:21:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5078361C7D for ; Mon, 28 Jun 2021 18:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234551AbhF1SX1 (ORCPT ); Mon, 28 Jun 2021 14:23:27 -0400 Received: from out28-125.mail.aliyun.com ([115.124.28.125]:60040 "EHLO out28-125.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233478AbhF1SXU (ORCPT ); Mon, 28 Jun 2021 14:23:20 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436541|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0195473-0.00039859-0.980054; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:51 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 02/11] clk: Ingenic: Adjust cgu code to make it compatible with I2S PLL. Date: Tue, 29 Jun 2021 02:20:35 +0800 Message-Id: <1624904444-2618-3-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org I2S PLL is different from the APLL/MPLL, which have no OD bits, no stable bit, but have parent clock selection bits, therefore, it is necessary to modify the CGU PLL correlation code to make it compatible with I2S PLL. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. drivers/clk/ingenic/cgu.c | 118 ++++++++++++++++++++++++++++++++++++++++------ drivers/clk/ingenic/cgu.h | 1 + 2 files changed, 104 insertions(+), 15 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 266c759..391bf50 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -76,6 +76,85 @@ ingenic_cgu_gate_set(struct ingenic_cgu *cgu, * PLL operations */ +static u8 ingenic_pll_get_parent(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + const struct ingenic_cgu_pll_info *pll_info; + u32 reg; + u8 i, hw_idx, idx = 0; + + BUG_ON(clk_info->type != CGU_CLK_PLL); + pll_info = &clk_info->pll; + + if (pll_info->mux_bits <= 0) + return 1; + + reg = readl(cgu->base + pll_info->reg); + hw_idx = (reg >> pll_info->mux_shift) & + GENMASK(pll_info->mux_bits - 1, 0); + + /* + * Convert the hardware index to the parent index by skipping + * over any -1's in the parents array. + */ + for (i = 0; i < hw_idx; i++) { + if (clk_info->parents[i] != -1) + idx++; + } + + return idx; +} + +static int ingenic_pll_set_parent(struct clk_hw *hw, u8 idx) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + const struct ingenic_cgu_pll_info *pll_info; + unsigned long flags; + u32 reg; + u8 curr_idx, hw_idx, num_poss; + + BUG_ON(clk_info->type != CGU_CLK_PLL); + pll_info = &clk_info->pll; + + if (pll_info->mux_bits <= 0) + return 0; + + /* + * Convert the parent index to the hardware index by adding + * 1 for any -1 in the parents array preceding the given + * index. That is, we want the index of idx'th entry in + * clk_info->parents which does not equal -1. + */ + hw_idx = curr_idx = 0; + num_poss = 1 << pll_info->mux_bits; + for (; hw_idx < num_poss; hw_idx++) { + if (clk_info->parents[hw_idx] == -1) + continue; + if (curr_idx == idx) + break; + curr_idx++; + } + + /* idx should always be a valid parent */ + BUG_ON(curr_idx != idx); + + spin_lock_irqsave(&cgu->lock, flags); + + /* write the register */ + reg = readl(cgu->base + pll_info->reg); + reg &= ~(GENMASK(pll_info->mux_bits - 1, 0) << pll_info->mux_shift); + reg |= hw_idx << pll_info->mux_shift; + writel(reg, cgu->base + pll_info->reg); + + spin_unlock_irqrestore(&cgu->lock, flags); + + return 0; +} + static unsigned long ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -96,8 +175,20 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) m += pll_info->m_offset; n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); n += pll_info->n_offset; - od_enc = ctl >> pll_info->od_shift; - od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + if (pll_info->od_encoding) { + od_enc = ctl >> pll_info->od_shift; + od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + for (od = 0; od < pll_info->od_max; od++) { + if (pll_info->od_encoding[od] == od_enc) + break; + } + BUG_ON(od == pll_info->od_max); + od++; + } else { + od = 1; + } if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -108,15 +199,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return parent_rate; } - for (od = 0; od < pll_info->od_max; od++) { - if (pll_info->od_encoding[od] == od_enc) - break; - } - BUG_ON(od == pll_info->od_max); - od++; - - return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, - n * od); + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, n * od); } static void @@ -215,13 +298,15 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); ctl |= (n - pll_info->n_offset) << pll_info->n_shift; - ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); - ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + if (pll_info->od_encoding) { + ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); + ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + } writel(ctl, cgu->base + pll_info->reg); /* If the PLL is enabled, verify that it's stable */ - if (ctl & BIT(pll_info->enable_bit)) + if ((pll_info->stable_bit >= 0) && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); spin_unlock_irqrestore(&cgu->lock, flags); @@ -292,6 +377,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) } static const struct clk_ops ingenic_pll_ops = { + .get_parent = ingenic_pll_get_parent, + .set_parent = ingenic_pll_set_parent, + .recalc_rate = ingenic_pll_recalc_rate, .round_rate = ingenic_pll_round_rate, .set_rate = ingenic_pll_set_rate, @@ -672,7 +760,7 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx) clk_init.flags |= CLK_SET_RATE_PARENT; } - if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) { + if (caps & (CGU_CLK_PLL | CGU_CLK_MUX | CGU_CLK_CUSTOM)) { clk_init.num_parents = 0; if (caps & CGU_CLK_MUX) diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index bfc2b9c..87d716e 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -48,6 +48,7 @@ struct ingenic_cgu_pll_info { unsigned reg; unsigned rate_multiplier; const s8 *od_encoding; + u8 mux_shift, mux_bits; u8 m_shift, m_bits, m_offset; u8 n_shift, n_bits, n_offset; u8 od_shift, od_bits, od_max; From patchwork Mon Jun 28 18:20:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95A00C11F64 for ; Mon, 28 Jun 2021 18:21:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80EB161C76 for ; Mon, 28 Jun 2021 18:21:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233956AbhF1SXX (ORCPT ); Mon, 28 Jun 2021 14:23:23 -0400 Received: from out28-2.mail.aliyun.com ([115.124.28.2]:41007 "EHLO out28-2.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232620AbhF1SXV (ORCPT ); Mon, 28 Jun 2021 14:23:21 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1171114|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0051153-0.000427568-0.994457; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:53 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 03/11] dt-bindings: clock: Add missing clocks for Ingenic SoCs. Date: Tue, 29 Jun 2021 02:20:36 +0800 Message-Id: <1624904444-2618-4-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC and the X1830 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Acked-by: Rob Herring --- Notes: v1->v2: 1.Add MACPHY and I2S for X1000, and add MACPHY for X1830. 2.Add Paul Cercueil's Reviewed-by and Rob Herring's Acked-by. v2->v3: No change. v3->v4: No change. v4->v5: Add CIM, AIC, DMIC for X1000, and add CIM, AIC, DMIC, I2S for X1830. include/dt-bindings/clock/x1000-cgu.h | 5 +++++ include/dt-bindings/clock/x1830-cgu.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index f187e07..3e79f36 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -50,5 +50,10 @@ #define X1000_CLK_PDMA 35 #define X1000_CLK_EXCLK_DIV512 36 #define X1000_CLK_RTC 37 +#define X1000_CLK_MACPHY 38 +#define X1000_CLK_CIM 39 +#define X1000_CLK_AIC 40 +#define X1000_CLK_DMIC 41 +#define X1000_CLK_I2S 42 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h index 8845537..8da2997 100644 --- a/include/dt-bindings/clock/x1830-cgu.h +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -53,5 +53,10 @@ #define X1830_CLK_OST 38 #define X1830_CLK_EXCLK_DIV512 39 #define X1830_CLK_RTC 40 +#define X1830_CLK_MACPHY 41 +#define X1830_CLK_CIM 42 +#define X1830_CLK_AIC 43 +#define X1830_CLK_DMIC 44 +#define X1830_CLK_I2S 45 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ From patchwork Mon Jun 28 18:20:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D66C11F67 for ; Mon, 28 Jun 2021 18:21:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BDC861C7D for ; Mon, 28 Jun 2021 18:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235012AbhF1SX2 (ORCPT ); Mon, 28 Jun 2021 14:23:28 -0400 Received: from out28-121.mail.aliyun.com ([115.124.28.121]:40685 "EHLO out28-121.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233658AbhF1SXW (ORCPT ); Mon, 28 Jun 2021 14:23:22 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1222889|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.00100954-1.46352e-05-0.998976; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047201; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:54 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 04/11] clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830. Date: Tue, 29 Jun 2021 02:20:37 +0800 Message-Id: <1624904444-2618-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org X1000 and X1830 have two MAC related clocks, one is MACPHY, which is controlled by MACCDR register, the other is MAC, which is controlled by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent). The original driver mistakenly mixed the two clocks together. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v2: New patch. v2->v3: No change. v3->v4: No change. v4->v5: No change. drivers/clk/ingenic/x1000-cgu.c | 11 ++++++++--- drivers/clk/ingenic/x1830-cgu.c | 11 ++++++++--- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 9aa20b5..53e5fe0 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -296,12 +296,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 31 }, }, - [X1000_CLK_MAC] = { - "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + [X1000_CLK_MACPHY] = { + "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_MACCDR, 31, 1 }, .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, - .gate = { CGU_REG_CLKGR, 25 }, }, [X1000_CLK_LCD] = { @@ -452,6 +451,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 21 }, }, + + [X1000_CLK_MAC] = { + "mac", CGU_CLK_GATE, + .parents = { X1000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR, 25 }, + }, }; static void __init x1000_cgu_init(struct device_node *np) diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index 950aee2..59342bc 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -270,13 +270,12 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .gate = { CGU_REG_CLKGR0, 31 }, }, - [X1830_CLK_MAC] = { - "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + [X1830_CLK_MACPHY] = { + "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, X1830_CLK_VPLL, X1830_CLK_EPLL }, .mux = { CGU_REG_MACCDR, 30, 2 }, .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, - .gate = { CGU_REG_CLKGR1, 4 }, }, [X1830_CLK_LCD] = { @@ -428,6 +427,12 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .gate = { CGU_REG_CLKGR1, 1 }, }, + [X1830_CLK_MAC] = { + "mac", CGU_CLK_GATE, + .parents = { X1830_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR1, 4 }, + }, + [X1830_CLK_OST] = { "ost", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, From patchwork Mon Jun 28 18:20:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 644A9C11F6E for ; Mon, 28 Jun 2021 18:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40C3C61C7E for ; Mon, 28 Jun 2021 18:21:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233854AbhF1SXb (ORCPT ); Mon, 28 Jun 2021 14:23:31 -0400 Received: from out28-170.mail.aliyun.com ([115.124.28.170]:45601 "EHLO out28-170.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233739AbhF1SXX (ORCPT ); Mon, 28 Jun 2021 14:23:23 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07437116|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0041116-0.000363272-0.995525; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:55 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 05/11] clk: Ingenic: Add missing clocks for Ingenic SoCs. Date: Tue, 29 Jun 2021 02:20:38 +0800 Message-Id: <1624904444-2618-6-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the X1830 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: Add I2S clock for X1000. v2->v3: Correct the comment in x1000-cgu.c, change it from "Custom (SoC-specific) OTG PHY" to "Custom (SoC-specific)", since there is more than just the "OTG PHY" clock. v3->v4: No change. v4->v5: 1.Change X1000's I2S clock to CGU_CLK_PLL as Paul Cercueil's suggestion 2.Add I2S clock for X1830. drivers/clk/ingenic/x1000-cgu.c | 88 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/ingenic/x1830-cgu.c | 90 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 178 insertions(+) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 53e5fe0..59b16a6 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -60,6 +60,54 @@ static struct ingenic_cgu *cgu; +static void x1000_i2s_calc_m_n(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + unsigned int delta, m, n; + u64 curr_delta, curr_m, curr_n; + + if ((parent_rate % rate == 0) && ((parent_rate / rate) > 1)) { + m = 1; + n = parent_rate / rate; + goto out; + } + + delta = rate; + + /* + * The length of M is 9 bits, its value must be between 1 and 511. + * The length of N is 13 bits, its value must be between 2 and 8191, + * and must not be less than 2 times of the value of M. + */ + for (curr_m = 511; curr_m >= 1; curr_m--) { + curr_n = parent_rate * curr_m; + curr_delta = do_div(curr_n, rate); + + if (curr_n < 2 * curr_m || curr_n > 8191) + continue; + + if (curr_delta == 0) + break; + + if (curr_delta < delta) { + m = curr_m; + n = curr_n; + delta = curr_delta; + } + } + +out: + *pm = m; + *pn = n; + + /* + * The I2S PLL does not have OD bits, so set the *pod to 1 to ensure + * that the ingenic_pll_calc() in cgu.c can run properly. + */ + *pod = 1; +} + static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -227,6 +275,27 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { }, }, + [X1000_CLK_I2S] = { + "i2s", CGU_CLK_PLL, + .parents = { X1000_CLK_EXCLK, X1000_CLK_SCLKA, -1, X1000_CLK_MPLL }, + .pll = { + .reg = CGU_REG_I2SCDR, + .rate_multiplier = 1, + .mux_shift = 30, + .mux_bits = 2, + .m_shift = 13, + .m_bits = 9, + .m_offset = 0, + .n_shift = 0, + .n_bits = 13, + .n_offset = 0, + .bypass_bit = -1, + .enable_bit = 29, + .stable_bit = -1, + .calc_m_n_od = x1000_i2s_calc_m_n, + }, + }, + /* Custom (SoC-specific) OTG PHY */ [X1000_CLK_OTGPHY] = { @@ -359,6 +428,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .mux = { CGU_REG_SSICDR, 30, 1 }, }, + [X1000_CLK_CIM] = { + "cim", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .mux = { CGU_REG_CIMCDR, 31, 1 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, 29, 28, 27 }, + }, + [X1000_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { X1000_CLK_EXCLK }, @@ -410,6 +486,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 9 }, }, + [X1000_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, @@ -428,6 +510,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 16 }, }, + [X1000_CLK_DMIC] = { + "dmic", CGU_CLK_GATE, + .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + [X1000_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index 59342bc..cfb0314 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -54,6 +54,54 @@ static struct ingenic_cgu *cgu; +static void x1830_i2s_calc_m_n(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + unsigned int delta, m, n; + u64 curr_delta, curr_m, curr_n; + + if ((parent_rate % rate == 0) && ((parent_rate / rate) > 1)) { + m = 1; + n = parent_rate / rate; + goto out; + } + + delta = rate; + + /* + * The length of M is 9 bits, its value must be between 1 and 511. + * The length of N is 20 bits, its value must be between 2 and 1048575, + * and must not be less than 2 times of the value of M. + */ + for (curr_m = 511; curr_m >= 1; curr_m--) { + curr_n = parent_rate * curr_m; + curr_delta = do_div(curr_n, rate); + + if (curr_n < 2 * curr_m || curr_n > 1048575) + continue; + + if (curr_delta == 0) + break; + + if (curr_delta < delta) { + m = curr_m; + n = curr_n; + delta = curr_delta; + } + } + +out: + *pm = m; + *pn = n; + + /* + * The I2S PLL does not have OD bits, so set the *pod to 1 to ensure + * that the ingenic_pll_calc() in cgu.c can run properly. + */ + *pod = 1; +} + static int x1830_usb_phy_enable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; @@ -201,6 +249,28 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { }, }, + [X1830_CLK_I2S] = { + "i2s", CGU_CLK_PLL, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .pll = { + .reg = CGU_REG_I2SCDR, + .rate_multiplier = 1, + .mux_shift = 30, + .mux_bits = 2, + .m_shift = 20, + .m_bits = 9, + .m_offset = 0, + .n_shift = 0, + .n_bits = 20, + .n_offset = 0, + .bypass_bit = -1, + .enable_bit = 29, + .stable_bit = -1, + .calc_m_n_od = x1830_i2s_calc_m_n, + }, + }, + /* Custom (SoC-specific) OTG PHY */ [X1830_CLK_OTGPHY] = { @@ -328,6 +398,14 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .mux = { CGU_REG_SSICDR, 29, 1 }, }, + [X1830_CLK_CIM] = { + "cim", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_CIMCDR, 30, 2 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, 29, 28, 27 }, + }, + [X1830_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { X1830_CLK_EXCLK }, @@ -385,6 +463,18 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { .gate = { CGU_REG_CLKGR0, 9 }, }, + [X1830_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 11 }, + }, + + [X1830_CLK_DMIC] = { + "dmic", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 12 }, + }, + [X1830_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, From patchwork Mon Jun 28 18:20:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4304DC11F7C for ; Mon, 28 Jun 2021 18:21:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27D8B61C7C for ; Mon, 28 Jun 2021 18:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236004AbhF1SXe (ORCPT ); Mon, 28 Jun 2021 14:23:34 -0400 Received: from out28-49.mail.aliyun.com ([115.124.28.49]:48553 "EHLO out28-49.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234329AbhF1SX1 (ORCPT ); Mon, 28 Jun 2021 14:23:27 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07608247|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0330205-0.000718331-0.966261; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047188; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:56 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 06/11] clk: Ingenic: Clean up and reformat the code. Date: Tue, 29 Jun 2021 02:20:39 +0800 Message-Id: <1624904444-2618-7-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 1.When the clock does not have "CGU_CLK_MUX", the 2/3/4 bits in parents do not need to be filled with -1. When the clock have a "CGU_CLK_MUX" has only one bit, the 3/4 bits of parents do not need to be filled with -1. Clean up these unnecessary -1 from all the xxxx-cgu.c files. 2.Reformat code, add missing blank lines, remove unnecessary commas and tabs, and align code. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: Remove unnecessary -1 and commas. v2->v3: No change. v3->v4: 1.The -1 used for placeholders on the unused bits of the parents in the custom clock should not be removed. 2.Move "JZ4780_CLK_CORE1" from the "Gate-only clocks" class to the "Custom (SoC-specific)" class, because it belongs to the custom clock. v4->v5: No change. drivers/clk/ingenic/jz4725b-cgu.c | 48 +++++++------- drivers/clk/ingenic/jz4740-cgu.c | 48 +++++++------- drivers/clk/ingenic/jz4760-cgu.c | 106 ++++++++++++++++++++----------- drivers/clk/ingenic/jz4770-cgu.c | 83 +++++++++++++------------ drivers/clk/ingenic/jz4780-cgu.c | 127 +++++++++++++++++++------------------- drivers/clk/ingenic/x1000-cgu.c | 116 +++++++++++++++++----------------- drivers/clk/ingenic/x1830-cgu.c | 112 ++++++++++++++++----------------- 7 files changed, 338 insertions(+), 302 deletions(-) diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index 5154b0c..f1a23e1 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -17,7 +17,7 @@ /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 -#define CGU_REG_LCR 0x04 +#define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 #define CGU_REG_CLKGR 0x20 #define CGU_REG_OPCR 0x24 @@ -28,7 +28,7 @@ #define CGU_REG_CIMCDR 0x78 /* bits within the LCR register */ -#define LCR_SLEEP BIT(0) +#define LCR_SLEEP BIT(0) static struct ingenic_cgu *cgu; @@ -78,7 +78,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, - .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL }, .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4725b_cgu_pll_half_div_table, @@ -87,7 +87,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_CCLK] = { "cclk", CGU_CLK_DIV, - .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, @@ -96,7 +96,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_HCLK] = { "hclk", CGU_CLK_DIV, - .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, @@ -105,7 +105,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_PCLK] = { "pclk", CGU_CLK_DIV, - .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, @@ -114,7 +114,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_MCLK] = { "mclk", CGU_CLK_DIV, - .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, @@ -123,7 +123,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_IPU] = { "ipu", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, @@ -133,14 +133,14 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_LCD] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL_HALF }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 9 }, }, [JZ4725B_CLK_I2S] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, + .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF }, .mux = { CGU_REG_CPCCR, 31, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 6 }, @@ -148,7 +148,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_SPI] = { "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 }, + .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 4 }, @@ -156,13 +156,13 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_MMC_MUX] = { "mmc_mux", CGU_CLK_DIV, - .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PLL_HALF }, .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, }, [JZ4725B_CLK_UDC] = { "udc", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, + .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, }, @@ -171,55 +171,55 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_UART] = { "uart", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4725B_CLK_EXT }, .gate = { CGU_REG_CLKGR, 0 }, }, [JZ4725B_CLK_DMA] = { "dma", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4725B_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 12 }, }, [JZ4725B_CLK_ADC] = { "adc", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4725B_CLK_EXT }, .gate = { CGU_REG_CLKGR, 7 }, }, [JZ4725B_CLK_I2C] = { "i2c", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4725B_CLK_EXT }, .gate = { CGU_REG_CLKGR, 3 }, }, [JZ4725B_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4725B_CLK_EXT }, .gate = { CGU_REG_CLKGR, 5 }, }, [JZ4725B_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, + .parents = { JZ4725B_CLK_MMC_MUX }, .gate = { CGU_REG_CLKGR, 6 }, }, [JZ4725B_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, + .parents = { JZ4725B_CLK_MMC_MUX }, .gate = { CGU_REG_CLKGR, 16 }, }, [JZ4725B_CLK_BCH] = { "bch", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 }, + .parents = { JZ4725B_CLK_MCLK/* not sure */ }, .gate = { CGU_REG_CLKGR, 11 }, }, [JZ4725B_CLK_TCU] = { "tcu", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 }, + .parents = { JZ4725B_CLK_EXT/* not sure */ }, .gate = { CGU_REG_CLKGR, 1 }, }, @@ -233,13 +233,13 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_RTC] = { "rtc", CGU_CLK_MUX, - .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 }, + .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K }, .mux = { CGU_REG_OPCR, 2, 1}, }, [JZ4725B_CLK_UDC_PHY] = { "udc_phy", CGU_CLK_GATE, - .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4725B_CLK_EXT }, .gate = { CGU_REG_OPCR, 6, true }, }, }; diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index cd878f0..a4b7683 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -18,10 +18,10 @@ /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 -#define CGU_REG_LCR 0x04 +#define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 #define CGU_REG_CLKGR 0x20 -#define CGU_REG_SCR 0x24 +#define CGU_REG_SCR 0x24 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 @@ -40,10 +40,10 @@ #define PLLCTL_ENABLE (1 << 8) /* bits within the LCR register */ -#define LCR_SLEEP (1 << 0) +#define LCR_SLEEP (1 << 0) /* bits within the CLKGR register */ -#define CLKGR_UDC (1 << 11) +#define CLKGR_UDC (1 << 11) static struct ingenic_cgu *cgu; @@ -93,7 +93,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, - .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL }, .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4740_cgu_pll_half_div_table, @@ -102,7 +102,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_CCLK] = { "cclk", CGU_CLK_DIV, - .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, @@ -111,7 +111,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_HCLK] = { "hclk", CGU_CLK_DIV, - .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, @@ -120,7 +120,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_PCLK] = { "pclk", CGU_CLK_DIV, - .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, @@ -129,7 +129,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_MCLK] = { "mclk", CGU_CLK_DIV, - .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, @@ -138,7 +138,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_LCD] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL_HALF }, .div = { CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, @@ -148,13 +148,13 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_LCD_PCLK] = { "lcd_pclk", CGU_CLK_DIV, - .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL_HALF }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, }, [JZ4740_CLK_I2S] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, + .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF }, .mux = { CGU_REG_CPCCR, 31, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 6 }, @@ -162,7 +162,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_SPI] = { "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 }, + .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 4 }, @@ -170,21 +170,21 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_MMC] = { "mmc", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL_HALF }, .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 7 }, }, [JZ4740_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, + .parents = { JZ4740_CLK_PLL_HALF }, .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 14 }, }, [JZ4740_CLK_UDC] = { "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, + .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, .gate = { CGU_REG_SCR, 6, true }, @@ -194,49 +194,49 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4740_CLK_EXT }, .gate = { CGU_REG_CLKGR, 0 }, }, [JZ4740_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4740_CLK_EXT }, .gate = { CGU_REG_CLKGR, 15 }, }, [JZ4740_CLK_DMA] = { "dma", CGU_CLK_GATE, - .parents = { JZ4740_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4740_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 12 }, }, [JZ4740_CLK_IPU] = { "ipu", CGU_CLK_GATE, - .parents = { JZ4740_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4740_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 13 }, }, [JZ4740_CLK_ADC] = { "adc", CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4740_CLK_EXT }, .gate = { CGU_REG_CLKGR, 8 }, }, [JZ4740_CLK_I2C] = { "i2c", CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4740_CLK_EXT }, .gate = { CGU_REG_CLKGR, 3 }, }, [JZ4740_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4740_CLK_EXT }, .gate = { CGU_REG_CLKGR, 5 }, }, [JZ4740_CLK_TCU] = { "tcu", CGU_CLK_GATE, - .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .parents = { JZ4740_CLK_EXT }, .gate = { CGU_REG_CLKGR, 1 }, }, }; diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c index a45327c..0629ce7 100644 --- a/drivers/clk/ingenic/jz4760-cgu.c +++ b/drivers/clk/ingenic/jz4760-cgu.c @@ -23,7 +23,7 @@ * CPM registers offset address definition */ #define CGU_REG_CPCCR 0x00 -#define CGU_REG_LCR 0x04 +#define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR0 0x10 #define CGU_REG_CLKGR0 0x20 #define CGU_REG_OPCR 0x24 @@ -98,7 +98,7 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_PLL0] = { "pll0", CGU_CLK_PLL, - .parents = { JZ4760_CLK_EXT }, + .parents = { JZ4760_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR0, .rate_multiplier = 1, @@ -123,7 +123,7 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_PLL1] = { /* TODO: PLL1 can depend on PLL0 */ "pll1", CGU_CLK_PLL, - .parents = { JZ4760_CLK_EXT }, + .parents = { JZ4760_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR1, .rate_multiplier = 1, @@ -148,47 +148,52 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_CCLK] = { "cclk", CGU_CLK_DIV, - .parents = { JZ4760_CLK_PLL0, }, + .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, + [JZ4760_CLK_HCLK] = { "hclk", CGU_CLK_DIV, - .parents = { JZ4760_CLK_PLL0, }, + .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, + [JZ4760_CLK_SCLK] = { "sclk", CGU_CLK_DIV, - .parents = { JZ4760_CLK_PLL0, }, + .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, + [JZ4760_CLK_H2CLK] = { "h2clk", CGU_CLK_DIV, - .parents = { JZ4760_CLK_PLL0, }, + .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, + [JZ4760_CLK_MCLK] = { "mclk", CGU_CLK_DIV, - .parents = { JZ4760_CLK_PLL0, }, + .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, + [JZ4760_CLK_PCLK] = { "pclk", CGU_CLK_DIV, - .parents = { JZ4760_CLK_PLL0, }, + .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, @@ -210,39 +215,44 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_UHCCDR, 31, 1 }, .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 24 }, }, + [JZ4760_CLK_GPU] = { "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_GPUCDR, 31, 1 }, .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 9 }, }, + [JZ4760_CLK_LPCLK_DIV] = { "lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX, - .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_LPCDR, 29, 1 }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, }, + [JZ4760_CLK_TVE] = { "tve", CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT }, .mux = { CGU_REG_LPCDR, 31, 1 }, .gate = { CGU_REG_CLKGR0, 27 }, }, + [JZ4760_CLK_LPCLK] = { "lpclk", CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, }, + .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE }, .mux = { CGU_REG_LPCDR, 30, 1 }, .gate = { CGU_REG_CLKGR0, 28 }, }, + [JZ4760_CLK_GPS] = { "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, + .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_GPSCDR, 31, 1 }, .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 22 }, @@ -258,6 +268,7 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) }, .gate = { CGU_REG_CLKGR1, 8 }, }, + [JZ4760_CLK_I2S] = { "i2s", CGU_CLK_DIV | CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT, -1, @@ -265,6 +276,7 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { .mux = { CGU_REG_I2SCDR, 30, 2 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) }, }, + [JZ4760_CLK_OTG] = { "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT, -1, @@ -277,13 +289,14 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { /* Those divided clocks can connect to EXT or PLL0 */ [JZ4760_CLK_MMC_MUX] = { "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, }, + .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF }, .mux = { CGU_REG_MSCCDR, 31, 1 }, .div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) }, }, + [JZ4760_CLK_SSI_MUX] = { "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX, - .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, }, + .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) }, }, @@ -300,94 +313,112 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, - .parents = { JZ4760_CLK_SSI_MUX, }, + .parents = { JZ4760_CLK_SSI_MUX }, .gate = { CGU_REG_CLKGR0, 4 }, }, + [JZ4760_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, - .parents = { JZ4760_CLK_SSI_MUX, }, + .parents = { JZ4760_CLK_SSI_MUX }, .gate = { CGU_REG_CLKGR0, 19 }, }, + [JZ4760_CLK_SSI2] = { "ssi2", CGU_CLK_GATE, - .parents = { JZ4760_CLK_SSI_MUX, }, + .parents = { JZ4760_CLK_SSI_MUX }, .gate = { CGU_REG_CLKGR0, 20 }, }, + [JZ4760_CLK_DMA] = { "dma", CGU_CLK_GATE, - .parents = { JZ4760_CLK_H2CLK, }, + .parents = { JZ4760_CLK_H2CLK }, .gate = { CGU_REG_CLKGR0, 21 }, }, + [JZ4760_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 5 }, }, + [JZ4760_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 6 }, }, + [JZ4760_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 15 }, }, + [JZ4760_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 16 }, }, + [JZ4760_CLK_UART2] = { "uart2", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 17 }, }, + [JZ4760_CLK_UART3] = { "uart3", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 18 }, }, + [JZ4760_CLK_IPU] = { "ipu", CGU_CLK_GATE, - .parents = { JZ4760_CLK_HCLK, }, + .parents = { JZ4760_CLK_HCLK }, .gate = { CGU_REG_CLKGR0, 29 }, }, + [JZ4760_CLK_ADC] = { "adc", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 14 }, }, + [JZ4760_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { JZ4760_CLK_EXT, }, + .parents = { JZ4760_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 8 }, }, + [JZ4760_CLK_VPU] = { "vpu", CGU_CLK_GATE, - .parents = { JZ4760_CLK_HCLK, }, + .parents = { JZ4760_CLK_HCLK }, .gate = { CGU_REG_LCR, 30, false, 150 }, }, + [JZ4760_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, - .parents = { JZ4760_CLK_MMC_MUX, }, + .parents = { JZ4760_CLK_MMC_MUX }, .gate = { CGU_REG_CLKGR0, 3 }, }, + [JZ4760_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, - .parents = { JZ4760_CLK_MMC_MUX, }, + .parents = { JZ4760_CLK_MMC_MUX }, .gate = { CGU_REG_CLKGR0, 11 }, }, + [JZ4760_CLK_MMC2] = { "mmc2", CGU_CLK_GATE, - .parents = { JZ4760_CLK_MMC_MUX, }, + .parents = { JZ4760_CLK_MMC_MUX }, .gate = { CGU_REG_CLKGR0, 12 }, }, + [JZ4760_CLK_UHC_PHY] = { "uhc_phy", CGU_CLK_GATE, - .parents = { JZ4760_CLK_UHC, }, + .parents = { JZ4760_CLK_UHC }, .gate = { CGU_REG_OPCR, 5 }, }, + [JZ4760_CLK_OTG_PHY] = { "usb_phy", CGU_CLK_GATE, .parents = { JZ4760_CLK_OTG }, @@ -400,10 +431,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { .parents = { JZ4760_CLK_EXT }, .fixdiv = { 512 }, }, + [JZ4760_CLK_RTC] = { "rtc", CGU_CLK_MUX, - .parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, }, - .mux = { CGU_REG_OPCR, 2, 1}, + .parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K }, + .mux = { CGU_REG_OPCR, 2, 1 }, }, }; diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 2321742..315caa0 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -19,7 +19,7 @@ * CPM registers offset address definition */ #define CGU_REG_CPCCR 0x00 -#define CGU_REG_LCR 0x04 +#define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR0 0x10 #define CGU_REG_CLKGR0 0x20 #define CGU_REG_OPCR 0x24 @@ -41,7 +41,7 @@ #define CGU_REG_BCHCDR 0xAC /* bits within the OPCR register */ -#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ +#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ /* bits within the USBPCR1 register */ #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ @@ -55,6 +55,7 @@ static int jz4770_uhc_phy_enable(struct clk_hw *hw) writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr); writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1); + return 0; } @@ -101,7 +102,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_PLL0] = { "pll0", CGU_CLK_PLL, - .parents = { JZ4770_CLK_EXT }, + .parents = { JZ4770_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR0, .rate_multiplier = 1, @@ -125,7 +126,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_PLL1] = { /* TODO: PLL1 can depend on PLL0 */ "pll1", CGU_CLK_PLL, - .parents = { JZ4770_CLK_EXT }, + .parents = { JZ4770_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR1, .rate_multiplier = 1, @@ -149,7 +150,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_CCLK] = { "cclk", CGU_CLK_DIV, - .parents = { JZ4770_CLK_PLL0, }, + .parents = { JZ4770_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, @@ -157,7 +158,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { }, [JZ4770_CLK_H0CLK] = { "h0clk", CGU_CLK_DIV, - .parents = { JZ4770_CLK_PLL0, }, + .parents = { JZ4770_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, @@ -165,7 +166,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { }, [JZ4770_CLK_H1CLK] = { "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4770_CLK_PLL0, }, + .parents = { JZ4770_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, @@ -174,7 +175,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { }, [JZ4770_CLK_H2CLK] = { "h2clk", CGU_CLK_DIV, - .parents = { JZ4770_CLK_PLL0, }, + .parents = { JZ4770_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, @@ -182,7 +183,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { }, [JZ4770_CLK_C1CLK] = { "c1clk", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4770_CLK_PLL0, }, + .parents = { JZ4770_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, @@ -191,7 +192,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { }, [JZ4770_CLK_PCLK] = { "pclk", CGU_CLK_DIV, - .parents = { JZ4770_CLK_PLL0, }, + .parents = { JZ4770_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, @@ -202,63 +203,63 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_MMC0_MUX] = { "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_MSC0CDR, 30, 1 }, .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 }, .gate = { CGU_REG_MSC0CDR, 31 }, }, [JZ4770_CLK_MMC1_MUX] = { "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_MSC1CDR, 30, 1 }, .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 }, .gate = { CGU_REG_MSC1CDR, 31 }, }, [JZ4770_CLK_MMC2_MUX] = { "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_MSC2CDR, 30, 1 }, .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 }, .gate = { CGU_REG_MSC2CDR, 31 }, }, [JZ4770_CLK_CIM] = { "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_CIMCDR, 31, 1 }, .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 26 }, }, [JZ4770_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_UHCCDR, 29, 1 }, .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 24 }, }, [JZ4770_CLK_GPU] = { "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_GPUCDR, 31, 1 }, .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 9 }, }, [JZ4770_CLK_BCH] = { "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_BCHCDR, 31, 1 }, .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 1 }, }, [JZ4770_CLK_LPCLK_MUX] = { "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_LPCDR, 29, 1 }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 28 }, }, [JZ4770_CLK_GPS] = { "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, - .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, + .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_GPSCDR, 31, 1 }, .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 22 }, @@ -301,107 +302,107 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, - .parents = { JZ4770_CLK_SSI_MUX, }, + .parents = { JZ4770_CLK_SSI_MUX }, .gate = { CGU_REG_CLKGR0, 4 }, }, [JZ4770_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, - .parents = { JZ4770_CLK_SSI_MUX, }, + .parents = { JZ4770_CLK_SSI_MUX }, .gate = { CGU_REG_CLKGR0, 19 }, }, [JZ4770_CLK_SSI2] = { "ssi2", CGU_CLK_GATE, - .parents = { JZ4770_CLK_SSI_MUX, }, + .parents = { JZ4770_CLK_SSI_MUX }, .gate = { CGU_REG_CLKGR0, 20 }, }, [JZ4770_CLK_PCM0] = { "pcm0", CGU_CLK_GATE, - .parents = { JZ4770_CLK_PCM_MUX, }, + .parents = { JZ4770_CLK_PCM_MUX }, .gate = { CGU_REG_CLKGR1, 8 }, }, [JZ4770_CLK_PCM1] = { "pcm1", CGU_CLK_GATE, - .parents = { JZ4770_CLK_PCM_MUX, }, + .parents = { JZ4770_CLK_PCM_MUX }, .gate = { CGU_REG_CLKGR1, 10 }, }, [JZ4770_CLK_DMA] = { "dma", CGU_CLK_GATE, - .parents = { JZ4770_CLK_H2CLK, }, + .parents = { JZ4770_CLK_H2CLK }, .gate = { CGU_REG_CLKGR0, 21 }, }, [JZ4770_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 5 }, }, [JZ4770_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 6 }, }, [JZ4770_CLK_I2C2] = { "i2c2", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR1, 15 }, }, [JZ4770_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 15 }, }, [JZ4770_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 16 }, }, [JZ4770_CLK_UART2] = { "uart2", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 17 }, }, [JZ4770_CLK_UART3] = { "uart3", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 18 }, }, [JZ4770_CLK_IPU] = { "ipu", CGU_CLK_GATE, - .parents = { JZ4770_CLK_H0CLK, }, + .parents = { JZ4770_CLK_H0CLK }, .gate = { CGU_REG_CLKGR0, 29 }, }, [JZ4770_CLK_ADC] = { "adc", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 14 }, }, [JZ4770_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { JZ4770_CLK_EXT, }, + .parents = { JZ4770_CLK_EXT }, .gate = { CGU_REG_CLKGR0, 8 }, }, [JZ4770_CLK_AUX] = { "aux", CGU_CLK_GATE, - .parents = { JZ4770_CLK_C1CLK, }, + .parents = { JZ4770_CLK_C1CLK }, .gate = { CGU_REG_CLKGR1, 14 }, }, [JZ4770_CLK_VPU] = { "vpu", CGU_CLK_GATE, - .parents = { JZ4770_CLK_H1CLK, }, + .parents = { JZ4770_CLK_H1CLK }, .gate = { CGU_REG_LCR, 30, false, 150 }, }, [JZ4770_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, - .parents = { JZ4770_CLK_MMC0_MUX, }, + .parents = { JZ4770_CLK_MMC0_MUX }, .gate = { CGU_REG_CLKGR0, 3 }, }, [JZ4770_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, - .parents = { JZ4770_CLK_MMC1_MUX, }, + .parents = { JZ4770_CLK_MMC1_MUX }, .gate = { CGU_REG_CLKGR0, 11 }, }, [JZ4770_CLK_MMC2] = { "mmc2", CGU_CLK_GATE, - .parents = { JZ4770_CLK_MMC2_MUX, }, + .parents = { JZ4770_CLK_MMC2_MUX }, .gate = { CGU_REG_CLKGR0, 12 }, }, [JZ4770_CLK_OTG_PHY] = { @@ -426,7 +427,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_RTC] = { "rtc", CGU_CLK_MUX, - .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, }, + .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K }, .mux = { CGU_REG_OPCR, 2, 1}, }, }; diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index dcca74e..94bc76b 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -178,6 +178,7 @@ static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); spin_unlock_irqrestore(&cgu->lock, flags); + return 0; } @@ -188,6 +189,7 @@ static int jz4780_otg_phy_enable(struct clk_hw *hw) writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); + return 0; } @@ -215,9 +217,9 @@ static const struct clk_ops jz4780_otg_phy_ops = { .round_rate = jz4780_otg_phy_round_rate, .set_rate = jz4780_otg_phy_set_rate, - .enable = jz4780_otg_phy_enable, - .disable = jz4780_otg_phy_disable, - .is_enabled = jz4780_otg_phy_is_enabled, + .enable = jz4780_otg_phy_enable, + .disable = jz4780_otg_phy_disable, + .is_enabled = jz4780_otg_phy_is_enabled, }; static int jz4780_core1_enable(struct clk_hw *hw) @@ -336,11 +338,17 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { #undef DEF_PLL - /* Custom (SoC-specific) OTG PHY */ + /* Custom (SoC-specific) */ + + [JZ4780_CLK_CORE1] = { + "core1", CGU_CLK_CUSTOM, + .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, + .custom = { &jz4780_core1_ops }, + }, [JZ4780_CLK_OTGPHY] = { "otg_phy", CGU_CLK_CUSTOM, - .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 }, + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .custom = { &jz4780_otg_phy_ops }, }, @@ -362,13 +370,13 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_CPU] = { "cpu", CGU_CLK_DIV, - .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_CPUMUX }, .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 }, }, [JZ4780_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, - .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_CPUMUX }, .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 }, }, @@ -389,13 +397,13 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, - .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_AHB2PMUX }, .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 }, }, [JZ4780_CLK_PCLK] = { "pclk", CGU_CLK_DIV, - .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_AHB2PMUX }, .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 }, }, @@ -417,14 +425,14 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_I2SPLL] = { "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 }, + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL }, .mux = { CGU_REG_I2SCDR, 30, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 }, }, [JZ4780_CLK_I2S] = { "i2s", CGU_CLK_MUX, - .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL }, .mux = { CGU_REG_I2SCDR, 31, 1 }, }, @@ -452,21 +460,21 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_MSCMUX }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 3 }, }, [JZ4780_CLK_MSC1] = { "msc1", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_MSCMUX }, .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 11 }, }, [JZ4780_CLK_MSC2] = { "msc2", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, + .parents = { JZ4780_CLK_MSCMUX }, .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 12 }, }, @@ -482,20 +490,20 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL }, .mux = { CGU_REG_SSICDR, 30, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, }, [JZ4780_CLK_SSI] = { "ssi", CGU_CLK_MUX, - .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL }, .mux = { CGU_REG_SSICDR, 31, 1 }, }, [JZ4780_CLK_CIMMCLK] = { "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL }, .mux = { CGU_REG_CIMCDR, 31, 1 }, .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 }, }, @@ -510,7 +518,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_PCM] = { "pcm", CGU_CLK_MUX | CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL }, .mux = { CGU_REG_PCMCDR, 31, 1 }, .gate = { CGU_REG_CLKGR1, 3 }, }, @@ -558,238 +566,231 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_NEMC] = { "nemc", CGU_CLK_GATE, - .parents = { JZ4780_CLK_AHB2, -1, -1, -1 }, + .parents = { JZ4780_CLK_AHB2 }, .gate = { CGU_REG_CLKGR0, 0 }, }, [JZ4780_CLK_OTG0] = { "otg0", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 2 }, }, [JZ4780_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, - .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, + .parents = { JZ4780_CLK_SSI }, .gate = { CGU_REG_CLKGR0, 4 }, }, [JZ4780_CLK_SMB0] = { "smb0", CGU_CLK_GATE, - .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 5 }, }, [JZ4780_CLK_SMB1] = { "smb1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 6 }, }, [JZ4780_CLK_SCC] = { "scc", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 7 }, }, [JZ4780_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 8 }, }, [JZ4780_CLK_TSSI0] = { "tssi0", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 9 }, }, [JZ4780_CLK_OWI] = { "owi", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 10 }, }, [JZ4780_CLK_KBC] = { "kbc", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 13 }, }, [JZ4780_CLK_SADC] = { "sadc", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 14 }, }, [JZ4780_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 15 }, }, [JZ4780_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 16 }, }, [JZ4780_CLK_UART2] = { "uart2", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 17 }, }, [JZ4780_CLK_UART3] = { "uart3", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 18 }, }, [JZ4780_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, + .parents = { JZ4780_CLK_SSI }, .gate = { CGU_REG_CLKGR0, 19 }, }, [JZ4780_CLK_SSI2] = { "ssi2", CGU_CLK_GATE, - .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, + .parents = { JZ4780_CLK_SSI }, .gate = { CGU_REG_CLKGR0, 20 }, }, [JZ4780_CLK_PDMA] = { "pdma", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 21 }, }, [JZ4780_CLK_GPS] = { "gps", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 22 }, }, [JZ4780_CLK_MAC] = { "mac", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 23 }, }, [JZ4780_CLK_SMB2] = { "smb2", CGU_CLK_GATE, - .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 24 }, }, [JZ4780_CLK_CIM] = { "cim", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 26 }, }, [JZ4780_CLK_LCD] = { "lcd", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 28 }, }, [JZ4780_CLK_TVE] = { "tve", CGU_CLK_GATE, - .parents = { JZ4780_CLK_LCD, -1, -1, -1 }, + .parents = { JZ4780_CLK_LCD }, .gate = { CGU_REG_CLKGR0, 27 }, }, [JZ4780_CLK_IPU] = { "ipu", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 29 }, }, [JZ4780_CLK_DDR0] = { "ddr0", CGU_CLK_GATE, - .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, + .parents = { JZ4780_CLK_DDR }, .gate = { CGU_REG_CLKGR0, 30 }, }, [JZ4780_CLK_DDR1] = { "ddr1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, + .parents = { JZ4780_CLK_DDR }, .gate = { CGU_REG_CLKGR0, 31 }, }, [JZ4780_CLK_SMB3] = { "smb3", CGU_CLK_GATE, - .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_PCLK }, .gate = { CGU_REG_CLKGR1, 0 }, }, [JZ4780_CLK_TSSI1] = { "tssi1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 1 }, }, [JZ4780_CLK_COMPRESS] = { "compress", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 5 }, }, [JZ4780_CLK_AIC1] = { "aic1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 6 }, }, [JZ4780_CLK_GPVLC] = { "gpvlc", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 7 }, }, [JZ4780_CLK_OTG1] = { "otg1", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 8 }, }, [JZ4780_CLK_UART4] = { "uart4", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 10 }, }, [JZ4780_CLK_AHBMON] = { "ahb_mon", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 11 }, }, [JZ4780_CLK_SMB4] = { "smb4", CGU_CLK_GATE, - .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_PCLK }, .gate = { CGU_REG_CLKGR1, 12 }, }, [JZ4780_CLK_DES] = { "des", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 13 }, }, [JZ4780_CLK_X2D] = { "x2d", CGU_CLK_GATE, - .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, + .parents = { JZ4780_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 14 }, }, - - [JZ4780_CLK_CORE1] = { - "core1", CGU_CLK_CUSTOM, - .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, - .custom = { &jz4780_core1_ops }, - }, - }; static void __init jz4780_cgu_init(struct device_node *np) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 59b16a6..41b2c2e 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -15,38 +15,38 @@ #include "pm.h" /* CGU register offsets */ -#define CGU_REG_CPCCR 0x00 -#define CGU_REG_APLL 0x10 -#define CGU_REG_MPLL 0x14 -#define CGU_REG_CLKGR 0x20 -#define CGU_REG_OPCR 0x24 -#define CGU_REG_DDRCDR 0x2c -#define CGU_REG_USBPCR 0x3c -#define CGU_REG_USBPCR1 0x48 -#define CGU_REG_USBCDR 0x50 -#define CGU_REG_MACCDR 0x54 -#define CGU_REG_I2SCDR 0x60 -#define CGU_REG_LPCDR 0x64 -#define CGU_REG_MSC0CDR 0x68 -#define CGU_REG_I2SCDR1 0x70 -#define CGU_REG_SSICDR 0x74 -#define CGU_REG_CIMCDR 0x7c -#define CGU_REG_PCMCDR 0x84 -#define CGU_REG_MSC1CDR 0xa4 -#define CGU_REG_CMP_INTR 0xb0 -#define CGU_REG_CMP_INTRE 0xb4 -#define CGU_REG_DRCG 0xd0 -#define CGU_REG_CPCSR 0xd4 -#define CGU_REG_PCMCDR1 0xe0 -#define CGU_REG_MACPHYC 0xe8 +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_APLL 0x10 +#define CGU_REG_MPLL 0x14 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_USBCDR 0x50 +#define CGU_REG_MACCDR 0x54 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_I2SCDR1 0x70 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7c +#define CGU_REG_PCMCDR 0x84 +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_PCMCDR1 0xe0 +#define CGU_REG_MACPHYC 0xe8 /* bits within the OPCR register */ -#define OPCR_SPENDN0 BIT(7) -#define OPCR_SPENDN1 BIT(6) +#define OPCR_SPENDN0 BIT(7) +#define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ -#define USBPCR_SIDDQ BIT(21) -#define USBPCR_OTG_DISABLE BIT(20) +#define USBPCR_SIDDQ BIT(21) +#define USBPCR_OTG_DISABLE BIT(20) /* bits within the USBPCR1 register */ #define USBPCR1_REFCLKSEL_SHIFT 26 @@ -174,6 +174,7 @@ static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); spin_unlock_irqrestore(&cgu->lock, flags); + return 0; } @@ -184,6 +185,7 @@ static int x1000_usb_phy_enable(struct clk_hw *hw) writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); + return 0; } @@ -211,9 +213,9 @@ static const struct clk_ops x1000_otg_phy_ops = { .round_rate = x1000_otg_phy_round_rate, .set_rate = x1000_otg_phy_set_rate, - .enable = x1000_usb_phy_enable, - .disable = x1000_usb_phy_disable, - .is_enabled = x1000_usb_phy_is_enabled, + .enable = x1000_usb_phy_enable, + .disable = x1000_usb_phy_disable, + .is_enabled = x1000_usb_phy_is_enabled, }; static const s8 pll_od_encoding[8] = { @@ -300,7 +302,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_OTGPHY] = { "otg_phy", CGU_CLK_CUSTOM, - .parents = { -1, -1, X1000_CLK_EXCLK, -1 }, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .custom = { &x1000_otg_phy_ops }, }, @@ -320,14 +322,14 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, + .parents = { X1000_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR, 30 }, }, [X1000_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, - .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, + .parents = { X1000_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -346,13 +348,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, - .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, }, [X1000_CLK_PCLK] = { "pclk", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, .gate = { CGU_REG_CLKGR, 28 }, }, @@ -382,20 +384,20 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_MSC0CDR, 31, 1 }, }, [X1000_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_MSCMUX, -1, -1, -1 }, + .parents = { X1000_CLK_MSCMUX }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 4 }, }, [X1000_CLK_MSC1] = { "msc1", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_MSCMUX, -1, -1, -1 }, + .parents = { X1000_CLK_MSCMUX }, .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 5 }, }, @@ -411,7 +413,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, }, @@ -424,13 +426,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_SSIMUX] = { "ssi_mux", CGU_CLK_MUX, - .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 }, + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2 }, .mux = { CGU_REG_SSICDR, 30, 1 }, }, [X1000_CLK_CIM] = { "cim", CGU_CLK_MUX | CGU_CLK_DIV, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_CIMCDR, 31, 1 }, .div = { CGU_REG_CIMCDR, 0, 1, 8, 29, 28, 27 }, }, @@ -452,91 +454,91 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_EMC] = { "emc", CGU_CLK_GATE, - .parents = { X1000_CLK_AHB2, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2 }, .gate = { CGU_REG_CLKGR, 0 }, }, [X1000_CLK_EFUSE] = { "efuse", CGU_CLK_GATE, - .parents = { X1000_CLK_AHB2, -1, -1, -1 }, + .parents = { X1000_CLK_AHB2 }, .gate = { CGU_REG_CLKGR, 1 }, }, [X1000_CLK_SFC] = { "sfc", CGU_CLK_GATE, - .parents = { X1000_CLK_SSIPLL, -1, -1, -1 }, + .parents = { X1000_CLK_SSIPLL }, .gate = { CGU_REG_CLKGR, 2 }, }, [X1000_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 7 }, }, [X1000_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 8 }, }, [X1000_CLK_I2C2] = { "i2c2", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 9 }, }, [X1000_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 11 }, }, [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 14 }, }, [X1000_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 15 }, }, [X1000_CLK_UART2] = { "uart2", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 16 }, }, [X1000_CLK_DMIC] = { "dmic", CGU_CLK_GATE, - .parents = { X1000_CLK_PCLK, -1, -1, -1 }, + .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 17 }, }, [X1000_CLK_TCU] = { "tcu", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 18 }, }, [X1000_CLK_SSI] = { "ssi", CGU_CLK_GATE, - .parents = { X1000_CLK_SSIMUX, -1, -1, -1 }, + .parents = { X1000_CLK_SSIMUX }, .gate = { CGU_REG_CLKGR, 19 }, }, [X1000_CLK_OST] = { "ost", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 20 }, }, [X1000_CLK_PDMA] = { "pdma", CGU_CLK_GATE, - .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 21 }, }, diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index cfb0314..9f463fe 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -15,42 +15,42 @@ #include "pm.h" /* CGU register offsets */ -#define CGU_REG_CPCCR 0x00 -#define CGU_REG_CPPCR 0x0c -#define CGU_REG_APLL 0x10 -#define CGU_REG_MPLL 0x14 -#define CGU_REG_CLKGR0 0x20 -#define CGU_REG_OPCR 0x24 -#define CGU_REG_CLKGR1 0x28 -#define CGU_REG_DDRCDR 0x2c -#define CGU_REG_USBPCR 0x3c -#define CGU_REG_USBRDT 0x40 -#define CGU_REG_USBVBFIL 0x44 -#define CGU_REG_USBPCR1 0x48 -#define CGU_REG_MACCDR 0x54 -#define CGU_REG_EPLL 0x58 -#define CGU_REG_I2SCDR 0x60 -#define CGU_REG_LPCDR 0x64 -#define CGU_REG_MSC0CDR 0x68 -#define CGU_REG_I2SCDR1 0x70 -#define CGU_REG_SSICDR 0x74 -#define CGU_REG_CIMCDR 0x7c -#define CGU_REG_MSC1CDR 0xa4 -#define CGU_REG_CMP_INTR 0xb0 -#define CGU_REG_CMP_INTRE 0xb4 -#define CGU_REG_DRCG 0xd0 -#define CGU_REG_CPCSR 0xd4 -#define CGU_REG_VPLL 0xe0 -#define CGU_REG_MACPHYC 0xe8 +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_CPPCR 0x0c +#define CGU_REG_APLL 0x10 +#define CGU_REG_MPLL 0x14 +#define CGU_REG_CLKGR0 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_CLKGR1 0x28 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBRDT 0x40 +#define CGU_REG_USBVBFIL 0x44 +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_MACCDR 0x54 +#define CGU_REG_EPLL 0x58 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_I2SCDR1 0x70 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7c +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_VPLL 0xe0 +#define CGU_REG_MACPHYC 0xe8 /* bits within the OPCR register */ -#define OPCR_GATE_USBPHYCLK BIT(23) -#define OPCR_SPENDN0 BIT(7) -#define OPCR_SPENDN1 BIT(6) +#define OPCR_GATE_USBPHYCLK BIT(23) +#define OPCR_SPENDN0 BIT(7) +#define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ -#define USBPCR_SIDDQ BIT(21) -#define USBPCR_OTG_DISABLE BIT(20) +#define USBPCR_SIDDQ BIT(21) +#define USBPCR_OTG_DISABLE BIT(20) static struct ingenic_cgu *cgu; @@ -295,14 +295,14 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, + .parents = { X1830_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR1, 15 }, }, [X1830_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, - .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, + .parents = { X1830_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -321,13 +321,13 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, - .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { X1830_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, }, [X1830_CLK_PCLK] = { "pclk", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, + .parents = { X1830_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, .gate = { CGU_REG_CLKGR1, 14 }, }, @@ -366,14 +366,14 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, + .parents = { X1830_CLK_MSCMUX }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 4 }, }, [X1830_CLK_MSC1] = { "msc1", CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, + .parents = { X1830_CLK_MSCMUX }, .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 5 }, }, @@ -394,7 +394,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_SSIMUX] = { "ssi_mux", CGU_CLK_MUX, - .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 }, + .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2 }, .mux = { CGU_REG_SSICDR, 29, 1 }, }, @@ -423,97 +423,97 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_EMC] = { "emc", CGU_CLK_GATE, - .parents = { X1830_CLK_AHB2, -1, -1, -1 }, + .parents = { X1830_CLK_AHB2 }, .gate = { CGU_REG_CLKGR0, 0 }, }, [X1830_CLK_EFUSE] = { "efuse", CGU_CLK_GATE, - .parents = { X1830_CLK_AHB2, -1, -1, -1 }, + .parents = { X1830_CLK_AHB2 }, .gate = { CGU_REG_CLKGR0, 1 }, }, [X1830_CLK_OTG] = { "otg", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 3 }, }, [X1830_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, - .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, + .parents = { X1830_CLK_SSIMUX }, .gate = { CGU_REG_CLKGR0, 6 }, }, [X1830_CLK_SMB0] = { "smb0", CGU_CLK_GATE, - .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .parents = { X1830_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 7 }, }, [X1830_CLK_SMB1] = { "smb1", CGU_CLK_GATE, - .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .parents = { X1830_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 8 }, }, [X1830_CLK_SMB2] = { "smb2", CGU_CLK_GATE, - .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .parents = { X1830_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 9 }, }, [X1830_CLK_AIC] = { "aic", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 11 }, }, [X1830_CLK_DMIC] = { "dmic", CGU_CLK_GATE, - .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .parents = { X1830_CLK_PCLK }, .gate = { CGU_REG_CLKGR0, 12 }, }, [X1830_CLK_UART0] = { "uart0", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 14 }, }, [X1830_CLK_UART1] = { "uart1", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 15 }, }, [X1830_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, - .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, + .parents = { X1830_CLK_SSIMUX }, .gate = { CGU_REG_CLKGR0, 19 }, }, [X1830_CLK_SFC] = { "sfc", CGU_CLK_GATE, - .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, + .parents = { X1830_CLK_SSIPLL }, .gate = { CGU_REG_CLKGR0, 20 }, }, [X1830_CLK_PDMA] = { "pdma", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 21 }, }, [X1830_CLK_TCU] = { "tcu", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR0, 30 }, }, [X1830_CLK_DTRNG] = { "dtrng", CGU_CLK_GATE, - .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .parents = { X1830_CLK_PCLK }, .gate = { CGU_REG_CLKGR1, 1 }, }, @@ -525,7 +525,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_OST] = { "ost", CGU_CLK_GATE, - .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .parents = { X1830_CLK_EXCLK }, .gate = { CGU_REG_CLKGR1, 11 }, }, }; From patchwork Mon Jun 28 18:20:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 630CAC11F7F for ; Mon, 28 Jun 2021 18:21:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A84661C7C for ; Mon, 28 Jun 2021 18:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235529AbhF1SXd (ORCPT ); Mon, 28 Jun 2021 14:23:33 -0400 Received: from out28-98.mail.aliyun.com ([115.124.28.98]:34426 "EHLO out28-98.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234507AbhF1SX0 (ORCPT ); Mon, 28 Jun 2021 14:23:26 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.53124|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0604461-0.00470573-0.934848; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047209; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:57 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 07/11] dt-bindings: clock: Add documentation for JZ4775 and X2000 bindings. Date: Tue, 29 Jun 2021 02:20:40 +0800 Message-Id: <1624904444-2618-8-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the clock bindings of the JZ4775 SoC and the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index 6d6236e..5d699b3 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -25,9 +25,11 @@ select: - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu + - ingenic,jz4775-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu - ingenic,x1830-cgu + - ingenic,x2000-cgu required: - compatible @@ -54,9 +56,11 @@ properties: - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu + - ingenic,jz4775-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu - ingenic,x1830-cgu + - ingenic,x2000-cgu - const: simple-mfd minItems: 1 From patchwork Mon Jun 28 18:20:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B921EC11F70 for ; Mon, 28 Jun 2021 18:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A5D9861C7E for ; Mon, 28 Jun 2021 18:21:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234741AbhF1SXc (ORCPT ); Mon, 28 Jun 2021 14:23:32 -0400 Received: from out28-99.mail.aliyun.com ([115.124.28.99]:43652 "EHLO out28-99.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234627AbhF1SX2 (ORCPT ); Mon, 28 Jun 2021 14:23:28 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2811473|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.00620392-0.000189541-0.993607; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047190; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:20:59 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 08/11] dt-bindings: clock: Add JZ4775 clock bindings. Date: Tue, 29 Jun 2021 02:20:41 +0800 Message-Id: <1624904444-2618-9-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock bindings for the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. include/dt-bindings/clock/jz4775-cgu.h | 59 ++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/clock/jz4775-cgu.h diff --git a/include/dt-bindings/clock/jz4775-cgu.h b/include/dt-bindings/clock/jz4775-cgu.h new file mode 100644 index 00000000..8c2af69 --- /dev/null +++ b/include/dt-bindings/clock/jz4775-cgu.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4775-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4775 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ + +#define JZ4775_CLK_EXCLK 0 +#define JZ4775_CLK_RTCLK 1 +#define JZ4775_CLK_APLL 2 +#define JZ4775_CLK_MPLL 3 +#define JZ4775_CLK_OTGPHY 4 +#define JZ4775_CLK_SCLKA 5 +#define JZ4775_CLK_UHC 6 +#define JZ4775_CLK_UHCPHY 7 +#define JZ4775_CLK_CPUMUX 8 +#define JZ4775_CLK_CPU 9 +#define JZ4775_CLK_L2CACHE 10 +#define JZ4775_CLK_AHB0 11 +#define JZ4775_CLK_AHB2PMUX 12 +#define JZ4775_CLK_AHB2 13 +#define JZ4775_CLK_PCLK 14 +#define JZ4775_CLK_DDR 15 +#define JZ4775_CLK_VPU 16 +#define JZ4775_CLK_OTG 17 +#define JZ4775_CLK_EXCLK_DIV2 18 +#define JZ4775_CLK_I2S 19 +#define JZ4775_CLK_LCD 20 +#define JZ4775_CLK_MSCMUX 21 +#define JZ4775_CLK_MSC0 22 +#define JZ4775_CLK_MSC1 23 +#define JZ4775_CLK_MSC2 24 +#define JZ4775_CLK_SSI 25 +#define JZ4775_CLK_CIM0 26 +#define JZ4775_CLK_CIM1 27 +#define JZ4775_CLK_PCM 28 +#define JZ4775_CLK_BCH 29 +#define JZ4775_CLK_EXCLK_DIV512 30 +#define JZ4775_CLK_RTC 31 +#define JZ4775_CLK_NEMC 32 +#define JZ4775_CLK_I2C0 33 +#define JZ4775_CLK_I2C1 34 +#define JZ4775_CLK_I2C2 35 +#define JZ4775_CLK_SADC 36 +#define JZ4775_CLK_UART0 37 +#define JZ4775_CLK_UART1 38 +#define JZ4775_CLK_UART2 39 +#define JZ4775_CLK_UART3 40 +#define JZ4775_CLK_PDMA 41 +#define JZ4775_CLK_MAC 42 + +#endif /* __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ */ From patchwork Mon Jun 28 18:20:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AD04C11F75 for ; Mon, 28 Jun 2021 18:21:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EEC0261C7E for ; Mon, 28 Jun 2021 18:21:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235248AbhF1SXc (ORCPT ); Mon, 28 Jun 2021 14:23:32 -0400 Received: from out28-125.mail.aliyun.com ([115.124.28.125]:53254 "EHLO out28-125.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234642AbhF1SX2 (ORCPT ); Mon, 28 Jun 2021 14:23:28 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.29605|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0239892-0.00116343-0.974847; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047208; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:21:00 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 09/11] dt-bindings: clock: Add X2000 clock bindings. Date: Tue, 29 Jun 2021 02:20:42 +0800 Message-Id: <1624904444-2618-10-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock bindings for the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. include/dt-bindings/clock/x2000-cgu.h | 88 +++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 include/dt-bindings/clock/x2000-cgu.h diff --git a/include/dt-bindings/clock/x2000-cgu.h b/include/dt-bindings/clock/x2000-cgu.h new file mode 100644 index 00000000..222468d --- /dev/null +++ b/include/dt-bindings/clock/x2000-cgu.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x2000-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x2000 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X2000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X2000_CGU_H__ + +#define X2000_CLK_EXCLK 0 +#define X2000_CLK_RTCLK 1 +#define X2000_CLK_APLL 2 +#define X2000_CLK_MPLL 3 +#define X2000_CLK_EPLL 4 +#define X2000_CLK_OTGPHY 5 +#define X2000_CLK_SCLKA 6 +#define X2000_CLK_I2S0 7 +#define X2000_CLK_I2S1 8 +#define X2000_CLK_I2S2 9 +#define X2000_CLK_I2S3 10 +#define X2000_CLK_CPUMUX 11 +#define X2000_CLK_CPU 12 +#define X2000_CLK_L2CACHE 13 +#define X2000_CLK_AHB0 14 +#define X2000_CLK_AHB2PMUX 15 +#define X2000_CLK_AHB2 16 +#define X2000_CLK_PCLK 17 +#define X2000_CLK_DDR 18 +#define X2000_CLK_ISP 19 +#define X2000_CLK_MACPTP 20 +#define X2000_CLK_MACPHY 21 +#define X2000_CLK_MAC0TX 22 +#define X2000_CLK_MAC1TX 23 +#define X2000_CLK_RSA 24 +#define X2000_CLK_SSIPLL 25 +#define X2000_CLK_LCD 26 +#define X2000_CLK_MSC0 27 +#define X2000_CLK_MSC1 28 +#define X2000_CLK_MSC2 29 +#define X2000_CLK_PWM 30 +#define X2000_CLK_SFC 31 +#define X2000_CLK_CIM 32 +#define X2000_CLK_DMIC_EXCLK 33 +#define X2000_CLK_DMIC 34 +#define X2000_CLK_EXCLK_DIV512 35 +#define X2000_CLK_RTC 36 +#define X2000_CLK_EMC 37 +#define X2000_CLK_EFUSE 38 +#define X2000_CLK_OTG 39 +#define X2000_CLK_SCC 40 +#define X2000_CLK_I2C0 41 +#define X2000_CLK_I2C1 42 +#define X2000_CLK_I2C2 43 +#define X2000_CLK_I2C3 44 +#define X2000_CLK_SADC 45 +#define X2000_CLK_UART0 46 +#define X2000_CLK_UART1 47 +#define X2000_CLK_UART2 48 +#define X2000_CLK_DTRNG 49 +#define X2000_CLK_TCU 50 +#define X2000_CLK_SSI0 51 +#define X2000_CLK_OST 52 +#define X2000_CLK_PDMA 53 +#define X2000_CLK_SSI1 54 +#define X2000_CLK_I2C4 55 +#define X2000_CLK_I2C5 56 +#define X2000_CLK_ISP0 57 +#define X2000_CLK_ISP1 58 +#define X2000_CLK_HASH 59 +#define X2000_CLK_UART3 60 +#define X2000_CLK_UART4 61 +#define X2000_CLK_UART5 62 +#define X2000_CLK_UART6 63 +#define X2000_CLK_UART7 64 +#define X2000_CLK_UART8 65 +#define X2000_CLK_UART9 66 +#define X2000_CLK_MAC0 67 +#define X2000_CLK_MAC1 68 +#define X2000_CLK_INTC 69 +#define X2000_CLK_CSI 70 +#define X2000_CLK_DSI 71 + +#endif /* __DT_BINDINGS_CLOCK_X2000_CGU_H__ */ From patchwork Mon Jun 28 18:20:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABA30C11F79 for ; Mon, 28 Jun 2021 18:21:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BB4761C7B for ; Mon, 28 Jun 2021 18:21:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235355AbhF1SXd (ORCPT ); Mon, 28 Jun 2021 14:23:33 -0400 Received: from out28-53.mail.aliyun.com ([115.124.28.53]:50462 "EHLO out28-53.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235033AbhF1SXa (ORCPT ); Mon, 28 Jun 2021 14:23:30 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0272629-0.000267404-0.97247; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:21:01 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 10/11] clk: Ingenic: Add CGU driver for JZ4775. Date: Tue, 29 Jun 2021 02:20:43 +0800 Message-Id: <1624904444-2618-11-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the clocks provided by the CGU in the Ingenic JZ4775 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/jz4775-cgu.c | 571 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 582 insertions(+) create mode 100644 drivers/clk/ingenic/jz4775-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 898f1bc..7fda7bb 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -45,6 +45,16 @@ config INGENIC_CGU_JZ4770 If building for a JZ4770 SoC, you want to say Y here. +config INGENIC_CGU_JZ4775 + bool "Ingenic JZ4775 CGU driver" + default MACH_JZ4775 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4775 + and compatible SoCs. + + If building for a JZ4775 SoC, you want to say Y here. + config INGENIC_CGU_JZ4780 bool "Ingenic JZ4780 CGU driver" default MACH_JZ4780 diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 9edfaf4..aed8da4 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4775) += jz4775-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o diff --git a/drivers/clk/ingenic/jz4775-cgu.c b/drivers/clk/ingenic/jz4775-cgu.c new file mode 100644 index 00000000..b967d61 --- /dev/null +++ b/drivers/clk/ingenic/jz4775-cgu.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * JZ4775 SoC CGU driver + * Copyright (c) 2020 周琰杰 (Zhou Yanjie) + */ + +#include +#include +#include +#include + +#include + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_APLL 0x10 +#define CGU_REG_MPLL 0x14 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_VPUCDR 0x30 +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_USBCDR 0x50 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_UHCCDR 0x6c +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIM0CDR 0x7c +#define CGU_REG_CIM1CDR 0x80 +#define CGU_REG_PCMCDR 0x84 +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_MSC2CDR 0xa8 +#define CGU_REG_BCHCDR 0xac +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_SRBC 0xc4 +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_MACPHYC 0xe0 + +/* bits within the OPCR register */ +#define OPCR_SPENDN0 BIT(7) + +/* bits within the USBPCR register */ +#define USBPCR_SIDDQ BIT(21) +#define USBPCR_OTG_DISABLE BIT(20) + +/* bits within the USBPCR1 register */ +#define USBPCR1_REFCLKDIV_SHIFT 24 +#define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT) +#define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT) +#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT) +#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT) +#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT) +#define USBPCR1_PDBAR BIT(17) +#define USBPCR1_XP_SHIFT 12 +#define USBPCR1_XP_MASK (0x3 << USBPCR1_XP_SHIFT) +#define USBPCR1_XP_DFT (0x1 << USBPCR1_XP_SHIFT) +#define USBPCR1_SM_SHIFT 6 +#define USBPCR1_SM_MASK (0x7 << USBPCR1_XP_SHIFT) +#define USBPCR1_SM_RPD (0x1 << USBPCR1_XP_SHIFT) + +static struct ingenic_cgu *cgu; + +static int jz4775_uhc_phy_enable(struct clk_hw *hw) +{ + void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; + u32 usbpcr1; + + usbpcr1 = readl(reg_usbpcr1); + usbpcr1 &= ~(USBPCR1_XP_MASK | USBPCR1_SM_MASK); + usbpcr1 |= USBPCR1_XP_DFT | USBPCR1_SM_RPD; + writel(usbpcr1, reg_usbpcr1); + + return 0; +} + +static void jz4775_uhc_phy_disable(struct clk_hw *hw) +{ + void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; + + writel(readl(reg_usbpcr1) & ~USBPCR1_PDBAR, reg_usbpcr1); +} + +static int jz4775_uhc_phy_is_enabled(struct clk_hw *hw) +{ + void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; + + return !!(readl(reg_usbpcr1) & USBPCR1_PDBAR); +} + +static const struct clk_ops jz4775_uhc_phy_ops = { + .enable = jz4775_uhc_phy_enable, + .disable = jz4775_uhc_phy_disable, + .is_enabled = jz4775_uhc_phy_is_enabled, +}; + +static unsigned long jz4775_otg_phy_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 usbpcr1; + unsigned refclk_div; + + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); + refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; + + switch (refclk_div) { + case USBPCR1_REFCLKDIV_12: + return 12000000; + + case USBPCR1_REFCLKDIV_24: + return 24000000; + + case USBPCR1_REFCLKDIV_48: + return 48000000; + + case USBPCR1_REFCLKDIV_19_2: + return 19200000; + } + + return parent_rate; +} + +static long jz4775_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, + unsigned long *parent_rate) +{ + if (req_rate < 15600000) + return 12000000; + + if (req_rate < 21600000) + return 19200000; + + if (req_rate < 36000000) + return 24000000; + + return 48000000; +} + +static int jz4775_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, + unsigned long parent_rate) +{ + unsigned long flags; + u32 usbpcr1, div_bits; + + switch (req_rate) { + case 12000000: + div_bits = USBPCR1_REFCLKDIV_12; + break; + + case 19200000: + div_bits = USBPCR1_REFCLKDIV_19_2; + break; + + case 24000000: + div_bits = USBPCR1_REFCLKDIV_24; + break; + + case 48000000: + div_bits = USBPCR1_REFCLKDIV_48; + break; + + default: + return -EINVAL; + } + + spin_lock_irqsave(&cgu->lock, flags); + + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); + usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; + usbpcr1 |= div_bits; + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); + + spin_unlock_irqrestore(&cgu->lock, flags); + + return 0; +} + +static int jz4775_otg_phy_enable(struct clk_hw *hw) +{ + void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; + void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; + + writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); + writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); + + return 0; +} + +static void jz4775_otg_phy_disable(struct clk_hw *hw) +{ + void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; + void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; + + writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr); + writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr); +} + +static int jz4775_otg_phy_is_enabled(struct clk_hw *hw) +{ + void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; + void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; + + return (readl(reg_opcr) & OPCR_SPENDN0) && + !(readl(reg_usbpcr) & USBPCR_SIDDQ) && + !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE); +} + +static const struct clk_ops jz4775_otg_phy_ops = { + .recalc_rate = jz4775_otg_phy_recalc_rate, + .round_rate = jz4775_otg_phy_round_rate, + .set_rate = jz4775_otg_phy_set_rate, + + .enable = jz4775_otg_phy_enable, + .disable = jz4775_otg_phy_disable, + .is_enabled = jz4775_otg_phy_is_enabled, +}; + +static const s8 pll_od_encoding[8] = { + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, +}; + +static const struct ingenic_cgu_clk_info jz4775_cgu_clocks[] = { + + /* External clocks */ + + [JZ4775_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, + [JZ4775_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, + + /* PLLs */ + + [JZ4775_CLK_APLL] = { + "apll", CGU_CLK_PLL, + .parents = { JZ4775_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_APLL, + .rate_multiplier = 1, + .m_shift = 24, + .m_bits = 7, + .m_offset = 1, + .n_shift = 18, + .n_bits = 5, + .n_offset = 1, + .od_shift = 16, + .od_bits = 2, + .od_max = 8, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_APLL, + .bypass_bit = 9, + .enable_bit = 8, + .stable_bit = 10, + }, + }, + + [JZ4775_CLK_MPLL] = { + "mpll", CGU_CLK_PLL, + .parents = { JZ4775_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_MPLL, + .rate_multiplier = 1, + .m_shift = 24, + .m_bits = 7, + .m_offset = 1, + .n_shift = 18, + .n_bits = 5, + .n_offset = 1, + .od_shift = 16, + .od_bits = 2, + .od_max = 8, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_MPLL, + .bypass_bit = 6, + .enable_bit = 7, + .stable_bit = 0, + }, + }, + + /* Custom (SoC-specific) */ + + [JZ4775_CLK_UHCPHY] = { + "uhc_phy", CGU_CLK_CUSTOM, + .parents = { JZ4775_CLK_UHC, -1, -1, -1 }, + .custom = { &jz4775_uhc_phy_ops }, + }, + + [JZ4775_CLK_OTGPHY] = { + "otg_phy", CGU_CLK_CUSTOM, + .parents = { JZ4775_CLK_EXCLK, -1, -1, -1 }, + .custom = { &jz4775_otg_phy_ops }, + }, + + /* Muxes & dividers */ + + [JZ4775_CLK_SCLKA] = { + "sclk_a", CGU_CLK_MUX, + .parents = { -1, JZ4775_CLK_APLL, JZ4775_CLK_EXCLK, JZ4775_CLK_RTCLK }, + .mux = { CGU_REG_CPCCR, 30, 2 }, + }, + + [JZ4775_CLK_CPUMUX] = { + "cpu_mux", CGU_CLK_MUX, + .parents = { -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 28, 2 }, + }, + + [JZ4775_CLK_CPU] = { + "cpu", CGU_CLK_DIV, + .parents = { JZ4775_CLK_CPUMUX }, + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, + }, + + [JZ4775_CLK_L2CACHE] = { + "l2cache", CGU_CLK_DIV, + .parents = { JZ4775_CLK_CPUMUX }, + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, + }, + + [JZ4775_CLK_AHB0] = { + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 26, 2 }, + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, + }, + + [JZ4775_CLK_AHB2PMUX] = { + "ahb2_apb_mux", CGU_CLK_MUX, + .parents = { -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, JZ4775_CLK_RTCLK }, + .mux = { CGU_REG_CPCCR, 24, 2 }, + }, + + [JZ4775_CLK_AHB2] = { + "ahb2", CGU_CLK_DIV, + .parents = { JZ4775_CLK_AHB2PMUX }, + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, + }, + + [JZ4775_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4775_CLK_AHB2PMUX }, + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, + }, + + [JZ4775_CLK_DDR] = { + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, -1 }, + .mux = { CGU_REG_DDRCDR, 30, 2 }, + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 31 }, + }, + + [JZ4775_CLK_VPU] = { + "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_VPUCDR, 31, 1 }, + .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 19 }, + }, + + [JZ4775_CLK_OTG] = { + "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { JZ4775_CLK_EXCLK, -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_USBCDR, 30, 2 }, + .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 2 }, + }, + + [JZ4775_CLK_EXCLK_DIV2] = { + "exclk_div2", CGU_CLK_FIXDIV, + .parents = { JZ4775_CLK_EXCLK }, + .fixdiv = { 2 }, + }, + + [JZ4775_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4775_CLK_EXCLK_DIV2, -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_I2SCDR, 30, 2 }, + .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 }, + }, + + [JZ4775_CLK_LCD] = { + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, + .gate = { CGU_REG_CLKGR, 25 }, + }, + + [JZ4775_CLK_MSCMUX] = { + "msc_mux", CGU_CLK_MUX, + .parents = { -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, -1 }, + .mux = { CGU_REG_MSC0CDR, 30, 2 }, + }, + + [JZ4775_CLK_MSC0] = { + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_MSCMUX }, + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4775_CLK_MSC1] = { + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_MSCMUX }, + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4775_CLK_MSC2] = { + "msc2", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_MSCMUX }, + .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4775_CLK_UHC] = { + "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, JZ4775_CLK_OTGPHY, -1 }, + .mux = { CGU_REG_UHCCDR, 30, 2 }, + .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 22 }, + }, + + [JZ4775_CLK_SSI] = { + "ssi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK, -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_SSICDR, 30, 2 }, + .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4775_CLK_CIM0] = { + "cim0", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_CIM0CDR, 31, 1 }, + .div = { CGU_REG_CIM0CDR, 0, 1, 8, 30, 29, 28 }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + + [JZ4775_CLK_CIM1] = { + "cim1", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_CIM1CDR, 31, 1 }, + .div = { CGU_REG_CIM1CDR, 0, 1, 8, 30, 29, 28 }, + .gate = { CGU_REG_CLKGR, 24 }, + }, + + [JZ4775_CLK_PCM] = { + "pcm", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK_DIV2, -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL }, + .mux = { CGU_REG_PCMCDR, 30, 2 }, + .div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4775_CLK_BCH] = { + "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { -1, JZ4775_CLK_SCLKA, JZ4775_CLK_MPLL, -1 }, + .mux = { CGU_REG_BCHCDR, 30, 2 }, + .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4775_CLK_EXCLK_DIV512] = { + "exclk_div512", CGU_CLK_FIXDIV, + .parents = { JZ4775_CLK_EXCLK }, + .fixdiv = { 512 }, + }, + + [JZ4775_CLK_RTC] = { + "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK_DIV512, JZ4775_CLK_RTCLK }, + .mux = { CGU_REG_OPCR, 2, 1}, + }, + + /* Gate-only clocks */ + + [JZ4775_CLK_NEMC] = { + "nemc", CGU_CLK_GATE, + .parents = { JZ4775_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4775_CLK_I2C0] = { + "i2c0", CGU_CLK_GATE, + .parents = { JZ4775_CLK_PCLK }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4775_CLK_I2C1] = { + "i2c1", CGU_CLK_GATE, + .parents = { JZ4775_CLK_PCLK }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4775_CLK_I2C2] = { + "i2c2", CGU_CLK_GATE, + .parents = { JZ4775_CLK_PCLK }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4775_CLK_SADC] = { + "sadc", CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 14 }, + }, + + [JZ4775_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 15 }, + }, + + [JZ4775_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4775_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + + [JZ4775_CLK_UART3] = { + "uart3", CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 18 }, + }, + + [JZ4775_CLK_PDMA] = { + "pdma", CGU_CLK_GATE, + .parents = { JZ4775_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + + [JZ4775_CLK_MAC] = { + "mac", CGU_CLK_GATE, + .parents = { JZ4775_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR, 21 }, + }, +}; + +static void __init jz4775_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4775_cgu_clocks, + ARRAY_SIZE(jz4775_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) { + pr_err("%s: failed to register CGU Clocks\n", __func__); + return; + } + + ingenic_cgu_register_syscore_ops(cgu); +} +/* + * CGU has some children devices, this is useful for probing children devices + * in the case where the device node is compatible with "simple-mfd". + */ +CLK_OF_DECLARE_DRIVER(jz4775_cgu, "ingenic,jz4775-cgu", jz4775_cgu_init); From patchwork Mon Jun 28 18:20:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 468466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B5AEC11F81 for ; Mon, 28 Jun 2021 18:21:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E135E61C92 for ; Mon, 28 Jun 2021 18:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236031AbhF1SXe (ORCPT ); Mon, 28 Jun 2021 14:23:34 -0400 Received: from out28-124.mail.aliyun.com ([115.124.28.124]:52676 "EHLO out28-124.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235160AbhF1SXb (ORCPT ); Mon, 28 Jun 2021 14:23:31 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0313972-0.000392417-0.96821; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047207; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=14; RT=14; SR=0; TI=SMTPD_---.KZOO9TY_1624904444; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZOO9TY_1624904444) by smtp.aliyun-inc.com(10.147.42.253); Tue, 29 Jun 2021 02:21:02 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v5 11/11] clk: Ingenic: Add CGU driver for X2000. Date: Tue, 29 Jun 2021 02:20:44 +0800 Message-Id: <1624904444-2618-12-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624904444-2618-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the clocks provided by the CGU in the Ingenic X2000 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/x2000-cgu.c | 783 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 794 insertions(+) create mode 100644 drivers/clk/ingenic/x2000-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 7fda7bb..f5dd2f2 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -85,6 +85,16 @@ config INGENIC_CGU_X1830 If building for a X1830 SoC, you want to say Y here. +config INGENIC_CGU_X2000 + bool "Ingenic X2000 CGU driver" + default MACH_X2000 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic X2000 + and compatible SoCs. + + If building for a X2000 SoC, you want to say Y here. + config INGENIC_TCU_CLK bool "Ingenic JZ47xx TCU clocks driver" default MACH_INGENIC diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index aed8da4..de265ae 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4775) += jz4775-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o +obj-$(CONFIG_INGENIC_CGU_X2000) += x2000-cgu.o obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o diff --git a/drivers/clk/ingenic/x2000-cgu.c b/drivers/clk/ingenic/x2000-cgu.c new file mode 100644 index 00000000..21c02a6 --- /dev/null +++ b/drivers/clk/ingenic/x2000-cgu.c @@ -0,0 +1,783 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * X2000 SoC CGU driver + * Copyright (C) 2020 周琰杰 (Zhou Yanjie) + */ + +#include +#include +#include +#include + +#include + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR 0x0c +#define CGU_REG_CPAPCR 0x10 +#define CGU_REG_CPMPCR 0x14 +#define CGU_REG_CPEPCR 0x18 +#define CGU_REG_CLKGR0 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_CLKGR1 0x28 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_ISPCDR 0x30 +#define CGU_REG_CPSPR 0x34 +#define CGU_REG_CPSPPR 0x38 +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBRDT 0x40 +#define CGU_REG_USBVBFIL 0x44 +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_MACPTPCDR 0x4c +#define CGU_REG_RSACDR 0x50 +#define CGU_REG_MACCDR 0x54 +#define CGU_REG_MAC0TXCDR 0x58 +#define CGU_REG_SSICDR 0x5c +#define CGU_REG_I2S0CDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_PWMCDR 0x6c +#define CGU_REG_I2S0CDR1 0x70 +#define CGU_REG_SFCCDR 0x74 +#define CGU_REG_CIMCDR 0x78 +#define CGU_REG_I2S1CDR 0x7c +#define CGU_REG_I2S1CDR1 0x80 +#define CGU_REG_I2S2CDR 0x84 +#define CGU_REG_I2S2CDR1 0x88 +#define CGU_REG_I2S3CDR 0x8c +#define CGU_REG_PSWC0ST 0x90 +#define CGU_REG_PSWC1ST 0x94 +#define CGU_REG_PSWC2ST 0x98 +#define CGU_REG_PSWC3ST 0x9c +#define CGU_REG_I2S3CDR1 0xa0 +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_MSC2CDR 0xa8 +#define CGU_REG_AUDIOCR 0xac +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_CMP_SFTINT 0xbc +#define CGU_REG_SRBC 0xc4 +#define CGU_REG_SLBC 0xc8 +#define CGU_REG_SLPC 0xcc +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_MAC1TXCDR 0xdc +#define CGU_REG_MAC0PHYC 0xe4 +#define CGU_REG_MAC1PHYC 0xe8 +#define CGU_REG_MESTSEL 0xec +#define CGU_REG_MEMPD0 0xf8 +#define CGU_REG_MEMPD1 0xfc + +/* bits within the OPCR register */ +#define OPCR_GATE_USBPHYCLK BIT(23) +#define OPCR_SPENDN BIT(7) + +/* bits within the I2SCDR register */ +#define I2SCDR_I2PCS_SHIFT 30 +#define I2SCDR_I2PCS_MASK (0x1 << I2SCDR_I2PCS_SHIFT) +#define I2SCDR_I2SDIV_M_SHIFT 20 +#define I2SCDR_I2SDIV_M_MASK (0x1ff << I2SCDR_I2SDIV_M_SHIFT) +#define I2SCDR_I2SDIV_N_SHIFT 0 +#define I2SCDR_I2SDIV_N_MASK (0xfffff << I2SCDR_I2SDIV_N_SHIFT) +#define I2SCDR_CE_I2S BIT(29) + +/* bits within the CLKGR1 register */ +#define CLKGR1_I2S0 BIT(8) +#define CLKGR1_I2S1 BIT(9) +#define CLKGR1_I2S2 BIT(10) +#define CLKGR1_I2S3 BIT(11) + +static struct ingenic_cgu *cgu; + +static void x2000_i2s_calc_m_n(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + unsigned int delta, m, n; + u64 curr_delta, curr_m, curr_n; + + if ((parent_rate % rate == 0) && ((parent_rate / rate) > 1)) { + m = 1; + n = parent_rate / rate; + goto out; + } + + delta = rate; + + /* + * The length of M is 9 bits, its value must be between 1 and 511. + * The length of N is 20 bits, its value must be between 2 and 1048575, + * and must not be less than 2 times of the value of M. + */ + for (curr_m = 511; curr_m >= 1; curr_m--) { + curr_n = parent_rate * curr_m; + curr_delta = do_div(curr_n, rate); + + if (curr_n < 2 * curr_m || curr_n > 1048575) + continue; + + if (curr_delta == 0) + break; + + if (curr_delta < delta) { + m = curr_m; + n = curr_n; + delta = curr_delta; + } + } + +out: + *pm = m; + *pn = n; + + /* + * The I2S PLL does not have OD bits, so set the *pod to 1 to ensure + * that the ingenic_pll_calc() in cgu.c can run properly. + */ + *pod = 1; +} + +static int x2000_usb_phy_enable(struct clk_hw *hw) +{ + void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; + + writel((readl(reg_opcr) | OPCR_SPENDN) & ~OPCR_GATE_USBPHYCLK, reg_opcr); + + return 0; +} + +static void x2000_usb_phy_disable(struct clk_hw *hw) +{ + void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; + + writel((readl(reg_opcr) & ~OPCR_SPENDN) | OPCR_GATE_USBPHYCLK, reg_opcr); +} + +static int x2000_usb_phy_is_enabled(struct clk_hw *hw) +{ + void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; + + return !!(readl(reg_opcr) & OPCR_SPENDN); +} + +static const struct clk_ops x2000_otg_phy_ops = { + .enable = x2000_usb_phy_enable, + .disable = x2000_usb_phy_disable, + .is_enabled = x2000_usb_phy_is_enabled, +}; + +static const s8 pll_od_encoding[64] = { + -1, 0x1, -1, 0x2, -1, -1, -1, 0x3, + -1, -1, -1, -1, -1, -1, -1, 0x4, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 0x5, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 0x6, +}; + +static const struct ingenic_cgu_clk_info x2000_cgu_clocks[] = { + + /* External clocks */ + + [X2000_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, + [X2000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, + + /* PLLs */ + + [X2000_CLK_APLL] = { + "apll", CGU_CLK_PLL, + .parents = { X2000_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPAPCR, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 30, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X2000_CLK_MPLL] = { + "mpll", CGU_CLK_PLL, + .parents = { X2000_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPMPCR, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 10, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 28, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X2000_CLK_EPLL] = { + "epll", CGU_CLK_PLL, + .parents = { X2000_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPEPCR, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 10, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 26, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X2000_CLK_I2S0] = { + "i2s0", CGU_CLK_PLL, + .parents = { X2000_CLK_SCLKA, X2000_CLK_EPLL, -1, -1 }, + .pll = { + .reg = CGU_REG_I2S0CDR, + .rate_multiplier = 1, + .mux_shift = 30, + .mux_bits = 1, + .m_shift = 20, + .m_bits = 9, + .m_offset = 0, + .n_shift = 0, + .n_bits = 20, + .n_offset = 0, + .bypass_bit = -1, + .enable_bit = 29, + .stable_bit = -1, + .calc_m_n_od = x2000_i2s_calc_m_n, + }, + }, + + [X2000_CLK_I2S1] = { + "i2s1", CGU_CLK_PLL, + .parents = { X2000_CLK_SCLKA, X2000_CLK_EPLL, -1, -1 }, + .pll = { + .reg = CGU_REG_I2S1CDR, + .rate_multiplier = 1, + .mux_shift = 30, + .mux_bits = 1, + .m_shift = 20, + .m_bits = 9, + .m_offset = 0, + .n_shift = 0, + .n_bits = 20, + .n_offset = 0, + .bypass_bit = -1, + .enable_bit = 29, + .stable_bit = -1, + .calc_m_n_od = x2000_i2s_calc_m_n, + }, + }, + + [X2000_CLK_I2S2] = { + "i2s2", CGU_CLK_PLL, + .parents = { X2000_CLK_SCLKA, X2000_CLK_EPLL, -1, -1 }, + .pll = { + .reg = CGU_REG_I2S2CDR, + .rate_multiplier = 1, + .mux_shift = 30, + .mux_bits = 1, + .m_shift = 20, + .m_bits = 9, + .m_offset = 0, + .n_shift = 0, + .n_bits = 20, + .n_offset = 0, + .bypass_bit = -1, + .enable_bit = 29, + .stable_bit = -1, + .calc_m_n_od = x2000_i2s_calc_m_n, + }, + }, + + [X2000_CLK_I2S3] = { + "i2s3", CGU_CLK_PLL, + .parents = { X2000_CLK_SCLKA, X2000_CLK_EPLL, -1, -1 }, + .pll = { + .reg = CGU_REG_I2S3CDR, + .rate_multiplier = 1, + .mux_shift = 30, + .mux_bits = 1, + .m_shift = 20, + .m_bits = 9, + .m_offset = 0, + .n_shift = 0, + .n_bits = 20, + .n_offset = 0, + .bypass_bit = -1, + .enable_bit = 29, + .stable_bit = -1, + .calc_m_n_od = x2000_i2s_calc_m_n, + }, + }, + + /* Custom (SoC-specific) OTG PHY */ + + [X2000_CLK_OTGPHY] = { + "otg_phy", CGU_CLK_CUSTOM, + .parents = { X2000_CLK_EXCLK, -1, -1, -1 }, + .custom = { &x2000_otg_phy_ops }, + }, + + /* Muxes & dividers */ + + [X2000_CLK_SCLKA] = { + "sclk_a", CGU_CLK_MUX, + .parents = { -1, X2000_CLK_EXCLK, X2000_CLK_APLL, -1 }, + .mux = { CGU_REG_CPCCR, 30, 2 }, + }, + + [X2000_CLK_CPUMUX] = { + "cpu_mux", CGU_CLK_MUX, + .parents = { -1, X2000_CLK_SCLKA, X2000_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 28, 2 }, + }, + + [X2000_CLK_CPU] = { + "cpu", CGU_CLK_DIV, + .parents = { X2000_CLK_CPUMUX }, + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, + }, + + [X2000_CLK_L2CACHE] = { + "l2cache", CGU_CLK_DIV, + .parents = { X2000_CLK_CPUMUX }, + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, + }, + + [X2000_CLK_AHB0] = { + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { -1, X2000_CLK_SCLKA, X2000_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 26, 2 }, + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 29 }, + }, + + [X2000_CLK_AHB2PMUX] = { + "ahb2_apb_mux", CGU_CLK_MUX, + .parents = { -1, X2000_CLK_SCLKA, X2000_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 24, 2 }, + }, + + [X2000_CLK_AHB2] = { + "ahb2", CGU_CLK_DIV, + .parents = { X2000_CLK_AHB2PMUX }, + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, + }, + + [X2000_CLK_PCLK] = { + "pclk", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2PMUX }, + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 28 }, + }, + + [X2000_CLK_DDR] = { + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { -1, X2000_CLK_SCLKA, X2000_CLK_MPLL, -1 }, + .mux = { CGU_REG_DDRCDR, 30, 2 }, + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 31 }, + }, + + [X2000_CLK_ISP] = { + "isp", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_ISPCDR, 30, 2 }, + .div = { CGU_REG_ISPCDR, 0, 1, 4, 29, 28, 27 }, + }, + + [X2000_CLK_MACPTP] = { + "mac_ptp", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_MACPTPCDR, 30, 2 }, + .div = { CGU_REG_MACPTPCDR, 0, 1, 8, 29, 28, 27 }, + }, + + [X2000_CLK_MACPHY] = { + "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_MACCDR, 30, 2 }, + .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, + }, + + [X2000_CLK_MAC0TX] = { + "mac0_tx", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_MAC0TXCDR, 30, 2 }, + .div = { CGU_REG_MAC0TXCDR, 0, 1, 8, 29, 28, 27 }, + }, + + [X2000_CLK_MAC1TX] = { + "mac1_tx", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_MAC1TXCDR, 30, 2 }, + .div = { CGU_REG_MAC1TXCDR, 0, 1, 8, 29, 28, 27 }, + }, + + [X2000_CLK_RSA] = { + "rsa", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EXCLK, -1 }, + .mux = { CGU_REG_LPCDR, 30, 2 }, + .div = { CGU_REG_LPCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 25 }, + }, + + [X2000_CLK_SSIPLL] = { + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_SSICDR, 30, 2 }, + .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, + }, + + [X2000_CLK_LCD] = { + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EXCLK, -1 }, + .mux = { CGU_REG_LPCDR, 30, 2 }, + .div = { CGU_REG_LPCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 23 }, + }, + + [X2000_CLK_MSC0] = { + "msc0", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EXCLK, -1 }, + .mux = { CGU_REG_MSC0CDR, 30, 2 }, + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 4 }, + }, + + [X2000_CLK_MSC1] = { + "msc1", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EXCLK, -1 }, + .mux = { CGU_REG_MSC1CDR, 30, 2 }, + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 5 }, + }, + + [X2000_CLK_MSC2] = { + "msc2", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EXCLK, -1 }, + .mux = { CGU_REG_MSC2CDR, 30, 2 }, + .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR1, 25 }, + }, + + [X2000_CLK_PWM] = { + "pwm", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_PWMCDR, 30, 2 }, + .div = { CGU_REG_PWMCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR1, 5 }, + }, + + [X2000_CLK_SFC] = { + "sfc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_SFCCDR, 30, 2 }, + .div = { CGU_REG_SFCCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 2 }, + }, + + [X2000_CLK_CIM] = { + "cim", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X2000_CLK_SCLKA, X2000_CLK_MPLL, X2000_CLK_EPLL, -1 }, + .mux = { CGU_REG_CIMCDR, 30, 2 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 22 }, + }, + + [X2000_CLK_DMIC_EXCLK] = { + "dmic_exclk", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_AUDIOCR, 31 }, + }, + + [X2000_CLK_DMIC] = { + "dmic", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { X2000_CLK_DMIC_EXCLK, X2000_CLK_I2S3 }, + .mux = { CGU_REG_AUDIOCR, 0, 1}, + .gate = { CGU_REG_CLKGR1, 13 }, + }, + + [X2000_CLK_EXCLK_DIV512] = { + "exclk_div512", CGU_CLK_FIXDIV, + .parents = { X2000_CLK_EXCLK }, + .fixdiv = { 512 }, + }, + + [X2000_CLK_RTC] = { + "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK_DIV512, X2000_CLK_RTCLK }, + .mux = { CGU_REG_OPCR, 2, 1}, + .gate = { CGU_REG_CLKGR0, 27 }, + }, + + /* Gate-only clocks */ + + [X2000_CLK_EMC] = { + "emc", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR0, 0 }, + }, + + [X2000_CLK_EFUSE] = { + "efuse", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR0, 1 }, + }, + + [X2000_CLK_OTG] = { + "otg", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 3 }, + }, + + [X2000_CLK_SCC] = { + "scc", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 6 }, + }, + + [X2000_CLK_I2C0] = { + "i2c0", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR0, 7 }, + }, + + [X2000_CLK_I2C1] = { + "i2c1", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR0, 8 }, + }, + + [X2000_CLK_I2C2] = { + "i2c2", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR0, 9 }, + }, + + [X2000_CLK_I2C3] = { + "i2c3", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR0, 10 }, + }, + + [X2000_CLK_SADC] = { + "sadc", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 13 }, + }, + + [X2000_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 14 }, + }, + + [X2000_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 15 }, + }, + + [X2000_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 16 }, + }, + + [X2000_CLK_DTRNG] = { + "dtrng", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR0, 17 }, + }, + + [X2000_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 18 }, + }, + + [X2000_CLK_SSI0] = { + "ssi0", CGU_CLK_GATE, + .parents = { X2000_CLK_SSIPLL }, + .gate = { CGU_REG_CLKGR0, 19 }, + }, + + [X2000_CLK_OST] = { + "ost", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 20 }, + }, + + [X2000_CLK_PDMA] = { + "pdma", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR0, 21 }, + }, + + [X2000_CLK_SSI1] = { + "ssi1", CGU_CLK_GATE, + .parents = { X2000_CLK_SSIPLL }, + .gate = { CGU_REG_CLKGR0, 26 }, + }, + + [X2000_CLK_I2C4] = { + "i2c4", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR1, 0 }, + }, + + [X2000_CLK_I2C5] = { + "i2c5", CGU_CLK_GATE, + .parents = { X2000_CLK_PCLK }, + .gate = { CGU_REG_CLKGR1, 1 }, + }, + + [X2000_CLK_ISP0] = { + "isp0", CGU_CLK_GATE, + .parents = { X2000_CLK_ISP }, + .gate = { CGU_REG_CLKGR1, 2 }, + }, + + [X2000_CLK_ISP1] = { + "isp1", CGU_CLK_GATE, + .parents = { X2000_CLK_ISP }, + .gate = { CGU_REG_CLKGR1, 3 }, + }, + + [X2000_CLK_HASH] = { + "hash", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR1, 6 }, + }, + + [X2000_CLK_UART3] = { + "uart3", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 16 }, + }, + + [X2000_CLK_UART4] = { + "uart4", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 17 }, + }, + + [X2000_CLK_UART5] = { + "uart5", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 18 }, + }, + + [X2000_CLK_UART6] = { + "uart6", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 19 }, + }, + + [X2000_CLK_UART7] = { + "uart7", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 20 }, + }, + + [X2000_CLK_UART8] = { + "uart8", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 21 }, + }, + + [X2000_CLK_UART9] = { + "uart9", CGU_CLK_GATE, + .parents = { X2000_CLK_EXCLK }, + .gate = { CGU_REG_CLKGR1, 22 }, + }, + + [X2000_CLK_MAC0] = { + "mac0", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR1, 23 }, + }, + + [X2000_CLK_MAC1] = { + "mac1", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR1, 24 }, + }, + + [X2000_CLK_INTC] = { + "intc", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB2 }, + .gate = { CGU_REG_CLKGR1, 26 }, + }, + + [X2000_CLK_CSI] = { + "csi", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB0 }, + .gate = { CGU_REG_CLKGR1, 28 }, + }, + + [X2000_CLK_DSI] = { + "dsi", CGU_CLK_GATE, + .parents = { X2000_CLK_AHB0 }, + .gate = { CGU_REG_CLKGR1, 29 }, + }, +}; + +static void __init x2000_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(x2000_cgu_clocks, + ARRAY_SIZE(x2000_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) { + pr_err("%s: failed to register CGU Clocks\n", __func__); + return; + } + + ingenic_cgu_register_syscore_ops(cgu); +} +/* + * CGU has some children devices, this is useful for probing children devices + * in the case where the device node is compatible with "simple-mfd". + */ +CLK_OF_DECLARE_DRIVER(x2000_cgu, "ingenic,x2000-cgu", x2000_cgu_init);