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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id v10-v6si1809595qvn.266.2018.08.16.07.30.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 16 Aug 2018 07:30:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=X8pRFrTG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56057 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJHs-0006WT-40 for patch@linaro.org; Thu, 16 Aug 2018 10:30:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJ1o-0006Uk-I4 for qemu-devel@nongnu.org; Thu, 16 Aug 2018 10:13:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqJ1m-0004Lm-NP for qemu-devel@nongnu.org; Thu, 16 Aug 2018 10:13:32 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:41730) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fqJ1l-0004Jx-Hr; Thu, 16 Aug 2018 10:13:30 -0400 Received: by mail-pf1-x432.google.com with SMTP id y10-v6so2083721pfn.8; Thu, 16 Aug 2018 07:13:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KwnVk0FZbRL5sACB19TJDzQlDaPoBQkUgoOUVam8cLY=; b=X8pRFrTGUtSLi0g1TjIvFw6wRO7d04PPrQJghiSAd9PBbmNSCnhCiklMn6CIRjM8NO PcZPGnvPyN1iRKuC6wSd6me8LknJ1dQ5LEW0CBpS9JCaJKwfOcW9o22CPMQ+uGIG/KtU S1EoyaTSTb89DlIK+5QBZVcKl0N1ZcRhakCQ/9OnH2wtHRCBSNKM5+q9NO79uWEl43wI sh/zfKPbRbzT8begRR2kuWEn2OKNUyzyk6OL67iBOEd5iw7wPe+4rPZN44gniS7jkW8d NA+wtsx7pxaviBBWNGxJGcHvyybHVL5JlNQkSRIFn0HkDHsYol3k2aEZTyJvU5WM9z8J KINg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KwnVk0FZbRL5sACB19TJDzQlDaPoBQkUgoOUVam8cLY=; b=rrQzlLGAvFlhEx2QzU7qrzbgr4aUePE7090Erbinxvg5VQdvaftaNih0qVi6Rsx05O SeY8+bDRGxbZmsFCW7TUqi7l6e17lAYPMQn45iKfmjHcNAvo/cct+jOKfI0A2synpRXR ySVsfq3e6FNk3vGGojoKwzwf5Gy86XBzLyn6CBFRsK+bjKpMKWVGblW1MA3WzDeTrCB1 pr0LpCdmb6IWwzY+08buwUkxXhg7MCVxn7x2Fd6xEJF4g3nAhfcXF1JxscdpElMkBn6t rlUPHfCia1KNyNg5FIouD8RKU0W1Z9aL3Zh078/7GuFJgryIUq4W4mPfwpWVLnlBA37+ 2v9Q== X-Gm-Message-State: AOUpUlEgyFSyzBpAucAyQkUIcW6qQQEADAuj6MyyasbDP4V2T/XeYbp/ MG+WI7uMAb6/o+Ah+ou6wyQ= X-Received: by 2002:a63:dd49:: with SMTP id g9-v6mr28991934pgj.356.1534428808214; Thu, 16 Aug 2018 07:13:28 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id c66-v6sm47934034pfc.138.2018.08.16.07.13.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Aug 2018 07:13:27 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 16 Aug 2018 23:43:19 +0930 From: Joel Stanley To: Peter Maydell Date: Thu, 16 Aug 2018 23:43:01 +0930 Message-Id: <20180816141303.20518-2-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180816141303.20518-1-joel@jms.id.au> References: <20180816141303.20518-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v5 1/3] MAINTAINERS: Add NRF51 entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This contains the NRF51, and the machine that uses it, the BBC micro:bit. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v3: fix spelling of mailing list add stefan's reviewed-by --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index c48d9271cf15..5a0d2e327d4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -656,6 +656,14 @@ F: include/hw/*/*aspeed* F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h +NRF51 +M: Joel Stanley +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/nrf51_soc.c +F: hw/arm/microbit.c +F: include/hw/arm/nrf51_soc.h + CRIS Machines ------------- Axis Dev88 From patchwork Thu Aug 16 14:13:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 144428 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2152604ljj; Thu, 16 Aug 2018 07:31:39 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyMGOLoZHhLi3j0mAt9nFmOaNGgV+OzhWkff0Jk6AUSeWy9OSroZEuZvtDf7qRQKXbCS5dv X-Received: by 2002:ac8:725a:: with SMTP id l26-v6mr30341159qtp.181.1534429898927; Thu, 16 Aug 2018 07:31:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534429898; cv=none; d=google.com; s=arc-20160816; b=IpcdUPZupbneGVJ/SfXhvxse1W0M4XhRUuN4+ijMRKW+/EoTO3NNYL7CdlIURVzLs2 bxABoXxKntVKESAnCMM4pl/8mJz9wHEIQx764I+xxEu/S+inqD05VGXicbB51bU6VqzC 4RM18BnL/wlXtNL4mtfX2G3OtLC/c2FYGK5N/Fh8+SIMO3OmBm2sNJiWMjL7Agpz3/FJ skR8zz0kBivKrtCSLLNw3jIyhyu0Nf1Y8XPLiEc3aOoUEU1/g1WAoCrRUsRU9Xra0r4g yp4P6WutlWoxXbYRXC0Ye8rrEUrEoUwxJI3xZc+YGXOzJH2an8HjMbc4mtLH/6/6N/12 Ip1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HD9livxLG0d3HiRBZ02LtrmS9pKMvLvMeGEh1xLS3aw=; b=itbT9PqBOKCMjAzZ7BC3n0uUKUNDBtgco+Dxjy0JyKlG6URyidw9oHWst7NL3GkvBr LY6QmH8gKsWmYK61+ZnbAj4vssY40DfAtL1kuKkHJeB1p9FrzIkI+mEMMIUvsaFE1y6y okLQKEIXYF3/d9LaNCaitWukTojGl+bakWkrveK826Nyp4N4AAO+waTUWavAdkH+f+Hj p7YbW42J0n19Umu/gjh66tqhuMCk1oaFTzEQHGxhAiquC1BXtJ3AbrCyI2/sFuIQ8uWT UtSMhaNGtFzFkLopG6zjIcSa/3G/d+lkckqP3UJV4YTtvqYrSpayVs/aNrX4oA3pcNFW lxKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=h6JltKWH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v24-v6si7296355qta.334.2018.08.16.07.31.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 16 Aug 2018 07:31:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=h6JltKWH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56070 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJJK-00089w-Bs for patch@linaro.org; Thu, 16 Aug 2018 10:31:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42617) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqJ1w-0006bs-7x for qemu-devel@nongnu.org; Thu, 16 Aug 2018 10:13:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqJ1v-0004Rs-0r for qemu-devel@nongnu.org; Thu, 16 Aug 2018 10:13:40 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39486) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fqJ1u-0004Qa-6w; Thu, 16 Aug 2018 10:13:38 -0400 Received: by mail-pf1-x442.google.com with SMTP id j8-v6so2089613pff.6; Thu, 16 Aug 2018 07:13:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=HD9livxLG0d3HiRBZ02LtrmS9pKMvLvMeGEh1xLS3aw=; b=h6JltKWH5kDTmmCjEou04HUYLweMqhVqL9e3FxYTYycgWrwKL8s5ZJQ/yKvfGpsHsD o8TbloukfayjKoW+TkVIJXfWP0Q3ni9Onmrlb2gB6cJAsA+MwWrDr6rnk3AHuY7Qr5Ek lDDfZ6vC0dIhxLWFBfSO0U5oFcCuY2Pd/nL/+DHEtboYVrCMAOkNCo8vke+pYAYvIcIN VWOO7QEYGYyb5X8k15zN06iM7rVhUcWZkXE1GPI43FOnOGNAV3tcCGiQyHU6DsJ7DHYj vcdsBkVmgj8Edyer4kYKBbwLN1hrO6Ffj3SQk1wwtAqk7svjLli965evVnFjcRXGLwqs 1Ydg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=HD9livxLG0d3HiRBZ02LtrmS9pKMvLvMeGEh1xLS3aw=; b=R9TD1Mb1vhz6eBdj+KIrgFu72sDtZjaNymQBdrzsX4YiISdFdkpXzdGbJP150NfaPn gqH0tBug/yIcvsiAB77oI598i/9cxbEwKjG2j8lgEnuMWJs/d5t/i+/2L4CMABHRnloM AeDp1FVJvPsBjSTyZ5Fb/sz4gCvS0oL4hEmeguXpF4LE1vLmvthFjCZI9yyMbBNVJgFQ tqW46TW3XnZK1tyxZd/jrCdkIxy7yA/Eaq/0kRsPwfg1GbzWAoppUhAy+bemErPIWnKA 3Ou+Er1tvE4E7aT3EW4G21QUBztC7CA+XuHBScAewg9K2fcPKjMB1GiJrK3tMU5UB0Eq L0gQ== X-Gm-Message-State: AOUpUlHYVdvkLK3qtLx5u/wHkwylHaXRQ+tnlLyBwGkfz/FI0ONDSZoU We5NWCIICOd0uSSnaataEG8= X-Received: by 2002:a63:dd49:: with SMTP id g9-v6mr28992501pgj.356.1534428816982; Thu, 16 Aug 2018 07:13:36 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id o3-v6sm24614163pgp.3.2018.08.16.07.13.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Aug 2018 07:13:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 16 Aug 2018 23:43:28 +0930 From: Joel Stanley To: Peter Maydell Date: Thu, 16 Aug 2018 23:43:02 +0930 Message-Id: <20180816141303.20518-3-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180816141303.20518-1-joel@jms.id.au> References: <20180816141303.20518-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v5 2/3] arm: Add Nordic Semiconductor nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley --- v2: put memory as struct fileds in state structure pass OBJECT(s) as owner, not NULL Add missing addresses for ficr Fix flash and sram sizes for microbit Embed cpu object in state object an initalise it without use of armv7m_init Link to datasheet v3: rebase nrf51 on m0 changes remove unused kernel_filename clarify flash and sram size make flash and sram size properties of the soc state v4: set the number of interrupts to 32 v5: move back to armv7m calls, as v4 of Stefan's patch removed the m_profile changes --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/nrf51_soc.c | 119 ++++++++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 42 +++++++++++ 4 files changed, 163 insertions(+) create mode 100644 hw/arm/nrf51_soc.c create mode 100644 include/hw/arm/nrf51_soc.h -- 2.17.1 Reviewed-by: Stefan Hajnoczi diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 311584fd74eb..2ff27c2e1d5a 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -101,6 +101,7 @@ CONFIG_STM32F2XX_SYSCFG=y CONFIG_STM32F2XX_ADC=y CONFIG_STM32F2XX_SPI=y CONFIG_STM32F205_SOC=y +CONFIG_NRF51_SOC=y CONFIG_CMSDK_APB_TIMER=y CONFIG_CMSDK_APB_UART=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 2902f47b4c4c..ae4e20373b9e 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -37,3 +37,4 @@ obj-$(CONFIG_IOTKIT) += iotkit.o obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c new file mode 100644 index 000000000000..9f9649c7807d --- /dev/null +++ b/hw/arm/nrf51_soc.c @@ -0,0 +1,119 @@ +/* + * Nordic Semiconductor nRF51 SoC + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/devices.h" +#include "hw/misc/unimp.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" +#include "cpu.h" + +#include "hw/arm/nrf51_soc.h" + +#define IOMEM_BASE 0x40000000 +#define IOMEM_SIZE 0x20000000 + +#define FICR_BASE 0x10000000 +#define FICR_SIZE 0x000000fc + +#define FLASH_BASE 0x00000000 +#define SRAM_BASE 0x20000000 + +/* The size and base is for the NRF51822 part. If other parts + * are supported in the future, add a sub-class of NRF51SoC for + * the specific variants */ +#define NRF51822_FLASH_SIZE (256 * 1024) +#define NRF51822_SRAM_SIZE (16 * 1024) + +static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) +{ + NRF51State *s = NRF51_SOC(dev_soc); + Error *err = NULL; + + if (!s->board_memory) { + error_setg(errp, "memory property was not set"); + return; + } + + object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", + &err); + object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); + + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); + + memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, + &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_set_readonly(&s->flash, true); + memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + + memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + + create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.private", 0xF0000000, 0x10000000); +} + +static void nrf51_soc_init(Object *obj) +{ + NRF51State *s = NRF51_SOC(obj); + + memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); + + object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARMV7M); + object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error_abort); + qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default()); + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0")); + qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); +} + +static Property nrf51_soc_properties[] = { + DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), + DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLASH_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = nrf51_soc_realize; + dc->props = nrf51_soc_properties; +} + +static const TypeInfo nrf51_soc_info = { + .name = TYPE_NRF51_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51State), + .instance_init = nrf51_soc_init, + .class_init = nrf51_soc_class_init, +}; + +static void nrf51_soc_types(void) +{ + type_register_static(&nrf51_soc_info); +} +type_init(nrf51_soc_types) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h new file mode 100644 index 000000000000..e380ec26b8eb --- /dev/null +++ b/include/hw/arm/nrf51_soc.h @@ -0,0 +1,42 @@ +/* + * Nordic Semiconductor nRF51 SoC + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_SOC_H +#define NRF51_SOC_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/arm/armv7m.h" + +#define TYPE_NRF51_SOC "nrf51-soc" +#define NRF51_SOC(obj) \ + OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) + +typedef struct NRF51State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + ARMv7MState cpu; + + MemoryRegion iomem; + MemoryRegion sram; + MemoryRegion flash; + + uint32_t sram_size; + uint32_t flash_size; + + MemoryRegion *board_memory; + + MemoryRegion container; + +} NRF51State; + +#endif + From patchwork Thu Aug 16 14:13:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 144426 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2146728ljj; Thu, 16 Aug 2018 07:26:03 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxLS/4OqT3z51KH/Gea2gjEYd522aUlhEDYywb6r8se7vfHzpz48V78nKMR0nyBA+Fqipd1 X-Received: by 2002:aed:23f8:: with SMTP id k53-v6mr29297331qtc.230.1534429563602; Thu, 16 Aug 2018 07:26:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534429563; cv=none; d=google.com; s=arc-20160816; b=YODEZMzrMHkTtjitRsN4IjFToMGEywoRg55p7HotYsfqzZyAAsGLzbX2iru2vAYX7Q DLQGkJfDCMg7x1vA9qYO0HNoMbGYydWKZru5MuAuakZYyp5NNeej3kryIU9d1WrnOxEe dbawW/0RcfuFlahfoOjnUN43mPmkZBjldz7mSe73Zy1xk605hRFv11kNlvph6MANe4sK CCe2VvyskzUK5Vn5YFgPSm68ZPIMA6j+lwfF0hj4GN/Cc6n3WHdxS7CY22AwIK44iaEp 6LfWT0SH7bfItilgsDOjoVTr339hpIi8msqE4QTuOhQWKagLlwhGbNpouGcuMqsNQrh/ VZgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=BEuLX0ahye47Gf5X2qlGa21bUMaQV4A951E5uD+yS84=; b=PRu18r4N933PU6isiglf6ulJlCQ8pZimafCQn/0861JWRL/pfaIK00JMohHxG8IibT 4ntYF5tOv/68Khv9lrng7trnP2L6SEEKU47I+U2GPlon7XVwvQ3c4JpI+oYXCRrwQz7+ 2cMN+d+sIpt4JTYxIctX3ju1D6AzhgnuHJW6Kk6OXtzWUIrcZa7gHUB+AS3iUsWuIgsF +kVwd2ty80De8PHuwfAWmiakxN5wm9nBcB6bjK24JNFUBWDMk8K4+0f1TwBbHmyOxr5w qRgVmisY9+OttjXSN8QPr/elYAuY7w7S4cE3DiRGmV38pbixID3lvdkSxOaAcELo2DYo m0iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=PLnETtpg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v5 3/3] arm: Add BBC micro:bit machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v2: - Instead of setting kernel filename property, load the image directly - Add link to hardware overview website v3: - Rebase microbit on m0 changes - Remove hard-coded flash size and retrieve from the soc - Add Stefan's reviewed-by v5: - move back to armv7m calls, as v4 of Stefan's patch removed the m_profile changes --- hw/arm/Makefile.objs | 2 +- hw/arm/microbit.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 hw/arm/microbit.c -- 2.17.1 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index ae4e20373b9e..5f88062c666d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -37,4 +37,4 @@ obj-$(CONFIG_IOTKIT) += iotkit.o obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o -obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o microbit.o diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c new file mode 100644 index 000000000000..467cfbda2348 --- /dev/null +++ b/hw/arm/microbit.c @@ -0,0 +1,54 @@ +/* + * BBC micro:bit machine + * http://tech.microbit.org/hardware/ + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" + +#include "hw/arm/nrf51_soc.h" + +typedef struct { + MachineState parent; + + NRF51State nrf51; +} MICROBITMachineState; + +#define TYPE_MICROBIT_MACHINE "microbit" + +#define MICROBIT_MACHINE(obj) \ + OBJECT_CHECK(MICROBITMachineState, obj, TYPE_MICROBIT_MACHINE) + +static void microbit_init(MachineState *machine) +{ + MICROBITMachineState *s = g_new(MICROBITMachineState, 1); + MemoryRegion *system_memory = get_system_memory(); + Object *soc; + + object_initialize(&s->nrf51, sizeof(s->nrf51), TYPE_NRF51_SOC); + soc = OBJECT(&s->nrf51); + object_property_add_child(OBJECT(machine), "nrf51", soc, &error_fatal); + object_property_set_link(soc, OBJECT(system_memory), + "memory", &error_abort); + + object_property_set_bool(soc, true, "realized", &error_abort); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + NRF51_SOC(soc)->flash_size); +} + +static void microbit_machine_init(MachineClass *mc) +{ + mc->desc = "BBC micro:bit"; + mc->init = microbit_init; + mc->max_cpus = 1; +} +DEFINE_MACHINE("microbit", microbit_machine_init);