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Sat, 26 Jun 2021 03:28:20 -0700 Envelope-to: git@xilinx.com, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, marex@denx.de, joe@perches.com Received: from [10.140.6.6] (port=55646 helo=xhdappanad40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lx5Xv-000AWJ-Aw; Sat, 26 Jun 2021 03:28:19 -0700 From: Raviteja Narayanam To: , CC: , , , , , Raviteja Narayanam Subject: [PATCH v2 02/10] i2c: xiic: Add standard mode support for > 255 byte read transfers Date: Sat, 26 Jun 2021 15:57:58 +0530 Message-ID: <20210626102806.15402-3-raviteja.narayanam@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> References: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 18a6c846-7710-47cc-d375-08d9388d2824 X-MS-TrafficTypeDiagnostic: DM5PR02MB3765: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:232; 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CAT:NONE; SFS:(4636009)(376002)(39860400002)(136003)(396003)(346002)(46966006)(36840700001)(336012)(70206006)(36860700001)(6636002)(36906005)(8936002)(54906003)(82740400003)(316002)(356005)(5660300002)(82310400003)(30864003)(8676002)(83380400001)(2906002)(7636003)(44832011)(1076003)(9786002)(186003)(7696005)(26005)(110136005)(70586007)(2616005)(107886003)(4326008)(6666004)(36756003)(426003)(478600001)(47076005)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2021 10:28:36.3882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18a6c846-7710-47cc-d375-08d9388d2824 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0061.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB3765 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org In the current driver implementation, there is a limit of read transfer size to 255 bytes as it is using AXI I2C dynamic mode. But the IP supports this transfer through standard mode. So added AXI I2C standard mode support to enable read transfers of size more than 255 bytes. The driver scans through the message request from user space and selects AXI I2C standard mode if there is a read request of more than 255 bytes. Then the whole message goes through standard mode Tx and Rx paths. Signed-off-by: Raviteja Narayanam --- drivers/i2c/busses/i2c-xiic.c | 367 +++++++++++++++++++++++++++++----- 1 file changed, 319 insertions(+), 48 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index b0cfd9d15467..004103267e9c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -60,6 +60,8 @@ enum xiic_endian { * @clk: Pointer to AXI4-lite input clock * @state: See STATE_ * @singlemaster: Indicates bus is single master + * @dynamic: Mode of controller + * @prev_msg_tx: Previous message is Tx */ struct xiic_i2c { struct device *dev; @@ -76,6 +78,8 @@ struct xiic_i2c { struct clk *clk; enum xilinx_i2c_state state; bool singlemaster; + bool dynamic; + bool prev_msg_tx; }; @@ -144,6 +148,9 @@ struct xiic_i2c { #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ +/* Dynamic mode constants */ +#define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ + /* * The following constants define the register offsets for the Interrupt * registers. There are some holes in the memory map for reserved addresses @@ -270,6 +277,24 @@ static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) return 0; } +static int xiic_wait_tx_empty(struct xiic_i2c *i2c) +{ + u8 isr; + unsigned long timeout; + + timeout = jiffies + XIIC_I2C_TIMEOUT; + for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + !(isr & XIIC_INTR_TX_EMPTY_MASK); + isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { + if (time_after(jiffies, timeout)) { + dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + static int xiic_reinit(struct xiic_i2c *i2c) { int ret; @@ -311,13 +336,14 @@ static void xiic_deinit(struct xiic_i2c *i2c) static void xiic_read_rx(struct xiic_i2c *i2c) { - u8 bytes_in_fifo; + u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; + u32 bytes_rem = 0; int i; bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; dev_dbg(i2c->adap.dev.parent, - "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", + "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", __func__, bytes_in_fifo, xiic_rx_space(i2c), xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); @@ -325,13 +351,53 @@ static void xiic_read_rx(struct xiic_i2c *i2c) if (bytes_in_fifo > xiic_rx_space(i2c)) bytes_in_fifo = xiic_rx_space(i2c); - for (i = 0; i < bytes_in_fifo; i++) + bytes_to_read = bytes_in_fifo; + + if (!i2c->dynamic) { + bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; + + if (bytes_rem > IIC_RX_FIFO_DEPTH) { + bytes_to_read = bytes_in_fifo; + } else if (bytes_rem > 1) { + bytes_to_read = bytes_rem - 1; + } else if (bytes_rem == 1) { + bytes_to_read = 1; + /* Set NACK in CR to indicate slave transmitter */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | + XIIC_CR_NO_ACK_MASK); + } else if (bytes_rem == 0) { + bytes_to_read = bytes_in_fifo; + + /* Generate stop on the bus if it is last message */ + if (i2c->nmsgs == 1) { + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_MSMS_MASK); + } + + /* Make TXACK=0, clean up for next transaction */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_NO_ACK_MASK); + } + } + + /* Read the fifo */ + for (i = 0; i < bytes_to_read; i++) { i2c->rx_msg->buf[i2c->rx_pos++] = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + } - xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, - (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? - IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); + if (i2c->dynamic) { + u8 bytes; + + /* Receive remaining bytes if less than fifo depth */ + bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); + bytes--; + + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); + } } static int xiic_tx_fifo_space(struct xiic_i2c *i2c) @@ -361,6 +427,62 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) } } +static void xiic_std_fill_tx_fifo(struct xiic_i2c *i2c) +{ + u8 fifo_space = xiic_tx_fifo_space(i2c); + u16 data = 0; + int len = xiic_tx_space(i2c); + + dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", + __func__, len, fifo_space); + + if (len > fifo_space) + len = fifo_space; + else if (len && !(i2c->nmsgs > 1)) + len--; + + while (len--) { + data = i2c->tx_msg->buf[i2c->tx_pos++]; + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } +} + +static void xiic_send_tx(struct xiic_i2c *i2c) +{ + dev_dbg(i2c->adap.dev.parent, + "%s entry, rem: %d, SR: 0x%x, CR: 0x%x\n", + __func__, xiic_tx_space(i2c), + xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + + if (xiic_tx_space(i2c) > 1) { + xiic_std_fill_tx_fifo(i2c); + return; + } + + if ((xiic_tx_space(i2c) == 1)) { + u16 data; + + if (i2c->nmsgs == 1) { + u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; + + /* Write to CR to stop */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_MSMS_MASK); + } + /* Send last byte */ + data = i2c->tx_msg->buf[i2c->tx_pos++]; + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } +} + static void xiic_wakeup(struct xiic_i2c *i2c, int code) { i2c->tx_msg = NULL; @@ -391,7 +513,9 @@ static irqreturn_t xiic_process(int irq, void *dev_id) dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), i2c->tx_msg, i2c->nmsgs); - + dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); /* Service requesting interrupt */ if ((pend & XIIC_INTR_ARB_LOST_MASK) || @@ -465,7 +589,10 @@ static irqreturn_t xiic_process(int irq, void *dev_id) goto out; } - xiic_fill_tx_fifo(i2c); + if (i2c->dynamic) + xiic_fill_tx_fifo(i2c); + else + xiic_send_tx(i2c); /* current message sent and there is space in the fifo */ if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { @@ -554,35 +681,113 @@ static int xiic_busy(struct xiic_i2c *i2c) static void xiic_start_recv(struct xiic_i2c *i2c) { - u8 rx_watermark; + u16 rx_watermark; + u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; unsigned long flags; - /* Clear and enable Rx full interrupt. */ - xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); + dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + + /* Disable Tx interrupts */ + xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); - /* we want to get all but last byte, because the TX_ERROR IRQ is used - * to inidicate error ACK on the address, and negative ack on the last - * received byte, so to not mix them receive all but last. - * In the case where there is only one byte to receive - * we can check if ERROR and RX full is set at the same time - */ - rx_watermark = msg->len; - if (rx_watermark > IIC_RX_FIFO_DEPTH) - rx_watermark = IIC_RX_FIFO_DEPTH; - xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); - - local_irq_save(flags); - if (!(msg->flags & I2C_M_NOSTART)) - /* write the address */ + if (i2c->dynamic) { + u8 bytes; + u16 val; + + /* Clear and enable Rx full interrupt. */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK); + + /* + * We want to get all but last byte, because the TX_ERROR IRQ + * is used to indicate error ACK on the address, and + * negative ack on the last received byte, so to not mix + * them receive all but last. + * In the case where there is only one byte to receive + * we can check if ERROR and RX full is set at the same time + */ + rx_watermark = msg->len; + bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); + bytes--; + + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); + + local_irq_save(flags); + if (!(msg->flags & I2C_M_NOSTART)) + /* write the address */ + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, + i2c_8bit_addr_from_msg(msg) | + XIIC_TX_DYN_START_MASK); + + xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + + /* If last message, include dynamic stop bit with length */ + val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; + val |= msg->len; + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); + local_irq_restore(flags); + } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } + + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + + /* Set Receive fifo depth */ + rx_watermark = msg->len; + if (rx_watermark > IIC_RX_FIFO_DEPTH) { + rfd_set = IIC_RX_FIFO_DEPTH - 1; + } else if ((rx_watermark == 1) || (rx_watermark == 0)) { + rfd_set = rx_watermark - 1; + /* Handle single byte transfer separately */ + cr |= XIIC_CR_NO_ACK_MASK; + } else { + rfd_set = rx_watermark - 2; + } + + /* Check if RSTA should be set */ + if (cr & XIIC_CR_MSMS_MASK) { + /* Already a master, RSTA should be set */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_REPEATED_START_MASK) & + ~(XIIC_CR_DIR_IS_TX_MASK)); + } + + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); + + /* Clear and enable Rx full and transmit complete interrupts */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK); + + /* Write the address */ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, - i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); + i2c_8bit_addr_from_msg(msg)); - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + /* Write to Control Register,to start transaction in Rx mode */ + if ((cr & XIIC_CR_MSMS_MASK) == 0) { + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_MSMS_MASK) + & ~(XIIC_CR_DIR_IS_TX_MASK)); + } - xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, - msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); - local_irq_restore(flags); + dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + } if (i2c->nmsgs == 1) /* very last, enable bus not busy as well */ @@ -590,10 +795,17 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* the message is tx:ed */ i2c->tx_pos = msg->len; + + /* Enable interrupts */ + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); + + i2c->prev_msg_tx = false; } static void xiic_start_send(struct xiic_i2c *i2c) { + u8 cr = 0; + u16 data; struct i2c_msg *msg = i2c->tx_msg; xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); @@ -604,22 +816,71 @@ static void xiic_start_send(struct xiic_i2c *i2c) __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); - if (!(msg->flags & I2C_M_NOSTART)) { - /* write the address */ - u16 data = i2c_8bit_addr_from_msg(msg) | - XIIC_TX_DYN_START_MASK; - if ((i2c->nmsgs == 1) && msg->len == 0) - /* no data and last message -> add STOP */ - data |= XIIC_TX_DYN_STOP_MASK; + if (i2c->dynamic) { + if (!(msg->flags & I2C_M_NOSTART)) { + /* write the address */ + data = i2c_8bit_addr_from_msg(msg) | + XIIC_TX_DYN_START_MASK; + + if (i2c->nmsgs == 1 && msg->len == 0) + /* no data and last message -> add STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } + + xiic_fill_tx_fifo(i2c); + + /* Clear any pending Tx empty, Tx Error and then enable them */ + xiic_irq_clr_en(i2c, (XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK)); + } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } + /* Check if RSTA should be set */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + if (cr & XIIC_CR_MSMS_MASK) { + /* Already a master, RSTA should be set */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_REPEATED_START_MASK | + XIIC_CR_DIR_IS_TX_MASK) & + ~(XIIC_CR_NO_ACK_MASK)); + } + + /* Write address to FIFO */ + data = i2c_8bit_addr_from_msg(msg); xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); - } + /* Fill fifo */ + xiic_std_fill_tx_fifo(i2c); - xiic_fill_tx_fifo(i2c); + if ((cr & XIIC_CR_MSMS_MASK) == 0) { - /* Clear any pending Tx empty, Tx Error and then enable them. */ - xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK); + /* Start Tx by writing to CR */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | + XIIC_CR_MSMS_MASK | + XIIC_CR_DIR_IS_TX_MASK); + } + + /* Clear any pending Tx empty, Tx Error and then enable them */ + xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK); + } + i2c->prev_msg_tx = true; } static irqreturn_t xiic_isr(int irq, void *dev_id) @@ -703,7 +964,7 @@ static int xiic_start_xfer(struct xiic_i2c *i2c) static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { struct xiic_i2c *i2c = i2c_get_adapdata(adap); - int err; + int err, count; dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); @@ -719,6 +980,21 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) i2c->tx_msg = msgs; i2c->nmsgs = num; + /* Decide standard mode or Dynamic mode */ + i2c->dynamic = true; + + /* Initialize prev message type */ + i2c->prev_msg_tx = false; + + /* Enter standard mode only when read length is > 255 bytes */ + for (count = 0; count < i2c->nmsgs; count++) { + if ((i2c->tx_msg[count].flags & I2C_M_RD) && + i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC) { + i2c->dynamic = false; + break; + } + } + err = xiic_start_xfer(i2c); if (err < 0) { dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); @@ -752,16 +1028,11 @@ static const struct i2c_algorithm xiic_algorithm = { .functionality = xiic_func, }; -static const struct i2c_adapter_quirks xiic_quirks = { - .max_read_len = 255, -}; - static const struct i2c_adapter xiic_adapter = { .owner = THIS_MODULE, .name = DRIVER_NAME, .class = I2C_CLASS_DEPRECATED, .algo = &xiic_algorithm, - .quirks = &xiic_quirks, }; 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Sat, 26 Jun 2021 03:28:27 -0700 Envelope-to: git@xilinx.com, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, marex@denx.de, joe@perches.com Received: from [10.140.6.6] (port=55646 helo=xhdappanad40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lx5Y2-000AWJ-Nr; Sat, 26 Jun 2021 03:28:27 -0700 From: Raviteja Narayanam To: , CC: , , , , , Raviteja Narayanam Subject: [PATCH v2 04/10] i2c: xiic: Remove interrupt enable/disable in Rx path Date: Sat, 26 Jun 2021 15:58:00 +0530 Message-ID: <20210626102806.15402-5-raviteja.narayanam@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> References: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2a1765c1-4eba-4c52-13a1-08d9388d2b67 X-MS-TrafficTypeDiagnostic: DM5PR02MB3339: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2021 10:28:41.8435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a1765c1-4eba-4c52-13a1-08d9388d2b67 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0005.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB3339 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org As the 'DYNAMIC_MODE_READ_BROKEN_BIT' quirk is added in the driver, we no longer enter dynamic mode for the effected IP versions. So, remove local_irq_save/local_irq_restore APIs from driver. Signed-off-by: Raviteja Narayanam --- drivers/i2c/busses/i2c-xiic.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index c31d0d0a8384..72c46cdfa712 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -691,7 +691,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) u16 rx_watermark; u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; - unsigned long flags; dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), @@ -722,7 +721,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); - local_irq_save(flags); if (!(msg->flags & I2C_M_NOSTART)) /* write the address */ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, @@ -736,7 +734,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) val |= msg->len; xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); - local_irq_restore(flags); } else { /* * If previous message is Tx, make sure that Tx FIFO is empty From patchwork Sat Jun 26 10:28:02 2021 Content-Type: text/plain; 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Sat, 26 Jun 2021 03:28:37 -0700 Envelope-to: git@xilinx.com, linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, marex@denx.de, joe@perches.com Received: from [10.140.6.6] (port=55646 helo=xhdappanad40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lx5YC-000AWJ-9s; Sat, 26 Jun 2021 03:28:36 -0700 From: Raviteja Narayanam To: , CC: , , , , , Raviteja Narayanam Subject: [PATCH v2 06/10] i2c: xiic: Update compatible with new IP version Date: Sat, 26 Jun 2021 15:58:02 +0530 Message-ID: <20210626102806.15402-7-raviteja.narayanam@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> References: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f0672b42-0d4c-451a-76ab-08d9388d2dae X-MS-TrafficTypeDiagnostic: BN8PR02MB5748: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1122; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2021 10:28:45.6788 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0672b42-0d4c-451a-76ab-08d9388d2dae X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0005.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR02MB5748 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads. Older IPs are handled with a workaround in which they are using xiic standard mode for all these effected use cases. Added the new IP version to compatible. Signed-off-by: Raviteja Narayanam --- drivers/i2c/busses/i2c-xiic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 72c46cdfa712..007a78215a90 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -1058,6 +1058,7 @@ static const struct xiic_version_data xiic_2_00 = { #if defined(CONFIG_OF) static const struct of_device_id xiic_of_match[] = { { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, + { .compatible = "xlnx,axi-iic-2.1", }, {}, }; MODULE_DEVICE_TABLE(of, xiic_of_match); From patchwork Sat Jun 26 10:28:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Narayanam X-Patchwork-Id: 467607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 084BAC49EA6 for ; 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Sat, 26 Jun 2021 03:28:45 -0700 From: Raviteja Narayanam To: , CC: , , , , , Shubhrajyoti Datta , Raviteja Narayanam Subject: [PATCH v2 08/10] i2c: xiic: Fix the type check for xiic_wakeup Date: Sat, 26 Jun 2021 15:58:04 +0530 Message-ID: <20210626102806.15402-9-raviteja.narayanam@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> References: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: abee86ec-1002-4232-a31b-08d9388d33c0 X-MS-TrafficTypeDiagnostic: SN6PR02MB5230: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ufj0jL+PuPvtO0v63smS9DPqPy46FreY7+NGAZyZT6OY9myw386VPZxWeljybwoWBeqb3TeCpQKhXgs3Jp8Wu91bPS1APZjUCNS25pfdHFeiQns9KkZWKZyefIZt1Ujcyb0NsKXPg3N8kVaEQJLsBQc2NPwKAwbM+QrKiJI2ZuJHBraKtLKf3z73/CH7Se2xZTv/L4dAxclpXC25nUtPoHaTfNfreXB/FudGBqZ4iMdgFi1w39YFk/zxlSV1kbdpBqIE/gShEIRIXg1jDMWqvI3oMVmJJxrpyCjbDXWuEZx38UJvDR+MqIg7wzzEOj1i8+N9MXdcr/z65eSMBHlq0spV6uGRyfLl3lTzgcYzSaoUXG02VNdtvCHasx1oQUK4BHV4dVCg/DzYDWTuJ2L01/CnXtjRZ0oG2jSX0YKIWn207pYoU8odt59zwe/JLCuhBb8XkD9wfEWrIbXbQ47xoEMFEE3CklMqscSBHusJTuaeQtnOjhG0Zv2bA4XHjCYXQVFYWJ+r23G/f1z6MBAR+l9DJpQDqs9rzmrXOnYj70FI0ZwONI2+PfWASOvJP2UuOOiCdUVudt2VLnJAwXC4SkY80X2Z5W4IWSq963RMpZycC3eRRCDSKhqllSXGVg4cOa0Jqjgoo9gAQUuc5mFX/P9AUc6hqU0P+eHQ+1AVmHfne3PU4uFUHF98K1VkRMfHWdhXSk2iNCS0Qg0qAvshGScNlb98XTrvlbYQ8H3hiwM= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(376002)(39860400002)(136003)(396003)(346002)(46966006)(36840700001)(110136005)(4744005)(7696005)(316002)(36860700001)(107886003)(1076003)(356005)(2616005)(426003)(336012)(9786002)(70206006)(6636002)(5660300002)(70586007)(7636003)(82310400003)(478600001)(6666004)(36906005)(4326008)(44832011)(186003)(82740400003)(54906003)(83380400001)(26005)(36756003)(47076005)(8936002)(8676002)(2906002)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2021 10:28:55.8633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abee86ec-1002-4232-a31b-08d9388d33c0 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0005.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5230 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Shubhrajyoti Datta Fix the coverity warning mixed_enum_type: enumerated type mixed with another type We are passing an enum in the xiic_wakeup lets change the function parameters to reflect that. Signed-off-by: Shubhrajyoti Datta Signed-off-by: Raviteja Narayanam --- drivers/i2c/busses/i2c-xiic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 0d76261f1841..3e81ec08b001 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -490,7 +490,7 @@ static void xiic_send_tx(struct xiic_i2c *i2c) } } -static void xiic_wakeup(struct xiic_i2c *i2c, int code) +static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) { i2c->tx_msg = NULL; i2c->rx_msg = NULL; From patchwork Sat Jun 26 10:28:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Narayanam X-Patchwork-Id: 467606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6729CC49EA5 for ; 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Sat, 26 Jun 2021 03:29:02 -0700 From: Raviteja Narayanam To: , CC: , , , , , Raviteja Narayanam Subject: [PATCH v2 10/10] i2c: xiic: Add smbus_block_read functionality Date: Sat, 26 Jun 2021 15:58:06 +0530 Message-ID: <20210626102806.15402-11-raviteja.narayanam@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> References: <20210626102806.15402-1-raviteja.narayanam@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ccc7fc19-5a25-4549-e0fe-08d9388d40d6 X-MS-TrafficTypeDiagnostic: DM6PR02MB7098: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: t95PndNEtNYswBD17tlWxm5K2WuK05Q4VzQbB89f0Wgu3nxdYeTPADMKWuLnJ31g/vL5BH+ybXNFmb+IlGOk7QjytA9K07fshcTssccCkeXRc9StconoofI2/GlNapi5xDKq9uwbOztB/dscWn6shkfC9qqEk9LJhsScM5lFt48/4/7YH96jT+ZCQ4Hfdlkq6g6Kb4cIQxrnVHRQUO+Yi8IUJcaP4XcpQT672eIA6KBw5yzmI5zjfRbP4hDaPBlCcGBtXgUryfJVZYKrM4OdX4xFCIvq6HxEpOV6chs/OFzdFtjvFkutZWKfNoo150CoKxH4UMQyU/w1vH1s0jixW8B8Ja3y+SQfT6fCLJQujoLSLU/9RBjdUBUCcw2RrJPG2CS3OmeQEmAUtgoyedExcbfuMIWONqYB8QYyy3y0mn6bzizWOvyfrXHWQhhI7poWeDrcKixiYKPCgtc7CwBu2ziyFy7pxLmfayUNVLoeJ45tVZ2+7lHk4GN4KYyfITJyNtY1fN3hGpyBuDGaK2DwPMAInq8lLBGknhT7/1oOUt8qx/YgOEXdY6s3/6yIHPylPW165YuU3abm8a3ATvOVAVPkSEuTOXc6e1mVH5zid4arjoy2RhOgzmnBsvd3BrX4mbJiGqi67npZJWbXApnIozBeIjXjjMbS39VNk5EGV4zfyAgYrSUW0BlRBU+G5vTTXvdNuvGdiJui25wA37SdQA== X-Forefront-Antispam-Report: CIP:149.199.62.198; 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Since the number of bytes to read is not known prior to transfer, we are using xiic standard mode for low level control of IP. Signed-off-by: Raviteja Narayanam --- drivers/i2c/busses/i2c-xiic.c | 80 ++++++++++++++++++++++++++++++++--- 1 file changed, 74 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 26fc174b8e95..931b9bce87fe 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -65,6 +65,7 @@ enum xiic_endian { * @dynamic: Mode of controller * @prev_msg_tx: Previous message is Tx * @quirks: To hold platform specific bug info + * @smbus_block_read: Flag to handle block read */ struct xiic_i2c { struct device *dev; @@ -84,6 +85,7 @@ struct xiic_i2c { bool dynamic; bool prev_msg_tx; u32 quirks; + bool smbus_block_read; }; struct xiic_version_data { @@ -344,6 +346,54 @@ static void xiic_deinit(struct xiic_i2c *i2c) xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); } +static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) +{ + u8 rxmsg_len; + u8 rfd_set = 0; + + /* + * Clear the I2C_M_RECV_LEN flag to avoid setting + * message length again + */ + i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; + + /* Set smbus_block_read flag to identify in isr */ + i2c->smbus_block_read = true; + + /* Read byte from rx fifo and set message length */ + rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + + i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; + + /* Check if received length is valid */ + if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) { + /* Set Receive fifo depth */ + if (rxmsg_len > IIC_RX_FIFO_DEPTH) { + rfd_set = IIC_RX_FIFO_DEPTH - 1; + i2c->rx_msg->len = rxmsg_len + 1; + } else if ((rxmsg_len == 1) || + (rxmsg_len == 0)) { + /* + * Minimum of 3 bytes required to exit cleanly. 1 byte + * already received, Second byte is being received. Have + * to set NACK in read_rx before receiving the last byte + */ + i2c->rx_msg->len = 3; + } else { + rfd_set = rxmsg_len - 2; + i2c->rx_msg->len = rxmsg_len + 1; + } + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); + + return; + } + + /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */ + i2c->tx_msg->len = 3; + i2c->smbus_block_read = false; + dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); +} + static void xiic_read_rx(struct xiic_i2c *i2c) { u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; @@ -366,6 +416,12 @@ static void xiic_read_rx(struct xiic_i2c *i2c) if (!i2c->dynamic) { bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; + /* Set msg length if smbus_block_read */ + if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { + xiic_smbus_block_read_setup(i2c); + return; + } + if (bytes_rem > IIC_RX_FIFO_DEPTH) { bytes_to_read = bytes_in_fifo; } else if (bytes_rem > 1) { @@ -638,6 +694,12 @@ static irqreturn_t xiic_process(int irq, void *dev_id) /* The bus is not busy, disable BusNotBusy interrupt */ xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); + if (i2c->tx_msg && i2c->smbus_block_read) { + i2c->smbus_block_read = false; + /* Set requested message len=1 to indicate STATE_DONE */ + i2c->tx_msg->len = 1; + } + if (!i2c->tx_msg) goto out; @@ -763,8 +825,12 @@ static void xiic_start_recv(struct xiic_i2c *i2c) rfd_set = IIC_RX_FIFO_DEPTH - 1; } else if ((rx_watermark == 1) || (rx_watermark == 0)) { rfd_set = rx_watermark - 1; - /* Handle single byte transfer separately */ - cr |= XIIC_CR_NO_ACK_MASK; + + /* Set No_ACK, except for smbus_block_read */ + if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { + /* Handle single byte transfer separately */ + cr |= XIIC_CR_NO_ACK_MASK; + } } else { rfd_set = rx_watermark - 2; } @@ -971,7 +1037,7 @@ static int xiic_start_xfer(struct xiic_i2c *i2c) static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { - bool broken_read, max_read_len; + bool broken_read, max_read_len, smbus_blk_read; struct xiic_i2c *i2c = i2c_get_adapdata(adap); int err, count; @@ -996,20 +1062,22 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) i2c->prev_msg_tx = false; /* - * Scan through nmsgs, use dynamic mode when none of the below two + * Scan through nmsgs, use dynamic mode when none of the below three * conditions occur. We need standard mode even if one condition holds * true in the entire array of messages in a single transfer. * If read transaction as dynamic mode is broken for delayed reads * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. * If read length is > 255 bytes. + * If smbus_block_read transaction. */ for (count = 0; count < i2c->nmsgs; count++) { broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && (i2c->tx_msg[count].flags & I2C_M_RD); max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); + smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); - if (broken_read || max_read_len) { + if (broken_read || max_read_len || smbus_blk_read) { i2c->dynamic = false; break; } @@ -1040,7 +1108,7 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) static u32 xiic_func(struct i2c_adapter *adap) { - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; } static const struct i2c_algorithm xiic_algorithm = {