From patchwork Tue Aug 14 22:14:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 144252 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp104281ljj; Tue, 14 Aug 2018 15:14:33 -0700 (PDT) X-Google-Smtp-Source: AA+uWPya4dM7tHtoqG9sNgn5FG8R1S5MT9ekTIS0lhLyVWEp7ImjM7Bzw2+0gDclAJv0WFzkMAJY X-Received: by 2002:a17:902:4403:: with SMTP id k3-v6mr21598200pld.243.1534284872914; Tue, 14 Aug 2018 15:14:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534284872; cv=none; d=google.com; s=arc-20160816; b=QREpaETsBXW4n55ysNcXVKB9M0PAYu7rMWT4zukyMnC02vri5Ng9omBWy+zoTpjwzJ cVl7RjJD7mWFpZopjXJwXmyv3GNG2Cv6i7YTLXXVLcEVKRN33uEfVYqFkio+Bg8w6le0 v2JrTkpkEl9GJA0Ko44N0iWzc7hj7USX3DuvUsP6WMZjduqcPr09T6Yy1862fDEtYRLN q1T/kfs5O187gdTUySxZtDAEjDlBMtuwssjldmnHHhsrEH9RNuhvSRqNGXd0t4SQVfWm bZk4HiNLNu2lg82BaxHJd+78VdrZm6Utx45Ug8UgRvn32gxxdM1M5AQ1ck743/kC5hqO xjAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=ESncSgmCF65uR5Mjzqxtn9ajR1WbAE7v81L5WJOABy4=; b=rc/vmcChbXMsclpqT72rJCI6QrSEz7l5lw0U2M/YybzpK/1pW8RD/gr9uvUQCpxJ5f /Eiuz7v+hkOmmPCxzXv9EB8XFxDkWBvtPMGpUW0CXGI/F5BTIpWHWpFN8Bf+aBIl6ML/ As1oEfvI/x4uMv0ftgSS95UVg3TOq2eXTOwrRRo6hXaBcT2XvNV/eAvA4cl5EXTbhni5 44n1XqMAb9/pfl9yFkogu/f2z8Tb5DbRGvcjCJ61109pa9paJwFnSbkVDnT7/DxvtpfW MKpOS3QT0pcDS78xuEBTMrzAy08T9DeLMY6MhmrCP6w+LWctxiF/58JbymlG/Fxf8h5/ JXQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OxtBixD2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id m1-v6sm7858231iok.81.2018.08.14.15.14.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Aug 2018 15:14:28 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] coresight: etb10: Refactor etb_drvdata::mode handling Date: Tue, 14 Aug 2018 16:14:25 -0600 Message-Id: <1534284866-2523-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch moves the etb_drvdata::mode from a locat_t to a simple u32, as it is for the ETF and ETR drivers. This streamlines the code and adds commonality with the other drivers when dealing with similar operations. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 62 +++++++++++++++------------ 1 file changed, 34 insertions(+), 28 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 9fd77fdc1244..69287163ce4e 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -5,7 +5,6 @@ * Description: CoreSight Embedded Trace Buffer driver */ -#include #include #include #include @@ -72,8 +71,8 @@ * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @spinlock: only one at a time pls. * @reading: synchronise user space access to etb buffer. - * @mode: this ETB is being used. * @buf: area of memory where ETB buffer content gets sent. + * @mode: this ETB is being used. * @buffer_depth: size of @buf. * @trigger_cntr: amount of words to store after a trigger. */ @@ -85,8 +84,8 @@ struct etb_drvdata { struct miscdevice miscdev; spinlock_t spinlock; local_t reading; - local_t mode; u8 *buf; + u32 mode; u32 buffer_depth; u32 trigger_cntr; }; @@ -138,44 +137,48 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) { int ret = 0; - u32 val; unsigned long flags; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - /* - * We don't have an internal state to clean up if we fail to setup - * the perf buffer. So we can perform the step before we turn the - * ETB on and leave without cleaning up. - */ - if (mode == CS_MODE_PERF) { - ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); - if (ret) - goto out; - } + spin_lock_irqsave(&drvdata->spinlock, flags); - val = local_cmpxchg(&drvdata->mode, - CS_MODE_DISABLED, mode); /* * When accessing from Perf, a HW buffer can be handled * by a single trace entity. In sysFS mode many tracers * can be logging to the same HW buffer. */ - if (val == CS_MODE_PERF) - return -EBUSY; + if (drvdata->mode == CS_MODE_PERF) { + ret = -EBUSY; + goto out; + } /* Don't let perf disturb sysFS sessions */ - if (val == CS_MODE_SYSFS && mode == CS_MODE_PERF) - return -EBUSY; + if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_PERF) { + ret = -EBUSY; + goto out; + } /* Nothing to do, the tracer is already enabled. */ - if (val == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_SYSFS) goto out; - spin_lock_irqsave(&drvdata->spinlock, flags); + /* + * We don't have an internal state to clean up if we fail to setup + * the perf buffer. So we can perform the step before we turn the + * ETB on and leave without cleaning up. + */ + if (mode == CS_MODE_PERF) { + ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); + if (ret) + goto out; + } + + drvdata->mode = mode; etb_enable_hw(drvdata); - spin_unlock_irqrestore(&drvdata->spinlock, flags); out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + if (!ret) dev_dbg(drvdata->dev, "ETB enabled\n"); return ret; @@ -277,11 +280,14 @@ static void etb_disable(struct coresight_device *csdev) unsigned long flags; spin_lock_irqsave(&drvdata->spinlock, flags); - etb_disable_hw(drvdata); - etb_dump_hw(drvdata); - spin_unlock_irqrestore(&drvdata->spinlock, flags); - local_set(&drvdata->mode, CS_MODE_DISABLED); + /* Disable the ETB only if it needs to */ + if (drvdata->mode != CS_MODE_DISABLED) { + etb_disable_hw(drvdata); + etb_dump_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; + } + spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "ETB disabled\n"); } @@ -488,7 +494,7 @@ static void etb_dump(struct etb_drvdata *drvdata) unsigned long flags; spin_lock_irqsave(&drvdata->spinlock, flags); - if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { + if (drvdata->mode == CS_MODE_SYSFS) { etb_disable_hw(drvdata); etb_dump_hw(drvdata); etb_enable_hw(drvdata); From patchwork Tue Aug 14 22:14:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 144253 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp104304ljj; Tue, 14 Aug 2018 15:14:35 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyPmsa8a21iXPW2mPm+LAqEf6x9Yaz6KXcJ5GMMTGECIz3UsXeF94gvexz58+XfKge/4D0j X-Received: by 2002:a62:4add:: with SMTP id c90-v6mr25315723pfj.23.1534284875582; Tue, 14 Aug 2018 15:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534284875; cv=none; d=google.com; s=arc-20160816; b=DIamVaWq1YybI3b54zND0GwfmG7TW3B2/tTBovPvr71soJ6nbRv6p2l4EopfEPKFzh J/KvQaV/0Gvb15W+jyWoypojCQYWdhcg36ZOmSdTQlZOqfi92QHph93dSbvOFcNo2P8E 6O7qMJ46CqmO2GA1VsdY+GnwNhQZjVEFDJJfVPYeiUoElWdtktdxoNgS3kch0EzW7N7Y lcQuZuu5sVeOaQq/3RJxGVZHNEBGPcDkmaClSciW7R+OPkQYrnCJ/Y/8bcopCM++B4VI /+EkoxleL9BfQSlKg/gm4uH5v/93Yf362og9ZlTvGhd3fN0q05w4W4EehE/d+mMTTSud wUcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=n51nv7HwDkyeWHHsQ0Nv037MqvdoJ65KhHly2Ldym/Y=; b=JEUOrKAbkLzdTok/0pH69zrQb25+mw5g4ES3ZC7Z56Q3J4fOf5sYeUO0pCubkeXxDi wAit+tHPedlWXTj8A8QfGBPs4xvpUFwYA4DZ82DODesW40Bgehk3LDJEuASeohkPn7fI fMqC3YKS1UVDLNIaueOHCkNagD/0UDI36EAo/mx4xUPxY0HlXrb7O/YbSJa6in6GBRZb RgdRj5Ggf32rN/c0ruq8g3yhYGAbWbXJNN91N68aUFStM6KaOBpvTOPePSkpw5WtuwaA HrRBBvUfwQRHau1+IRkUa85Z5quQHDWEh76f7ddm+yJ+loIv5ISHvEIJMMPH//km70Fj RP1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UxIhyTxw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id m1-v6sm7858231iok.81.2018.08.14.15.14.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Aug 2018 15:14:29 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] coresight: etb10: Splitting function etb_enable() Date: Tue, 14 Aug 2018 16:14:26 -0600 Message-Id: <1534284866-2523-2-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534284866-2523-1-git-send-email-mathieu.poirier@linaro.org> References: <1534284866-2523-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Up until now the relative simplicity of enabling the ETB made it possible to accommodate processing for both sysFS and perf methods. But work on claimtags and CPU-wide trace scenarios is adding some complexity, making the current code messy and hard to maintain. As such follow what has been done for ETF and ETR components and split function etb_enable() so that processing for both API can be done cleanly. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 73 +++++++++++++++++++-------- 1 file changed, 52 insertions(+), 21 deletions(-) -- 2.7.4 Reviewed-by: Suzuki K Poulose diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 69287163ce4e..08fa660098f8 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -134,7 +134,7 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) +static int etb_enable_sysfs(struct coresight_device *csdev) { int ret = 0; unsigned long flags; @@ -142,48 +142,79 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) spin_lock_irqsave(&drvdata->spinlock, flags); - /* - * When accessing from Perf, a HW buffer can be handled - * by a single trace entity. In sysFS mode many tracers - * can be logging to the same HW buffer. - */ + /* Don't messup with perf sessions. */ if (drvdata->mode == CS_MODE_PERF) { ret = -EBUSY; goto out; } - /* Don't let perf disturb sysFS sessions */ - if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_PERF) { - ret = -EBUSY; + /* Nothing to do, the tracer is already enabled. */ + if (drvdata->mode == CS_MODE_SYSFS) goto out; - } - /* Nothing to do, the tracer is already enabled. */ - if (drvdata->mode == CS_MODE_SYSFS && mode == CS_MODE_SYSFS) + drvdata->mode = CS_MODE_SYSFS; + etb_enable_hw(drvdata); + +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; +} + +static int etb_enable_perf(struct coresight_device *csdev, void *data) +{ + int ret = 0; + unsigned long flags; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* No need to continue if the component is already in use. */ + if (drvdata->mode != CS_MODE_DISABLED) { + ret = -EBUSY; goto out; + } /* * We don't have an internal state to clean up if we fail to setup * the perf buffer. So we can perform the step before we turn the * ETB on and leave without cleaning up. */ - if (mode == CS_MODE_PERF) { - ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); - if (ret) - goto out; - } + ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); + if (ret) + goto out; - drvdata->mode = mode; + drvdata->mode = CS_MODE_PERF; etb_enable_hw(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); - - if (!ret) - dev_dbg(drvdata->dev, "ETB enabled\n"); return ret; } +static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + int ret; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + switch (mode) { + case CS_MODE_SYSFS: + ret = etb_enable_sysfs(csdev); + break; + case CS_MODE_PERF: + ret = etb_enable_perf(csdev, data); + break; + default: + ret = -EINVAL; + break; + } + + if (ret) + return ret; + + dev_dbg(drvdata->dev, "ETB enabled\n"); + return 0; +} + static void etb_disable_hw(struct etb_drvdata *drvdata) { u32 ffcr;