From patchwork Fri Jun 25 12:33:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466848 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1417212jao; Fri, 25 Jun 2021 05:34:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBgrF0BGcM47L2moZYLgpvHTxbiwsLSJ7OWmptPqRQaeAUVSKk2rCBNFzrqitGr1ob+no5 X-Received: by 2002:a17:906:4b15:: with SMTP id y21mr10543985eju.261.1624624461815; Fri, 25 Jun 2021 05:34:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624461; cv=none; d=google.com; s=arc-20160816; b=MeeeFitlcgU2jEtOLg097HHXUlIWA0jKAK41FRapka9OaB6bK/NFkVQPIaBeXFGrZL QLglmVydX+UMiH+CBfPFbs9DuOq06WDlBcyfVijnHS1Vwcazbul6L6LgeoRIve8r7ih/ 6nSVY4uStolg9XhyydaqKAf6B237YS1edTqj3W+XPq+x6waqKOeJHxcUhv1kvLMdSzdA +9jfZgZloWYGk55FN03MuAUvXgzs0wS4cDNdpzQFV3uPT9vULhevTnL4tANgYpxrzTch KgTGkvFP2Y2pImi47ZfwZ0EC7z7ZkWFS0zxNM8E2kzd/hEKn4DpYwAJ9C3Lhifx158vr /kDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hj7+vE89NLcN6VtiJk8liEDNDGGaHkJP2vUV3wC5YME=; b=xlQ3CQ6wryjlvzG9luCNPd5DhdJbI98EBsZp5JSL0mYhsJfXsK8IBSqBqGPoUVh/2C ATnmGQRynQYsGltCT0u2kUYPy1lSQviIY8PC0l7xt9fst5goTpZyUktyuNT15tQ8PIpD Y5tu8h+ISr7dZdjnDOz8x941W4jFlKQILUvRmFzP4k8Yptyubxr1cyoNsUAdmmm0VSIO gQ1I/q22RsZpKKmQZLTzmnI6W6sFetjVtGUJ5KDhQhuzNgiOoK5APzNJRC0NL/ti/0F2 /fRfj9FI3UwWH8n1MWpEGPJTvLtEv5zcRPMcmpZ0bSqPVmh2sdMJIw1i7dOUw2tTx1i1 lBFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hiT+ldac; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ec39si5821899edb.37.2021.06.25.05.34.21; Fri, 25 Jun 2021 05:34:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hiT+ldac; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229712AbhFYMgj (ORCPT + 17 others); Fri, 25 Jun 2021 08:36:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231465AbhFYMgi (ORCPT ); Fri, 25 Jun 2021 08:36:38 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0024C061767 for ; Fri, 25 Jun 2021 05:34:16 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id i6so7958668pfq.1 for ; Fri, 25 Jun 2021 05:34:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hj7+vE89NLcN6VtiJk8liEDNDGGaHkJP2vUV3wC5YME=; b=hiT+ldacaYWUgBD9Aop2Z0rZq+1KBV2BrcyDluGMooPqHzj4xQEhy91jM41LMO40YL 5h23h+xhkWLqhSCIjniylNnTByCSIIPo5i/GcOyzSV8ku/xM2Pc94fZYy6mdfrPjGPuu bGQvSGWYNuoWN7hHfAIfRaMlffyRK9jqlfBvhAdvu01b2YRp2uZih7PLh3osBYmcy1d8 zasIV9yTEc8Z9sG+QBLJgSo4j+yTKe8yxI6RKuxh2dsW9oFIEMKefv5mlSoT7O015vle G5tzqe3JNIfmCekQnh8ddk4wW4MckttCW4MPTtnTXT9OLHXtIjm3HXDVBONstSdB87Jt RcXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hj7+vE89NLcN6VtiJk8liEDNDGGaHkJP2vUV3wC5YME=; b=c6GiAIGQ83ZbwvY8A968CRiVVqcSkyfAWAEnVXUOUR+nCTpmIxT08JkpKiRdFe7wds zaKX5FhSDbswZ+iLxNwd9Wgz05gso3SjnBcTivcCATnJWIOTBPt5+o1vIDHVNqcmQzRi qYv4kUl3mFnnP0HEs+7jjEyEYyLZM8yI9PfJYYlKn35MkKeVt//lPyhdYnKgPU/q6nCR /hRcqwxdJG9018RXzgVygbz9P6xmSVTGI7wmmGJ9yDJ134BKGIO2Zwg9lkTY8BB2nko+ fW3JCgofqpfyh0H71Tu94/m7/6g3V/FOpjRDS7XntPbXXqNw13tQneHSS7ieXO++Hjza +yqw== X-Gm-Message-State: AOAM531P+wIPfyNTECpwbaeIKpsyorK8g55CGxlHN38OzehPHgC7mM6Z KiXnxcZxxGXzl11qR5oJGWJj X-Received: by 2002:a05:6a00:810:b029:301:f08c:6b0d with SMTP id m16-20020a056a000810b0290301f08c6b0dmr10387776pfk.8.1624624456392; Fri, 25 Jun 2021 05:34:16 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:600b:2a0:ed5d:53e7:c64e:1bac]) by smtp.gmail.com with ESMTPSA id y7sm6077780pfy.153.2021.06.25.05.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 05:34:15 -0700 (PDT) From: Manivannan Sadhasivam To: gregkh@linuxfoundation.org Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, loic.poulain@linaro.org, kvalo@codeaurora.org, ath11k@lists.infradead.org, Manivannan Sadhasivam , Jakub Kicinski Subject: [PATCH 01/10] bus: mhi: Add inbound buffers allocation flag Date: Fri, 25 Jun 2021 18:03:46 +0530 Message-Id: <20210625123355.11578-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> References: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Loic Poulain Currently, the MHI controller driver defines which channels should have their inbound buffers allocated and queued. But ideally, this is something that should be decided by the MHI device driver instead, which actually deals with that buffers. Add a flag parameter to mhi_prepare_for_transfer allowing to specify if buffers have to be allocated and queued by the MHI stack. Keep auto_queue flag for now, but should be removed at some point. Signed-off-by: Loic Poulain Tested-by: Bhaumik Bhatt Reviewed-by: Bhaumik Bhatt Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Acked-by: Jakub Kicinski Link: https://lore.kernel.org/r/1624566520-20406-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/core/internal.h | 2 +- drivers/bus/mhi/core/main.c | 9 ++++++--- drivers/net/mhi/net.c | 2 +- drivers/net/wwan/mhi_wwan_ctrl.c | 2 +- include/linux/mhi.h | 7 ++++++- net/qrtr/mhi.c | 2 +- 6 files changed, 16 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h index 5b9ea66b92dc..bc239a11aa69 100644 --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h @@ -682,7 +682,7 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, struct image_info *img_info); void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl); int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan); + struct mhi_chan *mhi_chan, unsigned int flags); int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan); void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index 22acde118bc3..69cd9dcde6d8 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -1423,7 +1423,7 @@ static void mhi_unprepare_channel(struct mhi_controller *mhi_cntrl, } int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, - struct mhi_chan *mhi_chan) + struct mhi_chan *mhi_chan, unsigned int flags) { int ret = 0; struct device *dev = &mhi_chan->mhi_dev->dev; @@ -1448,6 +1448,9 @@ int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, if (ret) goto error_pm_state; + if (mhi_chan->dir == DMA_FROM_DEVICE) + mhi_chan->pre_alloc = !!(flags & MHI_CH_INBOUND_ALLOC_BUFS); + /* Pre-allocate buffer for xfer ring */ if (mhi_chan->pre_alloc) { int nr_el = get_nr_avail_ring_elements(mhi_cntrl, @@ -1603,7 +1606,7 @@ void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan) } /* Move channel to start state */ -int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) +int mhi_prepare_for_transfer(struct mhi_device *mhi_dev, unsigned int flags) { int ret, dir; struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; @@ -1614,7 +1617,7 @@ int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) if (!mhi_chan) continue; - ret = mhi_prepare_channel(mhi_cntrl, mhi_chan); + ret = mhi_prepare_channel(mhi_cntrl, mhi_chan, flags); if (ret) goto error_open_chan; } diff --git a/drivers/net/mhi/net.c b/drivers/net/mhi/net.c index 0d8293a47a56..774e32960e09 100644 --- a/drivers/net/mhi/net.c +++ b/drivers/net/mhi/net.c @@ -327,7 +327,7 @@ static int mhi_net_probe(struct mhi_device *mhi_dev, u64_stats_init(&mhi_netdev->stats.tx_syncp); /* Start MHI channels */ - err = mhi_prepare_for_transfer(mhi_dev); + err = mhi_prepare_for_transfer(mhi_dev, 0); if (err) goto out_err; diff --git a/drivers/net/wwan/mhi_wwan_ctrl.c b/drivers/net/wwan/mhi_wwan_ctrl.c index 1bc6b69aa530..1e18420ce404 100644 --- a/drivers/net/wwan/mhi_wwan_ctrl.c +++ b/drivers/net/wwan/mhi_wwan_ctrl.c @@ -110,7 +110,7 @@ static int mhi_wwan_ctrl_start(struct wwan_port *port) int ret; /* Start mhi device's channel(s) */ - ret = mhi_prepare_for_transfer(mhiwwan->mhi_dev); + ret = mhi_prepare_for_transfer(mhiwwan->mhi_dev, 0); if (ret) return ret; diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 944aa3aa3035..5e08468854db 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -719,8 +719,13 @@ void mhi_device_put(struct mhi_device *mhi_dev); * host and device execution environments match and * channels are in a DISABLED state. * @mhi_dev: Device associated with the channels + * @flags: MHI channel flags */ -int mhi_prepare_for_transfer(struct mhi_device *mhi_dev); +int mhi_prepare_for_transfer(struct mhi_device *mhi_dev, + unsigned int flags); + +/* Automatically allocate and queue inbound buffers */ +#define MHI_CH_INBOUND_ALLOC_BUFS BIT(0) /** * mhi_unprepare_from_transfer - Reset UL and DL channels for data transfer. diff --git a/net/qrtr/mhi.c b/net/qrtr/mhi.c index fa611678af05..29b4fa3b72ab 100644 --- a/net/qrtr/mhi.c +++ b/net/qrtr/mhi.c @@ -79,7 +79,7 @@ static int qcom_mhi_qrtr_probe(struct mhi_device *mhi_dev, int rc; /* start channels */ - rc = mhi_prepare_for_transfer(mhi_dev); + rc = mhi_prepare_for_transfer(mhi_dev, MHI_CH_INBOUND_ALLOC_BUFS); if (rc) return rc; From patchwork Fri Jun 25 12:33:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466849 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1417348jao; Fri, 25 Jun 2021 05:34:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx3TItmKAfFyYFpStB8faFSvEfKr7miJrRotUAsXkxonyLRpo3UVu5w5Li7lbtzSPpKk9Gp X-Received: by 2002:a17:906:9e05:: with SMTP id fp5mr3306897ejc.376.1624624472160; Fri, 25 Jun 2021 05:34:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624472; cv=none; d=google.com; s=arc-20160816; b=tbLAXlhDgv0fFVpzjCLk08Gg8geyX+Xjla0gm9gLv9Bf2gJ0J3SMrbFSU3BK4E0cqA q1M3DmXmiF3F7omfGiQBzlt8qyTS2WWAA62nK54aA8tyS9PeRZGdD8/OZBUVEYd6bFMd P9q0MVy2EwDjlgmmsZNbMz8pdMaiJf4jKVFOXCI9RF3S2C/kcrc2e8LDetko4tBBQNdu xrQz5RUVVEKY7Ykqz265Pn/ZxCnToCXE2Frds70VHtJmeWpaRmP79Gcz1121x4cqGx4Y 97cLvDnKxQL1herx1XjnDEs97Vw4V3uiTPQNcb1WXnmfpXnITf+ijPKA1hdCxqG0QdEX Hlmg== ARC-Message-Signature: i=1; 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Newer devices such as SDX55 or SDX65 support inband wake method by default. Ensure the functionality is used based on this such that device wake stays held when a client driver uses mhi_device_get() API or the equivalent debugfs entry. Cc: stable@vger.kernel.org Fixes: e3e5e6508fc1 ("bus: mhi: pci_generic: No-Op for device_wake operations") Signed-off-by: Bhaumik Bhatt Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1624560809-30610-1-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index d84b74396c6a..eac4d10f99c9 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -32,6 +32,8 @@ * @edl: emergency download mode firmware path (if any) * @bar_num: PCI base address register to use for MHI MMIO register space * @dma_data_width: DMA transfer word size (32 or 64 bits) + * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead + * of inband wake support (such as sdx24) */ struct mhi_pci_dev_info { const struct mhi_controller_config *config; @@ -40,6 +42,7 @@ struct mhi_pci_dev_info { const char *edl; unsigned int bar_num; unsigned int dma_data_width; + bool sideband_wake; }; #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ @@ -242,7 +245,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { .edl = "qcom/sdx65m/edl.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false, }; static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { @@ -251,7 +255,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .edl = "qcom/sdx55m/edl.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false, }; static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { @@ -259,7 +264,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { .edl = "qcom/prog_firehose_sdx24.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = true, }; static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { @@ -301,7 +307,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { .edl = "qcom/prog_firehose_sdx24.mbn", .config = &modem_quectel_em1xx_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = true, }; static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { @@ -339,7 +346,8 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { .edl = "qcom/sdx55m/edl.mbn", .config = &modem_foxconn_sdx55_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false, }; static const struct pci_device_id mhi_pci_id_table[] = { @@ -640,9 +648,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mhi_cntrl->status_cb = mhi_pci_status_cb; mhi_cntrl->runtime_get = mhi_pci_runtime_get; mhi_cntrl->runtime_put = mhi_pci_runtime_put; - mhi_cntrl->wake_get = mhi_pci_wake_get_nop; - mhi_cntrl->wake_put = mhi_pci_wake_put_nop; - mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; + + if (info->sideband_wake) { + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; + } err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) From patchwork Fri Jun 25 12:33:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466850 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1417361jao; Fri, 25 Jun 2021 05:34:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqxWzS8KB9jb0a+0CIzmKeYW+7VnEWlIdWUAJWfS4ONMhGaiRBD50K1kyKgI4eN57Yf7Cv X-Received: by 2002:a05:6402:138c:: with SMTP id b12mr14413589edv.268.1624624473161; Fri, 25 Jun 2021 05:34:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624473; cv=none; d=google.com; s=arc-20160816; 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Cinterion MV31-W (by Thales) Additional information on such Modem Card (USB or PCIe variant) is available at: https://www.thalesgroup.com/en/markets/digital-identity-and-security/iot/iot-connectivity/products/iot-products/mv31-w-ultra-high Signed-off-by: ULRICH Thomas Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/PAZP264MB284690134DA010698E6B3BDDE60A9@PAZP264MB2846.FRAP264.PROD.OUTLOOK.COM [mani: fixed the subject, whitespace, and added sideband_wake field] Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.25.1 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index eac4d10f99c9..89f71e6db23f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -350,6 +350,40 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { .sideband_wake = false, }; +static const struct mhi_channel_config mhi_mv31_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), + /* MBIM Control Channel */ + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), + /* MBIM Data Channel */ + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), +}; + +static struct mhi_event_config mhi_mv31_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 256), + MHI_EVENT_CONFIG_DATA(1, 256), + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), +}; + +static const struct mhi_controller_config modem_mv31_config = { + .max_channels = 128, + .timeout_ms = 20000, + .num_channels = ARRAY_SIZE(mhi_mv31_channels), + .ch_cfg = mhi_mv31_channels, + .num_events = ARRAY_SIZE(mhi_mv31_events), + .event_cfg = mhi_mv31_events, +}; + +static const struct mhi_pci_dev_info mhi_mv31_info = { + .name = "cinterion-mv31", + .config = &modem_mv31_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, @@ -370,6 +404,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, + /* MV31-W (Cinterion) */ + { PCI_DEVICE(0x1269, 0x00b3), + .driver_data = (kernel_ulong_t) &mhi_mv31_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); From patchwork Fri Jun 25 12:33:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466851 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1417616jao; Fri, 25 Jun 2021 05:34:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybrX7+szNs4vwroHNisDiJiiVGs0j2RGrYE3EEUuLGHGad05CQDSx/YWbSZ7LaNe2xNgHn X-Received: by 2002:a05:6402:411:: with SMTP id q17mr14252674edv.313.1624624494033; Fri, 25 Jun 2021 05:34:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624494; cv=none; d=google.com; s=arc-20160816; b=pZtRuLSHWSRFPcGlvfTb8b1R3ghCf/1j3HsGTCzNeqH7ZWa+USSGfSA+QHyV7VJhiU PvuGJ6HobQ5r5Mblr2DV/S4L1Y4hXtuBvJZXoXftbhN6KklGo5gW/scPei7buJ6tf1YE MQN7GtsepMSFb+IyX1O2cwunoNWMjhTYa+hArc5x6Xb3eVMBmiEOrVcl/2DUhMkBojmR bdOgUPHS8jPuqT47zljJsmMl6k6zcw0d0Ub+5+EQw+zs/vfOrmG67DuDxVYd6iQ0REFJ sgp+qOXShZEul6yC52sLvbhoBxFw9ZnCWdCxCpOF3xRvdjA+S1RCjrsbQY6wGO5EBdss yCDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g+lLagFeszou/6sKi0JtQNyDv5OxzHHtHPuB74dMzb0=; b=y0z6otPUFtuNPRn4WjX83JhBfRdN/iiSAYfdPFsFzzAtku2oljiXkCq55KhYFed8j+ qNtdUroQ/P0QMCd3LGCCG5vWgQQZIVMrA1lL07cyq+VVLThx3YrPZ770QAAURECfBIq9 K2teGbGmN9n+vxiXt0LXIin/QoG6oaZc+zzdwGYQX6l1pii7F7d0OIC/htmyqCwuAGL9 EJUP8dgFNPqXdhtwJ7pf6+5bn7d2CQh1XZR2GI04JawpTyza3PSC/zl+kHCbJ9Fq5bf0 KV5UO1PDc/wfBeSQFxK564lJNsmD0PenLybaDa6FTs6JItkwrZi4pXYuLpHIZKCh0Y77 t8Dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S83L6xzt; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w9si5765682ejk.580.2021.06.25.05.34.53; Fri, 25 Jun 2021 05:34:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S83L6xzt; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231607AbhFYMhL (ORCPT + 17 others); Fri, 25 Jun 2021 08:37:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231630AbhFYMg5 (ORCPT ); Fri, 25 Jun 2021 08:36:57 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07DBAC061768 for ; Fri, 25 Jun 2021 05:34:34 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id b3so4656598plg.2 for ; Fri, 25 Jun 2021 05:34:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g+lLagFeszou/6sKi0JtQNyDv5OxzHHtHPuB74dMzb0=; b=S83L6xztJyvMDdrDFudWRKLH2YgerUT+jvHanW2eS+hr0VefoDlCCLQxtDG9RwEV9B WocxhY2bygwxU1a+h4YRatVNm8Pu+p4kQpIR8AV9HJrzPaZs+wbPsujVvyhJKbHhIvnl 3fZcwkDXnx1o4sS6fWNHoN4vjTJAgsJ2wD1ObNa1zhzvz8iFz0QlLAHr5uk/rBNJV2kR SOgH278CQrhzmGgm1dmbaVUnnZpckIYDupAzYRTE2bV7GLro+DD9xhXf66jyWaS4p8zf ezLhNM1qCEhYlr9VM+CsGs1HiVKqFI0gzDpDylrcMlWu5BXXUazz665O5/OV5520le5H +YjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g+lLagFeszou/6sKi0JtQNyDv5OxzHHtHPuB74dMzb0=; b=hUYG1f9fxsxcemu5GgIxL47djLEZm42jXdJkQ7C44oKYhEnWkhWTCDxeHFgUas0UDw MWnOwmrcAcNK2DdUjnlYjnhqsiEkDzlKGxdJ9gr5/nn3dEHfFrOeiRWtrQE7WsEetf3Q fC/oog8Jq+7CUubwzs3mxuJkJGV8yYY2jqXWEf+i7L6nawcM8k8fSbWLTa4jbRQh4ZUK xA8eEYYJL3Xq7T9xMzh6N115DzzE0ScKIVz7fIR8cUK8TcRUBszGAmkYYHLA+PltzaOk 3PkRQgCRfHLFwQ3v6fqsz9QE5cNun/AngH7jDHCfAG4rViCwjX/uizvQjjGVMmL9EoUs p8kQ== X-Gm-Message-State: AOAM5329g4hLcCc4L7UtU/ada6YXyimH95P+ONBsSlWgXEiPLchtO93+ +wfhk2f1HHIj/nRvlUho6a8V X-Received: by 2002:a17:90b:603:: with SMTP id gb3mr11364268pjb.230.1624624473578; Fri, 25 Jun 2021 05:34:33 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:600b:2a0:ed5d:53e7:c64e:1bac]) by smtp.gmail.com with ESMTPSA id y7sm6077780pfy.153.2021.06.25.05.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 05:34:32 -0700 (PDT) From: Manivannan Sadhasivam To: gregkh@linuxfoundation.org Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, loic.poulain@linaro.org, kvalo@codeaurora.org, ath11k@lists.infradead.org, stable@vger.kernel.org, Manivannan Sadhasivam , Jeffrey Hugo Subject: [PATCH 04/10] bus: mhi: core: Validate channel ID when processing command completions Date: Fri, 25 Jun 2021 18:03:49 +0530 Message-Id: <20210625123355.11578-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> References: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bhaumik Bhatt MHI reads the channel ID from the event ring element sent by the device which can be any value between 0 and 255. In order to prevent any out of bound accesses, add a check against the maximum number of channels supported by the controller and those channels not configured yet so as to skip processing of that event ring element. Cc: stable@vger.kernel.org Fixes: 1d3173a3bae7 ("bus: mhi: core: Add support for processing events from client device") Signed-off-by: Bhaumik Bhatt Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Reviewed-by: Jeffrey Hugo Link: https://lore.kernel.org/r/1624558141-11045-1-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/core/main.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index 69cd9dcde6d8..26bbc812121d 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -773,11 +773,18 @@ static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, cmd_pkt = mhi_to_virtual(mhi_ring, ptr); chan = MHI_TRE_GET_CMD_CHID(cmd_pkt); - mhi_chan = &mhi_cntrl->mhi_chan[chan]; - write_lock_bh(&mhi_chan->lock); - mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); - complete(&mhi_chan->completion); - write_unlock_bh(&mhi_chan->lock); + + if (chan < mhi_cntrl->max_chan && + mhi_cntrl->mhi_chan[chan].configured) { + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + write_lock_bh(&mhi_chan->lock); + mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); + complete(&mhi_chan->completion); + write_unlock_bh(&mhi_chan->lock); + } else { + dev_err(&mhi_cntrl->mhi_dev->dev, + "Completion packet for invalid channel ID: %d\n", chan); + } mhi_del_ring_element(mhi_cntrl, mhi_ring); } From patchwork Fri Jun 25 12:33:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466852 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1417783jao; Fri, 25 Jun 2021 05:35:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQUSqEYNprB4KP7sRPH8xWdP1roLq75Jf2aRRywYdvpdrGj5FAZ60GXIY2gKnHcMVbl1KF X-Received: by 2002:a17:906:8988:: with SMTP id gg8mr10703561ejc.104.1624624504015; Fri, 25 Jun 2021 05:35:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624504; cv=none; d=google.com; s=arc-20160816; b=l/gIHKvFqDjWb0YWeUb5Ql6lmiBcX3zFx+kSUkG/sUK/XvQ56sCr1anRcBPEWkKxt4 OGjGHVzD14v+q36IIFnK2QJwGWp89kn5PlkMPcYWzYYwl3LGCILXm8zAXnA9NuD/Gsjp 1r0ueD8cHeArO2lpNNEkV4gtx244pM6SjCVr7L2qAfrTNADSBqjAq9KDUKNnE2tPEc9o pls6DzDl2p3tyv6Q9Q/kMgz4nx76Ptn7o/dT8VjYbvPHu5WQp+QCF8FLmfBMGqRkp2WL D18rffpqCcTjWer6RFnJHucXn81g63/UyFlcuUDMnG8xedfuMz9+OQUQz1psJHdlW54c u4CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=26+KEZ0Hx72pvjQJfrOEoIc8ilnySOUXy/nlBhCQtpo=; b=xzF6aQD3zMd/qR1YI7KtD+103Ek9AuF4kmeJ2hH5b+6RkArUOEBE+c40gG2RhzV2sN +fxQ+jsO2CiaiEm7n+WBAQ/h3ZcdY1b98MmgicUyqVuYZ1SUb+BDUUAW6jkjmP87i5h1 PxIv+ja9/7JFsMNc73Zab0JZDnXvVrsw9nTs00tEHPtuzEZ+Tp9Zj99/utqP2niywI1p WqG34bPyaFEde3FXDWnuy3VvVR2GE4fRP827DEXqlwAkOlTinNhx0LGFyeS0VSXZVvgt ajxlyxu3eptcHEjKbxaL7M9gOs+7oXp0dKn56bqZFaa8hsRQ8/EO6ylPdDBgHoO3RE44 x0FQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YotlkkYF; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 28si5822157ejk.511.2021.06.25.05.35.03; Fri, 25 Jun 2021 05:35:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YotlkkYF; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231654AbhFYMhT (ORCPT + 17 others); Fri, 25 Jun 2021 08:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231526AbhFYMhK (ORCPT ); Fri, 25 Jun 2021 08:37:10 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7959C0617AF for ; Fri, 25 Jun 2021 05:34:39 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id f10so4671576plg.0 for ; Fri, 25 Jun 2021 05:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=26+KEZ0Hx72pvjQJfrOEoIc8ilnySOUXy/nlBhCQtpo=; b=YotlkkYFXipWrpHhbZnc7WPGJNhr6V4C7LtlckRCgvhIXOmkT9k9C4UEA3ym2/Ocqc ACXDQTu4TKQXGwoAJyvMkKdhbJDnmRSA6mzagez11GgFs/sBPOH/vcWB2qKcf6r2obbJ G+/QOhEkRs/cvE6z065OQYyqU1BwkFp4q/97q3Vzcov+DV2tfRRgsERYUjjX1soqi+uA s+HVgMVBKVZgVauxLGGTdhD1ltHOuoP1sIVvry3uMBA5D3Lfy2IXhjQoIQ7klGPHYwTv SQVX/fLGN4WBi/Vi1p8sviuonS5HaVCe7by3V8sqrBD5RmgOvUzJdbLJi303B66OXHmm kGBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=26+KEZ0Hx72pvjQJfrOEoIc8ilnySOUXy/nlBhCQtpo=; b=Z831REhaDIHncI/c0HcYJNcQoZcn/IkGar9uNJSGrVHPJTNl7a6OuoNWpDCDq5aGqT KsZiVh2NPz4ZnKFcMUs9fN/v0FfkZW0qEan68ArSXXDcAjJTOxK0C4KC1iSTveMIQ4JM ID1/tmYESGXuRgeAODAX2871GswA0BzeqXDTFMNZgwP+EpvLh0dJhS/wm7MIV7uSRI7x EvXDERygSDZw8v2TD74Yo8SUXGP3hnXr7RaVvd4yDN1gY+qSLy6Qab0zV5SFYsXlcCwt 0Q4a/NpUnciXhhfV1i/NfhO7laKOQFrI5tpfR/is/ySCXqn6qPLOQKo7Ar54vCVAmSox ywsQ== X-Gm-Message-State: AOAM532qwSyyUKtRi4hpDY4hracs+Yfgr9ce+IU2FZ/Tt815+W3Cqhbw 6ChPXhEEL4movqjtRGfGgRJm X-Received: by 2002:a17:90a:2e87:: with SMTP id r7mr20900741pjd.232.1624624479187; Fri, 25 Jun 2021 05:34:39 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:600b:2a0:ed5d:53e7:c64e:1bac]) by smtp.gmail.com with ESMTPSA id y7sm6077780pfy.153.2021.06.25.05.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 05:34:38 -0700 (PDT) From: Manivannan Sadhasivam To: gregkh@linuxfoundation.org Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, loic.poulain@linaro.org, kvalo@codeaurora.org, ath11k@lists.infradead.org, Jeffrey Hugo , Manivannan Sadhasivam Subject: [PATCH 05/10] bus: mhi: core: Set BHI/BHIe offsets on power up preparation Date: Fri, 25 Jun 2021 18:03:50 +0530 Message-Id: <20210625123355.11578-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> References: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bhaumik Bhatt Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(), rearrange the function, and remove the equivalent from mhi_async_power_up(). This helps consolidate multiple checks in different parts of the driver and can help MHI fail early on before power up begins if the offsets are not read correctly. Signed-off-by: Bhaumik Bhatt Reviewed-by: Jeffrey Hugo Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1620330705-40192-2-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/core/init.c | 42 ++++++++++++++++++++----------------- drivers/bus/mhi/core/pm.c | 28 ++++--------------------- 2 files changed, 27 insertions(+), 43 deletions(-) -- 2.25.1 diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index c81b377fca8f..11c7a3d3c9bf 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -1063,7 +1063,7 @@ EXPORT_SYMBOL_GPL(mhi_free_controller); int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) { struct device *dev = &mhi_cntrl->mhi_dev->dev; - u32 bhie_off; + u32 bhi_off, bhie_off; int ret; mutex_lock(&mhi_cntrl->pm_mutex); @@ -1072,29 +1072,36 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) if (ret) goto error_dev_ctxt; - /* - * Allocate RDDM table if specified, this table is for debugging purpose - */ - if (mhi_cntrl->rddm_size) { - mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, - mhi_cntrl->rddm_size); + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off); + if (ret) { + dev_err(dev, "Error getting BHI offset\n"); + goto error_reg_offset; + } + mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off; - /* - * This controller supports RDDM, so we need to manually clear - * BHIE RX registers since POR values are undefined. - */ + if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) { ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &bhie_off); if (ret) { dev_err(dev, "Error getting BHIE offset\n"); - goto bhie_error; + goto error_reg_offset; } - mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off; + } + + if (mhi_cntrl->rddm_size) { + /* + * This controller supports RDDM, so we need to manually clear + * BHIE RX registers since POR values are undefined. + */ memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS, 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS + 4); - + /* + * Allocate RDDM table for debugging purpose if specified + */ + mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, + mhi_cntrl->rddm_size); if (mhi_cntrl->rddm_image) mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image); } @@ -1103,11 +1110,8 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) return 0; -bhie_error: - if (mhi_cntrl->rddm_image) { - mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); - mhi_cntrl->rddm_image = NULL; - } +error_reg_offset: + mhi_deinit_dev_ctxt(mhi_cntrl); error_dev_ctxt: mutex_unlock(&mhi_cntrl->pm_mutex); diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c index bbf6cd04861e..ff7cdc8653ef 100644 --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c @@ -1059,28 +1059,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) if (ret) goto error_setup_irq; - /* Setup BHI offset & INTVEC */ + /* Setup BHI INTVEC */ write_lock_irq(&mhi_cntrl->pm_lock); - ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val); - if (ret) { - write_unlock_irq(&mhi_cntrl->pm_lock); - goto error_bhi_offset; - } - - mhi_cntrl->bhi = mhi_cntrl->regs + val; - - /* Setup BHIE offset */ - if (mhi_cntrl->fbc_download) { - ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val); - if (ret) { - write_unlock_irq(&mhi_cntrl->pm_lock); - dev_err(dev, "Error reading BHIE offset\n"); - goto error_bhi_offset; - } - - mhi_cntrl->bhie = mhi_cntrl->regs + val; - } - mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); mhi_cntrl->pm_state = MHI_PM_POR; mhi_cntrl->ee = MHI_EE_MAX; @@ -1091,7 +1071,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) { dev_err(dev, "Not a valid EE for power on\n"); ret = -EIO; - goto error_bhi_offset; + goto error_async_power_up; } state = mhi_get_mhi_state(mhi_cntrl); @@ -1110,7 +1090,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) if (!ret) { ret = -EIO; dev_info(dev, "Failed to reset MHI due to syserr state\n"); - goto error_bhi_offset; + goto error_async_power_up; } /* @@ -1132,7 +1112,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) return 0; -error_bhi_offset: +error_async_power_up: mhi_deinit_free_irq(mhi_cntrl); error_setup_irq: From patchwork Fri Jun 25 12:33:52 2021 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id qp24si7221044ejb.742.2021.06.25.05.35.12; Fri, 25 Jun 2021 05:35:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ktHLP1O9; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230274AbhFYMh3 (ORCPT + 17 others); Fri, 25 Jun 2021 08:37:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231666AbhFYMhO (ORCPT ); Fri, 25 Jun 2021 08:37:14 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32465C061766 for ; Fri, 25 Jun 2021 05:34:52 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id 21so7954112pfp.3 for ; Fri, 25 Jun 2021 05:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4vCP14x51ZT3xHTsGRwNOFfupBHNf+HcNjz+uJv37tc=; b=ktHLP1O9pdgttROJ/3d/zqYT2d35eagqTUHjpN0GfpcWbPh7NmalFXQtu1zu/5tXsw Xvbdhc4o67mkTGwm6o+sVB7IRHNMPMtU4HvrruA2ocB4SRyeqMtU8VsZ00zxspnkPavM Z60HD6xD5u9uBTB0ChMeaNa2cPkxVXw3wW2Ync+7cJu+5qb+VHjaPRyLjXiVgdXzKldw 1EB63Ag0x8+SRu0ahaJJnn3nBZXkzSYipqu/XKY5IrbCXV1RM/6nGJZc8otYplg1zgiI 5Uk/i8znvTY2xXXPPpmko1myRwptIkqzqj42Yr5iri2at2qR6RSBmHN5oUXnWSHaUmLZ SGjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4vCP14x51ZT3xHTsGRwNOFfupBHNf+HcNjz+uJv37tc=; b=VJSO6Hm2GRdNH+ksuf0mV99CD43L0Ls3KTF+VvmuoPgfJs5VYyDIPrx33cnyQBLN39 G3Q9/qrPjlwt84XULJete8fZDzaBWlmbyT1ueMyn2lKhV61mkajGuITy5meqdplUmN2K YpIJJFm794nPEVw6pahvEcuUQrKm2ACSTIuQ8TiKlcRJQxSfyLPoiyRUiGNrpD/ZG0QL p1cLKDHG4YoD32u9JX6GPy4R85qJ01LIBUf55UGsg1PAJr7u8JTN/9yWsVo2OPp+QAb7 P3KZx+1af22YkpWm5pBPOsXaV7RiOUamujo6Ic8MJV4iX3iQoIyeHbF3mX8Tumt0Autq aiZw== X-Gm-Message-State: AOAM530ffimnSm31aT50pl7AZYFrt6fZAfAiT4kSKe4/osJ5MA9oXtsM FolThSjDTdfSIRqtzlEOds3J X-Received: by 2002:a62:53c1:0:b029:2ef:25e8:d9e5 with SMTP id h184-20020a6253c10000b02902ef25e8d9e5mr10439876pfb.74.1624624491735; Fri, 25 Jun 2021 05:34:51 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:600b:2a0:ed5d:53e7:c64e:1bac]) by smtp.gmail.com with ESMTPSA id y7sm6077780pfy.153.2021.06.25.05.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 05:34:51 -0700 (PDT) From: Manivannan Sadhasivam To: gregkh@linuxfoundation.org Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, loic.poulain@linaro.org, kvalo@codeaurora.org, ath11k@lists.infradead.org, Jeffrey Hugo , Manivannan Sadhasivam Subject: [PATCH 07/10] bus: mhi: Add MMIO region length to controller structure Date: Fri, 25 Jun 2021 18:03:52 +0530 Message-Id: <20210625123355.11578-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> References: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bhaumik Bhatt Make controller driver specify the MMIO register region length for range checking of BHI or BHIe space. This can help validate that offsets are in acceptable memory region or not and avoid any boot-up issues due to BHI or BHIe memory accesses. Signed-off-by: Bhaumik Bhatt Reviewed-by: Jeffrey Hugo Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1620330705-40192-4-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- include/linux/mhi.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 5e08468854db..b8ca6943f0b7 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -303,6 +303,7 @@ struct mhi_controller_config { * @rddm_size: RAM dump size that host should allocate for debugging purpose * @sbl_size: SBL image size downloaded through BHIe (optional) * @seg_len: BHIe vector size (optional) + * @reg_len: Length of the MHI MMIO region (required) * @fbc_image: Points to firmware image buffer * @rddm_image: Points to RAM dump buffer * @mhi_chan: Points to the channel configuration table @@ -386,6 +387,7 @@ struct mhi_controller { size_t rddm_size; size_t sbl_size; size_t seg_len; + size_t reg_len; struct image_info *fbc_image; struct image_info *rddm_image; struct mhi_chan *mhi_chan; From patchwork Fri Jun 25 12:33:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466855 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1417972jao; Fri, 25 Jun 2021 05:35:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwdibaiZn83fRcMgaUOZ+0JQGRPt+oO+n7JS5Gp8HCpWir951m5ezlOILmeFWNADiQL5ggn X-Received: by 2002:aa7:dbc3:: with SMTP id v3mr14454710edt.63.1624624515836; Fri, 25 Jun 2021 05:35:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624515; cv=none; d=google.com; s=arc-20160816; b=OzObTNf1oDtJNTLxLNAWFeorIBkwpSNAAoLZ0QP+P/A90lV7hw3p7ZWtKdnMXJmnUX /25DEz9km9uSZ3qLZx2zb345LvALVgaBc2HFAiCJbFrQlBdy1MfSg2+LrXVhv0bF8FVL pfZFx2/areZxs5clt4pMU6EPMsA75t0FBjceur7XRRYdVRCZs2YZWAlEzQNgb1Q/fusw EYcLmG22kBTDDnsXI+0bgX3CNgrECmgvYPkvO3bjaoxIWxcSJxX1PMX+TmbJEp07Nyy6 igJ3RiPsuoWbaCM6W+56XShPvBtykdOpbkcPE/KAQA+udcA7eTwtt7LElEBQrpp0dJ0X y9Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=b0yKlt0Q933fIPy75KLLXBy+WqH1A4lfhq0nnaDRBRU=; b=Ja7sMqEnWdh7HUa2J4sDq0trtwFNyVrlB/Z27RyUfGU+c/beqbu/4eIObVuqH3R75z 3BQKr+2s/+SenQqxAkdtAe86VnvnAt6sDEn93ltq1hc2TVtrT2qMWFfojyWLSGecR+dh 8jUWwF/on3DQT/ErFi0YH99t8RpnboKo9b/2imNef137PF6Zc3C+EY5YSzbuOhv5h0At mAEFxR9WfIwoUTdxr74YioxPuL8PK0Y4enS8RFDeFy8DVufZIA3FZWw6A6sMKloPQjq2 zeMmtNJrC59arSuysjGTHXUmveXpVqJD+tpliLVRutKhkEhrZdPBm+RrKvqrRK4rZ0ix h2fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KQDZCGGr; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Set it before registering the MHI controller. Signed-off-by: Bhaumik Bhatt Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Acked-by: Kalle Valo Link: https://lore.kernel.org/r/1620330705-40192-5-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/net/wireless/ath/ath11k/mhi.c | 1 + 1 file changed, 1 insertion(+) -- 2.25.1 diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c index 27b394d115e2..e097ae52e257 100644 --- a/drivers/net/wireless/ath/ath11k/mhi.c +++ b/drivers/net/wireless/ath/ath11k/mhi.c @@ -330,6 +330,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci) mhi_ctrl->cntrl_dev = ab->dev; mhi_ctrl->fw_image = ab_pci->amss_path; mhi_ctrl->regs = ab->mem; + mhi_ctrl->reg_len = ab->mem_len; ret = ath11k_mhi_get_msi(ab_pci); if (ret) { From patchwork Fri Jun 25 12:33:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466856 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1418000jao; Fri, 25 Jun 2021 05:35:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhrOUciBOK2kVVukaC35WuKmrIJwI13qoEvqh0DKf2c77gyTULVhBWjppVpe+IPrXnuCHb X-Received: by 2002:a05:6402:35cf:: with SMTP id z15mr14484100edc.208.1624624517487; Fri, 25 Jun 2021 05:35:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624517; cv=none; d=google.com; s=arc-20160816; b=triA2Q3rQ64Wezjpyp+wb8plPKhNiTUL9+K04O5gYmLA1bfZtH2ELILo8DRyhyn84Q jZANjkIhKTYpCRODLC1cBb9PD0O/2yS02CK9p3YcXWQvO3u/gTpTKmRBDxjZCHtnco/m wnTflCehsrcu8l4nR6l/I/FBy4cMdH5MzKaK8qV5rPPhDhT9OUovVJBX4iHS0TWWH+V8 7BhKiKGvh/fCt0WBI06FRqD+C/SwD5OypjmXTMoVqmMQ+2ylqUOSs3JIuPTSg7OtE5vf 7SzYUCTiovqE+mUqlGK1GxKIxn/0EtMO5OiSB2jyfAnB2Ptpo5MnIN6UhJOfGUSAy2pw Q8jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3DgnnTTSnmT/peV2biYKlFU/kMTbnc/Zi2T2QGThm6g=; b=FDnBszICZOu/NGWuIHHhMVp25w985ybs22LFXc8ZrpmPlRNtWaFdVlk5Jemq0kKW+b 8Q1A7/TOfzgxa2FWfbXg8Rb2KTfaGp1TE/BFhvbXXIcnS99dYgKYShZpUurdd3gFHsC6 gjTqjKLDSesJXxSpBawte6+VwNAr4rmX7HC4w9pNuyPYE3cv/BbWvMxst5eNrcOJ50Jv LNk1YdmLWx1FweQy+y+YbExxcBQJqRkJrEF8FxE4I3n7MiNlEQ7r1cf5cAiEtX75pUqD IYqDZRAfmitToODTUK3OhYgKAtwlbhPylYPUHQLErlo+2dVZ5QOnRiX/nQ9K3iSFzCSJ h/lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z6mW3ccQ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q2si6532256edb.244.2021.06.25.05.35.17; Fri, 25 Jun 2021 05:35:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z6mW3ccQ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231579AbhFYMhf (ORCPT + 17 others); Fri, 25 Jun 2021 08:37:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231693AbhFYMh0 (ORCPT ); Fri, 25 Jun 2021 08:37:26 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3A33C0617AE for ; Fri, 25 Jun 2021 05:35:02 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id s137so307038pfc.4 for ; Fri, 25 Jun 2021 05:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3DgnnTTSnmT/peV2biYKlFU/kMTbnc/Zi2T2QGThm6g=; b=Z6mW3ccQN2YBGjwffpJ73Duxw2kzlNc3b4cHutlQBqVWyoJmNhswvJXGEFOk2WB5qU kkptZQqQ1o481oe2WiehWE3FNtq02Zue2ZCHyjqalzIbhNv1tv4hC6nNIgCErdBHfQ/3 kiD/2TB8H6xe2KvJFKhX72fI9SB2dWoCQvSKi6QFLbdKivWUTD4h706ganAsEcxqYaDM D0OBejyeEFuIUE1WqugERo3plTuoYotGPM3hdP3UYJT2oT7VFSriD8mTV5eXqWyo6uX7 lji/5RU/ZK/yqAuRBPWtPr3giwKCHRX57uZ8iHyG/P6X5pp0s7hjjTqXy/pSEoSTzWz2 0iVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3DgnnTTSnmT/peV2biYKlFU/kMTbnc/Zi2T2QGThm6g=; b=dALwAmv7kOl4p/Bz8n6Zk9qEor13Wvfe7EbYFR/EE8E1Iu285Adlo0v0Ia4GfBdrMF 3IkFgEtsNtEFQrbiJfsLYkirVvITCjUHEAY2HCqQBQs+NydVV9y/94WDorpRQztYRwJ1 iJAvpelPDjrZDzxGILltfwFHZRqTD2xi/rjowSsiLxlcAXvaXUgoTr0fYtkaYd2CYAKI yT1TI0UV2Ja4uC8HuQvgJTdbRU0oggKLawiz7ZQtviGVG1FpFAqrbT8Xy9NhY6RSzJS2 eete53Qzhbwk0FKNGB+yP2qx6ZYTxsS+9WQXBKCZbXmcUsCrmnJfNoRLJqWkZGqiMlwO LAPA== X-Gm-Message-State: AOAM530j6tE25J5uA38Zrp6FUOfe3IuHk8/v5NG8WKfd1dkBBxKBQP5X hS4BwjA76c1UoOf1ilic9DDS X-Received: by 2002:a05:6a00:2491:b029:308:d524:1a26 with SMTP id c17-20020a056a002491b0290308d5241a26mr5630575pfv.45.1624624502242; Fri, 25 Jun 2021 05:35:02 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:600b:2a0:ed5d:53e7:c64e:1bac]) by smtp.gmail.com with ESMTPSA id y7sm6077780pfy.153.2021.06.25.05.34.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 05:35:01 -0700 (PDT) From: Manivannan Sadhasivam To: gregkh@linuxfoundation.org Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, jhugo@codeaurora.org, linux-kernel@vger.kernel.org, loic.poulain@linaro.org, kvalo@codeaurora.org, ath11k@lists.infradead.org, Manivannan Sadhasivam Subject: [PATCH 09/10] bus: mhi: pci_generic: Set register access length for MHI driver Date: Fri, 25 Jun 2021 18:03:54 +0530 Message-Id: <20210625123355.11578-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> References: <20210625123355.11578-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bhaumik Bhatt MHI driver requires register space length to add range checks and prevent memory region accesses outside of that for MMIO space. Set it from the PCI generic controller driver before registering the MHI controller. Signed-off-by: Bhaumik Bhatt Reviewed-by: Hemant Kumar Reviewed-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1620330705-40192-6-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 1 + 1 file changed, 1 insertion(+) -- 2.25.1 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 89f71e6db23f..8bc6149249e3 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -508,6 +508,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, return err; } mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num]; + mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); err = pci_set_dma_mask(pdev, dma_mask); if (err) { From patchwork Fri Jun 25 12:33:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 466857 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1418075jao; Fri, 25 Jun 2021 05:35:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOldH+xpV4fDVwIvfg+ouFxWsyRW7OA4kmdewy7ybY/dERUSAoufM7LsY5ZlpTO5TBKEC9 X-Received: by 2002:a17:906:6817:: with SMTP id k23mr10792023ejr.300.1624624522900; Fri, 25 Jun 2021 05:35:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624624522; cv=none; d=google.com; s=arc-20160816; b=gdF8usC8D7UvhvygAxL4+wdVgAN3SsoC0jM7BUc2e9+sWcnAyOXP0yIkNWjbhu/0GS 96HZjRWTJm86Taiq8oUY7IsKiaNrJ7mrb2ctnESQeMOPFHUNou5iMJYsKvubw8CMg2H9 149Ct+kMRV9JgzuV11NwERnA/RttEp8km/3tARsmHrS2wMNIENxCVgT4MIdmRN3JGUm1 1iZ1UUTzV+oKmmN7GcgASzAprIbeT+GZBYwDsBIM2t+CzO+nhBv9n93GkhnFcs8zYA+r UaoHj9xRSDktme11Lz4TS4K7WEaKHxS0+7XUfGMBYaYc91uLRdaetlnaNpteFY5kKYrw jAog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ONtT1ELTSrw1mSRZB+8b9XFyoudbRa+VTUtUIpf2uNg=; b=Ew2w23l8KKxEJ1G366br47wrroYvNH5Gmj6CYdWCQHFu3W+5SSwkiQnJVtqsEhpYrA 5GOuJBaSDU4ybFs1GNiD4L6VowpQUKD/Nc7nCsBx7gjwU0BwuR9UUVakqNVcOBZyMUMx gVoJOXXnpYIUJxTXLpq831soBxbtyCH+cFdUnMx8ssRVZ4qFQw/IucUqYCqq1IRrulbA 8ubYt9nJ9mfcC03m4fOqPh+dWUsof/jNxmBQHV3s15w2OYzIX3m35ru3Eb/pTATjZhGO hj3TCgzx3mg+Iq15CwSYWMtoI+ocjInkKHBqRvhxr0Q/+wd2uZqZf+1/PFJouojkHSU4 8Wcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hy65QO2G; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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These can help controller drivers avoid accessing any address outside of the MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI registration as it is a required field and range checks will fail without it. Signed-off-by: Bhaumik Bhatt Reviewed-by: Jeffrey Hugo Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1620330705-40192-7-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/core/init.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 1cc2f225d3d1..aeb1e3c2cdc4 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs || !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put || !mhi_cntrl->status_cb || !mhi_cntrl->read_reg || - !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq) + !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || + !mhi_cntrl->irq || !mhi_cntrl->reg_len) return -EINVAL; ret = parse_config(mhi_cntrl, config); @@ -1077,6 +1078,13 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) dev_err(dev, "Error getting BHI offset\n"); goto error_reg_offset; } + + if (bhi_off >= mhi_cntrl->reg_len) { + dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n", + bhi_off, mhi_cntrl->reg_len); + ret = -EINVAL; + goto error_reg_offset; + } mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off; if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) { @@ -1086,6 +1094,14 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) dev_err(dev, "Error getting BHIE offset\n"); goto error_reg_offset; } + + if (bhie_off >= mhi_cntrl->reg_len) { + dev_err(dev, + "BHIe offset: 0x%x is out of range: 0x%zx\n", + bhie_off, mhi_cntrl->reg_len); + ret = -EINVAL; + goto error_reg_offset; + } mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off; }