From patchwork Thu Jun 24 18:26:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 466560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4F06C49EA5 for ; Thu, 24 Jun 2021 18:26:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B63726135C for ; Thu, 24 Jun 2021 18:26:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232533AbhFXS2x (ORCPT ); Thu, 24 Jun 2021 14:28:53 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43740 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbhFXS2x (ORCPT ); Thu, 24 Jun 2021 14:28:53 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id 69B1C1F4420C From: Ezequiel Garcia To: linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Hans Verkuil , Philipp Zabel , Heiko Stuebner , Alex Bee , maccraft123mc@gmail.com, Chris Healy , Paul Kocialkowski , Jernej Skrabec , Jonas Karlman , Thierry Reding , Sam Ravnborg , David Airlie , Ezequiel Garcia , kernel@collabora.com Subject: [PATCH 01/12] drm/panel: kd35t133: Add panel orientation support Date: Thu, 24 Jun 2021 15:26:01 -0300 Message-Id: <20210624182612.177969-2-ezequiel@collabora.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624182612.177969-1-ezequiel@collabora.com> References: <20210624182612.177969-1-ezequiel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Parse the device tree rotation specifier, and set a DRM connector orientation property. The property can then be read by compositors to apply hardware plane rotation or a GPU transform. Signed-off-by: Ezequiel Garcia --- drivers/gpu/drm/panel/panel-elida-kd35t133.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c b/drivers/gpu/drm/panel/panel-elida-kd35t133.c index fe5ac3ef9018..5987d28c874c 100644 --- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c +++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c @@ -39,6 +39,7 @@ struct kd35t133 { struct device *dev; struct drm_panel panel; + enum drm_panel_orientation orientation; struct gpio_desc *reset_gpio; struct regulator *vdd; struct regulator *iovcc; @@ -216,6 +217,7 @@ static int kd35t133_get_modes(struct drm_panel *panel, connector->display_info.width_mm = mode->width_mm; connector->display_info.height_mm = mode->height_mm; drm_mode_probed_add(connector, mode); + drm_connector_set_panel_orientation(connector, ctx->orientation); return 1; } @@ -258,6 +260,12 @@ static int kd35t133_probe(struct mipi_dsi_device *dsi) return ret; } + ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation); + if (ret) { + dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret); + return ret; + } + mipi_dsi_set_drvdata(dsi, ctx); ctx->dev = dev; From patchwork Thu Jun 24 18:26:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 466559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEB37C49EA6 for ; Thu, 24 Jun 2021 18:26:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C40216128A for ; Thu, 24 Jun 2021 18:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232599AbhFXS3E (ORCPT ); Thu, 24 Jun 2021 14:29:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbhFXS3D (ORCPT ); Thu, 24 Jun 2021 14:29:03 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03B78C061574 for ; Thu, 24 Jun 2021 11:26:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id 4D9CF1F44210 From: Ezequiel Garcia To: linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Hans Verkuil , Philipp Zabel , Heiko Stuebner , Alex Bee , maccraft123mc@gmail.com, Chris Healy , Paul Kocialkowski , Jernej Skrabec , Jonas Karlman , Thierry Reding , Sam Ravnborg , David Airlie , Ezequiel Garcia , kernel@collabora.com, Nicolas Dufresne Subject: [PATCH 03/12] hantro: vp8: Move noisy WARN_ON to vpu_debug Date: Thu, 24 Jun 2021 15:26:03 -0300 Message-Id: <20210624182612.177969-4-ezequiel@collabora.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624182612.177969-1-ezequiel@collabora.com> References: <20210624182612.177969-1-ezequiel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org When the VP8 decoders can't find a reference frame, the driver falls back to the current output frame. This will probably produce some undesirable results, leading to frame corruption, but shouldn't cause noisy warnings. Signed-off-by: Ezequiel Garcia Acked-by: Nicolas Dufresne --- drivers/staging/media/hantro/hantro_g1_vp8_dec.c | 13 ++++++++++--- .../staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c | 13 ++++++++++--- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c index 96622a7f8279..2afd5996d75f 100644 --- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c @@ -376,12 +376,17 @@ static void cfg_ref(struct hantro_ctx *ctx, vb2_dst = hantro_get_dst_buf(ctx); ref = hantro_get_ref(ctx, hdr->last_frame_ts); - if (!ref) + if (!ref) { + vpu_debug(0, "failed to find last frame ts=%llu\n", + hdr->last_frame_ts); ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + } vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0)); ref = hantro_get_ref(ctx, hdr->golden_frame_ts); - WARN_ON(!ref && hdr->golden_frame_ts); + if (!ref && hdr->golden_frame_ts) + vpu_debug(0, "failed to find golden frame ts=%llu\n", + hdr->golden_frame_ts); if (!ref) ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) @@ -389,7 +394,9 @@ static void cfg_ref(struct hantro_ctx *ctx, vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4)); ref = hantro_get_ref(ctx, hdr->alt_frame_ts); - WARN_ON(!ref && hdr->alt_frame_ts); + if (!ref && hdr->alt_frame_ts) + vpu_debug(0, "failed to find alt frame ts=%llu\n", + hdr->alt_frame_ts); if (!ref) ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c index 951b55f58a61..704607511b57 100644 --- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c @@ -453,12 +453,17 @@ static void cfg_ref(struct hantro_ctx *ctx, vb2_dst = hantro_get_dst_buf(ctx); ref = hantro_get_ref(ctx, hdr->last_frame_ts); - if (!ref) + if (!ref) { + vpu_debug(0, "failed to find last frame ts=%llu\n", + hdr->last_frame_ts); ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + } vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF0); ref = hantro_get_ref(ctx, hdr->golden_frame_ts); - WARN_ON(!ref && hdr->golden_frame_ts); + if (!ref && hdr->golden_frame_ts) + vpu_debug(0, "failed to find golden frame ts=%llu\n", + hdr->golden_frame_ts); if (!ref) ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) @@ -466,7 +471,9 @@ static void cfg_ref(struct hantro_ctx *ctx, vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2)); ref = hantro_get_ref(ctx, hdr->alt_frame_ts); - WARN_ON(!ref && hdr->alt_frame_ts); + if (!ref && hdr->alt_frame_ts) + vpu_debug(0, "failed to find alt frame ts=%llu\n", + hdr->alt_frame_ts); if (!ref) ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) From patchwork Thu Jun 24 18:26:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 466558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78B75C49EA6 for ; Thu, 24 Jun 2021 18:26:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F583613B1 for ; Thu, 24 Jun 2021 18:26:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232573AbhFXS3O (ORCPT ); Thu, 24 Jun 2021 14:29:14 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43826 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbhFXS3N (ORCPT ); Thu, 24 Jun 2021 14:29:13 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id 5B97D1F44214 From: Ezequiel Garcia To: linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Hans Verkuil , Philipp Zabel , Heiko Stuebner , Alex Bee , maccraft123mc@gmail.com, Chris Healy , Paul Kocialkowski , Jernej Skrabec , Jonas Karlman , Thierry Reding , Sam Ravnborg , David Airlie , Ezequiel Garcia , kernel@collabora.com Subject: [PATCH 05/12] media: hantro: Avoid redundant hantro_get_{dst, src}_buf() calls Date: Thu, 24 Jun 2021 15:26:05 -0300 Message-Id: <20210624182612.177969-6-ezequiel@collabora.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624182612.177969-1-ezequiel@collabora.com> References: <20210624182612.177969-1-ezequiel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Getting the next src/dst buffer is relatively expensive so avoid doing it multiple times. Signed-off-by: Ezequiel Garcia --- .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++++++++--------- .../staging/media/hantro/hantro_g1_vp8_dec.c | 18 +++++++++--------- .../media/hantro/rockchip_vpu2_hw_vp8_dec.c | 19 +++++++++---------- 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index 5c792b7bcb79..2aa37baad0c3 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -19,13 +19,12 @@ #include "hantro_hw.h" #include "hantro_v4l2.h" -static void set_params(struct hantro_ctx *ctx) +static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; - struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx); struct hantro_dev *vpu = ctx->dev; u32 reg; @@ -226,22 +225,20 @@ static void set_ref(struct hantro_ctx *ctx) } } -static void set_buffers(struct hantro_ctx *ctx) +static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; - struct vb2_v4l2_buffer *src_buf, *dst_buf; + struct vb2_v4l2_buffer *dst_buf; struct hantro_dev *vpu = ctx->dev; dma_addr_t src_dma, dst_dma; size_t offset = 0; - src_buf = hantro_get_src_buf(ctx); - dst_buf = hantro_get_dst_buf(ctx); - /* Source (stream) buffer. */ src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR); /* Destination (decoded frame) buffer. */ + dst_buf = hantro_get_dst_buf(ctx); dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); /* Adjust dma addr to start at second line for bottom field */ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) @@ -276,6 +273,7 @@ static void set_buffers(struct hantro_ctx *ctx) int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *src_buf; int ret; /* Prepare the H264 decoder context. */ @@ -284,9 +282,10 @@ int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) return ret; /* Configure hardware registers. */ - set_params(ctx); + src_buf = hantro_get_src_buf(ctx); + set_params(ctx, src_buf); set_ref(ctx); - set_buffers(ctx); + set_buffers(ctx, src_buf); hantro_end_prepare_run(ctx); diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c index 2afd5996d75f..6180b23e7d94 100644 --- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c @@ -367,13 +367,12 @@ static void cfg_tap(struct hantro_ctx *ctx, } static void cfg_ref(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr) + const struct v4l2_ctrl_vp8_frame *hdr, + struct vb2_v4l2_buffer *vb2_dst) { struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *vb2_dst; dma_addr_t ref; - vb2_dst = hantro_get_dst_buf(ctx); ref = hantro_get_ref(ctx, hdr->last_frame_ts); if (!ref) { @@ -405,16 +404,14 @@ static void cfg_ref(struct hantro_ctx *ctx, } static void cfg_buffers(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr) + const struct v4l2_ctrl_vp8_frame *hdr, + struct vb2_v4l2_buffer *vb2_dst) { const struct v4l2_vp8_segment *seg = &hdr->segment; struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *vb2_dst; dma_addr_t dst_dma; u32 reg; - vb2_dst = hantro_get_dst_buf(ctx); - /* Set probability table buffer address */ vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, G1_REG_ADDR_QTABLE); @@ -436,6 +433,7 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) { const struct v4l2_ctrl_vp8_frame *hdr; struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *vb2_dst; size_t height = ctx->dst_fmt.height; size_t width = ctx->dst_fmt.width; u32 mb_width, mb_height; @@ -499,8 +497,10 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) cfg_qp(ctx, hdr); cfg_parts(ctx, hdr); cfg_tap(ctx, hdr); - cfg_ref(ctx, hdr); - cfg_buffers(ctx, hdr); + + vb2_dst = hantro_get_dst_buf(ctx); + cfg_ref(ctx, hdr, vb2_dst); + cfg_buffers(ctx, hdr, vb2_dst); hantro_end_prepare_run(ctx); diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c index 704607511b57..d079075448c9 100644 --- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c @@ -444,14 +444,12 @@ static void cfg_tap(struct hantro_ctx *ctx, } static void cfg_ref(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr) + const struct v4l2_ctrl_vp8_frame *hdr, + struct vb2_v4l2_buffer *vb2_dst) { struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *vb2_dst; dma_addr_t ref; - vb2_dst = hantro_get_dst_buf(ctx); - ref = hantro_get_ref(ctx, hdr->last_frame_ts); if (!ref) { vpu_debug(0, "failed to find last frame ts=%llu\n", @@ -482,16 +480,14 @@ static void cfg_ref(struct hantro_ctx *ctx, } static void cfg_buffers(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr) + const struct v4l2_ctrl_vp8_frame *hdr, + struct vb2_v4l2_buffer *vb2_dst) { const struct v4l2_vp8_segment *seg = &hdr->segment; struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *vb2_dst; dma_addr_t dst_dma; u32 reg; - vb2_dst = hantro_get_dst_buf(ctx); - /* Set probability table buffer address */ vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, VDPU_REG_ADDR_QTABLE); @@ -514,6 +510,7 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) { const struct v4l2_ctrl_vp8_frame *hdr; struct hantro_dev *vpu = ctx->dev; + struct vb2_v4l2_buffer *vb2_dst; size_t height = ctx->dst_fmt.height; size_t width = ctx->dst_fmt.width; u32 mb_width, mb_height; @@ -590,8 +587,10 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) cfg_qp(ctx, hdr); cfg_parts(ctx, hdr); cfg_tap(ctx, hdr); - cfg_ref(ctx, hdr); - cfg_buffers(ctx, hdr); + + vb2_dst = hantro_get_dst_buf(ctx); + cfg_ref(ctx, hdr, vb2_dst); + cfg_buffers(ctx, hdr, vb2_dst); hantro_end_prepare_run(ctx); From patchwork Thu Jun 24 18:26:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 466557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B521C49EA6 for ; Thu, 24 Jun 2021 18:27:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23E276128A for ; Thu, 24 Jun 2021 18:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232583AbhFXS31 (ORCPT ); Thu, 24 Jun 2021 14:29:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbhFXS31 (ORCPT ); Thu, 24 Jun 2021 14:29:27 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5950DC061574 for ; Thu, 24 Jun 2021 11:27:08 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id DF5CF1F44212 From: Ezequiel Garcia To: linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Hans Verkuil , Philipp Zabel , Heiko Stuebner , Alex Bee , maccraft123mc@gmail.com, Chris Healy , Paul Kocialkowski , Jernej Skrabec , Jonas Karlman , Thierry Reding , Sam Ravnborg , David Airlie , Ezequiel Garcia , kernel@collabora.com Subject: [PATCH 07/12] media: hantro: h264: Move reference picture number to a helper Date: Thu, 24 Jun 2021 15:26:07 -0300 Message-Id: <20210624182612.177969-8-ezequiel@collabora.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624182612.177969-1-ezequiel@collabora.com> References: <20210624182612.177969-1-ezequiel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a hantro_h264_get_ref_nbr() helper function to get the reference picture numbers. This will be used by the Rockchip VDPU2 H.264 driver. Signed-off-by: Ezequiel Garcia --- drivers/staging/media/hantro/hantro_g1_h264_dec.c | 14 ++------------ drivers/staging/media/hantro/hantro_h264.c | 11 +++++++++++ drivers/staging/media/hantro/hantro_hw.h | 2 ++ 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index 6faacfc44c7c..236ce24ca00c 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -126,7 +126,6 @@ static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) static void set_ref(struct hantro_ctx *ctx) { - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; const u8 *b0_reflist, *b1_reflist, *p_reflist; struct hantro_dev *vpu = ctx->dev; int reg_num; @@ -143,17 +142,8 @@ static void set_ref(struct hantro_ctx *ctx) * subsequential reference pictures. */ for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) { - reg = 0; - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) - reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num); - else - reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num); - - if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) - reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num); - else - reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num); - + reg = G1_REG_REF_PIC_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, i)) | + G1_REG_REF_PIC_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, i + 1)); vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2)); } diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c index 6d72136760e7..0b4d2491be3b 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -348,6 +348,17 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, return dma_addr; } +u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) +{ + const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx]; + + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + return 0; + if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + return dpb->pic_num; + return dpb->frame_num; +} + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) { struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index ce678fedaad6..7a8048afe357 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -238,6 +238,8 @@ void hantro_jpeg_enc_done(struct hantro_ctx *ctx); dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, unsigned int dpb_idx); +u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, + unsigned int dpb_idx); int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); int hantro_h264_dec_init(struct hantro_ctx *ctx); From patchwork Thu Jun 24 18:26:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 466556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EA90C49EA5 for ; Thu, 24 Jun 2021 18:27:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53A49613B1 for ; Thu, 24 Jun 2021 18:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232591AbhFXS3j (ORCPT ); Thu, 24 Jun 2021 14:29:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbhFXS3i (ORCPT ); Thu, 24 Jun 2021 14:29:38 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53085C061574 for ; Thu, 24 Jun 2021 11:27:18 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id D1F1F1F44217 From: Ezequiel Garcia To: linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Hans Verkuil , Philipp Zabel , Heiko Stuebner , Alex Bee , maccraft123mc@gmail.com, Chris Healy , Paul Kocialkowski , Jernej Skrabec , Jonas Karlman , Thierry Reding , Sam Ravnborg , David Airlie , Ezequiel Garcia , kernel@collabora.com Subject: [PATCH 09/12] media: hantro: Enable H.264 on Rockchip VDPU2 Date: Thu, 24 Jun 2021 15:26:09 -0300 Message-Id: <20210624182612.177969-10-ezequiel@collabora.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624182612.177969-1-ezequiel@collabora.com> References: <20210624182612.177969-1-ezequiel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Given H.264 support for VDPU2 was just added, let's enable it. For now, this is only enabled on platform that don't have an RKVDEC core, such as RK3328. Signed-off-by: Ezequiel Garcia --- .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c index 3ccc16413f42..e4e3b5e7689b 100644 --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c @@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1920, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 1088, + .step_height = MB_DIM, + }, + }, { .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, .codec_mode = HANTRO_MODE_MPEG2_DEC, @@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { .init = hantro_jpeg_enc_init, .exit = hantro_jpeg_enc_exit, }, + [HANTRO_MODE_H264_DEC] = { + .run = rockchip_vpu2_h264_dec_run, + .reset = rockchip_vpu2_dec_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, [HANTRO_MODE_MPEG2_DEC] = { .run = rockchip_vpu2_mpeg2_dec_run, .reset = rockchip_vpu2_dec_reset, @@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = { "aclk", "hclk" }; +/* VDPU1/VEPU1 */ + const struct hantro_variant rk3036_vpu_variant = { .dec_offset = 0x400, .dec_fmts = rk3066_vpu_dec_fmts, @@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; +/* VDPU2/VEPU2 */ + const struct hantro_variant rk3328_vpu_variant = { .dec_offset = 0x400, .dec_fmts = rk3399_vpu_dec_fmts, .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, .codec_ops = rk3399_vpu_codec_ops, .irqs = rockchip_vdpu2_irqs, .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), From patchwork Thu Jun 24 18:26:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 466555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2912FC49EA5 for ; Thu, 24 Jun 2021 18:27:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10D786135C for ; Thu, 24 Jun 2021 18:27:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232602AbhFXS3r (ORCPT ); Thu, 24 Jun 2021 14:29:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbhFXS3r (ORCPT ); Thu, 24 Jun 2021 14:29:47 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C2CBC061574 for ; Thu, 24 Jun 2021 11:27:28 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: ezequiel) with ESMTPSA id AF4051F4421A From: Ezequiel Garcia To: linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: Hans Verkuil , Philipp Zabel , Heiko Stuebner , Alex Bee , maccraft123mc@gmail.com, Chris Healy , Paul Kocialkowski , Jernej Skrabec , Jonas Karlman , Thierry Reding , Sam Ravnborg , David Airlie , kernel@collabora.com, Ezequiel Garcia Subject: [PATCH 11/12] arm64: dts: rockchip: Add VPU support for the PX30 Date: Thu, 24 Jun 2021 15:26:11 -0300 Message-Id: <20210624182612.177969-12-ezequiel@collabora.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624182612.177969-1-ezequiel@collabora.com> References: <20210624182612.177969-1-ezequiel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Paul Kocialkowski The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. Describe these two entities in device-tree. Signed-off-by: Paul Kocialkowski Signed-off-by: Ezequiel Garcia --- arch/arm64/boot/dts/rockchip/px30.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 09baa8a167ce..892eb074775b 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1016,6 +1016,29 @@ gpu: gpu@ff400000 { status = "disabled"; }; + vpu: video-codec@ff442000 { + compatible = "rockchip,px30-vpu", "rockchip,rk3399-vpu"; + reg = <0x0 0xff442000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power PX30_PD_VPU>; + }; + + vpu_mmu: iommu@ff442800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff442800 0x0 0x100>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power PX30_PD_VPU>; + }; + dsi: dsi@ff450000 { compatible = "rockchip,px30-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>;