From patchwork Thu Jun 24 15:00:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 466465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABE3EC49EA6 for ; Thu, 24 Jun 2021 15:01:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 94B41613C1 for ; Thu, 24 Jun 2021 15:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232323AbhFXPDU (ORCPT ); Thu, 24 Jun 2021 11:03:20 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:45849 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232316AbhFXPDS (ORCPT ); Thu, 24 Jun 2021 11:03:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1624546859; x=1656082859; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=SqNyNIfuwHW0yJuBwaT05X9QMLsai7UvDsw9rjA5dnQ=; b=zh1hjtUYoGk3tkUzVOrea8lmfVd+Ibc1Pnd2L4zy8L28b6rqCOmwfON8 1VXy1H/79vOPujbOHwtffYE4efPfOx1+qKeJWvonNHAiNb8u47aYe8Zt1 icOvwE8OSzDlVJfRbD1/DUJYViHAWlYDvO+FdmWts/LEhv+YhWT641niu s7TFHHgr+MrIrhH+zU297MC4gEESfciLJ46yygFEWlB4K7FlKcfPEQaMx MeU7a8SfqvV92VuxiIbAoW47tZeDKTYLxRbo5VC/osjYk+imepKHYJSqC M2MKcxW5nimwDDusfg+OQnFIShPtWlAEqXEGT95Frd1Fe9M8SLRHcVN61 g==; IronPort-SDR: ZN3jZTgMfMO50Eieqwy25SOWv37fS0ZdgVXPKEJgSvMSCVDvQG2l8dQMRr/vzqCCIoHPFazE88 M/DbBIv2p9VKaJXUr73Yus74owbcQf74r9KGP7AMTh/xd55JLgUA054MLZkqH6e2Wuxl1NArX+ zRtW12FOsSPrl7vH9t7xZdGf2ONpfAHeqPilVTV0CMtBReIiC/IwOeI4d8V9MiyZCmT+y4+0XZ 7li8yhxtXU8fQK26D5JErQYXqwXX/5liHrPOaWCK8RXYhWO0tTG6syzT4QbMMIHWGR0LXPnTJc p+w= X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="133328697" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Jun 2021 08:00:58 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 24 Jun 2021 08:00:52 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 08:00:49 -0700 From: To: , , , , , , , , , CC: , , , , , , Conor Dooley , Rob Herring Subject: [PATCH v9 1/5] dt-bindings: add bindings for polarfire soc mailbox Date: Thu, 24 Jun 2021 16:00:48 +0100 Message-ID: <20210624150048.11222-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the MSS system controller mailbox on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../microchip,polarfire-soc-mailbox.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml new file mode 100644 index 000000000000..bbb173ea483c --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-mailbox + + reg: + items: + - description: mailbox data registers + - description: mailbox interrupt registers + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + mbox: mailbox@37020000 { + compatible = "microchip,polarfire-soc-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; + interrupt-parent = <&L1>; + interrupts = <96>; + #mbox-cells = <1>; + }; + }; From patchwork Thu Jun 24 15:00:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 466464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4702EC49EA6 for ; Thu, 24 Jun 2021 15:01:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2C7CE613C0 for ; Thu, 24 Jun 2021 15:01:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230377AbhFXPEC (ORCPT ); Thu, 24 Jun 2021 11:04:02 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:26551 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230267AbhFXPEC (ORCPT ); Thu, 24 Jun 2021 11:04:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1624546902; x=1656082902; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ABlHuMU7/47NEwUn6U98jVGKhvjZVuWiEHuyHuNbCIs=; b=W3aAfO5YUL09Yssdj7DrHBxHnpPREAQMWA1R5/ULSpRHjZetc53MsabT X549wcYKUhnL3I8TbW54egkB51I7AnjSrtS2UY0bh9jUmFEoA3JuLYbyC FZdO50buIxvraSk25XiCYu7pjNMpkLLJ09NQ/zIDCNxzfLc05z2+qCkyb iuzIRl5pGIwFi8nc2NreUMDOJGIQVbxF/s6/9mQDDqG2dClZtMXPL/oYK /KPHBBP0O0s/AVjy65PCgbo+ANdhqPtCGZMuS3lJSyd6LwVf6dUFwy467 eMJ/XsVfPS2zb5kRpLPf0PQi8QPgeq4n993ii2Q7Urx4DYmO6xdyD1RrZ w==; IronPort-SDR: RPlQgSRknKq0oNe+bqEeG5mTZdXXi7aXGT776pTPWOUAer1kElnoIlzTQKplpi1s8viN+wViUY 5sjgPj9KjFn5iJRnKyfsp5x2X68OfJDtWwHdWzgOxIGZio9gxH1zQlokohZw/JnqeZMMt4Zhxm IJpysJ2OeNoGBg8fHevxW92AkNFrZed86/1G8KZ6Xn6aScxZ4pX5d7XusXOgbXKIUPvpOCL8yv DNr5cxXkAdR4vWoFR9qlpwzB2mrXwOenxq6MLtt3/8PXyDv1DQdh8EkHpX+BXKDQ2zZjPOWjzR 6gM= X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="119885687" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Jun 2021 08:01:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 24 Jun 2021 08:00:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 08:00:56 -0700 From: To: , , , , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH v9 2/5] mbox: add polarfire soc system controller mailbox Date: Thu, 24 Jun 2021 16:00:55 +0100 Message-ID: <20210624150055.11298-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox-mpfs.c | 251 +++++++++++++++++++++++++++++++++ include/soc/microchip/mpfs.h | 43 ++++++ 4 files changed, 308 insertions(+) create mode 100644 drivers/mailbox/mailbox-mpfs.c create mode 100644 include/soc/microchip/mpfs.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 68de2c6af727..b4b780ea2ac8 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -160,6 +160,18 @@ config MAILBOX_TEST Test client to help with testing new Controller driver implementations. +config POLARFIRE_SOC_MAILBOX + tristate "PolarFire SoC (MPFS) Mailbox" + depends on HAS_IOMEM + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST + help + This driver adds support for the PolarFire SoC (MPFS) mailbox controller. + + To compile this driver as a module, choose M here. the + module will be called mailbox-mpfs. + + If unsure, say N. + config QCOM_APCS_IPC tristate "Qualcomm APCS IPC driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 7194fa92c787..c2089f04887e 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -41,6 +41,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o +obj-$(CONFIG_POLARFIRE_SOC_MAILBOX) += mailbox-mpfs.o + obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c new file mode 100644 index 000000000000..0d6e2231a2c7 --- /dev/null +++ b/drivers/mailbox/mailbox-mpfs.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERVICES_CR_OFFSET 0x50u +#define SERVICES_SR_OFFSET 0x54u +#define MAILBOX_REG_OFFSET 0x800u +#define MSS_SYS_MAILBOX_DATA_OFFSET 0u +#define SCB_MASK_WIDTH 16u + +/* SCBCTRL service control register */ + +#define SCB_CTRL_REQ (0) +#define SCB_CTRL_REQ_MASK BIT(SCB_CTRL_REQ) + +#define SCB_CTRL_BUSY (1) +#define SCB_CTRL_BUSY_MASK BIT(SCB_CTRL_BUSY) + +#define SCB_CTRL_ABORT (2) +#define SCB_CTRL_ABORT_MASK BIT(SCB_CTRL_ABORT) + +#define SCB_CTRL_NOTIFY (3) +#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY) + +#define SCB_CTRL_POS (16) +#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS) + +/* SCBCTRL service status register */ + +#define SCB_STATUS_REQ (0) +#define SCB_STATUS_REQ_MASK BIT(SCB_STATUS_REQ) + +#define SCB_STATUS_BUSY (1) +#define SCB_STATUS_BUSY_MASK BIT(SCB_STATUS_BUSY) + +#define SCB_STATUS_ABORT (2) +#define SCB_STATUS_ABORT_MASK BIT(SCB_STATUS_ABORT) + +#define SCB_STATUS_NOTIFY (3) +#define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY) + +#define SCB_STATUS_POS (16) +#define SCB_STATUS_MASK GENMASK_ULL(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS) + +struct mpfs_mbox { + struct mbox_controller controller; + struct device *dev; + int irq; + void __iomem *mbox_base; + void __iomem *int_reg; + struct mbox_chan chans[1]; + struct mpfs_mss_response *response; + u16 resp_offset; +}; + +static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) +{ + u32 status; + + status = readl_relaxed(mbox->mbox_base + SERVICES_SR_OFFSET); + + return status & SCB_STATUS_BUSY_MASK; +} + +static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + struct mpfs_mss_msg *msg = data; + u32 tx_trigger; + u16 opt_sel; + u32 val = 0u; + + mbox->response = msg->response; + mbox->resp_offset = msg->resp_offset; + + if (mpfs_mbox_busy(mbox)) + return -EBUSY; + + if (msg->cmd_data_size) { + u32 index; + u8 extra_bits = msg->cmd_data_size & 3; + u32 *word_buf = (u32 *)msg->cmd_data; + + for (index = 0; index < (msg->cmd_data_size / 4); index++) + writel_relaxed(word_buf[index], + mbox->mbox_base + MAILBOX_REG_OFFSET + index * 0x4); + if (extra_bits) { + u8 i; + u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4); + u8 *byte_buf = msg->cmd_data + byte_off; + + val = readl_relaxed(mbox->mbox_base + + MAILBOX_REG_OFFSET + index * 0x4); + + for (i = 0u; i < extra_bits; i++) { + val &= ~(0xffu << (i * 8u)); + val |= (byte_buf[i] << (i * 8u)); + } + + writel_relaxed(val, + mbox->mbox_base + MAILBOX_REG_OFFSET + index * 0x4); + } + } + + opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu)); + tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK; + tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK; + writel_relaxed(tx_trigger, mbox->mbox_base + SERVICES_CR_OFFSET); + + return 0; +} + +static void mpfs_mbox_rx_data(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + struct mpfs_mss_response *response = mbox->response; + u16 num_words = ALIGN((response->resp_size), (4)) / 4U; + u32 i; + + if (!response->resp_msg) { + dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM); + return; + } + + if (!mpfs_mbox_busy(mbox)) { + for (i = 0; i < num_words; i++) { + response->resp_msg[i] = + readl_relaxed(mbox->mbox_base + MAILBOX_REG_OFFSET + + mbox->resp_offset + i * 0x4); + } + } + + mbox_chan_received_data(chan, response); +} + +static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data) +{ + struct mbox_chan *chan = data; + struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + + writel_relaxed(0, mbox->int_reg); + + mpfs_mbox_rx_data(chan); + + mbox_chan_txdone(chan, 0); + return IRQ_HANDLED; +} + +static int mpfs_mbox_startup(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + int ret = 0; + + if (!mbox) + return -EINVAL; + + ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, "mpfs-mailbox", chan); + if (ret) + dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", ret); + + return ret; +} + +static void mpfs_mbox_shutdown(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + + devm_free_irq(mbox->dev, mbox->irq, chan); +} + +static const struct mbox_chan_ops mpfs_mbox_ops = { + .send_data = mpfs_mbox_send_data, + .startup = mpfs_mbox_startup, + .shutdown = mpfs_mbox_shutdown, +}; + +static int mpfs_mbox_probe(struct platform_device *pdev) +{ + struct mpfs_mbox *mbox; + struct resource *regs; + int ret; + + mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); + if (IS_ERR(mbox->mbox_base)) + return PTR_ERR(mbox->mbox_base); + + mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s); + if (IS_ERR(mbox->int_reg)) + return PTR_ERR(mbox->int_reg); + + mbox->irq = platform_get_irq(pdev, 0); + if (mbox->irq < 0) + return mbox->irq; + + mbox->dev = &pdev->dev; + + mbox->chans[0].con_priv = mbox; + mbox->controller.dev = mbox->dev; + mbox->controller.num_chans = 1; + mbox->controller.chans = mbox->chans; + mbox->controller.ops = &mpfs_mbox_ops; + mbox->controller.txdone_irq = true; + + ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller); + if (ret) { + dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n"); + return ret; + } + dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n"); + + return 0; +} + +static const struct of_device_id mpfs_mbox_of_match[] = { + {.compatible = "microchip,polarfire-soc-mailbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match); + +static struct platform_driver mpfs_mbox_driver = { + .driver = { + .name = "mpfs-mailbox", + .of_match_table = mpfs_mbox_of_match, + }, + .probe = mpfs_mbox_probe, +}; +module_platform_driver(mpfs_mbox_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS mailbox controller driver"); diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h new file mode 100644 index 000000000000..2b64c95f3be5 --- /dev/null +++ b/include/soc/microchip/mpfs.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Microchip PolarFire SoC (MPFS) + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#ifndef __SOC_MPFS_H__ +#define __SOC_MPFS_H__ + +#include +#include + +struct mpfs_sys_controller; + +struct mpfs_mss_msg { + u8 cmd_opcode; + u16 cmd_data_size; + struct mpfs_mss_response *response; + u8 *cmd_data; + u16 mbox_offset; + u16 resp_offset; +}; + +struct mpfs_mss_response { + u32 resp_status; + u32 *resp_msg; + u16 resp_size; +}; + +#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg); + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node); + +#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ + +#endif /* __SOC_MPFS_H__ */ From patchwork Thu Jun 24 15:01:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 467049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4C5AC49EA6 for ; Thu, 24 Jun 2021 15:01:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8FEA7613C1 for ; Thu, 24 Jun 2021 15:01:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232300AbhFXPEK (ORCPT ); Thu, 24 Jun 2021 11:04:10 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:61392 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232172AbhFXPEK (ORCPT ); Thu, 24 Jun 2021 11:04:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1624546911; x=1656082911; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4p3t+4D2U+AKPg4n/O+ArrbzKLVo+0girpiXU0sKiVo=; b=HVlf9SpE+dgtLFDexsX/kciNELV7+hDsALruUot1pLQlPUB2CzjTGQTb EVP8XbZZ0sKJG3IWKpykpT9gs7DnxvcocSManVaB8q8pd/60pw0CLLznr DO97akETRPN/xTaRdG1fGFzQT10mDlAs6ZYp9lzAD9smYSkP83h/Y2bTN DL0ZFpr4n9dtYWs8GR93jM769RSdnSaS/3BYuL1bYGyC4Ld38qRlIduV3 IUxYQqoNdKtwg1rm1nqC4JJZ5+7BLmQX/gsnren1dz90AoMQwdwUTKgi1 DpLpNLPjsAdkPZOzz1+NzH4U9QxlaOTxCVQnoEQS0kIR7SuAQu6dm0vmu A==; IronPort-SDR: gYH0gztmGKoIz5RyPxBGq7++ny3ObjqqrWRBdtnr0REUqKI+DuD5zxjPeoEWMB3uCvDxMwwB+/ alFEdHq15YGFY/HSnfsNcfJVfuORXO+gQJVi5bs/ANqu87uDS3pJXk5ZLCjti59e2k7Tm2SaXH uyRrZrYYgt5Sjxhtt63sdobmAoPqKDJEhfIRGimOzwODSA3lJcftBtuzbdQMOBBBGJbR++uoDZ my0MCxxxdmS8aywN6zK9mbmIenMpcgGKmw4GlI683p0XdLDjL21p8WPf7YYhB5TF5oAd8+PGsi 3XA= X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="60084220" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Jun 2021 08:01:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 24 Jun 2021 08:01:42 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 08:01:39 -0700 From: To: , , , , , , , , , CC: , , , , , , Conor Dooley , Rob Herring Subject: [PATCH v9 3/5] dt-bindings: add bindings for polarfire soc system controller Date: Thu, 24 Jun 2021 16:01:39 +0100 Message-ID: <20210624150139.11528-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- ...icrochip,polarfire-soc-sys-controller.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml new file mode 100644 index 000000000000..2cd3bc6bd8d6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller + +maintainers: + - Conor Dooley + +description: | + The PolarFire SoC system controller is communicated with via a mailbox. + This document describes the bindings for the client portion of that mailbox. + + +properties: + mboxes: + maxItems: 1 + + compatible: + const: microchip,polarfire-soc-sys-controller + +required: + - compatible + - mboxes + +additionalProperties: false + +examples: + - | + syscontroller: syscontroller { + compatible = "microchip,polarfire-soc-sys-controller"; + mboxes = <&mbox 0>; + }; From patchwork Thu Jun 24 15:01:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 466463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92547C49EA7 for ; Thu, 24 Jun 2021 15:02:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71B666054E for ; Thu, 24 Jun 2021 15:02:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230267AbhFXPEX (ORCPT ); Thu, 24 Jun 2021 11:04:23 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:10332 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230249AbhFXPEX (ORCPT ); Thu, 24 Jun 2021 11:04:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1624546925; x=1656082925; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+hysN7uppNBxXU4G8gz4qACDyd+5MZH9w/le/rKF1kk=; b=XJOuv/fRfZ01faM/s24arWvbL43fGyAEBFVhjdy1CnYShmC6OIJKoKXz W6rXPaDlv1QRLQmsfx0KbQPzvDwbuLcdQsoIsQOFXIyO4ylApSZ6nniq8 CfPzuYN2MAEsSzgigEoneAM9FEKnyMIDpZ+2s3X2WwR/Wu7KOV1s2tjKX 0Y4a8SnFNBDxyyETMupLD4zjWyMvZfMb7q3dZ+Gqy+Xy8gqdZWb6hyqNc J6nYXqpgfdostBW1PZ7PKf+C1yycv+ql7yUAJln84jd9OHS9E+fy4gcTr 8lXBckdzMntM8/cwjJwdCZRZ0siK5bKHtRya7TfrnHMlWMJbiEyeP/5pi A==; IronPort-SDR: 3BF/SN3lAw5xFX05E8DTgYrKS9pQFhVk1GYPsBSWQ+NwVrMJb5H2pxgn87I8HcSGsYVwO1JUP3 sUpK9I95P++rYRBORHUl06W93Olqze4YGdHRnysVIEy1bki+Is4/CSIeonetl8gXR9WS+Lx83p 0x68mIHJzCg7SE8ttEwGZQnNHcUUstnffWblGnLvzdx2LR9p5Uf0Ht21WgGZwtjAB+n+ARF+l1 Rqg/w1RF/Z7Q1Rlw2lyK1muTZKMF+XUHzu8sGsoOcpKTF4rKYWhIsrvUDmSIZ2mzLe+PuBvNFd bUs= X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="125939057" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Jun 2021 08:01:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 24 Jun 2021 08:01:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 08:01:44 -0700 From: To: , , , , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH v9 4/5] soc: add polarfire soc system controller Date: Thu, 24 Jun 2021 16:01:44 +0100 Message-ID: <20210624150144.11590-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/microchip/Kconfig | 10 ++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-sys-controller.c | 121 ++++++++++++++++++++ 5 files changed, 134 insertions(+) create mode 100644 drivers/soc/microchip/Kconfig create mode 100644 drivers/soc/microchip/Makefile create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e8a30c4c5aec..b33142e020e0 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -12,6 +12,7 @@ source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" +source "drivers/soc/microchip/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index f678e4d9e585..10cfdcd972c7 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += mediatek/ +obj-y += microchip/ obj-y += amlogic/ obj-y += qcom/ obj-y += renesas/ diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig new file mode 100644 index 000000000000..eb656b33156b --- /dev/null +++ b/drivers/soc/microchip/Kconfig @@ -0,0 +1,10 @@ +config POLARFIRE_SOC_SYS_CTRL + tristate "POLARFIRE_SOC_SYS_CTRL" + depends on POLARFIRE_SOC_MAILBOX + help + This driver adds support for the PolarFire SoC (MPFS) system controller. + + To compile this driver as a module, choose M here. the + module will be called mpfs_system_controller. + + If unsure, say N. diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile new file mode 100644 index 000000000000..14489919fe4b --- /dev/null +++ b/drivers/soc/microchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c new file mode 100644 index 000000000000..b5c23cb5df2c --- /dev/null +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) system controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(transaction_lock); + +struct mpfs_sys_controller { + struct mbox_client client; + struct mbox_chan *chan; + struct completion c; + u32 enabled; +}; + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg) +{ + int ret; + + ret = mutex_lock_interruptible(&transaction_lock); + if (ret) + return ret; + + reinit_completion(&mpfs_client->c); + + ret = mbox_send_message(mpfs_client->chan, msg); + if (ret >= 0) { + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) { + ret = 0; + } else { + ret = -ETIMEDOUT; + dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout\n"); + } + } else { + dev_err(mpfs_client->client.dev, + "mpfs sys controller transaction returned %d\n", ret); + } + + mutex_unlock(&transaction_lock); + + return ret; +} +EXPORT_SYMBOL(mpfs_blocking_transaction); + +static void rx_callback(struct mbox_client *client, void *msg) +{ + struct mpfs_sys_controller *mpfs_client = + container_of(client, struct mpfs_sys_controller, client); + + complete(&mpfs_client->c); +} + +static int mpfs_sys_controller_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_sys_controller *mpfs_client; + + mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL); + if (!mpfs_client) + return -ENOMEM; + + mpfs_client->client.dev = dev; + mpfs_client->client.rx_callback = rx_callback; + mpfs_client->client.tx_block = 1U; + + mpfs_client->chan = mbox_request_channel(&mpfs_client->client, 0); + if (IS_ERR(mpfs_client->chan)) + return dev_err_probe(dev, PTR_ERR(mpfs_client->chan), + "Failed to get mbox channel\n"); + + init_completion(&mpfs_client->c); + + platform_set_drvdata(pdev, mpfs_client); + + dev_info(&pdev->dev, "Registered MPFS system controller driver\n"); + + return 0; +} + +struct mpfs_sys_controller * +mpfs_sys_controller_get(struct device_node *mss_node) +{ + struct platform_device *pdev = of_find_device_by_node(mss_node); + + if (!pdev) + return NULL; + + return platform_get_drvdata(pdev); +} +EXPORT_SYMBOL(mpfs_sys_controller_get); + +static const struct of_device_id mpfs_sys_controller_of_match[] = { + {.compatible = "microchip,polarfire-soc-sys-controller", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match); + +static struct platform_driver mpfs_sys_controller_driver = { + .driver = { + .name = "mpfs-sys-controller", + .of_match_table = mpfs_sys_controller_of_match, + }, + .probe = mpfs_sys_controller_probe, +}; +module_platform_driver(mpfs_sys_controller_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS system controller driver"); From patchwork Thu Jun 24 15:01:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 467048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4815AC49EA5 for ; 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IronPort-SDR: JQg4eJwB3AFpdM+Sl6Mxpb+DyL/xwgOk0ZVF2B6yYzhQnEvKUWz9Jt8bC7XGhUXqgk2/0bjvmY AB9HaQ3cHAfnQWb964ryfFTmlQrREgdfttA7LRQHAZC5Cg9FIiMuH6hyMwieo2kkz8oo/xkKBX hUIHWfXnDVOWpYacCYL1W8FmR9nc1aqwwFQ6acj++DK8mcCdNNh4wd3vCtpPbt/MG22E7AIgBU ymwmJmKQIcJkJ4TU9RzZn/xjgUG7K7ImyEyHDFc6o2JlwYESE6cNWjzTuxsZXH7o/yC6LWsS0N 9zc= X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="60084290" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Jun 2021 08:01:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 24 Jun 2021 08:01:55 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 08:01:52 -0700 From: To: , , , , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH v9 5/5] MAINTAINERS: add entry for polarfire soc mailbox Date: Thu, 24 Jun 2021 16:01:52 +0100 Message-ID: <20210624150152.11666-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add Lewis Hanly as a maintainer for the Microchip SoC directory and the system services mailbox driver Signed-off-by: Conor Dooley --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8c5ee008301a..dc549a60fddc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15705,6 +15705,14 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT +M: Lewis Hanly +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/mailbox/mailbox-mpfs.c +F: drivers/soc/microchip/ +F: include/soc/microchip/mpfs.h + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang