From patchwork Thu Jun 24 19:47:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 466437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 450F0C49EAB for ; Thu, 24 Jun 2021 19:48:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D781613EE for ; Thu, 24 Jun 2021 19:48:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232817AbhFXTu6 (ORCPT ); Thu, 24 Jun 2021 15:50:58 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:57997 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232805AbhFXTu6 (ORCPT ); Thu, 24 Jun 2021 15:50:58 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564118; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=YrIYc5RHw9lI1hfapLw2nYs17T/vihvpK3WWcZ6MUyQ=; b=NQG//UbG7p7VTzlBhDzJMESYjLYLqTeqOUG31wp47ok++sN6UOknzMEd+EUWb7Ku1od/wMq4 5ZEjbmFfX1yePp/sR3P89kfsVTp1X2QAi+uB3BV2EtP1La1qZqgQNDx248l2Z2tJlTtca4ox mHeAgwCMqAPuNJAP0/lwVEf3rsc= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-west-2.postgun.com with SMTP id 60d4e1877e5ba0fdc0a0a987 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:48:23 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id A5A93C4338A; Thu, 24 Jun 2021 19:48:23 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id D5294C43217; Thu, 24 Jun 2021 19:48:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D5294C43217 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 1/9] dt-bindings: remoteproc: qcom: pas: Add SC7280 MPSS support Date: Fri, 25 Jun 2021 01:17:30 +0530 Message-Id: <1624564058-24095-2-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MPSS PAS support for SC7280 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Matthias Kaehlcke Acked-by: Rob Herring --- Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index ad85617b43fa..28e41cef701c 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -25,6 +25,7 @@ properties: - qcom,qcs404-cdsp-pas - qcom,qcs404-wcss-pas - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sdx55-mpss-pas @@ -147,6 +148,7 @@ allOf: - qcom,msm8998-adsp-pas - qcom,qcs404-adsp-pas - qcom,qcs404-wcss-pas + - qcom,sc7280-mpss-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sm8150-adsp-pas @@ -287,6 +289,7 @@ allOf: contains: enum: - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas - qcom,sdx55-mpss-pas - qcom,sm8150-mpss-pas - qcom,sm8350-mpss-pas @@ -390,6 +393,7 @@ allOf: compatible: contains: enum: + - qcom,sc7280-mpss-pas - qcom,sdx55-mpss-pas - qcom,sm8150-mpss-pas - qcom,sm8350-mpss-pas @@ -463,6 +467,7 @@ allOf: contains: enum: - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas then: properties: resets: @@ -480,6 +485,7 @@ allOf: contains: enum: - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas - qcom,sm8150-adsp-pas - qcom,sm8150-cdsp-pas - qcom,sm8150-mpss-pas From patchwork Thu Jun 24 19:47:31 2021 Content-Type: text/plain; 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Thu, 24 Jun 2021 19:48:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 92C48C433D3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 2/9] remoteproc: qcom: pas: Add SC7280 Modem support Date: Fri, 25 Jun 2021 01:17:31 +0530 Message-Id: <1624564058-24095-3-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for booting the Modem DSP found on QTI SC7280 SoCs. Signed-off-by: Sibi Sankar --- drivers/remoteproc/qcom_q6v5_pas.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 282b56effe8b..a653f20a1fc6 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -768,6 +768,7 @@ static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init }, { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init }, { .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init}, + { .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init}, { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init}, { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init}, { .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource}, From patchwork Thu Jun 24 19:47:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 466436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17262C49EA6 for ; Thu, 24 Jun 2021 19:48:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0187A613E1 for ; Thu, 24 Jun 2021 19:48:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232871AbhFXTvC (ORCPT ); Thu, 24 Jun 2021 15:51:02 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:57997 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232847AbhFXTvB (ORCPT ); Thu, 24 Jun 2021 15:51:01 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564122; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=9bLGNmDATjl0rUFP7n52HvUKnH7Zer+7q57rzp4Kg+Y=; b=XqG+Y8oajt7S++w+ny414wTF/2G3C5Jao3Dl9pRQ5p89c7YU7u+/+JLuUbyxPEtbakrzdQzd ivwqPHzS55tpFulpsnLdAzqYB4e7dKyYBmiVU+pwdZaohHdXWQrothnCkZxS6CDEUaBrDPGD MTy5UDy+r1OQ5zB3jCZDWnawClo= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-east-1.postgun.com with SMTP id 60d4e1940090905e160d68f7 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:48:36 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 84C82C4360C; Thu, 24 Jun 2021 19:48:35 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4C1E6C4338A; Thu, 24 Jun 2021 19:48:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4C1E6C4338A Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 3/9] dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding Date: Fri, 25 Jun 2021 01:17:32 +0530 Message-Id: <1624564058-24095-4-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new modem compatible string for QTI SC7280 SoCs and introduce the "qcom,ext-regs" and "qcom,qaccept-regs" bindings needed by the modem sub-system running on SC7280 SoCs. Signed-off-by: Sibi Sankar Acked-by: Rob Herring --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32 ++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 494257010629..d802e57701b8 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -15,6 +15,7 @@ on the Qualcomm Hexagon core. "qcom,msm8996-mss-pil" "qcom,msm8998-mss-pil" "qcom,sc7180-mss-pil" + "qcom,sc7280-mss-pil" "qcom,sdm845-mss-pil" - reg: @@ -47,6 +48,7 @@ on the Qualcomm Hexagon core. qcom,msm8996-mss-pil: qcom,msm8998-mss-pil: qcom,sc7180-mss-pil: + qcom,sc7280-mss-pil: qcom,sdm845-mss-pil: must be "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack" @@ -87,6 +89,8 @@ on the Qualcomm Hexagon core. qcom,sc7180-mss-pil: must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi", "nav" + qcom,sc7280-mss-pil: + must be "iface", "xo", "snoc_axi", "offline" qcom,sdm845-mss-pil: must be "iface", "bus", "mem", "xo", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng" @@ -98,7 +102,7 @@ on the Qualcomm Hexagon core. reference to the list of 3 reset-controllers for the wcss sub-system reference to the list of 2 reset-controllers for the modem - sub-system on SC7180, SDM845 SoCs + sub-system on SC7180, SC7280, SDM845 SoCs - reset-names: Usage: required @@ -107,7 +111,7 @@ on the Qualcomm Hexagon core. must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" for the wcss sub-system must be "mss_restart", "pdc_reset" for the modem - sub-system on SC7180, SDM845 SoCs + sub-system on SC7180, SC7280, SDM845 SoCs For devices where the mba and mpss sub-nodes are not specified, mba/mpss region should be referenced as follows: @@ -173,6 +177,9 @@ For the compatible string below the following supplies are required: qcom,msm8998-mss-pil: must be "cx", "mx" qcom,sc7180-mss-pil: + must be "cx", "mx", "mss" + qcom,sc7280-mss-pil: + must be "cx", "mss" qcom,sdm845-mss-pil: must be "cx", "mx", "mss" @@ -198,6 +205,9 @@ For the compatible string below the following supplies are required: Definition: a phandle reference to a syscon representing TCSR followed by the three offsets within syscon for q6, modem and nc halt registers. + a phandle reference to a syscon representing TCSR followed + by the four offsets within syscon for q6, modem, nc and vq6 + halt registers on SC7280 SoCs. For the compatible strings below the following phandle references are required: "qcom,sc7180-mss-pil" @@ -208,6 +218,24 @@ For the compatible strings below the following phandle references are required: by the offset within syscon for conn_box_spare0 register used by the modem sub-system running on SC7180 SoC. +For the compatible strings below the following phandle references are required: + "qcom,sc7280-mss-pil" +- qcom,ext-regs: + Usage: required + Value type: + Definition: two phandles reference to syscons representing TCSR_REG and + TCSR register space followed by the two offset within the syscon + to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off + registers respectively. + +- qcom,qaccept-regs: + Usage: required + Value type: + Definition: a phandle reference to a syscon representing TCSR followed + by the three offsets within syscon for mdm, cx and axi + qaccept registers used by the modem sub-system running on + SC7280 SoC. + The Hexagon node must contain iommus property as described in ../iommu/iommu.txt on platforms which do not have TrustZone. From patchwork Thu Jun 24 19:47:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 467022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33D4AC49EB7 for ; Thu, 24 Jun 2021 19:48:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FF7A613E1 for ; Thu, 24 Jun 2021 19:48:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232864AbhFXTvC (ORCPT ); Thu, 24 Jun 2021 15:51:02 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:29608 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232851AbhFXTvB (ORCPT ); Thu, 24 Jun 2021 15:51:01 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564122; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=X7vj2e02vxqZySGLymVvVGrueUkU6mh0JD5tBwDdETQ=; b=NtxwflfZv/ggPXFoUr7qvV3YFPEP/Mg+EtbliKwaUDOAsxbyZ63ky4OpuaYoSDs1627Z3Tgz CyRViqfJ3669FLelxGy8rvutkfpu/NYL5wwn9kuLXhhg28v/QY1fpmkw1kLTjhkkUYmJRuKh USMsuZM6eriHCWewyOubf/hdXYY= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-east-1.postgun.com with SMTP id 60d4e1994ca9face34022be2 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:48:41 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 5001FC43148; Thu, 24 Jun 2021 19:48:41 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 09EFEC43460; Thu, 24 Jun 2021 19:48:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 09EFEC43460 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 4/9] iommu/arm-smmu-qcom: Request direct mapping for modem device Date: Fri, 25 Jun 2021 01:17:33 +0530 Message-Id: <1624564058-24095-5-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SID configuration requirement for Modem on SC7280 is similar to the ones found on SC7180/SDM845 SoCs. So, add the SC7280 modem compatible to the list to defer the programming of the modem SIDs to the kernel. Signed-off-by: Sibi Sankar --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 7771d40176de..90d471a387bf 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -179,6 +179,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,sc7180-mdss" }, { .compatible = "qcom,sc7180-mss-pil" }, { .compatible = "qcom,sc7280-mdss" }, + { .compatible = "qcom,sc7280-mss-pil" }, { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sdm845-mdss" }, { .compatible = "qcom,sdm845-mss-pil" }, From patchwork Thu Jun 24 19:47:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 466435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D6AAC49EA6 for ; Thu, 24 Jun 2021 19:49:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 342B1613F6 for ; Thu, 24 Jun 2021 19:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232417AbhFXTv3 (ORCPT ); Thu, 24 Jun 2021 15:51:29 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:53164 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232502AbhFXTv0 (ORCPT ); Thu, 24 Jun 2021 15:51:26 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564146; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=MWHYeYtEk0qF5cTCdbDuR20k/4XPFKEdMvheTpZeu8o=; b=qwee92edsh7p+BhOBtWM/sEIHAwY7/rIl40vSTpa50ppxQ8kINEQbF94CZ7lxvnniPkfTx4g WPoQNVb0UFtSBQwzqcmo72IHJRetu7L2W9ed+v4I0GQeqnCubB5HRGNrPC9EHebECGxy/Vmm pq1g2YYUlpuqGl7me8pGGVJ4D6M= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-east-1.postgun.com with SMTP id 60d4e1a51938941955804d5a (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:48:53 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id DB7E8C433D3; Thu, 24 Jun 2021 19:48:52 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id C4417C43144; Thu, 24 Jun 2021 19:48:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C4417C43144 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 5/9] remoteproc: mss: q6v5-mss: Add modem support on SC7280 Date: Fri, 25 Jun 2021 01:17:34 +0530 Message-Id: <1624564058-24095-6-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add out of reset sequence support for modem sub-system on SC7280 SoCs. It requires access to an additional set of qaccept registers, external power/clk control registers and halt vq6 register to put the modem back into reset. Signed-off-by: Sibi Sankar --- drivers/remoteproc/qcom_q6v5_mss.c | 245 ++++++++++++++++++++++++++++++++++++- 1 file changed, 241 insertions(+), 4 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 5d21084004cb..4e32811e0025 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -77,6 +77,14 @@ #define HALT_ACK_TIMEOUT_US 100000 +/* QACCEPT Register Offsets */ +#define QACCEPT_ACCEPT_REG 0x0 +#define QACCEPT_ACTIVE_REG 0x4 +#define QACCEPT_DENY_REG 0x8 +#define QACCEPT_REQ_REG 0xC + +#define QACCEPT_TIMEOUT_US 50 + /* QDSP6SS_RESET */ #define Q6SS_STOP_CORE BIT(0) #define Q6SS_CORE_ARES BIT(1) @@ -143,6 +151,9 @@ struct rproc_hexagon_res { bool has_alt_reset; bool has_mba_logs; bool has_spare_reg; + bool has_qaccept_regs; + bool has_ext_cntl_regs; + bool has_vq6; }; struct q6v5 { @@ -158,8 +169,18 @@ struct q6v5 { u32 halt_q6; u32 halt_modem; u32 halt_nc; + u32 halt_vq6; u32 conn_box; + u32 qaccept_mdm; + u32 qaccept_cx; + u32 qaccept_axi; + + u32 axim1_clk_off; + u32 crypto_clk_off; + u32 force_clk_on; + u32 rscc_disable; + struct reset_control *mss_restart; struct reset_control *pdc_reset; @@ -201,6 +222,9 @@ struct q6v5 { bool has_alt_reset; bool has_mba_logs; bool has_spare_reg; + bool has_qaccept_regs; + bool has_ext_cntl_regs; + bool has_vq6; int mpss_perm; int mba_perm; const char *hexagon_mdt_image; @@ -213,6 +237,7 @@ enum { MSS_MSM8996, MSS_MSM8998, MSS_SC7180, + MSS_SC7280, MSS_SDM845, }; @@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc) regmap_update_bits(qproc->conn_map, qproc->conn_box, AXI_GATING_VALID_OVERRIDE, 0); ret = reset_control_deassert(qproc->mss_restart); + } else if (qproc->has_ext_cntl_regs) { + regmap_write(qproc->conn_map, qproc->rscc_disable, 0); + reset_control_assert(qproc->pdc_reset); + reset_control_assert(qproc->mss_restart); + reset_control_deassert(qproc->pdc_reset); + ret = reset_control_deassert(qproc->mss_restart); } else { ret = reset_control_assert(qproc->mss_restart); } @@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc) ret = reset_control_reset(qproc->mss_restart); writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); reset_control_deassert(qproc->pdc_reset); - } else if (qproc->has_spare_reg) { + } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) { ret = reset_control_reset(qproc->mss_restart); } else { ret = reset_control_deassert(qproc->mss_restart); @@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc) } goto pbl_wait; - } else if (qproc->version == MSS_SC7180) { + } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) { val = readl(qproc->reg_base + QDSP6SS_SLEEP); val |= Q6SS_CBCR_CLKEN; writel(val, qproc->reg_base + QDSP6SS_SLEEP); @@ -787,6 +818,82 @@ static int q6v5proc_reset(struct q6v5 *qproc) return ret; } +static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) +{ + unsigned int val; + int ret; + + if (!qproc->has_qaccept_regs) + return 0; + + if (qproc->has_ext_cntl_regs) { + regmap_write(qproc->conn_map, qproc->rscc_disable, 0); + regmap_write(qproc->conn_map, qproc->force_clk_on, 1); + + ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, + !val, 1, Q6SS_CBCR_TIMEOUT_US); + if (ret) { + dev_err(qproc->dev, "failed to enable axim1 clock\n"); + return -ETIMEDOUT; + } + } + + regmap_write(map, offset + QACCEPT_REQ_REG, 1); + + /* Wait for accept */ + ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5, + QACCEPT_TIMEOUT_US); + if (ret) { + dev_err(qproc->dev, "qchannel enable failed\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) +{ + int ret; + unsigned int val, retry; + unsigned int nretry = 10; + bool takedown_complete = false; + + if (!qproc->has_qaccept_regs) + return; + + while (!takedown_complete && nretry) { + nretry--; + + regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5, + QACCEPT_TIMEOUT_US); + + regmap_write(map, offset + QACCEPT_REQ_REG, 0); + + retry = 10; + while (retry) { + usleep_range(5, 10); + retry--; + ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val); + if (!ret && val) { + regmap_write(map, offset + QACCEPT_REQ_REG, 1); + break; + } + + ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val); + if (!ret && !val) { + takedown_complete = true; + break; + } + } + + if (!retry) + break; + } + + if (!takedown_complete) + dev_err(qproc->dev, "qchannel takedown failed\n"); +} + static void q6v5proc_halt_axi_port(struct q6v5 *qproc, struct regmap *halt_map, u32 offset) @@ -950,6 +1057,12 @@ static int q6v5_mba_load(struct q6v5 *qproc) goto assert_reset; } + ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); + if (ret) { + dev_err(qproc->dev, "failed to enable axi bridge\n"); + goto disable_active_clks; + } + /* * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide * the Q6 access to this region. @@ -996,8 +1109,13 @@ static int q6v5_mba_load(struct q6v5 *qproc) halt_axi_ports: q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); + if (qproc->has_vq6) + q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); + q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm); + q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx); + q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); mba_load_err = true; reclaim_mba: xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, @@ -1047,6 +1165,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) qproc->dp_size = 0; q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); + if (qproc->has_vq6) + q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); if (qproc->version == MSS_MSM8996) { @@ -1059,6 +1179,24 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); } + if (qproc->has_ext_cntl_regs) { + regmap_write(qproc->conn_map, qproc->rscc_disable, 1); + + ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, + !val, 1, Q6SS_CBCR_TIMEOUT_US); + if (ret) + dev_err(qproc->dev, "failed to enable axim1 clock\n"); + + ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val, + !val, 1, Q6SS_CBCR_TIMEOUT_US); + if (ret) + dev_err(qproc->dev, "failed to enable crypto clock\n"); + } + + q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm); + q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx); + q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); + q6v5_reset_assert(qproc); q6v5_clk_disable(qproc->dev, qproc->reset_clks, @@ -1471,6 +1609,7 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) { struct of_phandle_args args; struct resource *res; + int halt_cell_cnt = 3; int ret; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); @@ -1483,8 +1622,11 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) if (IS_ERR(qproc->rmb_base)) return PTR_ERR(qproc->rmb_base); + if (qproc->has_vq6) + halt_cell_cnt++; + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, - "qcom,halt-regs", 3, 0, &args); + "qcom,halt-regs", halt_cell_cnt, 0, &args); if (ret < 0) { dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); return -EINVAL; @@ -1499,6 +1641,52 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) qproc->halt_modem = args.args[1]; qproc->halt_nc = args.args[2]; + if (qproc->has_vq6) + qproc->halt_vq6 = args.args[3]; + + if (qproc->has_qaccept_regs) { + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "qcom,qaccept-regs", + 3, 0, &args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse qaccept-regs\n"); + return -EINVAL; + } + + qproc->qaccept_mdm = args.args[0]; + qproc->qaccept_cx = args.args[1]; + qproc->qaccept_axi = args.args[2]; + } + + if (qproc->has_ext_cntl_regs) { + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "qcom,ext-regs", + 2, 0, &args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse ext-regs index 0\n"); + return -EINVAL; + } + + qproc->conn_map = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(qproc->conn_map)) + return PTR_ERR(qproc->conn_map); + + qproc->force_clk_on = args.args[0]; + qproc->rscc_disable = args.args[1]; + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "qcom,ext-regs", + 2, 1, &args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse ext-regs index 1\n"); + return -EINVAL; + } + + qproc->axim1_clk_off = args.args[0]; + qproc->crypto_clk_off = args.args[1]; + } + if (qproc->has_spare_reg) { ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,spare-regs", @@ -1590,7 +1778,7 @@ static int q6v5_init_reset(struct q6v5 *qproc) return PTR_ERR(qproc->mss_restart); } - if (qproc->has_alt_reset || qproc->has_spare_reg) { + if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) { qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, "pdc_reset"); if (IS_ERR(qproc->pdc_reset)) { @@ -1697,6 +1885,9 @@ static int q6v5_probe(struct platform_device *pdev) platform_set_drvdata(pdev, qproc); + qproc->has_qaccept_regs = desc->has_qaccept_regs; + qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs; + qproc->has_vq6 = desc->has_vq6; qproc->has_spare_reg = desc->has_spare_reg; ret = q6v5_init_mem(qproc, pdev); if (ret) @@ -1857,9 +2048,39 @@ static const struct rproc_hexagon_res sc7180_mss = { .has_alt_reset = false, .has_mba_logs = true, .has_spare_reg = true, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, .version = MSS_SC7180, }; +static const struct rproc_hexagon_res sc7280_mss = { + .hexagon_mba_image = "mba.mbn", + .proxy_clk_names = (char*[]){ + "xo", + NULL + }, + .active_clk_names = (char*[]){ + "iface", + "offline", + "snoc_axi", + NULL + }, + .proxy_pd_names = (char*[]){ + "cx", + "mss", + NULL + }, + .need_mem_protection = true, + .has_alt_reset = false, + .has_mba_logs = true, + .has_spare_reg = false, + .has_qaccept_regs = true, + .has_ext_cntl_regs = true, + .has_vq6 = true, + .version = MSS_SC7280, +}; + static const struct rproc_hexagon_res sdm845_mss = { .hexagon_mba_image = "mba.mbn", .proxy_clk_names = (char*[]){ @@ -1889,6 +2110,9 @@ static const struct rproc_hexagon_res sdm845_mss = { .has_alt_reset = true, .has_mba_logs = false, .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, .version = MSS_SDM845, }; @@ -1917,6 +2141,9 @@ static const struct rproc_hexagon_res msm8998_mss = { .has_alt_reset = false, .has_mba_logs = false, .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, .version = MSS_MSM8998, }; @@ -1948,6 +2175,9 @@ static const struct rproc_hexagon_res msm8996_mss = { .has_alt_reset = false, .has_mba_logs = false, .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, .version = MSS_MSM8996, }; @@ -1990,6 +2220,9 @@ static const struct rproc_hexagon_res msm8916_mss = { .has_alt_reset = false, .has_mba_logs = false, .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, .version = MSS_MSM8916, }; @@ -2040,6 +2273,9 @@ static const struct rproc_hexagon_res msm8974_mss = { .has_alt_reset = false, .has_mba_logs = false, .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, .version = MSS_MSM8974, }; @@ -2050,6 +2286,7 @@ static const struct of_device_id q6v5_of_match[] = { { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss}, { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss}, + { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss}, { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, { }, }; From patchwork Thu Jun 24 19:47:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 467020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE8BCC49EAB for ; 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Thu, 24 Jun 2021 19:49:00 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 12B6CC43149; Thu, 24 Jun 2021 19:48:58 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id A7FC9C4338A; Thu, 24 Jun 2021 19:48:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A7FC9C4338A Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 6/9] arm64: dts: qcom: sc7280: Update reserved memory map Date: Fri, 25 Jun 2021 01:17:35 +0530 Message-Id: <1624564058-24095-7-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing regions and remove unused regions from the reserved memory map, as described in version 1. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 52 +++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 34 +++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 3900cfc09562..191e8a92d153 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -30,6 +30,58 @@ }; }; +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the board dts. + * + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &reserved_xbl_uefi_log; +/delete-node/ &sec_apps_mem; + +/* Increase the size from 2.5MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x9c900000 0x0 0x800000>; +}; + +/ { + reserved-memory { + adsp_mem: memory@86700000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + camera_mem: memory@8ad00000 { + reg = <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: memory@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg = <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; +}; + &apps_rsc { pm7325-regulators { compatible = "qcom,pm7325-rpmh-regulators"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d1adf64e21e9..5ed7a511bfc9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -42,6 +42,16 @@ #size-cells = <2>; ranges; + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x200000>; + no-map; + }; + aop_mem: memory@80800000 { reg = <0x0 0x80800000 0x0 0x60000>; no-map; @@ -53,6 +63,16 @@ no-map; }; + reserved_xbl_uefi_log: memory@80880000 { + reg = <0x0 0x80884000 0x0 0x10000>; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; + }; + smem_mem: memory@80900000 { reg = <0x0 0x80900000 0x0 0x200000>; no-map; @@ -62,6 +82,20 @@ no-map; reg = <0x0 0x80b00000 0x0 0x100000>; }; + + wlan_fw_mem: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0xc00000>; + no-map; + }; + + rmtfs_mem: memory@9c900000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x9c900000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; }; cpus { From patchwork Thu Jun 24 19:47:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 466434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0AC9C49EB9 for ; Thu, 24 Jun 2021 19:49:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE127613B1 for ; Thu, 24 Jun 2021 19:49:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232900AbhFXTvo (ORCPT ); Thu, 24 Jun 2021 15:51:44 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:37659 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232879AbhFXTvn (ORCPT ); Thu, 24 Jun 2021 15:51:43 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564164; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=U3oyy9Wy1/W3yM/7R55rDsV8ZZWtSfsaxO4axT11yWo=; b=J+pOnzXHrSdSmnLGNcTBB1FB/8WBKJWe9vxssWbqI2X0WSWufKiPgeTgtMVsUZOaSG1PhNlT 9zX05jaV6hC6pysHk1Z9ofDs6LpseMB8vWIVgrn9sE11BvRHzVrZfjgC9MaqnbhP6jQDbJL5 L2H1aZYkPyzm0Iu+bc7axgOe1Pc= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 60d4e1b106ea41c941264ea3 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:49:05 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 070B1C4323A; Thu, 24 Jun 2021 19:49:05 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9F3DBC4360C; Thu, 24 Jun 2021 19:48:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9F3DBC4360C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 7/9] arm64: dts: qcom: sc7280: Add nodes to boot modem Date: Fri, 25 Jun 2021 01:17:36 +0530 Message-Id: <1624564058-24095-8-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add miscellaneous nodes to boot the modem and support post-mortem debug on SC7280 SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5ed7a511bfc9..3fb6a6ef39f8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -547,6 +547,11 @@ #hwlock-cells = <1>; }; + tcsr_regs: syscon@1fc0000 { + compatible = "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + }; + lpasscc: lpasscc@3000000 { compatible = "qcom,sc7280-lpasscc"; reg = <0 0x03000000 0 0x40>, @@ -1219,6 +1224,21 @@ }; }; + imem@146aa000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x146aa000 0 0x2000>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0 0x0 0 0x146aa000 0 0x2000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0 0x94c 0 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; From patchwork Thu Jun 24 19:47:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 467019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C7E0C49EA5 for ; Thu, 24 Jun 2021 19:49:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23E19613E1 for ; Thu, 24 Jun 2021 19:49:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232947AbhFXTvx (ORCPT ); Thu, 24 Jun 2021 15:51:53 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:29608 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232869AbhFXTvv (ORCPT ); Thu, 24 Jun 2021 15:51:51 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564172; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=u4pGnhlk1yX1orCgA43eLgI14IsX6mWl4H/bvIgWmdU=; b=Mv+BZw7ydPBp6/cmVPZD+LEd6rmwif12HA0OqE5m/tmQMwf1rc0Fcsio1YPUm0cOIXEtSJvQ BHoMT3TL+7AFdxwlOWrVmswP/gbRScwEhmZarOqS3nTeilYPLj9kQuaXqWL7eHwo10Dylkgn xsnZgo90D2nf2WOREYDe4opbXL8= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 60d4e1b87b2963a2825407ff (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:49:12 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 8BDD7C43144; Thu, 24 Jun 2021 19:49:10 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6715DC433D3; Thu, 24 Jun 2021 19:48:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6715DC433D3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 8/9] arm64: dts: qcom: sc7280: Add Q6V5 MSS node Date: Fri, 25 Jun 2021 01:17:37 +0530 Message-Id: <1624564058-24095-9-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Matthias Kaehlcke Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3fb6a6ef39f8..56ea172f641f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -584,6 +584,46 @@ #power-domain-cells = <1>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc7280-mpss-pas"; + reg = <0 0x04080000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC7280_CX>, + <&rpmhpd SC7280_MSS>; + power-domain-names = "cx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, From patchwork Thu Jun 24 19:47:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 466433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2422FC49EA6 for ; Thu, 24 Jun 2021 19:49:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 080856135C for ; Thu, 24 Jun 2021 19:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232970AbhFXTwF (ORCPT ); Thu, 24 Jun 2021 15:52:05 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:38403 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232932AbhFXTwD (ORCPT ); Thu, 24 Jun 2021 15:52:03 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1624564183; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=iaqWHZmgS8Lu3MlAqmI7Z55aQR1Dhk3as4p++438MG0=; b=VSenQBN7RQeZ/qKp6ZYl3N7HlpIGFAGqKDAmYE4XFPfR8UeyY9gEnKZRTxiwjP4NZncrwYSN h8yFhpPVwB0S2xQIUnFejt726vRZ4gwbWVndCdIikOIlTSZkiAbM731btMp+Je/XhgmUsRTO xDKzupIY0krlGCHl5+yneAqzq0Q= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-east-1.postgun.com with SMTP id 60d4e1be5e3e57240b977353 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 24 Jun 2021 19:49:18 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C5F08C43144; Thu, 24 Jun 2021 19:49:16 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 35C58C43145; Thu, 24 Jun 2021 19:49:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 35C58C43145 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: bjorn.andersson@linaro.org, robh+dt@kernel.org, will@kernel.org, saiprakash.ranjan@codeaurora.org Cc: ohad@wizery.com, agross@kernel.org, mathieu.poirier@linaro.org, robin.murphy@arm.com, joro@8bytes.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, evgreen@chromium.org, dianders@chromium.org, swboyd@chromium.org, Sibi Sankar Subject: [PATCH 9/9] arm64: dts: qcom: sc7280: Update Q6V5 MSS node Date: Fri, 25 Jun 2021 01:17:38 +0530 Message-Id: <1624564058-24095-10-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> References: <1624564058-24095-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update MSS node to support MSA based modem boot on SC7280 SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 7 +++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 191e8a92d153..d66e3ca42ad5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -343,3 +343,10 @@ bias-pull-up; }; }; + +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7280-mss-pil"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + memory-region = <&mba_mem &mpss_mem>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 56ea172f641f..6d3687744440 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -586,7 +586,8 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7280-mpss-pas"; - reg = <0 0x04080000 0 0x10000>; + reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, @@ -597,8 +598,11 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "offline", "snoc_axi", "xo"; power-domains = <&rpmhpd SC7280_CX>, <&rpmhpd SC7280_MSS>; @@ -611,6 +615,15 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + qcom,ext-regs = <&tcsr_regs 0x10000 0x10004 + &tcsr_mutex 0x26004 0x26008>; + qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; + status = "disabled"; glink-edge {