From patchwork Thu Jun 24 11:58:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 466341 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp382210jao; Thu, 24 Jun 2021 04:58:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhLPuMYKHElkY4rxd+CnEyWPocO6YuHcED0j8RWelhQOLceYiwd1K/IZ1RGwN8UT4sBsph X-Received: by 2002:a05:6402:d69:: with SMTP id ec41mr6732334edb.19.1624535898516; Thu, 24 Jun 2021 04:58:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624535898; cv=none; d=google.com; s=arc-20160816; b=lAs5tf6b+vvi3Fzv9onMkVbdcB5vFXoANQ2PsQVgptADQeIlnayLfEmibUGoxmsxJz TF5rGnY3jf+t+JdpC9T6ProB+wk7r/N17N+4tCQUsvfxRpDrH74wDFU6MngiIdmZ93Ch AOVjCdQg/yqearPnAq82K+Gi5yD+k+fHN+f+AgzWID1vLZvU6Kkpa5jGUllnP7iN+z7S z5J/n5StgCNgJG7eXjoPbulbk02Qgybl4ueQEEdLtKwpCC2GOKBU4W/yOXJaedhixN8+ Lxt/qCatJ+PChNeTsPzSDgr9omBxLEqlUNHyrA/HXPHRVxsDA54vRIZrOinzqr3D4eyv 1Xjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eijKYTcdSgjUORNbFd3aQ96Ibey7LIG8Pwg8gaFrgAg=; b=rzf6xanj8BJrW3oklTmugaEUGfnB4oSu6oa0m4y4LZUYriprP/60T+ECvRb7dKEHyA +16HGjr9MmuaSI8anrNh8Jo9WxPAOz0nlD3bmR0cutOwYEWudJQ15oLdk/S2MS4mUcHV 04mLRrznnCSxphiE/K63C48qMs6mwrjvvowfbIe7irlbjtm9iadKclogrdi+159ErzKo FkH0NnioMXYCw9EQ9dP1L9X8Q/793YKOktdT718F6521K24zj+OgBruzt7YcEg1Qn+HO lbgdT29rM2/V4bpOHvVU54d/U/MLSefZ9+j9jCbYAkm04SYFM9c7DUaVyxsKNfon1Q+s 7yWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JgMRZ1ot; spf=pass (google.com: domain of linux-pm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j12si2600954ejj.20.2021.06.24.04.58.18; Thu, 24 Jun 2021 04:58:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-pm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JgMRZ1ot; spf=pass (google.com: domain of linux-pm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230267AbhFXMAg (ORCPT + 8 others); Thu, 24 Jun 2021 08:00:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230225AbhFXMAf (ORCPT ); Thu, 24 Jun 2021 08:00:35 -0400 Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC3F7C061574 for ; Thu, 24 Jun 2021 04:58:16 -0700 (PDT) Received: by mail-qt1-x829.google.com with SMTP id x21so4544404qtq.9 for ; Thu, 24 Jun 2021 04:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eijKYTcdSgjUORNbFd3aQ96Ibey7LIG8Pwg8gaFrgAg=; b=JgMRZ1otbqrdr8v6RfG1O5qyiq+sc/UK6pR7wktlQI21P6U9Ot2ebbXpqyOfCswpXD vHnOrJq457FEZWbAPtRUd+0QxMYhptRZiNfxVN6WduYqUiNkjrraOj8V/VODKYnMfx7x UfS82fN7N2sE+mFkuiJQwL75JYtbA6JksESv3uMIQjW7zSgfAUKNwkGaoESy2x9yuu8N nLu0sXn9yBfr3QdST/FrJeuxBaM8SYzPjuFi7DgFg6dlsuBDJdPJgBlR3f+Dz52+qbUK pOLofkEx/PZ6MpDUCwec4rDfH9YKzJQIFIYr/xvdBa+SCqbqzUDrl99G966QjMJOtJ1H L2Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eijKYTcdSgjUORNbFd3aQ96Ibey7LIG8Pwg8gaFrgAg=; b=IzUblUQ0WeMxEkJIkAeVoWccmPnpR9qscqGeSM/5FYVJYYALZod1YNqIyxJTFHqGY+ cjTSSA2ejv8oeVfT2mx93OOw+yBRJ0icIc71GtT/XLj/WqFMu7OoFkB/ll8RYeEHRYxf J83qmjrAeINJC7DWOswnC+if/sqHaoqwKD7rSjvri/bjhsWjtqqAwneSodwWacUVOluZ HF1cpUzmA4e+enDawcVhZtCpG1JSe0un2RGGW2KoqZEaygk2Z/bj2w6/nzWiGs1PJA/O G0pch3LZ//wPbJa4cjetiYlFDUvW++r8qrjXTrnLC3Po39uI8vxu84GMHzQL2aB85TPs Py3Q== X-Gm-Message-State: AOAM530cF9Asrd00KZE1BVXRLpZzRaq/7jgK7UpQyB2ENWhwP+lCTj4P FDr5PzTfxFq7vXqxoYwXrjg7bg== X-Received: by 2002:ac8:7699:: with SMTP id g25mr4231845qtr.309.1624535896000; Thu, 24 Jun 2021 04:58:16 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id w3sm2287173qkp.55.2021.06.24.04.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 04:58:15 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v2 1/5] firmware: qcom_scm: Introduce SCM calls to access LMh Date: Thu, 24 Jun 2021 07:58:09 -0400 Message-Id: <20210624115813.3613290-2-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210624115813.3613290-1-thara.gopinath@linaro.org> References: <20210624115813.3613290-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce SCM calls to access/configure limits management hardware(LMH). Signed-off-by: Thara Gopinath --- v1->v2: Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review comments. drivers/firmware/qcom_scm.c | 54 +++++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 4 +++ include/linux/qcom_scm.h | 14 ++++++++++ 3 files changed, 72 insertions(+) -- 2.25.1 diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index ee9cb545e73b..19e9fb91d084 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1147,6 +1147,60 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) } EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); +bool qcom_scm_lmh_dcvsh_available(void) +{ + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); + +int qcom_scm_lmh_profile_change(u32 profile_id) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), + .args[0] = profile_id, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_profile_change); + +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version) +{ + dma_addr_t payload_phys; + u32 *payload_buf; + int payload_size = 5 * sizeof(u32); + + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_VAL, QCOM_SCM_VAL), + .args[1] = payload_size, + .args[2] = limit_node, + .args[3] = node_id, + .args[4] = version, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); + if (!payload_buf) + return -ENOMEM; + + payload_buf[0] = payload_fn; + payload_buf[1] = 0; + payload_buf[2] = payload_reg; + payload_buf[3] = 1; + payload_buf[4] = payload_val; + + desc.args[0] = payload_phys; + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 632fe3142462..d92156ceb3ac 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -114,6 +114,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SVC_HDCP 0x11 #define QCOM_SCM_HDCP_INVOKE 0x01 +#define QCOM_SCM_SVC_LMH 0x13 +#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01 +#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 + #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 0165824c5128..c0475d1c9885 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -109,6 +109,12 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); + +extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version); +extern int qcom_scm_lmh_profile_change(u32 profile_id); +extern bool qcom_scm_lmh_dcvsh_available(void); + #else #include @@ -170,5 +176,13 @@ static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; } + +static inline int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version) + { return -ENODEV; } + +static inline int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } + +static inline bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } #endif #endif From patchwork Thu Jun 24 11:58:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 466610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACB25C49EAF for ; Thu, 24 Jun 2021 11:58:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B908611CD for ; Thu, 24 Jun 2021 11:58:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230225AbhFXMAh (ORCPT ); Thu, 24 Jun 2021 08:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230308AbhFXMAg (ORCPT ); Thu, 24 Jun 2021 08:00:36 -0400 Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9F8DC061756 for ; Thu, 24 Jun 2021 04:58:17 -0700 (PDT) Received: by mail-qt1-x82a.google.com with SMTP id x21so4544447qtq.9 for ; Thu, 24 Jun 2021 04:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7aQPCJEPm39qd7fpESgLJT8mIRbMfhZrjqJmyb4g4Bc=; b=btP7+CL1DINZxYZnwfsWSJycd1kHuzajLbXMnGxVe71xQ8tgyOosRL5bgR6NidhOdm qidcG3ALAP4JBj/jg7Xz8T5xeSten2U2bM30hCqnnpEMhqpgtSDN0mLq8v0PH2tmJfha 4diP41Vbb5NRnAPcrNE2qlqlY0XQKBW20FUcZLuI/MtfIwqF6pt8rUY/3lCqhTQbE3EM i4FH4OLbwoxoIVDluks/IJxR0RHYtItLECH42XEeI1VArcv5eKhvW+BLZbH/OY8+fJJH jq+T0LBe9fx7M0bb0J3RlzKsj9bzZXheacFt3XEsF+uE0GlC8rZZH7yUiG8dqLKtiEr4 KaEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7aQPCJEPm39qd7fpESgLJT8mIRbMfhZrjqJmyb4g4Bc=; b=KvTvhWf55LnjraL5b+VVpNzKUbNIYGnDt8mUl15Txu0NMDV6Ffpz0NAl6d+U+VCpr3 COqVMmyfz5K6kvuhXWvFE7vN0PD+F6wcrK3P18GNrracLasZTDlienPK3kwDRA6IR+ao tsS/p7YGka2+wdUP8FtTedIRj+7rPcO5d/9xr1ekYfP9wd6Iqt5tMZSPT3SKV0N6MBcL gxUdRzddzCsmCoVa+GobO0BrbQMeOnsW94H1/XAKvW2EiXugelgD7dY0rIymVso755MP a+ic+bwNi6oDNWwwLUzaXz2QJP0KRyi0lEHJO/RmmQ6ufkEJ1Nh09JWsPPdwE1vt+V/3 rtxg== X-Gm-Message-State: AOAM5328pgYvcJX5waFCtUwGfHnlS76WAHigxX+3Oc996UwqdRHAUhpP NrXwUnJGBNYQoqqb3r4kldXr0g== X-Google-Smtp-Source: ABdhPJyo6dW/VHRmtbsoxHIK4a6bv80nadRLyuJCPpL2GXP3dZ4t8ukvHJHj6lFtCQ43iaklTElGZQ== X-Received: by 2002:ac8:7d91:: with SMTP id c17mr4310789qtd.287.1624535896985; Thu, 24 Jun 2021 04:58:16 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id w3sm2287173qkp.55.2021.06.24.04.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 04:58:16 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v2 2/5] thermal: qcom: Add support for LMh driver Date: Thu, 24 Jun 2021 07:58:10 -0400 Message-Id: <20210624115813.3613290-3-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210624115813.3613290-1-thara.gopinath@linaro.org> References: <20210624115813.3613290-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Driver enabling various pieces of Limits Management Hardware(LMh) for cpu cluster0 and cpu cluster1 namely kick starting monitoring of temperature, current, battery current violations, enabling reliability algorithm and setting up various temperature limits. The following has been explained in the cover letter. I am including this here so that this remains in the commit message as well. LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce temperature and current limits as programmed by software for certain IPs like CPU. On many newer LMh is configured by firmware/TZ and no programming is needed from the kernel side. But on certain SoCs like sdm845 the firmware does not do a complete programming of the h/w. On such soc's kernel software has to explicitly set up the temperature limits and turn on various monitoring and enforcing algorithms on the hardware. Signed-off-by: Thara Gopinath --- v1->v2: - Cosmetic and spelling fixes from review comments from Randy Dunlap - Added irq_disable to lmh_irq_ops and removed disabling of irq from lmh_handle_irq. Now cpufreq explicitly disables irq prior to handling it as per Bjorn's suggestion. - Rebased to new version of qcom_scm_lmh_dcvsh as changed in patch 1. - Removed generic dt compatible string and introduced platform specific one as per Bjorn's suggestion. - Take arm, low and high temp thresholds for LMh from dt properties instead of #defines in the driver as per Daniel's suggestion. - Other minor fixes. drivers/thermal/qcom/Kconfig | 10 ++ drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/lmh.c | 251 ++++++++++++++++++++++++++++++++++ 3 files changed, 262 insertions(+) create mode 100644 drivers/thermal/qcom/lmh.c diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index 8d5ac2df26dc..7d942f71e532 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -31,3 +31,13 @@ config QCOM_SPMI_TEMP_ALARM trip points. The temperature reported by the thermal sensor reflects the real time die temperature if an ADC is present or an estimate of the temperature based upon the over temperature stage value. + +config QCOM_LMH + tristate "Qualcomm Limits Management Hardware" + depends on ARCH_QCOM + help + This enables initialization of Qualcomm limits management + hardware(LMh). LMh allows for hardware-enforced mitigation for cpus based on + input from temperature and current sensors. On many newer Qualcomm SoCs + LMh is configured in the firmware and this feature need not be enabled. + However, on certain SoCs like sdm845 LMh has to be configured from kernel. diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 252ea7d9da0b..0fa2512042e7 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -5,3 +5,4 @@ qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o +obj-$(CONFIG_QCOM_LMH) += lmh.o diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c new file mode 100644 index 000000000000..a14cad83b459 --- /dev/null +++ b/drivers/thermal/qcom/lmh.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* + * Copyright (C) 2021, Linaro Limited. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define LMH_NODE_DCVS 0x44435653 +#define LMH_CLUSTER0_NODE_ID 0x6370302D +#define LMH_CLUSTER1_NODE_ID 0x6370312D + +#define LMH_SUB_FN_THERMAL 0x54484D4C +#define LMH_SUB_FN_CRNT 0x43524E54 +#define LMH_SUB_FN_REL 0x52454C00 +#define LMH_SUB_FN_BCL 0x42434C00 + +#define LMH_ALGO_MODE_ENABLE 0x454E424C +#define LMH_TH_HI_THRESHOLD 0x48494748 +#define LMH_TH_LOW_THRESHOLD 0x4C4F5700 +#define LMH_TH_ARM_THRESHOLD 0x41524D00 + +#define LMH_REG_DCVS_INTR_CLR 0x8 + +struct lmh_hw_data { + void __iomem *base; + struct irq_domain *domain; + int irq; + u32 cpu_id; +}; + +static irqreturn_t lmh_handle_irq(int hw_irq, void *data) +{ + struct lmh_hw_data *lmh_data = data; + int irq = irq_find_mapping(lmh_data->domain, 0); + + /* + * Call the cpufreq driver to handle the interrupt. + */ + if (irq) + generic_handle_irq(irq); + + return 0; +} + +static void lmh_enable_interrupt(struct irq_data *d) +{ + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d); + + /* Clear the existing interrupt */ + writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR); + enable_irq(lmh_data->irq); +} + +static void lmh_disable_interrupt(struct irq_data *d) +{ + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d); + + disable_irq_nosync(lmh_data->irq); +} + +static struct irq_chip lmh_irq_chip = { + .name = "lmh", + .irq_enable = lmh_enable_interrupt, + .irq_disable = lmh_disable_interrupt +}; + +static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + struct lmh_hw_data *lmh_data = d->host_data; + + irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, lmh_data); + + return 0; +} + +static const struct irq_domain_ops lmh_irq_ops = { + .map = lmh_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int lmh_probe(struct platform_device *pdev) +{ + struct device *dev; + struct device_node *np; + struct lmh_hw_data *lmh_data; + u32 node_id; + int temp_low, temp_high, temp_arm, ret; + + dev = &pdev->dev; + np = dev->of_node; + if (!np) + return -EINVAL; + + lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL); + if (!lmh_data) + return -ENOMEM; + + lmh_data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(lmh_data->base)) + return PTR_ERR(lmh_data->base); + + ret = of_property_read_u32(np, "qcom,lmh-cpu-id", &lmh_data->cpu_id); + if (ret) { + dev_err(dev, "missing qcom,lmh-cpu-id property\n"); + return ret; + } + + ret = of_property_read_u32(np, "qcom,lmh-temperature-high", &temp_high); + if (ret) { + dev_err(dev, "missing qcom,lmh-temperature-high property\n"); + return ret; + } + + ret = of_property_read_u32(np, "qcom,lmh-temperature-low", &temp_low); + if (ret) { + dev_err(dev, "missing qcom,lmh-temperature-low property\n"); + return ret; + } + + ret = of_property_read_u32(np, "qcom,lmh-temperature-arm", &temp_arm); + if (ret) { + dev_err(dev, "missing qcom,lmh-temperature-arm property\n"); + return ret; + } + + /* + * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed + * for other platforms, revisit this to check if the should be part + * of a dt match table. + */ + if (lmh_data->cpu_id == 0) { + node_id = LMH_CLUSTER0_NODE_ID; + } else if (lmh_data->cpu_id == 4) { + node_id = LMH_CLUSTER1_NODE_ID; + } else { + dev_err(dev, "Wrong CPU id associated with LMh node\n"); + return -EINVAL; + } + + platform_set_drvdata(pdev, lmh_data); + + if (!qcom_scm_lmh_dcvsh_available()) + return -EINVAL; + + /* Enable Thermal Algorithm */ + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error %d enabling thermal subfunction\n", ret); + return ret; + } + + /* Enable Current Sensing Algorithm */ + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error %d enabling current subfunction\n", ret); + return ret; + } + + /* Enable Reliability Algorithm */ + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error %d enabling reliability subfunction\n", ret); + return ret; + } + + /* Enable BCL Algorithm */ + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error %d enabling BCL subfunction\n", ret); + return ret; + } + + ret = qcom_scm_lmh_profile_change(0x1); + if (ret) { + dev_err(dev, "Error %d changing profile\n", ret); + return ret; + } + + /* Set default thermal trips */ + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret); + return ret; + } + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error setting thermal HI threshold%d\n", ret); + return ret; + } + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret); + return ret; + } + + lmh_data->irq = platform_get_irq(pdev, 0); + lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data); + if (!lmh_data->domain) { + dev_err(dev, "Error adding irq_domain\n"); + return -EINVAL; + } + + ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT | IRQF_NO_SUSPEND, + "lmh-irq", lmh_data); + if (ret) { + dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq); + irq_domain_remove(lmh_data->domain); + return ret; + } + + /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */ + disable_irq(lmh_data->irq); + + return 0; +} + +static const struct of_device_id lmh_table[] = { + { .compatible = "qcom,sdm845-lmh", }, + {} +}; +MODULE_DEVICE_TABLE(of, lmh_table); + +static struct platform_driver lmh_driver = { + .probe = lmh_probe, + .driver = { + .name = "qcom-lmh", + .of_match_table = lmh_table, + }, +}; +module_platform_driver(lmh_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QCOM LMh driver"); From patchwork Thu Jun 24 11:58:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 466609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0BABC49EB7 for ; Thu, 24 Jun 2021 11:58:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5BC0613CC for ; Thu, 24 Jun 2021 11:58:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230515AbhFXMAl (ORCPT ); Thu, 24 Jun 2021 08:00:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbhFXMAj (ORCPT ); Thu, 24 Jun 2021 08:00:39 -0400 Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8112C061756 for ; Thu, 24 Jun 2021 04:58:19 -0700 (PDT) Received: by mail-qt1-x82a.google.com with SMTP id t9so4535969qtw.7 for ; Thu, 24 Jun 2021 04:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rTRpC3uiw6MTlkqKW4TuhPSIXQr7Qt2j6LLeuz0vTvI=; b=tAbvLt9LtHb7XwdRozCDlbcHWH2wttPU6nspU3PwwNc/jYTRePpMvvJogDJS2ab3tN p2q8QBJZA1E4k22f8z9THTkmEmOEcSv+8+d9avxN8uAG8ELdgDsFpr0WrakxDW+Key/B nTzU73bNNpXd+IdPparXlw1MGzSOfDjIMZVGDEFCv4k5o2HmeqMUwqbq62elH9znRyy3 3NeS8gCqVLQ9RBd3uxlHF7mtwQ6VWyAxjAt7tDG6mvDcoPS6YXqb0VfbVnWmNqVvztil WxChLrlGGbJgDV0H2C84DBAxj5VyABESx482rju3rorLLsU0WgX8hUyMEy+Q+dWpblhJ fl3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTRpC3uiw6MTlkqKW4TuhPSIXQr7Qt2j6LLeuz0vTvI=; b=mJwcq4S//J8jlcu/dOHrvy8XxSTLMOZxoo9AEOIS0M7wyKa4CbyDyawrqM2IAVr6tn IfkZVRb3cWDiO07jR4TqS+zjYngvO+XSJ3KG9LtdbA5Pe6R/BawPIK1VTVcbkZ4hfWFy LuQthYIiGmm/U5Y8t/c2jNahijLvvlF5KZ1geFT1Y0U7IudDnvkQPn4uBrD7QpRQxxno 69tf0KxM2f4s9v1637Ayufk5weBtDp91M09pCT2k1FKdlOWC5ZwPan2pIdHikIQLNuSt aTz305WDDOM3jE2a++BWBT81bb7mmaDU+iGoXfvCeqUHiVJFNX/57X88i2Qd9NwovKyF gxCg== X-Gm-Message-State: AOAM5339ZyzuPbALewzX82+b6fIjq9vaF9RhyDU2XhPX50JBEeBFwuiK ocIJTTQKDlaJ9GA5CGSHz+jUzg== X-Google-Smtp-Source: ABdhPJyAwtibj3tAMnr/bmYnh5zjBnbuHkZ2Y0FaGlwH/JWcK90Jz9AlV2WRnEy3qDxsdRIsRrAi+A== X-Received: by 2002:ac8:59d4:: with SMTP id f20mr4359824qtf.189.1624535898877; Thu, 24 Jun 2021 04:58:18 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id w3sm2287173qkp.55.2021.06.24.04.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 04:58:18 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v2 4/5] arm64: boot: dts: qcom: sdm45: Add support for LMh node Date: Thu, 24 Jun 2021 07:58:12 -0400 Message-Id: <20210624115813.3613290-5-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210624115813.3613290-1-thara.gopinath@linaro.org> References: <20210624115813.3613290-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Signed-off-by: Thara Gopinath --- v1->v2: - Dropped dt property qcom,support-lmh as per Bjorn's review comments. - Changed lmh compatible from generic to platform specific. - Introduced properties specifying arm, low and high temp thresholds for LMh as per Daniel's suggestion. arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d..202fec09becd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3646,6 +3646,30 @@ swm: swm@c85 { }; }; + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x4>; + qcom,lmh-temperature-arm = <65000>; + qcom,lmh-temperature-low = <74500>; + qcom,lmh-temperature-high = <75000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x0>; + qcom,lmh-temperature-arm = <65000>; + qcom,lmh-temperature-low = <74500>; + qcom,lmh-temperature-high = <75000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + sound: sound { }; @@ -4911,6 +4935,8 @@ cpufreq_hw: cpufreq@17d43000 { reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate";