From patchwork Tue Jun 22 20:21:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 465248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA26BC49EAB for ; Tue, 22 Jun 2021 20:22:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 997D3613C7 for ; Tue, 22 Jun 2021 20:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229801AbhFVUYV (ORCPT ); Tue, 22 Jun 2021 16:24:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbhFVUYU (ORCPT ); Tue, 22 Jun 2021 16:24:20 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDCC5C061574; Tue, 22 Jun 2021 13:22:03 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id i24so475107edx.4; Tue, 22 Jun 2021 13:22:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wWlgqM4/GsaXHBR3lsRsq7dze3ZzgTNAhbjNgou3P9g=; b=RqB3hKDpArmGSJSSU9+qh628Y/Av3FGZvIWhzRs6GM6jrD04stjxHD1la7Nyxfy/xF 6c+tTuYnbM05rUqYCq9kwHM9POQy2UB2R7qCvXD6e/zmNBJxH5wVreUgZF0jEuBtFgGr fhLp6BaPzh7HvLheaMCQcjpW3XGO1vtnhhFUM0whRmFbk9lWTKgQ/mo481grwQmtZYWQ oC5llVXTAZ9WSqFX0g7JVy3ekskEVV4i5ac++u/QlNF0U/97TP/bc9Bl0Ow6vixb5AHT 6TGpT7EmDflZzrtJP6UXzcYqDe5Etysc/6UZEEoPsm1hj7iMIt4XY3/2P7Wx5hgUH1wR if5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wWlgqM4/GsaXHBR3lsRsq7dze3ZzgTNAhbjNgou3P9g=; b=SU4aOeeCLa+d//T64rfnD2nte0ta5E9B3EYIMBthdRYDlDnxpuv6ArVOlbVHtWP9xM MyEFHxGKG/BS0RcT0iMxQ5tcdLY65hlVlLZAWt3PHt0eUM7x5+UMv0yA3d4xWGT65FI4 kGZr15EK1mMt9aPUx0cWeQqv0ER28ngMdud10xOKYxKe03jQI68y9psnxQI0usRy7EOj jmK3R93i+bviZ6cJlLrHSGbKm+SJRymCOzkF8VX2qTM0eRn/uqQhZQm+FqyIpsxsZ5lE szn+74GQlNlYy0X9Oaaq2P7gpkrSQetA9pTIAQLEJ4J+E/VxvaG/kIqtwTvx3ZLD+KQU npug== X-Gm-Message-State: AOAM532P4uGeOdEhdEIi2wiDL8a7LyUye0IMhC7DxQgJ1oaW933Up7kD SuQXpoLw/KJmQ/83TuxR7wE= X-Google-Smtp-Source: ABdhPJxAdsQn5+vjpa3VM7IwGuv3GucqrMBQRb/iPy5MhjihrSQLSlROpy21VFe+4vBtFKNzaWLq2w== X-Received: by 2002:a05:6402:188:: with SMTP id r8mr7452569edv.75.1624393322624; Tue, 22 Jun 2021 13:22:02 -0700 (PDT) Received: from localhost (178-169-161-196.razgrad.ddns.bulsat.com. [178.169.161.196]) by smtp.gmail.com with ESMTPSA id yc20sm4675180ejb.5.2021.06.22.13.22.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Jun 2021 13:22:02 -0700 (PDT) From: Iskren Chernev To: Bjorn Andersson Cc: Andy Gross , Kathiravan T , Michael Turquette , Rajendra Nayak , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Iskren Chernev Subject: [PATCH v1 1/5] dt-bindings: soc: qcom: smd-rpm: Add SM4250, 6115 compatible Date: Tue, 22 Jun 2021 23:21:52 +0300 Message-Id: <20210622202156.546718-2-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210622202156.546718-1-iskren.chernev@gmail.com> References: <20210622202156.546718-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the dt-binding for the rpm on the Qualcomm SM4250 and SM6115 SoC platform. Signed-off-by: Iskren Chernev --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index d511f01fcac6..d9e97d8bc738 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -39,6 +39,8 @@ properties: - qcom,rpm-msm8996 - qcom,rpm-msm8998 - qcom,rpm-sdm660 + - qcom,rpm-sm4250 + - qcom,rpm-sm6115 - qcom,rpm-sm6125 - qcom,rpm-qcs404 From patchwork Tue Jun 22 20:21:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 465247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8509C49EA5 for ; Tue, 22 Jun 2021 20:22:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AFDCA61075 for ; Tue, 22 Jun 2021 20:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229774AbhFVUY1 (ORCPT ); Tue, 22 Jun 2021 16:24:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbhFVUYY (ORCPT ); Tue, 22 Jun 2021 16:24:24 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72DECC06175F; Tue, 22 Jun 2021 13:22:08 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id df12so493150edb.2; Tue, 22 Jun 2021 13:22:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IGxOTVhDeR7+VSK2BQTAkRHYfwpPBcI7fkcoGqIiLgQ=; b=YDN5u7cZPX8RNFIEiktPsd8SBpbGVy8BnWKD5e50kmFIZ7WMIN7JNK9m3tfKchEyYB pHGLg3faclltAr43ovZXew1217X3PdJhEM66U2LNWx9JPWsda8h2WpVbebUlGZMMgJtT A976YW8An4r5RW+mYIu2LNc1guH3sDvd4qjW7lU2580nP3C3g1aidXqt8gMzmI5dvmHO kQgrUlRLbrVXMiLwoZ6GnBRWvft2zAEzfxo/fSxP2drP0Yc0zCm3XYmsXtaTotUJJwx3 oyTEum7ULk1ahq3CeLHlfFKmqXa2NkacimT8OAXL22KnzbZeRzjYzaulAd5lT1Ib6szh GI8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IGxOTVhDeR7+VSK2BQTAkRHYfwpPBcI7fkcoGqIiLgQ=; b=DH9A9PR1IjVNKCVXMlAJR704wSLdU7scBIRe5LOQgSlBjv18VxNARgTHHXdB8BVZz9 kwcv73u2861c/Tt28P5qL2lpeSgoG2KBue/B5XU9zrmFoN17PUxVuswEOFU0+MqE84E9 jJp5qjp7mrPfiEIRhSV2A3zfJCOqOg6tJRwMYXaum6mu+lwnsvZ8rUesTZCANj7Dv1cM b41qHMlwgOWcT6ezXn6uS7L59p4nE3ZgjjtdOH7x9p0Y++1h96MJFYllzanQ9kfK86Ox mZwKIZp4diiWc0+CSh0saen5B9Ww+ifDwY/g4TsoBPgrFgp+vq+QVQ0ldu5OyhP3z97s H6cw== X-Gm-Message-State: AOAM530NR+ZC/7rXU61i9JqcTIu+1ILcouDOhrZ0jsJiNwwEAshartNm feaZ6WlPdWefydpGlVHq+7E= X-Google-Smtp-Source: ABdhPJxCBnF5Gv4eUi2dnWB8zI03CNTt5ZN9+YJj9XqfuPlAHZ0/F5WqoIlB54zLs4mtCdbKr5oGsA== X-Received: by 2002:a05:6402:3507:: with SMTP id b7mr7623583edd.66.1624393327092; Tue, 22 Jun 2021 13:22:07 -0700 (PDT) Received: from localhost (178-169-161-196.razgrad.ddns.bulsat.com. [178.169.161.196]) by smtp.gmail.com with ESMTPSA id dj24sm2431659edb.21.2021.06.22.13.22.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Jun 2021 13:22:06 -0700 (PDT) From: Iskren Chernev To: Bjorn Andersson Cc: Andy Gross , Kathiravan T , Michael Turquette , Rajendra Nayak , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Iskren Chernev Subject: [PATCH v1 3/5] clk: qcom: smd: Add support for SM6115 rpm clocks Date: Tue, 22 Jun 2021 23:21:54 +0300 Message-Id: <20210622202156.546718-4-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210622202156.546718-1-iskren.chernev@gmail.com> References: <20210622202156.546718-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add rpm smd clocks, PMIC and bus clocks which are required on SM4250/SM6115 for clients to vote on. Signed-off-by: Iskren Chernev --- drivers/clk/qcom/clk-smd-rpm.c | 64 ++++++++++++++++++++++++++++++++ drivers/soc/qcom/smd-rpm.c | 2 + include/linux/soc/qcom/smd-rpm.h | 1 + 3 files changed, 67 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index daf09dd61055..2c9de650bb63 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -913,6 +913,68 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { .num_clks = ARRAY_SIZE(sdm660_clks), }; +/* sm6115 */ +DEFINE_CLK_SMD_RPM_BRANCH(sm6115, bi_tcxo, bi_tcxo_ao, + QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM(sm6115, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sm6115, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6115, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM_BRANCH(sm6115, qdss_clk, qdss_a_clk, + QCOM_SMD_RPM_MISC_CLK, 1, 19200000); +DEFINE_CLK_SMD_RPM(sm6115, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6115, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6115, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6115, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6115, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); +DEFINE_CLK_SMD_RPM(sm6115, snoc_periph_clk, snoc_periph_a_clk, + QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6115, snoc_lpass_clk, snoc_lpass_a_clk, + QCOM_SMD_RPM_BUS_CLK, 5); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sm6115, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sm6115, rf_clk2, rf_clk2_a, 5); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sm6115, rf_clk1_pin, rf_clk1_a_pin, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sm6115, rf_clk2_pin, rf_clk2_a_pin, 5); + +static struct clk_smd_rpm *sm6115_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sm6115_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sm6115_bi_tcxo_ao, + [RPM_SMD_SNOC_CLK] = &sm6115_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6115_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &sm6115_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &sm6115_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6115_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6115_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &sm6115_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &sm6115_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &sm6115_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &sm6115_rf_clk2_a, + [RPM_SMD_CNOC_CLK] = &sm6115_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6115_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &sm6115_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &sm6115_ipa_a_clk, + [RPM_SMD_QUP_CLK] = &sm6115_qup_clk, + [RPM_SMD_QUP_A_CLK] = &sm6115_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &sm6115_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &sm6115_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &sm6115_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &sm6115_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6115_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6115_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6115_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6115_snoc_lpass_a_clk, + [RPM_SMD_CE1_CLK] = &sm6115_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &sm6115_ce1_a_clk, + [RPM_SMD_RF_CLK1_PIN] = &sm6115_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &sm6115_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &sm6115_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &sm6115_rf_clk2_a_pin, +}; + +static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { + .clks = sm6115_clks, + .num_clks = ARRAY_SIZE(sm6115_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, @@ -924,6 +986,8 @@ static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, + { .compatible = "qcom,rpmcc-sm4250", .data = &rpm_clk_sm6115 }, + { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index bc0be1d4be5f..83c844892643 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -242,6 +242,8 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-msm8996" }, { .compatible = "qcom,rpm-msm8998" }, { .compatible = "qcom,rpm-sdm660" }, + { .compatible = "qcom,rpm-sm4250" }, + { .compatible = "qcom,rpm-sm6115" }, { .compatible = "qcom,rpm-sm6125" }, { .compatible = "qcom,rpm-qcs404" }, {} diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index f2645ec52520..d350685039ad 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -37,6 +37,7 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_IPA_CLK 0x617069 #define QCOM_SMD_RPM_CE_CLK 0x6563 #define QCOM_SMD_RPM_AGGR_CLK 0x72676761 +#define QCOM_SMD_RPM_QUP_CLK 0x00707571 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, From patchwork Tue Jun 22 20:21:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 465246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC138C49EA5 for ; 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[178.169.161.196]) by smtp.gmail.com with ESMTPSA id jx9sm4087818ejc.110.2021.06.22.13.22.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Jun 2021 13:22:11 -0700 (PDT) From: Iskren Chernev To: Bjorn Andersson Cc: Andy Gross , Kathiravan T , Michael Turquette , Rajendra Nayak , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Iskren Chernev Subject: [PATCH v1 5/5] drivers: soc: qcom: rpmpd: Add SM6115 RPM Power Domains Date: Tue, 22 Jun 2021 23:21:56 +0300 Message-Id: <20210622202156.546718-6-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210622202156.546718-1-iskren.chernev@gmail.com> References: <20210622202156.546718-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SM6115 (and the compatible SM4250) have 4 rpm power domains, ported from downstream DT. Signed-off-by: Iskren Chernev --- drivers/soc/qcom/rpmpd.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 0b532a892d60..290b2f9db4e4 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -346,6 +346,33 @@ static const struct rpmpd_desc sdm660_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +/* sm6115 and sm4250 RPM Power domains */ +DEFINE_RPMPD_PAIR(sm6115, vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_VFL(sm6115, vddcx_vfl, RWCX, 0); + +DEFINE_RPMPD_PAIR(sm6115, vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_VFL(sm6115, vddmx_vfl, RWMX, 0); + +DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_cx, RWLC, 0); +DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_mx, RWLM, 0); + +static struct rpmpd *sm6115_rpmpds[] = { + [SM6115_VDDCX] = &sm6115_vddcx, + [SM6115_VDDCX_AO] = &sm6115_vddcx_ao, + [SM6115_VDDCX_VFL] = &sm6115_vddcx_vfl, + [SM6115_VDDMX] = &sm6115_vddmx, + [SM6115_VDDMX_AO] = &sm6115_vddmx_ao, + [SM6115_VDDMX_VFL] = &sm6115_vddmx_vfl, + [SM6115_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, + [SM6115_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, +}; + +static const struct rpmpd_desc sm6115_desc = { + .rpmpds = sm6115_rpmpds, + .num_pds = ARRAY_SIZE(sm6115_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, +}; + static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, @@ -356,6 +383,8 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, + { .compatible = "qcom,sm4250-rpmpd", .data = &sm6115_desc }, + { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmpd_match_table);