From patchwork Sat Jun 19 18:14:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463894 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1047367jao; Sat, 19 Jun 2021 11:19:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzb20bYSzXbB3govTKK3lUIvhluCeBxWTjevPWXaG5OvV6E27Gfi1bUq702Yp9dC+dvUUsf X-Received: by 2002:a05:620a:1a88:: with SMTP id bl8mr14693101qkb.480.1624126741944; Sat, 19 Jun 2021 11:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126741; cv=none; d=google.com; s=arc-20160816; b=dG8QmiI48zxb1utaiAc0q46ECUh9aHCJvZD57sAswAJ/pBNI9vBbLex2vKLKgUnvpw RKx/NtbiGwGzC1ezVmvM+CuFX1xjo03GleYQmWVyKKeKjrCFK/gxya4ZSNUhV+DEMi0l qmmVbJx/bJimWUzVfP0yb8/evk9gZHsaXQhE6EgtMD9cqHtEGRZ6uMUHJKCC7JxC0+gM Q9Bh+S1G4dvAQ4XzB636q3hx6n8YngNBk0bVi9RnyBuoaqdXuo7etGSKwGKw11Di+I73 frFY34wKrZsAXaF2NTf2aaJz5bQx4VDXCVItdvHuqUkDACIfGFIMDqQYF8Saf4a87gGd POCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4fKqYv8/HyyzIDsb2kKns/h9k87/3a9Ua+D2P7h6rxQ=; b=HlScEkLOxM8nDkDbv30JEAhvNbm9s2RPZmwkKM1/gXI49mTsFUNp/v9h/Kbkm/Cl5N g+hprsfUvwhhvkuMjZ28JB+U/jKM6HdQMzM4fN2BTgEWCukwhpZn+6Vnt8noclIyGRdN TNldez0/JDz/XUKv8OOmL/iI+N1Q/RxP4FqHZ8X7rlw6AmhjA6yybKRff0U0qx5khG+N Xo3OhrPTXeinMd56bFVexVnSlhoF0jgD7i7DUx6WeXyipxEDKbdCgsA2dqu/E85Eq8zX sNyx/XvFSuxVOccvQP8rIel+knRk88+WJexcCgN8I318mxVo4a8U9JaY5snK/3xwVdSW 9fIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SXRn1qti; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e187si6984997qkf.191.2021.06.19.11.19.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:19:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SXRn1qti; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufYb-0006XE-6n for patch@linaro.org; Sat, 19 Jun 2021 14:19:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUg-0000d2-0K for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:58 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:39733) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUd-0002CP-I3 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:57 -0400 Received: by mail-pf1-x436.google.com with SMTP id g192so2668571pfb.6 for ; Sat, 19 Jun 2021 11:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4fKqYv8/HyyzIDsb2kKns/h9k87/3a9Ua+D2P7h6rxQ=; b=SXRn1qtiy2EGwZ2bSoAuTL10OYbVZvCRy5HdZhb61sxvqkAEzPWI9/rt83b1QoiGD9 I3yREH8ayVQWRY0v1eu90f0uPfqjMZ37zo7vYIFGLxY7LqSDFwSFfXwIsQ+LEA/4IEB/ cmegoReA3m4Rmk36OBvO0aixD9DKY/cH3LatoFlK4DXW3M9cD56iCUz9ToihAc6IAi3Q owoJULxWvVXD9LFHnb3eyc6z6HiYTrl8TUT+SD/FH/jNc8z1XACOJBpRoX/ltquRgbaN THQLl3DYjTIAUAyASMwd4s14SCuzHjVQBLeA+hHdNdeIqii0SaY3pN3aVieU0Uoey3+4 F/yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4fKqYv8/HyyzIDsb2kKns/h9k87/3a9Ua+D2P7h6rxQ=; b=DyP/72rJg6uJGzVNO5huQRUhlryIDKeiipwTcGtDRhEPUX+queL9imdwYO61PB4A9s Q7VPvR2Dwo3vsdfoebxD9IA/3x2TrCM1HwHKATpu4ZBbAK++Ati2nuvZoBT7Tyser7M+ 6gI0WmYDZESW3lKFyN+1rhFo3Rb49BB1H79pnpD4lFgWVWYpAWzzEyJb0ERyDwTCUqdO ecDP3seLSRwEdCPvECC+C9ax9rbkvjzDu+3V20/gobDWMdL9UbozEldA4lmFLdgoaz5L 0zKmaV0kZMrw4uohThuyphWP//Uf3cFXhgvTmZLc6fPfgMXxiKpjeLpo39nsnBdyBn2q kpug== X-Gm-Message-State: AOAM532E+H+G387psxT+bOVgTH9pFeJfMmFPnT+QTgw9lyW9BCyPReo5 ju9wvpyclbpeanao59fzhuwJVSjb8B/qaA== X-Received: by 2002:a63:5619:: with SMTP id k25mr16196162pgb.92.1624126494109; Sat, 19 Jun 2021 11:14:54 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/33] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Date: Sat, 19 Jun 2021 11:14:20 -0700 Message-Id: <20210619181452.877683-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be interested in distinguishing pointers from integers in the helper's declaration, as well as a true void return. We currently have two parallel 1 bit fields; merge them and expand to a 3 bit field. Our current maximum is 7 helper arguments, plus the return makes 8 * 3 = 24 bits used within the uint32_t typemask. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 37 +++++-------------- include/exec/helper-tcg.h | 34 ++++++++--------- target/hppa/helper.h | 3 -- target/i386/ops_sse_header.h | 3 -- target/m68k/helper.h | 1 - target/ppc/helper.h | 3 -- tcg/tcg.c | 71 +++++++++++++++++++++--------------- 7 files changed, 67 insertions(+), 85 deletions(-) -- 2.25.1 diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 3094c7946d..b974eb394a 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -85,32 +85,14 @@ #define dh_retvar_ptr tcgv_ptr_temp(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) -#define dh_is_64bit_void 0 -#define dh_is_64bit_noreturn 0 -#define dh_is_64bit_i32 0 -#define dh_is_64bit_i64 1 -#define dh_is_64bit_ptr (sizeof(void *) == 8) -#define dh_is_64bit_cptr dh_is_64bit_ptr -#define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t)) - -#define dh_is_signed_void 0 -#define dh_is_signed_noreturn 0 -#define dh_is_signed_i32 0 -#define dh_is_signed_s32 1 -#define dh_is_signed_i64 0 -#define dh_is_signed_s64 1 -#define dh_is_signed_f16 0 -#define dh_is_signed_f32 0 -#define dh_is_signed_f64 0 -#define dh_is_signed_tl 0 -#define dh_is_signed_int 1 -/* ??? This is highly specific to the host cpu. There are even special - extension instructions that may be required, e.g. ia64's addp4. But - for now we don't support any 64-bit targets with 32-bit pointers. */ -#define dh_is_signed_ptr 0 -#define dh_is_signed_cptr dh_is_signed_ptr -#define dh_is_signed_env dh_is_signed_ptr -#define dh_is_signed(t) dh_is_signed_##t +#define dh_typecode_void 0 +#define dh_typecode_noreturn 0 +#define dh_typecode_i32 2 +#define dh_typecode_s32 3 +#define dh_typecode_i64 4 +#define dh_typecode_s64 5 +#define dh_typecode_ptr 6 +#define dh_typecode(t) glue(dh_typecode_, dh_alias(t)) #define dh_callflag_i32 0 #define dh_callflag_s32 0 @@ -126,8 +108,7 @@ #define dh_callflag_noreturn TCG_CALL_NO_RETURN #define dh_callflag(t) glue(dh_callflag_, dh_alias(t)) -#define dh_sizemask(t, n) \ - ((dh_is_64bit(t) << (n*2)) | (dh_is_signed(t) << (n*2+1))) +#define dh_typemask(t, n) (dh_typecode(t) << (n * 3)) #define dh_arg(t, n) \ glue(glue(tcgv_, dh_alias(t)), _temp)(glue(arg, n)) diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index 6888514635..16cd318b83 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -13,50 +13,50 @@ #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) }, + .typemask = dh_typemask(ret, 0) }, #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) }, #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ + | dh_typemask(t2, 2) }, #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ + | dh_typemask(t2, 2) | dh_typemask(t3, 3) }, #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ + | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) }, #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ - | dh_sizemask(t5, 5) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ + | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ + | dh_typemask(t5, 5) }, #define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ { .func = HELPER(NAME), .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ - | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ + | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ + | dh_typemask(t5, 5) | dh_typemask(t6, 6) }, #define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ - | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ - | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) }, + .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ + | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ + | dh_typemask(t5, 5) | dh_typemask(t6, 6) | dh_typemask(t7, 7) }, #include "helper.h" #include "trace/generated-helpers.h" diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 2d483aab58..0a629ffa7c 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,12 +1,9 @@ #if TARGET_REGISTER_BITS == 64 # define dh_alias_tr i64 -# define dh_is_64bit_tr 1 #else # define dh_alias_tr i32 -# define dh_is_64bit_tr 0 #endif #define dh_ctype_tr target_ureg -#define dh_is_signed_tr 0 DEF_HELPER_2(excp, noreturn, env, int) DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr) diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h index 6c0c849347..e68af5c403 100644 --- a/target/i386/ops_sse_header.h +++ b/target/i386/ops_sse_header.h @@ -30,9 +30,6 @@ #define dh_ctype_Reg Reg * #define dh_ctype_ZMMReg ZMMReg * #define dh_ctype_MMXReg MMXReg * -#define dh_is_signed_Reg dh_is_signed_ptr -#define dh_is_signed_ZMMReg dh_is_signed_ptr -#define dh_is_signed_MMXReg dh_is_signed_ptr DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 77808497a9..9842eeaa95 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -17,7 +17,6 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) #define dh_alias_fp ptr #define dh_ctype_fp FPReg * -#define dh_is_signed_fp dh_is_signed_ptr DEF_HELPER_3(exts32, void, env, fp, s32) DEF_HELPER_3(extf32, void, env, fp, f32) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index c517b9f025..4076aa281e 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -109,11 +109,9 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * -#define dh_is_signed_avr dh_is_signed_ptr #define dh_alias_vsr ptr #define dh_ctype_vsr ppc_vsr_t * -#define dh_is_signed_vsr dh_is_signed_ptr DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) @@ -697,7 +695,6 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl) #define dh_alias_fprp ptr #define dh_ctype_fprp ppc_fprp_t * -#define dh_is_signed_fprp dh_is_signed_ptr DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp) DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp) diff --git a/tcg/tcg.c b/tcg/tcg.c index ca482c2301..3d6e6b260c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -536,7 +536,7 @@ typedef struct TCGHelperInfo { void *func; const char *name; unsigned flags; - unsigned sizemask; + unsigned typemask; } TCGHelperInfo; #include "exec/helper-proto.h" @@ -1395,13 +1395,13 @@ bool tcg_op_supported(TCGOpcode op) void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) { int i, real_args, nb_rets, pi; - unsigned sizemask, flags; + unsigned typemask, flags; TCGHelperInfo *info; TCGOp *op; info = g_hash_table_lookup(helper_table, (gpointer)func); flags = info->flags; - sizemask = info->sizemask; + typemask = info->typemask; #ifdef CONFIG_PLUGIN /* detect non-plugin helpers */ @@ -1414,36 +1414,41 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) && !defined(CONFIG_TCG_INTERPRETER) /* We have 64-bit values in one register, but need to pass as two separate parameters. Split them. */ - int orig_sizemask = sizemask; + int orig_typemask = typemask; int orig_nargs = nargs; TCGv_i64 retl, reth; TCGTemp *split_args[MAX_OPC_PARAM]; retl = NULL; reth = NULL; - if (sizemask != 0) { - for (i = real_args = 0; i < nargs; ++i) { - int is_64bit = sizemask & (1 << (i+1)*2); - if (is_64bit) { - TCGv_i64 orig = temp_tcgv_i64(args[i]); - TCGv_i32 h = tcg_temp_new_i32(); - TCGv_i32 l = tcg_temp_new_i32(); - tcg_gen_extr_i64_i32(l, h, orig); - split_args[real_args++] = tcgv_i32_temp(h); - split_args[real_args++] = tcgv_i32_temp(l); - } else { - split_args[real_args++] = args[i]; - } + typemask = 0; + for (i = real_args = 0; i < nargs; ++i) { + int argtype = extract32(orig_typemask, (i + 1) * 3, 3); + bool is_64bit = (argtype & ~1) == dh_typecode_i64; + + if (is_64bit) { + TCGv_i64 orig = temp_tcgv_i64(args[i]); + TCGv_i32 h = tcg_temp_new_i32(); + TCGv_i32 l = tcg_temp_new_i32(); + tcg_gen_extr_i64_i32(l, h, orig); + split_args[real_args++] = tcgv_i32_temp(h); + typemask |= dh_typecode_i32 << (real_args * 3); + split_args[real_args++] = tcgv_i32_temp(l); + typemask |= dh_typecode_i32 << (real_args * 3); + } else { + split_args[real_args++] = args[i]; + typemask |= argtype << (real_args * 3); } - nargs = real_args; - args = split_args; - sizemask = 0; } + nargs = real_args; + args = split_args; #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 for (i = 0; i < nargs; ++i) { - int is_64bit = sizemask & (1 << (i+1)*2); - int is_signed = sizemask & (2 << (i+1)*2); - if (!is_64bit) { + int argtype = extract32(typemask, (i + 1) * 3, 3); + bool is_32bit = (argtype & ~1) == dh_typecode_i32; + bool is_signed = argtype & 1; + + if (is_32bit) { TCGv_i64 temp = tcg_temp_new_i64(); TCGv_i64 orig = temp_tcgv_i64(args[i]); if (is_signed) { @@ -1462,7 +1467,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) if (ret != NULL) { #if defined(__sparc__) && !defined(__arch64__) \ && !defined(CONFIG_TCG_INTERPRETER) - if (orig_sizemask & 1) { + if ((typemask & 6) == dh_typecode_i64) { /* The 32-bit ABI is going to return the 64-bit value in the %o0/%o1 register pair. Prepare for this by using two return temporaries, and reassemble below. */ @@ -1476,7 +1481,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) nb_rets = 1; } #else - if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) { + if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) == dh_typecode_i64) { #ifdef HOST_WORDS_BIGENDIAN op->args[pi++] = temp_arg(ret + 1); op->args[pi++] = temp_arg(ret); @@ -1497,7 +1502,9 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args = 0; for (i = 0; i < nargs; i++) { - int is_64bit = sizemask & (1 << (i+1)*2); + int argtype = extract32(typemask, (i + 1) * 3, 3); + bool is_64bit = (argtype & ~1) == dh_typecode_i64; + if (TCG_TARGET_REG_BITS < 64 && is_64bit) { #ifdef TCG_TARGET_CALL_ALIGN_ARGS /* some targets want aligned 64 bit args */ @@ -1542,7 +1549,9 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) && !defined(CONFIG_TCG_INTERPRETER) /* Free all of the parts we allocated above. */ for (i = real_args = 0; i < orig_nargs; ++i) { - int is_64bit = orig_sizemask & (1 << (i+1)*2); + int argtype = extract32(orig_typemask, (i + 1) * 3, 3); + bool is_64bit = (argtype & ~1) == dh_typecode_i64; + if (is_64bit) { tcg_temp_free_internal(args[real_args++]); tcg_temp_free_internal(args[real_args++]); @@ -1550,7 +1559,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args++; } } - if (orig_sizemask & 1) { + if ((orig_typemask & 6) == dh_typecode_i64) { /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them. Note that describing these as TCGv_i64 eliminates an unnecessary zero-extension that tcg_gen_concat_i32_i64 would create. */ @@ -1560,8 +1569,10 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 for (i = 0; i < nargs; ++i) { - int is_64bit = sizemask & (1 << (i+1)*2); - if (!is_64bit) { + int argtype = extract32(typemask, (i + 1) * 3, 3); + bool is_32bit = (argtype & ~1) == dh_typecode_i32; + + if (is_32bit) { tcg_temp_free_internal(args[i]); } } From patchwork Sat Jun 19 18:14:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463899 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1048661jao; Sat, 19 Jun 2021 11:21:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZB2fWSBnjO0cIBj33jFVIXrd4c+uAVi3G8H9trx2qneIsZ3j1lk0uM3RJFmv13AhZSNQ2 X-Received: by 2002:a1f:a897:: with SMTP id r145mr10486838vke.25.1624126891395; Sat, 19 Jun 2021 11:21:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126891; cv=none; d=google.com; s=arc-20160816; b=vRy6KzYvpxmt8ljEc7b8lSCbTJHH9P0QCT1rsS5euRB1kUqO3lw5EoPnQd/+FjhNow tZYg7jexRB937qyp+6jgyV/PYQaRdxuZx9A4xTR4Dl+KXb5Y6XKOqMLfzNaIwFpuLm9Z /AikB/M05EkHfe4YLegnVkfJtEz9Wwso3NxQ5TQ1doHaPA9G3TRuAh0Scc+Ci9XKgtHa pg0PJBoaMOhyM6/8ysT9Kuj+z4/9x9MYcMyrJYV4a0Dgllu4kD/mNXvq10JYr18YW+P8 cfuJ+1LqanNtj2MbEHiPdezev4b0rLcW3VqFtxWltNgQIZyR4qGFG3CHVuGXi5sjIaXb E2fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EdhOR4bbdTkQJ8JwWauxjmsHhxrFc7wx39xQEmIIlNk=; b=vDU1n8fT01m+OFm9jnKM3rS10s5/JSlXYsjvxhnuXkxKjJVHZkkX0NTeiVQWWsKjdv EChcul0ys+wgioliJVLlq4KzPIrOW4yoLYIcsZczUu3u81XodXBpd2xF6w7xhABa74Gk DR02dBUx//dy2U9EmHQ0JhBVIOdWhX2GAtGZcXIMIFelH8mbKPZb4DVpDaXexQy5om5x HheAcm1Kr1HhfCUmuYy3DWmOb41wJQxex2cVCIWAOnnX+zVc/IHRuMkHR+RUo+7I2sM3 lEQI3S8Arq13BoibQTAYf5VpDGyw62TVUULPyq8f18r4GhYZ5TXSLc0Orem/27qQRVMX zarQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aTw6s8p5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n13si4523423vkl.80.2021.06.19.11.21.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:21:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aTw6s8p5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufb0-0005ye-OR for patch@linaro.org; Sat, 19 Jun 2021 14:21:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUj-0000gk-33 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:01 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:44693) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUd-0002Cz-UD for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:00 -0400 Received: by mail-pf1-x42f.google.com with SMTP id u18so4989552pfk.11 for ; Sat, 19 Jun 2021 11:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EdhOR4bbdTkQJ8JwWauxjmsHhxrFc7wx39xQEmIIlNk=; b=aTw6s8p5DLyQl0qMrZeY4HFjOKnbBdgC6t6qLQ2eQP79GW+SbbdfL67rTjHHYfj8Fa wSVWKt0H/5Fo9iuuqsuOMRzKS0j5YaPw7QNmy4n4C/G4W0fT66SBz2mqPuedpyjbrnna geF0V8GDwCQn6lcn9ThU4BtgXUF2ohH4MBQylVQo5EXUIbNCL06L86v0K3A+cR79evXa N2UcevSMDru128REHTGF1o0aT797rLoRfhqH3PSL7l5HoTwN4gqbBrW/eIqRjWIlgVBu IEz73LxFJtR5YOBAVkj3TnryAQOuNFfn23/coHQeB5QBg1r9QhlgUYQgTneIhuTVjC2V LoZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EdhOR4bbdTkQJ8JwWauxjmsHhxrFc7wx39xQEmIIlNk=; b=kO6+DGIyL+/tBq4loQiVBOnG6I68jlozK0bqbJDRtrgyKDrDS3I6RA9em5y1dtZsnY jmVQgTcUXIO4xkfDU+8K+SCWsR9LSJgM73uGv3EgYRgKLDd3Fe9VtCrQsOE+V/S/ndbH dwPOs3mO/KeNSSiwe3w4YbsBeNRgv71mEZ5DEbySONvrDnTMz30fbPdSP9MuqVjE+lpt 8WOxSsuG43Qu7qShnQ6gj05+vHRC+ojToArwUNoThOjOD4aP0UkBWin9ouSyEUrE97l0 DjxEk+MciKrLfpWqiWp4M+lK0Y8jz6Q8T7J6tFZn/DhK9TvFtztK5EmaHsIGGJuytLVu BYvw== X-Gm-Message-State: AOAM532hMb3JsNDirgEoJ7ZqNVprll7t9ffxFAanqpiZJXIF95Q1JC34 m7y+FkjyL9nclndoU67u9Os1CiXWx0wuzQ== X-Received: by 2002:a63:bf0d:: with SMTP id v13mr15762243pgf.303.1624126494561; Sat, 19 Jun 2021 11:14:54 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/33] tcg: Add tcg_call_flags Date: Sat, 19 Jun 2021 11:14:21 -0700 Message-Id: <20210619181452.877683-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're going to change how to look up the call flags from a TCGop, so extract it as a helper. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 5 +++++ tcg/optimize.c | 3 ++- tcg/tcg.c | 14 ++++++-------- 3 files changed, 13 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 181f86507a..0796407c13 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -37,4 +37,9 @@ bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); void tcg_region_prologue_set(TCGContext *s); +static inline unsigned tcg_call_flags(TCGOp *op) +{ + return op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; +} + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/optimize.c b/tcg/optimize.c index 37c902283e..211a4209a0 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "tcg/tcg-op.h" +#include "tcg-internal.h" #define CASE_OP_32_64(x) \ glue(glue(case INDEX_op_, x), _i32): \ @@ -1481,7 +1482,7 @@ void tcg_optimize(TCGContext *s) break; case INDEX_op_call: - if (!(op->args[nb_oargs + nb_iargs + 1] + if (!(tcg_call_flags(op) & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { for (i = 0; i < nb_globals; i++) { if (test_bit(i, temps_used.l)) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 3d6e6b260c..51c1f61828 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1766,9 +1766,9 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) nb_cargs = def->nb_cargs; /* function name, flags, out args */ - col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, + col += qemu_log(" %s %s,$0x%x,$%d", def->name, tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), - op->args[nb_oargs + nb_iargs + 1], nb_oargs); + tcg_call_flags(op), nb_oargs); for (i = 0; i < nb_oargs; i++) { col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), op->args[i])); @@ -2155,7 +2155,6 @@ static void reachable_code_pass(TCGContext *s) QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { bool remove = dead; TCGLabel *label; - int call_flags; switch (op->opc) { case INDEX_op_set_label: @@ -2200,8 +2199,7 @@ static void reachable_code_pass(TCGContext *s) case INDEX_op_call: /* Notice noreturn helper calls, raising exceptions. */ - call_flags = op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; - if (call_flags & TCG_CALL_NO_RETURN) { + if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) { dead = true; } break; @@ -2402,7 +2400,7 @@ static void liveness_pass_1(TCGContext *s) nb_oargs = TCGOP_CALLO(op); nb_iargs = TCGOP_CALLI(op); - call_flags = op->args[nb_oargs + nb_iargs + 1]; + call_flags = tcg_call_flags(op); /* pure functions can be removed if their result is unused */ if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { @@ -2717,7 +2715,7 @@ static bool liveness_pass_2(TCGContext *s) if (opc == INDEX_op_call) { nb_oargs = TCGOP_CALLO(op); nb_iargs = TCGOP_CALLI(op); - call_flags = op->args[nb_oargs + nb_iargs + 1]; + call_flags = tcg_call_flags(op); } else { nb_iargs = def->nb_iargs; nb_oargs = def->nb_oargs; @@ -3799,7 +3797,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) TCGRegSet allocated_regs; func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; - flags = op->args[nb_oargs + nb_iargs + 1]; + flags = tcg_call_flags(op); nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); if (nb_regs > nb_iargs) { From patchwork Sat Jun 19 18:14:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463889 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1045418jao; Sat, 19 Jun 2021 11:15:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPtYOuR0eq8x+LOL6feGe4I6lP9RCDhUQE+vVNYfBa/c6B3PgbX144C6hgHrmaewVn0EVp X-Received: by 2002:ac8:4c8c:: with SMTP id j12mr15970944qtv.390.1624126547363; Sat, 19 Jun 2021 11:15:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126547; cv=none; d=google.com; s=arc-20160816; b=x6J9Ia6H0S04a1AS0KmOfkzeS8CmgTbKuwwExURv4GQ76qCofnlWey5eUUVIUmYfmN LHLwBenteUxnWd9/UuS3F/o1GuutjJLrgRtI7BbjKGtK7FGjzdsdiHOv+448yXJrAzh7 MImH6droZrqjVQyxmNVI7CE9PCnJkiXhpw3/k0d3wLdLbHynpv33xVZviludI+nPoc8p LoCb34gMhKcb1f/zGBbABsdRlBGcViqVbD/4Y3Vde72UtEDxMiZqFI75ZQrrr99u4Pl5 dVMKi+5Zr7BB46rsVewXvU+y0OyZq2Mn0ZknDnKKviCsVC96v5TFbVhs8gQjbWv9oQ7h SdcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+jwIdOBO2HuauixyPD0ovcZT3pv5ECKgnsaAtql7n/I=; b=oekqL47XRJppkgJj8IPdzHZNXGZnX4dbKBg/NgvzMqrFfUAMDCRiUl+8g8X8HE6Jt7 gR+GNWbAcy8PcDEOGrP9xCdIUcqqcdew9Z3j215vKBTEo5lWaSfnhdAbCyh53iD+/jEo 5SXkkCaVogoXO0AI/M7DQHM4bJbLYVOK0cU6EyUoOSSWQncIwYPOdfi3gRKQwHqOaxXZ 3+wgbdzVgcJivx8NXplzNHQ1pTjQXtScMijWwjN8NDyvCrVLCc0LnvJuFLQYyXnsg/ks 6ZEvh6FngE1qagAiPeIb3rl1vRWGLcG3MGhKL5Ue+fff7K7RkV+3fvVsA0FAvp3MwsDc BUNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=amfjWPW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s4si9717873qvs.68.2021.06.19.11.15.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:15:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=amfjWPW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufVS-0000gP-QK for patch@linaro.org; Sat, 19 Jun 2021 14:15:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUg-0000dA-Vz for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:59 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:43613) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUe-0002D4-AD for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:58 -0400 Received: by mail-pl1-x631.google.com with SMTP id v12so6328953plo.10 for ; Sat, 19 Jun 2021 11:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+jwIdOBO2HuauixyPD0ovcZT3pv5ECKgnsaAtql7n/I=; b=amfjWPW9I9KgJtRnMC3EcVGWoxLVItHMgGzHgTvjVV3rlAy0tfDM1Z2+qfMYhya6IU 6VosD7T/K/rjT6zQ3aiWrjO0peRmIu56dGwBJWl+Bq4opnTKaqjibrTzeMkSts8/4Er/ Sdp5L2nQUzpNd1NQFBx+M+0rRi7ME8PyxI116R3TuMae8S7pWc0MwlrN8wpH1IpRPYvH nXls+EQQW/vjxf89bcMTf1c4nlke4DZbhH+DTBXxeFJGfDLRT9dvaz1e4KedZMto4URH 9OI99OsHsVXEgCJKf2Es1t24q3uVaUitHDHtWi4iHwUAIPVaov5NhcrcS9njrPCvvqUR UTgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+jwIdOBO2HuauixyPD0ovcZT3pv5ECKgnsaAtql7n/I=; b=r0gZxjo+3cFyHoCOZxQbo0eg9doYkc1asxfbNcF2Zki4e3g70Lgy3/aGilYVjMgHMg 5MIdlVhnblPw9EjYzRNHwcPRN9KMf9nlAt1fb3tl9eK/FQZo+zvIeC3kIPgY6GAtgE0k dDutAvrAILhMwUnLgZ7Ug/595HY7dKmh4feOABF5SwrK/l3m5Q5+5pEL3q9hlvXXbtoJ 3v++QheXfpptXrLaNRKsLue42zqBIszGjUM2dPD1brpGI1oydFxZXnabxFyiME61dNrD LUVfMxsVQ7eNzSsLQ8h7TqZawsXFRrUGGoWlFgh5PBplG20V4EJendE4JeMHYqsfPkgk KStg== X-Gm-Message-State: AOAM532JKt+diw4EF7A/GlWczU81DpcihOGDbTmETLjuapjvycjOLahi hdROL4+8m+jhVaAiVPPH6c0K1eB/8XP0Vw== X-Received: by 2002:a17:90a:4217:: with SMTP id o23mr28795487pjg.110.1624126495087; Sat, 19 Jun 2021 11:14:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/33] accel/tcg/plugin-gen: Drop inline markers Date: Sat, 19 Jun 2021 11:14:22 -0700 Message-Id: <20210619181452.877683-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Let the compiler decide on inlining. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 7627225aef..48bd2f36f0 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -160,9 +160,8 @@ static void gen_empty_mem_helper(void) tcg_temp_free_ptr(ptr); } -static inline -void gen_plugin_cb_start(enum plugin_gen_from from, - enum plugin_gen_cb type, unsigned wr) +static void gen_plugin_cb_start(enum plugin_gen_from from, + enum plugin_gen_cb type, unsigned wr) { TCGOp *op; @@ -179,7 +178,7 @@ static void gen_wrapped(enum plugin_gen_from from, tcg_gen_plugin_cb_end(); } -static inline void plugin_gen_empty_callback(enum plugin_gen_from from) +static void plugin_gen_empty_callback(enum plugin_gen_from from) { switch (from) { case PLUGIN_GEN_AFTER_INSN: @@ -513,9 +512,8 @@ static bool op_rw(const TCGOp *op, const struct qemu_plugin_dyn_cb *cb) return !!(cb->rw & (w + 1)); } -static inline -void inject_cb_type(const GArray *cbs, TCGOp *begin_op, inject_fn inject, - op_ok_fn ok) +static void inject_cb_type(const GArray *cbs, TCGOp *begin_op, + inject_fn inject, op_ok_fn ok) { TCGOp *end_op; TCGOp *op; From patchwork Sat Jun 19 18:14:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463891 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1045793jao; Sat, 19 Jun 2021 11:16:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlymZIqDmMJA3AcWlSVfSyZIhSYxoH7l+gB7ig2tPaXziAD5JSxgs5C2zbAAz88CgaexGM X-Received: by 2002:ac8:5c0f:: with SMTP id i15mr16044396qti.252.1624126586048; Sat, 19 Jun 2021 11:16:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126586; cv=none; d=google.com; s=arc-20160816; b=Upw5m8sk2d7VS4hn1jPXALZzG4JpyY2wimmvXrV9aDQXm9C21L7zBKkJbgfNgRofgZ p4GSXr5mVijSpSxaUrpBEpum/iFuoBrITgnCl7UyOMalU/oDv3cD0aCq6lUq5Q3aKvSu S56lUjfoDRcROJsaY90fU2m+e6R4r2iKo6IaDON1Yk4TuiGPljSvw/rgYFmVlZc6H7Vz 4E7hCefpeo6UnM+HMYzNmnw3o+jahQQu4e18jzOc6BuF5kUqTgWVHZ+rBIX9SvwMlAGZ QY5ai1f4Tsg1II3TcO4YUUSsgmu5ch4iaz4yuIhZPDRCN72k5yXJXJzYpkRKEh4FeiUT FadA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OeLRNKnSJRWwobrAkPzoaUrmD8xwClpaPzu+CpkjnbQ=; b=YHzLM3qH1oJRNzQReovZOrNbOnip9h+WdamoWONOfFBctf2SiAXv+Zr35vLWw6RY/M 5h9bL+VU2Ke49BaXcraBc1jw5LiufEwYbU6QO2l3/p6Wj/qf83TvUBFnLUWJbMgltJ2I vQ0a+2Qk6gsH4bwbdlDnEfEni/u2xHQziqDLkRgfqvlwq1ODXDixRbgUwHdEgRCf1fY6 jpICUBkSTF4OZDpOFzSgWgkGEeMhdLBWGIJWYleyptofyLw0w5ehyt4ikxRJbf3IjyKW fThV36vuwQhTddywbzTwpmS8C80b4Sk3/ii8+uBsT1MLeN5hQFh+RTsnCCpuSMENwcow sriQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=agl3FJWI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e2si10303284qtw.97.2021.06.19.11.16.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:16:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=agl3FJWI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufW5-0000gv-AR for patch@linaro.org; Sat, 19 Jun 2021 14:16:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUh-0000dR-C1 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:59 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:40604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUf-0002DR-7X for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:59 -0400 Received: by mail-pf1-x42e.google.com with SMTP id q192so3785959pfc.7 for ; Sat, 19 Jun 2021 11:14:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OeLRNKnSJRWwobrAkPzoaUrmD8xwClpaPzu+CpkjnbQ=; b=agl3FJWIRG00NOqapEFBJmruUMYVlbMjIj8jP0ZXYlCkB/yqEHWc53TMfUDh9fOaNE GHgu+JYj/uaetmue6ynmiRuJ5nfo2ChW8UXvKa3jjlF6EB2SvXFxc+r2tvzKXgwXqOZs p7NC6nC0TlS/H5ykHsT70aVKGYlbzeueBMqgAktVhqAPbZ6JmoV3BW4FAnO5okAwDZfz zLW1KsFCVs+muRVqu7yrc4gz0yNaMWmGz2T4fauO7fkCe1HFV61IEFNQJ3TH+1ZsAp5g psVRG7wsTCnFcNqvHUZPAzJ1VWq3CfviOmmQ4KZuRKVnFca1j23EFO22+qHXYD4pOpKQ mpyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OeLRNKnSJRWwobrAkPzoaUrmD8xwClpaPzu+CpkjnbQ=; b=nuRyne+q6cXDuf/c6WKSAWsopBR4zLtuXkZpXO2LwRzWYFlLhOd3p+0etHo81zzjGB ZWxD/qQFvtvqK2rDZDQ04eh7ENyhMafLA/j7LHDD7+FR3nU0eZFtJqzxpQ7iZ97DLAVb Fv+nrpwZFl58s+PNtJLOBH+3wloojfeBM0h5uOj4c+OKL1iGcE6WHoLrSE8v44y07ZxC i668a7oHHkviDtf4wiNJ151FoymkY/bglDE7g2PKSROC3Hvmrs7Ye6l0HznRq9UGTAdx STkhM/XUK94A/9A3ud1W6RCuaJXmAJ8xCvCL+mKOe/S7ApkJ59hEdQourGxamKWeb3Fj hyTg== X-Gm-Message-State: AOAM532FiNhlxBzTC1Y5VgGih3Fo+/cQ6YckJQGxY6iCM1SBndW+LL+H ZrqswtRo6Kx2Bg/bu9KOzD4V9kEZ9wKY4w== X-Received: by 2002:a63:1e1e:: with SMTP id e30mr6900617pge.149.1624126495676; Sat, 19 Jun 2021 11:14:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/33] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Date: Sat, 19 Jun 2021 11:14:23 -0700 Message-Id: <20210619181452.877683-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is currently unused -- plugins can neither read nor write guest registers. Tested-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-helpers.h | 1 - include/qemu/plugin.h | 1 - accel/tcg/plugin-gen.c | 8 ++++---- plugins/core.c | 30 ++++++------------------------ 4 files changed, 10 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h index 1916ee7920..853bd21677 100644 --- a/accel/tcg/plugin-helpers.h +++ b/accel/tcg/plugin-helpers.h @@ -1,5 +1,4 @@ #ifdef CONFIG_PLUGIN -/* Note: no TCG flags because those are overwritten later */ DEF_HELPER_2(plugin_vcpu_udata_cb, void, i32, ptr) DEF_HELPER_4(plugin_vcpu_mem_cb, void, i32, i32, i64, ptr) #endif diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index c5a79a89f0..0fefbc6084 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -79,7 +79,6 @@ enum plugin_dyn_cb_subtype { struct qemu_plugin_dyn_cb { union qemu_plugin_cb_sig f; void *userp; - unsigned tcg_flags; enum plugin_dyn_cb_subtype type; /* @rw applies to mem callbacks only (both regular and inline) */ enum qemu_plugin_mem_rw rw; diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 48bd2f36f0..88e25c6df9 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -384,7 +384,7 @@ static TCGOp *copy_st_ptr(TCGOp **begin_op, TCGOp *op) } static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func, - void *func, unsigned tcg_flags, int *cb_idx) + void *func, int *cb_idx) { /* copy all ops until the call */ do { @@ -411,7 +411,7 @@ static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func, tcg_debug_assert(i < MAX_OPC_PARAM_ARGS); } op->args[*cb_idx] = (uintptr_t)func; - op->args[*cb_idx + 1] = tcg_flags; + op->args[*cb_idx + 1] = (*begin_op)->args[*cb_idx + 1]; return op; } @@ -438,7 +438,7 @@ static TCGOp *append_udata_cb(const struct qemu_plugin_dyn_cb *cb, /* call */ op = copy_call(&begin_op, op, HELPER(plugin_vcpu_udata_cb), - cb->f.vcpu_udata, cb->tcg_flags, cb_idx); + cb->f.vcpu_udata, cb_idx); return op; } @@ -489,7 +489,7 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb, if (type == PLUGIN_GEN_CB_MEM) { /* call */ op = copy_call(&begin_op, op, HELPER(plugin_vcpu_mem_cb), - cb->f.vcpu_udata, cb->tcg_flags, cb_idx); + cb->f.vcpu_udata, cb_idx); } return op; diff --git a/plugins/core.c b/plugins/core.c index 55d188af51..e1bcdb570d 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -295,33 +295,15 @@ void plugin_register_inline_op(GArray **arr, dyn_cb->inline_insn.imm = imm; } -static inline uint32_t cb_to_tcg_flags(enum qemu_plugin_cb_flags flags) -{ - uint32_t ret; - - switch (flags) { - case QEMU_PLUGIN_CB_RW_REGS: - ret = 0; - break; - case QEMU_PLUGIN_CB_R_REGS: - ret = TCG_CALL_NO_WG; - break; - case QEMU_PLUGIN_CB_NO_REGS: - default: - ret = TCG_CALL_NO_RWG; - } - return ret; -} - -inline void -plugin_register_dyn_cb__udata(GArray **arr, - qemu_plugin_vcpu_udata_cb_t cb, - enum qemu_plugin_cb_flags flags, void *udata) +void plugin_register_dyn_cb__udata(GArray **arr, + qemu_plugin_vcpu_udata_cb_t cb, + enum qemu_plugin_cb_flags flags, + void *udata) { struct qemu_plugin_dyn_cb *dyn_cb = plugin_get_dyn_cb(arr); dyn_cb->userp = udata; - dyn_cb->tcg_flags = cb_to_tcg_flags(flags); + /* Note flags are discarded as unused. */ dyn_cb->f.vcpu_udata = cb; dyn_cb->type = PLUGIN_CB_REGULAR; } @@ -336,7 +318,7 @@ void plugin_register_vcpu_mem_cb(GArray **arr, dyn_cb = plugin_get_dyn_cb(arr); dyn_cb->userp = udata; - dyn_cb->tcg_flags = cb_to_tcg_flags(flags); + /* Note flags are discarded as unused. */ dyn_cb->type = PLUGIN_CB_REGULAR; dyn_cb->rw = rw; dyn_cb->f.generic = cb; From patchwork Sat Jun 19 18:14:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463892 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1047001jao; Sat, 19 Jun 2021 11:18:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7kYsviXThJ1Tl0kaRS2+1kGdSN/EjOErcXuJKRAdAXkFnphkYVMgfriACHfysNaijVpLh X-Received: by 2002:a05:6214:b26:: with SMTP id w6mr11689405qvj.61.1624126710464; Sat, 19 Jun 2021 11:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126710; cv=none; d=google.com; s=arc-20160816; b=BVIbWMv6ntAA2DiSYc32PIEWgDRF7SksVN9OlBHUzGW3FkEPDbJIquo/FG5Weph+CJ 9biJzPpadqhHrWlt2nXxzcMO/LRWlQEKhkRgjLF7fyGRXk0ft2yaz4C+Do9kAt9LSLtP naaPhL8urUd7j247zbU+3fhe0CM8Md57LgnaSl78pBLzf0J6nGWwrEG67uKk6Xt25dRp +DnfItLv366IpyB8vqi/bqMkg3D9DlkhGmjN5TPYhMeQ7BDXw8DxbywfNzBZcMiE0Huu pDQ8EQTPzUWPTtTxyzR0iTZYK0tZonsK0MxrfPInAC+E37F+LOdXOg3w3AOIHuBXZ3+5 HRWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WTAuQeHvP+DitVjZ51FBHL5ba/U3wc92oJ6UKQCTQ5E=; b=0moG/pq+CdC3mF1xiu6CvZplgqyqdkAim6CrFUb/TKcRW0pCtYA8yxBw4MHuq33SLq 8l2gCeIqG1NgoFvVNBmk0EkPC226A+EMcrEjp7hmTR3tE5m38/JF4QinGWPMv9eSldD/ qfneFBslj1d6JNmsT4rFXgp9wK73AOsjsCVFAlu3zepLEGVCKNIU/RdT8QKiiD0kP5pc xZ9lLq3c1oaQZ1Jxk68n0G/Tp+lsf5P1RmRtTTON0/vgNSQlFJk7zRF46KEql2kxA7yj 7k7Qo66P63lOouIzLf3tQ++XIP1IP2/k/mC+cGXjCzFPdTNUH3ut5vfjwnqOV92yBO+R jzbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bwgvALuQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v1si9393456qtq.271.2021.06.19.11.18.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:18:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bwgvALuQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufY5-0006fN-Qr for patch@linaro.org; Sat, 19 Jun 2021 14:18:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUh-0000dB-2m for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:59 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:45632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUf-0002Dn-Cg for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:58 -0400 Received: by mail-pf1-x434.google.com with SMTP id k6so10327933pfk.12 for ; Sat, 19 Jun 2021 11:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WTAuQeHvP+DitVjZ51FBHL5ba/U3wc92oJ6UKQCTQ5E=; b=bwgvALuQkylJ8ueGvgSsUhQPueoNtDOOJ57wgX4ga6V191AUJTRKatqnCgpaWmkfp6 CIMbOeth55Ng26C0FogrT0I8mgH+ETfhtUQG9EA1781sgWzbM8pNH3dmCg/O+Xtsma6i MDAyocTYhyeEWgbxlEpz8yf3NYbQ6o3y4leaS8Xb22ldW3ML0ips1RHk4S2x8Re49JcO ETJgsPK4UnKWQYWoG2ACLXbHoNDaFwLoE+N6E2VlvmdxQ6vIHUMNX83ZMX6nhsEs8SUq 736MCi5GAzdp6yD/ZNbGaO+QsjCLTHmJ/timI29o8OLpEZoogAUOcUteyZP4FHN+ye95 Ua7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WTAuQeHvP+DitVjZ51FBHL5ba/U3wc92oJ6UKQCTQ5E=; b=djnDdD0Pt8en8GQ5V9YanfWMCeEZuDD+3HExfIUCupREYx0t2qyKwdSf809T4joBNR LktG6HwUIkZjgL8MbCDAJS+lnWCuTEvZEA2bZ+v2pzkOk1YxQl515+gRdqeT+E4Zy73m yXWgtKtltaZeM2KpZf9zKxa0n4NUonZfScPOpmegBhwbUENx6eHPShq2B/gy5/cOj0PU 5Ac39yIvzhKskzbCPYYnEfIDoIDUWd12nmK10TSPJrith2yOTvf+95gJ4IdOrJMnxGLh z3Rue4+o5VcXj38KVU/uu+/eegw8auREiVWFHFkX453ASiypE2+k+Hj/xnC/oNxbh8xY vxhQ== X-Gm-Message-State: AOAM5301n9Fiv6hACoqk9VY1bkMLoHjG3cL2RPndXeMg53y90YQZmJsG jzcTh+qW0aB7GQU2IMVuOT1oEIlBmuViCw== X-Received: by 2002:a63:e253:: with SMTP id y19mr15995016pgj.137.1624126496246; Sat, 19 Jun 2021 11:14:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/33] accel/tcg: Add tcg call flags to plugins helpers Date: Sat, 19 Jun 2021 11:14:24 -0700 Message-Id: <20210619181452.877683-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As noted by qemu-plugins.h, plugins can neither read nor write guest registers. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-helpers.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h index 853bd21677..9829abe4a9 100644 --- a/accel/tcg/plugin-helpers.h +++ b/accel/tcg/plugin-helpers.h @@ -1,4 +1,4 @@ #ifdef CONFIG_PLUGIN -DEF_HELPER_2(plugin_vcpu_udata_cb, void, i32, ptr) -DEF_HELPER_4(plugin_vcpu_mem_cb, void, i32, i32, i64, ptr) +DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb, TCG_CALL_NO_RWG, void, i32, ptr) +DEF_HELPER_FLAGS_4(plugin_vcpu_mem_cb, TCG_CALL_NO_RWG, void, i32, i32, i64, ptr) #endif From patchwork Sat Jun 19 18:14:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463895 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1047391jao; Sat, 19 Jun 2021 11:19:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxowlLNXCoGbDnw3dWXeI9P7AZ2cPWKTwZApd2rZwoU39OgCUAGXRWcDaaGzsSMP/U3986y X-Received: by 2002:a37:3c2:: with SMTP id 185mr15212951qkd.140.1624126743670; Sat, 19 Jun 2021 11:19:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126743; cv=none; d=google.com; s=arc-20160816; b=Qj3B7Yi/xPnwariXpSE6LmHJW9Z9NfEY4TxpSKeHm+guYhN1rWiLglfFRm9fvxfM2F Df5FfOtfY0Cc6VXvVDYVEZG6k/c+gQ0ss6ZdWV865cGFTMUMb75OyGCzix9QhxiYVNNS JHLn/Pnu0G9/Kcs1TU0u0EaYoGnrvGuUtggtXwa9+yoTVA36xsXIr/tWa4TIWhCh7F4s D/4qoNxbBJH2278Tdl0TMPXQk6fotygurbBKZyP8uIgQ3agTFYsYarz5Gjh0BbjE8Af9 qfno2AF3M2Snhde3B5iXCJ35NZ+frnbIwHX3cr+3fyJ8ysBZ+eZhMA+mDX8bmcv77g9o w/mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=P6VUODZQuiU48isUCRVC+niQheqohXOPGz/BPO/+Smw=; b=qsFU2ty3M/H5WSiS3ykAPo0+91XRO5H8ub0mv3UrklAK2BYw21/Y3l4+HlRWkSs7mK 5it1owAjcq9gSy52458kOZ2GiHo7RIL/4K1KPmNT5HGy5wzmHPj5y6LJQkVAnD4KQ6Jz bnk8Hifn9nQ0BPR2fxtpssCbUxGqyY3DEhA9uJYflY+lDAcfbKl+JhSAFF+ciNYqvAvU DFo9lVLQVjccxKD8LVLz0KbWRr6CscqVVfZAsOyz4uRGVIYHUvN7FawIzyPF7nNslG5L HDgce/w45mLx1YuUf9yzPGTuE+dIGNUQv3OL1s/8ENTy+2O2yz9sAyiY7E3pCqgsCX9P hmPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yJlNRkW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y4si5595274qtv.331.2021.06.19.11.19.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:19:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yJlNRkW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufYc-0006jU-Uq for patch@linaro.org; Sat, 19 Jun 2021 14:19:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUi-0000eY-11 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:00 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:37520) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUg-0002ES-6j for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:14:59 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 22-20020a17090a0c16b0290164a5354ad0so10053295pjs.2 for ; Sat, 19 Jun 2021 11:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P6VUODZQuiU48isUCRVC+niQheqohXOPGz/BPO/+Smw=; b=yJlNRkW9NUjQJAHqRgWdUAE+KBQ7mTXr89wWLj/3JbD085ywl8FvpprRdAqrpHA6Tp M416lnOr1wHHWTx8j75+JkTkesbv9m1DCRc2du2eAf6TsC+S7XFB2srj5w2zWkscwKYP QSXBCEpcqp78eqDDIp8QxSi1lDydLoLXKOUrgX81IPfsTbcQo/E2sucuSmRH5/iZP0j+ GsXlrMYbNR4cpKDumHt0d2Jq11+CuWPSOMN85mr2LicSj8cirDlz9AD/yG/o3q+y+lc6 1+YjR/wmAgs4bHlevBP1OTd9jmUUnUG/X5D4VW1m24u1DNf5zijXC7lhNB4RowrCeYp4 q5Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P6VUODZQuiU48isUCRVC+niQheqohXOPGz/BPO/+Smw=; b=tDTiZZSfj06+DSqRcbTuLdQXyxhnZE9qJW1vKwMTSp3lIrSS7S6HnmhWptBHk4KtDn bK44ZCoLKFlnMh4w0ZfOhUpWQDRNNBBeCQIFLTi+221aWABV/LmB20VNK5iB/lWx5lZp ArxEJH05HMYg93XHOSxbbJviJwZTRRLRvqXGZ4H2tliXvMNRBl4n0AbwslY1AhPb2t8+ Y0NDGjAhEXQFeLUDP5b7aELWJ/ibvSfZWrXEFouiZ77Vu2f3NHvrEBLs0hs7w4/dyR8c gIVMwedeNurn1i3w8QWH6HLY2QFXlwafOvlhLJ1kd3ef4EFiBo0nkIs5ytVlW+2jlFcV AIKg== X-Gm-Message-State: AOAM5314U/yh3gJ1pdMduhKANjDuDQ9YePeO6D/F+Uj5xKkuge3txhFS CvSVEXxx+1URQGkZ1r18mhEBSvM7k1naag== X-Received: by 2002:a17:90a:8b0d:: with SMTP id y13mr28145254pjn.14.1624126496891; Sat, 19 Jun 2021 11:14:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/33] tcg: Store the TCGHelperInfo in the TCGOp for call Date: Sat, 19 Jun 2021 11:14:25 -0700 Message-Id: <20210619181452.877683-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will give us both flags and typemask for use later. We also fix a dumping bug, wherein calls generated for plugins fail tcg_find_helper and print (null) instead of either a name or the raw function pointer. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 14 ++++++++++++- tcg/tcg.c | 49 ++++++++++++++++++++-------------------------- 2 files changed, 34 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 0796407c13..6ab8910210 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -27,6 +27,13 @@ #define TCG_HIGHWATER 1024 +typedef struct TCGHelperInfo { + void *func; + const char *name; + unsigned flags; + unsigned typemask; +} TCGHelperInfo; + extern TCGContext tcg_init_ctx; extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; @@ -37,9 +44,14 @@ bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); void tcg_region_prologue_set(TCGContext *s); +static inline const TCGHelperInfo *tcg_call_info(TCGOp *op) +{ + return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; +} + static inline unsigned tcg_call_flags(TCGOp *op) { - return op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; + return tcg_call_info(op)->flags; } #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 51c1f61828..0dc99cc65b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -532,13 +532,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current = NULL; } -typedef struct TCGHelperInfo { - void *func; - const char *name; - unsigned flags; - unsigned typemask; -} TCGHelperInfo; - #include "exec/helper-proto.h" static const TCGHelperInfo all_helpers[] = { @@ -1395,12 +1388,11 @@ bool tcg_op_supported(TCGOpcode op) void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) { int i, real_args, nb_rets, pi; - unsigned typemask, flags; - TCGHelperInfo *info; + unsigned typemask; + const TCGHelperInfo *info; TCGOp *op; info = g_hash_table_lookup(helper_table, (gpointer)func); - flags = info->flags; typemask = info->typemask; #ifdef CONFIG_PLUGIN @@ -1538,7 +1530,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args++; } op->args[pi++] = (uintptr_t)func; - op->args[pi++] = flags; + op->args[pi++] = (uintptr_t)info; TCGOP_CALLI(op) = real_args; /* Make sure the fields didn't overflow. */ @@ -1657,19 +1649,6 @@ static char *tcg_get_arg_str(TCGContext *s, char *buf, return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); } -/* Find helper name. */ -static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) -{ - const char *ret = NULL; - if (helper_table) { - TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val); - if (info) { - ret = info->name; - } - } - return ret; -} - static const char * const cond_name[] = { [TCG_COND_NEVER] = "never", @@ -1760,15 +1739,29 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) col += qemu_log(" " TARGET_FMT_lx, a); } } else if (c == INDEX_op_call) { + const TCGHelperInfo *info = tcg_call_info(op); + void *func; + /* variable number of arguments */ nb_oargs = TCGOP_CALLO(op); nb_iargs = TCGOP_CALLI(op); nb_cargs = def->nb_cargs; - /* function name, flags, out args */ - col += qemu_log(" %s %s,$0x%x,$%d", def->name, - tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), - tcg_call_flags(op), nb_oargs); + col += qemu_log(" %s ", def->name); + + /* + * Print the function name from TCGHelperInfo, if available. + * Note that plugins have a template function for the info, + * but the actual function pointer comes from the plugin. + */ + func = (void *)(uintptr_t)op->args[nb_oargs + nb_iargs]; + if (func == info->func) { + col += qemu_log("%s", info->name); + } else { + col += qemu_log("plugin(%p)", func); + } + + col += qemu_log("$0x%x,$%d", info->flags, nb_oargs); for (i = 0; i < nb_oargs; i++) { col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), op->args[i])); From patchwork Sat Jun 19 18:14:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463890 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1045429jao; Sat, 19 Jun 2021 11:15:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxuEsRVfbU+4GhTLJW2u2+3f/miHkN231b4BJdauRiTZ1Ts8Zfo8uvWu6Uh/5BjBPjGcH6q X-Received: by 2002:ab0:140e:: with SMTP id b14mr17075521uae.94.1624126548058; Sat, 19 Jun 2021 11:15:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126548; cv=none; d=google.com; s=arc-20160816; b=vj1ASulg5xnr0ZSltAFkr5aOr2Asdm5nmJUb22cLAmL7jIoQyIflGoWKvueog17KpB K1+EKfkaveq09PXswfCHcEBP0yWxDDBhIqdpmtw3lXVFp5/idgfnR2FypNONnvVsb+Xf JhDrch+HIAPtyw8MQiA3U3//P+cbw+kPYneOga/n9RFUxwf6oTDsIUKRpUP/+U31iU0f bJiG0N8dcDGyA3cRS6hQ0nh4rScpCQ2xAatJ7a+TnzMy8vy7OfPktYZdUDM4X7jfvipg fEwD5Tax8o3awD9kam8elD3aDGRvyjuIvY7cjBlljOOLMj58yagWIh1A6kxAU8qyVtB1 MKrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M6WR/q/XMRsg+9/4YpwLpIga2lF+a4ZN740h5QwBqxQ=; b=pb/OO3eaRIskND6b1ypLO9DFvtmncpUJIvBPI7BPHJfe5UfO9j8u6QqPETHtToLYro WHLvmhjbDneMpOY+pHvmt66l3id5XuUjoYW5fshtmDL3k0LFVNrLyvvzOnhIUc/gm5Wd UUdilvc75AO8PINmlMkuuVNmvEsFYsmYHwdHR91TVW+yjkSBwNWHTru3hWZuGVw0urJw bfdvh0U2MZeqz+FAv9bwTKDtBZOqrXA1WMT/x0xMoF2v4Y9zh4JW1sYctwQf7JTaJ+Fs qRolHOzHZZ7Y+EgjgNjfG5X/qQas+VPVdNPnLIRpplGkbTuHd9szfv9wr4x2Cp8CYb+C TNKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aMXVnWd5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s23si8188709vsn.284.2021.06.19.11.15.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:15:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aMXVnWd5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufVT-0000hC-B8 for patch@linaro.org; Sat, 19 Jun 2021 14:15:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUi-0000fP-Bm for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:00 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:37795) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUg-0002Eb-N6 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:00 -0400 Received: by mail-pf1-x430.google.com with SMTP id w71so334886pfd.4 for ; Sat, 19 Jun 2021 11:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M6WR/q/XMRsg+9/4YpwLpIga2lF+a4ZN740h5QwBqxQ=; b=aMXVnWd56iSrYam62Ts1D8MZVDqvi51XYiGcbsMMZja+05Q6/MPHkPC08/kYQIrCRh LOn17q9UTq5KTCykPty9lH0bZjqcbLSDvKX7W1zw0G4hXeOB5IUBBeEy1avdXIVxNCvp c4JXWtQVcR87NOioYr7qVIxSu9BuCzB1ieclHuGGPWX/zETqlynuNNP0s09Hw+FHoKBm JTxNqCv0HT0H1xFQHAv1Rcm7Yup8ovN3A7G+sN+WstDT9hmesb7jHi/hdwSIwQzlGT8Z JK0gEHA+edFn1mYCfqlr5AF1VPT5VMP5iFb55jQDrN3UcXLhiz19Z8NhkmW8suM+XB/q jc3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M6WR/q/XMRsg+9/4YpwLpIga2lF+a4ZN740h5QwBqxQ=; b=a6Exac0j7kc+Q11/6ZNqNL2/dOYhmHEfzwgCV5k3HQ3TR8ynbTxZk+WGrqrs5WbPWf tGoGMEd0yb1wTnms8XExnPdAkR0gkeYxH/9O1F8BCA+aTimo9WSY51YpPFFq8tbnHAD0 yAOUMG7sZQ6qmK/COeXPAvEEnB8cxPkPgiCmfwiqxsZaTkTUylTiWaMjHtArmuy2KLQv RCybMi85RPtWIfNfUCNPKerPYHJnNHWgGq4Qbu0iw+X2KmJzzKgqYSr3nCJ0aAZzES8D b5vmXMHLatQf2tzrDYTsYPUn0HKQL25ECAF2a9OOLuRXj6+jpAe6H9D+B/nYFYMXw4lH y0fA== X-Gm-Message-State: AOAM531BpThFOGPCEcscdZRzVeG8+DtfRnaqOvduxO2IMu82rER+s+XK jS8tC2CXD1Np1Ww9d/RcgOTzMgd69mEbaQ== X-Received: by 2002:a63:d409:: with SMTP id a9mr16044437pgh.304.1624126497342; Sat, 19 Jun 2021 11:14:57 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/33] tcg: Add tcg_call_func Date: Sat, 19 Jun 2021 11:14:26 -0700 Message-Id: <20210619181452.877683-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 5 +++++ tcg/tcg.c | 5 ++--- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 6ab8910210..92c91dcde9 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -44,6 +44,11 @@ bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); void tcg_region_prologue_set(TCGContext *s); +static inline void *tcg_call_func(TCGOp *op) +{ + return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op)]; +} + static inline const TCGHelperInfo *tcg_call_info(TCGOp *op) { return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; diff --git a/tcg/tcg.c b/tcg/tcg.c index 0dc99cc65b..8f4f1711cd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1740,7 +1740,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) } } else if (c == INDEX_op_call) { const TCGHelperInfo *info = tcg_call_info(op); - void *func; + void *func = tcg_call_func(op); /* variable number of arguments */ nb_oargs = TCGOP_CALLO(op); @@ -1754,7 +1754,6 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) * Note that plugins have a template function for the info, * but the actual function pointer comes from the plugin. */ - func = (void *)(uintptr_t)op->args[nb_oargs + nb_iargs]; if (func == info->func) { col += qemu_log("%s", info->name); } else { @@ -3789,7 +3788,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) int allocate_args; TCGRegSet allocated_regs; - func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; + func_addr = tcg_call_func(op); flags = tcg_call_flags(op); nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); From patchwork Sat Jun 19 18:14:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463896 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1048224jao; Sat, 19 Jun 2021 11:20:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx65dtgiNuI5PDFKnwzVyg/CYcV2sX6fQgoYAA7zvR1CGQAFOVEPD+0SrhXZCoRwr9fAQTt X-Received: by 2002:a67:80c5:: with SMTP id b188mr12179994vsd.49.1624126839843; Sat, 19 Jun 2021 11:20:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126839; cv=none; d=google.com; s=arc-20160816; b=C0OQyz+VBfBNh5MdOyMWp7EzLO0cEuCotAszcFxnhllwQqftuvYXa8PniAUE2ALv/B x0w02O72ot/R1xbbkf7GH/qIiwDcPJJxwbexMP5er9aABXTJf1gSVbkcoUp1o/+AAfZG kAZBjxvBJmTl1zEFPs7J278S2ienZcyl2kQAqU4QZWV2mKejq7dXtr1h7NKDHTFYp2K2 F5LK8QQczj9a7HII/sNXYYfYQMLhZTmwD4iOGu5VfIdST65lDDOBcD9yXOmGYl2fuqFE 7qP0p0lHsf41RIY4QyBv13PktSfCPPbOZmR3iq1r/DVmTB/TZNdSWBcwOEQ1zBMCc3Qq dNQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GYoI4UBf5tUFjOCHxxgodMxhDrVCT55EmnBgp0S5rzE=; b=UuGiBzool029y40SRSfZS6/Ob3AddsEuDKvGl3GL4ahoFYrbHhjG8bO4eARXPI4RcI YYvfouK2cMqA8b+OYaWyvxpr7rmEW+HYR+HFdyfoqOU0Q5PDhZAfCOMLRF6OzPaoVh24 /4oGmXulQY+/AQXQMRAqJaL2zkPznQj+b6dP8UCQxRnD88lu3BCy5/tXhFo1KEd8V3s2 s/x7K826wKSmoMOcIl89UIR6wTPHXv3UxaOVla5qw5gBJhfs88TmTkjRYK4Bg3cEq7OA Se0SpdJ3jHjfqTGeSj9DWVDS9zz7z7NQjr6QPSP3mWLwfjEd0TYDj1pl+3zksfLGkef3 Tiyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K2VlTU99; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 90si10250695uam.157.2021.06.19.11.20.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:20:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K2VlTU99; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufaB-00043z-7F for patch@linaro.org; Sat, 19 Jun 2021 14:20:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUj-0000hS-D3 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:01 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:38654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUh-0002Eq-9q for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:01 -0400 Received: by mail-pl1-x635.google.com with SMTP id 69so6334630plc.5 for ; Sat, 19 Jun 2021 11:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GYoI4UBf5tUFjOCHxxgodMxhDrVCT55EmnBgp0S5rzE=; b=K2VlTU99K+nnNxnkfDuZ2Qz9BDLiIzztYqCJVeOkh4Q3+0v3n4dZhXNKnafYJczg/M UKk2zbOA3sX0UjQz2FxZtocKgFmzSjJgmuuS5UjwZHM6P/0o8c28CwSa+ZvmzORQ/Lvw rOXqFQlcDP2sj7wYVFby7BAWR13/pNBrG/ze8iPk/ijeE5nNRo27e7x71+cRwnP7vSp/ Wc5Q6h+5UBIV85lhdoTo0xFtn1Vdx9nfHr1DNjPmtufOF+sbCRbn67dpAUA1ULQw2aBp fJrhLfGOmnmK+Xe1AAk6ZBlSC0aOVMrvrHeAvc31GPq24LJ8B1BOllYWpDcgj+74RXTX 0bKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GYoI4UBf5tUFjOCHxxgodMxhDrVCT55EmnBgp0S5rzE=; b=KOKlbM23cJOqjE6POHuBqZ4MS3bXrOvKj8C+Y122yMlgIM/m+rwZD5dQk9aeisLKM8 pBC70KlJ//IixBHP9uH/CACNxEd2uumEI2jqzUgScgst/fOQ6lAiMfwPPk0VRu6q8Klk WIsMFaN5XpubIMBpbQ5Ltpr5+ZxqJQAhf8mXsqStpBZrrC2nwClluVaRHWcQLZUtrZi5 CxZ/oIqRUAZN/45Jk3rz55gy32LASLO+QBRH60gvEolQN3rxIp85RdoleptntRoM1gev vmtATQ5lbBEd94DHYCAqO/fR7c+4aQKbmq3M95WHeqsO75rIevNlT+O/3ZzSA36A/RVg znMA== X-Gm-Message-State: AOAM530xNp92I/L922jXRMq0uwqDxVLiGgoFGMNhnsB3U+TZantfZmme 594wVcyy86rG+zz2uT85VI3owI25AdqJWQ== X-Received: by 2002:a17:90a:f094:: with SMTP id cn20mr17779008pjb.157.1624126497869; Sat, 19 Jun 2021 11:14:57 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/33] tcg: Build ffi data structures for helpers Date: Sat, 19 Jun 2021 11:14:27 -0700 Message-Id: <20210619181452.877683-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add libffi as a build requirement for TCI. Add libffi to the dockerfiles to satisfy that requirement. Construct an ffi_cif structure for each unique typemask. Record the result in a separate hash table for later lookup; this allows helper_table to stay const. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 58 +++++++++++++++++++ tcg/meson.build | 8 ++- tests/docker/dockerfiles/alpine.docker | 1 + tests/docker/dockerfiles/centos8.docker | 1 + tests/docker/dockerfiles/debian10.docker | 1 + .../dockerfiles/fedora-i386-cross.docker | 1 + .../dockerfiles/fedora-win32-cross.docker | 1 + .../dockerfiles/fedora-win64-cross.docker | 1 + tests/docker/dockerfiles/fedora.docker | 1 + tests/docker/dockerfiles/ubuntu.docker | 1 + tests/docker/dockerfiles/ubuntu1804.docker | 1 + tests/docker/dockerfiles/ubuntu2004.docker | 1 + 12 files changed, 75 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 8f4f1711cd..de1a593ce7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -60,6 +60,10 @@ #include "exec/log.h" #include "tcg-internal.h" +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); @@ -539,6 +543,19 @@ static const TCGHelperInfo all_helpers[] = { }; static GHashTable *helper_table; +#ifdef CONFIG_TCG_INTERPRETER +static GHashTable *ffi_table; + +static ffi_type * const typecode_to_ffi[8] = { + [dh_typecode_void] = &ffi_type_void, + [dh_typecode_i32] = &ffi_type_uint32, + [dh_typecode_s32] = &ffi_type_sint32, + [dh_typecode_i64] = &ffi_type_uint64, + [dh_typecode_s64] = &ffi_type_sint64, + [dh_typecode_ptr] = &ffi_type_pointer, +}; +#endif + static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; static void process_op_defs(TCGContext *s); static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, @@ -582,6 +599,47 @@ static void tcg_context_init(unsigned max_cpus) (gpointer)&all_helpers[i]); } +#ifdef CONFIG_TCG_INTERPRETER + /* g_direct_hash/equal for direct comparisons on uint32_t. */ + ffi_table = g_hash_table_new(NULL, NULL); + for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { + struct { + ffi_cif cif; + ffi_type *args[]; + } *ca; + uint32_t typemask = all_helpers[i].typemask; + gpointer hash = (gpointer)(uintptr_t)typemask; + ffi_status status; + int nargs; + + if (g_hash_table_lookup(ffi_table, hash)) { + continue; + } + + /* Ignoring the return type, find the last non-zero field. */ + nargs = 32 - clz32(typemask >> 3); + nargs = DIV_ROUND_UP(nargs, 3); + + ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); + ca->cif.rtype = typecode_to_ffi[typemask & 7]; + ca->cif.nargs = nargs; + + if (nargs != 0) { + ca->cif.arg_types = ca->args; + for (i = 0; i < nargs; ++i) { + int typecode = extract32(typemask, (i + 1) * 3, 3); + ca->args[i] = typecode_to_ffi[typecode]; + } + } + + status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, + ca->cif.rtype, ca->cif.arg_types); + assert(status == FFI_OK); + + g_hash_table_insert(ffi_table, hash, (gpointer)&ca->cif); + } +#endif + tcg_target_init(s); process_op_defs(s); diff --git a/tcg/meson.build b/tcg/meson.build index 5be3915529..c4c63b19d4 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -9,6 +9,12 @@ tcg_ss.add(files( 'tcg-op-gvec.c', 'tcg-op-vec.c', )) -tcg_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tci.c')) + +if get_option('tcg_interpreter') + libffi = dependency('libffi', version: '>=3.0', required: true, + method: 'pkg-config', kwargs: static_kwargs) + specific_ss.add(libffi) + specific_ss.add(files('tci.c')) +endif specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) diff --git a/tests/docker/dockerfiles/alpine.docker b/tests/docker/dockerfiles/alpine.docker index 7eeecacc46..7e6997e301 100644 --- a/tests/docker/dockerfiles/alpine.docker +++ b/tests/docker/dockerfiles/alpine.docker @@ -22,6 +22,7 @@ ENV PACKAGES \ libaio-dev \ libbpf-dev \ libcap-ng-dev \ + libffi-dev \ libjpeg-turbo-dev \ libnfs-dev \ libpng-dev \ diff --git a/tests/docker/dockerfiles/centos8.docker b/tests/docker/dockerfiles/centos8.docker index efc1349cc8..03e0440e03 100644 --- a/tests/docker/dockerfiles/centos8.docker +++ b/tests/docker/dockerfiles/centos8.docker @@ -17,6 +17,7 @@ ENV PACKAGES \ libbpf-devel \ libepoxy-devel \ libfdt-devel \ + libffi-devel \ libgcrypt-devel \ lzo-devel \ make \ diff --git a/tests/docker/dockerfiles/debian10.docker b/tests/docker/dockerfiles/debian10.docker index 63cf835ec5..4ffe47671e 100644 --- a/tests/docker/dockerfiles/debian10.docker +++ b/tests/docker/dockerfiles/debian10.docker @@ -26,6 +26,7 @@ RUN apt update && \ gdb-multiarch \ gettext \ git \ + libffi-dev \ libncurses5-dev \ ninja-build \ pkg-config \ diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker index 66cdb06c19..8004fd8ee5 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -6,6 +6,7 @@ ENV PACKAGES \ findutils \ gcc \ git \ + libffi-devel.i686 \ libtasn1-devel.i686 \ libzstd-devel.i686 \ make \ diff --git a/tests/docker/dockerfiles/fedora-win32-cross.docker b/tests/docker/dockerfiles/fedora-win32-cross.docker index 3733df63e9..a638afb525 100644 --- a/tests/docker/dockerfiles/fedora-win32-cross.docker +++ b/tests/docker/dockerfiles/fedora-win32-cross.docker @@ -19,6 +19,7 @@ ENV PACKAGES \ mingw32-gmp \ mingw32-gnutls \ mingw32-gtk3 \ + mingw32-libffi \ mingw32-libjpeg-turbo \ mingw32-libpng \ mingw32-libtasn1 \ diff --git a/tests/docker/dockerfiles/fedora-win64-cross.docker b/tests/docker/dockerfiles/fedora-win64-cross.docker index 2564ce4979..f53007ac86 100644 --- a/tests/docker/dockerfiles/fedora-win64-cross.docker +++ b/tests/docker/dockerfiles/fedora-win64-cross.docker @@ -18,6 +18,7 @@ ENV PACKAGES \ mingw64-glib2 \ mingw64-gmp \ mingw64-gtk3 \ + mingw64-libffi \ mingw64-libjpeg-turbo \ mingw64-libpng \ mingw64-libtasn1 \ diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 0979c0e1f4..00cac5d61c 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -33,6 +33,7 @@ ENV PACKAGES \ libepoxy-devel \ libfdt-devel \ libbpf-devel \ + libffi-devel \ libiscsi-devel \ libjpeg-devel \ libpmem-devel \ diff --git a/tests/docker/dockerfiles/ubuntu.docker b/tests/docker/dockerfiles/ubuntu.docker index 98a527361c..24d1647a65 100644 --- a/tests/docker/dockerfiles/ubuntu.docker +++ b/tests/docker/dockerfiles/ubuntu.docker @@ -28,6 +28,7 @@ ENV PACKAGES \ libdrm-dev \ libepoxy-dev \ libfdt-dev \ + libffi-dev \ libgbm-dev \ libgnutls28-dev \ libgtk-3-dev \ diff --git a/tests/docker/dockerfiles/ubuntu1804.docker b/tests/docker/dockerfiles/ubuntu1804.docker index c0d3642507..2f1ec7c42b 100644 --- a/tests/docker/dockerfiles/ubuntu1804.docker +++ b/tests/docker/dockerfiles/ubuntu1804.docker @@ -16,6 +16,7 @@ ENV PACKAGES \ libdrm-dev \ libepoxy-dev \ libfdt-dev \ + libffi-dev \ libgbm-dev \ libgtk-3-dev \ libibverbs-dev \ diff --git a/tests/docker/dockerfiles/ubuntu2004.docker b/tests/docker/dockerfiles/ubuntu2004.docker index f1e0ebad49..fe993fe2a3 100644 --- a/tests/docker/dockerfiles/ubuntu2004.docker +++ b/tests/docker/dockerfiles/ubuntu2004.docker @@ -19,6 +19,7 @@ ENV PACKAGES flex bison \ libdrm-dev \ libepoxy-dev \ libfdt-dev \ + libffi-dev \ libgbm-dev \ libgtk-3-dev \ libibverbs-dev \ From patchwork Sat Jun 19 18:14:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463902 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1049942jao; Sat, 19 Jun 2021 11:24:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuGuJDSB1KqDZ2+0QCS4slstV1U7+12pF2dMK0YR+so8EeK1ne5t2S/9g5UwmG/HxXP746 X-Received: by 2002:a37:b17:: with SMTP id 23mr15445179qkl.60.1624127049490; Sat, 19 Jun 2021 11:24:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127049; cv=none; d=google.com; s=arc-20160816; b=epCC+VBRlDI7w2gE9lxLdD/M+1SdZith/Eq0DNUDNkiwIzTkJaSaKBzgevqgML6Hru SIV7an+MhZzN1bLe7UHvg9gRcSGwcviAm4N8X27H3loqLYIyTBt2LCb/79iJ1Y32UbHP oI4uEnVF2uDUzUB5RCRFXZi2W1fIvQ+krDjH6goy6qghtaFJYAYeuRQCwYjcZ3T1QIFu kb1WcW47IouP+lH0OrCfUgcDl3xgj3RMTE5viNizvEM5HxBOXOWsdRx8kYaiVM+50pdi nLtbCF6MP75GS4yLfV5VbflXoxIVYlURQarIwNYO0Sgpo0tUaUWG66E4OIRXxH4C+6uv TusQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vC/L18edcuCe8FZFGeMjtTSdBtjX4uN3kFKzp4cnVKo=; b=YkpJ36aiRqhkNRDTnWCOYOAgumecyA31wguvJX9UeFNDEtWq2AidC3g1O/CrprYaBj gCB8RsE4E0gOqZKpw5GKyvc0l2JVj86k6l+kCn9lfzeX3tydWye5M4nd0+HENJH/BFD0 dP2P8OhthTZMj2oQgPMCFBzmXwg6KrjS2niTl8hVcfRfgPSlalqZpEC8darHIkihurc7 g9K8W3rviPLvO9Wa3s5P/WGPMAnWESkgwLFFgdE6ocBydLuRMKL9bBxW7cDeiEQ83VV2 Dm5arxnbQwxMhUeEtdw6PuYfxMSujxa6nDZPJaVa0CwKnprH/BcUq9dFS2DbrnRWvBO7 K+lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NpcmAhth; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d18si6319743qvs.197.2021.06.19.11.24.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:24:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NpcmAhth; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufdY-0001O1-O1 for patch@linaro.org; Sat, 19 Jun 2021 14:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUm-0000ls-6F for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:04 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:46847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUh-0002Fd-Q2 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:03 -0400 Received: by mail-pf1-x429.google.com with SMTP id x16so10323888pfa.13 for ; Sat, 19 Jun 2021 11:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vC/L18edcuCe8FZFGeMjtTSdBtjX4uN3kFKzp4cnVKo=; b=NpcmAhthp5Daas6jXrcETc/yk4/7uyz+K0DRRYtXghovRVi7vC0/LorACo1kNEGmhJ Dr+8G5N5NFPdMEyPxDxQp/91PlPziiHhE+4OP186qfY8625SdWbhciW6EfYcjR+UuX8s n1Zn3XCidcC1Po4U6HKI8qHYA4VlbjF5Aw5OpKAnZP35lzdR+Akr2CKvJA+b5sm0O1Jy fIZ2p+fVD7le767l/1nJtAIuLIrj5UKGkJeDB2LcSeYZ/vi3hS5hdPcQfsnB2R4tQ7LA bSAY1lU44RhTHlROPy0tAV8v6Cn2clHMi5juJSH00zLys9KbVx8r95PQlvmIxok0EUuY gbYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vC/L18edcuCe8FZFGeMjtTSdBtjX4uN3kFKzp4cnVKo=; b=M6C9RhbHqU9/9I5edc44UgUc21pCPJCk3uEsinH4qKX3KzwzZ79aBytXG2hV6trDJN KiA7w97uq+Bx/IVr+CBIZ62BFJxuPTKVkbndjMl2vn38/y5SPqsqCa2abbAySHzjMZ1l 7FUGKWGe7nSOc32z6IVO6BfuDyFfsjYCVPS7o9EHPeZLCixnMmUNRhH8moVnwFIryhhJ 2v6/yAgKizzX858REp454V6vFq/z2Td8LA7KA5JuxvNzYIjL0R8s6CPzWHKPk+OVzGnW iTDKBXJuwjQkVrTb0QFMkXUyHTt+DJdVibHTDpq/gVyWbROeW9WzfgP71+Ni+gyk6Sw4 XwTA== X-Gm-Message-State: AOAM532EOyZEYJGHwC7iHVO9BV8VtBlIOU4tAhcmBGEgXs7Pt/HJorwT PYbrK90Ldy5KgLBMnK2s03gILply6tgITA== X-Received: by 2002:a65:4c46:: with SMTP id l6mr16030341pgr.91.1624126498579; Sat, 19 Jun 2021 11:14:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/33] tcg/tci: Improve tcg_target_call_clobber_regs Date: Sat, 19 Jun 2021 11:14:28 -0700 Message-Id: <20210619181452.877683-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The current setting is much too pessimistic. Indicating only the one or two registers that are actually assigned after a call should avoid unnecessary movement between the register array and the stack array. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 823ecd5d35..8f3f9ef7d3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -810,8 +810,14 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; /* Registers available for 64 bit operations. */ tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; - /* TODO: Which registers should be set here? */ - tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; + /* + * The interpreter "registers" are in the local stack frame and + * cannot be clobbered by the called helper functions. However, + * the interpreter assumes a 64-bit return value and assigns to + * the return value registers. + */ + tcg_target_call_clobber_regs = + MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); From patchwork Sat Jun 19 18:14:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463903 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1049994jao; Sat, 19 Jun 2021 11:24:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFwzDVordNeUirZyNN+WcHlB8VV9Yq2W967n629R6EoG6DSenPimPue1jG4WAdnrZ48TJ0 X-Received: by 2002:a05:622a:1a96:: with SMTP id s22mr15608010qtc.229.1624127055845; Sat, 19 Jun 2021 11:24:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127055; cv=none; d=google.com; s=arc-20160816; b=WsPCuNO795Jj9l9JUzNih782u7ip6clG4DYI4P4A3fR6Sj231z573Z9TplCtawC9SL G0KZwHemOpx1ms8S4e4YQ/VM0IVE7xIG5J2N3qXdgDDslWcmNw8QmVucLOdMfxwVYaZN Iq7kiafWYynREbODxdC4D2whPE7g3UZGO90LTgxmq55sWOKoKGXuC7cCBqg2GPwZ72id GIHi/k82z07Tl8pl8hlgUYafPKyHywmzsbgKejF3YxJg3piFYPcuu80NTn0FCcU/kQA6 MTYBcWc4ggy+4Nibu05JGT8slC/GDNQOgIS6tdjr40klM+lJDnzoVanwZmDnF4biuzuq JJ8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6t5cjIM/Jta9nl2/Scc7LjVmb2HvXKv6yCUdQdTGseM=; b=YVvEsfZ0ZQUbkxoE1fif4+c/OaojX+SL1fej1OIIGlwJ6A+6H88NCtaH2GynmPOEbr fnWHdib+MJi0vePCr0DU5muf7Qq+GEqVn5bHLUsJok0Yw9dqdZgyrYg97p7opoRUoSDm WRwMycjciAiwPMaiRozSkPCvyz2sdabHy4V5C4Qc/XLYACP4BmDOE7Bwgt4ZvFeyfeji Z7+DIcEii3cKtr+ASfiKVlA1iGPGYc2AejGACePKEIws1zBuUtGl0OPuQr//FTgLgikh MOCqOYjf0ZfGZ6gTNNjnH3IGifAq0gQF0iFGvXUgh5st7To4H5lUiGf8OO/5njXoLFu7 ixQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ddS4CFsl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x15si7179083qkn.310.2021.06.19.11.24.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:24:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ddS4CFsl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufdf-0003K2-64 for patch@linaro.org; Sat, 19 Jun 2021 14:24:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUj-0000j9-QB for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:02 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:51712) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUi-0002GK-6a for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:01 -0400 Received: by mail-pj1-x102d.google.com with SMTP id k5so7550071pjj.1 for ; Sat, 19 Jun 2021 11:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6t5cjIM/Jta9nl2/Scc7LjVmb2HvXKv6yCUdQdTGseM=; b=ddS4CFsly/DYmYNV+uZx6dgnVKuB1yIG89i0fXhpLAdCqMXGEuzJNx7WoyP2aliF57 uH+mWB4tfXRCRZFNhaOBECV7EljrxxNaOdqo1O5cvGV/BoGGs6PgEonfSZkzx25FjVpF o9v6IY1mc2B6zTDKzK1sbdsMqS7SIKvR88dT+y6FL77A8O4mhQrIoB0zkZF7ETfnUnqL Y+j2TGAMGafKIZumerdHD59g8ABh7XdQu6kw+Exndgs5v/b8cc5HpE3in8ZEjhO9MEca bTzXUAMDi8q9jOgoscDbMUtO9i48kNu/btpNTtfkXIchhOzVU9f/eL7pwHmNRzfPERo2 NiRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6t5cjIM/Jta9nl2/Scc7LjVmb2HvXKv6yCUdQdTGseM=; b=MCNbxyd83NHeCJ+WiF8/AWYW5ivFCct/oHMKeE0EZwjgL1u+PkCugTcO2QtoLofat7 f21jk1lIxLVhLwrDzfQTrBB7hJG/Yr4G18Xt6f1NzVG1W/Ls3Fo/5AOGLt9cDNY2BGxh iDFD/sonznhLxXFiGOW5YRlwhJeG5R5sYS5N+VP9i/zIDZYDTCreFieTizb5IscK6lwT K5fzOE6ffVU9uCSqaw0OjxpdEBupKEOFsdwC8eydvtktKc7qiYH5u7aCgDEm7abODf2C v/2gdA1PVy5GcqN876hn+rDY4WKJBv3LQzF4vJpOxZgmTBQ5id8jFsTIMJh/TFAg4Icq IgtA== X-Gm-Message-State: AOAM531GXsrnp0j6XZKXiC8wMxtgUODlva53neC/YzJWHUVUNIZVDkVL zOUSUKwEK90ge65Vuf+3Zq7R3OcuaoN/LA== X-Received: by 2002:a17:90a:3d47:: with SMTP id o7mr28864733pjf.68.1624126499110; Sat, 19 Jun 2021 11:14:59 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/33] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Date: Sat, 19 Jun 2021 11:14:29 -0700 Message-Id: <20210619181452.877683-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the only call-clobbered regs for TCI, these should receive the least priority. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8f3f9ef7d3..d54c01b9de 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) } static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, @@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R1, + TCG_REG_R0, }; #if MAX_OPC_PARAM_IARGS != 6 From patchwork Sat Jun 19 18:14:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463893 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1047005jao; Sat, 19 Jun 2021 11:18:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx1mgSjGHSW7ihrSvqFgPUh6/w9pT16V7eVezidniVQvclFh2hv4QcQpl1yc2PL5pPOclJP X-Received: by 2002:ad4:4772:: with SMTP id d18mr11744659qvx.35.1624126710696; Sat, 19 Jun 2021 11:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126710; cv=none; d=google.com; s=arc-20160816; b=HbzGew2fBERF+7tvwVxyjGo07waII6aVD1iTJ43F7RU4BcU1QxFcTN5PO3f850uMLA gLlKETOY2RyisaJSKYPcCEv6nKORRRBqINrtZsfyYh6n2Hilxz9WyANvvEQhY0lj9vK6 8ZodPSVszIBrD7d359j1erp0OYJ/iUNdtzz2lL643MsB2VpnBAfxN6OEmvLSDO6dbVEa HX9oGAbLXUVx0koXalJtX4l8cDWY5nNToNVD+TOCp58NkCh1BsLq16tvTxsZxORrtHmS Tvfp4/ilGTWbsS0NLBCqVIp2ghlerhsRKKY1GbqU4gQMr/UEKqNM0NDWSPTEauDOPxH5 8GUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=enag5t9ucLqzxU+wgX9ngItIHENTMN1ScQ87ee6B1uY=; b=yK55tKb+mKs2iO2jYZ+r6qOHujm9791qTd39MJ9X3/WCWco4ILpAUwLRPFT2Jk2zqS FmLi8I4mSfLCBy0L2NKJjXQnCWRHUyVgBdIg9mIe3cNOPKv8FTAnOgcXdWKsvcDTXbQt L9sMyiuxWPKMU1lu+IhZVYYzNbv4tPZRvzKyBjbFzJbmsB6k3QkpiGxFnfybvfuJxRWc hEOEmTOUasls7UOfE8UZUjOMnIXgrDysykJRNUFnbANyzBDiMCn9SI9fdabxbc2oNvsd 3W0MKOpFEOgpw0H0kfrGvLzk9GmvVyPwOAupSt5/8GhU3j2+ifjExGzlhQriunf4AaOX kKNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MnSM+TuF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t4si7274456qkf.214.2021.06.19.11.18.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:18:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MnSM+TuF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufY6-0006gX-0c for patch@linaro.org; Sat, 19 Jun 2021 14:18:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUm-0000nS-UC for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:05 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:42935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUj-0002H9-3K for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:04 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 13-20020a17090a08cdb029016eed209ca4so7788166pjn.1 for ; Sat, 19 Jun 2021 11:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=enag5t9ucLqzxU+wgX9ngItIHENTMN1ScQ87ee6B1uY=; b=MnSM+TuFngCLx/H8lP1H31sOo8KLoJNfKQRgNcFwpWUhhukIKqCi3IxjQ2lolOmiB+ 9aDiQ/cHrPywgnf+iyJjClf/SK2aq5QkQUIESzoMYiZDD5zOaibKCHiOlGyV+O+obLvx Xzz53xH84pBMFtWBrh/LWJGoy9cV19m9TObP9RgST6ktRlBJcz4wEuRbXPeKbVqMFrV3 u3EiwPx6bJDYYXOKvusgf0qm16OSjC8QZUfyjkk61AXq6X4M2E09P4htVZ2lRpqKAmdO PmynpTcallO6iOvdJbdJrNA8km7KSz2aT8q75BbIGz0uhygo5mhzHRM4S/j/2kFCyd9F /oFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=enag5t9ucLqzxU+wgX9ngItIHENTMN1ScQ87ee6B1uY=; b=Cw/LkmUtV2a3CJMzqByjqYw1m8FZV8/Cn0VLe4PVNXno43ljSrRHfWRvXnEkwTEEZa FWbp6c80dDkW2W2OEMGy5sUEsVjTXeQiT0Hpbp7X2iH+yWCzRp5BLROY52+fuSTQI4NH f9tiW/Mg3Nn73yyaF1WDOAAgYh0qCPnuRgzMeu49HJ9oi/tkb9Nr5VkYVJRcnjX/QH7x JE+L+V5fCJUHt34JjdDbJw8jKiWHMMitO5wPfBSZW11fSfLs31aIp68urqhgj65jII7d aRTa4aXeIlCX3tu95/Z/mOni2OHD9JL9uo8z3iMT752uE2GA2W89a1EXmGdYj2gs2pIj mX3g== X-Gm-Message-State: AOAM532AodIu8hD2xlSbudWdNymNd8/JFV7pyPXmgluPm5fI59v4IO62 EoSOLtW4jVGBPEPKiugblCRdkvroy0S4NQ== X-Received: by 2002:a17:90a:9f8f:: with SMTP id o15mr17569219pjp.55.1624126499782; Sat, 19 Jun 2021 11:14:59 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:14:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/33] tcg/tci: Use ffi for calls Date: Sat, 19 Jun 2021 11:14:30 -0700 Message-Id: <20210619181452.877683-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 64 +++++++++++++----- tcg/tci.c | 142 ++++++++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 50 +++++++------- 5 files changed, 153 insertions(+), 106 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 064dab383b..236315b682 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -52,6 +52,7 @@ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) #define CPU_TEMP_BUF_NLONGS 128 +#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) /* Default target word size to pointer size. */ #ifndef TCG_TARGET_REG_BITS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d0b5f3fa64..f2e5cba539 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -162,7 +162,7 @@ typedef enum { /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 -#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_STACK_ALIGN 8 #define HAVE_TCG_QEMU_TB_EXEC diff --git a/tcg/tcg.c b/tcg/tcg.c index de1a593ce7..6472c6a8f4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -147,7 +147,12 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2); static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); +#ifdef CONFIG_TCG_INTERPRETER +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, + ffi_cif *cif); +#else static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target); +#endif static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -1554,25 +1559,37 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) for (i = 0; i < nargs; i++) { int argtype = extract32(typemask, (i + 1) * 3, 3); bool is_64bit = (argtype & ~1) == dh_typecode_i64; + bool want_align = false; + +#if defined(CONFIG_TCG_INTERPRETER) + /* + * Align all arguments, so that they land in predictable places + * for passing off to ffi_call. + */ + want_align = true; +#elif defined(TCG_TARGET_CALL_ALIGN_ARGS) + /* Some targets want aligned 64 bit args */ + want_align = is_64bit; +#endif + + if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { + op->args[pi++] = TCG_CALL_DUMMY_ARG; + real_args++; + } if (TCG_TARGET_REG_BITS < 64 && is_64bit) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - /* some targets want aligned 64 bit args */ - if (real_args & 1) { - op->args[pi++] = TCG_CALL_DUMMY_ARG; - real_args++; - } -#endif - /* If stack grows up, then we will be placing successive - arguments at lower addresses, which means we need to - reverse the order compared to how we would normally - treat either big or little-endian. For those arguments - that will wind up in registers, this still works for - HPPA (the only current STACK_GROWSUP target) since the - argument registers are *also* allocated in decreasing - order. If another such target is added, this logic may - have to get more complicated to differentiate between - stack arguments and register arguments. */ + /* + * If stack grows up, then we will be placing successive + * arguments at lower addresses, which means we need to + * reverse the order compared to how we would normally + * treat either big or little-endian. For those arguments + * that will wind up in registers, this still works for + * HPPA (the only current STACK_GROWSUP target) since the + * argument registers are *also* allocated in decreasing + * order. If another such target is added, this logic may + * have to get more complicated to differentiate between + * stack arguments and register arguments. + */ #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] = temp_arg(args[i] + 1); op->args[pi++] = temp_arg(args[i]); @@ -3836,6 +3853,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) const int nb_oargs = TCGOP_CALLO(op); const int nb_iargs = TCGOP_CALLI(op); const TCGLifeData arg_life = op->life; + const TCGHelperInfo *info; int flags, nb_regs, i; TCGReg reg; TCGArg arg; @@ -3847,7 +3865,8 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) TCGRegSet allocated_regs; func_addr = tcg_call_func(op); - flags = tcg_call_flags(op); + info = tcg_call_info(op); + flags = info->flags; nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); if (nb_regs > nb_iargs) { @@ -3939,7 +3958,16 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) save_globals(s, allocated_regs); } +#ifdef CONFIG_TCG_INTERPRETER + { + gpointer hash = (gpointer)(uintptr_t)info->typemask; + ffi_cif *cif = g_hash_table_lookup(ffi_table, hash); + assert(cif != NULL); + tcg_out_call(s, func_addr, cif); + } +#else tcg_out_call(s, func_addr); +#endif /* assign output registers and emit moves if needed */ for(i = 0; i < nb_oargs; i++) { diff --git a/tcg/tci.c b/tcg/tci.c index d68c5a4e55..a3d23514cc 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,45 +18,26 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" +#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ +#include "exec/cpu_ldst.h" +#include "tcg/tcg-op.h" +#include "qemu/compiler.h" +#include -/* Enable TCI assertions only when debugging TCG (and without NDEBUG defined). - * Without assertions, the interpreter runs much faster. */ + +/* + * Enable TCI assertions only when debugging TCG (and without NDEBUG defined). + * Without assertions, the interpreter runs much faster. + */ #if defined(CONFIG_DEBUG_TCG) # define tci_assert(cond) assert(cond) #else # define tci_assert(cond) ((void)(cond)) #endif -#include "qemu-common.h" -#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" -#include "qemu/compiler.h" - -#if MAX_OPC_PARAM_IARGS != 6 -# error Fix needed, number of supported input arguments changed! -#endif -#if TCG_TARGET_REG_BITS == 32 -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#else -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#endif - __thread uintptr_t tci_tb_ptr; -static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - return regs[index]; -} - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -133,6 +114,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * I = immediate (tcg_target_ulong) * l = label or pointer * m = immediate (TCGMemOpIdx) + * n = immediate (call return length) * r = register * s = signed ldst offset */ @@ -153,6 +135,18 @@ static void tci_args_l(const uint8_t **tb_ptr, void **l0) check_size(start, tb_ptr); } +static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0, + void **l1, void **l2) +{ + const uint8_t *start = *tb_ptr; + + *n0 = tci_read_b(tb_ptr); + *l1 = (void *)tci_read_label(tb_ptr); + *l2 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -487,11 +481,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, { const uint8_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; - long tcg_temps[CPU_TEMP_BUF_NLONGS]; - uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); + uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) + / sizeof(uint64_t)]; + void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; regs[TCG_AREG0] = (tcg_target_ulong)env; - regs[TCG_REG_CALL_STACK] = sp_value; + regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; + /* Other call_slots entries initialized at first use (see below). */ + call_slots[0] = NULL; tci_assert(tb_ptr); for (;;) { @@ -509,40 +506,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif TCGMemOpIdx oi; int32_t ofs; - void *ptr; + void *ptr, *cif; /* Skip opcode and size entry. */ tb_ptr += 2; switch (opc) { case INDEX_op_call: - tci_args_l(&tb_ptr, &ptr); + /* + * Set up the ffi_avalue array once, delayed until now + * because many TB's do not make any calls. In tcg_gen_callN, + * we arranged for every real argument to be "left-aligned" + * in each 64-bit slot. + */ + if (unlikely(call_slots[0] == NULL)) { + for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) { + call_slots[i] = &stack[i]; + } + } + + tci_args_nll(&tb_ptr, &len, &ptr, &cif); + + /* Helper functions may need to access the "return address" */ tci_tb_ptr = (uintptr_t)tb_ptr; -#if TCG_TARGET_REG_BITS == 32 - tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); - tci_write_reg(regs, TCG_REG_R0, tmp64); - tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); -#else - tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); - tci_write_reg(regs, TCG_REG_R0, tmp64); -#endif + + ffi_call(cif, ptr, stack, call_slots); + + /* Any result winds up "left-aligned" in the stack[0] slot. */ + switch (len) { + case 0: /* void */ + break; + case 1: /* uint32_t */ + /* + * Note that libffi has an odd special case in that it will + * always widen an integral result to ffi_arg. + */ + if (sizeof(ffi_arg) == 4) { + regs[TCG_REG_R0] = *(uint32_t *)stack; + break; + } + /* fall through */ + case 2: /* uint64_t */ + if (TCG_TARGET_REG_BITS == 32) { + tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]); + } else { + regs[TCG_REG_R0] = stack[0]; + } + break; + default: + g_assert_not_reached(); + } break; + case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); tb_ptr = ptr; @@ -1119,7 +1134,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) TCGCond c; TCGMemOpIdx oi; uint8_t pos, len; - void *ptr; + void *ptr, *cif; const uint8_t *tb_ptr; status = info->read_memory_func(addr, buf, 2, info); @@ -1147,13 +1162,18 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) switch (op) { case INDEX_op_br: - case INDEX_op_call: case INDEX_op_exit_tb: case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; + case INDEX_op_call: + tci_args_nll(&tb_ptr, &len, &ptr, &cif); + info->fprintf_func(info->stream, "%-12s %d, %p, %p", + op_name, len, ptr, cif); + break; + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d54c01b9de..fa3de99445 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] = { # error Fix needed, number of supported input arguments changed! #endif -static const int tcg_target_call_iarg_regs[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, -#if TCG_TARGET_REG_BITS == 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, -#endif -}; +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] = { }; static const int tcg_target_call_oarg_regs[] = { TCG_REG_R0, @@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *label) static void stack_bounds_check(TCGReg base, target_long offset) { if (base == TCG_REG_CALL_STACK) { - tcg_debug_assert(offset < 0); - tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long))); + tcg_debug_assert(offset >= 0); + tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE + + TCG_STATIC_FRAME_SIZE)); } } @@ -593,11 +579,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, + ffi_cif *cif) { uint8_t *old_code_ptr = s->code_ptr; + uint8_t which; + + if (cif->rtype == &ffi_type_void) { + which = 0; + } else if (cif->rtype->size == 4) { + which = 1; + } else { + tcg_debug_assert(cif->rtype->size == 8); + which = 2; + } tcg_out_op_t(s, INDEX_op_call); - tcg_out_i(s, (uintptr_t)arg); + tcg_out8(s, which); + tcg_out_i(s, (uintptr_t)func); + tcg_out_i(s, (uintptr_t)cif); + old_code_ptr[1] = s->code_ptr - old_code_ptr; } @@ -822,11 +822,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - /* We use negative offsets from "sp" so that we can distinguish - stores that might pretend to be call arguments. */ - tcg_set_frame(s, TCG_REG_CALL_STACK, - -CPU_TEMP_BUF_NLONGS * sizeof(long), - CPU_TEMP_BUF_NLONGS * sizeof(long)); + /* The call arguments come first, followed by the temp storage. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + TCG_STATIC_FRAME_SIZE); } /* Generate global QEMU prologue and epilogue code. */ From patchwork Sat Jun 19 18:14:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463897 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1048600jao; Sat, 19 Jun 2021 11:21:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyPweEQgirJi7NNPKab02QSk551nMofwCD8LajcRC+Var9QGfku5otqoI86xua2fTlxre1+ X-Received: by 2002:a67:bb14:: with SMTP id m20mr12429005vsn.0.1624126883635; Sat, 19 Jun 2021 11:21:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126883; cv=none; d=google.com; s=arc-20160816; b=nROsO28ruuWgMDrplOvXLl8yv7zHzXhN/l356CB5nXLrFhENhSYp5enm92DVuRsEgK Zml7U2nHf0hdfJYKSuQnuTODUBM0ILXJGQ/jz4o+iL7uwlxBMrEqmeH8bPbvYn+84mwp y3iG2mAtUqaXJby+biIVYIOwU6jH4b+DBvrlLUrdehgmkM9Sz7xFsnq37/ipQxUAv1KS sTOo7Me9OeAM6lxojPkreGjcU42kd1d2IZspOkmE46yTAYg5rd6xSw91sFvxDfyuKBot ugnUoEgMapkYgrrI2YilHktCxuE5Hs0kbWj/ayjWNSzxRvRnCeyPxGRnbtLmTqgZ2rAi nFng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5QdQmSf+pzajUTai4DfkX1iSEONbc6XyiW6SAwFXLCc=; b=rhTB5VuUqfo6ZvA4gMCgZBAQegxSZt8yGyKcL81i0t9CbP1zPeb5FP2t/A/j8E9b37 +DSt05PKB9nLGP2NHUrQcxnRFrg07kQl96EuA8AyEthYSWCu+eNjqVYotucmEHtDPxSr cdrBCZEZQoAc1JSH7kjGImTUEXrYnbMkra7zfsqwxO8qd3MYnrijO0yd7aKLZxmQgpwH 7kt1TNMO79mproMeq86I/7T8618WItwFoho5Ku3yjJw2GdROLQAz3bV3LG4Hh0J16Lmz j1K/iOx2HSpzbbnnJfpWH8to39fQT99TiGlx2u7RBQY9ZTjCISBALVk7l+sxFHSQu/HS 124Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y9wnx1Sp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s12si8681219uar.64.2021.06.19.11.21.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:21:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y9wnx1Sp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufas-00042j-W6 for patch@linaro.org; Sat, 19 Jun 2021 14:21:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUl-0000ky-E9 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:03 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:36577) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUj-0002HG-O1 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:03 -0400 Received: by mail-pl1-x630.google.com with SMTP id x10so6336592plg.3 for ; Sat, 19 Jun 2021 11:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5QdQmSf+pzajUTai4DfkX1iSEONbc6XyiW6SAwFXLCc=; b=y9wnx1SpSiLtUXrd+yFyqLRIIR4pfhoC5cxnunWpKSwlHD1An7RwsM4UuD4fEPtgKv UbiZMfHE21zTfuX1er9PoacW/8LEiex+gjny5LYeIXriOhA1AGzcd5EcvOOWGY+xikBd CYA25rAPmqCHrQhUZxbBAnYjuCV2nZs+O4lmUIydNu3W+rhiNln+u3PmrcDkJCT1OuX/ KfdWi6hu5TtyymA9Y0EWNrCHP3LWFQnL2rS/xm6svamNbdBKokItCus4ceaoLFrDM++R fPDCNIJZlwM6nB+DY5Fad/eS/7LxxYW9gVLIFS6dke2pidUx7Lgaqov1kzSupj+EmqMj OnPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5QdQmSf+pzajUTai4DfkX1iSEONbc6XyiW6SAwFXLCc=; b=Bm0h11MvSMan+ODz1Ru048U3bTBbGLsMdzSsnV+aCyxdzn9muXk812WhR1xj4WG/LM Rqm7kJfc8qac+gJH8ov6c2UfyhUZpJTaHTSZZF0CI5MQY7DNIWnBTx/fcpcaNWuBYjQO Y/898aKz+FMUc+6RM5eY9q23FDaVIjburWpEksmfHO9W+owEOEPf3KUOC5W7VCzVElt2 n1Zvih2WMwamLsrBdEwuu6cjvKZoXTpnLrn32X42cFiBMeGohZjIeygujI6h/XeK8P0Y wHrgGzRyOJlHK82EHyblA7JOKNczNFJB+JrTNv8u0so1OJSH8fXtcMK4zYVEqxS9wG+0 6iPA== X-Gm-Message-State: AOAM533lTICrFW3RyuwXD3pkhHwf2WmdTtqG7rOb5pgicZk10nvzTk1l 3tW4dNm898nt43GmlfTayLqHhSO2+qgi+g== X-Received: by 2002:a17:90a:ab0c:: with SMTP id m12mr17623456pjq.179.1624126500372; Sat, 19 Jun 2021 11:15:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/33] tcg/tci: Reserve r13 for a temporary Date: Sat, 19 Jun 2021 11:14:31 -0700 Message-Id: <20210619181452.877683-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 1 + tcg/tci/tcg-target.c.inc | 1 + 2 files changed, 2 insertions(+) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f2e5cba539..80cafb7d18 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -156,6 +156,7 @@ typedef enum { TCG_REG_R14, TCG_REG_R15, + TCG_REG_TMP = TCG_REG_R13, TCG_AREG0 = TCG_REG_R14, TCG_REG_CALL_STACK = TCG_REG_R15, } TCGReg; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fa3de99445..5269a788a3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -820,6 +820,7 @@ static void tcg_target_init(TCGContext *s) MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); /* The call arguments come first, followed by the temp storage. */ From patchwork Sat Jun 19 18:14:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463906 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1051463jao; Sat, 19 Jun 2021 11:26:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxt48DXLrq8g+c35X1sDpgNRPJMEDctWP/pk9kgMCg+vKUBJduy5UlMfLfhIuu7nR93D7G1 X-Received: by 2002:a5d:97d9:: with SMTP id k25mr13185315ios.197.1624127217399; Sat, 19 Jun 2021 11:26:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127217; cv=none; d=google.com; s=arc-20160816; b=vby+2Bnfty8CWn7+3RXzI4MHrtE0BlH60H2iMBcBUGZxC8OnuEBVhThVebFwYz+1aC gzMthMOaCVJeolJUXlBR/KQmz13edOFZKfNsf6FfNR3hMP03bd97en/jgMxMBRac48It arnqu54X0e94sQz0a6ohHNyuQXpWAVajvpwtBQCdQEvYCJ/BLBhijp6InixYpJFlKaf2 50QOECfXaS3jxQLjZu6OGigQCKYAHyh6ABkO1Q6AYn8z0bE+7ueQPZA7BTB9gFUyrIZB 6y3S8whl1aEdYaP4hkkznY70Ss4nPqvRxsfzho79MmTZ5RHX6zTagRHeofJqwpQy1LUt 84SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y+NCVD/iV2FQ8NI37/cDaR7p2qu2Su9WKfwbtj7nnfI=; b=ON7jMepKnN8BgmPM3iWggXrERx78lG24Zh6zRUKQepKJ9NNEuPFcZYkPlAb0FpLLwD tGQEDyS+8OSAU+yuf2miPl9z49xlCpK7uhqAH1x014T4C2jV7ZAa61WOZYk43PwjBUw+ maGpdh8W1sMQC9CSUFEl9KmDDvsQdvr3gubmCrUJYPcAdk/k5iOFIpS5yt8RF/JG4ejz 3hr7XEDUcClbN3rvfmGvrsMXdvTbooWu/SxLGVHei225kf59aiKYY6SdLBsuf15xU2Mh uUg3H0U8OAiNjwvi7YQa8pLjclLwEbrT23GYiNMZ5aivmSL6YzmC/o54fJ6eN/qf+NrC /FoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l0kGsHtN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k14si1675144ion.22.2021.06.19.11.26.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:26:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l0kGsHtN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufgG-0007AJ-QM for patch@linaro.org; Sat, 19 Jun 2021 14:26:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUm-0000nD-Fr for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:05 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:36619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUk-0002HU-9f for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:04 -0400 Received: by mail-pj1-x102f.google.com with SMTP id s17-20020a17090a8811b029016e89654f93so10057604pjn.1 for ; Sat, 19 Jun 2021 11:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y+NCVD/iV2FQ8NI37/cDaR7p2qu2Su9WKfwbtj7nnfI=; b=l0kGsHtN8fw5o8iiLwdz0d8s6hOOlmPgDnkhBqLuX/zA2vyOpCpxkNu1eJxxRtM5t2 3lmEiEReOa7x6VlB3NzHL/2nx2NJGSmxezyrh0YsUAUpO5AO65tzl3o/mNRcsweZRmhY T4mdFJCXgagnDIHsPbRtRtkwpgthXzPaOGXjn1iP3TUdpK4MZag11OXuh72CzQu9LMMg gCD4dQoy73mH8BUauOllEM8HBb8fqAebrlXKIWZ2T0n/w8Rr+lLlBv7MDSo2WLMgEmb0 aSYsATAomCi+iwnUKGWOfXUAiYcSLispSLOmpa8m2AIwLOlhAlqCdWsvVYtpNbLfflFB lewg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y+NCVD/iV2FQ8NI37/cDaR7p2qu2Su9WKfwbtj7nnfI=; b=CDQP4JRgsLza59nhFwzLBQPBbts0BO2VVKSdFSvT9J/tz4Q6phkx5tdtnvpLk9MnZ6 wO1sCxR8nA48Zakb+dCK+SifoucZNaQRnMiBT26gBQRGfk2sphHQxZEPWdPFmMhyeYlp N9v6LidoOnxFpUycA32bYs6t9+WfIxFGj8GXvvRLQ23jo+1/BGJthvJRiZ+75hoD4C4x ErUeCEVBO1exYioY2OS0FnNhN3FvNDBXkcxCPCEnM9GAdGIuU/knfLLKOOB/E6hGsNyH hFlmO9bByx6BNJSzFCikDOlcsDR6qW7E7H1q3HTDKyxiSNSZisYrTqzd+9zmYUJu8zPe ECyA== X-Gm-Message-State: AOAM533vBpXA+OBAX+tb92oF+Q0MtanRSUoNdvRi0VfLA417IO5pJJwj hyjILnvuLAWG1D4TXkrlOJ1eoBvnydohMw== X-Received: by 2002:a17:90a:bf87:: with SMTP id d7mr28332124pjs.118.1624126500985; Sat, 19 Jun 2021 11:15:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/33] tcg/tci: Emit setcond before brcond Date: Sat, 19 Jun 2021 11:14:32 -0700 Message-Id: <20210619181452.877683-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg != 0. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 68 ++++++++++------------------------------ tcg/tci/tcg-target.c.inc | 52 +++++++++++------------------- 2 files changed, 35 insertions(+), 85 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index a3d23514cc..dfaa9c0fa0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -147,6 +147,16 @@ static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0, check_size(start, tb_ptr); } +static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +{ + const uint8_t *start = *tb_ptr; + + *r0 = tci_read_r(tb_ptr); + *l1 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -218,19 +228,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr, check_size(start, tb_ptr); } -static void tci_args_rrcl(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *c2 = tci_read_b(tb_ptr); - *l3 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -299,21 +296,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr, check_size(start, tb_ptr); } -static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *c4 = tci_read_b(tb_ptr); - *l5 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) { @@ -710,8 +692,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i32: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare32(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if ((uint32_t)regs[r0]) { tb_ptr = ptr; } break; @@ -728,15 +710,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); - T1 = tci_uint64(regs[r1], regs[r0]); - T2 = tci_uint64(regs[r3], regs[r2]); - if (tci_compare64(T1, T2, condition)) { - tb_ptr = ptr; - continue; - } - break; case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); @@ -864,8 +837,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare64(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if (regs[r0]) { tb_ptr = ptr; } break; @@ -1176,9 +1149,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s, %s, %s, %p", - op_name, str_r(r0), str_r(r1), str_c(c), ptr); + tci_args_rl(&tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p", + op_name, str_r(r0), ptr); break; case INDEX_op_setcond_i32: @@ -1303,13 +1276,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r3), str_r(r4), str_c(c)); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %p", - op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), str_c(c), ptr); - break; - case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5269a788a3..a1b5177abb 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -337,6 +337,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, } #endif +static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tci_out_label(s, l1); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { uint8_t *old_code_ptr = s->code_ptr; @@ -388,20 +399,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out8(s, c2); - tci_out_label(s, l3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -475,23 +472,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, - TCGCond c4, TCGLabel *l5) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out8(s, c4); - tci_out_label(s, l5); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -697,7 +677,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; CASE_32_64(brcond) - tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3])); + tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32 + ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64), + TCG_REG_TMP, args[0], args[1], args[2]); + tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3])); break; CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -723,8 +706,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], - args[3], args[4], arg_label(args[5])); + tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, + args[0], args[1], args[2], args[3], args[4]); + tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); From patchwork Sat Jun 19 18:14:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463908 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1052184jao; Sat, 19 Jun 2021 11:28:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeHgLpVVNXNma8z2cYtTrJSHEWXY2Fq6Qifz/ikssd9zwSOyBjRIKPYTBWBlmmLMJRhOtN X-Received: by 2002:a05:620a:f03:: with SMTP id v3mr15612846qkl.96.1624127293408; Sat, 19 Jun 2021 11:28:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127293; cv=none; d=google.com; s=arc-20160816; b=Zh4wV11+wkN1N0tqujNXLYB3N788w8w+/L5+gk2wLWN7syQCmSCmTWlRewaD1+aP4j nDxKZhmbyxdTdlYJjDAE1fxZ4SpQ1FZUo8OEQzpG6t/eFJgCqz384U8x+LzH9hF1SIR6 fqzl4VV2wjsl7ItjD8t2hGJ8R2gqct4gajs06RtHUDJjjWwOf73nZ28mEtk8+ug8EeTw 9dUPdYoWJYbTwj2lE4uBxA6azOOxJRu6eKooFCwzWxufB4PEIx7d7TmgMkTON5o3XBGY H5MWD1vPNOgJR6y3N50Yw809XPMzm+anb1jZukwOYVtR23xdhp24DYPKcAZPzzSQTSs5 yPpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vE1OJEIR9F5uVVqwRhGWH88diro5kD/GK3hhxvFNkQ4=; b=uBzN+EgYDMYgthIOObJsPSHo5i2uvSpUVxhmcUrTSliOjHk69Sxq8GV35A8R2z3pHL pA+C3iXHsbNRXFcGQJIPqupwb40vjG7kG60yyBdhVM6nJXzAvdkoP6QbWw2ANxcB6Bue pJZlkFrI2xJg/HqSX03XrnjGBrhwYPOhRZFyrLWkhl4BijMbK/5qv3CJBODTRPS+vhza bXcgNS4lRiu8AxwYqlbN2OrttccZdWY6VkeZveSPS7WdlC6OzCsqqmZanG4uV7hCO62G IAnbXOe7aNbraZwU4ebeF+yExoYQQgDmqo6yeLOfzwTVWYIBXf0kKVPVeXnl89HOwQaF j7bA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kDeSHUIL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m18si3287974qtx.247.2021.06.19.11.28.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:28:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kDeSHUIL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufhU-0004Ma-RJ for patch@linaro.org; Sat, 19 Jun 2021 14:28:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUo-0000oZ-Fu for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:07 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:44879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUk-0002IB-Nt for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:06 -0400 Received: by mail-pj1-x102a.google.com with SMTP id p4-20020a17090a9304b029016f3020d867so5690981pjo.3 for ; Sat, 19 Jun 2021 11:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vE1OJEIR9F5uVVqwRhGWH88diro5kD/GK3hhxvFNkQ4=; b=kDeSHUILd304QDyxew7USDq3jiZv6+vvdx0qEx9xnbcLTBmGaNW25fov6SuzpPZwDB QtpdEnL+JJigxr2D61FaT4e3CIwg18eFmZGez7r8BoODxtQsfvceV9sdEotmoeB0zxyw Mbx8aSSUeD5UqiYl3YT02Z59VLwiHKTHbGFsDvYZ03tFDs+0mrGfrn4Ad6gzEpZB8tL1 HeqD2H3DGzrTnYnQZOnnZqOUcEpJxzIwHtPiqbtXiDm3AN/oUflzcd8TF9xHgRe8oYsH 7ZZC7G9lyAnnY26VbzUrVWPGfhPwCtHRDmTCk4ifXXs2o+Ko3u/KCnmbHAJIL/HHKWI0 QdPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vE1OJEIR9F5uVVqwRhGWH88diro5kD/GK3hhxvFNkQ4=; b=dN8LU+gNaQFx9+HWjnpZYVZJXqDk+R1YhB0QhTGXx+ap5gHpWpEBR4EBEgr/+qGAqV 9C+AXZNU5bTs0xGEI40GSE7j696FNTKsdg+EBr+1jS9+JH0phlPYGxmbzY/HmT/qrL79 Eh58qyIlzg6EpqUP2l2AXlVN5c9X0y4ofyQIiH+OetzwDf5Naou7JMu/l9++aloQZi0i xyfbaWs7RDNKGAPT8KAJpCYFZ5dqMbq/zzxZhl6p3MyQ0xqgIozaEc0rjZSsND6JSomQ c8Ri54pPfNlYChvBW3RQdZc1K8vAT+G8lJFNSe5p1GLG9oEBGGthVxsumuHkh3rPh02C H6Rg== X-Gm-Message-State: AOAM530D+llEEQX6qs9L3UYuDuWlhJ6ux7FfIpICDFV3PoV5By88u/ou Fl42FiklRg3nml1TlmG3cy8a+fiAIoC2jw== X-Received: by 2002:a17:90b:78e:: with SMTP id l14mr16365527pjz.4.1624126501498; Sat, 19 Jun 2021 11:15:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/33] tcg/tci: Remove tci_write_reg Date: Sat, 19 Jun 2021 11:14:33 -0700 Message-Id: <20210619181452.877683-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index dfaa9c0fa0..613b94997c 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -38,20 +38,11 @@ __thread uintptr_t tci_tb_ptr; -static void -tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - tci_assert(index != TCG_AREG0); - tci_assert(index != TCG_REG_CALL_STACK); - regs[index] = value; -} - static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - tci_write_reg(regs, low_index, value); - tci_write_reg(regs, high_index, value >> 32); + regs[low_index] = value; + regs[high_index] = value >> 32; } /* Create a 64 bit value from two 32 bit values. */ From patchwork Sat Jun 19 18:14:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463904 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1050961jao; Sat, 19 Jun 2021 11:25:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxcS18pjk8esz4hGpXaDDjM3SGxObPtWqqSw8NHlPWXWgmhcJKZKTTAS/NI8o2XLUnN07Rx X-Received: by 2002:a05:6638:191d:: with SMTP id p29mr9487640jal.75.1624127157715; Sat, 19 Jun 2021 11:25:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127157; cv=none; d=google.com; s=arc-20160816; b=Ob6k5NOpdufRoP9D72u7i3IwcUhce0t1MHDDiJOxFl4vrhMItnoYziQwC1+lx/E3dS P5OdTHq/csc7GTRRH5b7bbtmqsFnxDXSNdQEG0ifruW9qtUJXuDXMb1pNn3vjKXPxdLV orViEgVMMcW4DLhoYd2+Awq+0u/wNzyIjODv2MWAOVRm4PLLcKiZYSraddyorUS0miCq awH35CzzfDQYtKC3kPVAeClrNluy8k781LJAsg+BeEBTd3pquna0TUbhaQMbO/KYtwXp HSyGCM0e88ErFkYRoY4kql3IrC2DP47xUhjYooHTWFLYOOrgTr4zGb7UgsONFldLPond stYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xaFjDc+u1QeFt8s+O5ZUvzDbRkO/VrPA0c1zmGNTbNE=; b=LgsUynGpxCgpOf/nv6TFUCpzoVmODboaM2ryf1akQ/KNWnT2Bgbt1lHzKbLlC3beyc EPfjBkkjAe/jinD6m1DK2iJBX3tn+AcEY8fwwGb9CScV8l4nxYhnk7tazWDUVsFpN4jQ ROo46LeyoY6fzd5W/glTEVx9zM4uDDlM7IxACVu000W3n6DgAjzQAclyPHX77t+r/aiM 8XhR3SbkSlit80FZ+pk1P2hJfVTN0GWxVKIOK+5EwaNXn7dtBc4FyAOD0xDOP8/Y4MHp 8buZfIU+H7vAOhlHsG5/++5rszINE9yhqbApq240Y3njVbwxijDqxda3IzHI7qXUyfjP o6UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T4iGJ39v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o13si9860094jas.110.2021.06.19.11.25.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:25:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T4iGJ39v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1luffJ-00077Q-3t for patch@linaro.org; Sat, 19 Jun 2021 14:25:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36000) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUu-0000um-5x for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:14 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:39522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUm-0002Jh-4T for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:11 -0400 Received: by mail-pl1-x634.google.com with SMTP id o21so6323271pll.6 for ; Sat, 19 Jun 2021 11:15:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xaFjDc+u1QeFt8s+O5ZUvzDbRkO/VrPA0c1zmGNTbNE=; b=T4iGJ39vZqw/2lAS0tbC6vuwCDPk67QRFc/XNlboFBKOcqufChmgQSZVAat7I357Ic BGv0jvZxZgxEi0os1NZPxBDKR/8LBjpDW1MjNlJIF2KYwm2uaXwbClO6hRPk9hiwQ+aP vzMhdojaoP9EdAcUcWuqZ+4uisQCPzpT8EbZZZDrTG6KuCfn2w69kHU7fH7KvC5btW8X eU6eGqR7aOWLXhKA5xVTNg18vguqL555hOzqV1L5U4gFLlSK6xMtH3ruI1Mtmn8N84wi S2BLOyOMHJ84GHFRZK7iD3L3EE4K32DEzzOog5MQj8XYDU64t6nlo52vGVkUfneLgeYF 8Jsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xaFjDc+u1QeFt8s+O5ZUvzDbRkO/VrPA0c1zmGNTbNE=; b=eDuKULhRixV6SEEzC8KprjtX0dK9dtjx5w3ZN0Oo5En8xH5h9f0PPqwkEXV+jbXcsh dgaDMR1luJcvySaIG4WNTg6ORYdu3GJxsA89jT4QWnvv9I5faYj4lhbnUo77xE6ydZO7 ZXfCgCECHDN7+qpN0/IL1UK/67Z0gFAxV+5Ng2ir4jzjNkhwBkFGV4MXWjYWoiCCDCPR MLa/KgSu4ZX29adedB6ZPLUnP39UsXDaWyFxL/tzv4U3ECa56hFSYVbpdAdupu7KGIXS 8jM8Z1R4o4f7AaTVL2EwfK+1aq4BEpFixJdWOI9Oczw9572mzL8LZW5yh3NdCrT7IQDO fEgw== X-Gm-Message-State: AOAM531t3xgaJIWttlekwr/kR2dnb7elldl9THADWgbxL07H8Lblhi6u dSwBpJdS2HG2EKUWnRGCmdWp7oi38Tmb+Q== X-Received: by 2002:a17:90a:390d:: with SMTP id y13mr17887932pjb.52.1624126502305; Sat, 19 Jun 2021 11:15:02 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/33] tcg/tci: Change encoding to uint32_t units Date: Sat, 19 Jun 2021 11:14:34 -0700 Message-Id: <20210619181452.877683-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i32, which have 6 register operands. We have, in previous patches, rearranged things such that there are no operations with a label which have more than one other operand. Which leaves us with a 20-bit field in which to encode a label, giving us a maximum TB size of 512k -- easily large. Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il]. The former puts the immediate in the upper 20 bits of the insn, like we do for the label displacement. The later uses a label to reference an entry in the constant pool. Thus, in the worst case we still have a single memory reference for any constant, but now the constants are out-of-line of the bytecode and can be shared between different moves saving space. Change INDEX_op_call to use a label to reference a pair of pointers in the constant pool. This removes the only slightly dodgy link with the layout of struct TCGHelperInfo. The re-encode cannot be done in pieces. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 4 +- tcg/tci/tcg-target.h | 3 +- tcg/tci.c | 539 +++++++++++++++------------------------ tcg/tci/tcg-target.c.inc | 379 ++++++++++++--------------- tcg/tci/README | 20 +- 5 files changed, 383 insertions(+), 562 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index bbb0884af8..5bbec858aa 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interpreter. */ -DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) #endif #undef TLADDR_ARGS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 80cafb7d18..c9cbe505a7 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -41,7 +41,7 @@ #define TCG_TARGET_H #define TCG_TARGET_INTERPRETER 1 -#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) @@ -166,6 +166,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 #define HAVE_TCG_QEMU_TB_EXEC +#define TCG_TARGET_NEED_POOL_LABELS /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. diff --git a/tcg/tci.c b/tcg/tci.c index 613b94997c..c82d5b2f51 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -51,49 +51,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) return ((uint64_t)high << 32) + low; } -/* Read constant byte from bytecode. */ -static uint8_t tci_read_b(const uint8_t **tb_ptr) -{ - return *(tb_ptr[0]++); -} - -/* Read register number from bytecode. */ -static TCGReg tci_read_r(const uint8_t **tb_ptr) -{ - uint8_t regno = tci_read_b(tb_ptr); - tci_assert(regno < TCG_TARGET_NB_REGS); - return regno; -} - -/* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) -{ - tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} - -/* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(const uint8_t **tb_ptr) -{ - uint32_t value = *(const uint32_t *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} - -/* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(const uint8_t **tb_ptr) -{ - int32_t value = *(const int32_t *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} - -static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) -{ - return tci_read_i(tb_ptr); -} - /* * Load sets of arguments all at once. The naming convention is: * tci_args_ @@ -110,211 +67,128 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * s = signed ldst offset */ -static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) { - const uint8_t *old_code_ptr = start - 2; - uint8_t op_size = old_code_ptr[1]; - tci_assert(*tb_ptr == old_code_ptr + op_size); + int diff = sextract32(insn, 12, 20); + *l0 = diff ? (void *)tb_ptr + diff : NULL; } -static void tci_args_l(const uint8_t **tb_ptr, void **l0) +static void tci_args_nl(uint32_t insn, const void *tb_ptr, + uint8_t *n0, void **l1) { - const uint8_t *start = *tb_ptr; - - *l0 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *n0 = extract32(insn, 8, 4); + *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; } -static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0, - void **l1, void **l2) +static void tci_args_rl(uint32_t insn, const void *tb_ptr, + TCGReg *r0, void **l1) { - const uint8_t *start = *tb_ptr; - - *n0 = tci_read_b(tb_ptr); - *l1 = (void *)tci_read_label(tb_ptr); - *l2 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; } -static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *l1 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); } -static void tci_args_rr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1) +static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *i1 = sextract32(insn, 12, 20); } -static void tci_args_ri(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrm(uint32_t insn, TCGReg *r0, + TCGReg *r1, TCGMemOpIdx *m2) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *i1 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *m2 = extract32(insn, 20, 12); } -#if TCG_TARGET_REG_BITS == 64 -static void tci_args_rI(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *i1 = tci_read_i(tb_ptr); - - check_size(start, tb_ptr); -} -#endif - -static void tci_args_rrm(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *m2 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); } -static void tci_args_rrr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGReg *r2) +static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *i2 = sextract32(insn, 16, 16); } -static void tci_args_rrs(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, int32_t *i2) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *i2 = tci_read_s32(tb_ptr); - - check_size(start, tb_ptr); -} - -static void tci_args_rrrc(const uint8_t **tb_ptr, +static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *c3 = tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *c3 = extract32(insn, 20, 4); } -static void tci_args_rrrm(const uint8_t **tb_ptr, +static void tci_args_rrrm(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *m3 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *m3 = extract32(insn, 20, 12); } -static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *i3 = tci_read_b(tb_ptr); - *i4 = tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *i3 = extract32(insn, 20, 6); + *i4 = extract32(insn, 26, 6); } -static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *m4 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); + *r4 = extract32(insn, 24, 4); } #if TCG_TARGET_REG_BITS == 32 -static void tci_args_rrrr(const uint8_t **tb_ptr, +static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); } -static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *r4 = tci_read_r(tb_ptr); - *c5 = tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); + *r4 = extract32(insn, 24, 4); + *c5 = extract32(insn, 28, 4); } -static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *r4 = tci_read_r(tb_ptr); - *r5 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); + *r4 = extract32(insn, 24, 4); + *r5 = extract32(insn, 28, 4); } #endif @@ -452,7 +326,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - const uint8_t *tb_ptr = v_tb_ptr; + const uint32_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; @@ -465,8 +339,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_assert(tb_ptr); for (;;) { - TCGOpcode opc = tb_ptr[0]; - TCGReg r0, r1, r2, r3; + uint32_t insn; + TCGOpcode opc; + TCGReg r0, r1, r2, r3, r4; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -474,15 +349,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 - TCGReg r4, r5; + TCGReg r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; - void *ptr, *cif; + void *ptr; - /* Skip opcode and size entry. */ - tb_ptr += 2; + insn = *tb_ptr++; + opc = extract32(insn, 0, 8); switch (opc) { case INDEX_op_call: @@ -498,12 +373,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } } - tci_args_nll(&tb_ptr, &len, &ptr, &cif); + tci_args_nl(insn, tb_ptr, &len, &ptr); /* Helper functions may need to access the "return address" */ tci_tb_ptr = (uintptr_t)tb_ptr; - ffi_call(cif, ptr, stack, call_slots); + { + void **pptr = ptr; + ffi_call(pptr[1], pptr[0], stack, call_slots); + } /* Any result winds up "left-aligned" in the stack[0] slot. */ switch (len) { @@ -532,76 +410,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; case INDEX_op_br: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr = ptr; continue; case INDEX_op_setcond_i32: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); T1 = tci_uint64(regs[r2], regs[r1]); T2 = tci_uint64(regs[r4], regs[r3]); regs[r0] = tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = regs[r1]; break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &t1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &t1); regs[r0] = t1; break; + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + regs[r0] = *(tcg_target_ulong *)ptr; + break; /* Load/store operations (32 bit). */ CASE_32_64(ld8u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint8_t *)ptr; break; CASE_32_64(ld8s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(int8_t *)ptr; break; CASE_32_64(ld16u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint16_t *)ptr; break; CASE_32_64(ld16s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint32_t *)ptr; break; CASE_32_64(st8) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint8_t *)ptr = regs[r0]; break; CASE_32_64(st16) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint16_t *)ptr = regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint32_t *)ptr = regs[r0]; break; @@ -609,171 +491,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (mixed 32/64 bit). */ CASE_32_64(add) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] + regs[r2]; break; CASE_32_64(sub) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] - regs[r2]; break; CASE_32_64(mul) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] * regs[r2]; break; CASE_32_64(and) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] & regs[r2]; break; CASE_32_64(or) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] | regs[r2]; break; CASE_32_64(xor) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] ^ regs[r2]; break; /* Arithmetic operations (32 bit). */ case INDEX_op_div_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; /* Shift/rotate operations (32 bit). */ case INDEX_op_shl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if ((uint32_t)regs[r0]) { tb_ptr = ptr; } break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &t1); - regs[r0] = t1; - break; - /* Load/store operations (64 bit). */ case INDEX_op_ld32s_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(int32_t *)ptr; break; case INDEX_op_ld_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint64_t *)ptr; break; case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint64_t *)ptr = regs[r0]; break; @@ -781,71 +658,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (64 bit). */ case INDEX_op_div_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; /* Shift/rotate operations (64 bit). */ case INDEX_op_shl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if (regs[r0]) { tb_ptr = ptr; } break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = bswap64(regs[r1]); break; #endif @@ -854,20 +731,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* QEMU specific operations. */ case INDEX_op_exit_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); return (uintptr_t)ptr; case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr = *(void **)ptr; break; case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { @@ -903,14 +780,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_ld_i64: if (TCG_TARGET_REG_BITS == 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr = tci_uint64(regs[r3], regs[r2]); + oi = regs[r4]; } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -961,10 +839,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_st_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } tmp32 = regs[r0]; @@ -991,16 +869,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_st_i64: if (TCG_TARGET_REG_BITS == 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; tmp64 = regs[r0]; } else { if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr = tci_uint64(regs[r3], regs[r2]); + oi = regs[r4]; } tmp64 = tci_uint64(regs[r1], regs[r0]); } @@ -1084,87 +963,69 @@ static const char *str_c(TCGCond c) /* Disassemble TCI bytecode. */ int print_insn_tci(bfd_vma addr, disassemble_info *info) { - uint8_t buf[256]; - int length, status; + const uint32_t *tb_ptr = (const void *)(uintptr_t)addr; const TCGOpDef *def; const char *op_name; + uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3; + TCGReg r0, r1, r2, r3, r4; #if TCG_TARGET_REG_BITS == 32 - TCGReg r4, r5; + TCGReg r5; #endif tcg_target_ulong i1; int32_t s2; TCGCond c; TCGMemOpIdx oi; uint8_t pos, len; - void *ptr, *cif; - const uint8_t *tb_ptr; + void *ptr; - status = info->read_memory_func(addr, buf, 2, info); - if (status != 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op = buf[0]; - length = buf[1]; + /* TCI is always the host, so we don't need to load indirect. */ + insn = *tb_ptr++; - if (length < 2) { - info->fprintf_func(info->stream, "invalid length %d", length); - return 1; - } - - status = info->read_memory_func(addr + 2, buf + 2, length - 2, info); - if (status != 0) { - info->memory_error_func(status, addr + 2, info); - return -1; - } + info->fprintf_func(info->stream, "%08x ", insn); + op = extract32(insn, 0, 8); def = &tcg_op_defs[op]; op_name = def->name; - tb_ptr = buf + 2; switch (op) { case INDEX_op_br: case INDEX_op_exit_tb: case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; case INDEX_op_call: - tci_args_nll(&tb_ptr, &len, &ptr, &cif); - info->fprintf_func(info->stream, "%-12s %d, %p, %p", - op_name, len, ptr, cif); + tci_args_nl(insn, tb_ptr, &len, &ptr); + info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr); break; case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p", op_name, str_r(r0), ptr); break; case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + tci_args_rrrc(insn, &r0, &r1, &r2, &c); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &i1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &i1); info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, op_name, str_r(r0), i1); break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &i1); - info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, - op_name, str_r(r0), i1); + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s, %p", + op_name, str_r(r0), ptr); break; -#endif case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -1185,7 +1046,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + tci_args_rrs(insn, &r0, &r1, &s2); info->fprintf_func(info->stream, "%-12s %s, %s, %d", op_name, str_r(r0), str_r(r1), s2); break; @@ -1212,7 +1073,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s, %s", op_name, str_r(r0), str_r(r1)); break; @@ -1247,28 +1108,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2)); break; case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d", op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_c(c)); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); @@ -1276,7 +1137,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); @@ -1294,30 +1155,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); switch (len) { case 2: - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); info->fprintf_func(info->stream, "%-12s %s, %s, %x", op_name, str_r(r0), str_r(r1), oi); break; case 3: - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x", op_name, str_r(r0), str_r(r1), str_r(r2), oi); break; case 4: - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); - info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %x", + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), oi); + str_r(r2), str_r(r3), str_r(r4)); break; default: g_assert_not_reached(); } break; + case 0: + /* tcg_out_nop_fill uses zeros */ + if (insn == 0) { + info->fprintf_func(info->stream, "align"); + break; + } + /* fall through */ + default: info->fprintf_func(info->stream, "illegal opcode %d", op); break; } - return length; + return sizeof(insn); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a1b5177abb..f74328dcbd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -22,20 +22,7 @@ * THE SOFTWARE. */ -/* TODO list: - * - See TODO comments in code. - */ - -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - -/* Bitfield n...m (in 32 bit value). */ -#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) +#include "../tcg-pool.c.inc" static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { @@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - /* tcg_out_reloc always uses the same type, addend. */ - tcg_debug_assert(type == sizeof(tcg_target_long)); + intptr_t diff = value - (intptr_t)(code_ptr + 1); + tcg_debug_assert(addend == 0); - tcg_debug_assert(value != 0); - if (TCG_TARGET_REG_BITS == 32) { - tcg_patch32(code_ptr, value); - } else { - tcg_patch64(code_ptr, value); - } - return true; -} - -/* Write value (native size). */ -static void tcg_out_i(TCGContext *s, tcg_target_ulong v) -{ - if (TCG_TARGET_REG_BITS == 32) { - tcg_out32(s, v); - } else { - tcg_out64(s, v); - } -} - -/* Write opcode. */ -static void tcg_out_op_t(TCGContext *s, TCGOpcode op) -{ - tcg_out8(s, op); - tcg_out8(s, 0); -} - -/* Write register. */ -static void tcg_out_r(TCGContext *s, TCGArg t0) -{ - tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); - tcg_out8(s, t0); -} - -/* Write label. */ -static void tci_out_label(TCGContext *s, TCGLabel *label) -{ - if (label->has_value) { - tcg_out_i(s, label->u.value); - tcg_debug_assert(label->u.value); - } else { - tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); - s->code_ptr += sizeof(tcg_target_ulong); + tcg_debug_assert(type == 20); + + if (diff == sextract32(diff, 0, type)) { + tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff)); + return true; } + return false; } static void stack_bounds_check(TCGReg base, target_long offset) @@ -285,239 +236,236 @@ static void stack_bounds_check(TCGReg base, target_long offset) static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tci_out_label(s, l0); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l0, 0); + insn = deposit32(insn, 0, 8, op); + tcg_out32(s, insn); } static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; + intptr_t diff; - tcg_out_op_t(s, op); - tcg_out_i(s, (uintptr_t)p0); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + /* Special case for exit_tb: map null -> 0. */ + if (p0 == NULL) { + diff = 0; + } else { + diff = p0 - (void *)(s->code_ptr + 1); + tcg_debug_assert(diff != 0); + if (diff != sextract32(diff, 0, 20)) { + tcg_raise_tb_overflow(s); + } + } + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 12, 20, diff); + tcg_out32(s, insn); } static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out32(s, (uint8_t)op); } static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out32(s, i1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(i1 == sextract32(i1, 0, 20)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 20, i1); + tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, - TCGReg r0, uint64_t i1) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out64(s, i1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} -#endif - static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tci_out_label(s, l1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l1, 0); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); } static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + tcg_out32(s, insn); } static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGArg m2) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out32(s, m2); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(m2 == extract32(m2, 0, 12)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 20, 12, m2); + tcg_out32(s, insn); } static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + tcg_out32(s, insn); } static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_debug_assert(i2 == (int32_t)i2); - tcg_out32(s, i2); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(i2 == sextract32(i2, 0, 16)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 16, i2); + tcg_out32(s, insn); } static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, c3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, c3); + tcg_out32(s, insn); } static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out32(s, m3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(m3 == extract32(m3, 0, 12)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 12, m3); + tcg_out32(s, insn); } static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, b3); - tcg_out8(s, b4); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(b3 == extract32(b3, 0, 6)); + tcg_debug_assert(b4 == extract32(b4, 0, 6)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 6, b3); + insn = deposit32(insn, 26, 6, b4); + tcg_out32(s, insn); } -static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, - TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out32(s, m4); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + insn = deposit32(insn, 24, 4, r4); + tcg_out32(s, insn); } #if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + tcg_out32(s, insn); } static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out8(s, c5); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + insn = deposit32(insn, 24, 4, r4); + insn = deposit32(insn, 28, 4, c5); + tcg_out32(s, insn); } static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out_r(s, r5); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + insn = deposit32(insn, 24, 4, r4); + insn = deposit32(insn, 28, 4, r5); + tcg_out32(s, insn); } #endif +static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, + TCGReg base, intptr_t offset) +{ + stack_bounds_check(base, offset); + if (offset != sextract32(offset, 0, 16)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS == 32 + ? INDEX_op_add_i32 : INDEX_op_add_i64), + TCG_REG_TMP, TCG_REG_TMP, base); + base = TCG_REG_TMP; + offset = 0; + } + tcg_out_op_rrs(s, op, val, base, offset); +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, intptr_t offset) { - stack_bounds_check(base, offset); switch (type) { case TCG_TYPE_I32: - tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset); break; #if TCG_TARGET_REG_BITS == 64 case TCG_TYPE_I64: - tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset); break; #endif default: @@ -547,22 +495,32 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: - tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); - break; #if TCG_TARGET_REG_BITS == 64 + arg = (int32_t)arg; + /* fall through */ case TCG_TYPE_I64: - tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); - break; #endif + break; default: g_assert_not_reached(); } + + if (arg == sextract32(arg, 0, 20)) { + tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg); + } else { + tcg_insn_unit insn = 0; + + new_pool_label(s, arg, 20, s->code_ptr, 0); + insn = deposit32(insn, 0, 8, INDEX_op_tci_movl); + insn = deposit32(insn, 8, 4, ret); + tcg_out32(s, insn); + } } static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, ffi_cif *cif) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; uint8_t which; if (cif->rtype == &ffi_type_void) { @@ -573,12 +531,10 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, tcg_debug_assert(cif->rtype->size == 8); which = 2; } - tcg_out_op_t(s, INDEX_op_call); - tcg_out8(s, which); - tcg_out_i(s, (uintptr_t)func); - tcg_out_i(s, (uintptr_t)cif); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); + insn = deposit32(insn, 0, 8, INDEX_op_call); + insn = deposit32(insn, 8, 4, which); + tcg_out32(s, insn); } #if TCG_TARGET_REG_BITS == 64 @@ -637,8 +593,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_st_i32: CASE_64(st32) CASE_64(st) - stack_bounds_check(args[1], args[2]); - tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); + tcg_out_ldst(s, opc, args[0], args[1], args[2]); break; CASE_32_64(add) @@ -731,8 +686,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } else { - tcg_out_op_rrrrm(s, opc, args[0], args[1], - args[2], args[3], args[4]); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]); + tcg_out_op_rrrrr(s, opc, args[0], args[1], + args[2], args[3], TCG_REG_TMP); } break; @@ -778,6 +734,11 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) return ct & TCG_CT_CONST; } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, sizeof(*p) * count); +} + static void tcg_target_init(TCGContext *s) { #if defined(CONFIG_DEBUG_TCG_INTERPRETER) diff --git a/tcg/tci/README b/tcg/tci/README index 9bb7d7a5d3..f72a40a395 100644 --- a/tcg/tci/README +++ b/tcg/tci/README @@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does. Like each TCG host frontend, TCI implements the code generator in tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci. -The additional file tcg/tci.c adds the interpreter. +The additional file tcg/tci.c adds the interpreter and disassembler. -The bytecode consists of opcodes (same numeric values as those used by -TCG), command length and arguments of variable size and number. +The bytecode consists of opcodes (with only a few exceptions, with +the same same numeric values and semantics as used by TCG), and up +to six arguments packed into a 32-bit integer. See comments in tci.c +for details on the encoding. 3) Usage @@ -39,11 +41,6 @@ suggest using this option. Setting it automatically would need additional code in configure which must be fixed when new native TCG implementations are added. -System emulation should work on any 32 or 64 bit host. -User mode emulation might work. Maybe a new linker script (*.ld) -is needed. Byte order might be wrong (on big endian hosts) -and need fixes in configure. - For hosts with native TCG, the interpreter TCI can be enabled by configure --enable-tcg-interpreter @@ -118,13 +115,6 @@ u1 = linux-user-test works in the interpreter. These opcodes raise a runtime exception, so it is possible to see where code must be added. -* The pseudo code is not optimized and still ugly. For hosts with special - alignment requirements, it needs some fixes (maybe aligned bytecode - would also improve speed for hosts which support byte alignment). - -* A better disassembler for the pseudo code would be nice (a very primitive - disassembler is included in tcg-target.c.inc). - * It might be useful to have a runtime option which selects the native TCG or TCI, so QEMU would have to include two TCGs. Today, selecting TCI is a configure option, so you need two compilations of QEMU. From patchwork Sat Jun 19 18:14:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463907 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1051833jao; Sat, 19 Jun 2021 11:27:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyal248N1WLh0Xpwyzp678RYMJBtlpaETDI6bRkT8lSdMyNJH9ujC6baHx8FAvhhYLqqo2n X-Received: by 2002:a05:6e02:612:: with SMTP id t18mr12296425ils.261.1624127260791; Sat, 19 Jun 2021 11:27:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127260; cv=none; d=google.com; s=arc-20160816; b=MbC2aD/6VfIF/6bo3ErLKUQJJNM55PxK0Wn7CsKiGdZ4z+Ix2z/Qv1HSIUpVTJbkiC nKGROwYDd5wGNflmH+57rDZel4rttQaoPGLykmdeNwBz4wW0SF2bRxRNJFv9xqW0iy85 ohjr71Kx4cbZ5XR14wkKAchrfJNq4DYsLVskElU1kzxD2phGSG5/GWFwizSDWY7Ub8rX imS2xz1k9hQPUZ8/8NwrMSLCK/esEPqpeFoeXPJR8wfDNz6ADuQzuWW0nE0Fkadijnf7 TlrD0AxzBOhiI99zruofYMqTPGOtodk4CWOeGUX2EyQA+0DI0FijLjo32vKEK0MiA7pJ hJDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FIepckuQ0vf0IX35eDp/bRawEQA5SsFxOuzC6IQ1UvY=; b=dRyixe5koyUkPiEve9MpsJYitqpjNSDnWzSJKoV/jnb5OodJxFsf8RdlKrpXdV/Oh2 /oBk0UWPqzOLKiZRzxHssM8nqRZ40T6o83TRzOODu4sFdLCKElZVNh4CQPHcsnpuZflb 3kNsziODsyQJOJu2oI2+p/30GrvAGJ3i3BJEISksIghl3O+frEcwva/8UMyRUBkstx2E n4w/udWxHTNTYDl5f46hIySJAfyvJ48S4Rg7N6PcU60HB6uNmCE5hmiHsVaaVLKtkyb5 Vd6VEqfmClFuV2Iap0GeAfEkrmbXm02b0r/iRIU4X8bOEbo6xTcFRMtMoV/ZnzCowTe1 2HNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mrWN1x2q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a1si12739228ioe.96.2021.06.19.11.27.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:27:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mrWN1x2q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufgy-0000cp-7M for patch@linaro.org; Sat, 19 Jun 2021 14:27:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUu-0000uq-T5 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:14 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:45599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUm-0002Jj-5H for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:12 -0400 Received: by mail-pj1-x102c.google.com with SMTP id z3-20020a17090a3983b029016bc232e40bso7766693pjb.4 for ; Sat, 19 Jun 2021 11:15:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FIepckuQ0vf0IX35eDp/bRawEQA5SsFxOuzC6IQ1UvY=; b=mrWN1x2qb87Y/dgke9VdcfH56Oljdf6m51aLiYV2s3Dh6Rg9SmyNbX1YDsTZQSUTwL 6UygU6eXQKqneUc1yJF3qD5OyZphYBOHtfhZzy19dWCCPqvJKhk2fxI7JVC6QqsfcIsg 4M3q2ADPh8Fr6wBYVkyKNXupMRI1h33FDnzvgE/J1HtrdxmzXUBVrHPx+ejgvbwIPoE/ IEKbzawbZQ2eM+10bj/uM3eubXJx5SBtJZFgcFs1KRrmgHhWY7+EF6fgT6NXs9bDBoCD HnpLYijFsnYh+RKv7/ob07oj/pdwrX2ml+Si3BwqdTfMz6BW6M1BMk/zZ2BZaSrO3DZo fAUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FIepckuQ0vf0IX35eDp/bRawEQA5SsFxOuzC6IQ1UvY=; b=j9TwBW0BWjONzUGZ9W1g67iLoFF1BuBWnQ3F8LR2cOyepuUJ5y/jFOTA8N6tVKjY4K BxRUO4mzzz7WGvx9+HHuYrRA+MDjG5qGaRWXjPP+9jyDLEdxHHKaw0ZcMyH3p5jBWTaF pIeUPZKlNGnZweng/9R9qsc78d/GcuEDY8Lj43TYpxoh7bNWNtr87FISBGpCRQAQDRU0 Rf0AorpQsawY/xLgYfXYPemzcSCM3EaCCjzKpLrRPAnUFqWumcW3n8Ze6kutFV6kIVkv HfSZvEmOkEEnFQw78fgOQQ2krck0YTjfiTCgQMoC49vLgsRGNkQCSDw2fjy1hnW2fjdl wQWg== X-Gm-Message-State: AOAM5313EwL3BhCoF5aXU49hzX1I5vexranv85EmuxpjlP0CDgSyMZKs 9C8wJ1tHQTpnGYxJNMHrzbiI5fd3+q53RQ== X-Received: by 2002:a17:90b:2306:: with SMTP id mt6mr15675588pjb.71.1624126502819; Sat, 19 Jun 2021 11:15:02 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/33] tcg/tci: Implement goto_ptr Date: Sat, 19 Jun 2021 11:14:35 -0700 Message-Id: <20210619181452.877683-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 8 +++++++- tcg/tci.c | 19 +++++++++++++++++++ tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++ 5 files changed, 44 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 316730f32c..ae2dc3b844 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -9,6 +9,7 @@ * Each operand should be a sequence of constraint letters as defined by * tcg-target-con-str.h; the constraint combination is inclusive or. */ +C_O0_I1(r) C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index c9cbe505a7..6ced9282c1 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -87,7 +87,7 @@ #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 diff --git a/tcg/tcg.c b/tcg/tcg.c index 6472c6a8f4..dd584f3bba 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -785,10 +785,16 @@ void tcg_prologue_init(TCGContext *s) } #endif - /* Assert that goto_ptr is implemented completely. */ +#ifndef CONFIG_TCG_INTERPRETER + /* + * Assert that goto_ptr is implemented completely, setting an epilogue. + * For tci, we use NULL as the signal to return from the interpreter, + * so skip this check. + */ if (TCG_TARGET_HAS_goto_ptr) { tcg_debug_assert(tcg_code_gen_epilogue != NULL); } +#endif } void tcg_func_start(TCGContext *s) diff --git a/tcg/tci.c b/tcg/tci.c index c82d5b2f51..4696ca161c 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -73,6 +73,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) *l0 = diff ? (void *)tb_ptr + diff : NULL; } +static void tci_args_r(uint32_t insn, TCGReg *r0) +{ + *r0 = extract32(insn, 8, 4); +} + static void tci_args_nl(uint32_t insn, const void *tb_ptr, uint8_t *n0, void **l1) { @@ -739,6 +744,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tb_ptr = *(void **)ptr; break; + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + ptr = (void *)regs[r0]; + if (!ptr) { + return 0; + } + tb_ptr = ptr; + break; + case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); @@ -996,6 +1010,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); + break; + case INDEX_op_call: tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f74328dcbd..fc73c199a0 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -27,6 +27,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { + case INDEX_op_goto_ptr: + return C_O0_I1(r); + case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) tcg_out32(s, insn); } +static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) +{ + tcg_insn_unit insn = 0; + + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { tcg_out32(s, (uint8_t)op); @@ -565,6 +577,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_goto_ptr: + tcg_out_op_r(s, opc, args[0]); + break; + case INDEX_op_br: tcg_out_op_l(s, opc, arg_label(args[0])); break; From patchwork Sat Jun 19 18:14:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463911 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1053495jao; Sat, 19 Jun 2021 11:30:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2HSwRf5JAkMMYfHyOLAqKDB+OgECw3nu51LbRHq7Qix98mKEMIgvF0lx+9XGhrPaDX5l/ X-Received: by 2002:a05:6e02:84:: with SMTP id l4mr11642413ilm.288.1624127436657; Sat, 19 Jun 2021 11:30:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127436; cv=none; d=google.com; s=arc-20160816; b=dc3SVRvenaaLBcO5LaA36iPjzgDWCd1dR6R+P+7cGsKkPQOW8Sl6zGV3vSBgFTDCr5 6xxf6cIuSKM66kfRcuhQOOoZ8TdGLAgiKM/LiOA7GCSNKEiE+Js9+zIlLoaBU4yCta4A 1XFNVyUBdk7UpSio2LmPI8fVZTSCAKLDZcVkVG8XqUidhqc9nF8ZJGoUbDeEYIoTXjVa 0ALFyX5wyddGLN2F282vIHjDdSs+LvCrtV+UTLKHVqIGg45/G9QuCez4+kx6T5oHuKQv 4Ww02jd22KAyyLx71EvLp7Z13+d8wc1Uev1yGYf0HV3WCLMm01hwQtoqa3ji6cMM0rdL HGSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ht6qU91HuyjlBdxrNhfQi8RcRcfq+IY9qFgBD2RpEI8=; b=dpnj/RgownGwjxkv8JGdFUcWidWlj9J0O/JksAFjZwoW1Wak08bsnZhMTP/JLHd2wE MMRouSNmgf/lflN8CA0YGGBerequywUSn+gjeM31anBe+zkc1CfGUVMaMjq0dOdd4iGE 7xV9vre+s4BgJ3Gh5Ux9lRNWJTgqxARMGg98sjRX4KQG+47vBoCw+J2fe1A6aoNck3WQ 9n7ah/tCSZy+zv9wR9qjNOL6pu+MOaDor9jjQbEGfkRmIXM8CD56UOesTTTjFsh/YlV8 iEtwfz/aXOKcw5yfhOolzM3m36N7qB4DGUlWZm3MN7o1d82U87K3DQUmIW0WYyWe0zM7 jKOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Fszl9Q/7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b3si1341925ilh.84.2021.06.19.11.30.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:30:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Fszl9Q/7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufjo-0001g4-3M for patch@linaro.org; Sat, 19 Jun 2021 14:30:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUq-0000qf-BC for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:08 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:53948) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUm-0002KB-LW for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:07 -0400 Received: by mail-pj1-x1034.google.com with SMTP id bb20so3364181pjb.3 for ; Sat, 19 Jun 2021 11:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ht6qU91HuyjlBdxrNhfQi8RcRcfq+IY9qFgBD2RpEI8=; b=Fszl9Q/7OEFJTom15myNbgDZ6az6DocTqkbmANeW1mnRGnRFpEeHaNzAK5SVx2tAVD FwLqrszRPfBDUIg3vuE0yGFCeRu+IkF59A95stjybgm97yUzSfOG7atvjhZKHg1lECS9 kdT2NO0+hzEmbl5FS8PPZdHE1lKcDWvmphCJUKa4k9ixZFowuegHo6asBRFIWDF9E6P0 JTW63IbyQEswfuPPfF/3vdBtxzXRErKmupahgiw/1dRfqiKhUZ4HEJdhCNEpM3IYTqt4 +upxNmpUjFVOSP0NAA2w9S0q54YXDUDO4/nV9PXsKt0f1DEve9GMSAC+V1ubYIr4uXGu Nq3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ht6qU91HuyjlBdxrNhfQi8RcRcfq+IY9qFgBD2RpEI8=; b=oPoTqfU8SLoUB54DYxk6R8aGdrTaWEOf6qzE0vX/dr0wR2/kMisVgCg73F/v+/LZqf Uou/95KeJeadi1DmiVVrguboyG2AwTJQ1U3xLCvf/TJXCsAv1y9b2JnkSDKtzJEFglco mWUlMAK3y2UOJ9Ef+ExRHpULWC+lhMfTm1zkDFk+G8aEKHGXWYRm+L+R8ddKaOMTq8qB gO8Y9UDZzsXw66C6nnT8z1mNWUe/HwJ8La7S83gWrml3Qi0kHX46P+oe1xJMBcv6wvr1 hq4GDBhWCSx2v1T9ZjdGOucZofRknXf4BjZzjHWkzXVqHxO5/jt07VVYnrn+dErpsBiR PAug== X-Gm-Message-State: AOAM532rW8CDKgooeIzqD8jchxSqMkIDaWCljofmS4TfF9bFcEOgsIt/ iAZ+IrHZVsjLjCRJ8i1BXWAqlryhZAJZig== X-Received: by 2002:a17:90a:7d06:: with SMTP id g6mr17673155pjl.91.1624126503269; Sat, 19 Jun 2021 11:15:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/33] tcg/tci: Implement movcond Date: Sat, 19 Jun 2021 11:14:36 -0700 Message-Id: <20210619181452.877683-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c | 16 +++++++++++++++- tcg/tci/tcg-target.c.inc | 10 +++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 6ced9282c1..5c79bfcf49 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -83,7 +83,7 @@ #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 @@ -120,7 +120,7 @@ #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 diff --git a/tcg/tci.c b/tcg/tci.c index 4696ca161c..2374c04d6b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -173,6 +173,7 @@ static void tci_args_rrrr(uint32_t insn, *r2 = extract32(insn, 16, 4); *r3 = extract32(insn, 20, 4); } +#endif static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) @@ -185,6 +186,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, *c5 = extract32(insn, 28, 4); } +#if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -422,6 +424,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare32(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i32: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 = tci_compare32(regs[r1], regs[r2], condition); + regs[r0] = regs[tmp32 ? r3 : r4]; + break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); @@ -434,6 +441,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare64(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i64: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 = tci_compare64(regs[r1], regs[r2], condition); + regs[r0] = regs[tmp32 ? r3 : r4]; + break; #endif CASE_32_64(mov) tci_args_rr(insn, &r0, &r1); @@ -1139,7 +1151,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); break; -#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", @@ -1147,6 +1160,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r3), str_r(r4), str_c(c)); break; +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fc73c199a0..2db189673c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); +#endif + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, r, r); -#endif case INDEX_op_qemu_ld_i32: return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS @@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } +#endif static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } +#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -589,12 +594,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; -#if TCG_TARGET_REG_BITS == 32 + CASE_32_64(movcond) case INDEX_op_setcond2_i32: tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; -#endif CASE_32_64(ld8u) CASE_32_64(ld8s) From patchwork Sat Jun 19 18:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463901 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1049938jao; Sat, 19 Jun 2021 11:24:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZLwFzdui/rzSiZYDwQXx8DHHFaX0CsrR/PHjB5LvzPCGcUXJzQd9auqCxlVD4mtlD0r53 X-Received: by 2002:a37:6149:: with SMTP id v70mr15260507qkb.41.1624127048966; Sat, 19 Jun 2021 11:24:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127048; cv=none; d=google.com; s=arc-20160816; b=OblTpefrP2iI5zejGJVwdyVpioW7jTcYOlB1O9Ourzr3Qdnep38eQg77+ROXF7IQKt iaiPssrAqEY/ghtiUdpnIdgg+QcurbVJnNWRyKAsEG2J0bVRpsS90IWVQjmFewGkPTn3 1jy1K7ufis3SnYBrwvfTS8C5Ps0dzWBPbyfZWtTu/ACmNxwDEuhH4Lz7yeWH64qZUoNh 9/jjBf71RbqF5prQxLNgmcI5t80P+nSERJNjY6/mMy+86cgTWA+NlLRcOMMlowW/4E+A 474YLXZ3qGKu11xIqsWQ9rurCvCfUBbjoDKCcAPDWw2G4Aww+cFlrlrB8qB7BQMx6WzB EPMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HUfT+nYYyzAWwTPPLKXAsus9d0nf7cbcMDBdxzZsWSI=; b=rBMkVcvPbh467+btCDV/LCG9OCAtvhqqqfLG69m68DGOQexA2g+7+7o0V2m55ov9ju qq7ChRGpLgZVZ8lJbpNbooX34uNKDY0kvTvdQr+mRcaaadP1KNvLWrwpJA+gDy3/+f1Z WzKHSdCjQcZg2JVfr83HxzF4T5NGuWjRIzb67vl0A1+TBjsySnlCY6wazrPHOQ1QE+L1 QabLbPBNhs1MKhHYHPb/33lmJCx/GWkEa56DXM091wpc442Sey7nRmAmlD6SOBWQGggJ KxdLOLUwawP4vP2WfnjHub4VD6ulZuvQ6ynzryzQkgoUQMXZE6xA6BOyVR9ahMvsjlH4 fWeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jViAmxoU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 12si5372014qty.283.2021.06.19.11.24.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:24:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jViAmxoU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufdY-0001Lt-AO for patch@linaro.org; Sat, 19 Jun 2021 14:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUt-0000ss-2V for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:11 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:34713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUm-0002Kw-W7 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:09 -0400 Received: by mail-pl1-x629.google.com with SMTP id h1so6343572plt.1 for ; Sat, 19 Jun 2021 11:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HUfT+nYYyzAWwTPPLKXAsus9d0nf7cbcMDBdxzZsWSI=; b=jViAmxoUSc1i2U6nEilmwlnosySAIonqFmVRnPexnzF0nlrf+5YJcs54NT8da5WxBA 2zrtnaKQYeZA4UHPIF+lX1IOXTWpWNAEN9jih38MbXkVoPYufXWmh7QVmwRCAqVr3aSL TS3kF46g8MyhawOUTg3j7ailSuOI91U9Kl/W4ttstOiSa9HyHVeHN0pftuEivhRAefgV SMuHNhAl7WoNtZEFyVOhA7witiPhN/xBpx7OQsZJ5SP2avoerF1Iill0bwauwlqpX7kw zjytOL2loZCPPipX/BDb0GfM2aTP9orX6RdqNxO2Z6yu/Eru0gGvzmvE8wkyYPJ0IGKA 7mBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HUfT+nYYyzAWwTPPLKXAsus9d0nf7cbcMDBdxzZsWSI=; b=TOwGaRI4KAyc3KTYjmYjJa9jlp+7JawEu+IAOyhNfsOKREN8t/KMw61S4EUEkoivSH Eeir4KOcux1we01p/3tdJJuN9IRP33ZlSlLhcD7p5FjtjuLSYD3QPDNp+I0alAbegnYs W1R/TXHq0D92IuNdqKrYbzQ2xVQp2WB11c+qo91ktCZl34twhHNZlxVCOIufb4CD6LUT 441QFv4KKxzn2Wzy3Y84m6csfwHgbYyFzK+VG9kQzCqBIaFVfOzq3r0sYkeWZeUtX3CJ nnLUGuMUE2H4LlWM0AZLJb9ZFeg1w4DTcybnw8sQ5iz7oxh02Vv08zps0ztT3ePn351g U2Ag== X-Gm-Message-State: AOAM5322TBYksXMiCbjQzAHIzQ/w3ls8RYNBT7rYpHz3o8TNOHBgnz4s AXM2qKF26/oBjn4zqDj886m7VtUSlodqBQ== X-Received: by 2002:a17:90a:5b14:: with SMTP id o20mr21378154pji.131.1624126503776; Sat, 19 Jun 2021 11:15:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 18/33] tcg/tci: Implement andc, orc, eqv, nand, nor Date: Sat, 19 Jun 2021 11:14:37 -0700 Message-Id: <20210619181452.877683-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These were already present in tcg-target.c.inc, but not in the interpreter. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 20 ++++++++++---------- tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 5c79bfcf49..ac8c2d85bd 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -68,20 +68,20 @@ #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 @@ -109,16 +109,16 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 2374c04d6b..8af82c7da7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -531,6 +531,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] ^ regs[r2]; break; +#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 + CASE_32_64(andc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] & ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 + CASE_32_64(orc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] | ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 + CASE_32_64(eqv) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = ~(regs[r1] ^ regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 + CASE_32_64(nand) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = ~(regs[r1] & regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 + CASE_32_64(nor) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = ~(regs[r1] | regs[r2]); + break; +#endif /* Arithmetic operations (32 bit). */ @@ -1121,6 +1151,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: case INDEX_op_div_i32: case INDEX_op_div_i64: case INDEX_op_rem_i32: From patchwork Sat Jun 19 18:14:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463898 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1048612jao; Sat, 19 Jun 2021 11:21:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzR2pH0Fxyxrr5YmXhRpUBhBElE0FtrhKrECsjzd0B6BJxBR+sm1HHaZZpsE3sVK5yb53es X-Received: by 2002:a67:df85:: with SMTP id x5mr12237283vsk.3.1624126885622; Sat, 19 Jun 2021 11:21:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624126885; cv=none; d=google.com; s=arc-20160816; b=A4IUhj/Jp0uNOVTDkadVPjuMv/J6AqymI811nRyjBYlFnHg+dsF/tGdRZN1zKw5UWW RL1Hik4B63PA3MsYi3u52axudJTG+RuuQdVPuiA7Zl3m6SxArK/qIn1YW0Sitbn8HdNa l4bE5vyyTkkMgjSYuv7wUCIcdDTxPGaOXcjRKtlsMvlCYckET7Kayjy6CvNBo/7Ka7Xb C3FX9VT8ij0a6b53649KK1HKKaujUnpQ6vwqcE1mPj+Fcii6Aq3ur4JVy86KOhCRkYxG KsICbtYlb8e/sByBSmWnn0ZxmZNYWXJNGzEW4/stsvbI3yMwlBryk7zsiAakkfMbRIZ4 Gk1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0SOAybo6J+ne2yDH7134TCtulNcLcAOxalT/wR4e4eg=; b=sxPHjtZR0mTVncmbcnmH5MzirnWTmDvVXauz9PUw9dPyY7Ik/uioSefNf9TlAAwsY0 y2aCsZLlBH7Fze5HzcmlvEBTxy444quTUzw2y7Mh7WnM34DOMm/OlEXeS9SZcb1tRP0e ns6F5QzPRK7+UOQ2NzG9eVIowNjtEA9w5Q0Ia6mH4frtv2AnC+Xxqmi2Jbi9gMyIQ/U7 vbi1DdOPSpd8j9HZHdyt4me0dwGv7EdPJRRCHR+BAGw8qv6ZI0CRz4ATXhlKvgZwSdAG JWE1ELM71e5b659uNeEV/WfMxBfrsdmfAz+3K7lvgLc3aFFO18pELeTiBU1BXUUQCWlg df7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZcfucyzL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z184si9666811vkf.46.2021.06.19.11.21.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:21:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZcfucyzL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufau-00045u-Vz for patch@linaro.org; Sat, 19 Jun 2021 14:21:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUq-0000ru-Rr for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:10 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:37790) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUo-0002L7-0n for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:08 -0400 Received: by mail-pf1-x42a.google.com with SMTP id w71so335074pfd.4 for ; Sat, 19 Jun 2021 11:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0SOAybo6J+ne2yDH7134TCtulNcLcAOxalT/wR4e4eg=; b=ZcfucyzLKrgHsuAuvhlDhS65SSZVATs2//NcjNFqmmPePe5wIFBdPkuxGjhe6N0pr9 pVa88veiG8N7Rq39CQ8Y9OgggSlVLNKKy++7PYhUoIhWEtV11tJvvkc57k6Cvp/VHoyb GECJRYMXWdKVVjeLR4hNPg1eo6FEeqEZyA4ZbyGENgbJeRumGkhyGpYQneeL7mDNGkPj RF2eVMqo3N8dmrpzHp0w9A57qAQp9DUm6USC3yoiZvN/z+AeExKOTRCBw10wIpaID+qR N043ACH2QcCTLbfDL/D7ntyLjviORLEPSXLMDYiGx4MjwYqtMzSEDLmPENc7t78w5tqJ 9hzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0SOAybo6J+ne2yDH7134TCtulNcLcAOxalT/wR4e4eg=; b=NA+z7WUxL31rAV242BWCUupYH0U6jpJV9HFDe/MFxpAQ5/wFVkDkdknqtqb5gExWtC JxhrKBdzE/wcwGyKRsMaZ48/P8aol3hGr3w6maYSCMTrMp9qpjmm1GOKx31j8xSoJ7yL 5LWO96ncdkyc2/zM0VY21kINsfp9B3waHmy4m1dX2x0qd5WWjw8ZbBn6p525uZFswo1H VA/IYM+pKua1zNVQeVnsjROnpkweQYVLCb4q/7HAm2cv7TbA2a17fCHtZg7NbAR1/E2R Mcjo3b8jSNxkQFuHVHEzt6NtVaUxAxdazf7oEpewZkZPRxYbTy9GruyYxRgTvlcbC9Eb m4+g== X-Gm-Message-State: AOAM532sQPcDrNd1WDRU27NwXg9zWSKB4hFM1JXdgichRh5SGZE+T311 E/I2dA6WAXG2QEg7i4va/qWxzFTB/kHxvQ== X-Received: by 2002:aa7:8509:0:b029:2e5:8cfe:bc17 with SMTP id v9-20020aa785090000b02902e58cfebc17mr11313546pfn.2.1624126504239; Sat, 19 Jun 2021 11:15:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 19/33] tcg/tci: Implement extract, sextract Date: Sat, 19 Jun 2021 11:14:38 -0700 Message-Id: <20210619181452.877683-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index ac8c2d85bd..f35813bd01 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -70,8 +70,8 @@ #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 @@ -98,8 +98,8 @@ #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 8af82c7da7..788f0235bc 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -126,6 +126,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) *i2 = sextract32(insn, 16, 16); } +static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, + uint8_t *i2, uint8_t *i3) +{ + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *i2 = extract32(insn, 16, 6); + *i3 = extract32(insn, 22, 6); +} + static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -610,6 +619,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i32 + case INDEX_op_extract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = extract32(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i32 + case INDEX_op_sextract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = sextract32(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i32: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -750,6 +771,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i64 + case INDEX_op_extract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = extract64(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i64 + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = sextract64(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i64: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -1191,6 +1224,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); break; + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), pos, len); + break; + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2db189673c..65cdc26812 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32: @@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } +static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, uint8_t b2, uint8_t b3) +{ + tcg_insn_unit insn = 0; + + tcg_debug_assert(b2 == extract32(b2, 0, 6)); + tcg_debug_assert(b3 == extract32(b3, 0, 6)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 6, b2); + insn = deposit32(insn, 22, 6, b3); + tcg_out32(s, insn); +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -651,6 +670,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */ + CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */ + { + TCGArg pos = args[2], len = args[3]; + TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <= max); + + tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len); + } + break; + CASE_32_64(brcond) tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32 ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64), From patchwork Sat Jun 19 18:14:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463914 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1056280jao; Sat, 19 Jun 2021 11:35:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwEqaZF6rasp5oQHgzaV/ScCD6wODQeZFYWOUZYtGc1zejd/mzOTRZUV8+LO4QFWTYkur/m X-Received: by 2002:a1f:c644:: with SMTP id w65mr10306140vkf.12.1624127702058; Sat, 19 Jun 2021 11:35:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127702; cv=none; d=google.com; s=arc-20160816; b=wzx5FtHG7qplbp7KvnEGTMU3A/LmKVmePCfaiyTiLk18v9vxpYiujXyTwZRQOORxq7 3I5uu2nZRCCEVpQ7qR1vZNims61eNAEH6cUvvRp9OdP/gck46M7v1UF9k7JgfAYxMf6Y VqPTiUTkz9eQ7jj1vu7bYJikSzSFeY8qe/miSlA+rUoxPJ4N62E6fXhkNu91j+SQjSt4 xV/qAqg4pvD5oyen4zEmH+E9vAK1BvFRcJIqo/WqQpcqFL4XeTgFAJcqi2GwYv6HV3vO IL/u5jMxAG83iW9qf1dPnAQjTJ53VxYSPUZXX4BPzTxEitLg6Prv6aR2uOxSr/20cbAn Uudg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+uASXuWPiHASia1640RtC4Epc/VWwyRiO4sJJNxaueo=; b=F54h2WefQZ0KbJBOV585T968W6JxnkHegUjVA0oGWqh2VQ3/N+z+dkiZ+xhMLv1h3F aYhx7WjOsx8ibi21MSuLd4DN9lXBW2dMB2mjFBt4qcIHIbYXUHIWg93CTdreWDfG2QGa rjCn2eYeWe+TGrpR8Rx0xjJ91MNBBOhkJdUEO2Csif+6T5AVJwA9u/uPhGw66gTsPmCv Jlh00ooRjaAyXTPLuxFv06LGgtUUnUgy/seCFPQ7oJiNii0CqM4h+TqBjiRs4YNHdl4F 7yu19wPaWG7nAe9jI6jxW6RcPGMs9KT1iAsxqh9ZBApWT7wuSD+obtWcGsfrdZDhEJtP nR3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MniVet8f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r125si9232321vkf.32.2021.06.19.11.35.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:35:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MniVet8f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufo5-0007VU-B6 for patch@linaro.org; Sat, 19 Jun 2021 14:35:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUt-0000uM-PQ for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:14 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:34714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUo-0002LK-46 for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:11 -0400 Received: by mail-pl1-x62a.google.com with SMTP id h1so6343582plt.1 for ; Sat, 19 Jun 2021 11:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+uASXuWPiHASia1640RtC4Epc/VWwyRiO4sJJNxaueo=; b=MniVet8f5OncXvUYg/tpqMwzOwgrG4PKngLNxmMN5nXhIcXZYAcfhqOHanEHyF77Au MkjtWi+90aDWmTdNPzOmvxCWCbHGkcPeMIEkVO4RHuFa4UmnaAk0ln4a1zVpiQR46MnN 51q5eJr60lOLosx5wxSzgYsv/chLLFV2URbNBdpy7WnV1Ggv3S5bHniIAx1U/QQZEeNa T7526GVuYvlVXSYje+g4T0OCTPBtPM3oJwAlac1KO5XK/EXyNqnJMpyiVOXQhYr3fifm M27g5q9v9S8EANbdRRGYxcgMOBDIIkDDa0Rk1GjWJ6wLXFFVc/9uPnzhKSBfSmecH2Ax fYgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+uASXuWPiHASia1640RtC4Epc/VWwyRiO4sJJNxaueo=; b=VoNIjndzwXn9fZJwv6XgTy8J7wgZhBhG+cHHvpqMngI5so+/+xAlxY/k6JzvZfYEac s/3zoc8pAbKS+TlqjpzzOISmUksmSQ6L5aPTnuGPuwPxvDtk1lCSoVvaLhEOIS/rIiBH Qdbav1DqYZhmb8zSoWdpFs5hNACyr/2IRehAUtnp+GU5bt1xtCntqQ5nLXzvnxnUosX2 TVw8IYqkUF2J5DFKlYZjhI2PVUMTr7oE/R5p1FgOISgiPLyl6qOm1mGmtJ1ef0sQPBSO TfCrikv6qFQ1EV/DlYFZh0WgPhotv9K+3tT+9VjGj3jKQN7ojuxjOe4QXXL2wCqE8+Fx Czmg== X-Gm-Message-State: AOAM5330dKgZxviIZrUd9sgmhbwmVnc7OkyM2YOmpCIwX16QId3HZvqZ okYVxRADEuDV6cdoAONdydwcrDjSF/n35A== X-Received: by 2002:a17:902:8d92:b029:113:91e7:89d6 with SMTP id v18-20020a1709028d92b029011391e789d6mr10278746plo.85.1624126504850; Sat, 19 Jun 2021 11:15:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/33] tcg/tci: Implement clz, ctz, ctpop Date: Sat, 19 Jun 2021 11:14:39 -0700 Message-Id: <20210619181452.877683-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 12 +++++------ tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 9 ++++++++ 3 files changed, 59 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f35813bd01..5614e16857 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -76,9 +76,9 @@ #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -113,9 +113,9 @@ #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 788f0235bc..adfca71c0f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -589,6 +589,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i32 + case INDEX_op_clz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 = regs[r1]; + regs[r0] = tmp32 ? clz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i32 + case INDEX_op_ctz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 = regs[r1]; + regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i32 + case INDEX_op_ctpop_i32: + tci_args_rr(insn, &r0, &r1); + regs[r0] = ctpop32(regs[r1]); + break; +#endif /* Shift/rotate operations (32 bit). */ @@ -741,6 +761,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i64 + case INDEX_op_clz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i64 + case INDEX_op_ctz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i64 + case INDEX_op_ctpop_i64: + tci_args_rr(insn, &r0, &r1); + regs[r0] = ctpop64(regs[r1]); + break; +#endif /* Shift/rotate operations (64 bit). */ @@ -1167,6 +1205,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s, %s", op_name, str_r(r0), str_r(r1)); @@ -1212,6 +1252,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2)); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 65cdc26812..69f41659be 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32: @@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_setcond_i64: case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: return C_O1_I2(r, r, r); case INDEX_op_brcond_i32: @@ -655,6 +661,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */ + CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */ tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; @@ -703,6 +711,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ tcg_out_op_rr(s, opc, args[0], args[1]); break; From patchwork Sat Jun 19 18:14:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463909 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1052301jao; Sat, 19 Jun 2021 11:28:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOkDApDhHy+NYMOI4x9gwXyFxTjTEZ+MNYXZQ8DnXgtPo/P/7VbAp+5RaIZIK2MH8unZLa X-Received: by 2002:ac8:7586:: with SMTP id s6mr16080115qtq.117.1624127306560; Sat, 19 Jun 2021 11:28:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127306; cv=none; d=google.com; s=arc-20160816; b=HeRQxanaV1niAZ3wyW90CsXpoF1UBHlay40h0vNADWeBTbsgPGxdA2Bwv0au14katA H5GT0H8LJFHibE/pgYX/5hsdyqT1Q3j6NwPlriWR46zlNNqt+h57F+uw09wC+B27r5MN 7gglxxNEsW0+Q+jcqTp/GAGkk/MVProS8PvD1kf9dCE8Fw37ehNZbcs5olAX8OGxjF7f 1XnQfmL3Jz4ZCRwh2b5mXMc87rzeGWoV/4GAK3mKn9NQbA8CzCNBXMfvsgzo+Vbr2i7E bXUvounU3A0QUmCEu/tbYe12c0Y0C2fJXCyA9feoHZWkqGH6OkRfRdk7v1VAuLHt/38j 373g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kw7+bwGwUqn3XkCOlv8Pogxg02JLdDldMJ7UBex/Bo8=; b=abZVbiNYxaHGvClQyZsC/THdsrl0CDL27aljVctoG/ciUhthbYYgH4k0AstOuT1s2K fZrEXQyAgFmgjiiGvXEqcAQyG9N82+0qH1j8Go5h2JJwflUqarmbKf3jasouNMMnG8ad E/eqRszK07RDZNAK6HrO+7d/4C+o5PngkBR5NELaWUN2Sv0jirRdGQUMC1rsdoSEnA5m Lu6VFM7CGN9g47z9lVvyvZQD7yqOuPBkKvZIMxcGB5IpikOp86eVIHPe8ijUlQmr5HCe qNIVTKoLzS1Rr4PaCSAJoFj2miGNl4hdEWaSZsScAa3LuDXL4uq8IjR1mURfHDqlFgof ILTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qo7XwAri; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p14si9834269qtn.360.2021.06.19.11.28.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:28:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qo7XwAri; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufhh-0004v2-VZ for patch@linaro.org; Sat, 19 Jun 2021 14:28:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36058) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUy-0000wx-9n for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:17 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:45603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUp-0002Lx-SO for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:15 -0400 Received: by mail-pj1-x1030.google.com with SMTP id z3-20020a17090a3983b029016bc232e40bso7766718pjb.4 for ; Sat, 19 Jun 2021 11:15:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kw7+bwGwUqn3XkCOlv8Pogxg02JLdDldMJ7UBex/Bo8=; b=qo7XwAriiPOk37n6Ut2IeHprw/0x46D3cT2xLdPOXAJPSF0RoLVesVPPB6/3IE4h2P OOmL/smlw0epDh/9B1yIcwv7JfuLkIcd/WoQmpRpHdDO+Z4YPIB6/Q6T+Fw9KBymumai kHAPIvq+PIpVfpyUBKaRlBOkYVblyfZ3weTZP0aFV4GZCszBEv1lQoQt54KDfiLKvlpZ NhOxOMsmNHjHgtKoY00QWw548GI8L4Kn1Hjl1gW3eI1TXIovooDVxyKRPYX3WfvfXkdx RZnziHLZt9/tRsQQ6rwixBgd1VXZqrC0AzjkEbfBHRkSSeSCKxmztRRFRad67KoHDwr0 rDiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kw7+bwGwUqn3XkCOlv8Pogxg02JLdDldMJ7UBex/Bo8=; b=dKhQ++HFTmJti720dp/TETn8V139y6d+SpHrDVQM4D/o02hWrZ2eWXX8TTRWSbU5+M hNoZbuX/hqT38iEYXVAILTPpg93+P1M2UzU3NLFAvYlUaBFPaNpyf72g0gcZKpic0HRY XhuQNADUqbiDKYk49vSmMAe27sY3PUZnWgdikRRFeGHkHcDOEUNAkd06BgXJo7iRwSge XJY3U50t5hG+EKVvG7+NDHG2H71oenkwoTuastBRtO64BNw0FxhUidAMPcsCoiA1UJEH xTInuaI8rv43XGW9kqS4vkrjygUGaArhUtKZ2KQuFGhlknPqPkXMJW2RUXVxzUW+NbsN JqYg== X-Gm-Message-State: AOAM530E1I8m6Oq0t3ua6KJbRW/lBlYPAvmlpVHavd9vEb78eXjbHAdq kXo6YvmNAAGhvm9PraZ++EyXvc083HGjPQ== X-Received: by 2002:a17:90a:7026:: with SMTP id f35mr3424952pjk.219.1624126505413; Sat, 19 Jun 2021 11:15:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/33] tcg/tci: Implement mulu2, muls2 Date: Sat, 19 Jun 2021 11:14:40 -0700 Message-Id: <20210619181452.877683-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 35 +++++++++++++++++++++++++++++------ tcg/tci/tcg-target.c.inc | 16 ++++++++++------ 3 files changed, 43 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 5614e16857..533f62bfcb 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -84,7 +84,7 @@ #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 @@ -121,13 +121,13 @@ #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 -#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 #else diff --git a/tcg/tci.c b/tcg/tci.c index adfca71c0f..ebe2eafa62 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -41,7 +41,7 @@ __thread uintptr_t tci_tb_ptr; static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - regs[low_index] = value; + regs[low_index] = (uint32_t)value; regs[high_index] = value >> 32; } @@ -173,7 +173,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, *r4 = extract32(insn, 24, 4); } -#if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { @@ -182,7 +181,6 @@ static void tci_args_rrrr(uint32_t insn, *r2 = extract32(insn, 16, 4); *r3 = extract32(insn, 20, 4); } -#endif static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) @@ -671,11 +669,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; +#endif /* TCG_TARGET_REG_BITS == 32 */ +#if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); + tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); break; -#endif /* TCG_TARGET_REG_BITS == 32 */ +#endif +#if TCG_TARGET_HAS_muls2_i32 + case INDEX_op_muls2_i32: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); + break; +#endif #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) tci_args_rr(insn, &r0, &r1); @@ -779,6 +787,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = ctpop64(regs[r1]); break; #endif +#if TCG_TARGET_HAS_mulu2_i64 + case INDEX_op_mulu2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif +#if TCG_TARGET_HAS_muls2_i64 + case INDEX_op_muls2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif /* Shift/rotate operations (64 bit). */ @@ -1286,14 +1306,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r3), str_r(r4), str_c(c)); break; -#if TCG_TARGET_REG_BITS == 32 case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); break; +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 69f41659be..e48dbc95d2 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); - case INDEX_op_mulu2_i32: - return C_O2_I2(r, r, r, r); #endif + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: + return C_O2_I2(r, r, r, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: @@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { @@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } -#endif static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -726,10 +728,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], args[3], args[4]); tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5])); break; - case INDEX_op_mulu2_i32: +#endif + + CASE_32_64(mulu2) + CASE_32_64(muls2) tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; -#endif case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: From patchwork Sat Jun 19 18:14:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463910 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1052564jao; Sat, 19 Jun 2021 11:29:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwqon67VwCk/8O827Ol70MntZ2dYfdha6sr24KqK7tR+Ozwpfs4solyTpX75zvXEw9wYY2F X-Received: by 2002:ac8:5213:: with SMTP id r19mr1359308qtn.349.1624127340687; Sat, 19 Jun 2021 11:29:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127340; cv=none; d=google.com; s=arc-20160816; b=Net+1WNDpYz+aFrOwB6RsVn8AovcUmwwqIVrvI0vv0yOdE1Z3Us+SRfxo6BK2k9UGi q6TmNDJRfLbZ438ZBOr3pSEY/cuOWQf3HNZiaXRQbqVlcO4L61ZHHUrHBLQcRFrN/uop hnCCvv8g+3zf891ZYJVv9em6M3Q52kCKwZqAjBk9nSAAcuTOrETPA0F/1rk3nCMME2uV xtoWTIxN2ch4xZMobQOgWTL50ZOFN0rnHevGOOgdHeevxN5wxQCyYzbDeEsbzFvs0o/4 zC7ki9JBc6lnKD0vnERQ84rOWVSG6Qo0xl2/Iicq5I5SryFSP7smqNoaQXMOIFA1ihdH IVjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l587JsUodF+74oTdjV4o6x+aoHertBLrBAAODTMX1WI=; b=kYwJ/nvsO6CMCZ++egl8un2VGQYWbYlK1Oy0bBn/hSLRbUTXw9M66bJGtNMu6MYbQk Z13rW0yRFH85dYW1PKRJAVNUGWLiUXWcLynHn3aqo+UttvFGHgAnOtiqIl6o5gWJ95Vu myZfw6McQ5IJQ+bz4b4n2ZinsNogpgkQn5+h71C9xKC0fl0k+CwHzU3HlVDZ3kS46ueI El6oWKR9LuZUuJGEvF0vVsnz8qh/71Aqrns8mdpOGvXMuPr01mRJNFCWywdG+5TPp0GT GRhdWxMhZ6DOUH44yJ3AYtlW2ETAKBBhr31PEs0v99wIsltox0B6rOuxfGci22xw+nW4 xhug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o7E4B5Zf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b15si1478563qvq.191.2021.06.19.11.29.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:29:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o7E4B5Zf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufiG-0006GA-1s for patch@linaro.org; Sat, 19 Jun 2021 14:29:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUv-0000ur-6m for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:14 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:45945) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUq-0002M8-5B for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:12 -0400 Received: by mail-pg1-x52d.google.com with SMTP id q15so10560673pgg.12 for ; Sat, 19 Jun 2021 11:15:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l587JsUodF+74oTdjV4o6x+aoHertBLrBAAODTMX1WI=; b=o7E4B5ZfT50IwOGIDdN6d4Jhf9gtYyF6AeAY5Nd9w0jj4mGpP/eb5CIk6MQ0nAYbcc Yl2LBhRph2WYU3xxRS8tbFHI59EdGdS3OfvREPHwNooEiPp84GHOYErRLBDYqdDIjR4K P08VJtsupUE2i9PPlsDERZ/b16kiMyWFYWy1C/CDT4dveuDAyv6JUEV4hDlbm0mQzSAO OLO8BtKcqxm8xwTyoLPdNDFddKaPUgZCAGF2yimZu8Ov60kEAFClAFA56jtNBW6UDW+e KR2O8JhPOMsh71JAWp6sWuSx5bNetDp/VF2huSSSbCp3vY64jVwuIbX/E4J1Bkv9bwgJ TCnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l587JsUodF+74oTdjV4o6x+aoHertBLrBAAODTMX1WI=; b=PGvmfObS6RiL9niRlqRcmCLB9gEAzcqsAnDW9bES7KIMsV4sIInSJGCwKfIlH/6ckc wHivNLKyQf8XG0WKBQ5+gqRy9JFCUjBudnpKLT7yOh37JdKqT4HLzLy9axK7NPjJvYsV K0BnkXLPmYNEct4SBFxOcbdPSNi4zVcLEkm5QzymjFmlLzNcLjkyDlmVcHXWO9m18Rsm b0jzcXp9IqW55Gao6gR+q5CH7ISQHbeBCxciHvsW7gQfD70E5YpOescfvOt6hhPOVQgY PRaWN0SuL97vzwNZBxB4G6+hbmuoMEEr1pZMImu95cqv10PCTdZmut/QGXqBH9dWXqcb YFzw== X-Gm-Message-State: AOAM532Ly4Pipc7teWfXykfQpUpqeK8CFgT6AyBhS3mzW9YZqq9lHv4o fTKoVtJooGed3jvUG7gWfbcOEntJEVgtKw== X-Received: by 2002:a05:6a00:1146:b029:2fe:d681:fbcc with SMTP id b6-20020a056a001146b02902fed681fbccmr11496476pfm.31.1624126505911; Sat, 19 Jun 2021 11:15:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/33] tcg/tci: Implement add2, sub2 Date: Sat, 19 Jun 2021 11:14:41 -0700 Message-Id: <20210619181452.877683-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 40 ++++++++++++++++++++++++++-------------- tcg/tci/tcg-target.c.inc | 15 ++++++++------- 3 files changed, 38 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 533f62bfcb..7b6089f304 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -122,11 +122,11 @@ #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 1 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index ebe2eafa62..7103005889 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -193,7 +193,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, *c5 = extract32(insn, 28, 4); } -#if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -204,7 +203,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, *r4 = extract32(insn, 24, 4); *r5 = extract32(insn, 28, 4); } -#endif static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { @@ -355,17 +353,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, for (;;) { uint32_t insn; TCGOpcode opc; - TCGReg r0, r1, r2, r3, r4; + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; -#if TCG_TARGET_REG_BITS == 32 - TCGReg r5; uint64_t T1, T2; -#endif TCGMemOpIdx oi; int32_t ofs; void *ptr; @@ -656,20 +651,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tb_ptr = ptr; } break; -#if TCG_TARGET_REG_BITS == 32 +#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 case INDEX_op_add2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; +#endif +#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; -#endif /* TCG_TARGET_REG_BITS == 32 */ +#endif #if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); @@ -799,6 +796,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); break; #endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_add2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 = regs[r2] + regs[r4]; + T2 = regs[r3] + regs[r5] + (T1 < regs[r2]); + regs[r0] = T1; + regs[r1] = T2; + break; +#endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_sub2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 = regs[r2] - regs[r4]; + T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]); + regs[r0] = T1; + regs[r1] = T2; + break; +#endif /* Shift/rotate operations (64 bit). */ @@ -1115,10 +1130,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) const char *op_name; uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3, r4; -#if TCG_TARGET_REG_BITS == 32 - TCGReg r5; -#endif + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong i1; int32_t s2; TCGCond c; @@ -1316,15 +1328,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r2), str_r(r3)); break; -#if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); break; -#endif case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e48dbc95d2..9651e7a8f1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_brcond_i64: return C_O0_I2(r, r); -#if TCG_TARGET_REG_BITS == 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: return C_O2_I4(r, r, r, r, r, r); + +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); #endif @@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 28, 4, r5); tcg_out32(s, insn); } -#endif static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, TCGReg base, intptr_t offset) @@ -717,12 +717,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_op_rr(s, opc, args[0], args[1]); break; -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: + CASE_32_64(add2) + CASE_32_64(sub2) tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; + +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, args[0], args[1], args[2], args[3], args[4]); From patchwork Sat Jun 19 18:14:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463916 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1056732jao; Sat, 19 Jun 2021 11:35:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw5P4utBhIrSYC/NWnswAbo2IOKUi8dfhBjK+RCtPOvmXCD8CmdS4M+4K61rhk0p/1ljgN+ X-Received: by 2002:a05:6130:30a:: with SMTP id ay10mr17765767uab.14.1624127751502; Sat, 19 Jun 2021 11:35:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127751; cv=none; d=google.com; s=arc-20160816; b=AbrutrfkahngJNVyYeLzaqi7ynLtijVh9ptvWesoX7Ky7uRFB69XZ2/QukQCRb0cAV uaTnPaB8oSEgHFhpjDGOyus21fb3lBQ+/CKn63TlNkBjmumDwHuVEh+9XsdvxM/1lMmH mk0O8cMzgwCDpI5RgANDnE0y5vEVk0k+7h3kl5oOi2cAEqlP/sGQqFsfeSH90orMt7y1 fVz2V/xjbQPLZmCZ0e0E7ZC1tjC87n5dXfM+GAwyA4gnsahrF5vqpIleuvbLsGFbj9Aj yCypz42/yGgQImdYBMTY9u3n7F/MK1e9HAyL9QPSZhHsYs2VMi4uF35baqc7LTDmHQGl 5s3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h010+aEkxbeE0HjnliG8rW250ADGcYL5RGoALR2ggFU=; b=udZpG+M6ou1rEWdGg02v560FAKvsbKfpgimT1B4ZpJXOj7V0/TAtWt/cRN0Osx35b0 sCNJFaiRX62JL7tUfb1q4P7tnKnhrJrLISJHy23Muxh+ox+Cxv2FJRI4S3256zO/35KJ iCVvdqG7jV9vMQe1SgFQGR4EL9QPb0OBX4Bd3v8/Kd2/OA51Q7VxpWkEGlfKK+hADXT/ p7k/2IF7RpWbnjLaPAwmP9beDF5UYWBE3ReHnJx2WDCRDCLpqMAYbDhvA8r2f/nu3Tdf 9fZMqPWGxgs8iVHYnWUDWG2XWfuzc6choX/u3ZwJQVoqbLHPdk0sqWaPm40h5JDfyitl bjqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuvbQbNn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l4si3264072uai.170.2021.06.19.11.35.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:35:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuvbQbNn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufos-0000xx-SL for patch@linaro.org; Sat, 19 Jun 2021 14:35:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV0-0000xI-KD for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:20 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:38646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUq-0002MC-2A for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:18 -0400 Received: by mail-pl1-x62c.google.com with SMTP id 69so6334753plc.5 for ; Sat, 19 Jun 2021 11:15:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h010+aEkxbeE0HjnliG8rW250ADGcYL5RGoALR2ggFU=; b=fuvbQbNnjSXwVYCZ7ttPR8DdOw53MRSSrAwv/HnW4Wc3GFIakq/Jg+1Nqygf+z2sOK uFS0BC1QwgI7naO8hfLluGKkr1RdA4n7+MbU4D56PCrrchV+f6kE7mnSXq2aSZ01yAYB 5F6IdAHQORZ8Gwkgs4WFMGLfDPN8K6tu0ikYNpoqEF2W2WeSgR6YUoKkF2f9X500XW68 U/exNPwFU9KSSPM1K/R6rCSAN5bi5l5PFgAbpVQMPauC0jbJNXcUJFJLRemiHi9fWjEK ZP5r6STteA5WYQL1EqIyS7vNIbZIKcIZrj1+nyPXNGv2dxtp91fPiXT+JejQpoVQXJlr PN9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h010+aEkxbeE0HjnliG8rW250ADGcYL5RGoALR2ggFU=; b=gAODPoIzWjvXa/o7ulDnk1jKJExM1Z2hJiPNpQ3QQLhkzDmUblj7rc1j8wH9zJavVj ZOOI/dwWmzl1QkJ/BDYaRgvPjvyAcIamLpEd8Nzpm7FpHTqEK+Gx0kjqMeIhDuvZxOkR GVf31Sr2wu0OrqlFTp/GNPiSEqzZ4IPTYgMT6DKd/oA/faoaWWbomnQHh0F1Wh02p38y B1qnNLCR0nzUKAO8Df+FyFrKceWAdQG4f221dhoFInIeB3VnH9z4ciAx9p1OIImZsckK RweiqJJoOW+nmtb8HMa3TzTvAJVE6r5ojG80VHoRHzCXnIvQbLyWx3Ir+sDl3fXm9rRe qQAQ== X-Gm-Message-State: AOAM533m8HeYSoHLxVmz+p2P4LCM1uMP32VYFrDAsp08g9+0yKlLyl7E k7ois2c9WeMuzqpeGu38PLpEB1Jfo34ZWg== X-Received: by 2002:a17:902:be0d:b029:11d:6614:88cd with SMTP id r13-20020a170902be0db029011d661488cdmr10347541pls.40.1624126506366; Sat, 19 Jun 2021 11:15:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/33] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Date: Sat, 19 Jun 2021 11:14:42 -0700 Message-Id: <20210619181452.877683-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can share this code between 32-bit and 64-bit loads and stores. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 183 +++++++++++++++++++++--------------------------------- 1 file changed, 71 insertions(+), 112 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 7103005889..5520537abe 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -317,6 +317,73 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) #define qemu_st_beq(X) \ cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, + TCGMemOpIdx oi, const void *tb_ptr) +{ + MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); + + switch (mop) { + case MO_UB: + return qemu_ld_ub; + case MO_SB: + return (int8_t)qemu_ld_ub; + case MO_LEUW: + return qemu_ld_leuw; + case MO_LESW: + return (int16_t)qemu_ld_leuw; + case MO_LEUL: + return qemu_ld_leul; + case MO_LESL: + return (int32_t)qemu_ld_leul; + case MO_LEQ: + return qemu_ld_leq; + case MO_BEUW: + return qemu_ld_beuw; + case MO_BESW: + return (int16_t)qemu_ld_beuw; + case MO_BEUL: + return qemu_ld_beul; + case MO_BESL: + return (int32_t)qemu_ld_beul; + case MO_BEQ: + return qemu_ld_beq; + default: + g_assert_not_reached(); + } +} + +static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, + TCGMemOpIdx oi, const void *tb_ptr) +{ + MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); + + switch (mop) { + case MO_UB: + qemu_st_b(val); + break; + case MO_LEUW: + qemu_st_lew(val); + break; + case MO_LEUL: + qemu_st_lel(val); + break; + case MO_LEQ: + qemu_st_leq(val); + break; + case MO_BEUW: + qemu_st_bew(val); + break; + case MO_BEUL: + qemu_st_bel(val); + break; + case MO_BEQ: + qemu_st_beq(val); + break; + default: + g_assert_not_reached(); + } +} + #if TCG_TARGET_REG_BITS == 64 # define CASE_32_64(x) \ case glue(glue(INDEX_op_, x), _i64): \ @@ -909,34 +976,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp32 = qemu_ld_ub; - break; - case MO_SB: - tmp32 = (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp32 = qemu_ld_leuw; - break; - case MO_LESW: - tmp32 = (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp32 = qemu_ld_leul; - break; - case MO_BEUW: - tmp32 = qemu_ld_beuw; - break; - case MO_BESW: - tmp32 = (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp32 = qemu_ld_beul; - break; - default: - g_assert_not_reached(); - } + tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr); regs[r0] = tmp32; break; @@ -952,46 +992,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = tci_uint64(regs[r3], regs[r2]); oi = regs[r4]; } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp64 = qemu_ld_ub; - break; - case MO_SB: - tmp64 = (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp64 = qemu_ld_leuw; - break; - case MO_LESW: - tmp64 = (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp64 = qemu_ld_leul; - break; - case MO_LESL: - tmp64 = (int32_t)qemu_ld_leul; - break; - case MO_LEQ: - tmp64 = qemu_ld_leq; - break; - case MO_BEUW: - tmp64 = qemu_ld_beuw; - break; - case MO_BESW: - tmp64 = (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp64 = qemu_ld_beul; - break; - case MO_BESL: - tmp64 = (int32_t)qemu_ld_beul; - break; - case MO_BEQ: - tmp64 = qemu_ld_beq; - break; - default: - g_assert_not_reached(); - } + tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); if (TCG_TARGET_REG_BITS == 32) { tci_write_reg64(regs, r1, r0, tmp64); } else { @@ -1008,25 +1009,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = tci_uint64(regs[r2], regs[r1]); } tmp32 = regs[r0]; - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp32); - break; - case MO_LEUW: - qemu_st_lew(tmp32); - break; - case MO_LEUL: - qemu_st_lel(tmp32); - break; - case MO_BEUW: - qemu_st_bew(tmp32); - break; - case MO_BEUL: - qemu_st_bel(tmp32); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); break; case INDEX_op_qemu_st_i64: @@ -1045,31 +1028,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } tmp64 = tci_uint64(regs[r1], regs[r0]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp64); - break; - case MO_LEUW: - qemu_st_lew(tmp64); - break; - case MO_LEUL: - qemu_st_lel(tmp64); - break; - case MO_LEQ: - qemu_st_leq(tmp64); - break; - case MO_BEUW: - qemu_st_bew(tmp64); - break; - case MO_BEUL: - qemu_st_bel(tmp64); - break; - case MO_BEQ: - qemu_st_beq(tmp64); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); break; case INDEX_op_mb: From patchwork Sat Jun 19 18:14:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463913 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1054585jao; Sat, 19 Jun 2021 11:32:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzH3FWNwES2BNmr5rnbTdNi4p2vyEY2mjUGM1r0AuFOIZ4ATkTNk0GDoGPMhtHbEG4pu+EA X-Received: by 2002:a67:7908:: with SMTP id u8mr12170701vsc.10.1624127545491; Sat, 19 Jun 2021 11:32:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127545; cv=none; d=google.com; s=arc-20160816; b=Jb4UFvEn9+4mT3WO/A7P2jMQiLNiYxr46edcb6IT0y6i0aYzhWmAauyJU/QHmV78XO KRf/KgoH1eGlZcC1QxWVFm6zJOTaIEz70qh6cwwMGGH9fWYSR5qUVcwANCot/qInZ18G hQbXGLCE4zSV8/6v/bUkOlx4ScKYtROiEvDdtmOBIJq4RIKYy+XuJf5V2dEva4OPWCGs R3kALberB3qttvPYS8ARETRu4Jxmy6E/Qn2biWeeSfRFkeTnItD2uHmo+ldpqQdIiZie LBYEyaWBBzV2xuFrIM37PXt/a/ZekEgojzpEg+1v38GtzdYUQBB0P9LA8axB8xQ/NBi9 rxyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Df7s7cK7c8SL/IAlkHACnvMM9CkTin1F/Jwc/gsLKKI=; b=RI1aW76b/FoytJTkiT/eiy8AQO/KR8ZvP3ZX0f5IKNuGaGGOxg5ZpVDkc6JtMJRKtM ZDKpQcxT/JP2fUAebV+dPaRfEws6qZcxzRjFeRp2AFO+758AsTqTovHfs14b8QXQpYQC 5QfTrzvsmZodbEOufU+1J0eA6w5zsB3706EvM+UH0vWFkUPZPA3JlaT/h/J1SjKd2Qw4 A/KT5vG87FA25zXfpTkoQwp0P/5iNo/AjC9cM/SLERVLQlx4pa66O+DMfKTm61iul5vE iqDMGuDsFOJ7dQ3gUC7h8pXlaWbo3Q3ZBIsr9HdzJE0idVa2XFYRdP+xTNhwJFWABEso wsew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ssu4qkwF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2si9181943vsk.11.2021.06.19.11.32.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:32:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ssu4qkwF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1luflY-0003gs-Ry for patch@linaro.org; Sat, 19 Jun 2021 14:32:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUw-0000us-JT for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:14 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:50877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUq-0002MG-5r for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:14 -0400 Received: by mail-pj1-x1033.google.com with SMTP id g4so7565504pjk.0 for ; Sat, 19 Jun 2021 11:15:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Df7s7cK7c8SL/IAlkHACnvMM9CkTin1F/Jwc/gsLKKI=; b=ssu4qkwFkLYvbhiRMJT94wB7YMgb0s/Lhm5m2DP7+I9QADs/WEPYi2EcYcxm+4XB/q +UTrq8+05vSG+y9LTYsvbicIYy4OexCkxrFOXgHIrhS5YLOtNSetkxKmP/0cOv2BFX7v kmxZhlkTR62M/fqCbmQwJeXCn0n+AmGfpH3OhvlH2RPFozu7JYk8N+l5p2n3d2JNS/ah T7QMJQTOEiiXHyYUit4WokdorHHl4c3UzdCda1rn1r+5sHGsNBIi65mtaV49oQyfjBkq iPIZwLhkhnyUE+JyHDZVLQ6NF5d5QvHsnCYNlAsFmDaSUSlbd3cLFtosAxRl+401RpmY Bo8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Df7s7cK7c8SL/IAlkHACnvMM9CkTin1F/Jwc/gsLKKI=; b=H0YHGVpRtzXoDlnyL9rBdLM7buOuQ8RcSoBsZdGScvSFsXW5nxSEkRcCdftaClLvkI wD6OsM+92IQM0vCHDt1eoPTyN0MSjR/RRM9ibPYWCdjunvpIOPuPwmszTIbkvme0M0cs V6J4vCC6IVx42o/LE3l5xawA4nzFup7lgH7UV46v7SGIzSTswxwPMgZpEn0w0nvwZc9h O4yV2iLSjt0uUyNEiKuf9OYbDAUPvSnHdfLM75JqDTM8Ox4wGAfaWdaTNl0xHdW4AZb/ TV2KAqg+/NgtvgwugAJxAV6Hot4U8FH+ERaID4NpxOWVYMZCFLt/StZI3noeg2YOhKxJ Oh/g== X-Gm-Message-State: AOAM5326baXa7l1A4Xo/LnQLnSkxFx/KrKe+8jXR0Y4uO7xSX2s8FTTJ 6k34GwvmswidA9/T0fVqgVFAy3mMDjgwNw== X-Received: by 2002:a17:90b:3147:: with SMTP id ip7mr17848067pjb.8.1624126506814; Sat, 19 Jun 2021 11:15:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/33] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Date: Sat, 19 Jun 2021 11:14:43 -0700 Message-Id: <20210619181452.877683-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This reverts commit dc09f047eddec8f4a1991c4f5f4a428d7aa3f2c0. For tcg, tracepoints are expanded inline in tcg opcodes. Using a helper which generates a second tracepoint is incorrect. For system mode, the extraction and re-packing of MemOp and mmu_idx lost the alignment information from MemOp. So we were no longer raising alignment exceptions for !TARGET_ALIGNED_ONLY guests. This can be seen in tests/tcg/xtensa/test_load_store.S. For user mode, we must update to the new signature of g2h() so that the revert compiles. We can leave set_helper_retaddr for later. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 73 ++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 5520537abe..cbe1afa289 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -288,34 +288,51 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) return result; } -#define qemu_ld_ub \ - cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leuw \ - cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leul \ - cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leq \ - cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beuw \ - cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beul \ - cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beq \ - cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_b(X) \ - cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lew(X) \ - cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lel(X) \ - cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_leq(X) \ - cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bew(X) \ - cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bel(X) \ - cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_beq(X) \ - cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#ifdef CONFIG_SOFTMMU +# define qemu_ld_ub \ + helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_ld_leuw \ + helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_ld_leul \ + helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_ld_leq \ + helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_ld_beuw \ + helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_ld_beul \ + helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_ld_beq \ + helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) +# define qemu_st_b(X) \ + helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +# define qemu_st_lew(X) \ + helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +# define qemu_st_lel(X) \ + helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +# define qemu_st_leq(X) \ + helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +# define qemu_st_bew(X) \ + helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +# define qemu_st_bel(X) \ + helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +# define qemu_st_beq(X) \ + helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) +#else +# define qemu_ld_ub ldub_p(g2h(env_cpu(env), taddr)) +# define qemu_ld_leuw lduw_le_p(g2h(env_cpu(env), taddr)) +# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(env_cpu(env), taddr)) +# define qemu_ld_leq ldq_le_p(g2h(env_cpu(env), taddr)) +# define qemu_ld_beuw lduw_be_p(g2h(env_cpu(env), taddr)) +# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(env_cpu(env), taddr)) +# define qemu_ld_beq ldq_be_p(g2h(env_cpu(env), taddr)) +# define qemu_st_b(X) stb_p(g2h(env_cpu(env), taddr), X) +# define qemu_st_lew(X) stw_le_p(g2h(env_cpu(env), taddr), X) +# define qemu_st_lel(X) stl_le_p(g2h(env_cpu(env), taddr), X) +# define qemu_st_leq(X) stq_le_p(g2h(env_cpu(env), taddr), X) +# define qemu_st_bew(X) stw_be_p(g2h(env_cpu(env), taddr), X) +# define qemu_st_bel(X) stl_be_p(g2h(env_cpu(env), taddr), X) +# define qemu_st_beq(X) stq_be_p(g2h(env_cpu(env), taddr), X) +#endif static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, TCGMemOpIdx oi, const void *tb_ptr) From patchwork Sat Jun 19 18:14:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463918 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1057603jao; Sat, 19 Jun 2021 11:37:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjgT+KdAe3nO+rZLMQH2/ptf+dmRJM7mxFdVtM1BEgGAczyjL4pWT0yGbOZFnRnwpe+Rb2 X-Received: by 2002:ac8:5d47:: with SMTP id g7mr15834335qtx.351.1624127841438; Sat, 19 Jun 2021 11:37:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127841; cv=none; d=google.com; s=arc-20160816; b=0JeKiys/85bvydtUih4+MSk8TW9Aeu4e83Y0XDXMJQA/Es8D1vBxC9iEFc6dVMS/gr GmC4GL4cxIj507l9ZFBjag3tkSyJbOujUBgIvR/EfbmgPVpUyQxAOV9KgUEnQlaVSEHZ CYX4OHh3Rg8YXvxtv3rN2Vc78D3ftr2u4yonZaoHYaPTs22kstjUNU13gLkdqHC8KD9K zMv9PlUCqE7SH/333MhY9ClBw6SAHm/6iOTwjd86TDOnm0PbrAfW7K0rVAdiPbM+S3Ql cN2jiNiTlGbUxVPApwvenS9MXaeTixNaMDMEYdrzaaMV1Pfm9WPb+G+bUcUMhZ+vTba5 VnCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lDQh3RHIBvFFZ/5eKksAkO3SIZPBgL6PLHQwDZAQ6is=; b=KGMkznCsk43qXSdVctRIwaIoyTYUTt5OuvOMExKhw5RMiFWegQ6PWFKs6XoA70OnBM Xn1Sdkm3PZXHWL5JZWrQjuRZgemHR0eQjObhBEGimCOrrQj+HSwMqKQjtRWC+CBkTpZI IVTKiQvjwKRicUwX14UDludrRUVMRRNwbzy5jcc/GM4OyvdMNURO7YXeMlFShLaYlNk0 U349G6pB7cOfDFwvDbaXj8PlZPj6biNuNGeyoCBhKLHQAS0SvU6Ud4MJllyT6z5lYkoA s63Fq1shSj1ZfkY4Z/JQAwJ+x0eMDCWauqRQCD8ta6m+2vWUddSWeZm4CLcBa+hD9BNk 9sFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="uQplcpC/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u5si9481909qtq.336.2021.06.19.11.37.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:37:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="uQplcpC/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufqK-0005zA-Qy for patch@linaro.org; Sat, 19 Jun 2021 14:37:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUz-0000x0-6k for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:19 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:34515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUq-0002MO-Jj for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:16 -0400 Received: by mail-pg1-x536.google.com with SMTP id g22so10605449pgk.1 for ; Sat, 19 Jun 2021 11:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lDQh3RHIBvFFZ/5eKksAkO3SIZPBgL6PLHQwDZAQ6is=; b=uQplcpC/l1nzKRaEP/u/BzTQnEptuxX+qEP4qq8QTb0ZZ/fjPRUDbrZOZHvtHjdR4u VVrc35A6n2r3lPBe06rHj1kMYGP/vIZf7ydw3XqipHFbO8/FPOcC6Ry9ldgl83w0oCog OXdIiymm2k/oI4QAqlxwit8+pZzmWipwoqRnk4rMuH2kI9/nToP/Xs92310gmR5Py+Wf kBnHqoZ92ZjBCwKE0mRd+yo7dPM3lnFN1XoyY0CtE5w7CCc4J8RlWO2uxZ5Oa3HoLekT N8T357C8uS9o/1td34SNfiiI/7MGoaznCD7ImBCETzeRePQ3KDvQI6/ENWFa1wFKepoP i2pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lDQh3RHIBvFFZ/5eKksAkO3SIZPBgL6PLHQwDZAQ6is=; b=Oqp4UZWbjGvf6IS6Riz9vBPb18tENgkJuGTWdFmFluLtLbPbVbvdEjxR62tLwpOAoo jKCfHMIFc2WyuJzhOfOEprvFXd6guMJVaGpwqwm0GEAa/UJiseSSOIWzISgnLDq5sRBA 4rnA4jDa+3ANXmfbjiIGKT+TldBFfGgWLiCLeeOZGD7q3GdMzGJUnDNb/gnxVW4sf99h jwc+RCDAnW9SxFp+5OLEv9jsyxbYv2H4IZ1AL2CtG6NWy2SnOZc1gVrodDjEKhPYPE7d vB0sO8uZdExDASTToBG9O52Szzkk4BS1mfn3ssvTJZYsfiF/GAFtDGnQBsmMMh4YhCyR pLiA== X-Gm-Message-State: AOAM532aBKcBa56PKyX716cWBROF1bQXJ3Asg02RvnM2Ri3qOHGjQOdw EoOl3h32GNAPTD6nKuezNL8xH+Yyk19/PQ== X-Received: by 2002:aa7:82cb:0:b029:2e6:f397:d248 with SMTP id f11-20020aa782cb0000b02902e6f397d248mr11575950pfn.52.1624126507338; Sat, 19 Jun 2021 11:15:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 25/33] tcg/tci: Remove the qemu_ld/st_type macros Date: Sat, 19 Jun 2021 11:14:44 -0700 Message-Id: <20210619181452.877683-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These macros are only used in one place. By expanding, we get to apply some common-subexpression elimination and create some local variables. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 165 +++++++++++++++++++++++++++++++++--------------------- 1 file changed, 100 insertions(+), 65 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index cbe1afa289..a5670f2109 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -288,85 +288,88 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) return result; } -#ifdef CONFIG_SOFTMMU -# define qemu_ld_ub \ - helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leuw \ - helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leul \ - helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leq \ - helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beuw \ - helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beul \ - helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beq \ - helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_st_b(X) \ - helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lew(X) \ - helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lel(X) \ - helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_leq(X) \ - helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bew(X) \ - helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bel(X) \ - helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_beq(X) \ - helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -#else -# define qemu_ld_ub ldub_p(g2h(env_cpu(env), taddr)) -# define qemu_ld_leuw lduw_le_p(g2h(env_cpu(env), taddr)) -# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(env_cpu(env), taddr)) -# define qemu_ld_leq ldq_le_p(g2h(env_cpu(env), taddr)) -# define qemu_ld_beuw lduw_be_p(g2h(env_cpu(env), taddr)) -# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(env_cpu(env), taddr)) -# define qemu_ld_beq ldq_be_p(g2h(env_cpu(env), taddr)) -# define qemu_st_b(X) stb_p(g2h(env_cpu(env), taddr), X) -# define qemu_st_lew(X) stw_le_p(g2h(env_cpu(env), taddr), X) -# define qemu_st_lel(X) stl_le_p(g2h(env_cpu(env), taddr), X) -# define qemu_st_leq(X) stq_le_p(g2h(env_cpu(env), taddr), X) -# define qemu_st_bew(X) stw_be_p(g2h(env_cpu(env), taddr), X) -# define qemu_st_bel(X) stl_be_p(g2h(env_cpu(env), taddr), X) -# define qemu_st_beq(X) stq_be_p(g2h(env_cpu(env), taddr), X) -#endif - static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, TCGMemOpIdx oi, const void *tb_ptr) { MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); +#ifdef CONFIG_SOFTMMU + uintptr_t ra = (uintptr_t)tb_ptr; + switch (mop) { case MO_UB: - return qemu_ld_ub; + return helper_ret_ldub_mmu(env, taddr, oi, ra); case MO_SB: - return (int8_t)qemu_ld_ub; + return helper_ret_ldsb_mmu(env, taddr, oi, ra); case MO_LEUW: - return qemu_ld_leuw; + return helper_le_lduw_mmu(env, taddr, oi, ra); case MO_LESW: - return (int16_t)qemu_ld_leuw; + return helper_le_ldsw_mmu(env, taddr, oi, ra); case MO_LEUL: - return qemu_ld_leul; + return helper_le_ldul_mmu(env, taddr, oi, ra); case MO_LESL: - return (int32_t)qemu_ld_leul; + return helper_le_ldsl_mmu(env, taddr, oi, ra); case MO_LEQ: - return qemu_ld_leq; + return helper_le_ldq_mmu(env, taddr, oi, ra); case MO_BEUW: - return qemu_ld_beuw; + return helper_be_lduw_mmu(env, taddr, oi, ra); case MO_BESW: - return (int16_t)qemu_ld_beuw; + return helper_be_ldsw_mmu(env, taddr, oi, ra); case MO_BEUL: - return qemu_ld_beul; + return helper_be_ldul_mmu(env, taddr, oi, ra); case MO_BESL: - return (int32_t)qemu_ld_beul; + return helper_be_ldsl_mmu(env, taddr, oi, ra); case MO_BEQ: - return qemu_ld_beq; + return helper_be_ldq_mmu(env, taddr, oi, ra); default: g_assert_not_reached(); } +#else + void *haddr = g2h(env_cpu(env), taddr); + uint64_t ret; + + switch (mop) { + case MO_UB: + ret = ldub_p(haddr); + break; + case MO_SB: + ret = ldsb_p(haddr); + break; + case MO_LEUW: + ret = lduw_le_p(haddr); + break; + case MO_LESW: + ret = ldsw_le_p(haddr); + break; + case MO_LEUL: + ret = (uint32_t)ldl_le_p(haddr); + break; + case MO_LESL: + ret = (int32_t)ldl_le_p(haddr); + break; + case MO_LEQ: + ret = ldq_le_p(haddr); + break; + case MO_BEUW: + ret = lduw_be_p(haddr); + break; + case MO_BESW: + ret = ldsw_be_p(haddr); + break; + case MO_BEUL: + ret = (uint32_t)ldl_be_p(haddr); + break; + case MO_BESL: + ret = (int32_t)ldl_be_p(haddr); + break; + case MO_BEQ: + ret = ldq_be_p(haddr); + break; + default: + g_assert_not_reached(); + } + return ret; +#endif } static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, @@ -374,31 +377,63 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, { MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); +#ifdef CONFIG_SOFTMMU + uintptr_t ra = (uintptr_t)tb_ptr; + switch (mop) { case MO_UB: - qemu_st_b(val); + helper_ret_stb_mmu(env, taddr, val, oi, ra); break; case MO_LEUW: - qemu_st_lew(val); + helper_le_stw_mmu(env, taddr, val, oi, ra); break; case MO_LEUL: - qemu_st_lel(val); + helper_le_stl_mmu(env, taddr, val, oi, ra); break; case MO_LEQ: - qemu_st_leq(val); + helper_le_stq_mmu(env, taddr, val, oi, ra); break; case MO_BEUW: - qemu_st_bew(val); + helper_be_stw_mmu(env, taddr, val, oi, ra); break; case MO_BEUL: - qemu_st_bel(val); + helper_be_stl_mmu(env, taddr, val, oi, ra); break; case MO_BEQ: - qemu_st_beq(val); + helper_be_stq_mmu(env, taddr, val, oi, ra); break; default: g_assert_not_reached(); } +#else + void *haddr = g2h(env_cpu(env), taddr); + + switch (mop) { + case MO_UB: + stb_p(haddr, val); + break; + case MO_LEUW: + stw_le_p(haddr, val); + break; + case MO_LEUL: + stl_le_p(haddr, val); + break; + case MO_LEQ: + stq_le_p(haddr, val); + break; + case MO_BEUW: + stw_be_p(haddr, val); + break; + case MO_BEUL: + stl_be_p(haddr, val); + break; + case MO_BEQ: + stq_be_p(haddr, val); + break; + default: + g_assert_not_reached(); + } +#endif } #if TCG_TARGET_REG_BITS == 64 From patchwork Sat Jun 19 18:14:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463900 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1049543jao; Sat, 19 Jun 2021 11:23:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeDnnqci81PQhOsjRedYgPjgqqWQg/PvWkLWXtoaSjCdMcSFZdieQVL2DNg/mfHskaMf4l X-Received: by 2002:a05:620a:c8d:: with SMTP id q13mr15415926qki.70.1624127002436; Sat, 19 Jun 2021 11:23:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127002; cv=none; d=google.com; s=arc-20160816; b=Cz+rBH62XR/DTCAqPpZIVQxAP+wV0vY8xzkQFSPXPOrLJVDyejSrLD+QizapP/yBdp XDvy4xDZdxYTXPXEgCSFnR68W+SpXOR53RnWlixv6xGaYwOFtG0odh5iiW5dNBoNKm62 VOrye2xHKx+e09uqFvUKdrPMOB1bdRtXoSivdL6Cr7YF+rWxFg8kVthDAiLIxlVPmANk R2h4ZakbC2pAhMGObbGQ//X5sAzZTLjTMC3RzKwXLk4vOgJx9TIeDeZh52nxcaRJSReu d7UOYi4Z8sCf7nhaPD1LAK4wEALAw8HM9w/l03gPNsUUA6C5H9thyLbw1wKG52qtAnHJ EuGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3LWcBSiEHKmb3rQtnRtGOpef7nDxbsC5JhldyG/Wz8U=; b=oMdhTXULtJdpyB3x7Gom5GI4UQptoyh7F1i7nv5oBjWH2qId/pA1LyuMJwdEfAQ+eH 1JPMNLVAGJMyJGg3o0N2luz3v6TIokx4MGtCtaePlEnVpaDiTFHU9rPWbQf1Ps3rI5Ac nfWHcXOrHB+yzSsctI0Eqs7JPpFe/+M4WzwQck31JgmI2r8vor1j0shMSOMIu+JNef9T McV5AtO7KCz1Fmb2y3/yw5sUDUC2fKwL0UO1l9unwifLH1rwRfEkmnNCyvr0k0ewvS+k ez7bqXzsmqPArhSOqYzwKdS5dRZzydAjLCR6jBB0seeZS5Khv57oqoPFLnU5OMvM1/CW Fjrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AaTRtk1B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 9si8022851qvk.214.2021.06.19.11.23.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:23:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AaTRtk1B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufcn-0001Ue-QY for patch@linaro.org; Sat, 19 Jun 2021 14:23:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufUy-0000wy-VE for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:19 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:37523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUr-0002MZ-3W for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:16 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 22-20020a17090a0c16b0290164a5354ad0so10053437pjs.2 for ; Sat, 19 Jun 2021 11:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3LWcBSiEHKmb3rQtnRtGOpef7nDxbsC5JhldyG/Wz8U=; b=AaTRtk1BgDds5lbz83+8XWalqB2gzuR3euTJ/bCnA8L6afwaKEsq/+hGwZDtxA7+yj AnAiYPMDjSEdnAd4g4klZ6HF3CBuOU5GIwlGNup7Iot6Ew2bctGZ31oZFbQ55F5vx0LS OJtOvWukmRudX+ILNSVVHbfkhxEcHhkQ0P7mPFB6pzUXpXdjCWHe4kTaSMn4DPBOz1cM M4YyJAaNzAVMAuINitej3/vdZJ2TDvnwHz4T+OpX+qUfxMQ9O+9otBjPGlXYhLnX1yjm 1XFGjcgS1sVdOpIeTAx8ZZ4gcYk9Ifci30WoOj5KxNSMQpeI5KUySn2YJS7W54mDUd/V 4x2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3LWcBSiEHKmb3rQtnRtGOpef7nDxbsC5JhldyG/Wz8U=; b=XtFCnmo6g0Z0zcj4WO3S/uqhF4rZ3DtXWIhnli/c13zsRzI9IwAfWvMN10Yk3Y4WwR eXYMBl/JCgCKdin/AbHQ0l5ab4njBQAWWteROAEx9omPy8AuLeYszW/yfqM6md7hQj/B BW1IIM/iy8KdCPllYVe/yhplxfhtj6lj4cSdLbto4R3hrqIP+BExUO+DNsChqBqQzj3t BsPhqbzu5Lm7rnQCxU4YrYdAd0kN95BypMoydX3FSW67fxSkJksqEFZehvlrkd5mAYLJ miVKXtS3H29RAr+69p3PUu6ckxcQIiOOCDGpJabWdw50GN6i0f4s9hGB1Hwikxyg/ZwQ yBUg== X-Gm-Message-State: AOAM531mLne776WKQK4I/VQfIBTYCintMDKeRa9Ms2EsOOLXFQgmEMg1 EQd4vRpNTtoEMNAPrTEktJckGDPTStkyJA== X-Received: by 2002:a17:90b:3ec3:: with SMTP id rm3mr18119459pjb.105.1624126507946; Sat, 19 Jun 2021 11:15:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/33] tcg/tci: Use {set,clear}_helper_retaddr Date: Sat, 19 Jun 2021 11:14:45 -0700 Message-Id: <20210619181452.877683-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Wrap guest memory operations for tci like we do for cpu_ld*_data. We cannot actually use the cpu_ldst.h interface without duplicating the memory trace operations performed within, which will already have been expanded into the tcg opcode stream. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index a5670f2109..71689d4a40 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -292,10 +292,9 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, TCGMemOpIdx oi, const void *tb_ptr) { MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); - -#ifdef CONFIG_SOFTMMU uintptr_t ra = (uintptr_t)tb_ptr; +#ifdef CONFIG_SOFTMMU switch (mop) { case MO_UB: return helper_ret_ldub_mmu(env, taddr, oi, ra); @@ -328,6 +327,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, void *haddr = g2h(env_cpu(env), taddr); uint64_t ret; + set_helper_retaddr(ra); switch (mop) { case MO_UB: ret = ldub_p(haddr); @@ -368,6 +368,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, default: g_assert_not_reached(); } + clear_helper_retaddr(); return ret; #endif } @@ -376,10 +377,9 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, TCGMemOpIdx oi, const void *tb_ptr) { MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); - -#ifdef CONFIG_SOFTMMU uintptr_t ra = (uintptr_t)tb_ptr; +#ifdef CONFIG_SOFTMMU switch (mop) { case MO_UB: helper_ret_stb_mmu(env, taddr, val, oi, ra); @@ -408,6 +408,7 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, #else void *haddr = g2h(env_cpu(env), taddr); + set_helper_retaddr(ra); switch (mop) { case MO_UB: stb_p(haddr, val); @@ -433,6 +434,7 @@ static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, default: g_assert_not_reached(); } + clear_helper_retaddr(); #endif } From patchwork Sat Jun 19 18:14:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463917 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1057273jao; Sat, 19 Jun 2021 11:36:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHLdT57/Te6stmc2XVXYaDzDGC3/u8/WF8ohU5qJ0oXm9CiO6mpnn6paqZEBbo1s7Rz3w2 X-Received: by 2002:ac8:5b0e:: with SMTP id m14mr16000244qtw.357.1624127809484; Sat, 19 Jun 2021 11:36:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127809; cv=none; d=google.com; s=arc-20160816; b=kEHwBgxvNXIeOamAeuJJmdCVesScPg5ipkQJdPRZFqbncTKqmNSygi/P61fvw9/EAi J1OmHnVAguAER3ZQDcEU6ykQGt/7j49/Nk9xlScSQGb9lbGSf/3TLWfndM4B41JWol3O tjhhaswv7nJ2gyvIKrosxinZQJ36l7tdCbmJEZw59jcuc9tICp7AktbwawUieSFSWprW TgPaQy/ptnHEBi6+6H2CcXN9WArK3UgWmazye1CqDSmzv+NWcgBUtNLfemMVLURJat0A 0r3YyeGQBtHTH5wCYdZavYL7S0aILhJYR2gLN5fZbzJrIjlgfiI9QOrHyFXOQRnP0ArM FfGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9tP7H9IMjyOF2K2LwMruR2nM1MsyWjxrSP/yzA7RVlo=; b=tuA7ZNpexf//iIGM24qpkvNkczKI9M3W4L1XdeOder/JTWYlIEJJ5dwk6y9hX29RRc jsQHomunm81rm28D8zGkLVPeQAPuGKitwv4XijcwCr6zaAU/hmQ2Z/g3ONss+lS78qVQ j0E6hX3ixzwHjgwsbv59mgKrpQ41GcxBfeMzJ7T1czVbHwRR6aAKWHxrXXxfS/qdrBer /JFzCBBRz2noVN2ol7KcFattjLRKmD1C6unfGEkqlGub6eGWk5lo0Q0c/MPfJUjSLIKe 1+PhaR4GIAVH+/7UOAVfeQ9riTtDJk7ZvzQEr/9lU36fndTdos6yDf3L1uD+D7i3qThG Pa9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="sRj8/bFn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m3si6972769qkd.94.2021.06.19.11.36.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:36:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="sRj8/bFn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufpo-0004Rr-S4 for patch@linaro.org; Sat, 19 Jun 2021 14:36:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV0-0000xL-Tt for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:20 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:37479) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUs-0002NI-IS for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:18 -0400 Received: by mail-pl1-x62d.google.com with SMTP id y21so467595plb.4 for ; Sat, 19 Jun 2021 11:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9tP7H9IMjyOF2K2LwMruR2nM1MsyWjxrSP/yzA7RVlo=; b=sRj8/bFnE5GbRSN8keRbpb64VAbChpQXCeVzHlZAmJGVvVVmw0MVPQubgh74BVxciR NupdFlOBnsJGxsTHkuYlwqjUWopm4nYGYhFOa96I3p03dlIJUgqolLGnNik5MGe0Rfo7 Nrnp094r0r+pS7jJsJWiO8G0u55KKXiSI4ReDvNeYWIv7JIs1CeFgcUyOaRFPomqtR8p Q1DAmReiJ3Sek4t5oUaUfl4ehEDboIekaRNUo6MQbHfzqGwKSfjdR5BYtL0PiMhEIDn1 1cYPODBHcVpmau+GPiTsWbZAp/L+SIsqa14BV/TlRnZERVC1FPJpgF6WA6mnVFTp7uCR jUJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9tP7H9IMjyOF2K2LwMruR2nM1MsyWjxrSP/yzA7RVlo=; b=V5q1FC8u4TfTcF2SDUvkyvB12pCcd+jZLHJgYnb9aYQD6GtSZwVP5SMDB6v3+aKjsU U4lHW3ryOYNai3jq6Q2fWxLHukZN2RB4YPN9XfiiuJmMm9SlZBCaeKCjSew9Rw6HqTon Km+r7BGF46JvHKLu4UMH9qIBtuoe2aW9LHw0kdMJwdzZ8t2/R5yTfn87sKYnNRYAZXYg 1F80DfABtnhJqGANUxD/9DhJ7Ut/mMad35yezg8wOs9AnOVQ8uvR4ZvQIYpDojVcaNmW oQvsKbKQcJpsn2IZLrslj9Vxl8BEBxC/ddbVVqGkh4RoxlpNj2S8UeF+hMCsO+iCmAc3 1KAg== X-Gm-Message-State: AOAM532WX0g/GJtfQ+8LtaYvs9XqVlopynY8lt6E7QPis9y0PfDHOOI+ svtmJ3VJng9WWuOGoc0dVdQrIzNRfOT/hQ== X-Received: by 2002:a17:902:b288:b029:f8:fb4f:f8d3 with SMTP id u8-20020a170902b288b02900f8fb4ff8d3mr10165757plr.25.1624126508594; Sat, 19 Jun 2021 11:15:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/33] tests/tcg: Increase timeout for TCI Date: Sat, 19 Jun 2021 11:14:46 -0700 Message-Id: <20210619181452.877683-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Thomas Huth , =?utf-8?q?Al?= =?utf-8?q?ex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Tested-by: Philippe Mathieu-Daudé Acked-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- configure | 3 +++ tests/tcg/Makefile.target | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/configure b/configure index 262ab71802..55b85e256d 100755 --- a/configure +++ b/configure @@ -5803,6 +5803,9 @@ fi if test "$optreset" = "yes" ; then echo "HAVE_OPTRESET=y" >> $config_host_mak fi +if test "$tcg" = "enabled" -a "$tcg_interpreter" = "true" ; then + echo "CONFIG_TCG_INTERPRETER=y" >> $config_host_mak +fi if test "$fdatasync" = "yes" ; then echo "CONFIG_FDATASYNC=y" >> $config_host_mak fi diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index b29fae4630..63cf1b2573 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -81,8 +81,10 @@ LDFLAGS= QEMU_OPTS= -# If TCG debugging is enabled things are a lot slower -ifeq ($(CONFIG_DEBUG_TCG),y) +# If TCG debugging, or TCI is enabled things are a lot slower +ifneq ($(CONFIG_TCG_INTERPRETER),) +TIMEOUT=90 +else ifneq ($(CONFIG_DEBUG_TCG),) TIMEOUT=60 else TIMEOUT=15 From patchwork Sat Jun 19 18:14:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463920 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1058322jao; Sat, 19 Jun 2021 11:38:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAOvnPKMd/LxNMC19FseE7ZZNW7qZCJgr+q6jxM+xuw3o/hPxkiTueWDtXucd8aw7nkg1k X-Received: by 2002:a37:6002:: with SMTP id u2mr15762529qkb.1.1624127919595; Sat, 19 Jun 2021 11:38:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127919; cv=none; d=google.com; s=arc-20160816; b=zykLSfCbPbJFLQ0bpps1ryUz7uCqsjf9HKYO6xZ2Lyb6YKALCHRHj8kPXlJzNKE9wy i4xMCECioh00gGxm0JqTWxGUo4W34IKn6youWaCsD1QxNnikaUiJoubYjiQQ0NY4b1Cz jh9XaKj1li92YgJlgJm0bEiLP6mawkRV1nwBkmMBW6yyLSId3I5hdmd/KdaKTevdlIH/ SIcDqIejMMPNtpqOaE8DKkqTvlaizXkoZXGtUYxeX6fF+v7iHb/9Rp1kQAk7saEHM4FD 3piCpo6RZO5UDzOZ7q3rf0RSniZkk/q5+oTRPQUVadm1GkGUqCaDl17zWTQ9LRdL1P9m MLVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lTjiPJX2qviAPdJZ7s7MO0oToQmGDYu9Y8UAUdJPSvU=; b=0Z/UEyz0wBcyeo3i1LwXcY3amqZcYIff5z2vz3oFNiOsDQBRYYGs2qC+0wXhgiM4Hv JfvBoEQG13y+8dWTVVtrbQY37vbtZ5vWPCPWLtwBDkJ0eo+Nj9+Q2nNSZHES1Ue2HWiM bAIfEmGAExIoCr/VdMub9v3EmISx5OKGPVBW1feNiytbJOMbAl3gCYbPws2NWpPx6dr9 S4kDQE2JgV9RysuyVKInmJXSzLwJwIzKEgmJW6rl6r273vCn0DvioXZ3mVF2RTZLscUG nhCCZ3ygBf/jJMJdxwcylOL0lD9n5Z6Om8g4c40oNeMbc4LOlgELYvexmS1WhTFvYl+6 YF+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O+92sSYf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q13si6550158qke.110.2021.06.19.11.38.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:38:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O+92sSYf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufra-00016A-On for patch@linaro.org; Sat, 19 Jun 2021 14:38:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV1-0000xS-BU for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:20 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:42936) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUs-0002Nv-RL for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:19 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 13-20020a17090a08cdb029016eed209ca4so7788286pjn.1 for ; Sat, 19 Jun 2021 11:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lTjiPJX2qviAPdJZ7s7MO0oToQmGDYu9Y8UAUdJPSvU=; b=O+92sSYf+w/E0zHqmAYWFH9cCQK+FxS5pw73h96/V18JbFLsP2UqDZg2BDrzsv1zf2 ygoe1wxmuZFzC2FJIwRx6Q/5TlLwQen4xhvnxiOwEEo3T6BtBEyhL02hrFBn+umBR7Gg AQB6z2Ivjj2ETruQzUhgdBys3mBExVeEGbJzs2FdFpiAp/pRL4bsftlSx15YS/pcDacJ f96nKWFd61CipqNEUqGXQQ/usb1qrI4YNY+IidZYJn6FQsWFtFTsawhUsT+1zyqpmRZT uq5J6l4f4F0grMSGKWHj9qdW760008bQhPHuwU0gIWboxbEGEu2QOMKlqeRdw05jHtCp KSwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lTjiPJX2qviAPdJZ7s7MO0oToQmGDYu9Y8UAUdJPSvU=; b=PA31T9ymk6iPuGTecZ4Q91I6lpL2+ND/wz7af/YKW7VJcSmoRQhNhPnLOnwumwr23A VJkPaL+eg3JFR73oHDxO9/bcV7Unew4QLabDC3REzxvfXqAb4QsrHG2OLIRQcftXON3B 7s3OMBwIFyfkGipEmyHHndvcAGoCmEgxNMu2k6eSCHHIi8xU4mqTNlYDkrTOsc6rcKmi WTFYKyLyntgwu/TCwJ5NX1Pdmg7ODZQGG1hsyV48CeB7VO3pLySktINy7cOuD3zLrX+C SruSJBMD5yG35bm7fLBNM53oEPx/VCq8BBFVuoQHlWK+RTwMxUUvKb/pu4sl36if7TKS 3G/w== X-Gm-Message-State: AOAM531hLpPm6y5dhzFze70kr2DUg0zm0ukDoOHH2IcKcSPgku7MQbzt KRVXmhFSmNOpG0YP4yeUAHZpgCMh6lyq6g== X-Received: by 2002:a17:90b:1d89:: with SMTP id pf9mr28188650pjb.26.1624126509149; Sat, 19 Jun 2021 11:15:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 28/33] accel/tcg: Probe the proper permissions for atomic ops Date: Sat, 19 Jun 2021 11:14:47 -0700 Message-Id: <20210619181452.877683-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had a single ATOMIC_MMU_LOOKUP macro that probed for read+write on all atomic ops. This is incorrect for plain atomic load and atomic store. For user-only, we rely on the host page permissions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/390 Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 24 +++++----- accel/tcg/cputlb.c | 95 ++++++++++++++++++++++++++----------- accel/tcg/user-exec.c | 8 ++-- 3 files changed, 83 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 0ff7f913e1..afa8a9daf3 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -74,7 +74,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; DATA_TYPE ret; uint16_t info = trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); @@ -95,7 +95,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP_R; uint16_t info = trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); @@ -110,7 +110,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_W; uint16_t info = trace_mem_build_info(SHIFT, false, 0, true, ATOMIC_MMU_IDX); @@ -125,7 +125,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; DATA_TYPE ret; uint16_t info = trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); @@ -142,7 +142,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; \ DATA_TYPE ret; \ uint16_t info = trace_mem_build_info(SHIFT, false, 0, false, \ ATOMIC_MMU_IDX); \ @@ -176,7 +176,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ - XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ + XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; \ XDATA_TYPE cmp, old, new, val = xval; \ uint16_t info = trace_mem_build_info(SHIFT, false, 0, false, \ ATOMIC_MMU_IDX); \ @@ -221,7 +221,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; DATA_TYPE ret; uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); @@ -242,7 +242,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP_R; uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); @@ -257,7 +257,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_W; uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, true, ATOMIC_MMU_IDX); @@ -274,7 +274,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) { ATOMIC_MMU_DECLS; - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; ABI_TYPE ret; uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); @@ -291,7 +291,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ - DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ + DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; \ DATA_TYPE ret; \ uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, \ false, ATOMIC_MMU_IDX); \ @@ -323,7 +323,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ - XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ + XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP_RW; \ XDATA_TYPE ldo, ldn, old, new, val = xval; \ uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, \ false, ATOMIC_MMU_IDX); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f24348e979..b6d5fc6326 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1742,18 +1742,22 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx, #endif -/* Probe for a read-modify-write atomic operation. Do not allow unaligned - * operations, or io operations to proceed. Return the host address. */ +/* + * Probe for an atomic operation. Do not allow unaligned operations, + * or io operations to proceed. Return the host address. + * + * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. + */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) + TCGMemOpIdx oi, int size, int prot, + uintptr_t retaddr) { size_t mmu_idx = get_mmuidx(oi); - uintptr_t index = tlb_index(env, mmu_idx, addr); - CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = tlb_addr_write(tlbe); MemOp mop = get_memop(oi); int a_bits = get_alignment_bits(mop); - int s_bits = mop & MO_SIZE; + uintptr_t index; + CPUTLBEntry *tlbe; + target_ulong tlb_addr; void *hostaddr; /* Adjust the given return address. */ @@ -1767,7 +1771,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, } /* Enforce qemu required alignment. */ - if (unlikely(addr & ((1 << s_bits) - 1))) { + if (unlikely(addr & (size - 1))) { /* We get here if guest alignment was not requested, or was not enforced by cpu_unaligned_access above. We might widen the access and emulate, but for now @@ -1775,15 +1779,45 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, goto stop_the_world; } + index = tlb_index(env, mmu_idx, addr); + tlbe = tlb_entry(env, mmu_idx, addr); + /* Check TLB entry and enforce page permissions. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_STORE, - mmu_idx, retaddr); - index = tlb_index(env, mmu_idx, addr); - tlbe = tlb_entry(env, mmu_idx, addr); + if (prot & PAGE_WRITE) { + tlb_addr = tlb_addr_write(tlbe); + if (!tlb_hit(tlb_addr, addr)) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(env_cpu(env), addr, size, + MMU_DATA_STORE, mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + tlbe = tlb_entry(env, mmu_idx, addr); + } + tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; + } + + /* Let the guest notice RMW on a write-only page. */ + if ((prot & PAGE_READ) && + unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) { + tlb_fill(env_cpu(env), addr, size, + MMU_DATA_LOAD, mmu_idx, retaddr); + /* + * Since we don't support reads and writes to different addresses, + * and we do have the proper page loaded for write, this shouldn't + * ever return. But just in case, handle via stop-the-world. + */ + goto stop_the_world; + } + } else /* if (prot & PAGE_READ) */ { + tlb_addr = tlbe->addr_read; + if (!tlb_hit(tlb_addr, addr)) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(env_cpu(env), addr, size, + MMU_DATA_LOAD, mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + tlbe = tlb_entry(env, mmu_idx, addr); + } + tlb_addr = tlbe->addr_read & ~TLB_INVALID_MASK; } - tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } /* Notice an IO access or a needs-MMU-lookup access */ @@ -1793,20 +1827,10 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, goto stop_the_world; } - /* Let the guest notice RMW on a write-only page. */ - if (unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) { - tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_LOAD, - mmu_idx, retaddr); - /* Since we don't support reads and writes to different addresses, - and we do have the proper page loaded for write, this shouldn't - ever return. But just in case, handle via stop-the-world. */ - goto stop_the_world; - } - hostaddr = (void *)((uintptr_t)addr + tlbe->addend); if (unlikely(tlb_addr & TLB_NOTDIRTY)) { - notdirty_write(env_cpu(env), addr, 1 << s_bits, + notdirty_write(env_cpu(env), addr, size, &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); } @@ -2669,7 +2693,12 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val) #define ATOMIC_NAME(X) \ HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) #define ATOMIC_MMU_DECLS -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr) +#define ATOMIC_MMU_LOOKUP_RW \ + atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr) +#define ATOMIC_MMU_LOOKUP_R \ + atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr) +#define ATOMIC_MMU_LOOKUP_W \ + atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr) #define ATOMIC_MMU_CLEANUP #define ATOMIC_MMU_IDX get_mmuidx(oi) @@ -2698,10 +2727,18 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val) #undef EXTRA_ARGS #undef ATOMIC_NAME -#undef ATOMIC_MMU_LOOKUP +#undef ATOMIC_MMU_LOOKUP_RW +#undef ATOMIC_MMU_LOOKUP_R +#undef ATOMIC_MMU_LOOKUP_W + #define EXTRA_ARGS , TCGMemOpIdx oi #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC()) +#define ATOMIC_MMU_LOOKUP_RW \ + atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, GETPC()) +#define ATOMIC_MMU_LOOKUP_R \ + atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, GETPC()) +#define ATOMIC_MMU_LOOKUP_W \ + atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, GETPC()) #define DATA_SIZE 1 #include "atomic_template.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fb2d43e6a9..e67b1617b5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1220,7 +1220,9 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, /* Macro to call the above, with local variables from the use context. */ #define ATOMIC_MMU_DECLS do {} while (0) -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) +#define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) +#define ATOMIC_MMU_LOOKUP_R ATOMIC_MMU_LOOKUP_RW +#define ATOMIC_MMU_LOOKUP_W ATOMIC_MMU_LOOKUP_RW #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) #define ATOMIC_MMU_IDX MMU_USER_IDX @@ -1250,12 +1252,12 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #undef EXTRA_ARGS #undef ATOMIC_NAME -#undef ATOMIC_MMU_LOOKUP +#undef ATOMIC_MMU_LOOKUP_RW #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr #define ATOMIC_NAME(X) \ HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) -#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) +#define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) #define DATA_SIZE 16 #include "atomic_template.h" From patchwork Sat Jun 19 18:14:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463912 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1053838jao; Sat, 19 Jun 2021 11:31:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxh48uWJrTVPOVSlQTYnjuPh0Cw1dDwbIpWCgdoXI+m/gKDt1XFoCoBQtqTWNUGSm3uA8Q6 X-Received: by 2002:a67:ef08:: with SMTP id j8mr12197783vsr.15.1624127475374; Sat, 19 Jun 2021 11:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127475; cv=none; d=google.com; s=arc-20160816; b=TaXuPKdfO4SOIWmuQMnBSsuNZufkey0BwOXLe0lbJEgs4b59EnsJ7JOOnow64aeSPI U+Iy+mcyzniRxtRORMFoaIskgRIV+zIJL3oLlclnzENLqFJg/i6zE/OBf3Naz9Ub2TkO Q1GhOz+ICIseLkVnCtNQ0OyOfLqoN4B7LGz2B5LVuMPR2bG3loFlDcX0dl/+HduL8b+f 706B9A3LsIjyNIfmnqqMLhyiEIaZEDY7Z7d25XPINjNhwaWS1SkCX3KzvnfE2/LqI0hq qq3UHUrJpumdBjbqkHd6iI1cPn1M45zPRNhXKphP+b8N72EsqlPN+eU4+/HKJueI2cpJ jotg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vj3iM+4KuA8uBWwj0fsPq6mPv+uS3VpYfRQ2Oo4Z10Q=; b=uzpHP8pbesPcorvKo1GDRtUamggajF+zeoTl5YKaGmUyNu7kpjSCJBsa1hI02UxF1a mXar1FYarxHLspk59EbuZOouzX0C2Wqtt6C3kJsYXpXDqef2A/ZvmZjVheVWCZTbAsfZ bjOoTh6Te5IHKqsTlPATl3/+SUzqHAB4NN2QIDADsd96+4ye/4c/NCnNZaWUNYPwknGx UlVdppV4YyOgvw8Lt92JyGp5rSixEhiFPUc7hmxa5jL/hoSbiNktyzFWcDUu0AqsmFgt PgG1dtadD516ylZWPGTNAvh3knQLdhBZDcpSJWikdpc95qb/cU7LYAIkYq3DcJ6zdFW6 CZnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U8ljitxM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r125si9226717vkf.32.2021.06.19.11.31.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:31:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U8ljitxM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufkQ-0002KL-Bw for patch@linaro.org; Sat, 19 Jun 2021 14:31:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV3-0000yZ-OC for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:22 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:42726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUt-0002O1-5x for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:21 -0400 Received: by mail-pf1-x432.google.com with SMTP id y4so3365584pfi.9 for ; Sat, 19 Jun 2021 11:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vj3iM+4KuA8uBWwj0fsPq6mPv+uS3VpYfRQ2Oo4Z10Q=; b=U8ljitxM36Cf6eaNYCEB3xGms9dNWoFQy0TgDOw/IuCR3JGd3a6Ruyw6jsUAKkDKf0 D9swumuWUy+rktRk8Ejb52hfQ7Uz45YUJLqHxGQ1V9LVe3rZgbhu1toY6mcoDb+CVd8Y O3fp/EOZFeeqF9S4wbLqRQzc2hGVCWLvgopoH4OIV0Wcko8m3mUy2tcsyhqzGvDlZS6X f5055rcm2NdWhDrFpXRDYo7XkZ5as8IrtJ2lHLr08Mp3iWjkZu0FPTo7cLdhIZn3HCxg xRECphqiWY6xG3hxc5PM14qAl1JNjj88KjTlfaUjhDrY4CxRb0Qomn5F1KqrotzC26Wz ubqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vj3iM+4KuA8uBWwj0fsPq6mPv+uS3VpYfRQ2Oo4Z10Q=; b=sGXi93oy9kATe2E1Na7hy1uWQxkBficIDPadt7ZWzBeACkxXRxxZz5ivOzfBpY4Fh5 dHcuTWrzSQ95DoR0iddhDJhiiUUoP2bCgNAW8wsuRKqOPSHNDDrYAhRVNJqy30kwurGW tDCFX4R3hiektcmBuXMsZ2cCnmHSui8iEn/28E6un3VZOEXyTtl/ZTIMv8O/BX5eXn0F eJm4bb+FWZnZOpzz/kPsIprPRNvHg/0OBVsyYCRZUbKOydodS+0LBKWOGYD5Z1WO7IaF auZ8Zy4BSQmNpdlJenKwovinytttQFf5McTN6ByLHFCOVzMpl4ib/EGKPTufeKtpVGwd Gbfg== X-Gm-Message-State: AOAM533lmB1PSDmGJFceGbB4LM9JkvF7IMYKS0HROKODNDaTi6j7Fz3q Iy9G8sY/BcE7SIdnrSMjVEbQ81+tPLByIw== X-Received: by 2002:a63:5118:: with SMTP id f24mr15936118pgb.34.1624126509794; Sat, 19 Jun 2021 11:15:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 29/33] tcg/sparc: Fix temp_allocate_frame vs sparc stack bias Date: Sat, 19 Jun 2021 11:14:48 -0700 Message-Id: <20210619181452.877683-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-stable@nongnu.org, =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We should not be aligning the offset in temp_allocate_frame, because the odd offset produces an aligned address in the end. Instead, pass the logical offset into tcg_set_frame and add the stack bias last. Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 +++------ tcg/sparc/tcg-target.c.inc | 16 ++++++++++------ 2 files changed, 13 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index dd584f3bba..52e858523c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3015,17 +3015,14 @@ static void check_regs(TCGContext *s) static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { -#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64) - /* Sparc64 stack is accessed with offset of 2047 */ - s->current_frame_offset = (s->current_frame_offset + - (tcg_target_long)sizeof(tcg_target_long) - 1) & - ~(sizeof(tcg_target_long) - 1); -#endif if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) > s->frame_end) { tcg_abort(); } ts->mem_offset = s->current_frame_offset; +#if defined(__sparc__) + ts->mem_offset += TCG_TARGET_STACK_BIAS; +#endif ts->mem_base = s->frame_temp; ts->mem_allocated = 1; s->current_frame_offset += sizeof(tcg_target_long); diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index ce39ac2d86..a6ec94a094 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -984,14 +984,18 @@ static void tcg_target_qemu_prologue(TCGContext *s) { int tmp_buf_size, frame_size; - /* The TCG temp buffer is at the top of the frame, immediately - below the frame pointer. */ + /* + * The TCG temp buffer is at the top of the frame, immediately + * below the frame pointer. Use the logical (aligned) offset here; + * the stack bias is applied in temp_allocate_frame(). + */ tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); - tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size, - tmp_buf_size); + tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); - /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is - otherwise the minimal frame usable by callees. */ + /* + * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is + * otherwise the minimal frame usable by callees. + */ frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; frame_size += TCG_TARGET_STACK_ALIGN - 1; From patchwork Sat Jun 19 18:14:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463905 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1051028jao; Sat, 19 Jun 2021 11:26:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz6hkbEQbm5AVACvLmRYFaf/Y8q9FtbMOn2HGmo/Gpt38UZcJzr/9a15ZHV3ug/VUTNkCMZ X-Received: by 2002:a02:6382:: with SMTP id j124mr9461161jac.72.1624127165210; Sat, 19 Jun 2021 11:26:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127165; cv=none; d=google.com; s=arc-20160816; b=Hgrd3pHjLQjgRsenq6TxNI2i9MdZFS/FTAm0g9IB3S4G9ubDITBWzx4D0+K7/JdQ47 bmZ+te0j03gLGdMdiz2YhUk7xhq5NaNeHYYychSOTYUXHppnDT7xhO5ubo4qK7XEKUZp W/AGPcIsMd/EpYh9GEnzeDm7mbsQ2tolcutN6lXdlOZ89fXsle+HGE0ml2jXw95j1+El RSzcf8N5VRLup6yl8TOqe2b02opfELsUnlpcy49Qzds2BE48mL7u2/vOLwG42W9oyyza U2SQkM2X59s/TDiR0qdVJbtcGxdPlEJUpuNNDBHtgcB9wSZpGSe8reDaDzw0AB31XT06 ++9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dmNnvecqX0hYql4TUxzQSGInY+sbhElg47l+/R1+N+A=; b=EmwgRB74KChAH6SUSTyeK6tpFrYmERkBbunxfDRF4CVXgAZMbbgfRBPHCRIkbxnELc 2ecsN+4oY9q6wZpnUO+LSb5Cf6ewYkVliu39EVlprqN/VktaVNj1kIaoNgoVEYpeKdmA RXUROwUglmlSjqR0hgR3632vjWEUZ8Fj+Jf6S0OfqHhVKN828bH6KhFWU7V+UzJV9mb4 BoI8qOXAjVifUGkuaz5IwcrIaSRzSRJnTiQ8glAzkZnlyR9M3JGT1/ZgQmb4tBFBE8qz eIIB01zk0wBcUFn8tzvtBYiGvDXCJ+zFY+LlrjkUMk8aUmlGgV/foo0pHGnNuxLU6YK+ wC2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a29f3HfM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y11si5826214jai.99.2021.06.19.11.26.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:26:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a29f3HfM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1luffO-0007DY-Tf for patch@linaro.org; Sat, 19 Jun 2021 14:26:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV3-0000ya-PC for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:22 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:39850) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUt-0002OD-KC for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:21 -0400 Received: by mail-pj1-x102e.google.com with SMTP id o88-20020a17090a0a61b029016eeb2adf66so9861589pjo.4 for ; Sat, 19 Jun 2021 11:15:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dmNnvecqX0hYql4TUxzQSGInY+sbhElg47l+/R1+N+A=; b=a29f3HfMkuDoIwPpWQ3r0hOMGXeRaovLEy29yOwwYhmRKDC4RSRdv4GbRzVLxkWDfc SiZRBrxmGH6PyHzIeWQ9Nozd/u+dHw5bX+p2nJryDXQOPH+qyyjsRfqbsi6sV2EDWu0R CTJqqAShw6mVf5lPVMzA1TvLqOb+CyH62uZh/pXVUxiCXkaKtBW57Y00qfLI/BAb+VcO EHR8EzAaRcxTcWu/9Ucm76Az/HiV6PtHHSoRFnj+uDkaarOQskrAo+PenJF77lxS63/N cVbwCjn1TXlstvhIQyLbp3uJ6p/uux5l86C5MF3nH6YTgpxhgQvi6HvzepGGTxkTmjgX fnNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dmNnvecqX0hYql4TUxzQSGInY+sbhElg47l+/R1+N+A=; b=LnlKAGF5QE49i8ckGrW5He6Ihyy2A0jQEyZ2qCq5NZxg0D3g8mBDtrQn7k2/gE8LCF dCLwZEyRfhB18nofOx4vY2jFfqKknbWtz7OI/ywV8yA3Z9UfmFJ3vi8QFFFxbUambWJS fODKpz/kuzz+WVeJEV+aNLvfezcB70nnha5SbUFS7FUL166DQN/SKzlLF6kqUL8EPIBZ dBlvd+Yx0TBFXiXnVIeLvNVOl2+pRQGCq02G2wCf6mQRJDfGwX/ZujZCo3QI2oRnkYKs W8TalxQc/+F95mtrHfDR/xcUhcUZb/LHrSzKvrzyE+gBv+zmfrJ3H3V7ztyz3oBiA7Ba gWpw== X-Gm-Message-State: AOAM530gNVMk5L1cypMBUdp8vcev7T4JEjbnCkh3J4b+vy5PP0s+7Uy2 CWlCnD7fjU5VwC8s/EXXbn84I3WJ+/mxYg== X-Received: by 2002:a17:90b:1893:: with SMTP id mn19mr2866548pjb.51.1624126510409; Sat, 19 Jun 2021 11:15:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/33] tcg: Allocate sufficient storage in temp_allocate_frame Date: Sat, 19 Jun 2021 11:14:49 -0700 Message-Id: <20210619181452.877683-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Stefan Weil Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function should have been updated for vector types when they were introduced. Fixes: d2fd745fe8b Resolves: https://gitlab.com/qemu-project/qemu/-/issues/367 Cc: qemu-stable@nongnu.org Tested-by: Stefan Weil Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 52e858523c..47cc66f159 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3015,17 +3015,39 @@ static void check_regs(TCGContext *s) static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) > - s->frame_end) { - tcg_abort(); + size_t size, align; + intptr_t off; + + switch (ts->type) { + case TCG_TYPE_I32: + size = align = 4; + break; + case TCG_TYPE_I64: + case TCG_TYPE_V64: + size = align = 8; + break; + case TCG_TYPE_V128: + size = align = 16; + break; + case TCG_TYPE_V256: + /* Note that we do not require aligned storage for V256. */ + size = 32, align = 16; + break; + default: + g_assert_not_reached(); } - ts->mem_offset = s->current_frame_offset; + + assert(align <= TCG_TARGET_STACK_ALIGN); + off = ROUND_UP(s->current_frame_offset, align); + assert(off + size <= s->frame_end); + s->current_frame_offset = off + size; + + ts->mem_offset = off; #if defined(__sparc__) ts->mem_offset += TCG_TARGET_STACK_BIAS; #endif ts->mem_base = s->frame_temp; ts->mem_allocated = 1; - s->current_frame_offset += sizeof(tcg_target_long); } static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); From patchwork Sat Jun 19 18:14:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463919 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1058281jao; Sat, 19 Jun 2021 11:38:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4xv7+bqTJqdQY32EG4T9HS5cMN3ja9AL6ayq/goSIJio+vsGm6LFiFrIU4Yt5yT3HMfGj X-Received: by 2002:ae9:e512:: with SMTP id w18mr15424370qkf.281.1624127913176; Sat, 19 Jun 2021 11:38:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127913; cv=none; d=google.com; s=arc-20160816; b=WuhP5l12mNHCAFUGG4NvmFRkWqxCUVgNpsqKO6UkufjQVMBSyimIrv2cx/DMXprpbr j6Glr+JrxRxxvn4YYbS3XsgcVJ0lerOBhhoY2dKJ1TTWT4vtEqvt4Piyq5kWZjMw2r+8 REcTIlatyJ17EwWWoC5PFbGRpla6QExTvz7NNBf9ymEH/Xp0jh+zD+Az3Gb2qvwjmb2h jw/2XA0ePEsARdFh9TD1Kvg8yq+pltfGBh+f7Qu3qDgDnKnkoZ1FDotSohNahStQKXgc wnssoVBpSn+OPe7Dnd9abgxc3EVtBqlny13vlEyDcKdok7EzkgET80fQxjOAMhyMV/PW DCOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gsjy1JiJ2x2+FvZgfCJN+MKtpHaomLmEry8fdDvNSE4=; b=Y1ypINmvZFAislYb60QcDYIiErTEE283h3oy3W3dIrEek4w6YDGNOZjnbLbyFj/ZJy T4V6/PR7DrO2BckKRFjfVQ7xmRZOXyFXw9/iYqEWS1rwt4+5ci2xdugiMLtzoxOMBrSU uPhcQ0PEuH4BOXdO8XtZQU3cc92bslzdzxneaZe58TcOxcP70ig97IfCLbfORIfzJ0mB SqTUTBfD1pT63lvsL7mXhtPitcwFTurxS2/cRXR1HrpMO3HmrXWs466YVeiFSmivg3YA +2VpCInBvTtd/AgR/I3ur7K5Hj0VGe4YLrKP5O9GDoJaL5yO6m1IWzHNt50lJqWGMzji Opcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sR3puWTu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bx2si9486885qvb.216.2021.06.19.11.38.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:38:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sR3puWTu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufrU-0008PT-KL for patch@linaro.org; Sat, 19 Jun 2021 14:38:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV3-0000yU-JV for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:22 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:33355) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUu-0002Oz-Hz for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:21 -0400 Received: by mail-pf1-x432.google.com with SMTP id p13so10416254pfw.0 for ; Sat, 19 Jun 2021 11:15:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gsjy1JiJ2x2+FvZgfCJN+MKtpHaomLmEry8fdDvNSE4=; b=sR3puWTumD4O+ggwV5V+dLFrOpB3SOGZqC+D7xqRYlA+y+XR6UFg1HRmcwOaktsyvK YC2BXdGmz8sLil1nN0ojnZcCvGjDUf16nWz7wm5vKg5rIcjrsPYDWhLH7rsSTPE1e3X5 smfh00sAdcIaPlkx7NkNecm5LdFza7SgiuP2NKcEX9gZ+TkS/BdeAxPlmNUsnOaGvbL1 P+jZKacuUz4w9CwdQF99yYkBqjmtDFl+1dta1OntWO19gPQzNG9/fUgtf72j+uWzOB9H /VsTtLubLKWfrsQk0hQLz49pG95fuXc3LzDWnFtD3TQrzGTxo+mKP7PjO7mvJSlQJQgI olow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gsjy1JiJ2x2+FvZgfCJN+MKtpHaomLmEry8fdDvNSE4=; b=Kdw19uhjcZdY+6v0TeOpR03MMKGwK3WDtgJjJqb8Le6o9dG7RwfAbIkOOmqzW4xdqc O+qKhHjDwueLHAjaSFCymjABpUSmnrsMVUl0TyCgwsab8Q2rDeg60Gfix6995HNq6Goz WBFu2qdUnJsSjenGH/8Nb9EC/VdMBeVXO53i+agpBAT+YrkPr9q2zafNYJX6Hl/Xetem eVvSjfTUzzSFF5zhFpLokq3gC37cfWr/ovb9KSf29Dp3r5TpHTwspJBI5YT4CZjmbFAa cLgaMvwksrQ0+AB96JjqLk3bSvhT7d0sFCfWLSUkkrtkgQTGAV52KsCCpX5dgqFu4gE6 gd2Q== X-Gm-Message-State: AOAM531u9OiF/88G4v02agt/ZpTEA8zEKHu8sSm68ViGV0aG+5XxSChW EcQMKEWJrRvKRxWl1fz8TOjHXTfUGVqgKg== X-Received: by 2002:a63:c2:: with SMTP id 185mr16004604pga.18.1624126510999; Sat, 19 Jun 2021 11:15:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 31/33] tcg: Restart when exhausting the stack frame Date: Sat, 19 Jun 2021 11:14:50 -0700 Message-Id: <20210619181452.877683-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Assume that we'll have fewer temps allocated after restarting with a fewer number of instructions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 47cc66f159..fec922fa9e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3039,7 +3039,11 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) assert(align <= TCG_TARGET_STACK_ALIGN); off = ROUND_UP(s->current_frame_offset, align); - assert(off + size <= s->frame_end); + + /* If we've exhausted the stack frame, restart with a smaller TB. */ + if (off + size > s->frame_end) { + tcg_raise_tb_overflow(s); + } s->current_frame_offset = off + size; ts->mem_offset = off; From patchwork Sat Jun 19 18:14:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463921 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1058893jao; Sat, 19 Jun 2021 11:39:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDOJ5JBzRWZuD0mNazoXIXmmL96uKnfrcgvCp9USMl43nUyjRsKvuIKhCsKdyyYA8nC/wy X-Received: by 2002:ac8:5685:: with SMTP id h5mr16145413qta.255.1624127989132; Sat, 19 Jun 2021 11:39:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127989; cv=none; d=google.com; s=arc-20160816; b=eB3Du5ZuT2IB4+go4rnmKnH9A+07M13q8sLesnFD8xys19+EvXe7HWdIvT85lKiYm5 4gzRMbSOPvBV1s+MWA8wJ00bw3jQQvZkDu2z6vISYx8lyxv7erkP/IkG/avswvGOrFgh p8wJSpCehwpQA8Bh7chgdItvSIBDrLQH8Xd8RxX5z6BhAcJd96guyTD4GmhRgFgNHDfH HD1wQqypTl2HUxxligN32mOVgc7/DAH2WLkmJcXTsvEsoFtflJAWd4QA1RDBaB1HjxdR mz/zlN5kC9r5IukCHMpctY9SULrZ0V/kkdHMXwqUkXepLoFxD0nle3ueGC2b13CPP6hl 2IcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3Yk8M8YsYRyZDmwz+XZzO4sGMZKz1Bfw67bchE2cYjA=; b=BnVsg+l4ZlFXTCbhTsh+9qCHy7ieJIXpXjeEEsvrmGk0dSYmMtJ+ip83IU1w4z4EOy cQViDr7RSLdJmanp88yKsq2NBRTBE9GhbqYHE2t6F0CvsB5ndBNuYGmgmW+z/P3pK8Lh 7T6hDLsdcHK2wS/WPsQ5s5tDvxNYS7i/Gb6KSum9iVi1EOW68CMpRxNFDxXLSQdI2rd/ wlxQSKP+1Lie2H1PkQoWAndN/MKrf6o3ZsS5YLy2gBC+s4h0yG9xfiqr/mBwtHDAK3bI YO/Q2ZsKzmbgTVVKeupVF9tY9F1VfhIneUqHiNaUUx/a/hqXm3l6SP9JHE1BopIN3Wod 3K9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HEkI5RLq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e6si9331027qtx.253.2021.06.19.11.39.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:39:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HEkI5RLq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufsi-0002rF-Hs for patch@linaro.org; Sat, 19 Jun 2021 14:39:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV4-0000yl-AB for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:22 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:45623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUu-0002PC-UN for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:22 -0400 Received: by mail-pf1-x429.google.com with SMTP id k6so10328338pfk.12 for ; Sat, 19 Jun 2021 11:15:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Yk8M8YsYRyZDmwz+XZzO4sGMZKz1Bfw67bchE2cYjA=; b=HEkI5RLq7AoN/6woG8GSWz/bEWN++gtcfnbPJtsCEZ04CTtgk9wi9bcpPUdGwIDyXo uGzM5mVjLWgol6V9aw7mAxgEonh2iiYSpp8jwC5dJOjcl1jB6w8EoFlY5QlI6LbCeWbQ eVG0vPxAy0LJLxeJkxbJ9+74V40afajsr4kGnuveFm7J075IIjDYEKq8/M9QaR5MGo/y CLuru4jGoRVzkt3ZVNf+qJexJYDD/0WvGzq4r37Sf83FORiem5ZUL722LP+scmilNOH4 b0j82ESkaNYj60UwMBR3dXD+Wu2DRtPjWMv8SWh63+DTxWqcoOPy3V+rRlGWC8AxGIjh xdYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Yk8M8YsYRyZDmwz+XZzO4sGMZKz1Bfw67bchE2cYjA=; b=Po7Z7q74smLUVBD3piPCZivh4l7HYsulj3Tdd8WiVSXYVPR7V3lp5TsuXhmKgeT+IZ QaBIdQ+Muss2hW/L/VwvC1Su5zbMkHpaG9IjEcQxX7c2jfCx2hqC63+PgjN9x+hQH/7K LGmhakqy27+h4rlExLKeiMU99ZrbnjHAn8Gn8CyHt7jSJp5bq0A8THQXNIqriim7iRzV ISk3LG6i1z3Ei53EcgMINcCqIYOHiytBYza7iAnO8qgKAIulJ/R9bBBU+keCjIDlV1TV 17T4TLKw8PeF9TGEyW7r0UVUzV6tptR8nciThYI6AJPy0MCsn2iOnDmOLsITtb9ctV2S 4rhQ== X-Gm-Message-State: AOAM531+pn5pIrwUVjL4i+bKrIVatCglG4lWm2GoplBpFInqmcH39dYj i+SthVBvJq2gkz/gu+r2qYi+uuR1RrwADg== X-Received: by 2002:a63:1360:: with SMTP id 32mr16052270pgt.233.1624126511660; Sat, 19 Jun 2021 11:15:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/33] tcg: expose TCGCond manipulation routines Date: Sat, 19 Jun 2021 11:14:51 -0700 Message-Id: <20210619181452.877683-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alessandro Di Federico , peter.maydell@linaro.org, Paolo Montesel Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alessandro Di Federico This commit moves into a separate file routines used to manipulate TCGCond. These will be employed by the idef-parser. Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Message-Id: <20210619093713.1845446-2-ale.qemu@rev.ng> Signed-off-by: Richard Henderson --- include/tcg/tcg-cond.h | 101 +++++++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 70 +--------------------------- 2 files changed, 102 insertions(+), 69 deletions(-) create mode 100644 include/tcg/tcg-cond.h -- 2.25.1 diff --git a/include/tcg/tcg-cond.h b/include/tcg/tcg-cond.h new file mode 100644 index 0000000000..2a38a386d4 --- /dev/null +++ b/include/tcg/tcg-cond.h @@ -0,0 +1,101 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TCG_COND_H +#define TCG_COND_H + +/* + * Conditions. Note that these are laid out for easy manipulation by + * the functions below: + * bit 0 is used for inverting; + * bit 1 is signed, + * bit 2 is unsigned, + * bit 3 is used with bit 0 for swapping signed/unsigned. + */ +typedef enum { + /* non-signed */ + TCG_COND_NEVER = 0 | 0 | 0 | 0, + TCG_COND_ALWAYS = 0 | 0 | 0 | 1, + TCG_COND_EQ = 8 | 0 | 0 | 0, + TCG_COND_NE = 8 | 0 | 0 | 1, + /* signed */ + TCG_COND_LT = 0 | 0 | 2 | 0, + TCG_COND_GE = 0 | 0 | 2 | 1, + TCG_COND_LE = 8 | 0 | 2 | 0, + TCG_COND_GT = 8 | 0 | 2 | 1, + /* unsigned */ + TCG_COND_LTU = 0 | 4 | 0 | 0, + TCG_COND_GEU = 0 | 4 | 0 | 1, + TCG_COND_LEU = 8 | 4 | 0 | 0, + TCG_COND_GTU = 8 | 4 | 0 | 1, +} TCGCond; + +/* Invert the sense of the comparison. */ +static inline TCGCond tcg_invert_cond(TCGCond c) +{ + return (TCGCond)(c ^ 1); +} + +/* Swap the operands in a comparison. */ +static inline TCGCond tcg_swap_cond(TCGCond c) +{ + return c & 6 ? (TCGCond)(c ^ 9) : c; +} + +/* Create an "unsigned" version of a "signed" comparison. */ +static inline TCGCond tcg_unsigned_cond(TCGCond c) +{ + return c & 2 ? (TCGCond)(c ^ 6) : c; +} + +/* Create a "signed" version of an "unsigned" comparison. */ +static inline TCGCond tcg_signed_cond(TCGCond c) +{ + return c & 4 ? (TCGCond)(c ^ 6) : c; +} + +/* Must a comparison be considered unsigned? */ +static inline bool is_unsigned_cond(TCGCond c) +{ + return (c & 4) != 0; +} + +/* + * Create a "high" version of a double-word comparison. + * This removes equality from a LTE or GTE comparison. + */ +static inline TCGCond tcg_high_cond(TCGCond c) +{ + switch (c) { + case TCG_COND_GE: + case TCG_COND_LE: + case TCG_COND_GEU: + case TCG_COND_LEU: + return (TCGCond)(c ^ 8); + default: + return c; + } +} + +#endif /* TCG_COND_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 236315b682..41a6c4bfe5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -33,6 +33,7 @@ #include "tcg/tcg-mo.h" #include "tcg-target.h" #include "qemu/int128.h" +#include "tcg/tcg-cond.h" /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 @@ -407,75 +408,6 @@ typedef TCGv_ptr TCGv_env; /* Used to align parameters. See the comment before tcgv_i32_temp. */ #define TCG_CALL_DUMMY_ARG ((TCGArg)0) -/* Conditions. Note that these are laid out for easy manipulation by - the functions below: - bit 0 is used for inverting; - bit 1 is signed, - bit 2 is unsigned, - bit 3 is used with bit 0 for swapping signed/unsigned. */ -typedef enum { - /* non-signed */ - TCG_COND_NEVER = 0 | 0 | 0 | 0, - TCG_COND_ALWAYS = 0 | 0 | 0 | 1, - TCG_COND_EQ = 8 | 0 | 0 | 0, - TCG_COND_NE = 8 | 0 | 0 | 1, - /* signed */ - TCG_COND_LT = 0 | 0 | 2 | 0, - TCG_COND_GE = 0 | 0 | 2 | 1, - TCG_COND_LE = 8 | 0 | 2 | 0, - TCG_COND_GT = 8 | 0 | 2 | 1, - /* unsigned */ - TCG_COND_LTU = 0 | 4 | 0 | 0, - TCG_COND_GEU = 0 | 4 | 0 | 1, - TCG_COND_LEU = 8 | 4 | 0 | 0, - TCG_COND_GTU = 8 | 4 | 0 | 1, -} TCGCond; - -/* Invert the sense of the comparison. */ -static inline TCGCond tcg_invert_cond(TCGCond c) -{ - return (TCGCond)(c ^ 1); -} - -/* Swap the operands in a comparison. */ -static inline TCGCond tcg_swap_cond(TCGCond c) -{ - return c & 6 ? (TCGCond)(c ^ 9) : c; -} - -/* Create an "unsigned" version of a "signed" comparison. */ -static inline TCGCond tcg_unsigned_cond(TCGCond c) -{ - return c & 2 ? (TCGCond)(c ^ 6) : c; -} - -/* Create a "signed" version of an "unsigned" comparison. */ -static inline TCGCond tcg_signed_cond(TCGCond c) -{ - return c & 4 ? (TCGCond)(c ^ 6) : c; -} - -/* Must a comparison be considered unsigned? */ -static inline bool is_unsigned_cond(TCGCond c) -{ - return (c & 4) != 0; -} - -/* Create a "high" version of a double-word comparison. - This removes equality from a LTE or GTE comparison. */ -static inline TCGCond tcg_high_cond(TCGCond c) -{ - switch (c) { - case TCG_COND_GE: - case TCG_COND_LE: - case TCG_COND_GEU: - case TCG_COND_LEU: - return (TCGCond)(c ^ 8); - default: - return c; - } -} - typedef enum TCGTempVal { TEMP_VAL_DEAD, TEMP_VAL_REG, From patchwork Sat Jun 19 18:14:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 463915 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp1056406jao; Sat, 19 Jun 2021 11:35:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJWdUaUtrZQ/cpGBvPRDXaMOYCjHc055WHz/PbhnQESxKMSPkVA9DhmCxWXwjb0qMM7cxt X-Received: by 2002:a67:fa84:: with SMTP id f4mr12152368vsq.59.1624127713664; Sat, 19 Jun 2021 11:35:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624127713; cv=none; d=google.com; s=arc-20160816; b=j/wpR5lFSy7v1+i9eCFQO8KNM/0mAE45+S//ANK3xIv86dxHDt30J16Q6kYymSiqYh YkjmBbZzbpwuBaAm3yPSRy5uH1R0+bxmLCgdpvQsuZnAtQtiRhF2AoNpVKzrFpqP2Xll ZyyrzzvnvlZz54HwXVBRbiFUqa9HDmsTLMCnlC6JR1OH2Hh3JQSWvOqNLVJjYAy1QGQT o49ldmy6q9wEeqtM45fXxDHWfzSyU/JEFKTrd7XREaIfcaXCX8pCmG40Y1N2b0oTj5yH YdjPrnC/lvCFcGP/RgSvq5/XiP9UZk2p3v/N+MIZ7urH6SEm/miGnF+qE8IXzngqyUcm lH9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jM82TdfgD8ZhKwShzjucUE8ayynZiFP9Xnq8vxxePe0=; b=Gct7ZVxyCx2qegKSkspbs8zFsecxYevOocGCOzZx7b5zPvrGlWOR2yCpVKI17EkzRM XXIRne+8xJvtgeiG6ooCCknNv31nXlRwTe/ZXWFgxInQRXYFrmyBGgL7F2IboOSmxJQP lPpcvBl0n5LYXlrFaINBKpgi17P9/vgZ4+ncE+kUp3bhr36oQKvbxK2cuPTwcIJsFtOV d3BE3bempz0iWK6mQkgXhW9sU0ECCh3XVqZUrzJfphpVsoxPc6OUwt6Pb9u/n5lH0skp 3hgllgVqAGWcSdTjM7AiK7/cYSwV3ud3DqxO5SJmr9E9uokNZnhjZSRttaTgnysIot3P 807Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UIOuRIf5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t12si1218908uar.174.2021.06.19.11.35.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 Jun 2021 11:35:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UIOuRIf5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lufoG-00086V-Qx for patch@linaro.org; Sat, 19 Jun 2021 14:35:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lufV4-000103-NC for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:23 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:44911) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lufUw-0002PJ-4D for qemu-devel@nongnu.org; Sat, 19 Jun 2021 14:15:22 -0400 Received: by mail-pl1-x634.google.com with SMTP id x22so4790017pll.11 for ; Sat, 19 Jun 2021 11:15:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jM82TdfgD8ZhKwShzjucUE8ayynZiFP9Xnq8vxxePe0=; b=UIOuRIf526KN79GvU4inBWOgtFYJ14PwuzaLwrZWucLpF2bx0axEWo/6kVEFHNwEIF ctgydSJLFj1O0IDv0sIfbQRdx4m7eez4sHL9oFaN9BLFyP7mv8th+g0xXCDCmrarswvi Az5awNAeXtIwADlFi6l8p+M3T9OkV8l246WszZwyXyUsHN5Y2Xto87KnAkxz0Q2nDnKj NNiatBwSZcZOtrgPQnzfR3UuW5ye/1LNVnkgAbPFTbFdu8eH0o2o6oTKgpy+rMIIJ283 cVr5d/L0uhAzWtEh62Hd3iTlaOZhEADdNHygdomMDpIVNAtifdqpnlaPoRxzrZEqkLA0 KCfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jM82TdfgD8ZhKwShzjucUE8ayynZiFP9Xnq8vxxePe0=; b=YbCu/RLlpRFCV4e4G+BBz0HAz2p3KXbUoOpyQ53c3K6WJd1Ytq9OxWvw4oYhFwPbs4 5QUwchNZkccEhle2x3qSFYkdJ7/u9YH7Q77WhGHYrwjNSKdaHbj3q5DvirYW6VbEJi0r D/ZWP4p6gj7Mysm1U6a8gu7xeYRqe0YGknqMXNRu+qPcLLyxRM0jcQpIB41M0P77W0Y3 AHiWI63QrbdsI5LQI3SIh44n1ya5L6tLcBUizX1QxfVMEGSiy3jwK/lhteyCvep6pOLX u+TeYgJWxYlCqT+zxtaXFa0MiZsIRe7mVFEhzflax/OgWE1W/v0aCKeUofnNf17181ao LD3w== X-Gm-Message-State: AOAM530SPBquk90BnthTTBzn63PO0PwwAU7mVygbPH+Rm4/By65kl2qX YBdT6rZWRQAExXy71B34vWjP2oiyDe267Q== X-Received: by 2002:a17:90a:6001:: with SMTP id y1mr27477352pji.5.1624126512266; Sat, 19 Jun 2021 11:15:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id k35sm12059113pgi.21.2021.06.19.11.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 11:15:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 33/33] util/oslib-win32: Fix fatal assertion in qemu_try_memalign Date: Sat, 19 Jun 2021 11:14:52 -0700 Message-Id: <20210619181452.877683-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org> References: <20210619181452.877683-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Stefan Weil Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Stefan Weil The function is called with alignment == 0 which caused an assertion. Use the code from oslib-posix.c to fix that regression. Fixes: ed6f53f9ca9 Signed-off-by: Stefan Weil Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210611105846.347954-1-sw@weilnetz.de> Signed-off-by: Richard Henderson --- util/oslib-win32.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/util/oslib-win32.c b/util/oslib-win32.c index ee3a3692d8..af559ef339 100644 --- a/util/oslib-win32.c +++ b/util/oslib-win32.c @@ -58,7 +58,11 @@ void *qemu_try_memalign(size_t alignment, size_t size) void *ptr; g_assert(size != 0); - g_assert(is_power_of_2(alignment)); + if (alignment < sizeof(void *)) { + alignment = sizeof(void *); + } else { + g_assert(is_power_of_2(alignment)); + } ptr = _aligned_malloc(size, alignment); trace_qemu_memalign(alignment, size, ptr); return ptr;