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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 003/256] cl8k: add Kconfig Date: Thu, 17 Jun 2021 15:58:10 +0000 Message-Id: <20210617160223.160998-4-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:35 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b4784f96-6d5f-4b88-8f93-08d931a95322 X-MS-TrafficTypeDiagnostic: AM9P192MB1412: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yCNXvKtxKW4EXiu8Je7cRfAdQiBgGeglwoW4mGaqlfn/fCQC9HhuhoqAqIwFIqVf3aHXCyy8nF32D34beESjnEl9j7uAwXiAHheq/yX4JEQlp4yq6QG5Gx7D2gegAwcjqywv/ofZU6jjBgykIMCzTQnsTllWhzhqgie5Qc6/cPY1V2zZmLoqBVQCoBBbetDgNrjgV228Q64Sje3gAFJ5A05EYBfUs603GwsdQQCkshzYbUXOqWAmBpDYCzKrDprZrEIo20rcMdBWdXaL0GsiGGWpfcwIx5MYUbmQUjUXkWFKT/TMejGkN1bpv/4DPE+k0+v2fT/GEA+A6ApVgJyhBgsY2QhYpT44PU6pTT3ELfIXiN4FADDeuichxJtIbKEwWL5O3WBhXjVcMgieh56TVnkvgVZ0vqegS4Cd37doejKxXXg+xHZjHNhKjKMBzKy/e/kDzLh9uouw1hLsxL2+oFVvP4WQmxl0jGLtilNCAOC+ei7opkTyTLa37p06g5avY4oJdEJ14+OtNL19k2Lb9s30rCUEfRKURVKMG7iHACsCwwhsH79zps7kolpMdCb3O063EbVHv/ivp7qowN87n5MuTRGhDfRJORlK3XegRy2+sG/kDxwK70n0sbd8HZ4VzU34Ytx3kK1GJsprpsI5f7H1xwJcVUGtCX7mGP+h4bTyagUKzDIxdp8uiZVmu5NS2gagUuF6xcJ4acq7/RMyOw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(136003)(376002)(39840400004)(396003)(38350700002)(9686003)(16526019)(38100700002)(6512007)(478600001)(36756003)(6506007)(52116002)(55236004)(6486002)(186003)(66556008)(2906002)(8936002)(2616005)(26005)(66946007)(956004)(66476007)(86362001)(83380400001)(107886003)(5660300002)(1076003)(6666004)(4326008)(316002)(8676002)(6916009)(54906003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6vZV2ESeM9/8MWPBZfhn+Vkd/4QFcJ0MJG1ZHGmE/+338F/RAxkd8K7XIY14cchqZZm9UKgMiC0FDU5wfxDJ2/hZbA+LVequ2mNesDJWU2UKKdya6nPpUrw4Mo7m9dNdo/3r4clfSW3Db1R0QK8idg0A5f8Q9ZCZM/+bH2JTGtshJcuX+XlyUubYTkgWTev10p1p2lAjgzBuU9xj/++bcT+PHxYxyYoT9xzZc/Ie77ywLo5Q4RUGswjC7c5HtxS8w/Dzw28SkhSV+W4RMV9qmXA7QLjErq5KRto9zkHkEkRyGJl5rIfb/2JbAB2xbeNy81LLBIV4lvWdOauUgNmTjQQBi9bVpteRnTChU/nfa385jGyuoxaYN7MkWlDFrkjWujo5XQFxvqwF4LzOlKz+vvJE8yGMKOmyQZUuttB3s+bTNwwd5eBCoseUDpZN9PkDQCJlodkKou4nVybk5Kw/uy+Bd2n1ru7+hGmPNHaStqgyYJaLVy+twAXTMYHBevhA0FBluMG16iahOgx/xFmHnVpEL/rlCX2qL/Z3kurZS8Q2aIs72XBbffYsN9g1neRGVuLAVkj4w1bMd3Eu7ZQyJ7muOA4Q4eJZ3fKETuZxHSuFQ8yG/Fn7y5ZIWsFz9niqLoiK9XxMBCiI17hZr395iBhVVOyedGimkN02OLwKd3t90BnM3ax40y8g7vjhzKjw5xrMv7kAnkiiM2hr/pADmxqPmKMdSntGRrl4JxxrVWb/yYA+qVGxBNL6MBMJn21sc8ncjQmV5UWXW7MJgTuDgNgkAeyCm/W+exnn/uDmBeYUPK4KbVQX99hjHT9RJgsgIMMPY8tIjk3wTNIOqbKpeevEqh50KMQTrEcvkjIB+7VJ/YuE7ynaZRmAC5H5xr+pGrWCAQddSNTpPm24frLS4KY3KNzKOIg7qiaOsKDzyszbP09hBhphAo1cBwOsOfgDZMARYUGVj7+TQ0sksCmC6HtTKS43etqnPo4p5Vv6JLZmwfSaL/E2wbmpcrrKTLxjjVVc9kq7PbkBvfYtRj7EHn9QTh0Zzp04TBwSgG/M8TI7jAZCBfv/My3H+UPTcINCL4S3hOnLrN6AdUa+q4derR3T2rAK/FETF1NptPQPP7s6WHuTt6zIw9EAz6LfJkKUsGxrQ/hUTN9/RaYUs97/cANrk0wYl4+P8ugwq/sXSdsjQnmgS04xI6VAGj5NEvOvjNCh+yrmwVttO9155i99HUx2wqvSKZCrC+eOeU+YggA4v6DM2vy4p9o+Aj3S6cKgeCRVjcAHpg4gy7h1P0T3+lC+w42cRowQ/u+3SSflcY6q3SrpmP/pwFGtGrIC7yNO X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: b4784f96-6d5f-4b88-8f93-08d931a95322 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:36.5485 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YmdE3JGuezvdqhhKzz+5ZcI/LemqTKC3P2QtB977uWFCkEXGHA3tRLIx76Xp6J32ZKw5kEXaQnWsrXSkLtqJPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1412 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/Kconfig -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/Kconfig b/drivers/net/wireless/celeno/cl8k/Kconfig new file mode 100644 index 000000000000..452c647320de --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: MIT +config CL8K + tristate "Celeno CL8K WLAN support" + depends on m + depends on MAC80211 + select WANT_DEV_COREDUMP + help + This option enables support for Celeno CL8K WLAN. + Select M (recommended), if you have a wireless module. + +config CL8K_PCI + bool "PCI devices support" + depends on CL8K + default y + help + Say Y if you revision with PCIe-based interface. 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/afe.c | 737 +++++++++++++++++++++++++ 1 file changed, 737 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/afe.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/afe.c b/drivers/net/wireless/celeno/cl8k/afe.c new file mode 100644 index 000000000000..ce846396ac0f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/afe.c @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "afe.h" +#include "reg/reg_ricu.h" +#include "reg/reg_io_ctrl.h" +#include "fem.h" + +/* + * The configuration below supports: + * CL8080: 4 + 4 (chains 0-3 @ TCV0 and chains 0-3 @ TCV1) + * CL8060: 4 + 2 (chains 0-3 @ TCV0 and chains 2-3 @ TCV1) + * CL8064: 4 + 2 (chains 0-3 @ TCV0 and chains 2-3 @ TCV1) + * CL8040: 2 + 2 (chains 0-1 @ TCV0 and chains 2-3 @ TCV1) + * CL8046: 4 + 0 (chains 0-3 @ TCV0) + */ + +#define RICU_AFE_CTL_9_EN_DAC_REF_CL808X \ + (RICU_AFE_CTL_9_EN_DAC_REF_0_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_1_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_2_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_3_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_4_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_5_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_6_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_7_BIT) + +#define RICU_AFE_CTL_9_EN_DAC_REF_CL806X \ + (RICU_AFE_CTL_9_EN_DAC_REF_0_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_1_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_2_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_3_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_4_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_5_BIT) + +#define RICU_AFE_CTL_9_EN_DAC_REF_CL8046 \ + (RICU_AFE_CTL_9_EN_DAC_REF_0_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_1_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_2_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_3_BIT) + +#define RICU_AFE_CTL_9_EN_DAC_REF_CL8040 \ + (RICU_AFE_CTL_9_EN_DAC_REF_0_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_1_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_4_BIT | \ + RICU_AFE_CTL_9_EN_DAC_REF_5_BIT) + +#define RICU_AFE_CTL_8_EN_BGR_CL808X \ + (RICU_AFE_CTL_8_EN_BGR_0_BIT | \ + RICU_AFE_CTL_8_EN_BGR_1_BIT | \ + RICU_AFE_CTL_8_EN_BGR_2_BIT | \ + RICU_AFE_CTL_8_EN_BGR_3_BIT | \ + RICU_AFE_CTL_8_EN_BGR_4_BIT | \ + RICU_AFE_CTL_8_EN_BGR_5_BIT | \ + RICU_AFE_CTL_8_EN_BGR_6_BIT | \ + RICU_AFE_CTL_8_EN_BGR_7_BIT) + +#define RICU_AFE_CTL_8_EN_BGR_CL806X \ + (RICU_AFE_CTL_8_EN_BGR_0_BIT | \ + RICU_AFE_CTL_8_EN_BGR_1_BIT | \ + RICU_AFE_CTL_8_EN_BGR_2_BIT | \ + RICU_AFE_CTL_8_EN_BGR_3_BIT | \ + RICU_AFE_CTL_8_EN_BGR_4_BIT | \ + RICU_AFE_CTL_8_EN_BGR_5_BIT) + +#define RICU_AFE_CTL_8_EN_BGR_CL8046 \ + (RICU_AFE_CTL_8_EN_BGR_0_BIT | \ + RICU_AFE_CTL_8_EN_BGR_1_BIT | \ + RICU_AFE_CTL_8_EN_BGR_2_BIT | \ + RICU_AFE_CTL_8_EN_BGR_3_BIT) + +#define RICU_AFE_CTL_8_EN_BGR_CL8040 \ + (RICU_AFE_CTL_8_EN_BGR_0_BIT | \ + RICU_AFE_CTL_8_EN_BGR_1_BIT | \ + RICU_AFE_CTL_8_EN_BGR_4_BIT | \ + RICU_AFE_CTL_8_EN_BGR_5_BIT) + +#define RICU_AFE_CTL_8_EN_REF_CL808X \ + (RICU_AFE_CTL_8_EN_REF_0_BIT | \ + RICU_AFE_CTL_8_EN_REF_1_BIT | \ + RICU_AFE_CTL_8_EN_REF_2_BIT | \ + RICU_AFE_CTL_8_EN_REF_3_BIT | \ + RICU_AFE_CTL_8_EN_REF_4_BIT | \ + RICU_AFE_CTL_8_EN_REF_5_BIT | \ + RICU_AFE_CTL_8_EN_REF_6_BIT | \ + RICU_AFE_CTL_8_EN_REF_7_BIT) + +#define RICU_AFE_CTL_8_EN_REF_CL806X \ + (RICU_AFE_CTL_8_EN_REF_0_BIT | \ + RICU_AFE_CTL_8_EN_REF_1_BIT | \ + RICU_AFE_CTL_8_EN_REF_2_BIT | \ + RICU_AFE_CTL_8_EN_REF_3_BIT | \ + RICU_AFE_CTL_8_EN_REF_4_BIT | \ + RICU_AFE_CTL_8_EN_REF_5_BIT) + +#define RICU_AFE_CTL_8_EN_REF_CL8046 \ + (RICU_AFE_CTL_8_EN_REF_0_BIT | \ + RICU_AFE_CTL_8_EN_REF_1_BIT | \ + RICU_AFE_CTL_8_EN_REF_2_BIT | \ + RICU_AFE_CTL_8_EN_REF_3_BIT) + +#define RICU_AFE_CTL_8_EN_REF_CL8040 \ + (RICU_AFE_CTL_8_EN_REF_0_BIT | \ + RICU_AFE_CTL_8_EN_REF_1_BIT | \ + RICU_AFE_CTL_8_EN_REF_4_BIT | \ + RICU_AFE_CTL_8_EN_REF_5_BIT) + +#define RICU_AFE_CTRL_37_PHY_0_DAC_CL808X \ + (RICU_AFE_CTRL_37_PHY_0_EN_DAC_0_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_1_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_2_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_3_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_4_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_5_BIT) + +#define RICU_AFE_CTRL_37_PHY_0_DAC_CL806X \ + (RICU_AFE_CTRL_37_PHY_0_EN_DAC_0_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_1_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_2_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_3_BIT) + +#define RICU_AFE_CTRL_37_PHY_0_DAC_CL8046 \ + (RICU_AFE_CTRL_37_PHY_0_EN_DAC_0_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_1_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_2_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_3_BIT) + +#define RICU_AFE_CTRL_37_PHY_0_DAC_CL8040 \ + (RICU_AFE_CTRL_37_PHY_0_EN_DAC_0_BIT | \ + RICU_AFE_CTRL_37_PHY_0_EN_DAC_1_BIT) + +#define RICU_AFE_CTRL_37_PHY_1_DAC_CL808X \ + (RICU_AFE_CTRL_37_PHY_1_EN_DAC_0_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_1_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_2_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_3_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_4_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_5_BIT) + +#define RICU_AFE_CTRL_37_PHY_1_DAC_CL806X \ + (RICU_AFE_CTRL_37_PHY_1_EN_DAC_2_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_3_BIT) + +#define RICU_AFE_CTRL_37_PHY_1_DAC_CL804X \ + (RICU_AFE_CTRL_37_PHY_1_EN_DAC_2_BIT | \ + RICU_AFE_CTRL_37_PHY_1_EN_DAC_3_BIT) + +static void cl_afe_enable(struct cl_chip *chip) +{ + u32 regval; + + /* Enable PLL LDO */ + ricu_afe_ctl_1_en_pll_ldo_setf(chip, 1); + + /* Enable DAC BGR & reference */ + regval = ricu_afe_ctl_9_get(chip); + if (cl_chip_is_8ant(chip)) + regval |= RICU_AFE_CTL_9_EN_DAC_REF_CL808X; + else if (cl_chip_is_6ant(chip)) + regval |= RICU_AFE_CTL_9_EN_DAC_REF_CL806X; + else if (cl_chip_is_6g(chip)) + regval |= RICU_AFE_CTL_9_EN_DAC_REF_CL8046; + else + regval |= RICU_AFE_CTL_9_EN_DAC_REF_CL8040; + ricu_afe_ctl_9_set(chip, regval); + + /* Enable ADC BGR & Reference */ + regval = ricu_afe_ctl_8_get(chip); + if (cl_chip_is_8ant(chip)) { + regval |= RICU_AFE_CTL_8_EN_BGR_CL808X; + regval |= RICU_AFE_CTL_8_EN_REF_CL808X; + } else if (cl_chip_is_6ant(chip)) { + regval |= RICU_AFE_CTL_8_EN_BGR_CL806X; + regval |= RICU_AFE_CTL_8_EN_REF_CL806X; + } else if (cl_chip_is_6g(chip)) { + regval |= RICU_AFE_CTL_8_EN_BGR_CL8046; + regval |= RICU_AFE_CTL_8_EN_REF_CL8046; + } else { + regval |= RICU_AFE_CTL_8_EN_BGR_CL8040; + regval |= RICU_AFE_CTL_8_EN_REF_CL8040; + } + ricu_afe_ctl_8_set(chip, regval); + + /* Enable Embedded LDO */ + regval = ricu_afe_ctrl_36_phy_0_get(chip); + regval |= (RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_IR_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDI_BIT); + ricu_afe_ctrl_36_phy_0_set(chip, regval); + + regval = ricu_afe_ctrl_36_phy_1_get(chip); + regval |= (RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_IR_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDI_BIT); + ricu_afe_ctrl_36_phy_1_set(chip, regval); + + /* Wait 2 us PLL LDO settling time */ + udelay(2); + + /* Enable the LC oscillator of the LCPLL */ + ricu_afe_ctl_2_lock_con_rev_lc_setf(chip, 1); + /* Enable the LC PBIAS of the LCPLL */ + ricu_afe_ctl_0_pbias_ctrl_en_lc_setf(chip, 1); + + /* Wait 1 us */ + udelay(1); + + /* Power up control for LCPLL */ + ricu_afe_ctl_1_resetb_lc_setf(chip, 1); + + /* Wait 1 us */ + udelay(1); + + /* Enable DAC & ADC cores */ + if (cl_chip_is_8ant(chip)) + ricu_afe_ctrl_37_phy_0_set(chip, RICU_AFE_CTRL_37_PHY_0_DAC_CL808X); + else if (cl_chip_is_6ant(chip)) + ricu_afe_ctrl_37_phy_0_set(chip, RICU_AFE_CTRL_37_PHY_0_DAC_CL806X); + else if (cl_chip_is_6g(chip)) + ricu_afe_ctrl_37_phy_0_set(chip, RICU_AFE_CTRL_37_PHY_0_DAC_CL8046); + else + ricu_afe_ctrl_37_phy_0_set(chip, RICU_AFE_CTRL_37_PHY_0_DAC_CL8040); + + if (cl_chip_is_8ant(chip)) + ricu_afe_ctrl_37_phy_1_set(chip, RICU_AFE_CTRL_37_PHY_1_DAC_CL808X); + else if (cl_chip_is_6ant(chip)) + ricu_afe_ctrl_37_phy_1_set(chip, RICU_AFE_CTRL_37_PHY_1_DAC_CL806X); + else + ricu_afe_ctrl_37_phy_1_set(chip, RICU_AFE_CTRL_37_PHY_1_DAC_CL804X); + + /* Enable DAC & ADC cores */ + regval = ricu_afe_ctrl_36_phy_0_get(chip); + regval |= (RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCI_BIT); + ricu_afe_ctrl_36_phy_0_set(chip, regval); + + regval = ricu_afe_ctrl_36_phy_1_get(chip); + regval |= (RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCI_BIT); + ricu_afe_ctrl_36_phy_1_set(chip, regval); + + /* Wait 2us */ + udelay(2); + + /* Enable Main & 2nd CDB clock generators */ + ricu_afe_ctl_0_cdb_clk_resetb_setf(chip, 1); +} + +static void cl_afe_disable(struct cl_chip *chip) +{ + u32 regval; + + /* Power down control for LCPLL */ + ricu_afe_ctl_1_resetb_lc_setf(chip, 0); + /* Disable PLL LDO */ + ricu_afe_ctl_1_en_pll_ldo_setf(chip, 0); + /* Disable the LC oscillator of the LCPLL */ + ricu_afe_ctl_2_lock_con_rev_lc_setf(chip, 0); + /* Disable the LC PBIAS of the LCPLL */ + ricu_afe_ctl_0_pbias_ctrl_en_lc_setf(chip, 0); + + /* Disable DAC BGR & reference */ + regval = ricu_afe_ctl_9_get(chip); + if (cl_chip_is_8ant(chip)) + regval &= ~RICU_AFE_CTL_9_EN_DAC_REF_CL808X; + else if (cl_chip_is_6ant(chip)) + regval &= ~RICU_AFE_CTL_9_EN_DAC_REF_CL806X; + else if (cl_chip_is_6g(chip)) + regval &= ~RICU_AFE_CTL_9_EN_DAC_REF_CL8046; + else + regval &= ~RICU_AFE_CTL_9_EN_DAC_REF_CL8040; + ricu_afe_ctl_9_set(chip, regval); + + /* Disable ADC BGR & Reference */ + regval = ricu_afe_ctl_8_get(chip); + if (cl_chip_is_8ant(chip)) { + regval &= ~RICU_AFE_CTL_8_EN_BGR_CL808X; + regval &= ~RICU_AFE_CTL_8_EN_REF_CL808X; + } else if (cl_chip_is_6ant(chip)) { + regval &= ~RICU_AFE_CTL_8_EN_BGR_CL806X; + regval &= ~RICU_AFE_CTL_8_EN_REF_CL806X; + } else if (cl_chip_is_6g(chip)) { + regval &= ~RICU_AFE_CTL_8_EN_BGR_CL8046; + regval &= ~RICU_AFE_CTL_8_EN_REF_CL8046; + } else { + regval &= ~RICU_AFE_CTL_8_EN_BGR_CL8040; + regval &= ~RICU_AFE_CTL_8_EN_REF_CL8040; + } + ricu_afe_ctl_8_set(chip, regval); + + /* Disable Embedded LDO */ + regval = ricu_afe_ctrl_36_phy_0_get(chip); + regval &= ~(RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_IR_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDI_BIT); + ricu_afe_ctrl_36_phy_0_set(chip, regval); + + regval = ricu_afe_ctrl_36_phy_1_get(chip); + regval &= ~(RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_IR_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDI_BIT); + ricu_afe_ctrl_36_phy_1_set(chip, regval); + + /* Disable DAC & ADC cores */ + ricu_afe_ctrl_37_phy_0_set(chip, 0); + ricu_afe_ctrl_37_phy_1_set(chip, 0); + + /* Disable DAC & ADC cores */ + regval = ricu_afe_ctrl_36_phy_0_get(chip); + regval &= ~(RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCI_BIT); + ricu_afe_ctrl_36_phy_0_set(chip, regval); + + regval = ricu_afe_ctrl_36_phy_1_get(chip); + regval &= ~(RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCI_BIT); + ricu_afe_ctrl_36_phy_1_set(chip, regval); + + /* Disable Main & 2nd CDB clock generators */ + ricu_afe_ctl_0_cdb_clk_resetb_setf(chip, 0); +} + +static void cl_io_ctrl_config(struct cl_chip *chip) +{ + io_ctrl_fastwr_0_set(chip, 0x2338); + io_ctrl_fastwr_1_set(chip, 0x2338); + io_ctrl_fastwr_2_set(chip, 0x2338); + io_ctrl_fastwr_3_set(chip, 0x2338); + io_ctrl_fastwr_4_set(chip, 0x2338); + io_ctrl_fastwr_5_set(chip, 0x2338); + io_ctrl_fastwr_6_set(chip, 0x2338); + io_ctrl_fastwr_7_set(chip, 0x2338); + io_ctrl_fwr_en_1_set(chip, 0x338); + io_ctrl_spiclk_set(chip, 0x308); +} + +static int cl_adc_sampling_cfg_tcv0(struct cl_chip *chip, u16 adc_sampling_clk) +{ + switch (adc_sampling_clk) { + case 40: + ricu_afe_ctrl_43_freq_sel_setf(chip, 0x0); + /* Configure ADC sampling for primary chains */ + ricu_afe_ctl_25_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctl_26_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctl_27_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctl_33_pack(chip, 0x1, 0x3D, 0x3D); + break; + case 80: + ricu_afe_ctrl_43_freq_sel_setf(chip, 0x1); + /* Configure ADC sampling for primary chains */ + ricu_afe_ctl_25_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctl_26_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctl_27_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctl_33_pack(chip, 0x1, 0x3D, 0x3D); + break; + case 160: + ricu_afe_ctrl_43_freq_sel_setf(chip, 0x2); + /* Configure ADC sampling for primary chains */ + ricu_afe_ctl_25_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctl_26_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctl_27_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctl_33_pack(chip, 0x0, 0x7, 0x7); + break; + case 320: + ricu_afe_ctrl_43_freq_sel_setf(chip, 0x3); + /* Configure ADC sampling for primary chains */ + ricu_afe_ctl_25_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctl_26_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctl_27_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctl_33_pack(chip, 0x0, 0x7, 0x7); + break; + default: + CL_DBG_ERROR_CHIP(chip, "Invalid adc_sampling_clk %u\n", adc_sampling_clk); + return -1; + } + + return 0; +} + +static int cl_adc_sampling_cfg_tcv1(struct cl_chip *chip, u32 adc_sampling_clk) +{ + switch (adc_sampling_clk) { + case 40: + ricu_afe_ctrl_44_cdb_freq_sel_setf(chip, 0x0); + /* Configure ADC sampling for secondary chains */ + ricu_afe_ctrl_39_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctrl_40_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctrl_41_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctrl_42_pack(chip, 0x1, 0x3D, 0x3D); + break; + case 80: + ricu_afe_ctrl_44_cdb_freq_sel_setf(chip, 0x1); + /* Configure ADC sampling for secondary chains */ + ricu_afe_ctrl_39_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctrl_40_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctrl_41_pack(chip, 0x1, 0x3D, 0x3D); + ricu_afe_ctrl_42_pack(chip, 0x1, 0x3D, 0x3D); + break; + case 160: + ricu_afe_ctrl_44_cdb_freq_sel_setf(chip, 0x2); + /* Configure ADC sampling for secondary chains */ + ricu_afe_ctrl_39_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctrl_40_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctrl_41_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctrl_42_pack(chip, 0x0, 0x7, 0x7); + break; + case 320: + ricu_afe_ctrl_44_cdb_freq_sel_setf(chip, 0x3); + /* Configure ADC sampling for secondary chains */ + ricu_afe_ctrl_39_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctrl_40_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctrl_41_pack(chip, 0x0, 0x7, 0x7); + ricu_afe_ctrl_42_pack(chip, 0x0, 0x7, 0x7); + break; + default: + CL_DBG_ERROR_CHIP(chip, "Invalid adc_sampling_clk %u\n", adc_sampling_clk); + return -1; + } + + return 0; +} + +static int cl_afe_adc_and_dac_cfg(struct cl_chip *chip) +{ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + u16 bw_tcv0 = cl_hw_tcv0->conf->ce_channel_bandwidth; + u16 bw_tcv1 = cl_hw_tcv1->conf->ce_channel_bandwidth; + u16 riu_sampling_clk_tcv0 = cl_hw_tcv0->conf->ci_hr_factor[bw_tcv0] * BW_TO_MHZ(bw_tcv0); + u16 riu_sampling_clk_tcv1 = cl_hw_tcv1->conf->ci_hr_factor[bw_tcv1] * BW_TO_MHZ(bw_tcv1); + u16 adc_sampling_clk_tcv0 = 2 * riu_sampling_clk_tcv0; + u16 adc_sampling_clk_tcv1 = 2 * riu_sampling_clk_tcv1; + u8 sb_rd_delay_tcv0 = ((riu_sampling_clk_tcv0 == 80) || + (riu_sampling_clk_tcv0 == 160)) ? 4 : 2; + u8 sb_rd_delay_tcv1 = ((riu_sampling_clk_tcv1 == 80) || + (riu_sampling_clk_tcv1 == 160)) ? 4 : 2; + u32 regval; + + /* + * For ADC sampling CLK=40MHz set to 0 + * For ADC sampling CLK=80MHz set to 1 + * For ADC sampling CLK=160MHz set to 2 + * For ADC sampling CLK=320MHz set to 3 + * + * The sampling clock depends on the channel_bandwidth (20/40/80/160MHz) + * and hr_factor (1,2,4,8): + * ADC Sampling (MHz) = 2 * hr_factor * channel_bandwidth + * + * Select the external forced clock for ADC0..7: + * For ADC sampling CLK=40MHz/80MHz set to 1 + * For ADC sampling CLK=160MHz/320MHz set to 0 + * In our default case: rosel0-3 = 0x0; rosel4-7 = 0x1 + * + * Internal clock frequency of ADCI0..7 I (when its ROSEL is low): + * For ADC sampling CLK=40MHz/80MHz set to 7'b011_1101 + * For ADC sampling CLK=160MHz/320MHz set to 7'b000_0111 + * In our default case: roctrli0-3 = 0x7; roctrli4-7 = 0x3D + * + * Internal clock frequency of ADCQ0..7 I (when its ROSEL is low): + * For ADC sampling CLK=40MHz/80MHz set to 7'b011_1101 + * For ADC sampling CLK=160MHz/320MHz set to 7'b000_0111 + * In our default case: roctrlq0-3 = 0x7; roctrlq4-7 = 0x3D + */ + + if (cl_adc_sampling_cfg_tcv0(chip, adc_sampling_clk_tcv0)) + return -1; + if (cl_adc_sampling_cfg_tcv1(chip, adc_sampling_clk_tcv1)) + return -1; + + /* AFE_CTL_0 - AUX ADC for debug + for second band */ + regval = ricu_afe_ctl_0_get(chip); + if (cl_chip_is_4ant(chip) && cl_chip_is_6g(chip)) + regval |= (RICU_AFE_CTL_0_EN_GPADC_CLK_BIT | + RICU_AFE_CTL_0_EN_GPADC_BIT); + else + regval |= (RICU_AFE_CTL_0_EN_CDB_DAC_CLK_BIT | + RICU_AFE_CTL_0_EN_CDB_ADC_CLK_BIT | + RICU_AFE_CTL_0_EN_CDB_GEN_BIT | + RICU_AFE_CTL_0_EN_GPADC_CLK_BIT | + RICU_AFE_CTL_0_EN_GPADC_BIT); + ricu_afe_ctl_0_set(chip, regval); + + ricu_afe_ctl_3_cml_sel_setf(chip, 7); + + /* VC_LD_AVDI0..7 = 0x1 */ + ricu_afe_ctl_23_set(chip, 0x55555555); + /* VC_LD_AVDQ0..7 = 0x1 */ + ricu_afe_ctl_24_set(chip, 0x55555555); + /* EN_BGR0..7 = 0x1, CH_CML_SEL0..7 = 0x1, EN_EXT_LOAD0..7 = 0x0, EN_REF0..7 = 0x1 */ + ricu_afe_ctl_8_set(chip, 0xff00ffff); + /* VC_CML0..7_I = 0x0 */ + ricu_afe_ctl_29_set(chip, 0x0); + /* VC_CML0..7_Q = 0x0 */ + ricu_afe_ctl_30_set(chip, 0x0); + /* IC_REFSSF0..7 = 0x3, EOC_CTRL0..7 = 0x2 */ + ricu_afe_ctl_12_set(chip, 0xaaaaffff); + + /* + * Set channels to Transceiver0 (phy0) or Transceiver1 (phy1): + * 6'b11_0000 (Transceiver1 @CH7~6, Transceiver0 @CH5~0) + * 6'b11_1000 (Transceiver1 @CH7~5, Transceiver0 @CH4~0) + * 6'b11_1100 (Transceiver1 @CH7~4, Transceiver0 @CH3~0) + * 6'b11_1110 (Transceiver1 @CH7~3, Transceiver0 @CH3~0) + * 6'b11_1111 (Transceiver1 @CH7~2, Transceiver0 @CH2~0) + * In our default case: mainsel72 = 0x3C + */ + ricu_afe_ctl_5_main_sel_7_2_setf(chip, 0x3C); + + /* + * Set 1 - b0 to MINV0/1/2/3/4/5/6/7 (DAC) + * Set 1 - b1 to TWOS0/1/2/3/4/5/6/7 (ADC) + */ + ricu_afe_ctl_10_set(chip, 0x00FF0000); + + /* Set VC_REF0/1/2/../7 */ + ricu_afe_ctl_17_set(chip, 0x77777777); + + /* Set COMP_CTRL0/1/2/.../7[3:0] to 4'b1010 for normal mode */ + ricu_afe_ctl_19_set(chip, 0xAAAAAAAA); + + /* + * Disable DAC & ADC cores (To save power. + * Assuming RIU HW will control it due to HW_MODE_ADC/DAC) + */ + ricu_afe_ctrl_37_phy_0_set(chip, 0); + ricu_afe_ctrl_37_phy_1_set(chip, 0); + + regval = ricu_afe_ctrl_36_phy_0_get(chip); + regval &= ~(RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCI_BIT); + ricu_afe_ctrl_36_phy_0_set(chip, regval); + + regval = ricu_afe_ctrl_36_phy_1_get(chip); + regval &= ~(RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCI_BIT); + ricu_afe_ctrl_36_phy_1_set(chip, regval); + + /* Sync buffer read delay, ignore fifo indication */ + ricu_afe_ctrl_34_phy_0_adc_sb_rd_delay_setf(chip, sb_rd_delay_tcv0); + ricu_afe_ctrl_34_phy_0_adc_sb_ignore_fifo_indication_setf(chip, 1); + + ricu_afe_ctrl_34_phy_1_adc_sb_rd_delay_setf(chip, sb_rd_delay_tcv1); + ricu_afe_ctrl_34_phy_1_adc_sb_ignore_fifo_indication_setf(chip, 1); + + /* DAC - ignore fifo indication = true */ + ricu_afe_ctrl_35_phy_0_dac_sb_rd_delay_setf(chip, 1); + ricu_afe_ctrl_35_phy_0_dac_sb_ignore_fifo_indication_setf(chip, 1); + + ricu_afe_ctrl_35_phy_1_dac_sb_rd_delay_setf(chip, 1); + ricu_afe_ctrl_35_phy_1_dac_sb_ignore_fifo_indication_setf(chip, 1); + + /* Set to HW/SW control mode */ + ricu_afe_ctrl_36_phy_0_hw_mode_adc_setf(chip, 1); + ricu_afe_ctrl_36_phy_0_hw_mode_dac_setf(chip, 1); + + ricu_afe_ctrl_36_phy_1_hw_mode_adc_setf(chip, 1); + ricu_afe_ctrl_36_phy_1_hw_mode_dac_setf(chip, 1); + + return 0; +} + +static int cl_afe_set_cdb_mode(struct cl_chip *chip) +{ + /* Configure number of RF chains per PHY */ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + u8 ant_tcv0 = cl_hw_tcv0->num_antennas; + u8 ant_tcv1 = cl_hw_tcv1 ? cl_hw_tcv1->num_antennas : (chip->max_antennas - ant_tcv0); + u8 ant_total = ant_tcv0 + ant_tcv1; + + if (!cl_chip_is_8ant(chip)) { + ricu_static_conf_0_cdb_mode_maj_setf(chip, 0x4); + return 0; + } + + if (ant_total < MAX_ANTENNAS_CHIP) { + if (ant_tcv0 <= 4 && ant_tcv1 <= 4) { + ant_tcv0 = 4; + ant_tcv1 = 4; + } else { + ant_tcv0 += min(cl_hw_tcv0->max_antennas - cl_hw_tcv0->num_antennas, + chip->max_antennas - ant_total); + + if (cl_hw_tcv1) { + ant_total = ant_tcv0 + ant_tcv1; + ant_tcv1 += min(cl_hw_tcv1->max_antennas - cl_hw_tcv1->num_antennas, + chip->max_antennas - ant_total); + } else { + ant_tcv1 = MAX_ANTENNAS_CHIP - ant_tcv0; + } + } + } + + if (ant_tcv0 == 6 && ant_tcv1 == 2) { + ricu_static_conf_0_cdb_mode_maj_setf(chip, 0x2); + } else if (ant_tcv0 == 5 && ant_tcv1 == 3) { + ricu_static_conf_0_cdb_mode_maj_setf(chip, 0x3); + } else if (ant_tcv0 == 4 && ant_tcv1 == 4) { + ricu_static_conf_0_cdb_mode_maj_setf(chip, 0x4); + } else if (ant_tcv0 == 3 && ant_tcv1 == 5) { + ricu_static_conf_0_cdb_mode_maj_setf(chip, 0x5); + } else if (ant_tcv0 == 2 && ant_tcv1 == 6) { + ricu_static_conf_0_cdb_mode_maj_setf(chip, 0x6); + } else { + CL_DBG_ERROR_CHIP(chip, "Invalid antenna configuration (tcv0 %u) (tcv1 %u)\n", + ant_tcv0, ant_tcv1); + return -1; + } + + return 0; +} + +static int cl_afe_phy_type_and_rf_chains(struct cl_chip *chip) +{ + ricu_spi_clk_ctrl_set(chip, 0x1c); /* SPI clock bitmap */ + ricu_static_conf_0_btc_sel_setf(chip, 0); /* Clear BTC select */ + + if (cl_afe_set_cdb_mode(chip)) + return -1; + + if (cl_chip_is_8ant(chip)) + ricu_afe_adc_ch_alloc_afe_adc_ch_alloc_setf(chip, U8_MAX); + else if (cl_chip_is_6ant(chip)) + ricu_afe_adc_ch_alloc_afe_adc_ch_alloc_setf(chip, 0x3f); + else if (cl_chip_is_6g(chip)) + ricu_afe_adc_ch_alloc_afe_adc_ch_alloc_setf(chip, 0x0f); + else + ricu_afe_adc_ch_alloc_afe_adc_ch_alloc_setf(chip, 0x33); + + /* Reset RFIC */ + ricu_static_conf_0_rf_rst_n_req_setf(chip, 0x1); + + return 0; +} + +int cl_afe_cfg(struct cl_chip *chip) +{ + /* 1. Define PHY Type & RF Chains per band */ + if (cl_afe_phy_type_and_rf_chains(chip)) + return -1; + + /* 2. AFE Disable */ + cl_afe_disable(chip); + + /* Wait 2us for AFE LDO settling time */ + udelay(2); + + /* 3. AFE Enable */ + cl_afe_enable(chip); + + /* 4. ADC & DAC Configuration */ + cl_afe_adc_and_dac_cfg(chip); + + cl_io_ctrl_config(chip); + + /* 5. FEM Configuration */ + cl_fem_update_conf_params(chip); + + return 0; +} + +void cl_afe_cfg_calib(struct cl_chip *chip) +{ + struct cl_afe_reg *orig_afe_reg = &chip->orig_afe_reg; + u32 reg_phy0, reg_phy1; + + orig_afe_reg->ctrl36_phy0 = ricu_afe_ctrl_36_phy_0_get(chip); + orig_afe_reg->ctrl36_phy1 = ricu_afe_ctrl_36_phy_1_get(chip); + orig_afe_reg->ctrl37_phy0 = ricu_afe_ctrl_37_phy_0_get(chip); + orig_afe_reg->ctrl37_phy1 = ricu_afe_ctrl_37_phy_1_get(chip); + + reg_phy0 = orig_afe_reg->ctrl36_phy0; + reg_phy0 |= (RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCI_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_IR_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDQ_BIT | + RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDI_BIT); /* Enable ADC cores */ + reg_phy0 &= ~(RICU_AFE_CTRL_36_PHY_0_HW_MODE_ADC_BIT | + RICU_AFE_CTRL_36_PHY_0_HW_MODE_DAC_BIT); /* Set to SW control mode */ + ricu_afe_ctrl_36_phy_0_set(chip, reg_phy0); + + cl_dbg_chip_trace(chip, "Setting: RICU_AFE_CTRL_36_PHY_0 = 0x%x\n", reg_phy0); + + reg_phy1 = orig_afe_reg->ctrl36_phy1; + reg_phy1 |= (RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCI_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_IR_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDQ_BIT | + RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDI_BIT); + reg_phy1 &= ~(RICU_AFE_CTRL_36_PHY_1_HW_MODE_ADC_BIT | + RICU_AFE_CTRL_36_PHY_1_HW_MODE_DAC_BIT); /* Set to SW control mode */ + ricu_afe_ctrl_36_phy_1_set(chip, reg_phy1); + + cl_dbg_chip_trace(chip, "Setting: RICU_AFE_CTRL_36_PHY_1 = 0x%x\n", reg_phy1); + + /* Enable DAC cores */ + if (cl_chip_is_8ant(chip)) { + reg_phy0 = RICU_AFE_CTRL_37_PHY_0_DAC_CL808X; + reg_phy1 = RICU_AFE_CTRL_37_PHY_1_DAC_CL808X; + } else if (cl_chip_is_6ant(chip)) { + reg_phy0 = RICU_AFE_CTRL_37_PHY_0_DAC_CL806X; + reg_phy1 = RICU_AFE_CTRL_37_PHY_1_DAC_CL806X; + } else if (cl_chip_is_6g(chip)) { + reg_phy0 = RICU_AFE_CTRL_37_PHY_0_DAC_CL8046; + reg_phy1 = RICU_AFE_CTRL_37_PHY_1_DAC_CL804X; + } else { + reg_phy0 = RICU_AFE_CTRL_37_PHY_0_DAC_CL8040; + reg_phy1 = RICU_AFE_CTRL_37_PHY_1_DAC_CL804X; + } + + ricu_afe_ctrl_37_phy_0_set(chip, reg_phy0); + cl_dbg_chip_trace(chip, "Setting: RICU_AFE_CTRL_37_PHY_0 = 0x%x\n", reg_phy0); + + ricu_afe_ctrl_37_phy_1_set(chip, reg_phy1); + cl_dbg_chip_trace(chip, "Setting: RICU_AFE_CTRL_37_PHY_1 = 0x%x\n", reg_phy1); +} + +void cl_afe_cfg_restore(struct cl_chip *chip) +{ + struct cl_afe_reg *orig_afe_reg = &chip->orig_afe_reg; + + ricu_afe_ctrl_36_phy_0_set(chip, orig_afe_reg->ctrl36_phy0); + cl_dbg_chip_trace(chip, "Restoring: RICU_AFE_CTRL_36_PHY_0 = 0x%x\n", + orig_afe_reg->ctrl36_phy0); + + ricu_afe_ctrl_36_phy_1_set(chip, orig_afe_reg->ctrl36_phy1); + cl_dbg_chip_trace(chip, "Restoring: RICU_AFE_CTRL_36_PHY_1 = 0x%x\n", + orig_afe_reg->ctrl36_phy1); + + ricu_afe_ctrl_37_phy_0_set(chip, orig_afe_reg->ctrl37_phy0); + cl_dbg_chip_trace(chip, "Restoring: RICU_AFE_CTRL_37_PHY_0 = 0x%x\n", + orig_afe_reg->ctrl37_phy0); + + ricu_afe_ctrl_37_phy_1_set(chip, orig_afe_reg->ctrl37_phy1); + cl_dbg_chip_trace(chip, "Restoring: RICU_AFE_CTRL_37_PHY_1 = 0x%x\n", + orig_afe_reg->ctrl37_phy1); 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 009/256] cl8k: add ampdu.c Date: Thu, 17 Jun 2021 15:58:16 +0000 Message-Id: <20210617160223.160998-10-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:43 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fbd63310-9827-45a8-3abc-08d931a95787 X-MS-TrafficTypeDiagnostic: AM9P192MB1412: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1417; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZtBnSLZqIpL0GVGb/XC0raWVLtUO4rZFJ4JouHC0Cm1mrFQxkaqIqyosXrbnCXY0oxbYIROj2+oBN7OXdNpoaKHqsR4Bt0xZaZ0qOcRYHpVA2v4Rk+P7NF9EttQ8yUZFASIM9GXQTBBFW6F11nthvZc0eStYAaBRFzHIYxXI9rUDAVDg2DiN3/8Us2os0jyZPUnOTVCERAG1D3zXfTicIXOuU8WLj+TAk9C1DA8qs7TTBRSuYXCnR7EL49C5AljHTd/uPgsS8b8Ek1tsli9bTgevg5CA7anj+ZZ7xQW+5KbjQhRT18vZ5/ZaZ/ope+B7JiSNez3XWg6Udxj/CBNiFj6cVrZqDSGgvM1B3XabARLhomrRM14/GBhqPbOLgZrfHkGe0ghbCDv9Iez2aPWUGW+p+/gAfKMSM37ZFpeY4KszWo2w3whsP4R71cnRvm7SSWLoYqyssIZZhm97fOw8Nx5my9mUqZKpvA9oZj3UfCmL3JQ/0Rx9+vtexCiYJ9pVFHd8NY4vvmafuHOK+BGWAaSpyl9c2Ka/RppPSQYyW5Ks6+5CWCNsPNrPLms1TMgwB+R/wA7BMoUlBjN+OHB1jiTDPX+OZegFjxdqpydBYYV6svaw8+glrohU/zFBdkoyrt2I6DkHGn6tGAnsJxb+m0GLV/07b+eVySJTtzZ4vuI6jDS6SJluiOD/rhuh947Q3XQowPQYXfCyu6LyZLmWXA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(136003)(376002)(39840400004)(396003)(38350700002)(9686003)(16526019)(38100700002)(6512007)(478600001)(36756003)(6506007)(52116002)(55236004)(6486002)(186003)(66556008)(2906002)(8936002)(2616005)(26005)(66946007)(956004)(66476007)(86362001)(83380400001)(107886003)(5660300002)(1076003)(6666004)(4326008)(316002)(8676002)(30864003)(6916009)(54906003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SXQ95t4QpAJbGY+1ojIc84Fo5BRSifd8MpDt+Qjv42t8gwkAKbJE7Basb3YWiDTAR6ap3h3yySsTdHlvk1Pe2QZZDhrbSAdsPL19b/MFU8lUWz9m8i+3sNeuTJ7fu4ztJ5xSfKjzrL3TNKUsMD74aSNkH6mqbtjWaQjp+eJMO5ZfvoUPuufO6yyu8L6GORAtVtYl56H+lXd03qilP1LZfc8gYasqGNQlLit+ixoU5QM0pckUyqLhprapBjBIMOq/HrZ/snAz1DRpmlyvnU8WQ2nbtrrxEwqN+qK0dJGudLltCDByYF2RUFf/vhtPaFZ8MKJi06AS6b4a+SSsUUzqj6RrwUluHjJwyv07RbPrTd705SL59gH5ULrqvAiyDKXKaIojG7/GLlQyE3O0lm9COaX5w6sG/4qSGl2uidUv38E2oN9YDvLrdH01SWcdYJfneIT3/wKy65d/V/EZJTMYEsF5NA93bOuZKKLrLma6YodrbAeZ2KhjBf6SWkXcPlI9l2dTM2U1Few37V28jsFUcpMfFx/Lejm9hp6rFbVrI3K7Xo+MXqi1wJ13sT/5G0JF5lDbyoRgTdwczBjUiT12V6faBrOP8zIrG+GVYdfwcyZEpTclg7jakMojt/tjLDMCp35S2idJI2ZLuLRWQ8YEjO+6ApjzwVnj6PUELV5aYPVLy7ar+Va+hEVXGqb2v8EppzCXmYbQuAWSzRmqZDMzUWz7pD5xDRRpGYTrifOpqVwSQVv+FLKAg3wJQZx+pW0LKW1YIyGzmjeavQq1PVYRE/e8l0FFvEL/gxc4NZAHpgSYECu1VNQaWuzPrl1lhAX+GhIg2jdIPmK1yX3vnDI2FttT/2HSHvneCyeu34Ppw9KYcbo1334Karl6JyRvmhIMArgt+x5xc/g5GQ5+xGcYu3CqRzkMpmd3XFtcIl5omPsYXD598oUlZOdlTit3uJgUkKBHuxGlmRVcHz4aFQOMBob07+1bsKJ6s4QdkciglQZq9q9s9isF7fHoAW9oH6Gu91PwdVp/NwFAwFF5N0BZEUGDHcDJPEtfm3/5XUHImzCc1i8ucv8klzNBMrSpGg2r1fMo0FVViOwcAdAGZliaXU9LxgEA6H52sYT4I468gX9M+vjqemXTmo4ST9QzABe50OoIb5wV21mAexh3v8qwz7M7S8o0XNoib15qonxwLkeJoSP3yn5ipZZIohhaomErd2y+X6w+ML6Cz3iZpo286/NTrq79aUdrrBSQ3JsXrk7NhK0CN32pM7RwFzW/675jWJbocJ+fX3/xjobVhSiiqlODVl+OEdlcwSoesqdhkKhMkZKDlkomW1U+eQl4/tC5 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: fbd63310-9827-45a8-3abc-08d931a95787 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:43.9231 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 05DoVqR+hdA4GqjNounk8fkBdrtUdxaxF/R9Rz53CYywhhnCGMiIy++lLZlnr9aQ2lIvwOeTn+YRaFwTjklvPA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1412 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/ampdu.c | 344 +++++++++++++++++++++++ 1 file changed, 344 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ampdu.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ampdu.c b/drivers/net/wireless/celeno/cl8k/ampdu.c new file mode 100644 index 000000000000..7116995b5059 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ampdu.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "ampdu.h" +#include "hw.h" +#include "fw/msg_tx.h" +#include "tx/tx_queue.h" +#include "tx/agg_cfm.h" +#include "recovery.h" +#include "tx/tx_inject.h" +#include "tx/baw.h" +#include "utils/math.h" +#include "band.h" +#include "rx/rx_reorder.h" +#ifdef CONFIG_CL_PCIE +#include "bus/pci/ipc.h" +#endif + +int cl_ampdu_rx_start(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + u16 tid, + u16 ssn, + u16 buf_size) +{ + /* @IEEE80211_AMPDU_RX_START: start RX aggregation */ + if (!cl_hw->conf->ci_agg_rx) + return -EOPNOTSUPP; + + cl_dbg_trace(cl_hw, "sta_idx [%u] tid [%u]\n", cl_sta->sta_idx, tid); + + buf_size = min(buf_size, cl_hw->conf->ce_max_agg_size_rx); + + if (cl_hw->conf->ci_fast_rx_en) + cl_rx_reorder_init(cl_hw, cl_sta, tid, buf_size); + + cl_msg_tx_ba_add(cl_hw, BA_AGMT_RX, cl_sta->sta_idx, tid, buf_size, ssn); + + return 0; +} + +void cl_ampdu_rx_stop(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + u16 tid) +{ + /* @IEEE80211_AMPDU_RX_STOP: stop RX aggregation */ + cl_dbg_trace(cl_hw, "sta_idx [%u] tid [%u]\n", cl_sta->sta_idx, tid); + + if (cl_hw->conf->ci_fast_rx_en) + cl_rx_reorder_close(cl_sta, tid); +} + +int cl_ampdu_tx_start(struct cl_hw *cl_hw, + struct ieee80211_vif *vif, + struct cl_sta *cl_sta, + u16 tid, + u16 ssn) +{ + /* @IEEE80211_AMPDU_TX_START: start TX aggregation */ + struct mm_available_ba_txq_cfm *cfm = NULL; + int ret = 0; + + if (!ieee80211_hw_check(cl_hw->hw, AMPDU_AGGREGATION) || !cl_hw->conf->ci_agg_tx) + return -EOPNOTSUPP; + + if (!cl_txq_is_agg_available(cl_hw)) { + cl_dbg_warn(cl_hw, "No free aggregation queue for sta_idx [%u] tid [%u]\n", + cl_sta->sta_idx, tid); + return -1; + } + + ret = cl_msg_tx_available_ba_txq(cl_hw, cl_sta->sta_idx, tid); + if (ret) + return ret; + + /* Read FW confirm message */ + cfm = (struct mm_available_ba_txq_cfm *)(cl_hw->msg_cfm_params[MM_AVAILABLE_BA_TXQ_CFM]); + if (!cfm) + return -ENOMSG; + + /* Check if status is valid */ + if (cfm->status != BA_TXQUEUE_INVALID && cfm->status != BA_TXQUEUE_VALID) { + cl_dbg_verbose(cl_hw, "Status Error (%u)\n", cfm->status); + cl_msg_tx_free_cfm_params(cl_hw, MM_AVAILABLE_BA_TXQ_CFM); + return -EIO; + } + + if (cfm->status == BA_TXQUEUE_INVALID) { + cl_dbg_warn(cl_hw, "BA_TXQUEUE_INVALID - sta_idx [%u] tid [%u]\n", + cfm->sta_idx, cfm->tid); + cl_msg_tx_free_cfm_params(cl_hw, MM_AVAILABLE_BA_TXQ_CFM); + return -1; + } + + cl_msg_tx_free_cfm_params(cl_hw, MM_AVAILABLE_BA_TXQ_CFM); + cl_txq_agg_request_add(cl_hw, cl_sta->sta_idx, tid); + cl_baw_start(&cl_sta->baws[tid], ssn); + + /* Mandatory callback once setup preparations are done at lower level */ + ieee80211_start_tx_ba_cb_irqsafe(vif, cl_sta->addr, tid); + + return 0; +} + +int cl_ampdu_tx_operational(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + u16 tid, + u16 buf_size, + bool amsdu_supported) +{ + /* @IEEE80211_AMPDU_TX_OPERATIONAL: TX aggregation has become operational */ + struct mm_ba_add_cfm *cfm = NULL; + struct cl_baw *baw = &cl_sta->baws[tid]; + u16 ssn = baw->ssn; + int ret = 0; + + buf_size = min(buf_size, cl_hw->conf->ce_max_agg_size_tx); + + /* Send MM_BA_ADD_TX_REQ message to firmware */ + ret = cl_msg_tx_ba_add(cl_hw, BA_AGMT_TX, cl_sta->sta_idx, tid, buf_size, ssn); + if (ret) + return ret; + + /* Handle message confirmation */ + cfm = (struct mm_ba_add_cfm *)(cl_hw->msg_cfm_params[MM_BA_ADD_TX_CFM]); + if (!cfm) + return -ENOMSG; + + if (cfm->status != BA_AGMT_ESTABLISHED) { + cl_dbg_verbose(cl_hw, "Status Error (%u)\n", cfm->status); + cl_msg_tx_free_cfm_params(cl_hw, MM_BA_ADD_TX_CFM); + cl_txq_agg_request_del(cl_hw, cl_sta->sta_idx, tid); + return -EIO; + } + + cl_baw_operational(cl_hw, baw, cfm->agg_idx, amsdu_supported); + cl_agg_cfm_set_ssn(cl_hw, ssn, cfm->agg_idx); +#ifdef CONFIG_CL_PCIE + cl_hw->ipc_env->ring_indices_elem->indices->new_ssn_idx[cfm->agg_idx] = cpu_to_le16(ssn); +#endif + + if (amsdu_supported) + cl_tx_amsdu_set_max_len(cl_hw, cl_sta, tid); + else + cl_dbg_trace(cl_hw, "AMSDU not supported - sta_idx=%u\n", cl_sta->sta_idx); + + cl_txq_agg_alloc(cl_hw, cl_sta, cfm, buf_size); + cl_msg_tx_free_cfm_params(cl_hw, MM_BA_ADD_TX_CFM); + + return 0; +} + +void _cl_ampdu_tx_stop(struct cl_hw *cl_hw, + struct cl_tx_queue *tx_queue, + struct cl_sta *cl_sta, + u8 tid) +{ + struct mm_ba_del_cfm *cfm = NULL; + u8 fw_agg_idx = tx_queue->index; + + if (cl_recovery_in_progress(cl_hw)) + goto out; + + /* + * TX stop flow: + * 1) Flush TX queues - done in cl_ampdu_tx_stop() + * 2) Poll confirmation queue and clear enhanced TIM + * 3) Send MM_STA_DEL_REQ message to firmware + * 4) Poll again confirmation and flush confirmation queue + * 5) Reset write index + */ + cl_agg_cfm_poll_empty(cl_hw, fw_agg_idx, false); + + /* Send MM_BA_DEL_REQ message to firmware */ + if (cl_msg_tx_ba_del(cl_hw, cl_sta->sta_idx, tid)) + goto out; + + cfm = (struct mm_ba_del_cfm *)(cl_hw->msg_cfm_params[MM_BA_DEL_CFM]); + if (!cfm) { + cl_dbg_err(cl_hw, "Unable to fetch CFM\n"); + goto out; + } + + /* Check confirmation status */ + if (cfm->status != BA_AGMT_DELETED && cfm->status != BA_AGMT_DOES_NOT_EXIST) + cl_dbg_verbose(cl_hw, "Status Error (%u)\n", cfm->status); + + cl_msg_tx_free_cfm_params(cl_hw, MM_BA_DEL_CFM); + +out: + cl_agg_cfm_poll_empty(cl_hw, fw_agg_idx, true); + cl_txq_agg_free(cl_hw, tx_queue, cl_sta, tid); + +#ifdef CONFIG_CL_PCIE + /* Reset the synchronization counters between the fw and the IPC layer */ + cl_hw->ipc_env->ring_indices_elem->indices->txdesc_write_idx.agg[fw_agg_idx] = 0; +#endif +} + +int cl_ampdu_tx_stop(struct cl_hw *cl_hw, + struct ieee80211_vif *vif, + enum ieee80211_ampdu_mlme_action action, + struct cl_sta *cl_sta, + u16 tid) +{ + /* + * @IEEE80211_AMPDU_TX_STOP_CONT: stop TX aggregation but continue transmitting + * queued packets, now unaggregated. After all packets are transmitted the + * driver has to call ieee80211_stop_tx_ba_cb_irqsafe(). + * @IEEE80211_AMPDU_TX_STOP_FLUSH: stop TX aggregation and flush all packets, + * called when the station is removed. There's no need or reason to call + * ieee80211_stop_tx_ba_cb_irqsafe() in this case as mac80211 assumes the + * session is gone and removes the station. + * @IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: called when TX aggregation is stopped + * but the driver hasn't called ieee80211_stop_tx_ba_cb_irqsafe() yet and + * now the connection is dropped and the station will be removed. Drivers + * should clean up and drop remaining packets when this is called. + */ + + /* !!! Comment in agg-tx.c, ___ieee80211_stop_tx_ba_session(): !!! + * !!! HW shall not deny going back to legacy !!! + * !!! Therefore cl_ampdu_tx_stop() always returns 0 !!! + */ + + struct cl_tx_queue *tx_queue = cl_sta->agg_tx_queues[tid]; + struct cl_baw *baw = &cl_sta->baws[tid]; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + cl_baw_stop(baw); + cl_txq_agg_request_del(cl_hw, cl_sta->sta_idx, tid); + + /* Check if BA session exist */ + if (!tx_queue) { + spin_unlock_bh(&cl_hw->tx_lock_agg); + + if (!cl_recovery_in_progress(cl_hw)) + cl_dbg_warn(cl_hw, "Queue doesn't exist - sta_idx [%u] tid [%u]\n", + cl_sta->sta_idx, tid); + + goto out; + } + + if (action == IEEE80211_AMPDU_TX_STOP_CONT) { + /* + * The order of flow here is very important here to avoid reorder problem! + * 1) Take single lock to block single traffic + * 2) Stop agg traffic. + * 3) Transfer agg-to-single and push all skbs from agg queue to single queue. + * 4) Transfer BA window pending queue to single queue. + * 5) Release single lock + */ + spin_lock_bh(&cl_hw->tx_lock_single); + cl_txq_agg_stop(cl_sta, tid); + cl_txq_transfer_agg_to_single(cl_hw, tx_queue); + cl_baw_pending_to_single(cl_hw, cl_sta, baw); + spin_unlock_bh(&cl_hw->tx_lock_single); + } else { + cl_txq_agg_stop(cl_sta, tid); + cl_txq_flush(cl_hw, tx_queue); + cl_baw_pending_purge(baw); + } + + cl_tx_amsdu_anchor_reset(&cl_sta->amsdu_anchor[tid]); + + spin_unlock_bh(&cl_hw->tx_lock_agg); + + _cl_ampdu_tx_stop(cl_hw, tx_queue, cl_sta, tid); + +out: + /* Mandatory callback once we've made our own tear down ops */ + if (action != IEEE80211_AMPDU_TX_STOP_FLUSH) + ieee80211_stop_tx_ba_cb_irqsafe(vif, cl_sta->addr, tid); + + return 0; +} + +#define HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_OFFSET 3 +#define HE_EXP_MAX 22 /* 2 ^ 22 = 4194304 < 6500631 */ + +static void _cl_ampdu_size_exp(struct ieee80211_sta *sta, + u8 *ampdu_exp_he, + u8 *ampdu_exp_vht, + u8 *ampdu_exp_ht) +{ + struct ieee80211_sta_he_cap *he_cap = &sta->he_cap; + u8 mac_cap_info3 = he_cap->he_cap_elem.mac_cap_info[3]; + u8 he_exp; + + if (sta->ht_cap.ht_supported) + *ampdu_exp_ht = IEEE80211_HT_MAX_AMPDU_FACTOR + sta->ht_cap.ampdu_factor; + + if (sta->vht_cap.vht_supported) { + u32 vht_exp = (sta->vht_cap.cap & + IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK) >> + IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; + + *ampdu_exp_vht = IEEE80211_HT_MAX_AMPDU_FACTOR + vht_exp; + } + + he_exp = (mac_cap_info3 & IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK) >> + HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_OFFSET; + + if (sta->vht_cap.vht_supported) { + if (he_exp) + *ampdu_exp_he = min(IEEE80211_HE_VHT_MAX_AMPDU_FACTOR + he_exp, HE_EXP_MAX); + else + *ampdu_exp_he = *ampdu_exp_vht; + } else if (sta->ht_cap.ht_supported) { + if (he_exp) + *ampdu_exp_he = IEEE80211_HE_HT_MAX_AMPDU_FACTOR + he_exp; + else + *ampdu_exp_he = *ampdu_exp_ht; + } +} + +static void _cl_ampdu_size_exp_6g(struct ieee80211_sta *sta, u8 *ampdu_exp_he) +{ + u8 mac_cap_info3 = sta->he_cap.he_cap_elem.mac_cap_info[3]; + u8 he_exp_ext = (mac_cap_info3 & IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK) >> + HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_OFFSET; + + if (he_exp_ext) { + *ampdu_exp_he = min(IEEE80211_HE_VHT_MAX_AMPDU_FACTOR + he_exp_ext, HE_EXP_MAX); + } else { + struct ieee80211_he_6ghz_capa *he_6g_cap = &sta->he_6ghz_capa; + u8 he_exp_6ghz = (he_6g_cap->capa & HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP_MASK) >> + HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP_OFFSET; + + *ampdu_exp_he = min(HE_6GHZ_CAP_MAX_AMPDU_LEN_FACTOR + he_exp_6ghz, HE_EXP_MAX); + } +} + +void cl_ampdu_size_exp(struct cl_hw *cl_hw, struct ieee80211_sta *sta, + u8 *ampdu_exp_he, u8 *ampdu_exp_vht, u8 *ampdu_exp_ht) +{ + if (cl_band_is_6g(cl_hw)) + _cl_ampdu_size_exp_6g(sta, ampdu_exp_he); + else + _cl_ampdu_size_exp(sta, ampdu_exp_he, ampdu_exp_vht, ampdu_exp_ht); + + cl_dbg_info(cl_hw, "ampdu_size_exp: he = %u, vht = %u, ht = %u\n", + *ampdu_exp_he, *ampdu_exp_vht, *ampdu_exp_ht); +} + From patchwork Thu Jun 17 15:58:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30044C2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 011/256] cl8k: add ate.c Date: Thu, 17 Jun 2021 15:58:18 +0000 Message-Id: <20210617160223.160998-12-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:45 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2a4e4892-fc5a-4088-673d-08d931a958cd X-MS-TrafficTypeDiagnostic: AM9P192MB1412: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TCPDCaVzup+k+bm6enxjVbJU/qvrT3u6HEIkCtHCeh9al9+DGetwKYLuFLehXjUsxpa/7QC5WvswnhPUJue3H5Fo/uKZSgxTCwwaCiy7xMMYj69VPkESxVJYXMiEwfz12DTJ0L1blcSjcnFapwNm8KLCUJJSyEfqsxBlpfDM5JdP5xtClQsowvxKFPYJbxmrCcUGbzcnOuyxbxn6FeXGJsqlC/PHy0M0EY2tPgq3k8m6I/zw2mZH8jJE5+wGh8xr2coO7dbpbnn+zW4r98DnPLRg1UOH3hR5Q4HxZZpZ9YSV6OqNZjS2Y7YdMBCIPQVN3k284v3DxoAy5WHZh6XFe8UQ5DBWFiYVSNAF66aAvvLDp9arLj411kkoddiAWdaGdWMX9bwygzIkxMNR4W15JxCQbmjPONCqzS2EH1sjJmoJ3W2EM7swzRnBnGwCBOlj30qwkNQVqfPLmMi+yOVxA7ljPP9dkl/bUPaZvpaYCwLCWN8USIPoy1shzkcAwPyYLCqWld3iE+G6zJi3CiW2IpYHLYLAti4RuxYb6kVz7IgEYqDup9VlYx62LD8LkpTHFhzeIiMRWXRhrUdfsRLDLECfBf1t0JcF02dAEVxVeewin6XhjDsiI8Q2261Z7ORaBuL91NeEfvTDJ39GXhgrVsCJkvLrjoJb75NJ02iJEYCD44uuffzI3qFjoWLlgxku1AlOePIbB/DAhPoHs9yJvA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(136003)(376002)(39840400004)(396003)(38350700002)(9686003)(16526019)(38100700002)(6512007)(478600001)(36756003)(6506007)(52116002)(55236004)(6486002)(186003)(66556008)(2906002)(8936002)(2616005)(26005)(66946007)(956004)(66476007)(86362001)(83380400001)(107886003)(5660300002)(1076003)(6666004)(4326008)(316002)(8676002)(30864003)(6916009)(54906003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mztQ38tQqSJq75wZWCggqP/PugQ6oTALHkb14aJwk+8bfvdj9R3SIPdw/IffICGnHOgSsV4ogl/Rjr45ib4S38njjtNQaM/r14gtzJ1x41mNN8Mhn49Yf0yw4U0FfM5td+y+jeXYFSK3e1TdacAauQiNGcrodgXR3UvOOifi51vIe4WGbNeCkzNapUjuwQuIU4SzzxE4O1CttW3nipsvl0zTSIKnxZaL00QTzqvT8UWivqX6qWyOnqnzEyaLcU2Rohe3Baoxy2v0y3oLZ8ot8bNPKgfITvcoD+e+n8rPG+rzOacPwpkxRGNh91bMq5ntp9k1QdBNQBtG+oKvC3eu0/t09GL82nbIdUSmUYN0PkCvItA5fPhGNI8wnpBJjg+PLKwOhTgoe9kAujY1wCoDUmPrPJa7xcKGuPUHo1O6dQI5y8g36qsflzXHe3FG5BYNi/L3t3SYXv0KtkJ+2a8eCsOnyS2CmjSOSiNESruZI4/Or64M0YRf214SAJX9dmU7bfz6cj16aQkt2T+FAhkzTT8xAtUBL/kwPOjXjPF/WvJY6o7lLG/yvL0BjSMfn24eNJC8eMHBAp4ra//958wzGCqcS8nFfdt+1BR7xnM24j7tBC2BI2GGot5qPDBa64Wv5t4VLw+vXAro/53ZT1E8i7zramUK45f9OsAypKooMQjWxQraorXm/qerVmcAHy4b3GsTyaB8lKQpwkoxWttNzOdCO0yCgIozbB3nbCi6DtZvxsn+BBELpgQsz9dmnvr7qTItln5eT9Y8n9rZulgTPHwdnksVSjTN4laL7vexIXuUR+x4tpMEow0cRlVJ/Ac1vDUGR+hgU6LcyxfQBnqh/+CP/xk85QqGQ1asRZAoDuhcb97oa2cwYTI4ovKsTTWWPbB2fEt4UjiLCeYUCZtYzuTFFCPUjmV3ea5vcQ7RJ0V0oUPCcQ7aWN+Trxg/dxQQorDaD9sfuAfY99YDLllAe9twFhIjmBBzollaefFkKBC99z212w/2Bau5DQIzVH7AVOLRYAXBhhbWDoOjGTpFn4dhuDX/2Zy1U1t/tl4/6ANTRCQdMDyuVdmsaA3mAT5gIlhqtIqzxJSvzIRO/TbuWhvAdFXI5RuV1aCltWDRYsyzV71scOaeojMZAVBerKybl48XlFIU0PU+CWDcKYH8DOSvoxEwbCgtJ+6xMi6jtIuxthXWsSa2VizzeM1mvA1NyrGJzyVzCjZYjQpSC6GwK8PV3hZU3gzyIjKcuTL7vZdUYdse4epgbWcbQD9KlluF24xr5HQ98M5K/h4WMMz8HPSgfMTl224wX67lII59zKsJ5IIO9mDfbizo6XetvvJD X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2a4e4892-fc5a-4088-673d-08d931a958cd X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:46.1314 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nPBMBbSV3zWtaalOVmgUqjZ8ZyfkvT+cmMhgwCS8hnupb4yO90O+wCoYK55/SLZVpXriomZVATPT7HYL9C1BcA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1412 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/ate.c | 841 +++++++++++++++++++++++++ 1 file changed, 841 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ate.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ate.c b/drivers/net/wireless/celeno/cl8k/ate.c new file mode 100644 index 000000000000..95e4e73cd9c0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ate.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "ate.h" +#include "tx/tx_inject.h" +#include "calib.h" +#include "rate_ctrl.h" +#include "fw/msg_tx.h" +#include "mib.h" +#include "edca.h" +#include "reg/reg_mac_hw.h" +#include "reg/reg_macdsp_api.h" +#include "reg/reg_riu.h" +#include "tx/tx_queue.h" +#include "utils/utils.h" +#include "band.h" +#include "fem.h" +#include "chandef.h" +#include "mac_addr.h" +#include "power.h" +#include "e2p.h" + +#define DIFF(_diff, _new, _old, _member)\ + ((_diff)._member = (_new)._member - (_old)._member) + +/* Max freq delta is 100MHz in Q2 */ +#define MAX_FREQ_DELTA (100 << 2) + +static void set_fixed_rate(struct cl_hw *cl_hw) +{ + struct cl_ate_db *ate_db = &cl_hw->ate_db; + union cl_rate_ctrl_info_he rate_ctrl_he = {.word = 0}; + u8 ltf = 0; + + if (ate_db->mode == WRS_MODE_HE) { + rate_ctrl_he.field.spatial_conf = RATE_CNTRL_HE_SPATIAL_CONF_DEF; + + if (ate_db->ltf == LTF_MAX) + ltf = cl_map_gi_to_ltf(WRS_MODE_HE, ate_db->gi); + else + ltf = ate_db->ltf; + } + + cl_hw->entry_fixed_rate = true; + + cl_rate_ctrl_set_fixed(cl_hw, rate_ctrl_he.word, ate_db->mode, ate_db->mcs, + ate_db->nss, ate_db->bw, ate_db->gi, ltf); +} + +static inline void read_stat(struct cl_hw *cl_hw, struct ate_stats *stats) +{ + stats->tx_bw20 = cl_mib_cntr_read(cl_hw, MIB_DOT11_20MHZ_FRAME_TRANSMITTED_COUNT); + stats->tx_bw40 = cl_mib_cntr_read(cl_hw, MIB_DOT11_40MHZ_FRAME_TRANSMITTED_COUNT); + stats->tx_bw80 = cl_mib_cntr_read(cl_hw, MIB_DOT11_80MHZ_FRAME_TRANSMITTED_COUNT); + stats->tx_bw160 = cl_mib_cntr_read(cl_hw, MIB_DOT11_160MHZ_FRAME_TRANSMITTED_COUNT); + stats->rx_bw20 = cl_mib_cntr_read(cl_hw, MIB_DOT11_20MHZ_FRAME_RECEIVED_COUNT); + stats->rx_bw40 = cl_mib_cntr_read(cl_hw, MIB_DOT11_40MHZ_FRAME_RECEIVED_COUNT); + stats->rx_bw80 = cl_mib_cntr_read(cl_hw, MIB_DOT11_80MHZ_FRAME_RECEIVED_COUNT); + stats->rx_bw160 = cl_mib_cntr_read(cl_hw, MIB_DOT11_160MHZ_FRAME_RECEIVED_COUNT); + stats->fcs_err = cl_mib_cntr_read(cl_hw, MIB_DOT11_FCS_ERROR_COUNT); + stats->phy_err = cl_mib_cntr_read(cl_hw, MIB_DOT11_RX_PHY_ERROR_COUNT); + stats->delimiter_err = cl_mib_cntr_read(cl_hw, MIB_DOT11_AMPDU_DELIMITER_CRC_ERROR_COUNT); +} + +static bool is_valid_rate_he(struct cl_hw *cl_hw, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + u8 ltf = cl_hw->ate_db.ltf; + + /* BW */ + if (!cl_hw->conf->ce_txldpc_en) { + if (bw > CHNL_BW_20) { + u8 bw_mhz = BW_TO_MHZ(bw); + + cl_dbg_err(cl_hw, "Invalid bw [%u] - must be 20 when tx ldpc disabled\n", + bw_mhz); + return false; + } + } + + /* NSS */ + if (nss >= cl_hw->conf->ce_tx_nss) { + cl_dbg_err(cl_hw, "Invalid nss [%u] - must be < %u\n", + nss, cl_hw->conf->ce_tx_nss); + return false; + } + + /* MCS */ + if (cl_hw->conf->ce_txldpc_en) { + if (mcs >= WRS_MCS_MAX_HE) { + cl_dbg_err(cl_hw, "Invalid mcs [%u] - must be 0 - 11\n", mcs); + return false; + } + } else { + if (mcs >= WRS_MCS_10) { + cl_dbg_err(cl_hw, "Invalid mcs [%u] - must be 0-9 when tx ldpc disabled\n", + mcs); + return false; + } + } + + /* GI */ + if (gi >= WRS_GI_MAX_HE) { + cl_dbg_err(cl_hw, "Invalid gi [%u] - must be 0(0.8u)/1(1.6u)/2(3.2u)\n", gi); + return false; + } + + /* LTF */ + if (ltf > LTF_MAX) { + cl_dbg_err(cl_hw, "Invalid ltf [%u] - must be 0(X1)/1(X2)/2(X4)\n", ltf); + return -EINVAL; + } else if (ltf < LTF_MAX) { + /* + * Supported GI/LTF combinations: + * GI = 3.2: LTF_X4 + * GI = 1.6: LTF_X2 + * GI = 0.8: LTF_X1, LTF_X2, LTF_X4 + */ + if (gi == WRS_GI_LONG) { + if (ltf != LTF_X4) { + cl_dbg_err(cl_hw, "ltf must be 2 (=X4) for gi=0\n"); + return false; + } + } else if (gi == WRS_GI_SHORT) { + if (ltf != LTF_X2) { + cl_dbg_err(cl_hw, "ltf must be 1 (=X2) for gi=1\n"); + return false; + } + } + } + + return true; +} + +static bool is_valid_rate_vht(struct cl_hw *cl_hw, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + /* BW */ + if (bw == CHNL_BW_160 && nss >= WRS_SS_3) { + cl_dbg_err(cl_hw, "bw 160 is invalid in 3/4 nss\n"); + return false; + } + + /* NSS */ + if (nss >= cl_hw->conf->ce_tx_nss) { + cl_dbg_err(cl_hw, "Invalid nss [%u] - must be < %u\n", + nss, cl_hw->conf->ce_tx_nss); + return false; + } + + /* MCS */ + if (mcs >= WRS_MCS_MAX_VHT) { + cl_dbg_err(cl_hw, "Invalid mcs [%u] - must be 0-9\n", mcs); + return false; + } + + /* GI */ + if (gi >= WRS_GI_MAX_VHT) { + cl_dbg_err(cl_hw, "Invalid gi [%u] - must be 0(0.8u)/1(0.4u)\n", gi); + return false; + } + + /* Make sure it is not an invalid VHT rate */ + if (bw == CHNL_BW_20 && mcs == WRS_MCS_9) + if (nss == WRS_SS_1 || nss == WRS_SS_2 || nss == WRS_SS_4) { + cl_dbg_err(cl_hw, "nss 1/2/4 are invalid in bw 20, mcs 9\n"); + return false; + } + + if (bw == CHNL_BW_80 && mcs == WRS_MCS_6 && nss == WRS_SS_3) { + cl_dbg_err(cl_hw, "bw 80, mcs 6, nss 3 is invalid\n"); + return false; + } + + return true; +} + +static bool is_valid_rate_ht(struct cl_hw *cl_hw, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + /* BW */ + if (bw > CHNL_BW_40) { + u8 bw_mhz = BW_TO_MHZ(bw); + + cl_dbg_err(cl_hw, "Invalid bw [%u] - must be 20/40\n", bw_mhz); + return false; + } + + /* NSS */ + if (nss >= cl_hw->conf->ce_tx_nss) { + cl_dbg_err(cl_hw, "Invalid nss [%u] - must be < %u\n", + nss, cl_hw->conf->ce_tx_nss); + return false; + } + + /* MCS */ + if (mcs >= WRS_MCS_MAX_HT) { + cl_dbg_err(cl_hw, "Invalid mcs [%u] - must be 0 - 7\n", mcs); + return false; + } + + /* GI */ + if (gi >= WRS_GI_MAX_HT) { + cl_dbg_err(cl_hw, "Invalid gi [%u] - must be 0(0.8u)/1(0.4u)\n", gi); + return false; + } + + return true; +} + +static bool is_valid_rate_ofdm(struct cl_hw *cl_hw, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + /* + * BW + * There is no need to check if bw is valid. + * It was already done in is_valid_bw_mhz(). + * For ofdm we allow bw to be > 20, for FORMAT_NON_HT_DUP. + */ + + /* NSS */ + if (nss != 0) { + cl_dbg_err(cl_hw, "Invalid nss [%u] - must be 0\n", nss); + return false; + } + + /* MCS */ + if (mcs >= WRS_MCS_MAX_OFDM) { + cl_dbg_err(cl_hw, "Invalid mcs [%u] - must be 0 - 7\n", mcs); + return false; + } + + /* GI */ + if (gi != 0) { + cl_dbg_err(cl_hw, "Invalid gi [%u] - nust be 0\n", gi); + return false; + } + + return true; +} + +static bool is_valid_rate_cck(struct cl_hw *cl_hw, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + /* BW */ + if (bw > CHNL_BW_20) { + u8 bw_mhz = BW_TO_MHZ(bw); + + cl_dbg_err(cl_hw, "Invalid bw [%u] - must be 20\n", bw_mhz); + return false; + } + + /* NSS */ + if (nss != 0) { + cl_dbg_err(cl_hw, "Invalid nss [%u] - must be 0\n", nss); + return false; + } + + /* MCS */ + if (mcs >= WRS_MCS_MAX_CCK) { + cl_dbg_err(cl_hw, "Invalid mcs [%u] - must be 0 - 3\n", mcs); + return false; + } + + /* GI */ + if (gi != 0) { + cl_dbg_err(cl_hw, "Invalid gi [%u] - nust be 0\n", gi); + return false; + } + + return true; +} + +static bool is_valid_rate(struct cl_hw *cl_hw) +{ + u8 mode = cl_hw->ate_db.mode; + u8 bw = cl_hw->ate_db.bw; + u8 nss = cl_hw->ate_db.nss; + u8 mcs = cl_hw->ate_db.mcs; + u8 gi = cl_hw->ate_db.gi; + + switch (mode) { + case WRS_MODE_HE: + return is_valid_rate_he(cl_hw, bw, nss, mcs, gi); + case WRS_MODE_VHT: + return is_valid_rate_vht(cl_hw, bw, nss, mcs, gi); + case WRS_MODE_HT: + return is_valid_rate_ht(cl_hw, bw, nss, mcs, gi); + case WRS_MODE_OFDM: + return is_valid_rate_ofdm(cl_hw, bw, nss, mcs, gi); + case WRS_MODE_CCK: + return is_valid_rate_cck(cl_hw, bw, nss, mcs, gi); + default: + cl_dbg_err(cl_hw, + "Invalid mode [%u] - must be: 0(cck)/1(ofdm)/2(ht)/3(vht)/4(he)\n", + mode); + break; + } + + return false; +} + +static bool is_valid_bw(struct cl_hw *cl_hw) +{ + if (cl_hw->bw < cl_hw->ate_db.bw) { + cl_dbg_err(cl_hw, "TX bw [%u] can't be greater than channel bw [%u]\n", + BW_TO_MHZ(cl_hw->ate_db.bw), BW_TO_MHZ(cl_hw->bw)); + return false; + } + + return true; +} + +static bool is_valid_bw_mhz(struct cl_hw *cl_hw, u8 bw_mhz) +{ + if (BAND_IS_5G_6G(cl_hw)) { + if (bw_mhz != BW_TO_MHZ(CHNL_BW_20) && + bw_mhz != BW_TO_MHZ(CHNL_BW_40) && + bw_mhz != BW_TO_MHZ(CHNL_BW_80) && + bw_mhz != BW_TO_MHZ(CHNL_BW_160)) { + cl_dbg_err(cl_hw, + "Invalid bw [%u] - must be 20/40/80/160\n", bw_mhz); + return false; + } + } else { + if (bw_mhz != BW_TO_MHZ(CHNL_BW_20) && + bw_mhz != BW_TO_MHZ(CHNL_BW_40)) { + cl_dbg_err(cl_hw, "Invalid bw [%u] - must be 20/40\n", bw_mhz); + return false; + } + } + + return true; +} + +int cl_ate_reset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + if (cl_tx_inject_is_running(cl_hw)) { + tasklet_kill(&cl_hw->tx_inject.tasklet); + cl_ate_stop(wiphy, NULL, NULL, 0); + } + + /* Reset rate parameters */ + cl_hw->ate_db.mode = 0; + cl_hw->ate_db.bw = 0; + cl_hw->ate_db.nss = 0; + cl_hw->ate_db.mcs = 0; + cl_hw->ate_db.gi = 0; + cl_hw->ate_db.ltf = LTF_MAX; + + cl_hw->entry_fixed_rate = false; + + /* Reset TX power */ + cl_hw->ate_db.tx_power = S8_MAX; + memset(cl_hw->ate_db.tx_power_offset, S8_MAX, MAX_ANTENNAS); + + cl_tx_inject_reset(cl_hw); + + /* Go to ACTIVE state */ + if (cl_hw->chip->conf->ce_production_mode) + cl_msg_tx_set_idle(cl_hw, MAC_ACTIVE); + + if (cl_hw->ate_db.ant_mask) { + u8 default_ant_mask = ANT_MASK(cl_hw->num_antennas); + + cl_msg_tx_set_ant_bitmap(cl_hw, default_ant_mask); + cl_hw->ate_db.ant_mask = 0; + } + + cl_hw->ate_db.active = true; + + /* + * Rearm last_tbtt_irq so that error message will + * not be printed in cl_irq_status_tbtt() + */ + cl_hw->last_tbtt_irq = jiffies; + + cl_dbg_trace(cl_hw, "\n"); + + return 0; +} + +int cl_ate_mode(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_hw->ate_db.mode = *(u8 *)data; + + cl_dbg_trace(cl_hw, "mode = %u\n", cl_hw->ate_db.mode); + + return 0; +} + +int cl_ate_bw(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u8 bw_mhz = *(u8 *)data; + + if (!is_valid_bw_mhz(cl_hw, bw_mhz)) + return -EINVAL; + + cl_hw->ate_db.bw = MHZ_TO_BW(bw_mhz); + + cl_dbg_trace(cl_hw, "bw = %u\n", bw_mhz); + + return 0; +} + +int cl_ate_mcs(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_hw->ate_db.mcs = *(u8 *)data; + + cl_dbg_trace(cl_hw, "mcs = %u\n", cl_hw->ate_db.mcs); + + return 0; +} + +int cl_ate_nss(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_hw->ate_db.nss = *(u8 *)data; + + cl_dbg_trace(cl_hw, "nss = %u\n", cl_hw->ate_db.nss); + + return 0; +} + +int cl_ate_gi(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_hw->ate_db.gi = *(u8 *)data; + cl_dbg_trace(cl_hw, "gi = %u\n", cl_hw->ate_db.gi); + + return 0; +} + +int cl_ate_ltf(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_hw->ate_db.ltf = *(u8 *)data; + + cl_dbg_trace(cl_hw, "ltf = %u\n", cl_hw->ate_db.ltf); + + return 0; +} + +int cl_ate_ldpc(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_hw->conf->ce_txldpc_en = (bool)(*(u8 *)data); + + cl_dbg_trace(cl_hw, "ldpc = %u\n", cl_hw->conf->ce_txldpc_en); + + return 0; +} + +int cl_ate_channel(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u32 channel = ((u32 *)data)[0]; + u32 bw_mhz = ((u32 *)data)[1]; + u32 bw = 0; + u32 primary = 0; + u32 center = 0; + enum nl80211_chan_width width = NL80211_CHAN_WIDTH_20; + + if (!is_valid_bw_mhz(cl_hw, bw_mhz)) + return -EINVAL; + + if (cl_band_is_6g(cl_hw) && channel == 2 && + bw_mhz != BW_TO_MHZ(CHNL_BW_20)) { + cl_dbg_err(cl_hw, "Only 20Mhz is allowed for channel 2\n"); + return -EINVAL; + } + + bw = MHZ_TO_BW(bw_mhz); + + if (cl_chandef_calc(cl_hw, channel, bw, &width, &primary, ¢er)) { + cl_dbg_err(cl_hw, "cl_chandef_calc failed\n"); + return -EINVAL; + } + + if (cl_hw->set_calib) { + cl_hw->set_calib = false; + cl_calib_power_read(cl_hw); + } + + cl_msg_tx_set_channel(cl_hw, channel, bw, primary, center); + + return 0; +} + +int cl_ate_ant(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u8 ant = *(u8 *)data; + u8 mask; + + if (ant >= MAX_ANTENNAS) { + cl_dbg_err(cl_hw, "Invalid antenna value [%u]", ant); + return -EINVAL; + } + + mask = (1 << ant); + + if (mask != cl_hw->ate_db.ant_mask) { + cl_hw->ate_db.ant_mask = mask; + cl_msg_tx_set_ant_bitmap(cl_hw, mask); + } + + cl_dbg_trace(cl_hw, "ant = %u, mask = 0x%x\n", ant, mask); + + return 0; +} + +#define FULL_ANT_MASK ((1 << MAX_ANTENNAS) - 1) + +int cl_ate_multi_ant(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u8 mask = *(u8 *)data; + + if (mask == 0 || mask > FULL_ANT_MASK) { + cl_dbg_err(cl_hw, "Invalid antenna bitmap [0x%x]", mask); + return -EINVAL; + } + + if (mask != cl_hw->ate_db.ant_mask) { + cl_hw->ate_db.ant_mask = mask; + cl_msg_tx_set_ant_bitmap(cl_hw, mask); + } + + cl_dbg_trace(cl_hw, "mask = 0x%x\n", mask); + + return 0; +} + +int cl_ate_packet_len(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u32 packet_len = *(u32 *)data; + + cl_dbg_trace(cl_hw, "packet_len = %u\n", packet_len); + + return cl_tx_inject_set_length(cl_hw, packet_len); +} + +int cl_ate_vector(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u32 size = data_len / sizeof(u32); + int ret = 0; + + cl_dbg_trace(cl_hw, "\n"); + + ret = cl_calib_pivot_channels_set(cl_hw, data, size); + + /* Write EEPROM version when starting calibration process */ + if (!ret) + return cl_e2p_write_version(cl_hw->chip); + + return ret; +} + +int cl_ate_vector_reset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_dbg_trace(cl_hw, "\n"); + + return cl_calib_pivot_channels_reset(cl_hw); +} + +#define FREQ_OFST_MAX 959 + +int cl_ate_freq_offset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u16 freq_offset = *(u16 *)data; + + if (freq_offset > FREQ_OFST_MAX) { + cl_dbg_err(cl_hw, "Invalid freq offset 0x%04x\n", freq_offset); + return -1; + } + + cl_dbg_trace(cl_hw, "Freq offset 0x%04x\n", freq_offset); + + return cl_msg_tx_set_freq_offset(cl_hw, freq_offset); +} + +int cl_ate_stat(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + struct ate_stats new_stats; + struct ate_stats ret_stats; + + read_stat(cl_hw, &new_stats); + + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, tx_bw20); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, tx_bw40); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, tx_bw80); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, tx_bw160); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, rx_bw20); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, rx_bw40); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, rx_bw80); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, rx_bw160); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, fcs_err); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, phy_err); + DIFF(ret_stats, new_stats, cl_hw->ate_db.stats, delimiter_err); + + /* Present rx seccess of the defined bw */ + switch (cl_hw->ate_db.bw) { + case CHNL_BW_20: + ret_stats.rx_success = ret_stats.rx_bw20; + break; + case CHNL_BW_40: + ret_stats.rx_success = ret_stats.rx_bw40; + break; + case CHNL_BW_80: + ret_stats.rx_success = ret_stats.rx_bw80; + break; + case CHNL_BW_160: + ret_stats.rx_success = ret_stats.rx_bw160; + break; + default: + /* Should not get here */ + return -EINVAL; + } + + /* Read rssi */ + macdsp_api_inbdpow_20_unpack(cl_hw, &ret_stats.rssi3, &ret_stats.rssi2, + &ret_stats.rssi1, &ret_stats.rssi0); + ret_stats.rssi4 = S8_MIN; + ret_stats.rssi5 = S8_MIN; + + cl_dbg_trace(cl_hw, "\n"); + + return cl_vendor_reply(cl_hw, &ret_stats, sizeof(struct ate_stats)); +} + +int cl_ate_stat_reset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + read_stat(cl_hw, &cl_hw->ate_db.stats); + + cl_dbg_trace(cl_hw, "\n"); + + return 0; +} + +int cl_ate_power(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + s8 tx_power = *(s8 *)data; + s8 tx_power_q1 = 0; + + if (tx_power < POWER_MIN_DB || tx_power > POWER_MAX_DB) { + cl_dbg_err(cl_hw, "Invalid power (%d). Must be between %d and %d\n", + tx_power, POWER_MIN_DB, POWER_MAX_DB); + return 0; + } + + cl_hw->ate_db.tx_power = tx_power; + tx_power_q1 = tx_power << 1; + + cl_dbg_trace(cl_hw, "ate_power = %u\n", tx_power); + + memset(&cl_hw->phy_data_info.data->pwr_tables, + tx_power_q1, sizeof(struct cl_pwr_tables)); + + cl_msg_tx_refresh_power(cl_hw); + + return 0; +} + +int cl_ate_power_offset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + s8 *pwr_offset = cl_hw->ate_db.tx_power_offset; + int i; + + for (i = 0; i < MAX_ANTENNAS; i++) { + pwr_offset[i] = ((s8 *)data)[i]; + + if (pwr_offset[i] < POWER_OFFSET_MIN_Q2 || + pwr_offset[i] > POWER_OFFSET_MAX_Q2) { + cl_dbg_err(cl_hw, "Invalid power offset (%d). Valid range (%d - %d)\n", + pwr_offset[i], POWER_OFFSET_MIN_Q2, POWER_OFFSET_MAX_Q2); + memset(pwr_offset, S8_MAX, MAX_ANTENNAS); + return -1; + } + } + + cl_dbg_trace(cl_hw, "power_offset = %d,%d,%d,%d,%d,%d\n", + pwr_offset[0], pwr_offset[1], pwr_offset[2], + pwr_offset[3], pwr_offset[4], pwr_offset[5]); + + return cl_msg_tx_set_ant_pwr_offset(cl_hw, pwr_offset); +} + +int cl_ate_tx_start(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u32 tx_cnt = *(u32 *)data; + + if (!cl_hw->ate_db.active) { + cl_dbg_err(cl_hw, "Must call 'ATE reset' first.\n"); + return -EPERM; + } + + if (tx_cnt == 0) { + cl_tx_inject_stop_traffic(cl_hw); + return 0; + } + + if (cl_tx_inject_is_running(cl_hw)) { + cl_dbg_err(cl_hw, "TX already running.\n"); + return -EPERM; + } + + if (!is_valid_rate(cl_hw) || !is_valid_bw(cl_hw)) + return -EPERM; + + set_fixed_rate(cl_hw); + cl_tx_inject_start(cl_hw, tx_cnt); + + cl_dbg_trace(cl_hw, "\n"); + + return 0; +} + +int cl_ate_tx_continuous(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + if (!cl_hw->ate_db.active) { + cl_dbg_err(cl_hw, "Must call 'ATE reset' first.\n"); + return -EPERM; + } + + if (cl_tx_inject_is_running(cl_hw)) { + cl_dbg_err(cl_hw, "TX already running.\n"); + return -EPERM; + } + + if (!is_valid_rate(cl_hw) || !is_valid_bw(cl_hw)) + return -EPERM; + + set_fixed_rate(cl_hw); + cl_tx_inject_start_continuous(cl_hw); + + cl_dbg_trace(cl_hw, "\n"); + + return 0; +} + +int cl_ate_stop(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + cl_tx_inject_stop(cl_hw); + + /* Go back to IDLE state */ + if (cl_hw->chip->conf->ce_production_mode) + cl_msg_tx_set_idle(cl_hw, MAC_IDLE_SYNC); + + cl_hw->ate_db.active = false; + + cl_dbg_trace(cl_hw, "\n"); + + return 0; +} + +int cl_ate_help(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + char *ret_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!ret_buf) + return -ENOMEM; + + snprintf(ret_buf, PAGE_SIZE, + "usage:\n" + "reset - Reset ATE configuration\n" + "mode <0=CCK,1=OFDM,2=HT,3=VHT,4=HE> - Set mode\n" + "bw <20/40/80/160> - Set TX bandwidth parameter\n" + "mcs - set mcs parameter\n" + "nss <0-3> - set nss parameter\n" + "gi - set gi\n" + "ltf - set ltf\n" + "ldpc <0=Disable, 1=Enable> - set ldpc parameter\n" + "channel - change channel\n" + "ant - Enable single antenna\n" + "multi_ant - Enable multiple antennas\n" + "packet_len - Set length of packets to inject\n" + "vector - Set" + " vector of channels to calibrate\n" + "freq_offset <0-959> - Set frequency offset\n" + "stat - Display/Reset statistics\n" + "power <-10dB - 30dB> - Set tx power\n" + "power_offset - Power" + " offset per anthenna [range +/-64][units=0.25dB]\n" + "tx_start - Start TX packets\n" + "tx_continuous - Start transmitting infinite packets\n" + "stop - Stop transmission\n"); + + err = cl_vendor_reply(cl_hw, ret_buf, strlen(ret_buf)); + kfree(ret_buf); + + return err; +} + From patchwork Thu Jun 17 15:58:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BA47C48BE5 for ; Thu, 17 Jun 2021 16:02:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D8C1C613AA for ; Thu, 17 Jun 2021 16:02:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233548AbhFQQFB (ORCPT ); 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Thu, 17 Jun 2021 16:02:47 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 012/256] cl8k: add ate.h Date: Thu, 17 Jun 2021 15:58:19 +0000 Message-Id: <20210617160223.160998-13-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:46 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7323d57-4936-414f-c825-08d931a959cc X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7XVuqFLW8xlJXXARRBUVuTBNIX28dpNd+2+l//h5K7HnvPj4x+kl4IkrYArKfsFEYIOxzjd7bi9+qN0CV76AzLwnCfiOSG94GJC4Es2dRMrRrKbppfY1uhhuNs12Dply1Af4FSNbAT0BqCzDFEvtD1foNntBlzIhBQppHrDXdSv6xY7+kg2r6oeLTKCNRHBzrSg3rdZwI0MgpXTXdyz/kBr1bVtfhFAufku4p0tIu1qZyRZEEzquPmAqdgn79stgLF89Q30yUG1FPkYrp7sYgg/pNI4pLvqUPkYRKczeXlkZ2a8KYcY2nMfN2YBMeWrPWOYGH7N3wc0jEtnyqbVFvmGKrhcMS2Q3yd951fnM5HlaBAcV29NVykgg3I/4o5949DUubXpccVaFAtwK44pOEy+1PaZShZzCvr/jenXwvVRSsVrOtEg5qd0VlJKql6ReGvFD+uY/A/yh5SXjoiU8m+qgPvSORkTiBRoArkNEIKvhORSjkUfjfjgtAH/1l/zf2tEBojSoIRFy2y0HaZmjbcZ1IAKbHcmAmYl3IXH6js3EAHpwRm3t4fkmgiMSbVn0Efao4+CGGhmUyOxNU3I1Z9uP6upEBG1uQD+z8dSEL1OavVmD9BjxEhxOfEjcCpmVi49toIjaVRW9rvYISI1RUB95cLzxS91O+yzDOXxRlpxmHBlkTMjuMhFUXrVt9pQVaikdSVZKyHFbsrUz4r2cwQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JdtyG8bRE6j8Vlm5fqgt1xKR3o1oqLOSsk8cqEhnbhmQc9a3q1ol3ANUsXaphlHCwCPkSl6NOlY8NlhAMk+ov3sm+r4c33/cko55a5//2dVJdcCe0/il5lNtrren46ZlGUhZsleYlD3o7Zed3wHx23WQqM8jMmeyEu8Hb/p8Oy9EwdPkIr6nkWuNHvHdBxHfP3iNPqpr8hM/1j/B01UatRw2I//y7NOo3fB20qM5foNRXo9FbFujJ9Tv0Aw+8aMyl/pV7GgdYlOxZf4+6/bVk7QW/BOJzNgbh5BDcg7ChYA8P6SD7aoCuDXck3nD13FriTr7nJPw9+XA2T58+OE0Kfz+yU8WGHHqliYdBY6mR1DLs/Eid+E4YpKVx6IeaAZ93H8aRqKBR2GUKHtnvtD0DqHMc+pZ1/sEKsNEo10HaDEuJ9xv6ZKPQKIQuWNQ6qLnzKOK5zOLfwmgi75g8EwenYSapgpViQ5znwfKcCK6poMi4sVoNq6EjMpnILoCppicUfw6cmejeAYco+HwWuK/0I6GmhhSAQhWwUOlzJ72b8upB5ran/eoUTROIxFvPE3L1SF/NzXWWI/9d7JlDJDUgi0z/c5Z1Wf6L/1klGVPp7XhbiIwoft5zKMB6fqj7wc5qL2Pn1kBGEXJEB0hnBlV2Ql8Kgrs/ldiFZHBtPN2ez9Jqy/AY23CssvJ2F01DCUK5O1ifPje0rPGe/1q/rkj3TNfjJHLlU6ciwdpOz4nMtSq8Ri9g9iQ40i2VMoWLhkOuu5gBE3GQSzfKeXR9mO4cg5oJIqG8zqvVIb5zDFfa0zkHslr805TEIjBQ9DWMdfu20eX8R3qh95lmOu/iq8LXF8l9gC2ShZ86d2F/0T24q9ohOdwAxi7oH2yc4eX7D+xCYGN9gASmen5Wl1m+Wb9AXrWFvgbNCz+XhQw34wbA8AQ+C4QSO34axN7m2uic0YQnlaMdZJOAnPv7OE9mjoQ8CORRpcy34rDkkOLaLYLcksJOHrWIxpT5+hxdKHHT17S3bYvvcwqmtMDbG/RDNfSJtQdpASB2TyrU81gviYvhZaPQerDCqefbT0piLxYdpMlEEnU0xoYzOSWCKG3+Dobc/SqQULV7JoGDhBwlQRa9fE/753LyXilurtiIG/y6Zo93BZYU7HFEY7mr+Xd/6BnBngm2vmvqieHG9xBqZqt+Rd4JvApAGCPQalZ4QkMNCWy1PYbW3Wb4rY5S4agPKX37w6GyFZCpG1dGI/Ra/+74sorh2DxT+UQanhE11J7TkfXoTodh9HD5/SS6HD9mXvq7tddSlZdMSX2n3zteaxUB13PJJ99BtBnAGlAmsCx3SdV X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7323d57-4936-414f-c825-08d931a959cc X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:47.6757 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: beRdrKtJN863qHBrQoFLcQQ/36RZqlNnTX9ElBFFbnmfV0pSy5bmEwp7Pp5iifEC3JtfLT2S8CM9JywVh91UnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/ate.h | 90 ++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ate.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ate.h b/drivers/net/wireless/celeno/cl8k/ate.h new file mode 100644 index 000000000000..ae9ea58b1a01 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ate.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_ATE_H +#define CL_ATE_H + +#include "hw.h" + +/** + * DOC: ATE (=Automatic Test Equipment) + * + * Routines, that may be helpful in pre/post production stages to verify + * validity of the chip behavior. + */ + +int cl_ate_reset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_mode(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_bw(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_mcs(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_nss(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_gi(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_ltf(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_ldpc(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_channel(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_ant(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_multi_ant(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_packet_len(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_vector(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_vector_reset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_freq_offset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_stat(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_stat_reset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_power(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_power_offset(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_tx_start(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_tx_continuous(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_stop(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); +int cl_ate_help(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len); + +enum cl_ate_cmd { + CL_ATE_RESET, + CL_ATE_MODE, + CL_ATE_BW, + CL_ATE_MCS, + CL_ATE_NSS, + CL_ATE_GI, + CL_ATE_LTF, + CL_ATE_LDPC, + CL_ATE_CHANNEL, + CL_ATE_ANT, + CL_ATE_MULTI_ANT, + CL_ATE_PACKET_LEN, + CL_ATE_VECTOR_RESET, + CL_ATE_VECTOR, + CL_ATE_FREQ_OFFSET, + CL_ATE_STAT_RESET, + CL_ATE_STAT, + CL_ATE_POWER, + CL_ATE_POWER_OFFSET, + CL_ATE_TX_START, + CL_ATE_TX_CONTINUOUS, + CL_ATE_STOP, + + CL_ATE_MAX +}; + +#endif /* CL_ATE_H */ From patchwork Thu Jun 17 15:58:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22DD9C48BE5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 013/256] cl8k: add band.c Date: Thu, 17 Jun 2021 15:58:20 +0000 Message-Id: <20210617160223.160998-14-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:47 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f0acff10-9101-4cd5-f4ce-08d931a95a68 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 972egUFNcCHlQ6xVRJ54tSk9qcr2HsqLwUvazyfGpDI3cs4Be6U5158Sx/eUc8Uz7UJ2wDQnr6GSZK6Ev024LNU4gDvxNilX4+TijenO1f0tBzFVkd4agoZrVj1LXrblM5cWRp4Q7lqHNuQYJKha2Yv1lf2zmgb1zmHNK+VMYg0cPFcZ2rY9qcNebuL4jqwBXighltSvcIDi2BFt6dVB2E1Ph1y76d2AaVaKxFNqCSeGGSY/4VhOpQ47Xl4nwwkYaBZEDC7kEMSIJ8+ZcV97V8lI2shEBXYOzLFfiEdhqFNrimgBLP4mgu6xfvGFdgXudj0eNNnQPlPU2dgXUlf9BVUVvToEFSuXCwR19QYZ5gMO6/2i8uzm2Jn0AzNRVwGKPAb+YAw1RuQ5fvbJ6d6B/njNYZHcoZuCDJHTsxRA9ZeU1Md3tvtOFnUPWzjPRqdutHQtMkWDxFmlXjXXv0pa6R/Woh8T1yWBCMv9zihhclTw1nc+CGUX89vE1sqL6UEdTGQbDZ89cmALHXu3NYar8Pd7vQstTUSOgio+95c/wy6cr9sORyuM//9Btee4A6Fi62gpuFLehoug5oRvP3toLlS8UjYAeOsuII54bFi41iAGBGhaY5Vr72f3/YBhoPxyFOBFJZ/j3f/3A7aLlWV00bx5ZIJgJdpsl7E+d4uo+CpiqOB5p3bRZYokUdMcYXuNwds/9qaoJiax27humKfuVw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dyHyap+RV473Y7KQRAR04wZaMIf+TBD/3zDfN14fYiYyZLfF6YdoSBGXO4BHBAIhcysevu39+BMK35ton7ar3y3Oh5ARyFKw/UCUm0yWYKbo92DS1jsx2apEyTc0OVKa+kHxP4dWx6nt3mxDh7QBXlXQf1CST7UDCK6PxNsKfNimQCM6OdcmEvrLwM//GJaIHJlqW7mkF+/GxYsot99XlQq4833XhGNJNyiJrDG4NeoM4ASCyovE2VGJ8IpWekDN4YUE21gvuvs9qw2Ev8insbU6uNiuojAvdIkeyn/PJ9tCCoRe8drj0wZwfbCpMigANan19AOboMZNl/+9w/gZzgg29xj/JVThnZxg5kEABAGzoOfzVqeInhyZGcnwLEdC+9lIbTAXdmIPGmNAHjABUwd3+QEwbYtZuW6jZgNycZJLYKD1zP4JD+OTq3lp7ks3U5eKyT0AGiyaY6/gvzVziGSqN+4iveRoBwmUTkaL56yNvoHlWFo5wciPYj77ixn7+EhtTAjhzsC5mnc3AStiy2Dj11GEm4+t8rVUHI+NvsuA5gGMWdJoJrBUAwt21FF7kVbrzpER4aodzziwQCYKEW2+9H6a0IgvxNAYD+7cbJ141Tv1bR1am103B+VdqHqcUvBJF8OT0EdcWLU4j4rvF23VM6x62Q/erIC0QcrXtczXi1/SF+tuTYZI7SWftP3+PTUP9Q7UJOWXCgwO+m3mjezQQlrhHA+B/gTVH6bMKS61LE4QzbpAqiziQ5Sm225YCQ1gNNkgRTMpMt5qAzQV4xd605mBLYPG/5ybqmCHiN5cJHr5DtAymRrFNZgablSbEC55XWWmf5B+XAc1i6Gi0L/g4wpnFJZH93NdBDtQicbAqrozztKVihVaaQdK//86QqXSOAPnIsofzgfxJf5U6/acIqwZV+BcX2ZEftEezRs+p35Gs49JkJwhK5zn9/AyMW/gNFNRoVyfU9yenT0wynJLkXIcDAMIbjbwX5KRBGt1s88oXkwMdE56TvqEak+QuAE5ubO/iUSWAKZ/r1T/3H5bdyoX9lMHMtu42XMeh9i0CyHlNghgeVspAXYH6E9/ZCtOt2wkr1moptih3PzdFJDaTRtdbAKEyrzqNEAmEp+jKK2RSMfeZXbQY8zTSrS6PdFJZMDvFZ3kFNFR7DxIybbjdmfXn/rNpFbEX+TgDmQ65ucgBapQD8N7LXcTLPUG1xl7Niwu3runeslOgKApsOQcK8Bfum6LYjR/kKHbBrAFDQ67Di2MdoAWfNVryRN34ZntJ8eFbY+/h0TpS+fHNhqcDLyUjxbFGrBjcT8W/h7p8NftYbbWH6xMCQobhbiJ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: f0acff10-9101-4cd5-f4ce-08d931a95a68 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:48.7031 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 73XSNjQD939SEcMq73Aj3++xy7PxjeKqflSfY0fg9at9aBV6DI+80X1xMJT1kGKPHp7VClFhSRbC6b1nm8nD8w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/band.c | 60 +++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/band.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/band.c b/drivers/net/wireless/celeno/cl8k/band.c new file mode 100644 index 000000000000..6fc688613a51 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/band.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "band.h" + +bool cl_band_is_6g(struct cl_hw *cl_hw) +{ + return (cl_hw->conf->ci_band_num == 6); +} + +bool cl_band_is_6g_freq(u16 freq) +{ + return (freq > 5935) ? true : false; +} + +bool cl_band_is_5g(struct cl_hw *cl_hw) +{ + return (cl_hw->conf->ci_band_num == 5); +} + +bool cl_band_is_5g_freq(u16 freq) +{ + return (freq > 5000 && freq <= 5835) ? true : false; +} + +bool cl_band_is_24g(struct cl_hw *cl_hw) +{ + return (cl_hw->conf->ci_band_num == 24); +} + +bool cl_band_is_24g_freq(u16 freq) +{ + return (freq < 5000) ? true : false; +} + +u8 cl_band_to_fw_idx(struct cl_hw *cl_hw) +{ + if (cl_hw->nl_band == NL80211_BAND_6GHZ) + return FW_BAND_6GHZ; + + if (cl_hw->nl_band == NL80211_BAND_5GHZ) + return FW_BAND_5GHZ; + + return FW_BAND_2GHZ; +} + +static u8 fw_to_nl_band[FW_BAND_MAX] = { + [FW_BAND_6GHZ] = NL80211_BAND_6GHZ, + [FW_BAND_5GHZ] = NL80211_BAND_5GHZ, + [FW_BAND_2GHZ] = NL80211_BAND_2GHZ, +}; + +u8 cl_band_from_fw_idx(u32 phy_band) +{ + if (phy_band < FW_BAND_MAX) + return fw_to_nl_band[phy_band]; + + return FW_BAND_MAX; +} + From patchwork Thu Jun 17 15:58:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3420AC2B9F4 for ; Thu, 17 Jun 2021 16:03:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F11761351 for ; Thu, 17 Jun 2021 16:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233577AbhFQQFN (ORCPT ); Thu, 17 Jun 2021 12:05:13 -0400 Received: from mail-vi1eur05on2073.outbound.protection.outlook.com ([40.107.21.73]:38880 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233544AbhFQQFB (ORCPT ); Thu, 17 Jun 2021 12:05:01 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VhUeac6Fq5ReQjP4zpBM0ihHy35dXdgECd0D9mSUKhdW3C+Lkut8PdVF54DnF8EaLqOB6za8WtJ9uy2G76uVaB9v01pIhcii3fwF+y7YLVct9NXjWhy6w6H7FLaQioG12ot59P2RqZ3yKW58zFuNY0oIrjoeXTQ+FOw8HZ/v11bUHfYB7W3/vDSsJIQD5/gd86hnAzCeQJbCkb1gvsumBBIubf9jZxzoxwGfzuTOQFfHG1/5pZUEeEv/H8K2nHIzF6DJOERLIoNhoL0qM9Cf3HXxNCUx65tF8blMP0SjmS4QXewQghA7Aqg+aNpEecGa8onqytSmUzFNRQg7AyPWkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ntQVhnnCY+TGE5eAEDDAqLtm7VUEeochPaq4ND09qlE=; b=LNoLTMASKZoz05I6FlzpGtgFf/a2vk5DlMQDYBguNJB+qpPFrAfQborMOZjvPPuG+xwUpGk+Us3i52kS1CbL3KIQmm9y5o4OSHLAn7kdkinHkg/vBtJsOD1cUDXRXiMNw6F9/CmVhWiRxkt29TptJMbTeCuQ+6XMX8e3XiCcuXyR3Wu/8DzP7EQ5ydCx45HRSEsdOVCi++KyaOKZE55kP/rCWAbF2KoJUNfGfZcZzbdrpI9b0nRvrKXhvl5tZ3ChcSiyjvf9i5JIF7SpyWl9xqe4XVQSsQDFAqVEvExUwc01bcv8MgEb6fN8Hbk9cFsv0txk0hE3Eg4le3wdk9aM+w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ntQVhnnCY+TGE5eAEDDAqLtm7VUEeochPaq4ND09qlE=; b=wXBjW7yJIqkeOZ5Z0wAuGbf6zpdej6RdBZK3m+PFn/uI1vd9ckoSEVkM66cYVbKozASRpxV6Z61FvfXjCFEH7j+QxgNmfSLygV02SOJSf8H61Co0eCHyrmD5BBJHr4YxOr1MbJgRDlbSpZAGADkXQ5u2wQYFBQeRPJ48oO6kmog= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0499.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:02:49 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:02:49 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 014/256] cl8k: add band.h Date: Thu, 17 Jun 2021 15:58:21 +0000 Message-Id: <20210617160223.160998-15-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:48 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c12f8883-fe93-4480-b32f-08d931a95b02 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4502; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: A0TTErK8Q9ujRDSgE9DNLbd1OEDAEu8K/Zk3xTlSDb6/RLekJLzprFzhTb8YmsTrzeMA+5FXJK5rA7KiFaaLGfsbYV48/yG1IO7IFNOfhISiZ4SkvIJy6NnLLUIu4B+fRRspPPyLJJnLXlfU8QAG0UcA7dzSaRG37b/PJTkYA01w4AwDVaxaNEcdcmCMQxyG2IP8kNqhCZuypORfsatQty5sD4BkspejdWDtNQ3LjCOBc3c202Ja3BKQuHkrqs6e4Bb3aIoeMbAllGsMUIey35TiQYVVIG2LqTIip6Fz19xENaxU1Oqee538SfMFUlkQgAVN4CUc38DTs9fXo5tvrBmSWaO9o8FuKG1SJbSazAONYq71dyUYakLxzBIpFR8xTuFLcWCHs/wPnILJIuKkeatGX3Gi1AEgINdTVmOXH8y7bQgymQP91Xjl2cCBEUMKA8gNcpuJ9KcAotojwC4l3sX2CM2s1mjPrk2iPtxJ8zRqj7gCcZ/yfrsrHPdiheMl9Nmb0IqCSSY/ahm2m5zRfGw146ncYxnbsnd+XEuOwIuZE1N6ivRaY0FT5745WY3ZPIq+mLogyRCOdEDSfilYfBT1a9ASDe51JFVH2+k1MWudVvV/y1nxtd/AgA02MZgZbC2xnx+imxOo0e5/rquehhkTDblIdyXY9UBfAw8CsL7UC5xZRUBsYcBzPfMYBBSPE5tdR0uzvYGqUO4WLPYtLw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YT7IhFLSZ+fB4XX89G0EQt1YXTZKRLsJh7Ll5VITDAdphrdtjrUWogZVi1XekymR6YF5p9Wt24DbQfYj57pw5tEAV5y4SWksqTLGD9/3MeLLDK+1QYKAoH9r5l3GmDd/5V6aNaW88GfTZgM3UsQvscu/D1X/RO60r+YgJrheSaacE9hO5DJU0aJo6muAV8VYP5Qal8d51hmhPp1ppGUhEI9txJXMfkX3/i2frMQF6FD5QkwJcijqSHixMsD7qMsIGJBsuOhuWOeO87sKENorBW859XNO9saj1TrTtNwIAh7GKLTChbSGdQYYiUEHAVd2SkfRlCpCaCIoRWiIqRLs4ejW3Rmgp2RNyCu4W+Xu3pO4i40VXmI1wQPIBrr1SaF3cXWA3LJsRnExrdJOQEkVBNe0ns3+RoUV67RSEXCFJ187ULNQOom7bM1obr1PfHjZpaEnk2D3mSdPNJG9iBL7UbeU2r80gA4cb8565GummkA8HwJ16YDYNKIcMwxR63y8lu5t4NFH/CkxpLyX9KVq7WRmohm740ZE/ID/H4InffVxGVgGK5u2mPLpfF9rcGGY8eLkcWwisNmqmZUfJzaeZGY8aifARjhDogl9ugkAmmcKplFTifZLpFfUftnyJqB6Unr3mDvMeEAtomC1p0ml86xFearP6UGGS3CYdiAcCI4xL+Ug9ENVlvH1mWhdg9g5KsUM0CkkJlabezdmEScLRupbNmHdHaiczzdTu8h/0NBk6Z0tUYVsGPbB7rP0MvNgH+Q4FmmsYFpNIyjSQPesp8XuayqkPPoVoAlrMeq2GLDWKjlJEygJiQ1vkoBQxjkuS5O7Aprvdru25w7PDygkYa7R2+IEkYnkVMK1cE21Os7pAyylwmTHefo9scLlU3qVSrMPMm9PuNixMYZzOdwKfmNpzENQ0rP8y/SCE0/CRaMcxxLoMPiXV0KhjNEpV7lyNqDlZ7qqWAGlRHuk55FGeEC4NVrAlN+rDhceopAcF1tvZhJ7+ysCjVro+rPs8MraFUJ1XNHOZ92+mbmfdtJCNcQyAbulDg55Gp3ow5XdIsk9zFlIODgVcQ7udMDy7NPoAhILYHRBK20zGM8GXLJzlGZeGIjplqrigrRz2fgsbHCiNnqi6Vt4JddaGh1llzFsFVPrAxOEjSk7sefWM4ZU0C0x4UdBUhipV5ah5K++4cfVwxhaVJt+k/6Dhahuub8IXsAtcz4wThJd5TB3MlmmvokxpfzoeXqZWoZFxMZho/W69WUV2c2aNfh0OgIABP/DGpoD8XG/DIatFJZMewyA+LDSE8J/nmXokKoNHNATjINScaVQf3rGO2tbtQgt+9Ae X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: c12f8883-fe93-4480-b32f-08d931a95b02 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:49.7217 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6fSMM7C/GZlBtoW/jO37lDrGsl0wos9vm0NAKT5edEYIOraDWcaP2oZBFvuhykVC8NT2surXkZ0vjnAxCpLm7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/band.h | 40 +++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/band.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/band.h b/drivers/net/wireless/celeno/cl8k/band.h new file mode 100644 index 000000000000..9642432bed0f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/band.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_BAND_H +#define CL_BAND_H + +#include "hw.h" + +enum c_fw_band { + FW_BAND_2GHZ, + FW_BAND_5GHZ, + FW_BAND_6GHZ, + + FW_BAND_MAX, +}; + +#define BAND_6G 6 +#define BAND_5G 5 +#define BAND_24G 24 + +#define BAND_TO_STR(band) \ + ((band) == 6 ? "6G" : \ + ((band) == 5 ? "5G" : "24G")) + +#define BAND_IS_5G_6G(cl_hw) \ + (cl_band_is_5g(cl_hw) || cl_band_is_6g(cl_hw)) + +bool cl_band_is_6g(struct cl_hw *cl_hw); +bool cl_band_is_6g_freq(u16 freq); + +bool cl_band_is_5g(struct cl_hw *cl_hw); +bool cl_band_is_5g_freq(u16 freq); + +bool cl_band_is_24g(struct cl_hw *cl_hw); +bool cl_band_is_24g_freq(u16 freq); + +u8 cl_band_to_fw_idx(struct cl_hw *cl_hw); +u8 cl_band_from_fw_idx(u32 phy_band); + +#endif /* CL_BAND_H */ From patchwork Thu Jun 17 15:58:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 526EFC49EA2 for ; Thu, 17 Jun 2021 16:03:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25AA861249 for ; Thu, 17 Jun 2021 16:03:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233540AbhFQQFU (ORCPT ); Thu, 17 Jun 2021 12:05:20 -0400 Received: from mail-vi1eur05on2073.outbound.protection.outlook.com ([40.107.21.73]:38880 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233537AbhFQQFE (ORCPT ); Thu, 17 Jun 2021 12:05:04 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BfzO6U+SuMQ8ZO25tMx7J5OktJX44dm7ylH30Ug1D+S2iR0EmntgfPo6Evl81vLnGg2OQl5cJrFaWYWLA+PXwkAEBiYBF9OGqZog2L9ldjzBCGg2RJlEeYu17BZ0yL1dND4JxwHpQS9ml9Dspg4qubYuuZz6519gniuCGy9173McARjoPV0CUi7r7XWWvQyO80B3COe7oV+gmzbN2LAJQyexg+2QwpZGFdyPZPMmhFIHYfheJ1AVXDOH9lH4mdT7zWwVb0q9xUAg0lN7ObIZKBsrQfrjDIgg04oT6Fmao7JZQIVof15wC5/lXJPv4R5wdR2OX8fTXAGOLrMsIv4AYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aYw6R8I8CovpGgb96OdTjpfYCV0NuI2/N35pdIblpPc=; b=L2dzJGGhBIEIVoiBddO8rNLYV/bSQ3FjdhbyLLoZ+tRb3SJ78KXh0FrgpCW2RWbHbrg8y/C5Os24hjVWqVI5sWPKWKQfseZlvlCugLQ2bQGL1so+PqkAjeRfjkrMlWLv1zO1YeYJ+V7u2ZLJSAjGhecDWzJsQlb6RV0EGbV45n9chhmNuHaXPIpKbIGO3cN4YMSVrTFg5pmLgvnGmPNTm/PDHwBEH/ABNIXrjN9YwuNABRiz9hJD7JhMY+dTSnNW76T7i418q91XtapmCLeIjkKwcgd+c0vtqQpFPrrOSU/EC7kRywffJ74Y2kJOUUjrr+stVIYoNJPDDdkiN/r2tQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aYw6R8I8CovpGgb96OdTjpfYCV0NuI2/N35pdIblpPc=; b=cF8V5kBNB19I6La9kUrMi7pvU7onqguYY+hk5RHOHsiJbVxRdGjBGdHhs3J7dZeHp/e2CHtednsbrFXigZT8KyeTUbECZ4CjkQTeGSU8jdlckWjfEh/fLF3hWCSpvuQhlaDcamKDJleNiWm4pvIfYXXm5uL83qWu8BO3z/pBA0A= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0499.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:02:53 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:02:53 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 017/256] cl8k: add bus/pci/ipc.c Date: Thu, 17 Jun 2021 15:58:24 +0000 Message-Id: <20210617160223.160998-18-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:52 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 305a10b3-20a1-4198-0edd-08d931a95cd2 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S0ynlz/a8HgDVbGtRiX++GeE5+fY3CEYAXEtmxEyWj6/1xKVkQQanUssZc9IlXyLlxt/ShABj9sk0/3mqBz3M9SBzf70jHMQjGh0DfU/kXxxJeHeWwsQ5AIiVYy4qJ7o8AgF7RdXHOc2B5/Kv9Cy69Yc5qB5wcirTKcbR+3vwoKtl+N537LnrbagPa4wAHfk9ofYDutwxMPAs+YMrssPrf8nhE9LAFuGW+eIQMNgLgF3toonY1RwpJibaapW7mo4x+lJZ/pNTkQ5QINN6fzohbLwkFSoE34kqv98PGCcXE/JsrqzDPGVYUpIu9ap054xEZL9Vy39BrXSYjtSCvgpr0Lrn430JHh/M2AQD5sjww67Htz18/KSoYamoZn8G01uTklZWMXmA9SHeInpfKjDiHXbas+y/hWKnqP2S+am34LQ1YuJ0EsrYROIQ6yLu9T0nYrfq49f2jghzRdLzcBdBglM+0ZnFLwsrsUtKifSpyjNN4bW65SA9o7UcakLLaPLQP9R0x55bdHxJFzKkpRZmWYdswMfD64wjxxUEQlDjHKSJdJVoUuZ+qzGv/ctu/TuXpaJ9rXqp4mDoH7u1HwRcvW75Zkvby94gPrTvQXjyVUnCZoOhSey0XBDTHVT+EJEl+LtKr7cXUn5CSsOpGoIX+hJtMBDD2/3ViCIhUvZj1ORmwC8S38KgAGzUgX9riMxJ+bBceplJf/ojqumv+npvw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(30864003)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j/2eZcdhfb5SKzafMZzu3Pr9mgk9QpWl98MIcEEEFFViZRj9wuNn1vkVrSxUobgRi+PWzllnf8ZDRC0fIrY6AbHihcGQuU0i6iMG/p4ld196vO+r4VB9x/WACidvc17ifAHHNXceO+Gq0MuTAhbx1U9rJuK6jb/C8/oguD3nkxlkPFqB33Y3dMxZncEs4d5bKHlo3m1UpqPhYlLOFpDISZYsmJjlX0mNTsOgUwR8nnUPE8/M/lFtIETnTBROK5/E85TAfBR4Shy+Q6+Zdscc8boizZuQQMT0CkwisCVwnxi7mjaQHkOYtHKlt6N5YpY/0z34n1M+NsT2H+chXywz5b/4o3BaeG1Z0p7rLBqlRpTcnyUnSiPLLEOs/Slz7hIPLj8ztxYm/MzHy6i7/GzNfm1WSripNrajmOnhNv+fZjzr25VaGAjEltx0tKpyuhq9pcZarSECUL8c/i49eN3KyIgZH30bvusuFD2fiLZRI0lS9Vwra9OfyT94BmYKyd/VN0/xqFm60WLscsXuDADYlanT2d8YKZWV9JDIJ1nMK3YA01bochwu1/GEv+91c1hIMu4fujJf20zDdWPG5VJx/Uu9ZzvwpD/Hknux8W2oG0F43ZpK6dqYgfJj4ApBdU7YzsUCZucBcgdtsRItnVyAvt7P0son0YQv2+fDgh79q6w2yunlvWl7uyx0KBEuZa7jGGhxS9/B4xdcJ8J/2dDj0CzJEeRpvKzo/2TgbOIiE6yWqBqkY5rXIdpkVsUw5Q8ug/3E6OIMbT7ewSVNwHfVYeSij14YxndLJcuUrlfKt+TDG500AIE/vezNIFTkHWYmRTHNjxAOhhUag4WaonRhrzgYH7CIYHqvNFZRSvcDTORh/4a72pX+w18h+6oGiJMJcB5Ed0hq9e5UZXyzGv7I3VtXSr5QQW/3TXsrYuEOdn9hJA5NRwXlOOYAEGO02GgrzTKcD7lytA00MwyKGz1FtxFHL7za5rodTYSKXT2FF9iUGGjB5H14angBbpVeOiSYz9Wts4ueuXLl0r5d/vhpdK5eDZfN9AR98p0Xx2sggN1elTcHrZRpwBrIg2nTplWLhnFinqeiNqmWIv9V3U2HZ8nA+4nnSEDZb39UIK6TndkXUr5CcqhG75rY5zfpSRx5yn8k4DOOx3e+0+zh8qnkWKcu9Y1/o0kildgiZkzigqWdp35Jc1GE09jjV74Wqp2bz4lRRvWnzmgBMc2LnNNpiX/3eHLJ6lfzn2gNhbl1UPZ1QvFaCj72tbj2bjUXhmHK1K+CZOMHdH1Y0tsCxmGn+2UNxD+sQ7muZQyVWN/N1cm6ifzk3Grmb7Fvp0VosQr7 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 305a10b3-20a1-4198-0edd-08d931a95cd2 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:52.9196 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1XtyZGwRNt7zFcAI9g/CwsdyXadRPGgQ7iKp+M/28draDq6SxX3xuPX5CHG/Lor2nAiwerGx94lfQD/LRMA0AQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/bus/pci/ipc.c | 1278 +++++++++++++++++ 1 file changed, 1278 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/bus/pci/ipc.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/bus/pci/ipc.c b/drivers/net/wireless/celeno/cl8k/bus/pci/ipc.c new file mode 100644 index 000000000000..c7ba5eb09be0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/bus/pci/ipc.c @@ -0,0 +1,1278 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include + +#include "bus/pci/ipc.h" +#include "rx/rx.h" +#include "bus/pci/rx_pci.h" +#include "tx/tx.h" +#include "bus/pci/tx_pci.h" +#include "bus/pci/irq.h" +#include "fw/fw_dbg.h" +#include "reg/reg_access.h" +#include "reg/reg_ipc.h" +#include "enhanced_tim.h" +#include "fw/msg_rx.h" +#include "dbgfile.h" +#ifdef TRACE_SUPPORT +#include "trace.h" +#endif + +#define DMA_CFM_QUEUE_SIZE 1024 +#define DMA_CFM_TOTAL_SIZE (8 * sizeof(struct cl_ipc_cfm_msg) * DMA_CFM_QUEUE_SIZE) + +static void ipc_env_free(struct cl_hw *cl_hw) +{ + kfree(cl_hw->ipc_env); + cl_hw->ipc_env = NULL; +} + +static void ring_indices_dealloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + if (!ipc_env->ring_indices_elem) + return; + + memset(ipc_env->ring_indices_elem->indices, 0, sizeof(struct cl_ipc_ring_indices)); + ipc_env->ring_indices_elem->indices = NULL; + kfree(ipc_env->ring_indices_elem); + ipc_env->ring_indices_elem = NULL; +} + +static void _txdesc_dealloc(struct cl_hw *cl_hw, + struct txdesc *txdesc, + __le32 dma_addr, + u32 desc_num) +{ + dma_addr_t phys_dma_addr = le32_to_cpu(dma_addr); + u32 size = (desc_num * sizeof(struct txdesc)); + + if (size < PAGE_SIZE) + dma_pool_free(cl_hw->txdesc_pool, txdesc, phys_dma_addr); + else + dma_free_coherent(cl_hw->chip->dev, size, txdesc, phys_dma_addr); +} + +static void txdesc_dealloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_tx_queues *tx_queues = &cl_hw->ipc_env->tx_queues; + struct tx_queues_dma_addr *queues_dma_addr = tx_queues->queues_dma_addr; + u32 i; + + if (queues_dma_addr->bcmc) { + _txdesc_dealloc(cl_hw, tx_queues->ipc_txdesc_bcmc, queues_dma_addr->bcmc, + IPC_TXDESC_CNT_BCMC); + queues_dma_addr->bcmc = 0; + } + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) + if (queues_dma_addr->single[i]) { + _txdesc_dealloc(cl_hw, tx_queues->ipc_txdesc_single[i], + queues_dma_addr->single[i], IPC_TXDESC_CNT_SINGLE); + queues_dma_addr->single[i] = 0; + } + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) + if (queues_dma_addr->agg[i]) { + _txdesc_dealloc(cl_hw, tx_queues->ipc_txdesc_agg[i], + queues_dma_addr->agg[i], cl_hw->max_agg_tx_q_size); + queues_dma_addr->agg[i] = 0; + } + + dma_pool_destroy(cl_hw->txdesc_pool); + cl_hw->txdesc_pool = NULL; +} + +static void tx_queues_dealloc(struct cl_hw *cl_hw) +{ + u32 len = sizeof(struct tx_queues_dma_addr); + dma_addr_t phys_dma_addr = cl_hw->ipc_env->tx_queues.dma_addr; + + if (!cl_hw->ipc_env->tx_queues.queues_dma_addr) + return; + + dma_free_coherent(cl_hw->chip->dev, len, + (void *)cl_hw->ipc_env->tx_queues.queues_dma_addr, + phys_dma_addr); + cl_hw->ipc_env->tx_queues.queues_dma_addr = NULL; +} + +static void rx_dealloc_skb(struct cl_hw *cl_hw, struct cl_rx_elem *rx_elem, + u16 len) +{ + dma_unmap_single(cl_hw->chip->dev, rx_elem->dma_addr, len, + DMA_FROM_DEVICE); + kfree_skb(rx_elem->skb); + rx_elem->skb = NULL; +} + +static void _rx_dealloc_buff(struct cl_hw *cl_hw, + u32 *rxbuf, + __le32 dma_addr, + u32 desc_num) +{ + dma_addr_t phys_dma_addr = le32_to_cpu(dma_addr); + u32 size = (desc_num * sizeof(u32)); + + dma_free_coherent(cl_hw->chip->dev, size, rxbuf, phys_dma_addr); +} + +static void rx_dealloc_buff(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_ipc_host_rxbuf *rxbuf_rxm = &ipc_env->rx_hostbuf_array[CL_RX_BUF_RXM]; + struct cl_ipc_host_rxbuf *rxbuf_fw = &ipc_env->rx_hostbuf_array[CL_RX_BUF_FW]; + + if (rxbuf_rxm->dma_payload_base_addr) + _rx_dealloc_buff(cl_hw, + rxbuf_rxm->dma_payload_addr, + rxbuf_rxm->dma_payload_base_addr, + IPC_RXBUF_CNT_RXM); + + if (rxbuf_fw->dma_payload_base_addr) + _rx_dealloc_buff(cl_hw, + rxbuf_fw->dma_payload_addr, + rxbuf_fw->dma_payload_base_addr, + IPC_RXBUF_CNT_FW); +} + +static void rx_dealloc(struct cl_hw *cl_hw) +{ + struct cl_rx_elem *rx_elem = cl_hw->rx_elems; + u16 rxbuf_size_rxm = cl_hw->conf->ci_ipc_rxbuf_size[CL_RX_BUF_RXM]; + u16 rxbuf_size_fw = cl_hw->conf->ci_ipc_rxbuf_size[CL_RX_BUF_FW]; + int i; + + if (!cl_hw->rx_elems) + return; + + for (i = 0; i < IPC_RXBUF_CNT_RXM; i++, rx_elem++) + if (rx_elem->skb && !rx_elem->passed) + rx_dealloc_skb(cl_hw, rx_elem, rxbuf_size_rxm); + + for (i = 0; i < IPC_RXBUF_CNT_FW; i++, rx_elem++) + if (rx_elem->skb && !rx_elem->passed) + rx_dealloc_skb(cl_hw, rx_elem, rxbuf_size_fw); + + kfree(cl_hw->rx_elems); + cl_hw->rx_elems = NULL; + + rx_dealloc_buff(cl_hw); +} + +static void msg_dealloc(struct cl_hw *cl_hw) +{ + struct cl_e2a_msg_elem *msg_elem; + int i; + + if (!cl_hw->e2a_msg_elems || !cl_hw->e2a_msg_pool) + return; + + for (i = 0, msg_elem = cl_hw->e2a_msg_elems; + i < IPC_E2A_MSG_BUF_CNT; i++, msg_elem++) { + if (msg_elem->msgbuf_ptr) { + dma_pool_free(cl_hw->e2a_msg_pool, msg_elem->msgbuf_ptr, + msg_elem->dma_addr); + msg_elem->msgbuf_ptr = NULL; + } + } + + dma_pool_destroy(cl_hw->e2a_msg_pool); + cl_hw->e2a_msg_pool = NULL; + + kfree(cl_hw->e2a_msg_elems); + cl_hw->e2a_msg_elems = NULL; +} + +static void radar_dealloc(struct cl_hw *cl_hw) +{ + struct cl_radar_elem *radar_elem; + int i; + + if (!cl_hw->radar_pool || !cl_hw->radar_elems) + return; + + for (i = 0, radar_elem = cl_hw->radar_elems; + i < IPC_RADAR_BUF_CNT; i++, radar_elem++) { + if (radar_elem->radarbuf_ptr) { + dma_pool_free(cl_hw->radar_pool, radar_elem->radarbuf_ptr, + radar_elem->dma_addr); + radar_elem->radarbuf_ptr = NULL; + } + } + + dma_pool_destroy(cl_hw->radar_pool); + cl_hw->radar_pool = NULL; + + kfree(cl_hw->radar_elems); + cl_hw->radar_elems = NULL; +} + +static void dbg_dealloc(struct cl_hw *cl_hw) +{ + struct cl_dbg_elem *dbg_elem; + int i; + + if (!cl_hw->dbg_pool || !cl_hw->dbg_elems) + return; + + for (i = 0, dbg_elem = cl_hw->dbg_elems; + i < IPC_DBG_BUF_CNT; i++, dbg_elem++) { + if (dbg_elem->dbgbuf_ptr) { + dma_pool_free(cl_hw->dbg_pool, dbg_elem->dbgbuf_ptr, + dbg_elem->dma_addr); + dbg_elem->dbgbuf_ptr = NULL; + } + } + + dma_pool_destroy(cl_hw->dbg_pool); + cl_hw->dbg_pool = NULL; + + kfree(cl_hw->dbg_elems); + cl_hw->dbg_elems = NULL; +} + +static void cfm_dealloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + dma_free_coherent(cl_hw->chip->dev, + DMA_CFM_TOTAL_SIZE, + ipc_env->cfm_virt_base_addr, + ipc_env->cfm_dma_base_addr); + + ipc_env->cfm_dma_base_addr = 0; + ipc_env->cfm_virt_base_addr = NULL; +} + +static void dbg_info_dealloc(struct cl_hw *cl_hw) +{ + if (!cl_hw->dbginfo.buf) + return; + + dma_free_coherent(cl_hw->chip->dev, + cl_hw->dbginfo.bufsz, + cl_hw->dbginfo.buf, + cl_hw->dbginfo.dma_addr); + + cl_hw->dbginfo.buf = NULL; +} + +static void ipc_elems_dealloc(struct cl_hw *cl_hw) +{ + ring_indices_dealloc(cl_hw); + txdesc_dealloc(cl_hw); + tx_queues_dealloc(cl_hw); + rx_dealloc(cl_hw); + msg_dealloc(cl_hw); + radar_dealloc(cl_hw); + dbg_dealloc(cl_hw); + cfm_dealloc(cl_hw); + dbg_info_dealloc(cl_hw); +} + +static int ring_indices_alloc(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + ipc_env->ring_indices_elem = kzalloc(sizeof(*ipc_env->ring_indices_elem), GFP_KERNEL); + + if (!ipc_env->ring_indices_elem) + return -ENOMEM; + + if (cl_hw_is_tcv0(cl_hw)) { + ipc_env->ring_indices_elem->indices = chip->ring_indices.params; + ipc_env->ring_indices_elem->dma_addr = chip->ring_indices.dma_addr; + } else { + ipc_env->ring_indices_elem->indices = chip->ring_indices.params + 1; + ipc_env->ring_indices_elem->dma_addr = + (u32)chip->ring_indices.dma_addr + sizeof(struct cl_ipc_ring_indices); + } + + memset(ipc_env->ring_indices_elem->indices, 0, sizeof(struct cl_ipc_ring_indices)); + + return 0; +} + +static int tx_queues_alloc(struct cl_hw *cl_hw) +{ + struct tx_queues_dma_addr *buf = NULL; + u32 size = sizeof(struct tx_queues_dma_addr); + dma_addr_t phys_dma_addr; + + buf = dma_alloc_coherent(cl_hw->chip->dev, size, &phys_dma_addr, GFP_KERNEL); + + if (!buf) + return -ENOMEM; + + cl_hw->ipc_env->tx_queues.queues_dma_addr = buf; + cl_hw->ipc_env->tx_queues.dma_addr = phys_dma_addr; + + return 0; +} + +static int __txdesc_alloc(struct cl_hw *cl_hw, + struct txdesc **txdesc, + u32 *dma_addr, + u32 desc_num) +{ + dma_addr_t phys_dma_addr; + u32 size = (desc_num * sizeof(struct txdesc)); + + if (size < PAGE_SIZE) { + *txdesc = dma_pool_alloc(cl_hw->txdesc_pool, GFP_KERNEL, &phys_dma_addr); + + if (!(*txdesc)) { + cl_dbg_err(cl_hw, "dma_pool_alloc failed size=%d\n", size); + return -ENOMEM; + } + } else { + *txdesc = dma_alloc_coherent(cl_hw->chip->dev, size, &phys_dma_addr, GFP_KERNEL); + + if (!(*txdesc)) { + cl_dbg_err(cl_hw, "dma_alloc_coherent failed size=%d\n", size); + return -ENOMEM; + } + } + + *dma_addr = cpu_to_le32(phys_dma_addr); + memset(*txdesc, 0, size); + + return 0; +} + +static int _txdesc_alloc(struct cl_hw *cl_hw) +{ + /* + * Allocate ipc txdesc for each queue, map the base + * address to the DMA and set the queues size + */ + struct cl_ipc_tx_queues *tx_queues = &cl_hw->ipc_env->tx_queues; + struct tx_queues_dma_addr *queues_dma_addr = tx_queues->queues_dma_addr; + u32 i; + int ret = 0; + + cl_hw->max_agg_tx_q_size = LMAC_TXDESC_AGG_Q_SIZE_MAX; + + ret = __txdesc_alloc(cl_hw, &tx_queues->ipc_txdesc_bcmc, + &queues_dma_addr->bcmc, IPC_TXDESC_CNT_BCMC); + if (ret) + return ret; + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) { + ret = __txdesc_alloc(cl_hw, &tx_queues->ipc_txdesc_single[i], + &queues_dma_addr->single[i], IPC_TXDESC_CNT_SINGLE); + if (ret) + return ret; + } + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + ret = __txdesc_alloc(cl_hw, &tx_queues->ipc_txdesc_agg[i], + &queues_dma_addr->agg[i], cl_hw->max_agg_tx_q_size); + if (ret) + return ret; + } + + return 0; +} + +static int txdesc_alloc(struct cl_hw *cl_hw) +{ + u32 pool_size = IPC_TXDESC_CNT_SINGLE * sizeof(struct txdesc); + + cl_hw->txdesc_pool = dma_pool_create("cl_txdesc_pool", cl_hw->chip->dev, pool_size, + cache_line_size(), 0); + + if (!cl_hw->txdesc_pool) { + cl_dbg_verbose(cl_hw, "dma_pool_create failed !!!\n"); + return -ENOMEM; + } + + return _txdesc_alloc(cl_hw); +} + +static int rx_skb_alloc(struct cl_hw *cl_hw) +{ + /* + * This function allocates Rx elements for DMA + * transfers and pushes the DMA address to FW. + */ + struct cl_rx_elem *rx_elem = cl_hw->rx_elems; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + int i = 0; + u16 rxbuf_size_rxm = cl_hw->conf->ci_ipc_rxbuf_size[CL_RX_BUF_RXM]; + u16 rxbuf_size_fw = cl_hw->conf->ci_ipc_rxbuf_size[CL_RX_BUF_FW]; + + /* Allocate and push RXM buffers */ + for (i = 0; i < IPC_RXBUF_CNT_RXM; rx_elem++, i++) { + if (cl_ipc_rx_elem_alloc(cl_hw, rx_elem, rxbuf_size_rxm)) { + cl_dbg_verbose(cl_hw, "RXM rx_elem allocation failed !!!\n"); + return -ENOMEM; + } + cl_ipc_rxbuf_push(ipc_env, rx_elem, i, i, CL_RX_BUF_RXM); + } + + /* Allocate and push FW buffers */ + for (i = 0; i < IPC_RXBUF_CNT_FW; rx_elem++, i++) { + if (cl_ipc_rx_elem_alloc(cl_hw, rx_elem, rxbuf_size_fw)) { + cl_dbg_verbose(cl_hw, "FW rx_elem allocation failed !!!\n"); + return -ENOMEM; + } + cl_ipc_rxbuf_push(ipc_env, rx_elem, i, i, CL_RX_BUF_FW); + } + + return 0; +} + +static int _rx_buf_alloc(struct cl_hw *cl_hw, u32 **rxbuf, u32 *dma_addr, u32 desc_num) +{ + dma_addr_t phys_dma_addr; + u32 size = (desc_num * sizeof(u32)); + + *rxbuf = dma_alloc_coherent(cl_hw->chip->dev, + size, + &phys_dma_addr, + GFP_KERNEL); + + if (!(*rxbuf)) + return -ENOMEM; + + *dma_addr = cpu_to_le32(phys_dma_addr); + memset(*rxbuf, 0, size); + + return 0; +} + +static int rx_buf_alloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_ipc_host_rxbuf *rxbuf_rxm = &ipc_env->rx_hostbuf_array[CL_RX_BUF_RXM]; + struct cl_ipc_host_rxbuf *rxbuf_fw = &ipc_env->rx_hostbuf_array[CL_RX_BUF_FW]; + int ret = 0; + + rxbuf_rxm->ipc_host_rxdesc_ptr = ipc_env->ipc_host_rxdesc_rxm; + rxbuf_fw->ipc_host_rxdesc_ptr = ipc_env->ipc_host_rxdesc_fw; + + /* Allocate RXM RX write/read indexes */ + ret = _rx_buf_alloc(cl_hw, + (u32 **)&rxbuf_rxm->dma_payload_addr, + &rxbuf_rxm->dma_payload_base_addr, + IPC_RXBUF_CNT_RXM); + if (ret) + return ret; + + /* Allocate FW RX write/read indexes */ + ret = _rx_buf_alloc(cl_hw, + (u32 **)&rxbuf_fw->dma_payload_addr, + &rxbuf_fw->dma_payload_base_addr, + IPC_RXBUF_CNT_FW); + if (ret) + return ret; + + return 0; +} + +static int rx_alloc(struct cl_hw *cl_hw) +{ + u32 total_rx_elems = IPC_RXBUF_CNT_RXM + IPC_RXBUF_CNT_FW; + u32 alloc_size = total_rx_elems * sizeof(struct cl_rx_elem); + int ret = rx_buf_alloc(cl_hw); + + if (ret) + return ret; + + cl_hw->rx_elems = kzalloc(alloc_size, GFP_KERNEL); + + if (!cl_hw->rx_elems) + return -ENOMEM; + + return rx_skb_alloc(cl_hw); +} + +static int _msg_alloc(struct cl_hw *cl_hw, struct cl_e2a_msg_elem *msg_elem) +{ + dma_addr_t dma_addr; + struct cl_ipc_e2a_msg *msg; + + /* Initialize the message pattern to NULL */ + msg = dma_pool_alloc(cl_hw->e2a_msg_pool, GFP_KERNEL, &dma_addr); + if (!msg) + return -ENOMEM; + + msg->pattern = 0; + + /* Save the msg pointer (for deallocation) and the dma_addr */ + msg_elem->msgbuf_ptr = msg; + msg_elem->dma_addr = dma_addr; + + return 0; +} + +static int msg_alloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_e2a_msg_elem *msg_elem; + u32 alloc_size = IPC_E2A_MSG_BUF_CNT * sizeof(struct cl_e2a_msg_elem); + u32 i; + + cl_hw->e2a_msg_elems = kzalloc(alloc_size, GFP_KERNEL); + + if (!cl_hw->e2a_msg_elems) + return -ENOMEM; + + cl_hw->e2a_msg_pool = dma_pool_create("dma_pool_msg", + cl_hw->chip->dev, + sizeof(struct cl_ipc_e2a_msg), + cache_line_size(), + 0); + + if (!cl_hw->e2a_msg_pool) { + cl_dbg_verbose(cl_hw, "dma_pool_create failed !!!\n"); + return -ENOMEM; + } + + /* Initialize the msg buffers in the global IPC array. */ + for (i = 0, msg_elem = cl_hw->e2a_msg_elems; + i < IPC_E2A_MSG_BUF_CNT; msg_elem++, i++) { + if (_msg_alloc(cl_hw, msg_elem)) { + cl_dbg_verbose(cl_hw, "msg allocation failed !!!\n"); + return -ENOMEM; + } + + cl_ipc_msgbuf_push(ipc_env, (ptrdiff_t)msg_elem, msg_elem->dma_addr); + } + + return 0; +} + +static int _radar_alloc(struct cl_hw *cl_hw, struct cl_radar_elem *radar_elem) +{ + dma_addr_t dma_addr; + struct cl_radar_pulse_array *radar; + + /* Initialize the message pattern to NULL */ + radar = dma_pool_alloc(cl_hw->radar_pool, GFP_KERNEL, &dma_addr); + if (!radar) + return -ENOMEM; + + radar->cnt = 0; + + /* Save the msg pointer (for deallocation) and the dma_addr */ + radar_elem->radarbuf_ptr = radar; + radar_elem->dma_addr = dma_addr; + + return 0; +} + +static int radar_alloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_radar_elem *radar_elem; + u32 alloc_size = IPC_RADAR_BUF_CNT * sizeof(struct cl_radar_elem); + u32 i; + + cl_hw->radar_elems = kzalloc(alloc_size, GFP_KERNEL); + + if (!cl_hw->radar_elems) + return -ENOMEM; + + cl_hw->radar_pool = dma_pool_create("dma_pool_radar", + cl_hw->chip->dev, + sizeof(struct cl_radar_pulse_array), + cache_line_size(), + 0); + + if (!cl_hw->radar_pool) { + cl_dbg_verbose(cl_hw, "dma_pool_create failed !!!\n"); + return -ENOMEM; + } + + /* Initialize the radar buffers in the global IPC array. */ + for (i = 0, radar_elem = cl_hw->radar_elems; + i < IPC_RADAR_BUF_CNT; radar_elem++, i++) { + if (_radar_alloc(cl_hw, radar_elem)) { + cl_dbg_verbose(cl_hw, "radar allocation failed !!!\n"); + return -ENOMEM; + } + + cl_ipc_radarbuf_push(ipc_env, (ptrdiff_t)radar_elem, radar_elem->dma_addr); + } + + return 0; +} + +static int _dbg_alloc(struct cl_hw *cl_hw, struct cl_dbg_elem *dbg_elem) +{ + dma_addr_t dma_addr; + struct cl_ipc_dbg_msg *dbg_msg; + + dbg_msg = dma_pool_alloc(cl_hw->dbg_pool, GFP_KERNEL, &dma_addr); + if (!dbg_msg) + return -ENOMEM; + + dbg_msg->pattern = 0; + + /* Save the Debug msg pointer (for deallocation) and the dma_addr */ + dbg_elem->dbgbuf_ptr = dbg_msg; + dbg_elem->dma_addr = dma_addr; + + return 0; +} + +static int dbg_alloc(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_dbg_elem *dbg_elem; + u32 alloc_size = IPC_DBG_BUF_CNT * sizeof(struct cl_dbg_elem); + u32 i; + + cl_hw->dbg_elems = kzalloc(alloc_size, GFP_KERNEL); + + if (!cl_hw->dbg_elems) + return -ENOMEM; + + cl_hw->dbg_pool = dma_pool_create("dma_pool_dbg", + cl_hw->chip->dev, + sizeof(struct cl_ipc_dbg_msg), + cache_line_size(), + 0); + + if (!cl_hw->dbg_pool) { + cl_dbg_verbose(cl_hw, "dma_pool_create failed !!!\n"); + return -ENOMEM; + } + + /* Initialize the dbg buffers in the global IPC array. */ + for (i = 0, dbg_elem = cl_hw->dbg_elems; + i < IPC_DBG_BUF_CNT; dbg_elem++, i++) { + if (_dbg_alloc(cl_hw, dbg_elem)) { + cl_dbg_verbose(cl_hw, "dbgelem allocation failed !!!\n"); + return -ENOMEM; + } + + cl_ipc_dbgbuf_push(ipc_env, (ptrdiff_t)dbg_elem, dbg_elem->dma_addr); + } + + return 0; +} + +static int cfm_alloc(struct cl_hw *cl_hw) +{ + dma_addr_t dma_addr; + u8 *host_virt_addr; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + host_virt_addr = dma_alloc_coherent(cl_hw->chip->dev, + DMA_CFM_TOTAL_SIZE, + &dma_addr, + GFP_KERNEL); + + if (!host_virt_addr) + return -ENOMEM; + + memset(host_virt_addr, 0, DMA_CFM_TOTAL_SIZE); + ipc_env->cfm_dma_base_addr = dma_addr; + ipc_env->cfm_virt_base_addr = host_virt_addr; + + memset(ipc_env->cfm_virt_base_addr, 0, IPC_CFM_SIZE); + + return 0; +} + +static int _dbg_info_alloc(struct cl_hw *cl_hw) +{ + dma_addr_t dma_addr; + u32 len = sizeof(struct dbg_info); + struct dbg_info *buf = dma_alloc_coherent(cl_hw->chip->dev, len, &dma_addr, GFP_KERNEL); + + if (!buf) { + cl_dbg_verbose(cl_hw, "buffer alloc of size %u failed\n", len); + return -ENOMEM; + } + + memset(buf, 0, sizeof(struct dbg_info)); + buf->u.type = DBG_INFO_UNSET; + + cl_hw->dbginfo.buf = buf; + cl_hw->dbginfo.dma_addr = dma_addr; + cl_hw->dbginfo.bufsz = len; + + return 0; +} + +static int dbg_info_alloc(struct cl_hw *cl_hw) +{ + /* Initialize the debug information buffer */ + if (_dbg_info_alloc(cl_hw)) { + cl_dbg_verbose(cl_hw, "dbginfo allocation failed !!!\n"); + return -ENOMEM; + } + + cl_ipc_dbginfobuf_push(cl_hw->ipc_env, cl_hw->dbginfo.dma_addr); + + return 0; +} + +static int ipc_elems_alloc(struct cl_hw *cl_hw) +{ + /* Allocate all the elements required for communications with firmware */ + if (ring_indices_alloc(cl_hw)) + goto out_err; + + if (tx_queues_alloc(cl_hw)) + goto out_err; + + if (txdesc_alloc(cl_hw)) + goto out_err; + + if (rx_alloc(cl_hw)) + goto out_err; + + if (msg_alloc(cl_hw)) + goto out_err; + + if (radar_alloc(cl_hw)) + goto out_err; + + if (dbg_alloc(cl_hw)) + goto out_err; + + if (cfm_alloc(cl_hw)) + goto out_err; + + if (dbg_info_alloc(cl_hw)) + goto out_err; + + return 0; + +out_err: + ipc_elems_dealloc(cl_hw); + return -ENOMEM; +} + +static u8 cl_ipc_dbgfile_handler(struct cl_hw *cl_hw, ptrdiff_t hostid) +{ + struct cl_dbg_elem *dbg_elem = (struct cl_dbg_elem *)hostid; + struct cl_ipc_dbg_msg *dbg_msg; + u8 ret = 0; + + /* Retrieve the message structure */ + dbg_msg = (struct cl_ipc_dbg_msg *)dbg_elem->dbgbuf_ptr; + + if (!dbg_msg) { + ret = -1; + cl_dbg_err(cl_hw, "dbgbuf_ptr is NULL!!!!\n"); + goto dbg_push; + } + + /* Look for pattern which means that this hostbuf has been used for a MSG */ + if (le32_to_cpu(dbg_msg->pattern) != IPC_DBG_VALID_PATTERN) { + ret = -1; + goto dbg_no_push; + } + + /* Reset the msg element and re-use it */ + dbg_msg->pattern = 0; + + /* Display the firmware string */ + cl_dbgfile_print_fw_str(cl_hw, dbg_msg->string, IPC_DBG_PARAM_SIZE); + +dbg_push: + /* make sure memory is written before push to HW */ + wmb(); + + /* Push back the buffer to the firmware */ + cl_ipc_dbgbuf_push(cl_hw->ipc_env, (ptrdiff_t)dbg_elem, dbg_elem->dma_addr); + +dbg_no_push: + return ret; +} + +static void cl_ipc_dbgfile_tasklet(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_ipc_hostbuf *dbg_array = ipc_env->dbg_hostbuf_array; + int dbg_handled = 0; + +#ifdef TRACE_SUPPORT + trace_cl_trace_dbgfile_tasklet_start(cl_hw->idx); +#endif + + while (!cl_ipc_dbgfile_handler(cl_hw, dbg_array[ipc_env->dbg_host_idx].hostid)) + dbg_handled++; + +#ifdef TRACE_SUPPORT + trace_cl_trace_dbgfile_tasklet_end(cl_hw->idx, dbg_handled); +#endif + + /* Enable the DBG interrupt */ + if (!test_bit(CL_DEV_STOP_HW, &cl_hw->drv_flags)) + cl_irq_enable(cl_hw, cl_hw->ipc_e2a_irq.dbg); +} + +static void ipc_tasklet_init(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + tasklet_init(&ipc_env->rxdesc_tasklet, + cl_rx_pci_desc_tasklet, + (unsigned long)cl_hw); + tasklet_init(&ipc_env->tx_single_cfm_tasklet, + cl_tx_pci_single_cfm_tasklet, + (unsigned long)cl_hw); + tasklet_init(&ipc_env->tx_agg_cfm_tasklet, + cl_tx_pci_agg_cfm_tasklet, + (unsigned long)cl_hw); + tasklet_init(&ipc_env->msg_tasklet, + cl_msg_rx_tasklet, + (unsigned long)cl_hw); + tasklet_init(&ipc_env->dbg_tasklet, + cl_ipc_dbgfile_tasklet, + (unsigned long)cl_hw); +} + +static int ipc_env_init(struct cl_hw *cl_hw) +{ + u32 *dst; + u32 i; + + BUILD_BUG_ON_NOT_POWER_OF_2(IPC_RXBUF_CNT_RXM); + BUILD_BUG_ON_NOT_POWER_OF_2(IPC_RXBUF_CNT_FW); + + /* Allocate the IPC environment */ + cl_hw->ipc_env = kzalloc(sizeof(*cl_hw->ipc_env), GFP_KERNEL); + if (!cl_hw->ipc_env) + return -ENOMEM; + + dst = (u32 *)(cl_hw->ipc_env); + + /* + * Reset the IPC Host environment. + * Perform the reset word per word because memset() does + * not correctly reset all (due to misaligned accesses) + */ + for (i = 0; i < sizeof(*cl_hw->ipc_env); i += sizeof(u32)) + *dst++ = 0; + + return 0; +} + +static bool is_la_enabled(struct cl_chip *chip) +{ + s8 *ela_mode = chip->conf->ce_ela_mode; + + return (!strcmp(ela_mode, "default") || + !strncmp(ela_mode, "lcu_mac", 7) || + !strncmp(ela_mode, "lcu_phy", 7)); +} + +static void ipc_shared_env_init(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_ipc_shared_env *shared_env = + (struct cl_ipc_shared_env *)(chip->pci_bar0_virt_addr + SHARED_RAM_START_ADDR); + u32 *dst, i; + + /* The shared environment of TCV1 is located after the shared environment of TCV0. */ + if (cl_hw_is_tcv1(cl_hw)) + shared_env++; + + dst = (u32 *)(shared_env); + + /* Reset the shared environment */ + for (i = 0; i < sizeof(struct cl_ipc_shared_env); i += sizeof(u32)) + *dst++ = 0; + + shared_env->la_enable = is_la_enabled(chip); + shared_env->max_retry = cl_hw->chip->conf->ce_production_mode ? + 0 : cpu_to_le16(cl_hw->conf->ce_max_retry); + shared_env->lft_limit_ms = cpu_to_le16(CL_TX_LIFETIME_MS); + shared_env->phy_dev = cpu_to_le16(chip->conf->ci_phy_dev); + + /* Initialize the shared environment pointer */ + ipc_env->shared = shared_env; +} + +static void ipc_e2a_irq_init(struct cl_hw *cl_hw) +{ + struct cl_ipc_e2a_irq *ipc_e2a_irq = &cl_hw->ipc_e2a_irq; + + if (cl_hw_is_tcv0(cl_hw)) { + ipc_e2a_irq->dbg = IPC_IRQ_L2H_DBG; + ipc_e2a_irq->msg = IPC_IRQ_L2H_MSG; + ipc_e2a_irq->rxdesc = IPC_IRQ_L2H_RXDESC; + ipc_e2a_irq->txcfm = IPC_IRQ_L2H_TXCFM; + ipc_e2a_irq->radar = IPC_IRQ_L2H_RADAR; + ipc_e2a_irq->txdesc_ind = IPC_IRQ_L2H_TXDESC_IND; + ipc_e2a_irq->tbtt = IPC_IRQ_L2H_TBTT; + ipc_e2a_irq->sync = IPC_IRQ_L2H_SYNC; + ipc_e2a_irq->all = IPC_IRQ_L2H_ALL; + } else { + ipc_e2a_irq->dbg = IPC_IRQ_S2H_DBG; + ipc_e2a_irq->msg = IPC_IRQ_S2H_MSG; + ipc_e2a_irq->rxdesc = IPC_IRQ_S2H_RXDESC; + ipc_e2a_irq->txcfm = IPC_IRQ_S2H_TXCFM; + ipc_e2a_irq->radar = IPC_IRQ_S2H_RADAR; + ipc_e2a_irq->txdesc_ind = IPC_IRQ_S2H_TXDESC_IND; + ipc_e2a_irq->tbtt = IPC_IRQ_S2H_TBTT; + ipc_e2a_irq->sync = IPC_IRQ_S2H_SYNC; + ipc_e2a_irq->all = IPC_IRQ_S2H_ALL; + } +} + +int cl_ipc_init(struct cl_hw *cl_hw) +{ + /* + * This function initializes IPC interface by registering callbacks, setting + * shared memory area and calling IPC Init function. + * This function should be called only once during driver's lifetime. + */ + int ret = ipc_env_init(cl_hw); + + if (ret) + return ret; + + ipc_e2a_irq_init(cl_hw); + if (cl_hw_is_tcv0(cl_hw)) + cl_hw->ipc_host2xmac_trigger_set = ipc_host_2_lmac_trigger_set; + else + cl_hw->ipc_host2xmac_trigger_set = ipc_host_2_smac_trigger_set; + + ipc_shared_env_init(cl_hw); + + ret = ipc_elems_alloc(cl_hw); + if (ret) { + ipc_env_free(cl_hw); + return ret; + } + + ipc_tasklet_init(cl_hw); + + return ret; +} + +static void ring_indices_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + memset(ipc_env->ring_indices_elem->indices, 0, + sizeof(*ipc_env->ring_indices_elem->indices)); + + /* Reset host desc read idx follower */ + ipc_env->host_rxdesc_read_idx[CL_RX_BUF_RXM] = 0; + ipc_env->host_rxdesc_read_idx[CL_RX_BUF_FW] = 0; +} + +static void _txdesc_reset(struct txdesc **txdesc, u32 desc_num) +{ + u32 size = (desc_num * sizeof(struct txdesc)); + + memset(*txdesc, 0, size); +} + +static void txdesc_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_tx_queues *tx_queues = &cl_hw->ipc_env->tx_queues; + u32 i; + + _txdesc_reset(&tx_queues->ipc_txdesc_bcmc, IPC_TXDESC_CNT_BCMC); + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) + _txdesc_reset(&tx_queues->ipc_txdesc_single[i], IPC_TXDESC_CNT_SINGLE); + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) + _txdesc_reset(&tx_queues->ipc_txdesc_agg[i], cl_hw->max_agg_tx_q_size); +} + +static void rx_skb_reset(struct cl_hw *cl_hw) +{ + /* + * This function allocates Rx elements for DMA + * transfers and pushes the DMA address to FW. + */ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_rx_elem *rx_elem = cl_hw->rx_elems; + int i = 0; + + /* Push RXM buffers */ + for (i = 0; i < IPC_RXBUF_CNT_RXM; rx_elem++, i++) + cl_ipc_rxbuf_push(ipc_env, rx_elem, i, i, CL_RX_BUF_RXM); + + /* Push FW buffers */ + for (i = 0; i < IPC_RXBUF_CNT_FW; rx_elem++, i++) + cl_ipc_rxbuf_push(ipc_env, rx_elem, i, i, CL_RX_BUF_FW); +} + +static void _rx_buf_reset(u32 **rxbuf, u32 desc_num) +{ + u32 size = (desc_num * sizeof(u32)); + + memset(*rxbuf, 0, size); +} + +static void rx_buf_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_ipc_host_rxbuf *rxbuf_rxm = &ipc_env->rx_hostbuf_array[CL_RX_BUF_RXM]; + struct cl_ipc_host_rxbuf *rxbuf_fw = &ipc_env->rx_hostbuf_array[CL_RX_BUF_FW]; + + /* Reset RXM RX buffer */ + _rx_buf_reset((u32 **)&rxbuf_rxm->dma_payload_addr, + IPC_RXBUF_CNT_RXM); + + /* Reset FW RX buffer */ + _rx_buf_reset((u32 **)&rxbuf_fw->dma_payload_addr, + IPC_RXBUF_CNT_FW); +} + +static void rx_reset(struct cl_hw *cl_hw) +{ + rx_buf_reset(cl_hw); + rx_skb_reset(cl_hw); +} + +static void msg_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_e2a_msg_elem *msg_elem; + u32 i; + + ipc_env->e2a_msg_host_idx = 0; + + /* Initialize the msg buffers in the global IPC array. */ + for (i = 0, msg_elem = cl_hw->e2a_msg_elems; + i < IPC_E2A_MSG_BUF_CNT; msg_elem++, i++) { + msg_elem->msgbuf_ptr->pattern = 0; + cl_ipc_msgbuf_push(ipc_env, (ptrdiff_t)msg_elem, msg_elem->dma_addr); + } +} + +static void radar_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_radar_elem *radar_elem; + u32 i; + + ipc_env->radar_host_idx = 0; + + /* Initialize the radar buffers in the global IPC array. */ + for (i = 0, radar_elem = cl_hw->radar_elems; + i < IPC_RADAR_BUF_CNT; radar_elem++, i++) { + radar_elem->radarbuf_ptr->cnt = 0; + cl_ipc_radarbuf_push(ipc_env, (ptrdiff_t)radar_elem, radar_elem->dma_addr); + } +} + +static void dbg_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_dbg_elem *dbg_elem; + u32 i; + + ipc_env->dbg_host_idx = 0; + + /* Initialize the dbg buffers in the global IPC array. */ + for (i = 0, dbg_elem = cl_hw->dbg_elems; + i < IPC_DBG_BUF_CNT; dbg_elem++, i++) { + dbg_elem->dbgbuf_ptr->pattern = 0; + cl_ipc_dbgbuf_push(ipc_env, (ptrdiff_t)dbg_elem, dbg_elem->dma_addr); + } +} + +static void cfm_reset(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + ipc_env->cfm_used_idx = 0; + memset(ipc_env->cfm_virt_base_addr, 0, IPC_CFM_SIZE); +} + +static void dbg_info_reset(struct cl_hw *cl_hw) +{ + struct dbg_info *buf = cl_hw->dbginfo.buf; + + memset(buf, 0, sizeof(struct dbg_info)); + buf->u.type = DBG_INFO_UNSET; + + cl_ipc_dbginfobuf_push(cl_hw->ipc_env, cl_hw->dbginfo.dma_addr); +} + +static void ipc_elems_reset(struct cl_hw *cl_hw) +{ + ring_indices_reset(cl_hw); + txdesc_reset(cl_hw); + rx_reset(cl_hw); + msg_reset(cl_hw); + radar_reset(cl_hw); + dbg_reset(cl_hw); + cfm_reset(cl_hw); + dbg_info_reset(cl_hw); + cl_enhanced_tim_reset(cl_hw); +} + +void cl_ipc_recovery(struct cl_hw *cl_hw) +{ + ipc_shared_env_init(cl_hw); + ipc_elems_reset(cl_hw); +} + +void cl_ipc_reset(struct cl_hw *cl_hw) +{ + cl_hw->ipc_env->shared->cfm_read_pointer = 0; + cl_hw->ipc_env->cfm_used_idx = 0; +} + +void cl_ipc_deinit(struct cl_hw *cl_hw) +{ + ipc_elems_dealloc(cl_hw); + ipc_env_free(cl_hw); +} + +void cl_ipc_stop(struct cl_hw *cl_hw) +{ + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + tasklet_kill(&ipc_env->rxdesc_tasklet); + tasklet_kill(&ipc_env->tx_single_cfm_tasklet); + tasklet_kill(&ipc_env->tx_agg_cfm_tasklet); + tasklet_kill(&ipc_env->msg_tasklet); + tasklet_kill(&ipc_env->dbg_tasklet); +} + +int cl_ipc_rx_elem_alloc(struct cl_hw *cl_hw, struct cl_rx_elem *rx_elem, u32 size) +{ + struct sk_buff *skb; + dma_addr_t dma_addr; + struct hw_rxhdr *rxhdr; + + rx_elem->passed = 0; + + skb = dev_alloc_skb(size); + + if (unlikely(!skb)) { + cl_dbg_verbose(cl_hw, "skb alloc failed (size %u)\n", size); + rx_elem->dma_addr = (dma_addr_t)0; + return -ENOMEM; + } + + /* Reserve room for RX vector */ + skb_reserve(skb, IPC_RXBUF_EXTRA_HEADROOM); + + rxhdr = (struct hw_rxhdr *)skb->data; + rxhdr->pattern = 0; + + dma_addr = dma_map_single(cl_hw->chip->dev, skb->data, size, DMA_FROM_DEVICE); + + if (unlikely(dma_mapping_error(cl_hw->chip->dev, dma_addr))) { + cl_dbg_verbose(cl_hw, "dma_mapping_error\n"); + kfree_skb(skb); + return -1; + } + + rx_elem->skb = skb; + rx_elem->dma_addr = dma_addr; + + cl_rx_skb_alloc_handler(skb); + + return 0; +} + +void cl_ipc_msgbuf_push(struct cl_ipc_host_env *ipc_env, ptrdiff_t hostid, dma_addr_t hostbuf) +{ + /* + * Push a pre-allocated buffer descriptor for MSGs + * This function is only called at Init time since the MSGs will be handled directly + * and buffer can be re-used as soon as the message is handled, no need to re-allocate + * new buffers in the meantime. + */ + struct cl_ipc_shared_env *shared_env = ipc_env->shared; + u8 e2a_msg_host_idx = ipc_env->e2a_msg_host_idx; + + /* Save the hostid and the hostbuf in global array */ + ipc_env->e2a_msg_hostbuf_array[e2a_msg_host_idx].hostid = hostid; + ipc_env->e2a_msg_hostbuf_array[e2a_msg_host_idx].dma_addr = hostbuf; + + /* Copy the hostbuf (DMA address) in the ipc shared memory */ + shared_env->e2a_msg_hostbuf_addr[e2a_msg_host_idx] = cpu_to_le32(hostbuf); + + /* Increment the array index */ + ipc_env->e2a_msg_host_idx = (e2a_msg_host_idx + 1) % IPC_E2A_MSG_BUF_CNT; +} + +void cl_ipc_rxbuf_push(struct cl_ipc_host_env *ipc_env, struct cl_rx_elem *rx_elem, + u32 rxdesc_read_idx, u32 host_read_idx, enum rx_buf_type type) +{ + /* + * Push a pre-allocated buffer descriptor for Rx packet. + * This function is called to supply the firmware with new empty buffer. + */ + struct cl_ipc_ring_indices *indices = ipc_env->ring_indices_elem->indices; + struct cl_ipc_host_rxbuf *host_rxbuf = &ipc_env->rx_hostbuf_array[type]; + + /* Save the hostid and the hostbuf in global array */ + host_rxbuf->ipc_host_rxdesc_ptr[host_read_idx] = (ptrdiff_t *)rx_elem; + host_rxbuf->dma_payload_addr[host_read_idx] = rx_elem->dma_addr; + + /* Update rxbuff metadata */ + indices->rxdesc_read_idx[type] = cpu_to_le32(rxdesc_read_idx + 1); +} + +void cl_ipc_radarbuf_push(struct cl_ipc_host_env *ipc_env, ptrdiff_t hostid, dma_addr_t hostbuf) +{ + /* + * Push a pre-allocated radar event buffer descriptor. + * This function should be called by the host IRQ handler to supply the embedded + * side with new empty buffer. + */ + struct cl_ipc_shared_env *shared_env = ipc_env->shared; + u8 radar_host_idx = ipc_env->radar_host_idx; + + /* Save the hostid and the hostbuf in global array */ + ipc_env->radar_hostbuf_array[radar_host_idx].hostid = hostid; + ipc_env->radar_hostbuf_array[radar_host_idx].dma_addr = hostbuf; + + /* Copy the hostbuf (DMA address) in the ipc shared memory */ + shared_env->radarbuf_hostbuf[radar_host_idx] = cpu_to_le32(hostbuf); + + /* Increment the array index */ + ipc_env->radar_host_idx = (radar_host_idx + 1) % IPC_RADAR_BUF_CNT; +} + +void cl_ipc_dbgbuf_push(struct cl_ipc_host_env *ipc_env, ptrdiff_t hostid, dma_addr_t hostbuf) +{ + /* + * Push a pre-allocated buffer descriptor for Debug messages. + * This function is only called at Init time since the Debug messages will be + * handled directly and buffer can be re-used as soon as the message is handled, + * no need to re-allocate new buffers in the meantime. + */ + struct cl_ipc_shared_env *shared_env = ipc_env->shared; + u8 dbg_host_idx = ipc_env->dbg_host_idx; + + /* Save the hostid and the hostbuf in global array */ + ipc_env->dbg_hostbuf_array[dbg_host_idx].hostid = hostid; + ipc_env->dbg_hostbuf_array[dbg_host_idx].dma_addr = hostbuf; + + /* Copy the hostbuf (DMA address) in the ipc shared memory */ + shared_env->dbg_hostbuf_addr[dbg_host_idx] = cpu_to_le32(hostbuf); + + /* Increment the array index */ + ipc_env->dbg_host_idx = (dbg_host_idx + 1) % IPC_DBG_BUF_CNT; +} + +void cl_ipc_dbginfobuf_push(struct cl_ipc_host_env *ipc_env, dma_addr_t infobuf) +{ + /*Push the pre-allocated logic analyzer and debug information buffer */ + struct cl_ipc_shared_env *shared_env = ipc_env->shared; + + /* Copy the hostbuf (DMA address) in the ipc shared memory */ + shared_env->dbginfo_addr = cpu_to_le32(infobuf); + /* Copy the hostbuf size in the ipc shared memory */ + shared_env->dbginfo_size = cpu_to_le32(DBG_DUMP_BUFFER_SIZE); +} From patchwork Thu Jun 17 15:58:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4273C49361 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/bus/pci/ipc.h | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/bus/pci/ipc.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/bus/pci/ipc.h b/drivers/net/wireless/celeno/cl8k/bus/pci/ipc.h new file mode 100644 index 000000000000..81cdae55f467 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/bus/pci/ipc.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_IPC_H +#define CL_IPC_H + +#include "ipc_shared.h" +#include "hw.h" + +/* Struct used to store information about host buffers (DMA Address and local pointer) */ +struct cl_ipc_hostbuf { + ptrdiff_t hostid; /* Ptr to hostbuf client (ipc_host client) structure */ + dma_addr_t dma_addr; /* Ptr to real hostbuf dma address */ +}; + +/* + * Index in txdesc - updated by host on every push, used by firmware side + * Keep this structure aligned to 4-byte + */ +struct cl_ipc_txdesc_write_idx { + u32 agg[IPC_MAX_BA_SESSIONS]; + u32 single[MAX_SINGLE_QUEUES]; + u32 bcmc; +}; + +struct cl_ipc_ring_indices { + /* Last copy of ipc txdesc write desc right after DMA push operation */ + volatile struct cl_ipc_txdesc_write_idx txdesc_write_idx; + /* + * new start sn - equal to last acknowledged sequence number + 1. + * Updated by firmware and used by host. + */ + volatile u16 new_ssn_idx[IPC_MAX_BA_SESSIONS]; + volatile u8 dtim_count[MAX_BSS_NUM]; + /* Index in rxdesc array, updated by firmware on every payload push, used by host */ + volatile u32 rxdesc_write_idx[CL_RX_BUF_MAX]; + /* Index in rxdesc array, updated by host on rxdesc copy completion, used by firmware */ + volatile u32 rxdesc_read_idx[CL_RX_BUF_MAX]; + /* BSR data counters */ + volatile u32 bsr_data_ctrs[TID_MAX]; +}; + +/* Structure used to store Shared Txring indices */ +struct cl_ipc_ring_indices_elem { + struct cl_ipc_ring_indices *indices; + dma_addr_t dma_addr; +}; + +struct cl_ipc_host_rxbuf { + /* Array of drv desc which holds the skb and additional data */ + ptrdiff_t **ipc_host_rxdesc_ptr; + /* Address of payload for embedded push operation (part of rxdesc data) */ + u32 *dma_payload_addr; + /* Dma pointer to array of DMA payload addresses */ + __le32 dma_payload_base_addr; +}; + +/* + * struct tx_queues_dma_addr - ipc layer queues addresses casted to DMA addresses + * + * The ipc layer points to array of txdesc, there are: + * 'IPC_MAX_BA_SESSIONS' arrays for aggregation queues + * 'MAX_SINGLE_QUEUES' arrayes for singletons queues + * '1' arrays for broadcast/unicast queue + * + * Each one of this arrays should be copied compeletly to the FW, therefore we should + * cast all of the arrays to dma addresses. + */ +struct tx_queues_dma_addr { + u32 agg[IPC_MAX_BA_SESSIONS]; + u32 single[MAX_SINGLE_QUEUES]; + u32 bcmc; +}; + +/* struct cl_ipc_tx_queues - ipc layer tx queues */ +struct cl_ipc_tx_queues { + struct txdesc *ipc_txdesc_agg[IPC_MAX_BA_SESSIONS]; + struct txdesc *ipc_txdesc_single[MAX_SINGLE_QUEUES]; + struct txdesc *ipc_txdesc_bcmc; + /* Mapping of the TXQ's addresses to DMA addresses */ + struct tx_queues_dma_addr *queues_dma_addr; + /* DMA address of tx_queues_dma_addr */ + u32 dma_addr; +}; + +struct cl_ipc_host_env { + /* Pointer to the shared environment */ + struct cl_ipc_shared_env *shared; + /* TX ring indices (RD, WR idx & new_ssn) */ + struct cl_ipc_ring_indices_elem *ring_indices_elem; + /* RX buffers (rxdesc & dma_addr) */ + ptrdiff_t *ipc_host_rxdesc_rxm[IPC_RXBUF_CNT_RXM]; + ptrdiff_t *ipc_host_rxdesc_fw[IPC_RXBUF_CNT_FW]; + struct cl_ipc_host_rxbuf rx_hostbuf_array[CL_RX_BUF_MAX]; + /* Host last read idx */ + u32 host_rxdesc_read_idx[CL_RX_BUF_MAX]; + /* Fields for Radar events handling */ + struct cl_ipc_hostbuf radar_hostbuf_array[IPC_RADAR_BUF_CNT]; + u8 radar_host_idx; + /* Fields for Emb->App MSGs handling */ + struct cl_ipc_hostbuf e2a_msg_hostbuf_array[IPC_E2A_MSG_BUF_CNT]; + u8 e2a_msg_host_idx; + /* Fields for Debug MSGs handling */ + struct cl_ipc_hostbuf dbg_hostbuf_array[IPC_DBG_BUF_CNT]; + u8 dbg_host_idx; + /* IPC queues */ + struct cl_ipc_tx_queues tx_queues; + struct cl_ipc_enhanced_tim enhanced_tim; + /* Fields for single confirmation handling */ + u8 *cfm_virt_base_addr; + dma_addr_t cfm_dma_base_addr; + /* Index used that points to the first used CFM */ + u32 cfm_used_idx; + /* Tasklets */ + struct tasklet_struct rxdesc_tasklet; + struct tasklet_struct tx_single_cfm_tasklet; + struct tasklet_struct tx_agg_cfm_tasklet; + struct tasklet_struct msg_tasklet; + struct tasklet_struct dbg_tasklet; +}; + +int cl_ipc_init(struct cl_hw *cl_hw); +void cl_ipc_recovery(struct cl_hw *cl_hw); +void cl_ipc_reset(struct cl_hw *cl_hw); +void cl_ipc_deinit(struct cl_hw *cl_hw); +void cl_ipc_stop(struct cl_hw *cl_hw); +int cl_ipc_rx_elem_alloc(struct cl_hw *cl_hw, struct cl_rx_elem *rx_elem, u32 size); +void cl_ipc_msgbuf_push(struct cl_ipc_host_env *ipc_env, ptrdiff_t hostid, dma_addr_t hostbuf); +void cl_ipc_rxbuf_push(struct cl_ipc_host_env *ipc_env, struct cl_rx_elem *rx_elem, + u32 rxdesc_read_idx, u32 host_read_idx, enum rx_buf_type type); +void cl_ipc_radarbuf_push(struct cl_ipc_host_env *ipc_env, ptrdiff_t hostid, dma_addr_t hostbuf); +void cl_ipc_dbgbuf_push(struct cl_ipc_host_env *ipc_env, ptrdiff_t hostid, dma_addr_t hostbuf); +void cl_ipc_dbginfobuf_push(struct cl_ipc_host_env *ipc_env, dma_addr_t infobuf); + +#endif /* CL_IPC_H */ From patchwork Thu Jun 17 15:58:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F24C3C49361 for ; Thu, 17 Jun 2021 16:03:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF78761249 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 021/256] cl8k: add bus/pci/msg_pci.c Date: Thu, 17 Jun 2021 15:58:28 +0000 Message-Id: <20210617160223.160998-22-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:56 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e1d4803c-cc13-4d1a-a1de-08d931a95f58 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:923; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: L415dG700QzjDzum0P9kM61bZrEBRSuI4aQilQ3Ba0wNu36eMjZo5pmF9R6AWaQLBM29hpFZ3nBqodhdZZ+uOpgxpHGUTD5WWr129606SlIfeeUjW+8ycApli8BcDdlYdcTn5aasGmO7qFhwOxfEeVTKYc+o49AJ6rTqIqLcpyzZrQl8wxtOCR+M6ozds6t4Ra+nlkVo1SxqxTMQwBrLK5AJ4rBse3lpOOJT5OupjAO7HHsc3aWtIovTfxkxKV1rIoy0uO9v2Jxw3z8PnwNuVyT2Q1cKPtD+2nA1ak6xP1p6alm5+QRyxK14qSMqAqAOck3pFeOM25Sa4r9ca9oh3kigzFKXndc6xPIR892T9uzcOIRNWEbzLtUZbrmPIhpImJqRUPPzbG8fDuAfHvdC1TaHOTcaj6etuOZZdupwFOHt8S1I/ye1MAbaevTPopGlW7PndwL1oVyxVb8WB5u9o3D8ulZ5ElH+r/SZ4GGBFK26XHHOzhArXwClmISZcI8AmSterkYe+tNX0ieC1p6aWDnjnpRvVxCKk+WfrO6TsKYlgKxBvQo51DdetV7xXzdwBKFOG++Xw0c8Tus13f1N0pa6ZXMSnIS1Uw64aJYhrgiV/yOYUCZ/fZYS07GvpyWNH1tNrs/EoMC6CHcdXddrmP04Y9ioILsV5W9q5npV9kZqjNEBHjg2vSgVzc14K94vYmqhk85r7oW6bLRLwR7ncQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WVCFkAqqo9S7vhkLHkqaPV46C93UZC/cNWu2oUTJnQcS+EQQ+oblwpSoV8dpYmPqo8eOpp7WoVzd8MmcIzFMbArhBiQ+QXQoh+QIBb+izGUXtlxfWUphhqC9Mg5CnIHGOlikGOzrmyWQV5McC2kDJqlrW7tDbql3takIrFTF4aRuw2UoiBjMvrXASktr5okM4yuDGRfvHjPvkOpR27KobOuBqTB8+SxYKgJ3gzBqQbAUKilEsxt3HaU4nJiZJwTSWqBCTuJqsMGKix4vxdMq6UMmB36LYmq4BiOddVU6Cfy9KmjljIkyBSGyp53uXeYjpK8c8pYlI8NJrFOheLxOoHtv7LjFvraYa0soERfrkW/BQxKj/7DtOFCbdIKFGKtvmJebMpjv69CjEP5SiM2KMCxIOMZtogCCPpVNVaoJY74ki4JbNwu0LTeVzkqjfx8efXqmQShTM30rSpVaosjJnC5vKt6EffRK0uvMMA+zcNs2GOeFb1GFAco5c/qtQwRwEzTu6r30OAdLTE2NpS9PStDaP7EodVXIw1dbF5jO9A348NwoSDS+hACBrQW2bivt9Pgyi5kW7JaYzDV6bYfQVgw0aF92bYpSVZrt+spIPXFo9Ht8MbLtJkrSW1XBq6IcyIf0pRzPxN236se+Q/vGNhf6YoJep7EG2593uqWvVH0DKh2vaiWkRCfnut7gPIin/EeJCAZeL+h1gjHWPLRJENhtmI4YOFUDUmcN5P0cAuSRBYZ/MYXgyGHtP5/5OVNm4IWysdRSduCLg989tFZu0XPPn9g8r4POu95nhYE5BKfnTmcpWTpZoraaP844vdjC+5jT4FKNVrMEPDCm2FY/OCbonaeEswJ/WtYXsr/Wa7rlkM1n5Eadh9twXD+Af/2bIEkhbjxBlcwoWmGjw4C2gZe3sF11DxNeXu6+HxGC75T1/BXr3OKk92eT/0mqe9QjNpNu2q0H/Ir274khvjsVrn/Fy+2hPPq5+CpY7qiCVlt8LuATHLjry80CWf9kHE3zh9pB8SdSWTKMmSUD5a+SJnYs7QCI/bt5ZvLszDQWtNv/9cffCiE/6iQkQ2UAEYEQYyUZ4prs8HFLjbhsIdN7/mE8pztleEsC4Xj4ExZM4KRePKba+xiEi7i6BQN+Un5wwKGeCODAYOqI9roSpg6NqOGeZQc8OZ5l5Dj1dImnmMyQqrZexv8ZbAMBRq4OL2BokdwZNRxIGOJ/lR/zW+wvXbEswGgA+G/nnmhTSIK/UvJNr1APOEWiviG/nYHOKMKmWx593lVCWuOdEo4djVwGYIXukkYuHPpy47rSOpJxCiDUmdiGibxa0zaAWIBxfEaH X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1d4803c-cc13-4d1a-a1de-08d931a95f58 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:56.9848 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Enh3wZNByzRAvI0ZDgThjPb9yJeEMiruBAeeh1ZDR+IZJrCZ3BbtrMv0MKDnO69xdz3UtqPAVNhi19AP8zTY/Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/bus/pci/msg_pci.c | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/bus/pci/msg_pci.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/bus/pci/msg_pci.c b/drivers/net/wireless/celeno/cl8k/bus/pci/msg_pci.c new file mode 100644 index 000000000000..4ddc060940c1 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/bus/pci/msg_pci.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chip.h" +#include "hw.h" +#include "bus/pci/ipc.h" +#include "fw/fw_msg.h" +#include "fw/msg_cfm.h" +#ifdef TRACE_SUPPORT +#include "trace.h" +#endif + +static void cl_msg_pci_fw_push(struct cl_hw *cl_hw, void *msg_buf, u16 len) +{ + /* Send a message to the embedded side */ + int i; + u32 *src; + u32 *dst; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + + /* Copy the message into the IPC MSG buffer */ + src = (u32 *)msg_buf; + dst = (u32 *)&ipc_env->shared->a2e_msg_buf; + + /* + * Move the destination pointer forward by one word + * (due to the format of the firmware kernel messages) + */ + dst++; + + /* Align length of message to 4 */ + len = ALIGN(len, sizeof(u32)); + + /* Copy the message in the IPC queue */ + for (i = 0; i < len; i += sizeof(u32)) + *dst++ = cpu_to_le32(*src++); + + /* Trigger the irq to send the message to EMB */ + cl_hw->ipc_host2xmac_trigger_set(cl_hw->chip, IPC_IRQ_A2E_MSG); +} + +int cl_msg_pci_msg_fw_send(struct cl_hw *cl_hw, const void *msg_params, + bool background) +{ + struct fw_msg *msg = container_of((void *)msg_params, struct fw_msg, param); + u16 req_id = msg->msg_id; + u16 cfm_bit = cl_msg_cfm_set_bit(req_id); + int length = sizeof(struct fw_msg) + msg->param_len; + int error = 0; + + if (!cl_hw->fw_active) { + cl_dbg_verbose(cl_hw, "Bypass %s (firmware not loaded)\n", MSG_ID_STR(req_id)); + /* Free the message */ + kfree(msg); + return -EBUSY; + } + + if (test_bit(CL_DEV_FW_ERROR, &cl_hw->drv_flags)) { + cl_dbg_verbose(cl_hw, "Bypass %s (CL_DEV_FW_ERROR is set)\n", MSG_ID_STR(req_id)); + /* Free the message */ + kfree(msg); + return -EBUSY; + } + + if (!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) && + msg->msg_id != MM_RESET_REQ && + msg->msg_id != MM_START_REQ) { + cl_dbg_verbose(cl_hw, "Bypass %s (CL_DEV_STARTED not set)\n", MSG_ID_STR(req_id)); + /* Free the message */ + kfree(msg); + return -EBUSY; + } + + /* Lock msg tx of the correct msg buffer. */ + error = mutex_lock_interruptible(&cl_hw->msg_tx_mutex); + if (error != 0) { + cl_dbg_verbose(cl_hw, "Bypass %s (mutex error %d)\n", MSG_ID_STR(req_id), error); + /* Free the message */ + kfree(msg); + return error; + } + + cl_hw->msg_background = background; + + CFM_SET_BIT(cfm_bit, &cl_hw->cfm_flags); + + cl_dbg_trace(cl_hw, "%s\n", MSG_ID_STR(req_id)); + + /* Push the message in the IPC */ + cl_msg_pci_fw_push(cl_hw, msg, length); + + /* Free the message */ + kfree(msg); + +#ifdef TRACE_SUPPORT + trace_cl_trace_cl_msg_fw_send(cl_hw->idx, (int)req_id); +#endif + + return cl_msg_cfm_wait(cl_hw, cfm_bit, req_id); +} + From patchwork Thu Jun 17 15:58:30 2021 Content-Type: text/plain; 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Thu, 17 Jun 2021 16:02:59 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 023/256] cl8k: add bus/pci/pci.c Date: Thu, 17 Jun 2021 15:58:30 +0000 Message-Id: <20210617160223.160998-24-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:02:58 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 776cb767-edc8-4bbe-b6d6-08d931a96087 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M+3N3cbMDe1Vux7eYSyvGC20YlLr0YohT1pDa4eOXQYWlt8wOGTSkh1TZo2oMYiikhUb9YfXonQAd1T2M0FhWlFan2rFMaCIFJx89ZHLqqvjmYhIH6my/zDpoKll3mX5gcuEkj8n71tDhxYETVxOGAByx3tv/4O6lwDf8kdMF0lSHy/g8fOW8MBe7nGqDjM1BWhevQjb3Vh5vUozQaX0hSsaYE09Md6Fs/6i6YghIzhQ6SezCxtNcU73ObuvfpfgZ73qLvjvHItPqXo3acvgVFBIqv6gPfhth2ICFFGz2TwN1pWL5imnkOOys0WmcMSkfDuwDlQTkLmKrXXzYHnoRc57wGd3yntrjxbnb2Dfgwp0OcMzpY2IGfHHHUIk6K3kLNuQn6GFwuFtWTzWtbwTRw4KYm+qBNPLBzl/s926cHGxROqJ6CDDM/yg/XknM3p2EXpGJuN0LLG2Mytp/cl3Pl/MlQHCljRZYIxgFZCiYeo8olC64asILKwvb+v/TeLZ3MEaaQDJVsRkJuV25fz+M67ngb7ceq3Ff3WwmxD1qrqL1HzOB3aTivSyPn4Xpm+tAVkiv4Awqxgz+Z/fFNCE0aXD5p/8O5E05/nBv4u4swJqMTpplZK2I6tgVYzXGeJuHyTHIT6FdV/IOxmtclbkn81XYK+0CW7CwJdBGFjV5idz5hBZMDFsEn64qVNQP3eCtyfCXzo0eCoJ8LNRkEQnhQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /WeH96jDA8s6y1IVojrmJoYQ+Pt1EG+ucFCTqloXKWQHqJWjLtlEG73/dSrzOKd4LEp4IPGmx56ogXAzoC+qlAbsSyC6Sn5R+2n9ugnx6FhgZB70OeUoWuoGflaA4bk9QnEg19YcrhWitXoHpjqZLvWS8hwqfzNr/cCZOk3GAs5qDA7v+nz2EZ5rZfoWKQNWbGR5uzwTVf2I3tMUWy12J6AFvv5fbg/nhnhA7gjsWj2mmJYEEMh7oGVU5VX7NmigXsO3pDgvwFt41/ARG40b0Xc8J7iBsfv2P6dNwqcqiRjzyP4n74K1d0HikTCkwo80+EQJYxNcTDrhYxi/fZvA8IurnRbSLR5FkNdxQcEuHq8JHD9YnKW0soPBW7IUK75Qtae4x0ZuFHWzUfF186ndKKyxNDn5e01D/d8KLhWDyMMpcfHyEZaocdj0S6fpEHfK6WNQnlEKUMBFjzBHWVGd8XVRkTqP7bfWWqgywm+7eqYPnIyt724aqMkW/Q74HGDeOn585Yu8Q/ndrj9hZepPIQ+Va6hh6ecmOCh0EKxwpsUXSXzlBaTXVjbUTLGVHnA3eFjkImgn7IN8zpI2mS5NZ4RDwGlmRrlB1a613Rz/5UrCA3yaSLZRJKPkrtXB2PvE/1buU/vz/JqgX+TlszcC//i+y3cAKbyMfVgO04UpHHPQBbaE5ORx59RWCQGV8/3KTcf5Am2xDnHnxJA0jfLPSd6Fco/FLw6Grk8Uoe1YlpDxbXJGus5gRnCin/oJaMc8+oAkxYQyxMnKrEIreG8wppFtbsCW/aAEn9hExEeUTEndvp/m3Kx603Z1ghZgE+onQQnjQhKR/RAyqeWfQRAoxMFF2F99OaXHYbG8vNSSBW7gwcUVkW5NK6iYol/Noak5yHbv3kW1RIzGiuxdEMf/TMCiqFmRz8sX8SBgLD137sXAZiW/+TZH9+b0PL1D5Hftx4k/bcL2AqsHJJR07oVasOa/rHqFvh6KiAEq36syTYv12E5OVJuWyG2etMLpl7XGcp6IsqVXq8IH8WnYqB96nLk1ceoeg4TU9vTfYEq6mc/sDsl3XBqPFOZcQFR7UmGhufTlPcxBSnmBTpweAFfI43X3FUCPQLjLZ9YaEHL3QBbvG84p+nwMMbNu5iIw7VWJsRWQTLaungQyJCb1WokbLDyf/V9JOjvQ+c/YzQ0DkIoIEn5VnvwbTTIaQXWZ8Mb8B0mTeXjQ0yYclBe3vBnXUkLMRQtZbqQ4HcPtaW8zi9T3GQOQS2f9rIoFn9IlM+dFWQ69zG8xs1RAN9uv2yBqBWEuRvQsf2xmD0eP9Z53eQtRmdr3dbxivodIxsh8INq1 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 776cb767-edc8-4bbe-b6d6-08d931a96087 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:02:59.1035 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ds6vvgFjOUL+/21ZwWLAHWFdYZ79uKZTSoJWrMyrt8FFDgZhb3mHOJXA/2sieVSn8ajhIheIffu/XkeP8ZwvzA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/bus/pci/pci.c | 210 ++++++++++++++++++ 1 file changed, 210 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/bus/pci/pci.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/bus/pci/pci.c b/drivers/net/wireless/celeno/cl8k/bus/pci/pci.c new file mode 100644 index 000000000000..a9c2eebaeb1f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/bus/pci/pci.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chip.h" +#include "hw.h" +#include "bus/pci/msg_pci.h" +#include "bus/pci/tx_pci.h" +#include "bus/pci/rx_pci.h" +#include "reg/reg_macsys_gcu.h" +#include "main.h" +#include "ela.h" +#include "debug.h" + +struct cl_pci_db { + u8 device_cntr; + struct pci_dev *dev[CHIP_MAX]; +}; + +static struct cl_pci_db pci_db; + +void cl_pci_get_celeno_device(void) +{ + /* + * Search the PCI for all Celeno devices. + * If there are two devices sort them in ascending order. + */ + struct pci_dev *dev = NULL; + + while ((dev = pci_get_device(CL_VENDOR_ID, PCI_ANY_ID, dev))) { + pci_db.dev[pci_db.device_cntr] = dev; + pci_db.device_cntr++; + + if (pci_db.device_cntr == CHIP_MAX) { + if (pci_db.dev[CHIP0]->device > pci_db.dev[CHIP1]->device) + swap(pci_db.dev[CHIP0], pci_db.dev[CHIP1]); + + break; + } + } +} + +static u8 cl_pci_chip_idx(struct pci_dev *pci_dev) +{ + if (pci_db.device_cntr == 0) + cl_pci_get_celeno_device(); + + if (pci_db.device_cntr == 1) + return CHIP0; + + return (pci_db.dev[CHIP0] == pci_dev) ? CHIP0 : CHIP1; +} + +static const struct cl_driver_ops drv_ops = { + .msg_fw_send = cl_msg_pci_msg_fw_send, + .pkt_fw_send = cl_tx_pci_pkt_fw_send, +}; + +static int cl_pci_probe(struct pci_dev *pci_dev, + const struct pci_device_id *pci_id) +{ + u16 pci_cmd; + int ret; + u8 chip_idx = cl_pci_chip_idx(pci_dev); + u8 step_id; + struct cl_chip *chip = cl_chip_alloc(chip_idx); + + if (!chip) { + pr_err("Chip [%u] alloc failed\n", chip_idx); + ret = -ENOMEM; + goto out; + } + + ret = cl_chip_config_read(chip); + if (ret) { + cl_chip_dealloc(chip); + return 0; + } + + chip->pci_dev = pci_dev; + chip->dev = &pci_dev->dev; + chip->bus_type = CL_BUS_TYPE_PCI; + + pci_set_drvdata(pci_dev, chip); + + /* Hotplug fixups */ + pci_read_config_word(pci_dev, PCI_COMMAND, &pci_cmd); + pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + pci_write_config_word(pci_dev, PCI_COMMAND, pci_cmd); + pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES >> 2); + + ret = pci_enable_device(pci_dev); + if (ret) { + cl_dbg_chip_err(chip, "pci_enable_device failed\n"); + goto out; + } + + if (!dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32))) { + cl_dbg_chip_verbose(chip, "Using 32bit DMA\n"); + } else { + cl_dbg_chip_verbose(chip, "No suitable DMA available\n"); + goto out_disable_device; + } + + pci_set_master(pci_dev); + + ret = pci_request_regions(pci_dev, chip->pci_drv.name); + if (ret) { + cl_dbg_chip_verbose(chip, "pci_request_regions failed\n"); + goto out_disable_device; + } + + chip->pci_bar0_virt_addr = pci_ioremap_bar(pci_dev, 0); + if (!chip->pci_bar0_virt_addr) { + cl_dbg_chip_verbose(chip, "pci_ioremap_bar 0 failed\n"); + ret = -ENOMEM; + goto out_release_regions; + } + +#ifdef CONFIG_PCI_MSI + if (chip->conf->ci_pci_msi_enable) { + ret = pci_enable_msi(pci_dev); + if (ret) + cl_dbg_chip_err(chip, "pci_enable_msi failed (%d)\n", ret); + } +#endif + + step_id = macsys_gcu_chip_version_step_id_getf(chip); + if (step_id != 0xB) { + cl_dbg_chip_err(chip, "Invalid Step ID: 0x%X\n", step_id); + ret = -EOPNOTSUPP; + goto out_release_regions; + } + + ret = cl_chip_init(chip); + if (ret) + goto out_chip_deinit; + + ret = cl_main_init(chip, &drv_ops); + if (ret) + goto out_chip_deinit; + + if (cl_ela_init(chip)) + cl_dbg_chip_err(chip, "Non-critical: cl_ela_init failed\n"); + + return 0; + +out_chip_deinit: + cl_chip_deinit(chip); +#ifdef CONFIG_PCI_MSI + if (chip->conf->ci_pci_msi_enable) + pci_disable_msi(pci_dev); +#endif + iounmap(chip->pci_bar0_virt_addr); +out_release_regions: + pci_release_regions(pci_dev); +out_disable_device: + pci_disable_device(pci_dev); +out: + + return ret; +} + +static void cl_pci_remove(struct pci_dev *pci_dev) +{ + struct cl_chip *chip = pci_get_drvdata(pci_dev); + + if (!chip) { + pr_err("%s: failed to find chip\n", __func__); + return; + } + + cl_ela_deinit(chip); + + cl_main_deinit(chip); + + cl_chip_deinit(chip); + +#ifdef CONFIG_PCI_MSI + if (chip->conf->ci_pci_msi_enable) { + pci_disable_msi(pci_dev); + pr_debug("pci_disable_msi\n"); + } +#endif + + iounmap(chip->pci_bar0_virt_addr); + cl_chip_dealloc(chip); + pci_release_regions(pci_dev); + pci_disable_device(pci_dev); +} + +static const struct pci_device_id cl_pci_id_table[] = { + { PCI_DEVICE(CL_VENDOR_ID, 0x8000) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8001) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8040) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8060) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8080) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8046) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8066) }, + { PCI_DEVICE(CL_VENDOR_ID, 0x8086) }, + { }, +}; + +static struct pci_driver cl_pci_driver = { + .name = "cl_pci", + .id_table = cl_pci_id_table, + .probe = cl_pci_probe, + .remove = cl_pci_remove, +}; + +module_pci_driver(cl_pci_driver); From patchwork Thu Jun 17 15:58:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1CC3C49EA3 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 025/256] cl8k: add bus/pci/rx_pci.h Date: Thu, 17 Jun 2021 15:58:32 +0000 Message-Id: <20210617160223.160998-26-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:00 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e648c90c-9e5c-4f34-267c-08d931a9620e X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: C/YaLueHdthfWHKOPqQlX0xboLtoMG1l8u3a81yopQ1xTnb1F+ASywpJTaDol5/bhA6Y2Du7fYl92EbjSkkuKnb3kDEK6YQY7fn+sChyFqKKYuTudz2pPQzctMaXoY9m1oxpDOlt9FA5Wur8Uki2RyLNe780As6Rtg8IBkWQzlQQbdrMZAqo1SatMn02urF8Tgp6g+wlC+4E+3TZwhb285CbDi+TLoxRFIjF1X2XTNZeuuGd1EtxLQpc2MtdSIHiEWl04DC0ZdWNGKWHdQZRl6bW6EnUrrTa7jpiI0wq0UABHssUY59CIjcG1jXXnCUNZ/awDQjvnzgYUep1QWmjm2enp/iPyVJhvFEgkIICAtdxYEY71dY2hdNjAV05Byuf2HMOTHGVl18G0+50iuzbTcjpMeS3QqqWN7ZsQKeM1UzadJPinAA+Pu7qG+tc5/zVBJZ0NGwIKn3yi0P5SnatUOV9M0haUEWk7qxDHLqIwFJ5iO1OnaS6sFfiGIOcxBZ1fbfwa3T8MhfXGnYVuZMlT1pooRuUuHLavAEhbsfWrYs3iqOJg4T4TTuLuoXL/05Bq/Zwpu+HuO7rYHna+a/kLb5PWCutw3VTQxbbjNX8uaZj3nEP0shFitoz8TzyYepQEfXMABEeDVWnYP0UpTVC7jISBnpD7uDrsAkAqUV3ef6Y05ZF9yI7brhfqWJaE2vG2yxtPtZXt+tDMU2kMUYnrw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SfMKueb5radihOXk4M9gfnipMG1LT/LKw0aQLuduJodnc7LH8M+KJ1kfd/ETI5KJA6a9Wy/2zSgzmXRV1tQqXoepDtxKrx43WhFSa5VvuGhEnklA6KjoTSn9nEwfrPED3hm/AN6BcmkPKoNfntchuHDUMCWA5iX/P0JkmGUVVV6OVsP9Qeg7v3Tkjf/+NTiacfagBp8yaxL91UbcfFsIb2bwIC9zXfVNz+0uifCKZiRg3zHISptDkcu0hbSwd1bfLlCOhrFbGZl/MpaPeX7uzAKxzWv5hKrzqS8PcmCu4bdunkwyd1I1w50Z2sQbIXPFtX34mQ9FokCnuyFC6TPTfm2sTVxcuMb4yyfgszBrAN+u+GeycxEiiCY5+xKnyC9GwF4Kk1MMs8TO4I4wKYHGHXYx+aHxkfILFQPi8D8UCPHozgDYfLOcHdjXdehMSbx2xaVFLe6aLggc3oMArUMAetA7KCStKbJplJjGwLWbv2GjKFBChfUzDXFTbmLY1mP1rRcKeisL0yCenA1CFNilUZD2Os+Ogx3cytz77chepGpV6E9vulqCnc2ZUyTOL7ArM4s/VfF3iH+f+87fXPhHtWAP0FbzXPtKUGFdAek59635V5YZ1iLX1Y/0KXgfUgvRhJ3XPyXrYb5nqNSTx64I78dDDcL6SXtMokdfQRmlWxlZVrCBbszHSd1Sc0vP+QWGuQ8RUsAOa501IDAKwSPmLzxL4GHe/HLsyOD4r8Z5EU3YheFoa4HrILgvRxFlO8v54qZYhbTwDMnS9HTjRlONcZiajlZnGP0TrHQDpM+DyGZlXd6MZu5FPzaB8u9a6nYe6D0+SmfsfKJdtF4DDTZvH2MHT3rlFJWwhSEEeV45zg6Io7GeqTKpAGSZxd5GMgo2NpwcCTTzeGDaArFjqvwB4HQNct8zDFMbogsrX8PQiUhEsK2ncrAX64LwAuLiX6eCx2/yjL6KCpcYeboMMGHzOQW36zv/uW1lVvU6HaElXJWcLODbDet/xGfUgJ2e60RQXZXTGFHcVP173hA3Q2O/3/65zVUD3kZxuApdc0n/m+Uc9p8xWB6M58E1cYf9L5P7H2bQ+wZ29fPGKGgyo30RVRmJ+wg4iePVF4DrvcDZg1KfeYPSnC/c/3sZfPU7M9DEfU5HY8l2iPMoe7+T+g0DMaNbi00aWdp6UGd9Rc/b0MI8MGpEWL4zb/EiFvwvhS9DP+sM45faoeuyO3CAZ66sf/ujlaM5U7vngivPl/l7uFVAoopbcpAuEog/68SCchcm+RkNe9a+796imGIxeaG5cW53FcWuY8dpshlGguKLkAbMzjvqxjeKz6Ppe1zfG0Ja X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: e648c90c-9e5c-4f34-267c-08d931a9620e X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:01.5348 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JEPdoENDAA3YOXt7/kzkf71rENGYUQO7F/02D+rjjcJiDBc0OIPYrbDeEWP5EPAtOydKU7bvh0WriHH3z40ccQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/bus/pci/rx_pci.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/bus/pci/rx_pci.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/bus/pci/rx_pci.h b/drivers/net/wireless/celeno/cl8k/bus/pci/rx_pci.h new file mode 100644 index 000000000000..71dceddffb84 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/bus/pci/rx_pci.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_RX_PCI_H +#define CL_RX_PCI_H + +#include "hw.h" + +void cl_rx_pci_init(struct cl_hw *cl_hw); +void cl_rx_pci_deinit(struct cl_hw *cl_hw); +void cl_rx_pci_desc_handler(struct cl_hw *cl_hw); +void cl_rx_pci_desc_tasklet(unsigned long data); + +#endif /* CL_RX_PCI_H */ From patchwork Thu Jun 17 15:58:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DC10C2B9F4 for ; Thu, 17 Jun 2021 16:03:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 716356120A for ; Thu, 17 Jun 2021 16:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233604AbhFQQF3 (ORCPT ); Thu, 17 Jun 2021 12:05:29 -0400 Received: from mail-vi1eur05on2073.outbound.protection.outlook.com ([40.107.21.73]:38880 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233543AbhFQQFR (ORCPT ); Thu, 17 Jun 2021 12:05:17 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Noo9wRAQi+uKNt+YByopryEpJHhSvK3EpQBdH7gAqFhliQ2ASInnUtgwFBr+OFLBiPRV6r6ApdoeILrhCt9ZZ0El15vOr6q1oIMEeq9sVoECpn11n8jSHDh/qsQSSV5RhyhG6h9RhbjQU67FYBcLUPHyeRV9MGA/t/+iUvb7l975fvhdhKyO4luJoPHy5+LldwvujNso7ZE+LDC5yDvksZ4EJOFuvjZ6bAfDezX9YRAp4lKrEJWD+NZKpKJv+gxNNpqTIxc4NQu6X/8z9Olb4yHsK6+LkjNdqmGArOCSlMIedCo1YbJxkY7xqxn8A5S/SxVdCA+KrkKqFTdmpyWgOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iD/41sEriRtup+4fF6oWf/011z9oOz3y+id2pp+iDXU=; b=BvAurTV5v5nlLbnkAoa+F083pb7pUpATaucMCirPwcx1LRudO/t+FGEzm+J4tKFrAur799YueG5tTJ5CKD+rrAVAdPC3jBEqA8mqcHA3XOcTY9jMk//q97nYDu7pCPONt9ZDD8Li2UzEOlJViIboP1oZfsl53sdQOPSFPwYU9y8CGyyywYAx+lCKXp7Lf9Q/4FwGHHiyj12r93k4KRdRBXrhCIyJFQIFcZQLHEH6eKOEemm+elR16s0w9m9ruEvVZL4K51rCYEZrZGQRijntOYgKmESmL35csbtzW47rrS60rar+VVMvJVtVwMlFKsdSPyw7zctLElkctrhps5ijOg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iD/41sEriRtup+4fF6oWf/011z9oOz3y+id2pp+iDXU=; b=XcJHrTCwOWj52AOhemfOhHXvLnU9pHGqtPcetxTMGRFpepKT+2m+58YPcxJcuveJSDNG//eN3nO/Odyor9hx7p4+yL24sQYiJO4j6PXhLE4wWXV19Uiy2EU1GnkGlOFMhu86dLufQ8ci/fJXCoiner4RlO2ouh5raVHH74kAMZ8= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0499.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:03:02 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:03:02 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 026/256] cl8k: add bus/pci/tx_pci.c Date: Thu, 17 Jun 2021 15:58:33 +0000 Message-Id: <20210617160223.160998-27-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:01 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a8b3a71-8792-45c4-6066-08d931a962b2 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cy2zA+p1JFQhpk9byWFstmicGB536LdvixeN0cHy8aEpj8Wd3t6qaWDQ+AJzDe/AGuTnY13hvknyzAEowDVEuEt4tUvZGTJUWAUPWgnFmYpZMzPGEwXwsn3MPJdIwrlAgd7TJs5mo//bXHAsWwDTJl//EOfol/06xcgED6nm1LUvhBeATW8fttLY9lhv2c9V4n/Ts2F/hkaNhVGnv22B2J0lPHeQdAYk6byGa9zCMCZYq7MlPvo/RLeKFmcQBN5hTa3PdA+RB8cpJAFvaBAZtqRsut3i078C02zi7K3x1o1ErvgwcXkP8BzlBgF0HK1nsLqLW7qGsMe2PNNIQyl0zBG9C+i6IJzZymqfeuGfGWcT/I+UvuAXDZDKZdgHMwmxHvmRIFuLw0AZQwEl/KWitHU8BYPKHW9er80sxfwFzys+btolmmCqnMhd9fErJQKMpcufuSzL9DCcZYYZjmaeLpYUOIxIcAQYAnqTOYhZrt2rluUX0bUAj5qjzzA91Hd22aLyj0LTVO+z/uUxpYp8kOf8UmRWkU35ok3X8cskoXyk8yT5OOCKxPpxefFhm6ZT15pfkG/vEM3v6sA0iUFzHlDIEpez3VaGPP1U+2hJuqnDzm6Zxe1hJH1cQUDa9oa0H+aHgS1W7XWCiOUB0gzAbUGxKpHjTkDOKGU3nzTQI9YBWpb/Moqiz8Qs5urNtWhyJKvHiGpr+0liy9TOgHQCNw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(30864003)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YYXjy5PV1H2Sbg0m2m9KHXdkyTvu4fjjBjVyQy0x5b3bYL0TKnyXn9p/f858hGHIFIDpyOE42FvwJdlg4BcUj2R7cfXFifpvFD3bd2YnHX7d0SiWOsmlPJMnv8g2Ze1pNrUbCsnnAaSPNVmq5MdoZbKFdTQECkFCVpMv4mhsrHCms8m3Aci2zVJfuQl+sWbDT1x7D3zZORls5K7rBeBKqgF0cUF55ALzuHPUNQ/a2xNgNv3G/d1PEf8dzzBn11B7LxV3nQ/8a1nas1rf3fT7zkIsFd9Y0u/vBtaFhlinItsiTko+ssaLJxMeXkVLtp4+HEITZaN4cvkKqMiIjSF6kqBT4z4bNmIXixW9WdXS75Ttg6b1tkiumHpi+Jx9nLop87k9WMY077kXGaa7HOlrdBaZ6kecaVdtKX3idOVxO01GbyZxQzZR5lNYqLhbAPoSSRXKBS//kgTg4nn9E/wbKeQn+vbolehl65A8ZXGujHBzdpPDnp7txNaCggVE8aZ1tvHIwNv8DDm70U9qh2FSdJbxaNtcyT3DT45PGrqO7H5H/GwlfOxR1ouHaSQI46bEqrz0Owepm8Pz1asrcmTzY82CIIE/kuyd0vEq06I9+/CcfyQmB8yPbSNTQu6kXs9x4S1r0GfndIO9Le1znwsROk9BKTs4WMRUam9n8WyuVLZ0c1bqqbCEC1sdYiHw26U3WIlg/xLVLVZOs/Vdy8loudU6P4XFwduuef93sjolhRB3MTiu6ex6k9x2XaG2ELKnJ7qUNjr/QMBvz1i8WzYIWeLzJte+z+kQeloy4GJwva02Q4+vpMNH1mDLohrWPeRPfejX/quNIeSEwEtbijKwIFEfF5mQZ3SKPrcadJXlrWod6ll7ME/K20zdyeS9ATJ0mtp9A2CZbFNXq/8pO6j593bcV8PLDgCZNpIbP54+kUGUGa0X0VnzpxKX4pjCoVuq8l+lhAdgpCjUqia17hwOwHdwxAbzKeq4V2/3FaLxKErXSw7CFPPdFy5q7ziE2ZYqNsaoKANZTlq7RboGxpjUlPE1kxw28Y6lHmTP66br02zJcd0tYdrFCLOCb+n5OX1AWMovyY/dWpp4iojtekyjMSx/Ow2jVFgyjZpe2zeb+5ayjRUULaIqIthy8Sun5SlgWak6Gqew8dOrF5mAoChgGLAFKZ7gnwV0Y7Y5x7krGu3Z0wTql2l2QK3i6zQHyh3wI2husylZpRx5yxxzr9NgeS0VilDYaSbfizt4+8pIvtnmBQmcPMYF3z16RxVwNY2jAsNhQtGzddizV9tT2tS2qkWwG6jSxBYJAMPxF5zm4cQ9kirOQEJAfD9Uf6AMnA7O X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5a8b3a71-8792-45c4-6066-08d931a962b2 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:02.5981 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NnDbyZWVlmMt8CG3z85O5diYt+x3t26SGqSB8YfxXYmkQZQ82tlV7Dt8nMIg99gd59DBM7G482YtUMkZ85u4wA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/bus/pci/tx_pci.c | 434 ++++++++++++++++++ 1 file changed, 434 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/bus/pci/tx_pci.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/bus/pci/tx_pci.c b/drivers/net/wireless/celeno/cl8k/bus/pci/tx_pci.c new file mode 100644 index 000000000000..4aeaa6a74777 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/bus/pci/tx_pci.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "bus/pci/tx_pci.h" +#include "bus/pci/ipc.h" +#include "ipc_shared.h" +#include "chip.h" +#include "tx/tx.h" +#include "sta.h" +#include "enhanced_tim.h" +#include "tx/bcmc_cfm.h" +#include "tx/single_cfm.h" +#include "tx/agg_cfm.h" +#include "tx/tx_queue.h" +#include "tx/agg_tx_report.h" +#include "tx/sw_txhdr.h" +#include "tx/tx_inject.h" +#include "bus/pci/irq.h" +#ifdef TRACE_SUPPORT +#include "trace.h" +#endif + +static void cl_tx_ipc_txdesc_populate(struct cl_hw *cl_hw, struct txdesc *txdesc, + u8 queue_type, u32 ipc_queue_idx) +{ + /* + * 1) Request allocation of txdesc associated with queue type and index from the ipc layer. + * 2) Populate ipc-txdesc with the received txdesc. + * 3) Increase write index - (must be last action since FW fetch WR idx first). + */ + u32 *write_idx_ptr = NULL; + struct txdesc *ipc_txdesc = NULL; + struct cl_ipc_ring_indices *indices = cl_hw->ipc_env->ring_indices_elem->indices; + struct cl_ipc_txdesc_write_idx *txdesc_write_idx = + (struct cl_ipc_txdesc_write_idx *)&indices->txdesc_write_idx; + u32 write_idx = 0; + u32 masked_write_idx = 0; + + switch (queue_type) { + case QUEUE_TYPE_AGG: + ipc_txdesc = cl_hw->ipc_env->tx_queues.ipc_txdesc_agg[ipc_queue_idx]; + write_idx = le32_to_cpu(txdesc_write_idx->agg[ipc_queue_idx]); + write_idx_ptr = &txdesc_write_idx->agg[ipc_queue_idx]; + masked_write_idx = write_idx & (cl_hw->max_agg_tx_q_size - 1); + break; + case QUEUE_TYPE_SINGLE: + ipc_txdesc = cl_hw->ipc_env->tx_queues.ipc_txdesc_single[ipc_queue_idx]; + write_idx = le32_to_cpu(txdesc_write_idx->single[ipc_queue_idx]); + write_idx_ptr = &txdesc_write_idx->single[ipc_queue_idx]; + masked_write_idx = write_idx & (IPC_TXDESC_CNT_SINGLE - 1); + break; + case QUEUE_TYPE_BCMC: + ipc_txdesc = cl_hw->ipc_env->tx_queues.ipc_txdesc_bcmc; + write_idx = le32_to_cpu(txdesc_write_idx->bcmc); + write_idx_ptr = &txdesc_write_idx->bcmc; + masked_write_idx = write_idx & (IPC_TXDESC_CNT_BCMC - 1); + break; + default: + cl_dbg_verbose(cl_hw, "undefined queue type %u\n", queue_type); + WARN_ON(true); + } + + ipc_txdesc += masked_write_idx; + + memcpy(ipc_txdesc, txdesc, sizeof(struct txdesc)); + + /* + * Update write pointer only after new txdesc copy is done since FW + * fetch WR pointer first, if not, FW might read and old txdesc since + * WR index indicate txdesc is valid. + */ + *write_idx_ptr = cpu_to_le32(write_idx + 1); +} + +static int cl_tx_pci_agg_cfm_handler(struct cl_hw *cl_hw) +{ + struct cl_agg_cfm_queue *cfm_queue = NULL; + struct cl_tx_queue *tx_queue = NULL; + struct cl_ipc_ring_indices *indices = cl_hw->ipc_env->ring_indices_elem->indices; + int total_cfm_handled = 0; + int free_space_add = 0; + u16 new_ssn = 0; + u16 prev_ssn = 0; + u8 used_cntr = 0; + u8 ba_queue_idx = 0; + + for (ba_queue_idx = 0; ba_queue_idx < IPC_MAX_BA_SESSIONS; ba_queue_idx++) { + + spin_lock(&cl_hw->tx_lock_cfm_agg); + + cfm_queue = &cl_hw->agg_cfm_queues[ba_queue_idx]; + if (list_empty(&cfm_queue->head)) { + spin_unlock(&cl_hw->tx_lock_cfm_agg); + continue; + } + + tx_queue = cfm_queue->tx_queue; + free_space_add = 0; + prev_ssn = cfm_queue->ssn; + new_ssn = le16_to_cpu(indices->new_ssn_idx[ba_queue_idx]); + + /* + * Continue to free skb's until: + * 1. list is empty. + * 2. agg ssn is equal to new ssn received from ssn. + */ + while (!list_empty(&cfm_queue->head) && (cfm_queue->ssn != new_ssn)) { + cl_agg_cfm_free_head_skb(cl_hw, cfm_queue, ba_queue_idx); + free_space_add++; + cfm_queue->ssn = ((cfm_queue->ssn + 1) & 0xFFF); + } + + /* Sanity check. test if all skb's marked to be free. */ + if (unlikely(cfm_queue->ssn != new_ssn)) + cl_dbg_err(cl_hw, + "ssn diff - queue idx=%u, new ssn=%u, prev ssn=%u, cfm ssn=%u\n", + ba_queue_idx, new_ssn, prev_ssn, cfm_queue->ssn); + + spin_unlock(&cl_hw->tx_lock_cfm_agg); + + if (free_space_add > 0) { + spin_lock(&cl_hw->tx_lock_agg); + + if (tx_queue) { + tx_queue->fw_free_space += free_space_add; + tx_queue->total_fw_cfm += free_space_add; + + /* + * If FW used all packets that driver pushed to him, + * clear the enhanced TIM bit. + */ + if (cl_txq_is_fw_empty(tx_queue)) + cl_enhanced_tim_clear_tx_agg(cl_hw, + ba_queue_idx, + tx_queue->hw_index, + tx_queue->cl_sta, + tx_queue->tid); + } + + spin_unlock(&cl_hw->tx_lock_agg); + + total_cfm_handled += free_space_add; + } + + /* Optimization - avoid running the for loop IPC_MAX_BA_SESSIONS times */ + used_cntr++; + if (used_cntr == cl_hw->used_agg_queues) + break; + } + + return total_cfm_handled; +} + +void cl_tx_pci_agg_cfm_tasklet(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + int cfm_handled; + +#ifdef TRACE_SUPPORT + trace_cl_trace_tx_agg_cfm_tasklet_start(cl_hw->idx); +#endif + + cfm_handled = cl_tx_pci_agg_cfm_handler(cl_hw); + + if (!test_bit(CL_DEV_STOP_HW, &cl_hw->drv_flags)) + cl_irq_enable(cl_hw, cl_hw->ipc_e2a_irq.txdesc_ind); + +#ifdef TRACE_SUPPORT + trace_cl_trace_tx_agg_cfm_tasklet_end(cl_hw->idx, cfm_handled); +#endif +} + +static void cl_tx_pci_single_cfm_handler(struct cl_hw *cl_hw, u32 cfm_status, + u32 dma_addr, u32 single_queue_idx) +{ + struct sk_buff *skb = NULL; + struct ieee80211_tx_info *tx_info = NULL; + struct cl_hw_tx_status *status = (struct cl_hw_tx_status *)&cfm_status; + struct cl_sw_txhdr *sw_txhdr = NULL; + struct cl_tx_queue *tx_queue = NULL; + struct cl_sta *cl_sta = NULL; + unsigned long flags = 0; + u8 hw_queue; + bool is_bcn; + + if (status->is_bcmc) { + spin_lock_irqsave(&cl_hw->tx_lock_bcmc, flags); + sw_txhdr = cl_bcmc_cfm_find(cl_hw, dma_addr, status->keep_skb); + tx_queue = &cl_hw->tx_queues.bcmc; + } else { + spin_lock_bh(&cl_hw->tx_lock_single); + sw_txhdr = cl_single_cfm_find(cl_hw, single_queue_idx, dma_addr); + tx_queue = &cl_hw->tx_queues.single[single_queue_idx]; + } + + if (!sw_txhdr) { + cl_dbg_err(cl_hw, "Failed to find single cfm [single_queue_idx %u] status 0x%x\n", + single_queue_idx, cfm_status); + goto out; + } + + skb = sw_txhdr->skb; + tx_info = IEEE80211_SKB_CB(skb); + hw_queue = sw_txhdr->hw_queue; + is_bcn = sw_txhdr->is_bcn; + + /* + * Used for beacon frames only !! + * if skb was already confirmed we do not need to inc FwFreeSpace counter + */ + if (likely(!status->freespace_inc_skip)) { + tx_queue->total_fw_cfm++; + tx_queue->fw_free_space++; + + /* Clear the TIM element if assoicated IPC queue is empty */ + if (!is_bcn && cl_txq_is_fw_empty(tx_queue)) { + bool no_ps_buffer = + (tx_info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER) ? true : false; + + cl_sta_lock(cl_hw); + cl_sta = cl_sta_get(cl_hw, sw_txhdr->sta_idx); + cl_enhanced_tim_clear_tx_single(cl_hw, single_queue_idx, hw_queue, + no_ps_buffer, cl_sta, sw_txhdr->tid); + cl_sta_unlock(cl_hw); + } + } else if (!is_bcn) { + cl_dbg_verbose(cl_hw, "should no be here - is_bcn=%d hw_queue=%d\n", + is_bcn, hw_queue); + } + + /* + * Used for beacon frames only !! + * if this flag is set, it means FW still need this beacon skb, therefore + * we do not free this skb. + */ + if (unlikely(status->keep_skb)) { + if (!is_bcn) + cl_dbg_verbose(cl_hw, "should not be here - is_bcn=%d hw_queue=%d\n", + is_bcn, hw_queue); + goto out; + } + + dma_unmap_single(cl_hw->chip->dev, dma_addr, sw_txhdr->map_len, DMA_TO_DEVICE); + + /* + * If queue is not empty call cl_txq_sched() to + * transfer packets from the queue to firmware + */ + if (!list_empty(&tx_queue->hdrs)) + cl_txq_sched(cl_hw, tx_queue); + + /* Cl_tx_inject_cfm() must be called inside the lock */ + if (cl_tx_ctrl_is_inject(tx_info)) { + cl_sta_lock(cl_hw); + cl_sta = cl_sta_get(cl_hw, sw_txhdr->sta_idx); + if (cl_sta) + cl_agg_tx_report_simulate_for_single(cl_hw, cl_sta, status); + cl_sta_unlock(cl_hw); + + cl_tx_inject_cfm(cl_hw); + dev_kfree_skb_any(skb); + cl_sw_txhdr_free(cl_hw, sw_txhdr); + goto out; + } + + if (status->is_bcmc) + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); + else + spin_unlock_bh(&cl_hw->tx_lock_single); + + if (is_bcn) { + struct ieee80211_vif *vif = sw_txhdr->cl_vif->vif; + + if (vif) { + if (vif->csa_active && + ieee80211_beacon_cntdwn_is_complete(vif)) + ieee80211_csa_finish(vif); + } + + consume_skb(skb); + cl_sw_txhdr_free(cl_hw, sw_txhdr); + return; + } + + if (status->frm_successful && !(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) + tx_info->flags |= IEEE80211_TX_STAT_ACK; + + cl_sta_lock(cl_hw); + cl_sta = cl_sta_get(cl_hw, sw_txhdr->sta_idx); + + if (cl_sta) { + if (tx_queue->type != QUEUE_TYPE_BCMC && + ieee80211_is_data(sw_txhdr->fc) && + !cl_tx_ctrl_is_eapol(tx_info)) + cl_agg_tx_report_simulate_for_single(cl_hw, cl_sta, status); + + cl_tx_check_start_ba_session(cl_hw, cl_sta->stainfo, skb); + } + + cl_sta_unlock(cl_hw); + + if (tx_info->ack_frame_id) + ieee80211_tx_status(cl_hw->hw, skb); + else + consume_skb(skb); + + cl_sw_txhdr_free(cl_hw, sw_txhdr); + return; + +out: + if (status->is_bcmc) + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); + else + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +void cl_tx_pci_single_cfm_tasklet(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + struct cl_ipc_cfm_msg *msg = NULL; + +#ifdef TRACE_SUPPORT + trace_cl_trace_tx_pci_single_cfm_tasklet_start(cl_hw->idx, ipc_env->cfm_used_idx); +#endif + + msg = (struct cl_ipc_cfm_msg *)(ipc_env->cfm_virt_base_addr) + + (ipc_env->cfm_used_idx % IPC_CFM_CNT); + + while (msg && msg->dma_addr) { + u32 cfm_used_idx = ipc_env->cfm_used_idx++; + + cl_tx_pci_single_cfm_handler(cl_hw, + le32_to_cpu(msg->status), + le32_to_cpu(msg->dma_addr), + le32_to_cpu(msg->single_queue_idx)); + msg->dma_addr = 0; + ipc_env->shared->cfm_read_pointer = cpu_to_le32(cfm_used_idx); + msg = (struct cl_ipc_cfm_msg *)(ipc_env->cfm_virt_base_addr) + + (ipc_env->cfm_used_idx % IPC_CFM_CNT); + } + + /* Enable the Tx CFM interrupt bit */ + if (!test_bit(CL_DEV_STOP_HW, &cl_hw->drv_flags)) + cl_irq_enable(cl_hw, cl_hw->ipc_e2a_irq.txcfm); + +#ifdef TRACE_SUPPORT + trace_cl_trace_tx_pci_single_cfm_tasklet_end(cl_hw->idx, ipc_env->cfm_used_idx); +#endif +} + +void cl_tx_pci_pkt_fw_send(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr, + struct cl_tx_queue *tx_queue) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(sw_txhdr->skb); + struct txdesc *txdesc = &sw_txhdr->txdesc; + struct tx_host_info *host_info = &txdesc->host_info; + struct cl_sta *cl_sta = sw_txhdr->cl_sta; + struct cl_vif *cl_vif = sw_txhdr->cl_vif; + u8 hw_queue = sw_txhdr->hw_queue; + u16 a2e_trigger_bit_pos; + u8 tid = sw_txhdr->tid; + u8 queue_type = tx_queue->type; + bool no_ps_buffer = !!(tx_info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER); + u16 ipc_queue_idx = tx_queue->index; + bool is_mgmt = ieee80211_is_mgmt(sw_txhdr->fc); + u8 *cpu_addr = (u8 *)sw_txhdr->skb->data - + ((host_info->host_padding & 1) * 2); + dma_addr_t dma_addr = dma_map_single(cl_hw->chip->dev, cpu_addr, + sw_txhdr->map_len, DMA_TO_DEVICE); + + if (WARN_ON(dma_mapping_error(cl_hw->chip->dev, dma_addr))) { + tx_queue->dump_dma_map_fail++; + + if (queue_type == QUEUE_TYPE_SINGLE) { + if (!is_mgmt) + cl_vif->sequence_number = DEC_SN(cl_vif->sequence_number); + + cl_tx_single_free_skb(cl_hw, sw_txhdr->skb); + } else { + if (queue_type == QUEUE_TYPE_AGG) { + struct cl_baw *baw = &cl_sta->baws[tid]; + + baw->tid_seq = DEC_SN(baw->tid_seq); + } + + dev_kfree_skb_any(sw_txhdr->skb); + } + + cl_sw_txhdr_free(cl_hw, sw_txhdr); + return; + } + + txdesc->umacdesc.packet_addr[0] = cpu_to_le32(dma_addr); + + cl_tx_ipc_txdesc_populate(cl_hw, txdesc, queue_type, ipc_queue_idx); + + /* make sure memory is written before push to HW */ + wmb(); + + /* + * 1) Notify firmware on new buffered traffic by updating the enhanced tim. + * 2) Push sw_txhdr to confirmation list + */ + if (queue_type == QUEUE_TYPE_AGG) { + a2e_trigger_bit_pos = IPC_IRQ_A2E_TXDESC_AGG_MAP(hw_queue); + cl_agg_cfm_add(cl_hw, sw_txhdr, ipc_queue_idx); + cl_enhanced_tim_set_tx_agg(cl_hw, ipc_queue_idx, hw_queue, + no_ps_buffer, cl_sta, tid); + } else if (queue_type == QUEUE_TYPE_SINGLE) { + a2e_trigger_bit_pos = IPC_IRQ_A2E_TXDESC_SINGLE_MAP(hw_queue); + cl_single_cfm_add(cl_hw, sw_txhdr, ipc_queue_idx); + cl_enhanced_tim_set_tx_single(cl_hw, ipc_queue_idx, hw_queue, + no_ps_buffer, cl_sta, tid); + } else { + a2e_trigger_bit_pos = IPC_IRQ_A2E_TXDESC_SINGLE_MAP(hw_queue); + cl_bcmc_cfm_add(cl_hw, sw_txhdr); + } + + /* Tx_queue counters */ + tx_queue->fw_free_space--; + tx_queue->total_fw_push_desc++; + tx_queue->total_fw_push_skb += host_info->packet_cnt; + +#ifdef TRACE_SUPPORT + trace_cl_trace_tx_push(cl_hw->idx, sw_txhdr->skb, host_info->packet_cnt, + txdesc->e2w_txhdr_param.seq_ctrl, tid); +#endif + + /* Trigger interrupt to firmware so that it will know that a new descriptor is ready */ + cl_hw->ipc_host2xmac_trigger_set(cl_hw->chip, BIT(a2e_trigger_bit_pos)); +} + From patchwork Thu Jun 17 15:58:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B69DDC2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 028/256] cl8k: add calib.c Date: Thu, 17 Jun 2021 15:58:35 +0000 Message-Id: <20210617160223.160998-29-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:03 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 78e47537-56f8-4055-c322-08d931a963e1 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 57Xik0t4sBCMAaMUwurwupzZ3yzPBjAZQGPfKVWD/FdaEW0D8fSbCnCF+wOC+sfTEONXknGFbSqpyrG4Et5Zgy1wKDL2iJXKfwjTsDZPDBMpJ36GFS4itbxV9/JGGUA+ztu1pKk+VOcgu//Ft0yfubOknEKrjQUzGjNgISTcqiQZvpYllP5ntdXeSjcKV5YcD4pBZcskDLnCZQ+3phPD7uzD0cLg2uOjZeCvmF5qnMNeER5W0No9fCMHLWMcz+WEWc258PUccugFXHptO56mjWS0T9tm588NJLuQEkeI47ewQ6TKbGUTAfoSzZiFCerb5got/EXvoBGL4poLZaZt4CIZl3EqdvT+anVMVknkVkBL69cIsOQhYWruWuBlIpwgR7AC5V4pO783CI9rfaZeeQc/46Mg5++yNU1MFN3RWD8Uu9rskQ/okGnRcP4SqQ3FZhiCoDpJNQ5ctPL023USdkdp48dKubRQRsefPw2dp8GnNUa9VsO7ja/jdpwGauRbUcnVdtS0X8Kb6ZOUmN+9/BsgszxXglEHdeOvZLLp5md4kxG24COognqKKINjGVSKcqE3resVeO4QrWf4dXiv650QuYS4IIab7xISx9gEknT5NxH4/YW+w28CYxE+l/FVuYxgGprbrEzzatl7cJ80Ab55LADm+HAVUad5cbM0EBCA/rDfC5AsLedHBLZPUMzaRg4eLK4VgT7fgmc67y/2x8MF1Xekk0DyYIlhKnRFeIM= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(30864003)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001)(559001)(579004)(309714004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HRW3zIoOgaWIUhLKIlyK1jROz/zLTVs6BCdHgb+Y+DF4E/4kaZnXudC1KD1PX2eHeA6tR1fHypp6FPShq6PhlyCN/YCerC1VxLV7SVYbnZAarIUGwUq5sLW9M+aw2DNBjhrjkY8tt5kXdDR+WpaECEZVi8Tm7RR6opHLGKS9dk/v9ZPcDypX3SwNzp6C01ox5qfOCCvv2R+1Pmw2E3R6REZgZtuKs8lFW+s+tRGvmcgJPGhEUoLcPUwxCIqQPTCtRu1aakyaGqAD/rXG0mMw9uQM7KBeIKmv1nVLOMQlSq60nh76IFfmcxP+F9t7cqA1qEJDEcbVSrdZpGmx3SuDcJs8YgHtqngk98F79RBl9/s+Px1Snejt55KMjBtDMAVWVO7lOPnB0V4/S6seFfQZVJ9SVVgvulRVw6NK0T3TK41aqPKY9CC+BoF/jZikuT3vXDdvJezaspbaEFzpslmg3OTb5WHVAMtFAWKpaUyb7i/3UHotdlI2T4gubrtNxFkUX+0kr5cTtGciGbe8Mo2YLvCPpZ5CiqifKqV4y3AABpZBMqzpmE9Olkj9wc/PtswMg0UcENCXhFAtEmc1o1LXaFEhC7OwcAYwUuid06rFMJQryaMwFyAcHBz2kSzEn5awEV2cbBRJGTn+nbrP5bkvtlWBXV2IEO61Ii6Z7HV7AbQ/tWiXCPdHAlP57XrUaxut0cHIGDo6zQ9pI4SpnnXhr9vCv5DRMrvjZxRsd2oWjoH45E/z8g5fKQghSu5M10PBqFZYW4X5rkkPhVArvfMXWiPCZF/LR0hbjveLD/l7JQP+BJ2tkuvhn4qux2tBKOJL/zZ+/IZYUg/VbkgRNRIVZ1To3h4iJuLrzzFF46gr4XjCXToH+Sin3sw4XyABpIp+3PMHcydYsWOa9nrybDIO17UCe9ZCyzLeoVlPZG5N/cw+azN5+zDcObRN8FOwa10b7KcmhPuo4viwZSjKfrGVYgyuJGja+NAppY65GLFK5/kFK1B6r/dYd4UxSzpg283G1UD69kXYJNpabvR7llLHYUz8wTsZ0R0SByp7HrnC8+Eq44eCIg/T4zcvwLag5YIZt2CV4Yzp/TGFVoVettMzkEVFkDfL52en2doK39BhcJ269Bp3ELSjax5JK9LOSsG+lcl6gYKhcujT1nQTioQAvw/Bqh501sb3vgO7YTAZIVP6w4LXfnh9rgisQDL072MRdWlhVMqnsoHmH4aCiCZYST73ZI89sB9FQ1yTEisUSlLwQvVc6w2HLQzGzmul+dznebOz+8LaFvvncK/nODsxvU2gtg7SYmuw7HgfwRhkhuIPBVdge5aknI68HLTt8Lmc X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78e47537-56f8-4055-c322-08d931a963e1 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:04.8024 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6QmZ/D2zFQivifdTvk0YnZV/Bnco3enx2jLVT5vh8p3lBiMdztsI0yxOVtf+SJm09y3aw0AsB0BQAkE7Mu/8sw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/calib.c | 1682 ++++++++++++++++++++++ 1 file changed, 1682 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/calib.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/calib.c b/drivers/net/wireless/celeno/cl8k/calib.c new file mode 100644 index 000000000000..8861964e3aff --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/calib.c @@ -0,0 +1,1682 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include +#include +#include +#include +#include + +#include "calib.h" +#include "temperature.h" +#include "utils/utils.h" +#include "chip.h" +#include "chandef.h" +#include "fw/msg_cfm.h" +#include "fw/msg_tx.h" +#include "band.h" +#include "e2p.h" +#include "channel.h" +#include "power.h" +#include "afe.h" +#include "radio.h" + +/* + * CL80x0: TCV0 - 5g, TCV1 - 24g + * ============================================== + * 50 48 46 44 42 40 38 36 --> Start 5g + * 100 64 62 60 58 56 54 52 + * 116 114 112 110 108 106 104 102 + * 134 132 128 126 124 122 120 118 + * 153 151 149 144 142 140 138 136 + * 3 2 1 165 161 159 157 155 --> Start 24g + * 11 10 9 8 7 6 5 4 + * 14 13 12 + */ + +/* + * CL80x6: TCV0 - 6g, TCV1 - 5g + * ============================================== + * 25 21 17 13 9 5 2 1 --> Start 6g + * 57 53 49 45 41 37 33 29 + * 89 85 81 77 73 69 65 61 + * 121 117 113 109 105 101 97 93 + * 153 147 143 139 135 131 127 123 + * 185 181 177 173 169 165 161 157 + * 217 213 209 205 201 197 193 189 + * 42 40 38 36 233 229 225 221 --> Start 5g + * 58 56 54 52 50 48 46 44 + * 108 106 104 102 100 64 62 60 + * 124 122 120 118 116 114 112 110 + * 142 140 138 136 134 132 128 126 + * 161 159 157 155 153 151 149 144 + * 165 + */ + +#define BITMAP_80X0_START_TCV0 0 +#define BITMAP_80X0_MAX_TCV0 NUM_CHANNELS_5G + +#define BITMAP_80X0_START_TCV1 NUM_CHANNELS_5G +#define BITMAP_80X0_MAX_TCV1 (NUM_CHANNELS_5G + NUM_CHANNELS_24G) + +#define BITMAP_80X6_START_TCV0 0 +#define BITMAP_80X6_MAX_TCV0 NUM_CHANNELS_6G + +#define BITMAP_80X6_START_TCV1 NUM_CHANNELS_6G +#define BITMAP_80X6_MAX_TCV1 (NUM_CHANNELS_6G + NUM_CHANNELS_5G) + +#define INVALID_ADDR 0xffff + +#define S12_S_BIT (0x00000800) +#define U12_BIT_MASK (0x00000FFF) +#define CAST_S12_TO_S32(i) ((~(i) & S12_S_BIT) ? (i) : ((i) | ~U12_BIT_MASK)) + +static const u8 calib_channels_24g[CALIB_CHAN_24G_MAX] = { + 1, 6, 11 +}; + +static const u8 calib_channels_5g[CALIB_CHAN_5G_MAX] = { + 36, 52, 100, 116, 132, 149 +}; + +static const u8 calib_channels_6g[CALIB_CHAN_6G_MAX] = { + 1, 17, 33, 49, 65, 81, 97, 113, 129, 145, 161, 177, 193, 209, 225 +}; + +static u8 tone_vector_arr[CHNL_BW_MAX][IQ_NUM_TONES_REQ] = { + {6, 10, 14, 18, 22, 24, 26, 27}, + {10, 18, 26, 34, 41, 48, 53, 58}, + {18, 34, 50, 66, 82, 98, 110, 122}, + {18, 34, 66, 98, 130, 164, 224, 250} +}; + +static u8 get_bitmap_start_tcv1(struct cl_chip *chip) +{ + if (cl_chip_is_6g(chip)) + return BITMAP_80X6_START_TCV1; + else + return BITMAP_80X0_START_TCV1; +} + +static void get_bitmap_boundaries(struct cl_chip *chip, u8 tcv_idx, u8 *start, u8 *max) +{ + if (cl_chip_is_6g(chip)) { + if (tcv_idx == TCV0) { + *start = BITMAP_80X6_START_TCV0; + *max = BITMAP_80X6_MAX_TCV0; + } else { + *start = BITMAP_80X6_START_TCV1; + *max = BITMAP_80X6_MAX_TCV1; + } + } else { + if (tcv_idx == TCV0) { + *start = BITMAP_80X0_START_TCV0; + *max = BITMAP_80X0_MAX_TCV0; + } else { + *start = BITMAP_80X0_START_TCV1; + *max = BITMAP_80X0_MAX_TCV1; + } + } +} + +static u8 idx_to_arr_offset(u8 idx) +{ + /* Divide by 8 for array index */ + return idx >> 3; +} + +static u8 idx_to_bit_offset(u8 idx) +{ + /* Reminder is for bit index (assummed array of u8) */ + return idx & 0x07; +} + +static const u8 bits_cnt_table256[] = { + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 +}; + +static u8 count_bits(const u8 *bitmap) +{ + /* + * Count bits in a given u8 array ASSUMED ARRAY SIZE IS BIT_MAP_SIZE + * bitmap - pointer to u8 array (bitmap) + */ + u8 i = 0, cnt = 0; + + for (i = 0; i < BIT_MAP_SIZE; i++) + cnt += bits_cnt_table256[bitmap[i]]; + + return cnt; +} + +static bool is_vector_unset(const u8 *bitmap) +{ + /* Check bitmap is unset i.e. all values are CURR_BMP_UNSET */ + u8 empty_bitmap[BIT_MAP_SIZE] = {0}; + + return !memcmp(bitmap, empty_bitmap, BIT_MAP_SIZE); +} + +static bool bitmap_test_bit_idx(const u8 *bitmap, u8 idx) +{ + /* Check bit at a given index is set i.e. 1 */ + u8 arr_idx = idx_to_arr_offset(idx), bit_idx = idx_to_bit_offset(idx); + + if (arr_idx >= BIT_MAP_SIZE) + return false; + + /* Convert non-zero to true and zero to false */ + return !!(bitmap[arr_idx] & BIT(bit_idx)); +} + +static void bitmap_shift(u8 *bitmap, u8 shft) +{ + /* Shifts an array of byte of size len by shft number of bits to the left */ + u8 bitmap_tmp[BIT_MAP_SIZE] = {0}; + u8 msb_shifts = shft % 8; + u8 lsb_shifts = 8 - msb_shifts; + u8 byte_shift = shft / 8; + u8 last_byte = BIT_MAP_SIZE - byte_shift - 1; + u8 msb_idx; + u8 i; + + memcpy(bitmap_tmp, bitmap, BIT_MAP_SIZE); + memset(bitmap, 0, BIT_MAP_SIZE); + + for (i = 0; i < BIT_MAP_SIZE; i++) { + if (i <= last_byte) { + msb_idx = i + byte_shift; + bitmap[i] = bitmap_tmp[msb_idx] >> msb_shifts; + if (i != last_byte) + bitmap[i] |= bitmap_tmp[msb_idx + 1] << lsb_shifts; + } + } +} + +static bool bitmap_set_bit_idx(struct cl_hw *cl_hw, u8 *bitmap, u8 idx) +{ + /* Set bit at a given index */ + u8 arr_idx = idx_to_arr_offset(idx), bit_idx = idx_to_bit_offset(idx); + + if (arr_idx >= BIT_MAP_SIZE) { + cl_dbg_err(cl_hw, "invalid arr_idx (%u)\n", arr_idx); + return false; + } + + bitmap[arr_idx] |= BIT(bit_idx); + return true; +} + +static bool bitmap_clear_bit_idx(struct cl_hw *cl_hw, u8 *bitmap, u8 idx) +{ + /* Clear bit at a given index */ + u8 arr_idx = idx_to_arr_offset(idx), bit_idx = idx_to_bit_offset(idx); + + if (arr_idx >= BIT_MAP_SIZE) { + cl_dbg_err(cl_hw, "invalid arr_idx (%u)\n", arr_idx); + return false; + } + + bitmap[arr_idx] &= ~BIT(bit_idx); + return true; +} + +static u16 bitmap_look_lsb_up(struct cl_hw *cl_hw, u8 *bitmap, u16 idx) +{ + /* Find closest ON(1) bit with index haigher than idx inside bitmap */ + u16 curr_idx = idx; + u8 curr = 0; + + while (++curr_idx < cl_channel_num(cl_hw)) { + curr = bitmap[idx_to_arr_offset(curr_idx)]; + if (curr & (1ULL << idx_to_bit_offset(curr_idx))) + return curr_idx; + } + + /* No matching bit found - return original index */ + return idx; +} + +static u16 bitmap_look_msb_down(struct cl_hw *cl_hw, u8 *bitmap, u16 idx) +{ + /* Find closest ON(1) bit with index lower than idx inside bitmap */ + u16 curr_idx = idx; + u8 curr = 0; + + if (idx >= cl_channel_num(cl_hw)) { + cl_dbg_err(cl_hw, "Invalid channel index [%u]\n", idx); + return idx; + } + + while (curr_idx-- != 0) { + curr = bitmap[idx_to_arr_offset(curr_idx)]; + if (curr & (1ULL << idx_to_bit_offset(curr_idx))) + return curr_idx; + } + + /* No matching bit found - return original index */ + return idx; +} + +static u8 address_offset_tcv1(struct cl_hw *cl_hw) +{ + /* Calculate eeprom calibration data offset for tcv1 */ + struct cl_chip *chip = cl_hw->chip; + u8 i, cnt = 0; + u8 bitmap[BIT_MAP_SIZE] = {0}; + + if (cl_e2p_read(chip, bitmap, BIT_MAP_SIZE, ADDR_CALIB_CHAN_BMP)) + return 0; + + for (i = 0; i < get_bitmap_start_tcv1(chip); i++) + cnt += bitmap_test_bit_idx(bitmap, i); + + return cnt; +} + +static int point_idx_to_address(struct cl_hw *cl_hw, u8 *bitmap, struct point *pt) +{ + /* Calculate eeprom address for a given idx and phy (initiated point) */ + u8 i, cnt = 0; + + pt->addr = INVALID_ADDR; + + if (!bitmap_test_bit_idx(bitmap, pt->idx)) + return 0; + + if (pt->phy >= MAX_ANTENNAS) { + cl_dbg_err(cl_hw, "Invalid phy number %u", pt->phy); + return -EINVAL; + } + + for (i = 0; i < pt->idx; i++) + cnt += bitmap_test_bit_idx(bitmap, i); + + if (cl_hw_is_tcv1(cl_hw)) + cnt += address_offset_tcv1(cl_hw); + + pt->addr = ADDR_CALIB_PHY + + sizeof(struct eeprom_phy_calib) * (cnt * MAX_ANTENNAS + pt->phy); + + return 0; +} + +static bool linear_equation_signed(struct cl_hw *cl_hw, const u16 x, s8 *y, + const u16 x0, const s8 y0, const u16 x1, const s8 y1) +{ + /* Calculate y given to points (x0,y0) and (x1,y1) and x */ + s32 numerator = (x - x0) * (y1 - y0); + s32 denominator = x1 - x0; + + if (unlikely(!denominator)) { + cl_dbg_err(cl_hw, "zero denominator\n"); + return false; + } + + *y = (s8)(y0 + DIV_ROUND_CLOSEST(numerator, denominator)); + + return true; +} + +static bool calculate_calib(struct cl_hw *cl_hw, u8 *bitmap, + struct point *p0, struct point *p1, struct point *p2) +{ + /* Main interpolation/extrapolation function */ + bool calc_succsess = false; + u16 freq0, freq1, freq2; + + if (unlikely(is_vector_unset(bitmap))) + return false; + + p1->idx = bitmap_look_lsb_up(cl_hw, bitmap, p0->idx); + p2->idx = bitmap_look_msb_down(cl_hw, bitmap, p0->idx); + + /* Invalid case */ + if (p1->idx == p0->idx && p2->idx == p0->idx) { + cl_dbg_err(cl_hw, "Invalid index %u or bad bit map\n", p0->idx); + return false; + } + + /* Extrapolation case */ + if (p1->idx == p0->idx) + p1->idx = bitmap_look_msb_down(cl_hw, bitmap, p2->idx); + if (p2->idx == p0->idx) + p2->idx = bitmap_look_lsb_up(cl_hw, bitmap, p1->idx); + + /* Address from index */ + if (point_idx_to_address(cl_hw, bitmap, p1) || p1->addr == INVALID_ADDR) { + cl_dbg_err(cl_hw, "Point calculation failed\n"); + return false; + } + + if (point_idx_to_address(cl_hw, bitmap, p2) || p2->addr == INVALID_ADDR) { + cl_dbg_err(cl_hw, "Point calculation failed\n"); + return false; + } + + /* Read from eeprom */ + if (cl_e2p_read(cl_hw->chip, (u8 *)&p1->calib, sizeof(struct eeprom_phy_calib), p1->addr)) + return false; + + /* No interpolation required */ + if (p1->addr == p2->addr) { + p0->calib = p1->calib; + return true; + } + + /* Interpolation or extrapolation is required - read from eeprom */ + if (cl_e2p_read(cl_hw->chip, (u8 *)&p2->calib, sizeof(struct eeprom_phy_calib), p2->addr)) + return false; + + freq0 = cl_channel_idx_to_freq(cl_hw, p0->idx); + freq1 = cl_channel_idx_to_freq(cl_hw, p1->idx); + freq2 = cl_channel_idx_to_freq(cl_hw, p2->idx); + + /* Interpolate/extrapolate target power */ + calc_succsess = linear_equation_signed(cl_hw, + freq0, &p0->calib.pow, + freq1, p1->calib.pow, + freq2, p2->calib.pow); + + /* Interpolate/extrapolate power offset */ + calc_succsess = calc_succsess && linear_equation_signed(cl_hw, + freq0, &p0->calib.offset, + freq1, p1->calib.offset, + freq2, p2->calib.offset); + + /* Interpolate/extrapolate calibration temperature */ + calc_succsess = calc_succsess && linear_equation_signed(cl_hw, + freq0, &p0->calib.tmp, + freq1, p1->calib.tmp, + freq2, p2->calib.tmp); + + if (unlikely(!calc_succsess)) { + cl_dbg_err(cl_hw, + "Calc failed: freq0 %u idx0 %u, freq1 %u idx1 %u, freq2 %u idx2 %u\n", + freq0, p0->idx, freq1, p1->idx, freq2, p2->idx); + return false; + } + + return true; +} + +static int read_validate_vector_bitmap(struct cl_hw *cl_hw, u8 *bitmap) +{ + struct cl_chip *chip = cl_hw->chip; + + if (cl_e2p_read(chip, bitmap, BIT_MAP_SIZE, ADDR_CALIB_CHAN_BMP)) + return -1; + + /* Test if e2p was read succsefull since it is not ALL EMPTY */ + if (is_vector_unset(bitmap)) { + cl_dbg_err(cl_hw, "Vector not ready\n"); + return -EPERM; + } + + if (cl_hw_is_tcv1(cl_hw)) { + u8 bitmap_start = get_bitmap_start_tcv1(chip); + + bitmap_shift(bitmap, bitmap_start); + } + + return 0; +} + +static int e2p_prepare(struct cl_hw *cl_hw, struct point *data, u8 *bitmap) +{ + int ret = read_validate_vector_bitmap(cl_hw, bitmap); + + if (ret) { + cl_dbg_err(cl_hw, "read_validate_vector_bitmap failed\n"); + return ret; + } + + data->idx = cl_channel_to_index(cl_hw, data->chan); + + return point_idx_to_address(cl_hw, bitmap, data); +} + +static int read_or_interpolate_point(struct cl_hw *cl_hw, u8 *bitmap, struct point *p0) +{ + struct point p1 = {.phy = p0->phy}; + struct point p2 = {.phy = p0->phy}; + struct point tmp_pt = *p0; + + /* Invalid address = no physical address was allocated to this channel */ + if (tmp_pt.addr != INVALID_ADDR) { + if (cl_e2p_read(cl_hw->chip, (u8 *)&tmp_pt.calib, + sizeof(struct eeprom_phy_calib), tmp_pt.addr)) + return -1; + } else { + /* Interpolate */ + if (!calculate_calib(cl_hw, bitmap, &tmp_pt, &p1, &p2)) { + cl_dbg_err(cl_hw, "Interpolation Error\n"); + return -EFAULT; + } + } + + if (tmp_pt.calib.pow == 0 && tmp_pt.calib.offset == 0 && tmp_pt.calib.tmp == 0) { + u16 freq = cl_channel_idx_to_freq(cl_hw, tmp_pt.idx); + + cl_dbg_err(cl_hw, "Verify calibration point: addr %x, idx %u, freq %u, phy %u\n", + tmp_pt.addr, tmp_pt.idx, freq, tmp_pt.phy); + /* *Uninitiated eeprom value */ + return -EINVAL; + } + + /* Now p0 will contain "Valid" calculations of calib" */ + p0->calib = tmp_pt.calib; + return 0; +} + +int cl_calib_get(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + /* Kernel space callback for handling E2P_GET_CALIB vendor subcmd */ + int ret; + struct point *p0; + u8 e2p_bitmap[BIT_MAP_SIZE] = {0}; + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + + if (!data) { + cl_dbg_err(cl_hw, "data is null\n"); + return -1; + } + + p0 = (struct point *)data; + + ret = e2p_prepare(cl_hw, p0, e2p_bitmap); + if (ret) { + cl_dbg_err(cl_hw, "Unable prepare e2p\n"); + return ret; + } + + ret = read_or_interpolate_point(cl_hw, e2p_bitmap, p0); + if (ret) { + cl_dbg_trace(cl_hw, "read_or_interpolate_point error\n"); + return ret; + } + + return cl_vendor_reply(cl_hw, &p0->calib, sizeof(p0->calib)); +} + +int cl_calib_set(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + /* Kernel space callback for handling E2P_SET_CALIB vendor subcmd */ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + struct point pt; + int ret; + u8 e2p_bitmap[BIT_MAP_SIZE] = {0}; + u8 ch_idx = 0; + + if (!data) { + cl_dbg_err(cl_hw, "data is null\n"); + return -1; + } + + pt = *(struct point *)data; + + ret = e2p_prepare(cl_hw, &pt, e2p_bitmap); + if (ret) { + cl_dbg_err(cl_hw, "Unable prepare e2p\n"); + return ret; + } + + if (pt.addr == INVALID_ADDR) { + cl_dbg_err(cl_hw, "Invalid address - permission denied\n"); + return -EPERM; + } + + if (pt.calib.pow < POWER_MIN_DB || pt.calib.pow > POWER_MAX_DB) { + cl_dbg_err(cl_hw, "Invalid power (%d). Valid range (%d - %d)\n", + pt.calib.pow, POWER_MIN_DB, POWER_MAX_DB); + return -1; + } + + if (pt.calib.offset < POWER_OFFSET_MIN_Q2 || pt.calib.offset > POWER_OFFSET_MAX_Q2) { + cl_dbg_err(cl_hw, "Invalid power offset (%d). Valid range (%d - %d)\n", + pt.calib.offset, POWER_OFFSET_MIN_Q2, POWER_OFFSET_MAX_Q2); + return -1; + } + + if (!bitmap_test_bit_idx(e2p_bitmap, pt.idx)) { + cl_dbg_err(cl_hw, "No permition to write to this channel %u\n", pt.idx); + return -EACCES; + } + + /* + * Temperature is an optional argument for "e2p set calib" command. + * If value is 0x7f then temperature argument was not set, and it + * should be set by the driver. + */ + if (pt.calib.tmp == S8_MAX) + pt.calib.tmp = cl_temperature_read(cl_hw, TEMP_MODE_INTERNAL); + + if (cl_e2p_write(cl_hw->chip, (u8 *)&pt.calib, sizeof(struct eeprom_phy_calib), pt.addr)) + return -1; + + ch_idx = cl_channel_to_index(cl_hw, pt.chan); + + if (ch_idx < MAX_CHANNELS && pt.phy < MAX_ANTENNAS) { + cl_hw->tx_pow_info[ch_idx][pt.phy].power = pt.calib.pow; + cl_hw->tx_pow_info[ch_idx][pt.phy].offset = pt.calib.offset; + cl_hw->tx_pow_info[ch_idx][pt.phy].temperature = pt.calib.tmp; + cl_hw->set_calib = true; + } + + return 0; +} + +static void cl_calib_power_reset(struct cl_hw *cl_hw) +{ + u8 ch_idx; + u16 phy; + static const struct cl_tx_power_info default_info = { + .power = UNCALIBRATED_POWER, + .offset = UNCALIBRATED_POWER_OFFSET, + .temperature = UNCALIBRATED_TEMPERATURE + }; + + /* Initiate tx_pow_info struct to default values */ + for (ch_idx = 0; ch_idx < cl_channel_num(cl_hw); ch_idx++) + for (phy = 0; phy < MAX_ANTENNAS; phy++) + cl_hw->tx_pow_info[ch_idx][phy] = default_info; +} + +#define PHY0_OFFSET_FIX_Q2 -8 /* -2db */ +#define PHY3_OFFSET_FIX_Q2 14 /* +3.5db */ + +void cl_calib_power_read(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + int ret; + u8 bitmap[BIT_MAP_SIZE] = {0}; + struct point curr_point = {0}; + u8 *phy = &curr_point.phy; + u8 *ch_idx = &curr_point.idx; + + /* Initiate tx_pow_info struct to default values */ + cl_calib_power_reset(cl_hw); + + /* Vector not initiated set table to default values */ + if (unlikely(read_validate_vector_bitmap(cl_hw, bitmap))) { + cl_dbg_trace(cl_hw, "initiate to default values\n"); + return; + } + + /* Perform only on calibrated boards - read_validate_vector_bitmap succeeded (0) */ + for (*ch_idx = 0; *ch_idx < cl_channel_num(cl_hw); (*ch_idx)++) + for (*phy = 0; *phy < cl_hw->num_antennas; (*phy)++) { + ret = point_idx_to_address(cl_hw, bitmap, &curr_point); + + if (ret) { + /* *don't overwrite default values */ + cl_dbg_err(cl_hw, "point idx to address failed\n"); + continue; + } + + ret = read_or_interpolate_point(cl_hw, bitmap, &curr_point); + /* Unable to calculate new value ==> DON'T overwrite default values */ + if (unlikely(ret)) + continue; + + /* + * Work around: + * Add 3.5dB offset to PHY3 if EEPROM version is 0. + * Decrease 2dB offset to all PHYs if EEPROM version is 1. + */ + if (!cl_chip_is_6g(chip)) { + u8 eeprom_version = chip->eeprom_cache->general.version; + + if (cl_band_is_5g(cl_hw) && eeprom_version == 0 && *phy == 3) + curr_point.calib.offset += PHY3_OFFSET_FIX_Q2; + else if (cl_band_is_24g(cl_hw) && eeprom_version == 1) + curr_point.calib.offset += PHY0_OFFSET_FIX_Q2; + } + + cl_hw->tx_pow_info[*ch_idx][*phy].power = curr_point.calib.pow; + cl_hw->tx_pow_info[*ch_idx][*phy].offset = curr_point.calib.offset; + cl_hw->tx_pow_info[*ch_idx][*phy].temperature = curr_point.calib.tmp; + } + + cl_dbg_trace(cl_hw, "Created tx_pow_info\n"); +} + +void cl_calib_power_offset_fill(struct cl_hw *cl_hw, u8 channel, + u8 bw, u8 offset[MAX_ANTENNAS]) +{ + u8 i; + u8 chan_idx = cl_channel_to_index(cl_hw, channel); + s8 signed_offset; + struct cl_ate_db *ate_db = &cl_hw->ate_db; + + if (chan_idx == INVALID_CHAN_IDX) + return; + + /* In ATE mode, use values of 'ATE power_offset' if it was set */ + if (ate_db->active && ate_db->tx_power_offset[0] != S8_MAX) { + for (i = 0; i < MAX_ANTENNAS; i++) { + s8 pow_offset = ate_db->tx_power_offset[i]; + + signed_offset = cl_power_offset_check_margin(cl_hw, bw, i, pow_offset); + offset[i] = cl_convert_signed_to_reg_value(signed_offset); + } + + return; + } + + for (i = 0; i < MAX_ANTENNAS; i++) { + s8 pow_offset = cl_hw->tx_pow_info[chan_idx][i].offset; + + signed_offset = cl_power_offset_check_margin(cl_hw, bw, i, pow_offset); + offset[i] = cl_convert_signed_to_reg_value(signed_offset); + } +} + +static void pivot_channels_reset(struct cl_hw *cl_hw, u8 *bitmap) +{ + u8 i, start = 0, max = 0; + + get_bitmap_boundaries(cl_hw->chip, cl_hw->tcv_idx, &start, &max); + + for (i = start; i < max; i++) + bitmap_clear_bit_idx(cl_hw, bitmap, i); +} + +static u8 count_num_pivots(struct cl_chip *chip, const u8 *bitmap, u8 tcv_idx) +{ + u8 i = 0, cnt = 0, start = 0, max = 0; + + get_bitmap_boundaries(chip, tcv_idx, &start, &max); + + for (i = start; i < max; i++) + if (bitmap_test_bit_idx(bitmap, i)) + cnt++; + + return cnt; +} + +int cl_calib_pivot_channels_set(struct cl_hw *cl_hw, const void *chan_list, u32 size) +{ + struct cl_chip *chip = cl_hw->chip; + u8 bitmap[BIT_MAP_SIZE] = {0}; + u8 num_pivots = 0; + u8 idx = 0; + + if (cl_e2p_read(chip, bitmap, BIT_MAP_SIZE, ADDR_CALIB_CHAN_BMP)) + return -1; + + num_pivots = count_num_pivots(chip, bitmap, cl_hw->tcv_idx); + + if (num_pivots > 0) { + cl_dbg_err(cl_hw, "Vector already set\n"); + return -EACCES; + } + + while (size--) { + idx = cl_channel_to_index(cl_hw, ((u32 *)chan_list)[size]); + + if (idx == INVALID_CHAN_IDX) { + cl_dbg_err(cl_hw, "Bad channel index %u", idx); + return -EINVAL; + } + + if (cl_hw_is_tcv1(cl_hw)) + idx += get_bitmap_start_tcv1(chip); + + if (!bitmap_set_bit_idx(cl_hw, bitmap, idx)) { + cl_dbg_err(cl_hw, "Bad channel index %u", idx); + return -EINVAL; + } + } + + if (count_bits(bitmap) > NUM_OF_PIVOTS) { + cl_dbg_err(cl_hw, "Too much pivot channels chosen\n"); + return -EINVAL; + } + + if (cl_e2p_write(chip, bitmap, BIT_MAP_SIZE, ADDR_CALIB_CHAN_BMP)) + return -1; + + /* + * Pivots of tcv0 are located before the pivots of tcv1. + * If calibration of tcv1 was done before calibration of tcv0, we must move the + * calibration data of tcv1 so that there is room for the tcv0 calibration data. + */ + if (cl_hw_is_tcv0(cl_hw)) { + u8 num_pivots_tcv0 = count_num_pivots(chip, bitmap, TCV0); + u8 num_pivots_tcv1 = count_num_pivots(chip, bitmap, TCV1); + + if (num_pivots_tcv1 > 0) { + struct eeprom_phy_calib phy_calib[NUM_PIVOT_PHYS] = { {0} }; + + if (cl_e2p_read(chip, (u8 *)phy_calib, SIZE_CALIB_PHY, ADDR_CALIB_PHY)) + return -1; + + memmove(&phy_calib[num_pivots_tcv0 * MAX_ANTENNAS], + &phy_calib[0], + num_pivots_tcv1 * MAX_ANTENNAS * sizeof(struct eeprom_phy_calib)); + memset(&phy_calib[0], + 0, + num_pivots_tcv0 * MAX_ANTENNAS * sizeof(struct eeprom_phy_calib)); + + if (cl_e2p_write(chip, (u8 *)phy_calib, SIZE_CALIB_PHY, ADDR_CALIB_PHY)) + return -1; + } + } + + return 0; +} + +int cl_calib_pivot_channels_reset(struct cl_hw *cl_hw) +{ + /* Both eeprom and efuse are being set to 0 for reset */ + struct cl_chip *chip = cl_hw->chip; + u8 bitmap[BIT_MAP_SIZE] = {0}; + struct eeprom_phy_calib phy_calib[NUM_PIVOT_PHYS] = { {0} }; + u8 num_pivots_tcv0 = 0; + u8 num_pivots_tcv1 = 0; + + if (sizeof(phy_calib) != SIZE_CALIB_PHY) { + cl_dbg_err(cl_hw, "sizeof(phy_calib) != SIZE_CALIB_PHY\n"); + return -1; + } + + /* Read current bitmap and calibration data */ + if (cl_e2p_read(chip, (u8 *)bitmap, BIT_MAP_SIZE, ADDR_CALIB_CHAN_BMP)) + return -1; + if (cl_e2p_read(chip, (u8 *)phy_calib, SIZE_CALIB_PHY, ADDR_CALIB_PHY)) + return -1; + + /* Find number of pivots for each band */ + num_pivots_tcv0 = count_num_pivots(chip, bitmap, TCV0); + num_pivots_tcv1 = count_num_pivots(chip, bitmap, TCV1); + + /* Reset bitmap of this band */ + pivot_channels_reset(cl_hw, bitmap); + + /* Reset calibration data of this band */ + if (cl_hw_is_tcv0(cl_hw)) { + if (num_pivots_tcv1 > 0) { + /* For tcv0 shift calibration data of tcv1 to the beginning */ + memcpy(&phy_calib[0], &phy_calib[num_pivots_tcv0 * MAX_ANTENNAS], + num_pivots_tcv1 * MAX_ANTENNAS * sizeof(struct eeprom_phy_calib)); + memset(&phy_calib[num_pivots_tcv1 * MAX_ANTENNAS], 0, + num_pivots_tcv0 * MAX_ANTENNAS * sizeof(struct eeprom_phy_calib)); + } else { + memset(&phy_calib[0], 0, + num_pivots_tcv0 * MAX_ANTENNAS * sizeof(struct eeprom_phy_calib)); + } + } else { + memset(&phy_calib[num_pivots_tcv0 * MAX_ANTENNAS], + 0, num_pivots_tcv1 * MAX_ANTENNAS * sizeof(struct eeprom_phy_calib)); + } + + /* Write back modified bitmap and calibration data */ + if (cl_e2p_write(chip, (u8 *)bitmap, BIT_MAP_SIZE, ADDR_CALIB_CHAN_BMP)) + return -1; + if (cl_e2p_write(chip, (u8 *)phy_calib, SIZE_CALIB_PHY, ADDR_CALIB_PHY)) + return -1; + + /* Reset host calibration data */ + cl_calib_power_reset(cl_hw); + + return 0; +} + +static void cl_calib_init_cfm(struct cl_iq_dcoc_data *iq_dcoc_data) +{ + int i; + + for (i = 0; i < CALIB_CFM_MAX; i++) + iq_dcoc_data->dcoc_iq_cfm[i].status = CALIB_FAIL; +} + +static void cl_calib_save_channel(struct cl_hw *cl_hw, struct cl_calib_restore *calib_restore) +{ + calib_restore->bw = cl_hw->bw; + calib_restore->primary = cl_hw->primary_freq; + calib_restore->center = cl_hw->center_freq; + calib_restore->channel = ieee80211_frequency_to_channel(cl_hw->primary_freq); +} + +static int cl_calib_set_idle(struct cl_hw *cl_hw, bool idle) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + u8 is_prod = chip->conf->ce_production_mode; + bool tcv0_en = (cl_radio_is_on(cl_hw_tcv0) || (is_prod && cl_hw_tcv0->ate_db.active)); + bool tcv1_en = (cl_radio_is_on(cl_hw_tcv1) || (is_prod && cl_hw_tcv1->ate_db.active)); + + if (!idle) { + if (tcv1_en) + cl_msg_tx_set_idle(cl_hw_tcv1, MAC_ACTIVE); + + if (tcv0_en) + cl_msg_tx_set_idle(cl_hw_tcv0, MAC_ACTIVE); + + return 0; + } + + if (tcv1_en) + cl_msg_tx_idle_async(cl_hw_tcv1); + + if (tcv0_en) + cl_msg_tx_set_idle(cl_hw_tcv0, MAC_IDLE_SYNC); + + if (wait_event_timeout(cl_hw->wait_queue, !cl_hw->idle_async_set, + CL_MSG_CFM_TIMEOUT_JIFFIES)) + return 0; + + cl_dbg_err(cl_hw, "Timeout occurred - MM_IDLE_ASYNC_IND\n"); + + return -ETIMEDOUT; +} + +static int _cl_calib_set_channel(struct cl_hw *cl_hw, u32 channel, u32 bw) +{ + u32 primary = 0; + u32 center = 0; + enum nl80211_chan_width width = NL80211_CHAN_WIDTH_20; + + if (cl_chandef_calc(cl_hw, channel, bw, &width, &primary, ¢er)) { + cl_dbg_err(cl_hw, "cl_chandef_calc failed\n"); + return -EINVAL; + } + + cl_dbg_verbose(cl_hw, "Calibrate channel %u bw %u\n", channel, BW_TO_MHZ(bw)); + + return _cl_msg_tx_set_channel(cl_hw, channel, bw, primary, center, SET_CHANNEL_MODE_CALIB); +} + +static void cl_calib_channels_6g(struct cl_hw *cl_hw) +{ + int i; + + /* Calibrate channels: 1, 33, 65, 97, 129, 161, 193, 225 */ + for (i = 0; i < CALIB_CHAN_6G_MAX; i += 2) + _cl_calib_set_channel(cl_hw, calib_channels_6g[i], CHNL_BW_160); + + for (i = 0; i < CALIB_CHAN_6G_MAX; i++) { + _cl_calib_set_channel(cl_hw, calib_channels_6g[i], CHNL_BW_80); + _cl_calib_set_channel(cl_hw, calib_channels_6g[i], CHNL_BW_20); + } +} + +static void cl_calib_channels_5g(struct cl_hw *cl_hw) +{ + int i; + + _cl_calib_set_channel(cl_hw, 36, CHNL_BW_160); + _cl_calib_set_channel(cl_hw, 100, CHNL_BW_160); + + for (i = 0; i < CALIB_CHAN_5G_MAX; i++) { + _cl_calib_set_channel(cl_hw, calib_channels_5g[i], CHNL_BW_80); + _cl_calib_set_channel(cl_hw, calib_channels_5g[i], CHNL_BW_20); + } +} + +static void cl_calib_channels_24g(struct cl_hw *cl_hw) +{ + int i; + + for (i = 0; i < CALIB_CHAN_24G_MAX; i++) { + _cl_calib_set_channel(cl_hw, calib_channels_24g[i], CHNL_BW_40); + _cl_calib_set_channel(cl_hw, calib_channels_24g[i], CHNL_BW_20); + } +} + +static void cl_calib_scan_all_channels(struct cl_hw *cl_hw) +{ + if (cl_band_is_6g(cl_hw)) + cl_calib_channels_6g(cl_hw); + else if (cl_band_is_5g(cl_hw)) + cl_calib_channels_5g(cl_hw); + else + cl_calib_channels_24g(cl_hw); +} + +static void cl_calib_restore_channel(struct cl_hw *cl_hw, struct cl_calib_restore *calib_restore) +{ + u8 bw = calib_restore->bw; + u32 primary = calib_restore->primary; + u32 center = calib_restore->center; + u8 channel = calib_restore->channel; + + cl_msg_tx_set_channel(cl_hw, channel, bw, primary, center); +} + +static void cl_calib_print_errors(struct cl_hw *cl_hw) +{ + struct cl_calib_errors *errors = &cl_hw->chip->calib_db.errors[cl_hw->tcv_idx]; + + if (!errors->dcoc && !errors->lolc && !errors->iq_rx && !errors->iq_tx) + return; + + pr_warn("Calibration errors: DCOC %u, LOLC %u, IQ RX %u, IQ TX %u\n", + errors->dcoc, errors->lolc, errors->iq_rx, errors->iq_tx); +} + +static u8 cl_calib_channel_to_idx(struct cl_hw *cl_hw, u8 channel) +{ + u8 i = 0; + + if (cl_band_is_6g(cl_hw)) { + for (i = 0; i < CALIB_CHAN_6G_MAX; i++) + if (calib_channels_6g[i] == channel) + return i; + } else if (cl_band_is_5g(cl_hw)) { + for (i = 0; i < CALIB_CHAN_5G_MAX; i++) + if (calib_channels_5g[i] == channel) + return i; + } else { + for (i = 0; i < CALIB_CHAN_24G_MAX; i++) + if (calib_channels_24g[i] == channel) + return i; + } + + return 0; +} + +static void cl_calib_check_err_dcoc(struct cl_hw *cl_hw, s16 calib_temperature, + int channel, u8 bw) +{ + struct cl_chip *chip = cl_hw->chip; + int lna, ant; + struct cl_dcoc_report *dcoc_calib_report_dma; + u8 dcoc_threshold = chip->conf->ci_dcoc_mv_thr[bw]; + s16 i, q; + + for (lna = 0; lna < DCOC_LNA_GAIN_NUM; lna++) { + ant_for_each(ant) { + dcoc_calib_report_dma = + &cl_hw->iq_dcoc_data_info.iq_dcoc_data->report.dcoc[lna][ant]; + i = (s16)le16_to_cpu(dcoc_calib_report_dma->i_dc); + q = (s16)le16_to_cpu(dcoc_calib_report_dma->q_dc); + + if (abs(i) > dcoc_threshold) { + chip->calib_db.errors[cl_hw->tcv_idx].dcoc++; + cl_dbg_info(cl_hw, + "DCOC Error: lna = %u, ant = %u, " + "i (|%d|) > threshold (%d)\n", + lna, ant, i, dcoc_threshold); + } else { + cl_dbg_info(cl_hw, + "DCOC Valid: lna = %u, ant = %u, " + "i (|%d|) < threshold (%d)\n", + lna, ant, i, dcoc_threshold); + } + + if (abs(q) > dcoc_threshold) { + chip->calib_db.errors[cl_hw->tcv_idx].dcoc++; + cl_dbg_info(cl_hw, + "DCOC Error: lna = %u, ant = %u, " + "q (|%d|) > threshold (%d)\n", + lna, ant, q, dcoc_threshold); + } else { + cl_dbg_info(cl_hw, + "DCOC Valid: lna = %u, ant = %u, " + "q (|%d|) < threshold (%d)\n", + lna, ant, q, dcoc_threshold); + } + } + } +} + +static void cl_calib_check_err_iq_lolc(struct cl_hw *cl_hw, s16 calib_temperature, + int channel, u8 bw, u8 plan_bitmap) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_iq_dcoc_report *report = &cl_hw->iq_dcoc_data_info.iq_dcoc_data->report; + int ant; + struct cl_lolc_report lolc_report_dma; + s16 lolc_threshold = chip->conf->ci_lolc_db_thr; + s32 lolc_qual = 0; + + ant_for_each(ant) { + if ((plan_bitmap & (1 << ant)) == 0) + continue; + + lolc_report_dma = report->lolc_report[ant]; + lolc_qual = (s16)le16_to_cpu(lolc_report_dma.lolc_qual) >> 8; + + if (lolc_qual > lolc_threshold) { + chip->calib_db.errors[cl_hw->tcv_idx].lolc++; + + cl_dbg_info(cl_hw, + "LOLC Error: ant = %u, n_iter = %u, " + "quality (%d) > threshold (%d)\n", + ant, lolc_report_dma.n_iter, lolc_qual, lolc_threshold); + } else { + cl_dbg_info(cl_hw, + "LOLC Valid: ant = %u, n_iter = %u, " + "quality (%d) < threshold (%d)\n", + ant, lolc_report_dma.n_iter, lolc_qual, lolc_threshold); + } + } +} + +static void cl_calib_check_err_iq(struct cl_hw *cl_hw, s16 calib_temperature, + u8 ch, u8 bw, u8 plan_bitmap) +{ + struct cl_chip *chip = cl_hw->chip; + u8 tcv_idx = cl_hw->tcv_idx; + u8 ant = 0; + struct cl_iq_report iq_report_dma; + s8 iq_threshold = cl_hw->chip->conf->ci_iq_db_thr; + + ant_for_each(ant) { + if ((plan_bitmap & (1 << ant)) == 0) + continue; + + iq_report_dma = cl_hw->iq_dcoc_data_info.iq_dcoc_data->report.iq_tx[ant]; + + if (iq_report_dma.ir_db_avg_post > iq_threshold) { + chip->calib_db.errors[tcv_idx].iq_tx++; + cl_dbg_info(cl_hw, "IQ TX Error: ant = %u, ir (%d) > threshold (%d)\n", + ant, iq_report_dma.ir_db_avg_post, iq_threshold); + } else { + cl_dbg_info(cl_hw, "IQ TX Valid: ant = %u, ir (%d) < threshold (%d)\n", + ant, iq_report_dma.ir_db_avg_post, iq_threshold); + } + + iq_report_dma = cl_hw->iq_dcoc_data_info.iq_dcoc_data->report.iq_rx[ant]; + + if (iq_report_dma.ir_db_avg_post > iq_threshold) { + chip->calib_db.errors[tcv_idx].iq_rx++; + cl_dbg_info(cl_hw, "IQ RX Error: ant = %u, ir (%d) > threshold (%d)\n", + ant, iq_report_dma.ir_db_avg_post, iq_threshold); + } else { + cl_dbg_info(cl_hw, "IQ RX Valid: ant = %u, ir (%d) < threshold (%d)\n", + ant, iq_report_dma.ir_db_avg_post, iq_threshold); + } + } +} + +static u8 cl_calib_center_freq_to_idx(struct cl_hw *cl_hw, u32 center_freq) +{ + u8 i = 0; + u8 center_channel = ieee80211_frequency_to_channel(center_freq); + + if (cl_band_is_6g(cl_hw)) { + for (i = 1; i < CALIB_CHAN_6G_MAX; i++) + if (calib_channels_6g[i] > center_channel) + return (i - 1); + + return (CALIB_CHAN_6G_MAX - 1); + } + + if (cl_band_is_5g(cl_hw)) { + for (i = 1; i < CALIB_CHAN_5G_MAX; i++) + if (calib_channels_5g[i] > center_channel) + return (i - 1); + + return (CALIB_CHAN_5G_MAX - 1); + } + + for (i = 0; i < CALIB_CHAN_24G_MAX; i++) + if (abs(calib_channels_24g[i] - center_channel) < 3) + return i; + + return (CALIB_CHAN_24G_MAX - 1); +} + +static void cl_calib_fill_data_dcoc(struct cl_hw *cl_hw, struct cl_iq_dcoc_info *iq_dcoc_db) +{ + struct cl_chip *chip = cl_hw->chip; + u8 lna = 0, ant = 0; + u8 channel_idx = cl_calib_center_freq_to_idx(cl_hw, cl_hw->center_freq); + u8 bw = cl_hw->bw; + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + + for (lna = 0; lna < DCOC_LNA_GAIN_NUM; lna++) + ant_for_each(ant) + iq_dcoc_db->dcoc[lna][ant] = + chip->calib_db.dcoc[tcv_idx][channel_idx][bw][sx][ant][lna]; +} + +static void cl_calib_fill_data_iq(struct cl_hw *cl_hw, struct cl_iq_calib *iq_data, + struct cl_iq_calib *iq_chip_data) +{ + u8 ant = 0; + + ant_for_each(ant) { + iq_data[ant].coef0 = cpu_to_le32(iq_chip_data[ant].coef0); + iq_data[ant].coef1 = cpu_to_le32(iq_chip_data[ant].coef1); + iq_data[ant].coef2 = cpu_to_le32(iq_chip_data[ant].coef2); + iq_data[ant].gain = cpu_to_le32(iq_chip_data[ant].gain); + } +} + +static void cl_calib_fill_data_iq_lolc(struct cl_hw *cl_hw, __le32 *iq_lolc) +{ + struct cl_calib_db *calib_db = &cl_hw->chip->calib_db; + u8 ant = 0; + u8 chan_idx = cl_calib_center_freq_to_idx(cl_hw, cl_hw->center_freq); + u8 bw = cl_hw->bw; + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + + ant_for_each(ant) + iq_lolc[ant] = cpu_to_le32(calib_db->iq_tx_lolc[tcv_idx][chan_idx][bw][sx][ant]); +} + +static void cl_calib_handle_cfm_dcoc(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_dcoc_calib *dcoc_calib; + struct cl_dcoc_calib *dcoc_calib_dma; + struct calib_cfm *dcoc_iq_cfm = + &cl_hw->iq_dcoc_data_info.iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_DCOC]; + int lna, ant; + u16 raw_bits = (le16_to_cpu(dcoc_iq_cfm->raw_bits_data_0) + + le16_to_cpu(dcoc_iq_cfm->raw_bits_data_1)) / 2; + s16 calib_temperature = cl_temperature_calib_calc(cl_hw, raw_bits); + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + u8 channel = cl_hw->channel; + u8 bw = cl_hw->bw; + u8 channel_idx = cl_calib_channel_to_idx(cl_hw, channel); + + for (lna = 0; lna < DCOC_LNA_GAIN_NUM; lna++) { + ant_for_each(ant) { + dcoc_calib = &chip->calib_db.dcoc[tcv_idx][channel_idx][bw][sx][ant][lna]; + dcoc_calib_dma = + &cl_hw->iq_dcoc_data_info.iq_dcoc_data->iq_dcoc_db.dcoc[lna][ant]; + dcoc_calib->i = dcoc_calib_dma->i; + dcoc_calib->q = dcoc_calib_dma->q; + } + } + + cl_calib_check_err_dcoc(cl_hw, calib_temperature, channel, bw); + + /* + * Set the default status to FAIL, to ensure FW is actually changing the value, + * if the calibration succeeded. + */ + cl_hw->iq_dcoc_data_info.iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_DCOC].status = CALIB_FAIL; +} + +static void cl_calib_handle_cfm_iq(struct cl_hw *cl_hw, u8 plan_bitmap) +{ + struct calib_cfm *dcoc_iq_cfm = + &cl_hw->iq_dcoc_data_info.iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_IQ]; + u16 raw_bits_data_0 = le16_to_cpu(dcoc_iq_cfm->raw_bits_data_0); + u16 raw_bits_data_1 = le16_to_cpu(dcoc_iq_cfm->raw_bits_data_1); + u16 raw_bits = (raw_bits_data_0 + raw_bits_data_1) / 2; + s16 calib_temperature = cl_temperature_calib_calc(cl_hw, raw_bits); + u8 channel = cl_hw->channel; + u8 bw = cl_hw->bw; + int ant; + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + u8 channel_idx = cl_calib_channel_to_idx(cl_hw, channel); + + ant_for_each(ant) { + if ((plan_bitmap & (1 << ant)) == 0) + continue; + + cl_hw->chip->calib_db.iq_tx[tcv_idx][channel_idx][bw][sx][ant] = + cl_hw->iq_dcoc_data_info.iq_dcoc_data->iq_dcoc_db.iq_tx[ant]; + + cl_hw->chip->calib_db.iq_rx[tcv_idx][channel_idx][bw][sx][ant] = + cl_hw->iq_dcoc_data_info.iq_dcoc_data->iq_dcoc_db.iq_rx[ant]; + } + + cl_calib_check_err_iq(cl_hw, calib_temperature, channel, bw, plan_bitmap); + + /* + * Set the default status to FAIL, to ensure FW is actually changing the value, + * if the calibration succeeded. + */ + dcoc_iq_cfm->status = CALIB_FAIL; +} + +static void cl_calib_handle_cfm_iq_lolc(struct cl_hw *cl_hw, u8 plan_bitmap) +{ + struct calib_cfm *dcoc_iq_cfm = + &cl_hw->iq_dcoc_data_info.iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_IQ]; + u16 raw_bits = (le16_to_cpu(dcoc_iq_cfm->raw_bits_data_0) + + le16_to_cpu(dcoc_iq_cfm->raw_bits_data_1)) / 2; + s16 calib_temperature = cl_temperature_calib_calc(cl_hw, raw_bits); + u8 channel = cl_hw->channel; + u8 channel_idx = cl_calib_channel_to_idx(cl_hw, channel); + u8 bw = cl_hw->bw; + u8 sx = cl_hw->tcv_idx; + int ant; + + ant_for_each(ant) { + if ((plan_bitmap & (1 << ant)) == 0) + continue; + + cl_hw->chip->calib_db.iq_tx_lolc[cl_hw->tcv_idx][channel_idx][bw][sx][ant] = + cl_hw->iq_dcoc_data_info.iq_dcoc_data->iq_dcoc_db.iq_tx_lolc[ant]; + } + + cl_calib_check_err_iq_lolc(cl_hw, calib_temperature, channel, bw, plan_bitmap); + + /* + * Set the default status to FAIL, to ensure FW is actually changing the value, + * if the calibration succeeded. + */ + dcoc_iq_cfm->status = CALIB_FAIL; +} + +static void cl_calib_set_channel_start_work(struct work_struct *ws) +{ + struct cl_calib_work *calib_work = container_of(ws, struct cl_calib_work, ws); + struct cl_hw *cl_hw = calib_work->cl_hw; + struct cl_hw *cl_hw_other = cl_hw_other_tcv(cl_hw); + struct cl_chip *chip = cl_hw->chip; + + cl_calib_start(cl_hw); + + if (cl_chip_is_both_enabled(chip)) + cl_calib_start(cl_hw_other); + + chip->calib_db.scan_complete = true; +} + +int cl_calib_start(struct cl_hw *cl_hw) +{ + u8 channel = cl_hw->conf->ha_channel; + u8 bw = cl_hw->conf->ce_channel_bandwidth; + enum nl80211_chan_width width = NL80211_CHAN_WIDTH_20; + u32 primary = 0; + u32 center = 0; + + if (cl_chandef_calc(cl_hw, channel, bw, &width, &primary, ¢er)) + return -EINVAL; + + return cl_calib_set_channel(cl_hw, channel, bw, primary, center); +} + +void cl_calib_fill_phy_data(struct cl_hw *cl_hw, struct cl_iq_dcoc_info *iq_dcoc_db, u8 flags) +{ + struct cl_chip *chip = cl_hw->chip; + u8 channel_idx = cl_calib_center_freq_to_idx(cl_hw, cl_hw->center_freq); + u8 bw = cl_hw->bw; + u8 tcv_idx = cl_hw->tcv_idx; + + if (flags & SET_PHY_DATA_FLAGS_DCOC) + cl_calib_fill_data_dcoc(cl_hw, iq_dcoc_db); + + if (flags & SET_PHY_DATA_FLAGS_IQ_TX_LOLC) + cl_calib_fill_data_iq_lolc(cl_hw, iq_dcoc_db->iq_tx_lolc); + + if (flags & SET_PHY_DATA_FLAGS_IQ_TX) + cl_calib_fill_data_iq(cl_hw, iq_dcoc_db->iq_tx, + chip->calib_db.iq_tx[tcv_idx][channel_idx][bw][tcv_idx]); + + if (flags & SET_PHY_DATA_FLAGS_IQ_RX) + cl_calib_fill_data_iq(cl_hw, iq_dcoc_db->iq_rx, + chip->calib_db.iq_rx[tcv_idx][channel_idx][bw][tcv_idx]); +} + +int cl_calib_tables_alloc(struct cl_hw *cl_hw) +{ + struct cl_iq_dcoc_data *buf = NULL; + u32 len = sizeof(struct cl_iq_dcoc_data); + dma_addr_t phys_dma_addr; + + buf = dma_alloc_coherent(cl_hw->chip->dev, len, &phys_dma_addr, GFP_KERNEL); + + if (!buf) + return -1; + + cl_hw->iq_dcoc_data_info.iq_dcoc_data = buf; + cl_hw->iq_dcoc_data_info.dma_addr = cpu_to_le32(phys_dma_addr); + + cl_calib_init_cfm(cl_hw->iq_dcoc_data_info.iq_dcoc_data); + + return 0; +} + +void cl_calib_tables_free(struct cl_hw *cl_hw) +{ + struct cl_iq_dcoc_data_info *iq_dcoc_data_info = &cl_hw->iq_dcoc_data_info; + u32 len = sizeof(struct cl_iq_dcoc_data); + dma_addr_t phys_dma_addr = le32_to_cpu(iq_dcoc_data_info->dma_addr); + + if (!iq_dcoc_data_info->iq_dcoc_data) + return; + + dma_free_coherent(cl_hw->chip->dev, len, (void *)iq_dcoc_data_info->iq_dcoc_data, + phys_dma_addr); + iq_dcoc_data_info->iq_dcoc_data = NULL; +} + +bool cl_calib_is_needed(struct cl_hw *cl_hw, u8 channel, u8 bw) +{ + u8 channel_idx; + u8 tcv_idx = cl_hw->tcv_idx; + u8 ant; + u32 primary = 0; + u32 center_freq = 0; + enum nl80211_chan_width width = NL80211_CHAN_WIDTH_20; + + if (cl_chandef_calc(cl_hw, channel, bw, &width, &primary, ¢er_freq)) { + cl_dbg_err(cl_hw, "cl_chandef_calc failed\n"); + return false; + } + + channel_idx = cl_calib_center_freq_to_idx(cl_hw, center_freq); + + /* Check if we already calibrated */ + ant_for_each(ant) { + if (cl_hw->chip->calib_db.iq_tx_lolc[tcv_idx][channel_idx][bw][tcv_idx][ant]) + return false; + } + + return true; +} + +int cl_calib_set_channel(struct cl_hw *cl_hw, u8 channel, u8 bw, u32 primary, u32 center) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_hw *cl_hw_other = cl_hw_other_tcv(cl_hw); + struct cl_calib_restore calib_restore; + int ret = 0; + u8 fem_mode = cl_hw->fem_system_mode; + bool save_ch_other = !!cl_hw_other->primary_freq; + + if (save_ch_other) + cl_calib_save_channel(cl_hw_other, &calib_restore); + + ret = cl_calib_set_idle(cl_hw, true); + if (ret) + return ret; + + cl_fem_set_system_mode(cl_hw, FEM_MODE_LNA_BYPASS_ONLY, U8_MAX); + cl_afe_cfg_calib(chip); + + if (chip->conf->ce_calib_scan_en && !chip->calib_db.scan_complete && cl_hw->calib_ready) + cl_calib_scan_all_channels(cl_hw); + else + _cl_calib_set_channel(cl_hw, channel, bw); + + cl_fem_set_system_mode(cl_hw, fem_mode, U8_MAX); + cl_afe_cfg_restore(chip); + + _cl_msg_tx_set_channel(cl_hw, channel, bw, primary, center, SET_CHANNEL_MODE_OPERETIONAL); + + if (save_ch_other) + cl_calib_restore_channel(cl_hw_other, &calib_restore); + + cl_calib_set_idle(cl_hw, false); + + return ret; +} + +void cl_calib_start_work(struct cl_hw *cl_hw) +{ + struct cl_calib_work *calib_work = kzalloc(sizeof(*calib_work), GFP_ATOMIC); + + if (!calib_work) + return; + + calib_work->cl_hw = cl_hw; + INIT_WORK(&calib_work->ws, cl_calib_set_channel_start_work); + queue_work(cl_hw->drv_workqueue, &calib_work->ws); +} + +int cl_calib_handle_cfm(struct cl_hw *cl_hw, u8 mode) +{ + struct cl_iq_dcoc_data *iq_dcoc_data = cl_hw->iq_dcoc_data_info.iq_dcoc_data; + struct cl_calib_errors *errors = &cl_hw->chip->calib_db.errors[cl_hw->tcv_idx]; + + /* + * In case any of the requested calibrations failed - no need to copy + * the other Calibration data, and fail the whole calibration process. + */ + if ((mode & SET_CHANNEL_MODE_CALIB_DCOC && + iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_DCOC].status != CALIB_SUCCESS) || + (mode & SET_CHANNEL_MODE_CALIB_IQ && + iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_IQ].status != CALIB_SUCCESS)) { + cl_dbg_err(cl_hw, "Calibration failed! mode = %u, DCOC_CFM_STATUS = %u, " + "IQ_CFM_STATUS = %u\n", + mode, + iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_DCOC].status, + iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_IQ].status); + /* Set status to CALIB_FAIL to ensure that FW is writing the values. */ + iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_DCOC].status = CALIB_FAIL; + iq_dcoc_data->dcoc_iq_cfm[CALIB_CFM_IQ].status = CALIB_FAIL; + return -1; + } + + if (mode & SET_CHANNEL_MODE_CALIB_DCOC) + cl_calib_handle_cfm_dcoc(cl_hw); + + if (mode & SET_CHANNEL_MODE_CALIB_IQ) + cl_calib_handle_cfm_iq(cl_hw, cl_hw->mask_num_antennas); + + if (mode & SET_CHANNEL_MODE_CALIB_LOLC) + cl_calib_handle_cfm_iq_lolc(cl_hw, cl_hw->mask_num_antennas); + + /* Print calibration errors counters */ + cl_calib_print_errors(cl_hw); + + memset(errors, 0, sizeof(*errors)); + + return 0; +} + +int cl_calib_validate_ants(struct cl_hw *cl_hw) +{ + struct cl_tcv_conf *conf = cl_hw->conf; + u8 ant = 0; + int ret = 0; + + for (ant = 0; ant < cl_hw->num_antennas; ant++) { + if (conf->ci_calib_ant_tx[ant] < cl_hw->first_ant || + conf->ci_calib_ant_tx[ant] > cl_hw->last_ant) { + CL_DBG_ERROR(cl_hw, + "TX: Antenna [%u] value is out of boundaries [%u].\n" + "Minimum value allowed is: %u\n" + "Maximum value allowed is: %u\n", + ant, conf->ci_calib_ant_tx[ant], cl_hw->first_ant, + cl_hw->last_ant); + ret = -1; + } + + if (conf->ci_calib_ant_rx[ant] < cl_hw->first_ant || + conf->ci_calib_ant_rx[ant] > cl_hw->last_ant) { + CL_DBG_ERROR(cl_hw, + "RX: Antenna [%u] value is out of boundaries [%u]." + "Minimum value allowed is: %u\n" + "Maximum value allowed is: %u\n", + ant, conf->ci_calib_ant_tx[ant], cl_hw->first_ant, + cl_hw->last_ant); + ret = -1; + } + } + + return ret; +} + +void cl_calib_iq_get_tone_vector(u8 bw, u16 *tone_vector) +{ + u8 tone = 0; + + for (tone = 0; tone < IQ_NUM_TONES_REQ; tone++) + tone_vector[tone] = cpu_to_le16((u16)tone_vector_arr[bw][tone]); +} + +static int cl_calib_print_dcoc(struct cl_hw *cl_hw) +{ + struct cl_calib_db *calib_db = &cl_hw->chip->calib_db; + struct cl_dcoc_calib *dcoc_calib; + u8 lna = 0; + u8 ant = 0; + u8 channel_idx = cl_calib_center_freq_to_idx(cl_hw, cl_hw->center_freq); + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + u8 bw = cl_hw->bw; + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + int len = 0; + + if (!buf) + return -ENOMEM; + + len += snprintf(buf + len, PAGE_SIZE - len, + "DCOC:\n" + "LNA GAIN ANTENNA I Q\n" + "----------------------------\n"); + + for (lna = 0; lna < DCOC_LNA_GAIN_NUM; lna++) { + ant_for_each(ant) { + dcoc_calib = + &calib_db->dcoc[tcv_idx][channel_idx][bw][sx][ant][lna]; + + len += snprintf(buf + len, PAGE_SIZE - len, + "%-11u%-10u%-5d%-5d\n", lna, + ant, dcoc_calib->i, dcoc_calib->q); + } + } + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static int cl_calib_print_lolc(struct cl_hw *cl_hw) +{ + struct cl_calib_db *calib_db = &cl_hw->chip->calib_db; + u32 lolc_calib; + u8 ant = 0; + u8 channel_idx = cl_calib_center_freq_to_idx(cl_hw, cl_hw->center_freq); + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + u8 bw = cl_hw->bw; + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + int len = 0; + + if (!buf) + return -ENOMEM; + + len += snprintf(buf + len, PAGE_SIZE - len, + "LOLC:\n" + "ANTENNA I Q\n" + "---------------------\n"); + + ant_for_each(ant) { + lolc_calib = calib_db->iq_tx_lolc[tcv_idx][channel_idx][bw][sx][ant]; + + len += snprintf(buf + len, PAGE_SIZE - len, + "%-10u%-6d%-6d\n", + ant, CAST_S12_TO_S32(lolc_calib & U12_BIT_MASK), + CAST_S12_TO_S32((lolc_calib >> 2) & U12_BIT_MASK)); + } + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static int cl_calib_print_iq(struct cl_hw *cl_hw) +{ + struct cl_calib_db *calib_db = &cl_hw->chip->calib_db; + struct cl_iq_calib *iq; + u8 ant = 0; + u8 channel_idx = cl_calib_center_freq_to_idx(cl_hw, cl_hw->center_freq); + u8 tcv_idx = cl_hw->tcv_idx; + u8 sx = tcv_idx; + u8 bw = cl_hw->bw; + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + int len = 0; + + if (!buf) + return -ENOMEM; + + len += snprintf(buf + len, PAGE_SIZE - len, + "IQ TX:\n" + "ANTENNA COEF0 COEF1 COEF2 GAIN\n" + "---------------------------------------------------\n"); + + ant_for_each(ant) { + iq = &calib_db->iq_tx[tcv_idx][channel_idx][bw][sx][ant]; + + len += snprintf(buf + len, PAGE_SIZE - len, + "%-7u 0x%08x 0x%08x 0x%08x 0x%08x\n", + ant, iq->coef0, iq->coef1, iq->coef2, iq->gain); + } + + len += snprintf(buf + len, PAGE_SIZE - len, + "IQ RX:\n" + "ANTENNA COEF0 COEF1 COEF2 GAIN\n" + "---------------------------------------------------\n"); + + ant_for_each(ant) { + iq = &calib_db->iq_rx[tcv_idx][channel_idx][bw][sx][ant]; + + len += snprintf(buf + len, PAGE_SIZE - len, + "%-7u 0x%08x 0x%08x 0x%08x 0x%08x\n", + ant, iq->coef0, iq->coef1, iq->coef2, iq->gain); + } + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static int cl_calib_common_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "calib usage:\n" + "-d : Print DCOC coefficients\n" + "-i : Print IQ coefficients\n" + "-l : Print LOLC coefficients\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +int cl_calib_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + switch (cli_params->option) { + case 'd': + return cl_calib_print_dcoc(cl_hw); + case 'i': + return cl_calib_print_iq(cl_hw); + case 'l': + return cl_calib_print_lolc(cl_hw); + case '?': + return cl_calib_common_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", + cli_params->option); + return 0; + } +} From patchwork Thu Jun 17 15:58:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CE5EC48BE5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 030/256] cl8k: add cap.c Date: Thu, 17 Jun 2021 15:58:37 +0000 Message-Id: <20210617160223.160998-31-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:06 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cfd45bd2-124e-4905-4e7d-08d931a96541 X-MS-TrafficTypeDiagnostic: AM9P192MB0966: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:873; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8JG5NF5teuqUtOFcXzuqSXCDV4zV5KUtXqeOB1oOFq6p6XNjx2hRkMXWfwM8RNxESbgaDE7XtUi2eU/nSf6e5UZRAADUodOEuTj1KkBA7ugH4dAVX4vYiNaDTYbDEigq1MVD5SF64GJE8xRLx0bS2Azm4m+dG1QsNDx9wnacsk5EBrY8JNQsaD0l19FG/YWYcJE2tYLRf0ocL8qiHu3rmuRsuC6Q+wKdyIaoPEWBZd6B1bk4K5ApH2IcVJ2mHd+TR1aY/QKhq+wuWIqIpGljZjWWzmDqgZ4rsWDeOoM6u9j6A75XLMnulfqAl+xjaKgvRelJAJ6OsOn0Cg84mGhkZjrxAEm/elig+1YvRAXCurhlwMrCAHwEbKYlLRWyFmcnbZdbmM7lR2jZruBOx8bEgdH+fdX3XEz9XW5lINSbjnq5LsrZJ9DUHctw9tcntM3/4FchE6Pb8VE9vuApdDxGH3CsFuhEyG3p8q5ZHaXBmwbYx4ETnXBZdEJ1dO8wGgSwN0/4HgbLM7gpw2Z5Gx7IL5khwA6SReYM9VuJTqNypkihuAxWbzMVY2wFyc5gDUgdWZL+31HRlUBgZOKbFekBXt2O2cEFB3jAMs93WNClsLorBh07VZlhls0WLAtS85I6pX/oNg0TFKEGkv15Ta/a/eJgQnuI4ELH3ZH2k6he1CMoVeDf51OFtXs87yaPAqXgrVD4vwqc7reX+egk3vZfDQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(366004)(346002)(39850400004)(376002)(396003)(30864003)(4326008)(1076003)(2616005)(8676002)(186003)(6512007)(6486002)(107886003)(83380400001)(6916009)(38100700002)(55236004)(316002)(16526019)(6506007)(38350700002)(6666004)(54906003)(8936002)(26005)(508600001)(36756003)(2906002)(9686003)(52116002)(956004)(5660300002)(66946007)(66556008)(66476007)(86362001)(69590400013)(32563001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: F8RL9GhuGDiv5ZA/JTO/Qc1AHOccf/kWH061aMqXIE18qqLS/KIgueN877uf87bBqbJUjUhAvAOCdEYDEIPmNimpi3X8LrTpRiAwJZ+qEOZAegOT+5KuwzZSdooGl9ufzTjqMfyTfz/rDGKIGpFI5m8hxN0dDc2jjJQ3NM87qEuTD3FXTxvtJH/ouTSNtvtQHygBmSBvRv+XLcvVM4iLHWo5w0ltdILmq9ESSWJ4B9h3mkA6LAFp7GjUOs7onSxoeZg8NA8LwKEbH+jHfmJ4+emiOTvZe3NseTpSWnbPhEq6ah069/7h0zHzn9QaMvwwIAOToK9IEYEz/bBxytas24XTBa5hM95su0WZiRjqqKnh07QYws1v95IA2kCP7c/0Y2D5ng3vLx694jYHC7aFkQG4vQ5d1B6qqO62RTRWJDQtqYe1aeNPLyJ1c3XCbJCnsbjOp7h9kDBQUBXBQSmB1LDp3KbnAiTCSC4aLozVzJIF7D0yMt802Nid/8VLuCj/+A2bMUqfXv+mDZvGYlhmxgcvIqfeyF2YRQMxcXjymR68rNX6d/ze84D5jQ9pjjeZZTwkIueKyQ6dHpc/xapnB5gqHiCcg49VbbHaLfrEXRj6HLkh/ilkSQm8Lm+2VNPOm9x0TTWsdXOzPc9bRx8LVSNQPfCyLMb/uLkQslmrNPhgRaBg7LGFvj6RVw0KHlmKbbGmVFkN9yweDFFTpdB4ArBpYPD1GAwnJo6EKXphbXGyaZOK1+U3dh9mHpMPf5OZkLk6Zbqx9PGWBbcBX+AnjHRCGMDgm2yGyIj10TRvcMyYRvhsoJBc9F+1/DqQt7fP9hNuIbXG/m5ryv3N8klRjMVWdkrk8Zmd+k15kCxBGL8kcJfN8CfDDsx1yFywNG04fIR3t0kasO9zE6hKFbJkcNYwZrJuPGgTkjKOMXr9vndHuN1Wx8a+8gLY/1XQGeZK8mDdVBV7x67GU8XECluc5c1vFYHeXsmVd/YStXrJzGQ9MHv+8tT/jVpLBxedIbjfj5BrPMaNdv4aM219N3s0jx7E3TNo7nKu2lBmYphtAS+2UJauTok89Cdhyz1ysP/QS8SqvwS0qUtPk6ZG9XFohNz4S64PjvnJQii8CFw73QgKClFqqj/LOirHdMu5MeBOEhiJiz2dpHkCPM//t93+LjYx+sZcftnlkzhJWwM1rSOhLU4XnFvn56NYZFUm1RwWkQHCsBDs5c26kButBikpS4ff/Zzwrtc4ATW/DDVIent5gMPQ6ndSY+PIgLMAkHh4SnLo8xy6I0RTpyyzCeZA/sOzlVnI/mDrUul9rnOBmKYysZX0aVzXjR4IOIRh3EqY X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: cfd45bd2-124e-4905-4e7d-08d931a96541 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:07.1780 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mkvuawmXGSCGAAf6AmRzhVttEjWgyobcaVB6RjyDYE+yQl7jEzXPGY+PrSWT1Yl1jKmXJORs7pnjHwwPh8RJvg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0966 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/cap.c | 928 +++++++++++++++++++++++++ 1 file changed, 928 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/cap.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/cap.c b/drivers/net/wireless/celeno/cl8k/cap.c new file mode 100644 index 000000000000..bfd884706aa7 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/cap.c @@ -0,0 +1,928 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "cap.h" +#include "utils/utils.h" +#include "debug.h" +#include "band.h" +#include "chan_info.h" +#include "tx/tx.h" +#include "sta.h" +#include "rx/rx_amsdu.h" + +#define CL_HT_CAPABILITIES \ +{ \ + .ht_supported = true, \ + .cap = IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU, \ + .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K, \ + .ampdu_density = IEEE80211_HT_MPDU_DENSITY_1, \ + .mcs = { \ + .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ + .rx_highest = cpu_to_le16(65), \ + .tx_params = IEEE80211_HT_MCS_TX_DEFINED, \ + }, \ +} + +#define CL_VHT_CAPABILITIES \ +{ \ + .vht_supported = false, \ + .cap = \ + IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | \ + IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | \ + IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | \ + IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | \ + (3 << IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT) | \ + (3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT), \ + .vht_mcs = { \ + .rx_mcs_map = cpu_to_le16( \ + IEEE80211_VHT_MCS_SUPPORT_0_7 << 0 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 2 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 14), \ + .tx_mcs_map = cpu_to_le16( \ + IEEE80211_VHT_MCS_SUPPORT_0_7 << 0 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 2 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | \ + IEEE80211_VHT_MCS_NOT_SUPPORTED << 14), \ + } \ +} + +#define CL_HE_CAP_ELEM_STATION \ +{ \ + .mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE, \ + .mac_cap_info[1] = 0, \ + .mac_cap_info[2] = 0, \ + .mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2, \ + .mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_BQR, \ + .mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, \ + .phy_cap_info[0] = IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G, \ + .phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A, \ + .phy_cap_info[2] = 0, \ + .phy_cap_info[3] = 0, \ + .phy_cap_info[4] = 0, \ + .phy_cap_info[5] = 0, \ + .phy_cap_info[6] = 0, \ + .phy_cap_info[7] = 0, \ + .phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G, \ + .phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US, \ + .phy_cap_info[10] = 0, \ +} + +#define CL_HE_CAP_ELEM_AP \ +{ \ + .mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE, \ + .mac_cap_info[1] = 0, \ + .mac_cap_info[2] = 0, \ + .mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2, \ + .mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_BQR, \ + .mac_cap_info[5] = 0, \ + .phy_cap_info[0] = 0, \ + .phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A, \ + .phy_cap_info[2] = 0, \ + .phy_cap_info[3] = 0, \ + .phy_cap_info[4] = 0, \ + .phy_cap_info[5] = 0, \ + .phy_cap_info[6] = 0, \ + .phy_cap_info[7] = 0, \ + .phy_cap_info[8] = 0, \ + .phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US, \ + .phy_cap_info[10] = 0, \ +} + +#define CL_HE_CAP_ELEM_MESH_POINT \ +{ \ + .mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE, \ + .mac_cap_info[1] = 0, \ + .mac_cap_info[2] = 0, \ + .mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2, \ + .mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_BQR, \ + .mac_cap_info[5] = 0, \ + .phy_cap_info[0] = 0, \ + .phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A, \ + .phy_cap_info[2] = 0, \ + .phy_cap_info[3] = 0, \ + .phy_cap_info[4] = 0, \ + .phy_cap_info[5] = 0, \ + .phy_cap_info[6] = 0, \ + .phy_cap_info[7] = 0, \ + .phy_cap_info[8] = 0, \ + .phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US, \ + .phy_cap_info[10] = 0, \ +} + +#define CL_HE_MCS_NSS_SUPP \ +{ \ + .rx_mcs_80 = cpu_to_le16(0xff00), \ + .tx_mcs_80 = cpu_to_le16(0xff00), \ + .rx_mcs_160 = cpu_to_le16(0xff00), \ + .tx_mcs_160 = cpu_to_le16(0xff00), \ + .rx_mcs_80p80 = cpu_to_le16(0xffff), \ + .tx_mcs_80p80 = cpu_to_le16(0xffff), \ +} + +#define RATE(_bitrate, _hw_rate, _flags) { \ + .bitrate = (_bitrate), \ + .flags = (_flags), \ + .hw_value = (_hw_rate), \ +} + +#define CHAN(_freq, _idx) { \ + .center_freq = (_freq), \ + .hw_value = (_idx), \ + .max_power = 18, \ +} + +#define CHANF(_freq, _idx, _flags) { \ + .center_freq = (_freq), \ + .hw_value = (_idx), \ + .flags = (_flags), \ + .max_power = 18, \ +} + +static struct ieee80211_sband_iftype_data cl_he_data[] = { + { + .types_mask = BIT(NL80211_IFTYPE_STATION), + .he_cap = { + .has_he = true, + .he_cap_elem = CL_HE_CAP_ELEM_STATION, + .he_mcs_nss_supp = CL_HE_MCS_NSS_SUPP, + }, + }, + { + .types_mask = BIT(NL80211_IFTYPE_AP), + .he_cap = { + .has_he = true, + .he_cap_elem = CL_HE_CAP_ELEM_AP, + .he_mcs_nss_supp = CL_HE_MCS_NSS_SUPP, + }, + }, + { + .types_mask = BIT(NL80211_IFTYPE_MESH_POINT), + .he_cap = { + .has_he = true, + .he_cap_elem = CL_HE_CAP_ELEM_MESH_POINT, + .he_mcs_nss_supp = CL_HE_MCS_NSS_SUPP, + }, + }, +}; + +static struct ieee80211_rate cl_ratetable[] = { + RATE(10, 0x00, 0), + RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE), + RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE), + RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE), + RATE(60, 0x04, 0), + RATE(90, 0x05, 0), + RATE(120, 0x06, 0), + RATE(180, 0x07, 0), + RATE(240, 0x08, 0), + RATE(360, 0x09, 0), + RATE(480, 0x0A, 0), + RATE(540, 0x0B, 0), +}; + +/* The channels indexes here are not used anymore */ +static struct ieee80211_channel cl_2ghz_channels[] = { + CHAN(2412, 0), + CHAN(2417, 1), + CHAN(2422, 2), + CHAN(2427, 3), + CHAN(2432, 4), + CHAN(2437, 5), + CHAN(2442, 6), + CHAN(2447, 7), + CHAN(2452, 8), + CHAN(2457, 9), + CHAN(2462, 10), + CHAN(2467, 11), + CHAN(2472, 12), + CHAN(2484, 13), +}; + +static struct ieee80211_channel cl_5ghz_channels[] = { + CHAN(5180, 0), /* 36 - 20MHz */ + CHAN(5200, 1), /* 40 - 20MHz */ + CHAN(5220, 2), /* 44 - 20MHz */ + CHAN(5240, 3), /* 48 - 20MHz */ + + CHANF(5260, 4, IEEE80211_CHAN_RADAR), /* 52 - 20MHz */ + CHANF(5280, 5, IEEE80211_CHAN_RADAR), /* 56 - 20MHz */ + CHANF(5300, 6, IEEE80211_CHAN_RADAR), /* 60 - 20MHz */ + CHANF(5320, 7, IEEE80211_CHAN_RADAR), /* 64 - 20MHz */ + CHANF(5500, 8, IEEE80211_CHAN_RADAR), /* 100 - 20MHz */ + CHANF(5520, 9, IEEE80211_CHAN_RADAR), /* 104 - 20MHz */ + CHANF(5540, 10, IEEE80211_CHAN_RADAR), /* 108 - 20MHz */ + CHANF(5560, 11, IEEE80211_CHAN_RADAR), /* 112 - 20MHz */ + CHANF(5580, 12, IEEE80211_CHAN_RADAR), /* 116 - 20MHz */ + CHANF(5600, 13, IEEE80211_CHAN_RADAR), /* 120 - 20MHz */ + CHANF(5620, 14, IEEE80211_CHAN_RADAR), /* 124 - 20MHz */ + CHANF(5640, 15, IEEE80211_CHAN_RADAR), /* 128 - 20MHz */ + CHANF(5660, 16, IEEE80211_CHAN_RADAR), /* 132 - 20MHz */ + CHANF(5680, 17, IEEE80211_CHAN_RADAR), /* 136 - 20MHz */ + CHANF(5700, 18, IEEE80211_CHAN_RADAR), /* 140 - 20MHz */ + + CHAN(5720, 19), /* 144 - 20MHz */ + CHAN(5745, 20), /* 149 - 20MHz */ + CHAN(5765, 21), /* 153 - 20MHz */ + CHAN(5785, 22), /* 157 - 20MHz */ + CHAN(5805, 23), /* 161 - 20MHz */ + CHAN(5825, 24), /* 165 - 20MHz */ +}; + +static struct ieee80211_channel cl_6ghz_channels[] = { + CHAN(5955, 1), /* 1 - 20MHz */ + CHAN(5935, 2), /* 2 - 20MHz */ + CHAN(5975, 5), /* 5 - 20MHz */ + CHAN(5995, 9), /* 9 - 20MHz */ + CHAN(6015, 13), /* 13 - 20MHz */ + CHAN(6035, 17), /* 17 - 20MHz */ + CHAN(6055, 21), /* 21 - 20MHz */ + CHAN(6075, 25), /* 25 - 20MHz */ + CHAN(6095, 29), /* 29 - 20MHz */ + CHAN(6115, 33), /* 33 - 20MHz */ + CHAN(6135, 37), /* 37 - 20MHz */ + CHAN(6155, 41), /* 41 - 20MHz */ + CHAN(6175, 45), /* 45 - 20MHz */ + CHAN(6195, 49), /* 49 - 20MHz */ + CHAN(6215, 53), /* 53 - 20MHz */ + CHAN(6235, 57), /* 57 - 20MHz */ + CHAN(6255, 61), /* 61 - 20MHz */ + CHAN(6275, 65), /* 65 - 20MHz */ + CHAN(6295, 69), /* 69 - 20MHz */ + CHAN(6315, 73), /* 73 - 20MHz */ + CHAN(6335, 77), /* 77 - 20MHz */ + CHAN(6355, 81), /* 81 - 20MHz */ + CHAN(6375, 85), /* 85 - 20MHz */ + CHAN(6395, 89), /* 89 - 20MHz */ + CHAN(6415, 93), /* 93 - 20MHz */ + CHAN(6435, 97), /* 97 - 20MHz */ + CHAN(6455, 101), /* 101 - 20MHz */ + CHAN(6475, 105), /* 105 - 20MHz */ + CHAN(6495, 109), /* 109 - 20MHz */ + CHAN(6515, 113), /* 113 - 20MHz */ + CHAN(6535, 117), /* 117 - 20MHz */ + CHAN(6555, 121), /* 121 - 20MHz */ + CHAN(6575, 125), /* 125 - 20MHz */ + CHAN(6595, 129), /* 129 - 20MHz */ + CHAN(6615, 133), /* 133 - 20MHz */ + CHAN(6635, 137), /* 137 - 20MHz */ + CHAN(6655, 141), /* 141 - 20MHz */ + CHAN(6675, 145), /* 145 - 20MHz */ + CHAN(6695, 149), /* 149 - 20MHz */ + CHAN(6715, 153), /* 153 - 20MHz */ + CHAN(6735, 157), /* 157 - 20MHz */ + CHAN(6755, 161), /* 161 - 20MHz */ + CHAN(6775, 165), /* 165 - 20MHz */ + CHAN(6795, 169), /* 169 - 20MHz */ + CHAN(6815, 173), /* 173 - 20MHz */ + CHAN(6835, 177), /* 177 - 20MHz */ + CHAN(6855, 181), /* 181 - 20MHz */ + CHAN(6875, 188), /* 185 - 20MHz */ + CHAN(6895, 189), /* 189 - 20MHz */ + CHAN(6915, 193), /* 193 - 20MHz */ + CHAN(6935, 197), /* 197 - 20MHz */ + CHAN(6955, 201), /* 201 - 20MHz */ + CHAN(6975, 205), /* 205 - 20MHz */ + CHAN(6995, 209), /* 209 - 20MHz */ + CHAN(7015, 213), /* 213 - 20MHz */ + CHAN(7035, 217), /* 217 - 20MHz */ + CHAN(7055, 221), /* 221 - 20MHz */ + CHAN(7075, 225), /* 225 - 20MHz */ + CHAN(7095, 229), /* 229 - 20MHz */ + CHAN(7115, 233), /* 233 - 20MHz */ +}; + +static struct ieee80211_supported_band cl_band_2ghz = { + .channels = cl_2ghz_channels, + .n_channels = ARRAY_SIZE(cl_2ghz_channels), + .bitrates = cl_ratetable, + .n_bitrates = ARRAY_SIZE(cl_ratetable), + .ht_cap = CL_HT_CAPABILITIES, + .vht_cap = CL_VHT_CAPABILITIES, +}; + +static struct ieee80211_supported_band cl_band_5ghz = { + .channels = cl_5ghz_channels, + .n_channels = ARRAY_SIZE(cl_5ghz_channels), + .bitrates = &cl_ratetable[4], + .n_bitrates = ARRAY_SIZE(cl_ratetable) - 4, + .ht_cap = CL_HT_CAPABILITIES, + .vht_cap = CL_VHT_CAPABILITIES, +}; + +static struct ieee80211_supported_band cl_band_6ghz = { + .channels = cl_6ghz_channels, + .n_channels = ARRAY_SIZE(cl_6ghz_channels), + .bitrates = &cl_ratetable[4], + .n_bitrates = ARRAY_SIZE(cl_ratetable) - 4, +}; + +static const struct ieee80211_iface_limit cl_limits[] = { + { + .max = MAX_BSS_NUM, + .types = BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_MESH_POINT), + }, +}; + +static const u8 cl_if_types_ext_capa_ap[] = { + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, + [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, + [10] = WLAN_EXT_CAPA11_COMPLETE_LIST_OF_NONTXBSSID_PROFILES, +}; + +static const struct wiphy_iftype_ext_capab cl_iftypes_ext_capa[] = { + { + .iftype = NL80211_IFTYPE_AP, + .extended_capabilities = cl_if_types_ext_capa_ap, + .extended_capabilities_mask = cl_if_types_ext_capa_ap, + .extended_capabilities_len = sizeof(cl_if_types_ext_capa_ap), + }, +}; + +static const struct ieee80211_iface_combination cl_combinations[] = { + { + .limits = cl_limits, + .n_limits = ARRAY_SIZE(cl_limits), + .num_different_channels = 1, + .max_interfaces = MAX_BSS_NUM, + .beacon_int_min_gcd = 100, + .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20) | + BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_80) | + BIT(NL80211_CHAN_WIDTH_160), + } +}; + +static u8 he_mcs_supp_tx(struct cl_hw *cl_hw, u8 nss) +{ + u8 mcs = cl_hw->conf->ce_he_mcs_nss_supp_tx[nss]; + + switch (mcs) { + case WRS_MCS_7: + return IEEE80211_HE_MCS_SUPPORT_0_7; + case WRS_MCS_9: + return IEEE80211_HE_MCS_SUPPORT_0_9; + case WRS_MCS_11: + return IEEE80211_HE_MCS_SUPPORT_0_11; + } + + cl_dbg_err(cl_hw, "Invalid mcs %u for nss %u. Must be 7, 9 or 11!\n", mcs, nss); + return IEEE80211_HE_MCS_NOT_SUPPORTED; +} + +static u8 he_mcs_supp_rx(struct cl_hw *cl_hw, u8 nss) +{ + u8 mcs = cl_hw->conf->ce_he_mcs_nss_supp_rx[nss]; + + switch (mcs) { + case WRS_MCS_7: + return IEEE80211_HE_MCS_SUPPORT_0_7; + case WRS_MCS_9: + return IEEE80211_HE_MCS_SUPPORT_0_9; + case WRS_MCS_11: + return IEEE80211_HE_MCS_SUPPORT_0_11; + } + + cl_dbg_err(cl_hw, "Invalid mcs %u for nss %u. Must be 7, 9 or 11!\n", mcs, nss); + return IEEE80211_HE_MCS_NOT_SUPPORTED; +} + +static u8 vht_mcs_supp_tx(struct cl_hw *cl_hw, u8 nss) +{ + u8 mcs = cl_hw->conf->ce_vht_mcs_nss_supp_tx[nss]; + + switch (mcs) { + case WRS_MCS_7: + return IEEE80211_VHT_MCS_SUPPORT_0_7; + case WRS_MCS_8: + return IEEE80211_VHT_MCS_SUPPORT_0_8; + case WRS_MCS_9: + return IEEE80211_VHT_MCS_SUPPORT_0_9; + } + + cl_dbg_err(cl_hw, "Invalid mcs %u for nss %u. Must be 7-9!\n", mcs, nss); + return IEEE80211_VHT_MCS_NOT_SUPPORTED; +} + +static u8 vht_mcs_supp_rx(struct cl_hw *cl_hw, u8 nss) +{ + u8 mcs = cl_hw->conf->ce_vht_mcs_nss_supp_rx[nss]; + + switch (mcs) { + case WRS_MCS_7: + return IEEE80211_VHT_MCS_SUPPORT_0_7; + case WRS_MCS_8: + return IEEE80211_VHT_MCS_SUPPORT_0_8; + case WRS_MCS_9: + return IEEE80211_VHT_MCS_SUPPORT_0_9; + } + + cl_dbg_err(cl_hw, "Invalid mcs %u for nss %u. Must be 7-9!\n", mcs, nss); + return IEEE80211_VHT_MCS_NOT_SUPPORTED; +} + +static void cl_set_he_6ghz_capab(struct cl_hw *cl_hw) +{ + struct ieee80211_he_6ghz_capa *he_6ghz_cap0 = &cl_hw->iftype_data[0].he_6ghz_capa; + struct ieee80211_he_6ghz_capa *he_6ghz_cap1 = &cl_hw->iftype_data[1].he_6ghz_capa; + struct ieee80211_he_6ghz_capa *he_6ghz_cap2 = &cl_hw->iftype_data[2].he_6ghz_capa; + + he_6ghz_cap0->capa = cpu_to_le16(IEEE80211_HT_MPDU_DENSITY_1); + he_6ghz_cap0->capa |= + cpu_to_le16(cl_hw->conf->ha_max_mpdu_len << HE_6GHZ_CAP_MAX_MPDU_LEN_OFFSET); + he_6ghz_cap0->capa |= + cpu_to_le16(IEEE80211_VHT_MAX_AMPDU_1024K << HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP_OFFSET); + + he_6ghz_cap1->capa = he_6ghz_cap0->capa; + he_6ghz_cap2->capa = he_6ghz_cap0->capa; +} + +static void _cl_set_he_capab(struct cl_hw *cl_hw, u8 idx) +{ + struct ieee80211_sta_he_cap *he_cap = &cl_hw->iftype_data[idx].he_cap; + struct ieee80211_he_mcs_nss_supp *he_mcs_nss_supp = &he_cap->he_mcs_nss_supp; + struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; + u8 rx_nss = cl_hw->conf->ce_rx_nss; + u8 tx_nss = cl_hw->conf->ce_tx_nss; + int i = 0; + + if (BAND_IS_5G_6G(cl_hw)) { + he_cap_elem->phy_cap_info[0] |= + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; + + for (i = 0; i < rx_nss; i++) + he_mcs_nss_supp->rx_mcs_160 |= + cpu_to_le16(he_mcs_supp_rx(cl_hw, i) << (i * 2)); + + for (i = 0; i < tx_nss; i++) + he_mcs_nss_supp->tx_mcs_160 |= + cpu_to_le16(he_mcs_supp_tx(cl_hw, i) << (i * 2)); + + he_cap_elem->phy_cap_info[0] |= + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; + + for (i = 0; i < rx_nss; i++) + he_mcs_nss_supp->rx_mcs_80 |= + cpu_to_le16(he_mcs_supp_rx(cl_hw, i) << (i * 2)); + + for (i = 0; i < tx_nss; i++) + he_mcs_nss_supp->tx_mcs_80 |= + cpu_to_le16(he_mcs_supp_tx(cl_hw, i) << (i * 2)); + } else { + he_cap_elem->phy_cap_info[0] |= + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; + + for (i = 0; i < rx_nss; i++) + he_mcs_nss_supp->rx_mcs_80 |= + cpu_to_le16(he_mcs_supp_rx(cl_hw, i) << (i * 2)); + + for (i = 0; i < tx_nss; i++) + he_mcs_nss_supp->tx_mcs_80 |= + cpu_to_le16(he_mcs_supp_tx(cl_hw, i) << (i * 2)); + } + + for (i = rx_nss; i < 8; i++) { + he_mcs_nss_supp->rx_mcs_80 |= + cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); + he_mcs_nss_supp->rx_mcs_160 |= + cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); + } + + for (i = tx_nss; i < 8; i++) { + he_mcs_nss_supp->tx_mcs_80 |= + cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); + he_mcs_nss_supp->tx_mcs_160 |= + cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); + } + + if (cl_hw->conf->ce_he_rxldpc_en) + he_cap_elem->phy_cap_info[1] |= + IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; + + if (cl_hw->conf->ci_rx_he_mu_ppdu) + he_cap_elem->phy_cap_info[3] |= + IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; + + he_cap_elem->phy_cap_info[3] |= + IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; + he_cap_elem->phy_cap_info[5] |= + IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_4; +} + +static void cl_set_he_capab(struct cl_hw *cl_hw) +{ + struct ieee80211_sta_he_cap *he_cap0 = &cl_hw->iftype_data[0].he_cap; + struct ieee80211_sta_he_cap *he_cap1 = &cl_hw->iftype_data[1].he_cap; + struct ieee80211_he_cap_elem *he_cap_elem0 = &he_cap0->he_cap_elem; + struct ieee80211_he_cap_elem *he_cap_elem1 = &he_cap1->he_cap_elem; + + struct cl_tcv_conf *conf = cl_hw->conf; + u8 tf_mac_pad_dur = conf->ci_tf_mac_pad_dur; + + memcpy(&cl_hw->iftype_data, cl_he_data, sizeof(cl_hw->iftype_data)); + + /* TWT support */ + if (conf->ce_twt_en) { + /* STA mode */ + he_cap_elem0->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_REQ; + /* AP mode */ + he_cap_elem1->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; + } + + /* OMI support */ + if (conf->ce_omi_en) { + /* STA mode */ + he_cap_elem0->mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; + /* AP mode */ + he_cap_elem1->mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; + he_cap_elem1->mac_cap_info[5] |= IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; + } + + if (tf_mac_pad_dur == 1) + he_cap_elem0->mac_cap_info[1] |= IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_8US; + else if (tf_mac_pad_dur == 2) + he_cap_elem0->mac_cap_info[1] |= IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; + + _cl_set_he_capab(cl_hw, 0); + _cl_set_he_capab(cl_hw, 1); + _cl_set_he_capab(cl_hw, 2); + + if (cl_band_is_6g(cl_hw)) + cl_set_he_6ghz_capab(cl_hw); + + cl_hw->sband.n_iftype_data = ARRAY_SIZE(cl_he_data); + cl_hw->sband.iftype_data = cl_hw->iftype_data; +} + +void cl_cap_dyn_params(struct cl_hw *cl_hw) +{ + struct ieee80211_hw *hw = cl_hw->hw; + struct wiphy *wiphy = hw->wiphy; + struct cl_tcv_conf *conf = cl_hw->conf; + u8 rx_nss = conf->ce_rx_nss; + u8 tx_nss = conf->ce_tx_nss; + u8 guard_interval = conf->ha_short_guard_interval; + u8 i; + u8 bw = cl_hw->conf->ce_channel_bandwidth; + struct ieee80211_supported_band *sband = &cl_hw->sband; + struct ieee80211_sta_ht_cap *sband_ht_cap = &sband->ht_cap; + struct ieee80211_sta_vht_cap *sband_vht_cap = &sband->vht_cap; + + if (cl_band_is_6g(cl_hw)) { + memcpy(sband, &cl_band_6ghz, sizeof(struct ieee80211_supported_band)); + } else if (cl_band_is_5g(cl_hw)) { + memcpy(sband, &cl_band_5ghz, sizeof(struct ieee80211_supported_band)); + if (!conf->ci_ieee80211h) { + int i; + + for (i = 0; i < sband->n_channels; i++) + sband->channels[i].flags &= ~IEEE80211_CHAN_RADAR; + } + } else { + memcpy(sband, &cl_band_2ghz, sizeof(struct ieee80211_supported_band)); + + if (!conf->ci_vht_cap_24g) + memset(&sband->vht_cap, 0, sizeof(struct ieee80211_sta_vht_cap)); + } + + /* 6GHz doesn't support HT/VHT */ + if (!cl_band_is_6g(cl_hw)) { + if (bw > CHNL_BW_20) + sband_ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; + + /* Guard_interval */ + if (guard_interval) { + sband_ht_cap->cap |= IEEE80211_HT_CAP_SGI_20; + + if (bw >= CHNL_BW_40) + sband_ht_cap->cap |= IEEE80211_HT_CAP_SGI_40; + + if (bw >= CHNL_BW_80) + sband_vht_cap->cap |= IEEE80211_VHT_CAP_SHORT_GI_80; + + if (bw == CHNL_BW_160) + sband_vht_cap->cap |= IEEE80211_VHT_CAP_SHORT_GI_160; + } + } + + /* Amsdu */ + cl_rx_amsdu_hw_en(hw, conf->ce_rxamsdu_en); + cl_hw->txamsdu_en = conf->ce_txamsdu_en; + + /* Hw flags */ + ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); + ieee80211_hw_set(hw, SIGNAL_DBM); + ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); + ieee80211_hw_set(hw, QUEUE_CONTROL); + ieee80211_hw_set(hw, WANT_MONITOR_VIF); + ieee80211_hw_set(hw, SPECTRUM_MGMT); + ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); + ieee80211_hw_set(hw, HAS_RATE_CONTROL); + ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); + ieee80211_hw_set(hw, NO_AUTO_VIF); + + wiphy->features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE; + + /* Turn on "20/40 Coex Mgmt Support" bit (24g only) */ + if (cl_band_is_24g(cl_hw)) { + struct ieee80211_local *local = hw_to_local(hw); + + if (conf->ce_coex_en) + local->ext_capa[0] |= WLAN_EXT_CAPA1_2040_BSS_COEX_MGMT_ENABLED; + else + wiphy->features &= ~NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE; + } + + if (conf->ci_fast_rx_en) { + ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER); + ieee80211_hw_set(hw, AP_LINK_PS); + } + + /* + * To disable the dynamic PS we say to the stack that we support it in + * HW. This will force mac80211 rely on us to handle this. + */ + ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); + + if (conf->ci_agg_tx) + ieee80211_hw_set(hw, AMPDU_AGGREGATION); + + if (conf->ci_ieee80211w) + ieee80211_hw_set(hw, MFP_CAPABLE); + + wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_MESH_POINT); + + wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL | + WIPHY_FLAG_HAS_CHANNEL_SWITCH; + + if (conf->ce_uapsd_en) + wiphy->flags |= WIPHY_FLAG_AP_UAPSD; + + wiphy->iface_combinations = cl_combinations; + wiphy->n_iface_combinations = ARRAY_SIZE(cl_combinations); + + hw->max_rates = IEEE80211_TX_MAX_RATES; + hw->max_report_rates = IEEE80211_TX_MAX_RATES; + hw->max_rate_tries = 1; + + hw->max_tx_aggregation_subframes = conf->ce_max_agg_size_tx; + hw->max_rx_aggregation_subframes = conf->ce_max_agg_size_rx; + + hw->vif_data_size = sizeof(struct cl_vif); + hw->sta_data_size = sizeof(struct cl_sta); + + hw->extra_tx_headroom = 0; + hw->queues = IEEE80211_MAX_QUEUES; + hw->offchannel_tx_hw_queue = CL_HWQ_VO; + + if (!cl_band_is_6g(cl_hw)) { + if (conf->ce_ht_rxldpc_en) + sband_ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; + + sband_ht_cap->cap |= IEEE80211_HT_CAP_MAX_AMSDU; + sband_vht_cap->cap |= cl_hw->conf->ha_max_mpdu_len; + } + + if (cl_band_is_5g(cl_hw) || (cl_band_is_24g(cl_hw) && conf->ci_vht_cap_24g)) { + if (bw == CHNL_BW_160) + sband_vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; + + sband_vht_cap->cap |= (conf->ha_vht_max_ampdu_len_exp << + IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT); + + if (conf->ce_vht_rxldpc_en) + sband_vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; + + sband_vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(0); + sband_vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(0); + + for (i = 0; i < rx_nss; i++) + sband_vht_cap->vht_mcs.rx_mcs_map |= + cpu_to_le16(vht_mcs_supp_rx(cl_hw, i) << (i * 2)); + + for (; i < 8; i++) + sband_vht_cap->vht_mcs.rx_mcs_map |= + cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); + + for (i = 0; i < tx_nss; i++) + sband_vht_cap->vht_mcs.tx_mcs_map |= + cpu_to_le16(vht_mcs_supp_tx(cl_hw, i) << (i * 2)); + + for (; i < 8; i++) + sband_vht_cap->vht_mcs.tx_mcs_map |= + cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); + + sband_vht_cap->vht_mcs.rx_highest = cpu_to_le16(390 * rx_nss); + sband_vht_cap->vht_mcs.tx_highest = cpu_to_le16(390 * tx_nss); + sband_vht_cap->vht_supported = true; + } + + /* 6GHz band supports HE only */ + if (!cl_band_is_6g(cl_hw)) { + for (i = 0; i < rx_nss; i++) + sband_ht_cap->mcs.rx_mask[i] = U8_MAX; + + if (bw == CHNL_BW_20) + sband_ht_cap->mcs.rx_highest = guard_interval ? + cpu_to_le16(72 * rx_nss) : cpu_to_le16(65 * rx_nss); + else + sband_ht_cap->mcs.rx_highest = guard_interval ? + cpu_to_le16(150 * rx_nss) : cpu_to_le16(135 * rx_nss); + } + + if (cl_hw->conf->ce_wireless_mode > WIRELESS_MODE_HT_VHT) + cl_set_he_capab(cl_hw); + + /* Get channels and power limitations information from ChannelInfo file */ + cl_chan_info_init(cl_hw); + + if (cl_band_is_6g(cl_hw)) { + wiphy->bands[NL80211_BAND_2GHZ] = NULL; + wiphy->bands[NL80211_BAND_5GHZ] = NULL; + wiphy->bands[NL80211_BAND_6GHZ] = sband; + } else if (cl_band_is_5g(cl_hw)) { + wiphy->bands[NL80211_BAND_2GHZ] = NULL; + wiphy->bands[NL80211_BAND_5GHZ] = sband; + wiphy->bands[NL80211_BAND_6GHZ] = NULL; + } else { + wiphy->bands[NL80211_BAND_2GHZ] = sband; + wiphy->bands[NL80211_BAND_5GHZ] = NULL; + wiphy->bands[NL80211_BAND_6GHZ] = NULL; + } + + wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED; +} + +enum he_pkt_ext_constellations { + HE_PKT_EXT_BPSK = 0, + HE_PKT_EXT_QPSK, + HE_PKT_EXT_16QAM, + HE_PKT_EXT_64QAM, + HE_PKT_EXT_256QAM, + HE_PKT_EXT_1024QAM, + HE_PKT_EXT_RESERVED, + HE_PKT_EXT_NONE, +}; + +static u8 mcs_to_constellation[WRS_MCS_MAX_HE] = { + HE_PKT_EXT_BPSK, + HE_PKT_EXT_QPSK, + HE_PKT_EXT_QPSK, + HE_PKT_EXT_16QAM, + HE_PKT_EXT_16QAM, + HE_PKT_EXT_64QAM, + HE_PKT_EXT_64QAM, + HE_PKT_EXT_64QAM, + HE_PKT_EXT_256QAM, + HE_PKT_EXT_256QAM, + HE_PKT_EXT_1024QAM, + HE_PKT_EXT_1024QAM +}; + +#define QAM_THR_1 0 +#define QAM_THR_2 1 +#define QAM_THR_MAX 2 + +static u8 get_ppe_val(u8 *ppe, u8 ppe_pos_bit) +{ + u8 byte_num = ppe_pos_bit / 8; + u8 bit_num = ppe_pos_bit % 8; + u8 residue_bits; + u8 res; + + if (bit_num <= 5) + return (ppe[byte_num] >> bit_num) & + (BIT(IEEE80211_PPE_THRES_INFO_PPET_SIZE) - 1); + + /* + * If bit_num > 5, we have to combine bits with next byte. + * Calculate how many bits we need to take from current byte (called + * here "residue_bits"), and add them to bits from next byte. + */ + residue_bits = 8 - bit_num; + + res = (ppe[byte_num + 1] & + (BIT(IEEE80211_PPE_THRES_INFO_PPET_SIZE - residue_bits) - 1)) << + residue_bits; + res += (ppe[byte_num] >> bit_num) & (BIT(residue_bits) - 1); + + return res; +} + +static void set_fixed_ppe_val(u8 pe_dur[CHNL_BW_MAX][WRS_MCS_MAX_HE], u8 dur) +{ + u8 val = ((dur << 6) | (dur << 4) | (dur << 2) | dur); + + memset(pe_dur, val, CHNL_BW_MAX * WRS_MCS_MAX_HE); +} + +void cl_cap_ppe_duration(struct cl_hw *cl_hw, struct ieee80211_sta *sta, + u8 pe_dur[CHNL_BW_MAX][WRS_MCS_MAX_HE]) +{ + /* Force NVRAM parameter */ + if (cl_hw->conf->ci_pe_duration <= PPE_16US) { + set_fixed_ppe_val(pe_dur, cl_hw->conf->ci_pe_duration); + return; + } + + /* + * If STA sets the PPE Threshold Present subfield to 0, + * the value should be set according to the Nominal Packet Padding subfield + */ + if ((sta->he_cap.he_cap_elem.phy_cap_info[6] & + IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) == 0) { + switch (sta->he_cap.he_cap_elem.phy_cap_info[9] & + IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_MASK) { + case IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_0US: + set_fixed_ppe_val(pe_dur, PPE_0US); + break; + case IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_8US: + set_fixed_ppe_val(pe_dur, PPE_8US); + break; + case IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US: + default: + set_fixed_ppe_val(pe_dur, PPE_16US); + break; + } + + return; + } + + /* + * struct iwl_he_pkt_ext - QAM thresholds + * The required PPE is set via HE Capabilities IE, per Nss x BW x MCS + * The IE is organized in the following way: + * Support for Nss x BW (or RU) matrix: + * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz) + * Each entry contains 2 QAM thresholds for 8us and 16us: + * 0=BPSK, 1=QPSK, 2=16QAM, 3=64QAM, 4=256QAM, 5=1024QAM, 6=RES, 7=NONE + * i.e. QAM_th1 < QAM_th2 such if TX uses QAM_tx: + * QAM_tx < QAM_th1 --> PPE=0us + * QAM_th1 <= QAM_tx < QAM_th2 --> PPE=8us + * QAM_th2 <= QAM_tx --> PPE=16us + * @pkt_ext_qam_th: QAM thresholds + * For each Nss/Bw define 2 QAM thrsholds (0..5) + * For rates below the low_th, no need for PPE + * For rates between low_th and high_th, need 8us PPE + * For rates equal or higher then the high_th, need 16us PPE + * Nss (0-siso, 1-mimo2) x BW (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz) x + * (0-low_th, 1-high_th) + */ + u8 pkt_ext_qam_th[WRS_SS_MAX][CHNL_BW_MAX][QAM_THR_MAX]; + + /* If PPE Thresholds exist, parse them into a FW-familiar format. */ + u8 nss = (sta->he_cap.ppe_thres[0] & IEEE80211_PPE_THRES_NSS_MASK) + 1; + u8 ru_index_bitmap = u32_get_bits(sta->he_cap.ppe_thres[0], + IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK); + u8 *ppe = &sta->he_cap.ppe_thres[0]; + u8 ppe_pos_bit = 7; /* Starting after PPE header */ + u8 bw, ss, mcs, constellation; + + if (nss > WRS_SS_MAX) + nss = WRS_SS_MAX; + + for (ss = 0; ss < nss; ss++) { + u8 ru_index_tmp = ru_index_bitmap << 1; + + for (bw = 0; bw <= cl_hw->bw; bw++) { + ru_index_tmp >>= 1; + if (!(ru_index_tmp & 1)) + continue; + + pkt_ext_qam_th[ss][bw][QAM_THR_2] = get_ppe_val(ppe, ppe_pos_bit); + ppe_pos_bit += IEEE80211_PPE_THRES_INFO_PPET_SIZE; + pkt_ext_qam_th[ss][bw][QAM_THR_1] = get_ppe_val(ppe, ppe_pos_bit); + ppe_pos_bit += IEEE80211_PPE_THRES_INFO_PPET_SIZE; + } + } + + /* Reset PE duration before filling it */ + memset(pe_dur, 0, CHNL_BW_MAX * WRS_MCS_MAX_HE); + + for (ss = 0; ss < nss; ss++) { + for (bw = 0; bw <= cl_hw->bw; bw++) { + for (mcs = 0; mcs < WRS_MCS_MAX_HE; mcs++) { + constellation = mcs_to_constellation[mcs]; + + if (constellation < pkt_ext_qam_th[ss][bw][QAM_THR_1]) + pe_dur[bw][mcs] |= (PPE_0US << (ss * 2)); + else if (constellation < pkt_ext_qam_th[ss][bw][QAM_THR_2]) + pe_dur[bw][mcs] |= (PPE_8US << (ss * 2)); + else + pe_dur[bw][mcs] |= (PPE_16US << (ss * 2)); + } + } + } +} From patchwork Thu Jun 17 15:58:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71FB1C49EA2 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/cca.c | 518 +++++++++++++++++++++++++ 1 file changed, 518 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/cca.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/cca.c b/drivers/net/wireless/celeno/cl8k/cca.c new file mode 100644 index 000000000000..70f1d54b771b --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/cca.c @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "cca.h" +#include "reg/reg_mac_hw.h" +#include "reg/reg_riu.h" +#include "band.h" +#include "hw.h" + +#define TO_PERCENT(val, interval) (100 * (val) / (interval)) +#define SET_CCA_OPT(en, a, b) ((en) ? ((a) |= (b)) : ((a) &= ~(b))) +#define MDM_AFTER_L_SIG 0x3F0 +#define MDM_BEFORE_L_SIG 0x3F8 +#define SAMPLE_RES 5 + +static void cl_cca_print_cs(struct cl_hw *cl_hw, unsigned long time) +{ + u8 cca_cs = TO_PERCENT(riu_cca_cnt_cs_get(cl_hw), time); + + pr_debug("cca_cs = %u%%\n", cca_cs); +} + +static void cl_cca_print_mdm_state(struct cl_hw *cl_hw, unsigned long time) +{ + u32 cca_mdm_state_p = TO_PERCENT(riu_cca_cnt_modem_state_p_get(cl_hw), time); + u32 cca_mdm_state_20s = TO_PERCENT(riu_cca_cnt_modem_state_20_s_get(cl_hw), time); + u32 cca_mdm_state_40s = TO_PERCENT(riu_cca_cnt_modem_state_40_s_get(cl_hw), time); + u32 cca_mdm_state_80s = TO_PERCENT(riu_cca_cnt_modem_state_80_s_get(cl_hw), time); + + pr_debug("cca_mdm_state: primary = %u%%, sec20 = %u%%, sec40 = %u%%, sec80 = %u%%\n", + cca_mdm_state_p, cca_mdm_state_20s, cca_mdm_state_40s, cca_mdm_state_80s); +} + +static void cl_cca_print_mp(struct cl_hw *cl_hw, unsigned long time) +{ + u32 cca_mp_20p = TO_PERCENT(riu_cca_cnt_gi_20_p_get(cl_hw), time); + u32 cca_mp_20s = TO_PERCENT(riu_cca_cnt_gi_20_s_get(cl_hw), time); + u32 cca_mp_40s = TO_PERCENT(riu_cca_cnt_gi_40_s_get(cl_hw), time); + u32 cca_mp_80s = TO_PERCENT(riu_cca_cnt_gi_80_s_get(cl_hw), time); + + pr_debug("cca_mp: primary = %u%%, sec20 = %u%%, sec40 = %u, sec80 = %u%%\n", + cca_mp_20p, cca_mp_20s, cca_mp_40s, cca_mp_80s); +} + +static void cl_cca_print_energy(struct cl_hw *cl_hw, unsigned long time) +{ + u32 cca_energy_thr_p = TO_PERCENT(riu_cca_cnt_energy_thr_p_get(cl_hw), time); + u32 cca_energy_thr_20s = TO_PERCENT(riu_cca_cnt_energy_thr_20_s_get(cl_hw), time); + u32 cca_energy_thr_40s = TO_PERCENT(riu_cca_cnt_energy_thr_40_s_get(cl_hw), time); + u32 cca_energy_thr_80s = TO_PERCENT(riu_cca_cnt_energy_thr_80_s_get(cl_hw), time); + + pr_debug("cca_energy_thr: primary = %u%%, sec20 = %u%%, sec40 = (%u%%), sec80 = %u%%\n", + cca_energy_thr_p, cca_energy_thr_20s, cca_energy_thr_40s, cca_energy_thr_80s); +} + +static void cl_cca_print_energy_band(struct cl_hw *cl_hw, unsigned long time) +{ + u32 cca_energy_20_band0 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_0_get(cl_hw), time); + u32 cca_energy_20_band1 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_1_get(cl_hw), time); + u32 cca_energy_20_band2 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_2_get(cl_hw), time); + u32 cca_energy_20_band3 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_3_get(cl_hw), time); + u32 cca_energy_20_band4 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_4_get(cl_hw), time); + u32 cca_energy_20_band5 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_5_get(cl_hw), time); + u32 cca_energy_20_band6 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_6_get(cl_hw), time); + u32 cca_energy_20_band7 = TO_PERCENT(riu_cca_cnt_energy_thr_20_band_7_get(cl_hw), time); + + pr_debug("cca_energy_20: band0 = %u%%, band1 = %u%%, band2 = %u%%, band3 = %u%%, " + "band4 = %u%%, band5 = %u%%, band6 = %u%%, band7 = %u%%\n", + cca_energy_20_band0, cca_energy_20_band1, cca_energy_20_band2, + cca_energy_20_band3, cca_energy_20_band4, cca_energy_20_band5, + cca_energy_20_band6, cca_energy_20_band7); +} + +static void cl_cca_update_counters(u16 *hist, u32 counter) +{ + if (counter == 0) + hist[0]++; + else if (counter > 100) + hist[CCA_MAX_SAMPLE - 1]++; + else + hist[((counter - 1) / SAMPLE_RES) + 1]++; +} + +static void cl_cca_print_utility(struct cl_hw *cl_hw, unsigned long time) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + struct cl_edca_hist_db *hist_db = &cca_db->edca_hist; + u32 cca_cs = riu_cca_cnt_cs_get(cl_hw); + u32 edca_busy = mac_hw_edca_cca_busy_get(cl_hw); + u32 cca_mdm_state_p = riu_cca_cnt_modem_state_p_get(cl_hw); + u32 tx_mine = mac_hw_tx_mine_busy_get(cl_hw); + u32 rx_mine = mac_hw_rx_mine_busy_get(cl_hw); + u32 sample_cnt = hist_db->sample_cnt; + u32 edca_busy_diff = edca_busy - cca_db->edca_busy; + u32 tx_mine_diff = tx_mine - cca_db->tx_mine; + u32 rx_mine_diff = rx_mine - cca_db->rx_mine; + + /* Cca utility formulas */ + u32 air_util = cca_cs + tx_mine_diff; + u32 wifi_air_util = cca_mdm_state_p + tx_mine_diff; + u32 not_mine_rx_wifi = cca_mdm_state_p - rx_mine_diff; + u32 mine_util = tx_mine_diff + rx_mine_diff; + u32 non_wifi_util = edca_busy_diff - cca_mdm_state_p; + u32 not_mine_util = edca_busy_diff - rx_mine_diff; + u32 not_mine_time = time - mine_util; + + u32 air_util_percent = TO_PERCENT(air_util, time); + u32 wifi_air_util_percent = TO_PERCENT(wifi_air_util, time); + u32 not_mine_rx_wifi_percent = TO_PERCENT(not_mine_rx_wifi, time); + u32 mine_util_percent = TO_PERCENT(mine_util, time); + u32 non_wifi_util_percent = TO_PERCENT(non_wifi_util, time); + u32 not_mine_util_percent = TO_PERCENT(not_mine_util, time); + u32 not_mine_busy_util_percent = + (not_mine_time > 0) ? TO_PERCENT(not_mine_util, not_mine_time) : 0; + + cca_db->edca_busy = edca_busy; + cca_db->tx_mine = tx_mine; + cca_db->rx_mine = rx_mine; + + if (sample_cnt > 0) { + cl_cca_update_counters(hist_db->air_util, air_util_percent); + cl_cca_update_counters(hist_db->wifi_air_util, wifi_air_util_percent); + cl_cca_update_counters(hist_db->not_mine_rx_wifi, not_mine_rx_wifi_percent); + cl_cca_update_counters(hist_db->mine, mine_util_percent); + cl_cca_update_counters(hist_db->non_wifi_util, non_wifi_util_percent); + cl_cca_update_counters(hist_db->not_mine, not_mine_util_percent); + cl_cca_update_counters(hist_db->not_mine_busy, not_mine_busy_util_percent); + + hist_db->sample_cnt--; + + /* Stop sampling */ + if (hist_db->sample_cnt == 0) { + SET_CCA_OPT(0, cca_db->cca_opt, CCA_OPT_REC_HIST); + pr_debug("Record is done\n"); + } + } + + if (cca_db->cca_opt & CCA_OPT_UTIL) + pr_debug("air_util = %u%%, wifi_air_util = %u%%, not_mine_rx_wifi = %u%%, " + "mine_util = %u%%, non_wifi_util = %u%%, not_mine_util = %u%%, " + "not_mine_busy_util = %u%%\n", + air_util_percent, wifi_air_util_percent, not_mine_rx_wifi, + mine_util_percent, non_wifi_util_percent, not_mine_util_percent, + not_mine_busy_util_percent); +} + +static void cl_cca_print_tx_rx_mine(struct cl_hw *cl_hw, unsigned long time) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + + u32 tx_mine = mac_hw_tx_mine_busy_get(cl_hw); + u32 rx_mine = mac_hw_rx_mine_busy_get(cl_hw); + + u32 diff_tx_mine = tx_mine - cca_db->print_tx_mine; + u32 diff_rx_mine = rx_mine - cca_db->print_rx_mine; + + cca_db->print_tx_mine = tx_mine; + cca_db->print_rx_mine = rx_mine; + + pr_debug("tx_mine = %u (%lu%%), rx_mine = %u (%lu%%)\n", + diff_tx_mine, + TO_PERCENT(diff_tx_mine, time), + diff_rx_mine, + TO_PERCENT(diff_rx_mine, time)); +} + +static void cl_cca_edca(struct cl_hw *cl_hw, unsigned long time) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + bool is_24g = cl_band_is_24g(cl_hw); + bool sec80 = !is_24g; + + u32 new_edca_busy = mac_hw_edca_cca_busy_get(cl_hw); + u32 new_edca_busy_sec20 = mac_hw_add_cca_busy_sec_20_get(cl_hw); + u32 new_edca_busy_sec40 = is_24g ? 0 : mac_hw_add_cca_busy_sec_40_get(cl_hw); + u32 new_edca_busy_sec80 = sec80 ? mac_hw_add_cca_busy_sec_80_get(cl_hw) : 0; + + u32 diff_edca_busy = new_edca_busy - cca_db->edca_busy; + u32 diff_edca_busy_sec20 = new_edca_busy_sec20 - cca_db->edca_busy_sec20; + u32 diff_edca_busy_sec40 = new_edca_busy_sec40 - cca_db->edca_busy_sec40; + u32 diff_edca_busy_sec80 = new_edca_busy_sec80 - cca_db->edca_busy_sec80; + + u32 percent_edca_busy = TO_PERCENT(diff_edca_busy, time); + u32 percent_edca_busy_sec20 = TO_PERCENT(diff_edca_busy_sec20, time); + u32 percent_edca_busy_sec40 = TO_PERCENT(diff_edca_busy_sec40, time); + u32 percent_edca_busy_sec80 = TO_PERCENT(diff_edca_busy_sec80, time); + + cca_db->edca_busy = new_edca_busy; + cca_db->edca_busy_sec20 = new_edca_busy_sec20; + cca_db->edca_busy_sec40 = new_edca_busy_sec40; + cca_db->edca_busy_sec80 = new_edca_busy_sec80; + + pr_debug("edca_busy: primary = %u (%u%%), sec20 = %u (%u%%), " + "sec40 = %u (%u%%), sec80 = %u (%u%%)\n", + diff_edca_busy, percent_edca_busy, + diff_edca_busy_sec20, percent_edca_busy_sec20, + diff_edca_busy_sec40, percent_edca_busy_sec40, + diff_edca_busy_sec80, percent_edca_busy_sec80); +} + +static void cl_cca_print_edca_nav(struct cl_hw *cl_hw, unsigned long time) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + + u32 new_cca_busy_nav = mac_hw_edca_nav_busy_get(cl_hw); + u32 new_cca_intra_bss_nav = mac_hw_intra_bss_nav_busy_get(cl_hw); + u32 new_cca_inter_bss_nav = mac_hw_inter_bss_nav_busy_get(cl_hw); + + u32 diff_cca_busy_nav = new_cca_busy_nav - cca_db->cca_busy_nav; + u32 diff_cca_intra_bss_nav = new_cca_intra_bss_nav - cca_db->cca_intra_bss_nav; + u32 diff_cca_inter_bss_nav = new_cca_inter_bss_nav - cca_db->cca_inter_bss_nav; + + u32 percent_cca_busy_nav = TO_PERCENT(diff_cca_busy_nav, time); + u32 percent_cca_intra_bss_nav = TO_PERCENT(diff_cca_intra_bss_nav, time); + u32 percent_cca_inter_bss_nav = TO_PERCENT(diff_cca_inter_bss_nav, time); + + cca_db->cca_busy_nav = new_cca_busy_nav; + cca_db->cca_intra_bss_nav = new_cca_intra_bss_nav; + cca_db->cca_inter_bss_nav = new_cca_inter_bss_nav; + + pr_debug("cca_busy_nav = %u%%, cca_intra_bass_nav = %u%%, cca_inter_bass_nav = %u%%\n", + percent_cca_busy_nav, percent_cca_intra_bss_nav, percent_cca_inter_bss_nav); +} + +static int cl_cca_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "cca usage:\n" + "-a : Print TX mine and RX mine [0-dis, 1-en]\n" + "-b : Print energy detect registers per20 [0-dis, 1-en]\n" + "-c : Print EDCA registers [0-dis, 1-en]\n" + "-d : Enable/Disable CCA statistics - [0-dis, 0xff-en all]\n" + "-e : Print energy detect registers [0-dis, 1-en]\n" + "-g : Print mid-packet registers [0-dis, 1-en]\n" + "-h : Print histogram [0-reset, 1-print]\n" + "-i : Print NAV busy registers [0-dis, 1-en]\n" + "-m : Print modem-state registers [0-dis, 1-en]\n" + "-n : Set modem-state registers [0-before L-SIG, 1-after L-SIG]\n" + "-r : Record histogram [samples #]\n" + "-s : Print carrier-sense register [0-dis, 1-en]\n" + "-u : Print CCA utility [0-dis, 1-en]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static bool cl_cca_is_hist_empty(struct cl_edca_hist_db *hist_db, u8 cnt) +{ + if (!hist_db->air_util[cnt] && + !hist_db->mine[cnt] && + !hist_db->non_wifi_util[cnt] && + !hist_db->not_mine[cnt] && + !hist_db->not_mine_busy[cnt] && + !hist_db->not_mine_rx_wifi[cnt] && + !hist_db->wifi_air_util[cnt]) + return true; + + return false; +} + +static void cl_cca_print_histogram(struct cl_hw *cl_hw) +{ + struct cl_edca_hist_db *hist_db = &cl_hw->cca_db.edca_hist; + u8 i = 0; + u8 range = 1; + + pr_debug("|---------------------------------------------------------------|\n"); + pr_debug("|Samples|AirUtil|WifiAir|NonWifi|Mine |NotMine|NotMine|NotMine|\n"); + pr_debug("| | |Util |Util | | |Busy |RxWifi |\n"); + pr_debug("|-------+-------+-------+-------+-------+-------+-------+-------|\n"); + + for (i = 0; i < CCA_MAX_SAMPLE; i++) { + if (cl_cca_is_hist_empty(hist_db, i)) + continue; + + if (i > 1) + range = ((i - 1) * SAMPLE_RES) + 1; + + if (i != 0) + pr_debug("|%3u-%-3u| %5u | %5u | %5u | %5u | %5u | %5u | %5u |\n", + range, range + SAMPLE_RES - 1, hist_db->air_util[i], + hist_db->wifi_air_util[i], hist_db->non_wifi_util[i], + hist_db->mine[i], hist_db->not_mine[i], + hist_db->not_mine_busy[i], hist_db->not_mine_rx_wifi[i]); + else + pr_debug("|0 | %5u | %5u | %5u | %5u | %5u | %5u | %5u |\n", + hist_db->air_util[i], hist_db->wifi_air_util[i], + hist_db->non_wifi_util[i], hist_db->mine[i], + hist_db->not_mine[i], hist_db->not_mine_busy[i], + hist_db->not_mine_rx_wifi[i]); + } + + pr_debug("|---------------------------------------------------------------|\n"); +} + +static void cl_cca_opt_update(struct cl_hw *cl_hw, u32 cca_opt_prev) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + u32 cca_opt_new = cca_db->cca_opt; + + if (cca_opt_prev == 0 && cca_opt_new != 0) { + cca_db->time = jiffies_to_usecs(jiffies); + riu_rwnxagccca_1_cca_cnt_clear_setf(cl_hw, 0); + } + + if (((cca_opt_prev & CCA_OPT_TX_RX_MINE) != CCA_OPT_TX_RX_MINE) && + (cca_opt_new & CCA_OPT_TX_RX_MINE)) { + cca_db->print_tx_mine = mac_hw_tx_mine_busy_get(cl_hw); + cca_db->print_rx_mine = mac_hw_rx_mine_busy_get(cl_hw); + } + + if (((cca_opt_prev & CCA_OPT_UTIL) != CCA_OPT_UTIL) && + (cca_opt_new & CCA_OPT_UTIL)) { + cca_db->tx_mine = mac_hw_tx_mine_busy_get(cl_hw); + cca_db->rx_mine = mac_hw_rx_mine_busy_get(cl_hw); + cca_db->edca_busy = mac_hw_edca_cca_busy_get(cl_hw); + } +} + +int cl_cca_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + u32 cca_opt_prev = cca_db->cca_opt; + u32 expected_params = -1; + u32 param = (u32)cli_params->params[0]; + bool print_tx_rx_mine = false; + bool print_energy_band = false; + bool print_edca = false; + bool print_all = false; + bool print_energy = false; + bool print_mp = false; + bool print_histogram = false; + bool print_nav_edca = false; + bool print_mdm = false; + bool set_mdm = false; + bool record_histogram = false; + bool print_cs = false; + bool print_util = false; + + switch (cli_params->option) { + case 'a': + print_tx_rx_mine = true; + expected_params = 1; + break; + case 'b': + print_energy_band = true; + expected_params = 1; + break; + case 'c': + print_edca = true; + expected_params = 1; + break; + case 'd': + print_all = true; + expected_params = 1; + break; + case 'e': + print_energy = true; + expected_params = 1; + break; + case 'g': + print_mp = true; + expected_params = 1; + break; + case 'h': + print_histogram = true; + expected_params = 1; + break; + case 'i': + print_nav_edca = true; + expected_params = 1; + break; + case 'm': + print_mdm = true; + expected_params = 1; + break; + case 'n': + set_mdm = true; + expected_params = 1; + break; + case 'r': + record_histogram = true; + expected_params = 1; + break; + case 's': + print_cs = true; + expected_params = 1; + break; + case 'u': + print_util = true; + expected_params = 1; + break; + case '?': + return cl_cca_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (print_tx_rx_mine) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_TX_RX_MINE); + + if (print_energy_band) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_CNT_ENERGY_BAND); + + if (print_all) + cca_db->cca_opt = param; + + if (print_edca) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_EDCA); + + if (print_energy) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_CNT_ENERGY); + + if (print_mp) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_CNT_MP); + + if (print_histogram) { + if (param) + cl_cca_print_histogram(cl_hw); + else + memset(&cca_db->edca_hist, 0, sizeof(struct cl_edca_hist_db)); + + return 0; + } + + if (print_nav_edca) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_EDCA_NAV); + + if (print_mdm) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_CNT_MDM_STATE); + + if (set_mdm) { + u16 psel = param ? MDM_AFTER_L_SIG : MDM_BEFORE_L_SIG; + + pr_debug("Modem state register set to : %s L-SIG detection!\n", + param ? "after" : "before"); + riu_rwnxagcccastate_0_rxstatecca_20_psel_setf(cl_hw, psel); + + return 0; + } + + if (record_histogram) { + pr_debug("%s recording samples\n", param ? "Start" : "Stop"); + cca_db->edca_hist.sample_cnt = param; + SET_CCA_OPT(!!param, cca_db->cca_opt, CCA_OPT_REC_HIST); + } + + if (print_cs) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_CNT_CS); + + if (print_util) + SET_CCA_OPT(param, cca_db->cca_opt, CCA_OPT_UTIL); + + cl_cca_opt_update(cl_hw, cca_opt_prev); + return 0; + +out_err: + return -EIO; +} + +void cl_cca_maintenance(struct cl_hw *cl_hw) +{ + struct cl_cca_db *cca_db = &cl_hw->cca_db; + unsigned long time = jiffies_to_usecs(jiffies); + unsigned long diff_time = time - cca_db->time; + u32 cca_opt = cca_db->cca_opt; + + cca_db->time = time; + + if (!diff_time || !cca_opt) + return; + + if (cca_opt & CCA_OPT_CNT_CS) + cl_cca_print_cs(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_CNT_MDM_STATE) + cl_cca_print_mdm_state(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_CNT_MP) + cl_cca_print_mp(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_CNT_ENERGY) + cl_cca_print_energy(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_CNT_ENERGY_BAND) + cl_cca_print_energy_band(cl_hw, diff_time); + + if (cca_opt & (CCA_OPT_UTIL | CCA_OPT_REC_HIST)) + cl_cca_print_utility(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_TX_RX_MINE) + cl_cca_print_tx_rx_mine(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_EDCA) + cl_cca_edca(cl_hw, diff_time); + + if (cca_opt & CCA_OPT_EDCA_NAV) + cl_cca_print_edca_nav(cl_hw, diff_time); + + /* Rest CCA counters */ + riu_rwnxagccca_1_cca_cnt_clear_setf(cl_hw, 0); +} + From patchwork Thu Jun 17 15:58:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7592DC2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 037/256] cl8k: add chandef.h Date: Thu, 17 Jun 2021 15:58:44 +0000 Message-Id: <20210617160223.160998-38-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:14 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5150c747-026c-42db-f7ce-08d931a96a1f X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g2JJxOydRMPzeOMY2ZPpGRr0WSedpSo8YYnRGGBd25tH6vsIBjsAq1vlfWG72jbpZp29Bg3Jz2DIyxi7827Qh9C0vEc/6tTm/EoDqOX0HrCfsmRurdtNncYKDMG9UOJy5Rjs1+hWqvs9ajFoBvzuY6kFJR7Yi/Oin4bp5eu0VRin11vQdXikPLZlzNffJwh6/FlZ8v0R4D4AZ1sE68WtpqtciQsZHrDD91BYRU0OMadL9zP5fh5tkVBzrYbtGEzc2drxHnXYxikUvcS0ym8iKGxk9rPwex5dv1SMg8Ibdv47aCTSexmbITLlgs6S8cIRI9RdI2ypwP7HYEftrPYv8QSUwuwQk7oaxGlsc6Buxgae37U2+9uSO5e4a76e6d9xYHnwqp3i3INBTEXNRu1mEsQ/zyJDrQrPZvQIZ9OPpQFbBxnvq/coA0nEl4arVPi4KMaOpDSJe+z3J5PF3SOGxO7hbpIJbitD3gFMbIJh+jkCDkXZJkDUzyF+a+NTxySw2evQBlNr6Y3bEaab4FurAZePLZ72N2KBBFMqF90Vt3ANdF3bZWDwuDsm9eEkRjUZu6v7OoT8bQw1MJBwbC+fZG20TRJcRhCXY6lw9x0qFvIGmSRxu+7OTTCNc9/1PEJerqe/iCgTOJhv/cS+UdwM9Zlzuhr5u9Va43za/ZJYkgx86IX5WGc+FPKROQB7o0etrHp1P53G3pz6qExgCN6H6w== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ea2Hum377YXihS0Dj8hXEqioFooaCty9divkzXnwDOWok+H/2eoCv9oX4H7MGC76qtAoEUQYqBKKTKSWGr4Js6x9iq6A1lCINhcP+81luVamrH68P4Fzc42MBLjDqEkZiMx+/NeKBzC/SDGU8BgCmSoFNSwbxW2pMHminRBekyo7kzvNDhZFEKeGA13Vd378+tViY+O0kDIoDrL/LuxGhZhh84YVXqqXs3e3Q/gIoJPnKOjkWnZGqyPxMEBhFL1MwE0cr6AAF5GCGmZqhijy9GjieIk2VIkmFpZZbFrKj+cLUwvhnOBUpKpwq4sIRDq90dtW6Berl6gyqSEU4VWEtbnPWLQ5ZIO6eyXX2QMbXntKAeIqkW0/JpUVRH2zrDOBUPuZg8QRgTVqtgmzcuOpdGp4p79RywhDs7TeknxFjD7KKbT20LeHBinzcFsZQUhir7P6cA4BECXzguPYf1uUlpn8vPlPcacOk+5PHfCHHGinN53lPpZv8cNlUi8cG6lrZQOdl5D4o/zEjlKFEOu1agjAPiU1PAlje1BpXIq/0xT4V4hp+S8awUhrROlKIleE6SJcZfURo5+xc6x01cq/GkX8OlWHPjZdrDYtDOdl6ex9VPYEWUYolHaE5e+TOabp1SYZX+KUKsy1bH7COxBEapUWH5Nt7l2y2Wko3K+77s9daPhKz60j5JGhuGinee5OQVI9HP+XisU3ZXep4qheWlfTgO9rABJMWB2uTWbPtKaXD+0agoqRlR7fKrICV6yTaV7uRzYWUodvWZY92gsua1v+YirLBz18d29KoqhZbOoTeJKtdZjhU5+HEFiVhed2R+aLO4qTCrYNskT68evempYzfBQxBtQWWlhkcVmvJAUpEaiLuOtEdje9es6jnj3Qi19BY5bNtRc/b6O9GnVyp6EKy/SBWMDveeJ3VtilDOyTPX35xiBFOZVlPddIuiH4M7bnk7Uvzmf5Fb5eT0eh4rqlaNWMD+glPzx77dnYzlxQwZCQu92/6LtBgCYAtd/T0b2+87dLkn2CcGUY+pwYKhVOdiChW9bPraxL1C63qkcsslzZJUaskk2OhDcHwIlFKAkwNugVxmvoF/rUbkgyfU8RW9MFfq6BBs/S9UMQOasYrp1eumwEn6bF1dxRNqU8W0OOPhmOwLg1QWXfgBB53V+daP+32dbVyCukC2RBsGIo84CyScK2Pg3seL0jWSXYDaJgBwo5dx8I5hUcRTQT4+w2Amf58X6cG0AgNY57m/2wXQHtq53Fgo9rNwuDdNRV1r7lcZvRrKJF0cYphuhuQbWVwA8qnc7vIfHbcawJOc4h2+sjv8Nni6t8UVx2F6FG X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5150c747-026c-42db-f7ce-08d931a96a1f X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:15.0932 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cDttx+5bfO1qyJA7mm2eY4OFqf7bhuy11S2+itw22E+k6/q6DqGVJLrQiXwIF+rsePaHCPgoLcKmKF0Gv1MCNg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/chandef.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/chandef.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/chandef.h b/drivers/net/wireless/celeno/cl8k/chandef.h new file mode 100644 index 000000000000..414e5c76f09f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/chandef.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_CHANDEF_H +#define CL_CHANDEF_H + +#include "hw.h" + +int cl_chandef_calc(struct cl_hw *cl_hw, u32 channel, u32 bw, + enum nl80211_chan_width *width, u32 *primary, u32 *center); +int cl_chandef_get_default(struct cl_hw *cl_hw, enum nl80211_chan_width *width, + u32 *primary, u32 *center); + +#endif /* CL_CHANDEF_H */ From patchwork Thu Jun 17 15:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54F5FC2B9F4 for ; Thu, 17 Jun 2021 16:03:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3BAB9613A9 for ; Thu, 17 Jun 2021 16:03:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233640AbhFQQF5 (ORCPT ); Thu, 17 Jun 2021 12:05:57 -0400 Received: from mail-eopbgr80052.outbound.protection.outlook.com ([40.107.8.52]:15895 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233612AbhFQQFt (ORCPT ); Thu, 17 Jun 2021 12:05:49 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DE3HfU3qnbfAPPKQC4SQLKJ5ICpn1iCSDh1xt8OD18Eyi0eY06oznIjid/ri2qB06XhBxffnD0Fp3e8RC7/Qlo3xsgCZmBt2fxuU19tqJrMQ7znTA3GGKtvfFJydpyNSp6C7ZuJ+zKOHfJ7Is9XfI79hh8CZltlkKL9Au6gd1hWg0kXSTvUCOlCXF1y15n8pZs/YPbLqQNQacypsW5+amg1Zd0UOFahiX7Nyubvswep7uOaMdE9QTP5H8UCreKASkCYbmdndB5jOT7WrH2SUSpDK817RMkbQTTyXO1HzbF7AN7qRtM5SmF/vgDoY+glsAH9ZCrtX0SYj/pCx6gMu2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ReQanTgEXuRxzelIJk0KTx50AVXqAMRyWugjXCwn+uk=; b=ZfwarfcIGSC+K9hWG0EO7O863/XxWv7DUhvZkZgrzcS2JZyWJXEGkODPOECYTj2iFCk3y1RTRhJLXsUm0PhlDrgiVTQIhyJIDd871OOc7EwoS1FdIdcmj0Mse6M0HS2flvywuqqUcMMDv+k7b+Lyk6oAmd1PfwsPZisZlJmCyV6IKNUmhC0iykHCImsvl7FDaLEcSaNcisuC28oJGhU2oFPWxP6BgNSkRUFW4fDgRnXJa1W+jS+1EOs34JBYETg+h1Y07rwtD3+2je6/sNqoOUURUXS1FUdDOxtkbn6nYi8uJ9pjCegdTBQAqeC9dgHOLiVongZLoLn8odf/lo7IxA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ReQanTgEXuRxzelIJk0KTx50AVXqAMRyWugjXCwn+uk=; b=kIASny7ohn8dSyFuohvBy5MrYjjo4RvEVZhnN88ixbecipxjeSRJFka0jlPd0nrolEnK1oBdAHnZY3Q0Z8ThFZH59Ptopz8PE2eFOUPjayg+uqC/XR6qd23Jx73i8W+4h1K9v0ud7cu4hhd/WnBWwHZmlT4CRGSKADSxRHY/aJ8= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0966.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1ce::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.25; Thu, 17 Jun 2021 16:03:40 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:03:40 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 038/256] cl8k: add channel.c Date: Thu, 17 Jun 2021 15:58:45 +0000 Message-Id: <20210617160223.160998-39-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:15 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2eebb8a3-c120-4005-f0bc-08d931a96abf X-MS-TrafficTypeDiagnostic: AM9P192MB0966: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: j+XbNkP4ObsE9USE9bf+wvIg2Zr8h1wnBl7NJ9bDW5QTCo32GJ11tux+rQhf9flrW+HoqsCMhzOjMuXKjL2F055NZa06KBKfLgioN9rzFHCHD3HDYj7XOE+hDuOssxknsmLK9Y1u9cUVhp7EEzvgAbSYFtBQ+fSaJmv66Fh4ffiVXlRJ7RVKsNityEt2SrehZFmdonqKrYHHf1pvL4GPJoWP0Yiok6UzKcB4Yxrn9ARLMCzCmmW5NKVYWPnbBGwrsgMKhO2c468FeaUEfi/5hl/7NqgsUjS5IcN0xsinHBL9v5ejiA+VGTuOdS9zK/kgQBBehqV3RQ7/9UZQwvLQmfcYhCbsq1uvhdUNobcoIUIIMOwl6NmXPYLd3q7QIIf5WJDQNIZozcqzzwU1forqRyoKdq8mkeezP5rmS84ob3rHLifSMOPYn9+Mv8PXbeYcL2YDInqEL5/DeDD9TKMqB3tWS6PmtHTy9QlSMCDlmRwsXBA3eYLe+HxSwbgyfC2iRe2LZ3AaIJYZV4tgQ4p4DhIvcuXraXJXA1g7npgDDKTzOb8O1hDrYEn8ecn/CPQ28KI8kLKG1ZldLTF6OxmcWiQr/f5VK/QFyLa57Fb9G8MkHbPcH1k+Ls2K+dRSo1V6mxWgPxTQsxe8XCcq6QfxjmkfzBl43Vcar5QaMlBpxFzEkqjM3sqXz9akJA47X9fIzB0d/yg/spCLSgAjENJeaA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(366004)(346002)(39850400004)(376002)(396003)(30864003)(4326008)(1076003)(2616005)(8676002)(186003)(6512007)(6486002)(107886003)(83380400001)(6916009)(38100700002)(55236004)(316002)(16526019)(6506007)(38350700002)(6666004)(54906003)(8936002)(26005)(508600001)(36756003)(2906002)(9686003)(52116002)(956004)(5660300002)(66946007)(66556008)(66476007)(86362001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vWIU4rNfoP31y+Af2VVv4ss+rKKOOFtxpiJw/P5o/givQawBk9r3UkPV0poo2rPkacEC+r0/6fu+uggwMohWYRHlPgppShh22sH9tIaF/+pEQItvfgqB/zxKPmdw2eT5/SWn6EArIxqLjOfLzRfK9yGtGBvp124jA2tJi+8j3uGpLTmpSSuKgu7X6sbMfE+JISUJB7V77qDO8Xr9hheKRwNXv1y7ZFL3DvL5QT/XQ+8dPUhrJhms84XvXb20c3tTNmbpfwxAjcwdk0Z2xQVFbJpUHeOR9XFXuOCCnZK4K4Fnv/7RhKqnKO5zs43SbmMxSI8iBHn+fJ2Rt3TsbM5BF/rnDpg0UiZq1PTPcml+I6quHUDqlRQxE/2FBKXUt6Jg9pXwd/5D5c+ja5hH3VQL8dx60DHVp1OHAyiy9/j6UkWiMEGj2aEPcKJYhv8I+NY/79nhJND/T7AnXz5D+PDWszZaAACI9KngMLlspozWyeLHHqMR1mQqhFz7PVB6w0cf8Qgs+Ytc9dP9R3vVCzLIeXraDDYFRM87d+VPgyJXFxaOSjvHzCu/zbAh7vz7OUC4zoKUirOcpxG5aoR3xtk6nnnGoZSh0sV7n3upFZy2l8758qmGOMc44OKM343fQRIGgVS3vm6m2wSSeA5WKBnyzabzTPXe7YwZgL+TPrsa3Vl8aFb5H/geOHGPxQI3WI/WpdOGz6wBbiaknURCrOzaVdzC3rXyvacAdGf/WDbzjl+eFHuCQ/iMom2MwvaNdQwPNKX5zwBcswsPHMaJL5RQw1OwErleFe041b47Bk6Q9icA8cFzcXQdW7vD8f9Ru7wuDYXvECkhq1Y/AqW5c168Cch1toBhNKjNex0vDDMCJNw6/eLNqYEal4AIsLSM0/lG/KOKWTmHeD8R7D1nTYQSMVsXyqQfXuR/hvtlVqpdgLSwumA1lPEypH4zXKR1UAx3y6al6tYUBDzxtAGxTRk4JhBWDqeL3Po980q/Elt1S0SoQzrcayOXu/jLLVcat/jZfu+KUtrLdL3/ujocfnbDvWaQbAJgJO/63f5739ion6cp9Twca6dEX7PtOTVTg2D170OWXRUJ3TqurO4bv+U7RiXLIHeXqAk0LLpD5excwu/f8mZDcp8AwZAeNffsJsDyaONFyXYHr7y753Ef8diTLJHwxxWjKFcf59RQ5lxrM4i4BT3qdo/R9yP/ygLvWZ0dng7wdU6j3ZbVNw8kr4RhnyZIVfVimshqEo9NZZCvuWVVpELwT6GG7RH3SF1XN7TagAS8qLEvySgPLDyuE9+BTVKQLIda7QLK0Uq51pWVSCH9Ip4itO6jtdvTRLl0k/Va X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2eebb8a3-c120-4005-f0bc-08d931a96abf X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:16.1725 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zRWGV8PNe1IQc8NYj7ZxvgCRuA7SmW6qHSP827UcWQAx0+4+2xpIzX5dgTC9wwcaH4ChoJQrZhShKlM3MwmtZg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0966 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/channel.c | 373 +++++++++++++++++++++ 1 file changed, 373 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/channel.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/channel.c b/drivers/net/wireless/celeno/cl8k/channel.c new file mode 100644 index 000000000000..78346f04e332 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/channel.c @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "channel.h" +#include "band.h" +#include "vif.h" +#include "dfs/dfs.h" +#include "chandef.h" +#include "netlink.h" + +#define CASE_CHAN2IDX_6G(_chan) { case _chan: return (b6g_ch ## _chan); } +#define CASE_CHAN2IDX_5G(_chan) { case _chan: return (b5g_ch ## _chan); } +#define CASE_CHAN2IDX_2G(_chan) { case _chan: return (b24g_ch ## _chan); } + +#define CASE_IDX2FREQ_6G(_chan) { case (b6g_ch ## _chan): return FREQ6G(_chan); } +#define CASE_IDX2FREQ_5G(_chan) { case (b5g_ch ## _chan): return FREQ5G(_chan); } +#define CASE_IDX2FREQ_2G(_chan) { case (b24g_ch ## _chan): return FREQ2G(_chan); } + +#define INVALID_FREQ 0xffff + +static u8 cl_channel_to_index_6g(struct cl_hw *cl_hw, u32 channel) +{ + switch (channel) { + CASE_CHAN2IDX_6G(1); + CASE_CHAN2IDX_6G(2); + CASE_CHAN2IDX_6G(5); + CASE_CHAN2IDX_6G(9); + CASE_CHAN2IDX_6G(13); + CASE_CHAN2IDX_6G(17); + CASE_CHAN2IDX_6G(21); + CASE_CHAN2IDX_6G(25); + CASE_CHAN2IDX_6G(29); + CASE_CHAN2IDX_6G(33); + CASE_CHAN2IDX_6G(37); + CASE_CHAN2IDX_6G(41); + CASE_CHAN2IDX_6G(45); + CASE_CHAN2IDX_6G(49); + CASE_CHAN2IDX_6G(53); + CASE_CHAN2IDX_6G(57); + CASE_CHAN2IDX_6G(61); + CASE_CHAN2IDX_6G(65); + CASE_CHAN2IDX_6G(69); + CASE_CHAN2IDX_6G(73); + CASE_CHAN2IDX_6G(77); + CASE_CHAN2IDX_6G(81); + CASE_CHAN2IDX_6G(85); + CASE_CHAN2IDX_6G(89); + CASE_CHAN2IDX_6G(93); + CASE_CHAN2IDX_6G(97); + CASE_CHAN2IDX_6G(101); + CASE_CHAN2IDX_6G(105); + CASE_CHAN2IDX_6G(109); + CASE_CHAN2IDX_6G(113); + CASE_CHAN2IDX_6G(117); + CASE_CHAN2IDX_6G(121); + CASE_CHAN2IDX_6G(125); + CASE_CHAN2IDX_6G(129); + CASE_CHAN2IDX_6G(133); + CASE_CHAN2IDX_6G(137); + CASE_CHAN2IDX_6G(141); + CASE_CHAN2IDX_6G(145); + CASE_CHAN2IDX_6G(149); + CASE_CHAN2IDX_6G(153); + CASE_CHAN2IDX_6G(157); + CASE_CHAN2IDX_6G(161); + CASE_CHAN2IDX_6G(165); + CASE_CHAN2IDX_6G(169); + CASE_CHAN2IDX_6G(173); + CASE_CHAN2IDX_6G(177); + CASE_CHAN2IDX_6G(181); + CASE_CHAN2IDX_6G(185); + CASE_CHAN2IDX_6G(189); + CASE_CHAN2IDX_6G(193); + CASE_CHAN2IDX_6G(197); + CASE_CHAN2IDX_6G(201); + CASE_CHAN2IDX_6G(205); + CASE_CHAN2IDX_6G(209); + CASE_CHAN2IDX_6G(213); + CASE_CHAN2IDX_6G(217); + CASE_CHAN2IDX_6G(221); + CASE_CHAN2IDX_6G(225); + CASE_CHAN2IDX_6G(229); + CASE_CHAN2IDX_6G(233); + }; + + return INVALID_CHAN_IDX; +} + +static u8 cl_channel_to_index_5g(struct cl_hw *cl_hw, u32 channel) +{ + switch (channel) { + CASE_CHAN2IDX_5G(36); + CASE_CHAN2IDX_5G(38); + CASE_CHAN2IDX_5G(40); + CASE_CHAN2IDX_5G(42); + CASE_CHAN2IDX_5G(44); + CASE_CHAN2IDX_5G(46); + CASE_CHAN2IDX_5G(48); + CASE_CHAN2IDX_5G(50); + CASE_CHAN2IDX_5G(52); + CASE_CHAN2IDX_5G(54); + CASE_CHAN2IDX_5G(56); + CASE_CHAN2IDX_5G(58); + CASE_CHAN2IDX_5G(60); + CASE_CHAN2IDX_5G(62); + CASE_CHAN2IDX_5G(64); + CASE_CHAN2IDX_5G(100); + CASE_CHAN2IDX_5G(102); + CASE_CHAN2IDX_5G(104); + CASE_CHAN2IDX_5G(106); + CASE_CHAN2IDX_5G(108); + CASE_CHAN2IDX_5G(110); + CASE_CHAN2IDX_5G(112); + CASE_CHAN2IDX_5G(114); + CASE_CHAN2IDX_5G(116); + CASE_CHAN2IDX_5G(118); + CASE_CHAN2IDX_5G(120); + CASE_CHAN2IDX_5G(122); + CASE_CHAN2IDX_5G(124); + CASE_CHAN2IDX_5G(126); + CASE_CHAN2IDX_5G(128); + /* 130 - invalid */ + CASE_CHAN2IDX_5G(132); + CASE_CHAN2IDX_5G(134); + CASE_CHAN2IDX_5G(136); + CASE_CHAN2IDX_5G(138); + CASE_CHAN2IDX_5G(140); + CASE_CHAN2IDX_5G(142); + CASE_CHAN2IDX_5G(144); + CASE_CHAN2IDX_5G(149); + CASE_CHAN2IDX_5G(151); + CASE_CHAN2IDX_5G(153); + CASE_CHAN2IDX_5G(155); + CASE_CHAN2IDX_5G(157); + CASE_CHAN2IDX_5G(159); + CASE_CHAN2IDX_5G(161); + /* 163 - invalid */ + CASE_CHAN2IDX_5G(165); + }; + + return INVALID_CHAN_IDX; +} + +static u8 cl_channel_to_index_24g(struct cl_hw *cl_hw, u32 channel) +{ + switch (channel) { + CASE_CHAN2IDX_2G(1); + CASE_CHAN2IDX_2G(2); + CASE_CHAN2IDX_2G(3); + CASE_CHAN2IDX_2G(4); + CASE_CHAN2IDX_2G(5); + CASE_CHAN2IDX_2G(6); + CASE_CHAN2IDX_2G(7); + CASE_CHAN2IDX_2G(8); + CASE_CHAN2IDX_2G(9); + CASE_CHAN2IDX_2G(10); + CASE_CHAN2IDX_2G(11); + CASE_CHAN2IDX_2G(12); + CASE_CHAN2IDX_2G(13); + CASE_CHAN2IDX_2G(14); + }; + + return INVALID_CHAN_IDX; +} + +u8 cl_channel_to_index(struct cl_hw *cl_hw, u32 channel) +{ + /* Calculate index for a given channel */ + if (cl_band_is_6g(cl_hw)) + return cl_channel_to_index_6g(cl_hw, channel); + else if (cl_band_is_5g(cl_hw)) + return cl_channel_to_index_5g(cl_hw, channel); + else + return cl_channel_to_index_24g(cl_hw, channel); +} + +static u16 cl_channel_idx_to_freq_6g(struct cl_hw *cl_hw, u8 index) +{ + switch (index) { + CASE_IDX2FREQ_6G(1); + CASE_IDX2FREQ_6G(2); + CASE_IDX2FREQ_6G(5); + CASE_IDX2FREQ_6G(9); + CASE_IDX2FREQ_6G(13); + CASE_IDX2FREQ_6G(17); + CASE_IDX2FREQ_6G(21); + CASE_IDX2FREQ_6G(25); + CASE_IDX2FREQ_6G(29); + CASE_IDX2FREQ_6G(33); + CASE_IDX2FREQ_6G(37); + CASE_IDX2FREQ_6G(41); + CASE_IDX2FREQ_6G(45); + CASE_IDX2FREQ_6G(49); + CASE_IDX2FREQ_6G(53); + CASE_IDX2FREQ_6G(57); + CASE_IDX2FREQ_6G(61); + CASE_IDX2FREQ_6G(65); + CASE_IDX2FREQ_6G(69); + CASE_IDX2FREQ_6G(73); + CASE_IDX2FREQ_6G(77); + CASE_IDX2FREQ_6G(81); + CASE_IDX2FREQ_6G(85); + CASE_IDX2FREQ_6G(89); + CASE_IDX2FREQ_6G(93); + CASE_IDX2FREQ_6G(97); + CASE_IDX2FREQ_6G(101); + CASE_IDX2FREQ_6G(105); + CASE_IDX2FREQ_6G(109); + CASE_IDX2FREQ_6G(113); + CASE_IDX2FREQ_6G(117); + CASE_IDX2FREQ_6G(121); + CASE_IDX2FREQ_6G(125); + CASE_IDX2FREQ_6G(129); + CASE_IDX2FREQ_6G(133); + CASE_IDX2FREQ_6G(137); + CASE_IDX2FREQ_6G(141); + CASE_IDX2FREQ_6G(145); + CASE_IDX2FREQ_6G(149); + CASE_IDX2FREQ_6G(153); + CASE_IDX2FREQ_6G(157); + CASE_IDX2FREQ_6G(161); + CASE_IDX2FREQ_6G(165); + CASE_IDX2FREQ_6G(169); + CASE_IDX2FREQ_6G(173); + CASE_IDX2FREQ_6G(177); + CASE_IDX2FREQ_6G(181); + CASE_IDX2FREQ_6G(185); + CASE_IDX2FREQ_6G(189); + CASE_IDX2FREQ_6G(193); + CASE_IDX2FREQ_6G(197); + CASE_IDX2FREQ_6G(201); + CASE_IDX2FREQ_6G(205); + CASE_IDX2FREQ_6G(209); + CASE_IDX2FREQ_6G(213); + CASE_IDX2FREQ_6G(217); + CASE_IDX2FREQ_6G(221); + CASE_IDX2FREQ_6G(225); + CASE_IDX2FREQ_6G(229); + CASE_IDX2FREQ_6G(233); + }; + + return INVALID_FREQ; +} + +static u16 cl_channel_idx_to_freq_5g(struct cl_hw *cl_hw, u8 index) +{ + switch (index) { + CASE_IDX2FREQ_5G(36); + CASE_IDX2FREQ_5G(38); + CASE_IDX2FREQ_5G(40); + CASE_IDX2FREQ_5G(42); + CASE_IDX2FREQ_5G(44); + CASE_IDX2FREQ_5G(46); + CASE_IDX2FREQ_5G(48); + CASE_IDX2FREQ_5G(50); + CASE_IDX2FREQ_5G(52); + CASE_IDX2FREQ_5G(54); + CASE_IDX2FREQ_5G(56); + CASE_IDX2FREQ_5G(58); + CASE_IDX2FREQ_5G(60); + CASE_IDX2FREQ_5G(62); + CASE_IDX2FREQ_5G(64); + CASE_IDX2FREQ_5G(100); + CASE_IDX2FREQ_5G(102); + CASE_IDX2FREQ_5G(104); + CASE_IDX2FREQ_5G(106); + CASE_IDX2FREQ_5G(108); + CASE_IDX2FREQ_5G(110); + CASE_IDX2FREQ_5G(112); + CASE_IDX2FREQ_5G(114); + CASE_IDX2FREQ_5G(116); + CASE_IDX2FREQ_5G(118); + CASE_IDX2FREQ_5G(120); + CASE_IDX2FREQ_5G(122); + CASE_IDX2FREQ_5G(124); + CASE_IDX2FREQ_5G(126); + CASE_IDX2FREQ_5G(128); + CASE_IDX2FREQ_5G(132); + CASE_IDX2FREQ_5G(134); + CASE_IDX2FREQ_5G(136); + CASE_IDX2FREQ_5G(138); + CASE_IDX2FREQ_5G(140); + CASE_IDX2FREQ_5G(142); + CASE_IDX2FREQ_5G(144); + CASE_IDX2FREQ_5G(149); + CASE_IDX2FREQ_5G(151); + CASE_IDX2FREQ_5G(153); + CASE_IDX2FREQ_5G(155); + CASE_IDX2FREQ_5G(157); + CASE_IDX2FREQ_5G(159); + CASE_IDX2FREQ_5G(161); + CASE_IDX2FREQ_5G(165); + }; + + return INVALID_FREQ; +} + +static u16 cl_channel_idx_to_freq_24g(struct cl_hw *cl_hw, u8 index) +{ + switch (index) { + CASE_IDX2FREQ_2G(1); + CASE_IDX2FREQ_2G(2); + CASE_IDX2FREQ_2G(3); + CASE_IDX2FREQ_2G(4); + CASE_IDX2FREQ_2G(5); + CASE_IDX2FREQ_2G(6); + CASE_IDX2FREQ_2G(7); + CASE_IDX2FREQ_2G(8); + CASE_IDX2FREQ_2G(9); + CASE_IDX2FREQ_2G(10); + CASE_IDX2FREQ_2G(11); + CASE_IDX2FREQ_2G(12); + CASE_IDX2FREQ_2G(13); + CASE_IDX2FREQ_2G(14); + }; + + return INVALID_FREQ; +} + +u16 cl_channel_idx_to_freq(struct cl_hw *cl_hw, u8 index) +{ + /* Calculate frequency of a given idnex */ + if (cl_band_is_6g(cl_hw)) + return cl_channel_idx_to_freq_6g(cl_hw, index); + else if (cl_band_is_5g(cl_hw)) + return cl_channel_idx_to_freq_5g(cl_hw, index); + else + return cl_channel_idx_to_freq_24g(cl_hw, index); +} + +bool cl_channel_is_valid(struct cl_hw *cl_hw, u8 channel) +{ + if (cl_band_is_24g(cl_hw)) { + return (channel > 0 && channel <= 14); + } else if (cl_band_is_5g(cl_hw)) { + if (channel >= 36 && channel <= 64) + return ((channel & 0x1) == 0x0); + + if (channel >= 100 && channel <= 144) + return ((channel & 0x1) == 0x0); + + if (channel >= 149 && channel <= 161) + return ((channel & 0x1) == 0x1); + + if (channel == 165) + return true; + } else { + if (channel == 2) + return true; + + if (channel >= 1 && channel <= 233) + if ((channel & 0x3) == 0x1) + return true; + } + + return false; +} + +u32 cl_channel_num(struct cl_hw *cl_hw) +{ + if (cl_hw->conf->ci_band_num == 6) + return NUM_CHANNELS_6G; + + if (cl_hw->conf->ci_band_num == 5) + return NUM_CHANNELS_5G; + + return NUM_CHANNELS_24G; +} + +bool __must_check cl_channel_is_scan_active(struct cl_hw *cl_hw) +{ + return false; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 039/256] cl8k: add channel.h Date: Thu, 17 Jun 2021 15:58:46 +0000 Message-Id: <20210617160223.160998-40-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:16 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 079f2c37-778c-420a-7b78-08d931a96b5d X-MS-TrafficTypeDiagnostic: AM9P192MB0966: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Gw/Juut75SNV0sgZblh/VraCeD1eB0AXrAgzSW2YqM6ph5ceqbdCmfEkUqMruhNkWSp+SgtEDEtz4vB82f2bUbxIi5t51PSvaPyPDrryQcnFhCw3wfer0lEI5a+ixotoxjThQSJgcJe+zPUdsBqUVX9UsfKAvmBOof4T6BfB72djAmflkpx3VJnr6X9KrrctSlWX3l+gXgtYQxQ6564azly/tCdnz7lX9CIe0ZiBJ4XROgPtJ9sLKcPbjdRfZt7YmBM2jIojONHR2Wk6CDcUHe/diQr+TYnCEkfj8Psetaq97NVnEjHoHskXrf0XQpFDApFsXmWKrxU9tv7cF9sKT6UkVOqKXDyB9Byfl0mEYAkzOz+Ismc3pEZb8iFnUNQeSDhBaI+5JeAruKN8Xu5ofSP7DCJCjrlhvhiJAFZYFQ20DrWCxmXs4/g86xNrtI4OBI4lqxZtHTDJy8BlPKy4L13ZWrwu30+nSXPisfSn9XkVn8Q51w+4t0+8OvT5qPXe++wTVJUMrlpLbMtvzDsyRSamu1S5mci/qUdM2j0YOiB1fqxjBnkHM5BUcwmd/XILc5NtMC69CU1KLGRDvTe0yRvxGAM+sGjsAh5Ytr+u8dJgehEVNnyhMy1eOluWB6jeY43ythDIb9pLLA3ReMJJnjqDJ76OsmwFUBzGshtGOCud01e6dyKYC9FQ7YM3m9mWaBPtnKQwbLcilWvhSY6cBw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(366004)(346002)(39850400004)(376002)(396003)(4326008)(1076003)(2616005)(8676002)(186003)(6512007)(6486002)(107886003)(83380400001)(6916009)(38100700002)(55236004)(316002)(16526019)(6506007)(38350700002)(6666004)(54906003)(8936002)(26005)(508600001)(36756003)(2906002)(9686003)(52116002)(956004)(5660300002)(66946007)(66556008)(66476007)(86362001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bUfvF3fQvdX9Q359M14MSs3Q4UqwQvN0BzlFJ0c2po/dqzjBLSt0ROHbWfmXjVcphxL9pQsDuEA8xqv1kRy+lAetr//MsYNCRqzFsPKsuL0lI3KGywRF7QPkFdZ9D9RNgIjI2AlNovC0nzPDSRaHiCT3eJYL/J72nj7Dxm5aU0e5JuwmAPE8iv2heCfPt8MGQCGl1Q3GYOsWnR1wXzMd9Yp9SMj2Fb80WME1aQwFLIPQtcZXuZKUUYLWeiVUpvsriGwGCKg58oVJKjlP42pN/3TwWRF/slEoeq3eoEYUOaFbwdGmJW/J+AVrZUevLp2gLlygLZYruUherDAp2tZWZbVLZtDA0NmDuci00XpdTAMIPD9ONFR/PV40iZFZh4YXmic9S3jTYYdBEGDiMImo3o2KQxmrzdEyG1jJBk+a/tHMUAdBPKMGUwEc3fR9tDZWmGovOo2q6XLoV8ZzDUt5iErHxoS4jZK9/hQTqg1MWjIh9T+928/p6454rvks7bjTHxbO4lJuGlQ80qZWrPhDzdCYtGdNS5W1qb9dhbtQA+gCccp+voQpGAyZKc9FeykKDaf5Nql4ZQX6kpvuitn2+MtKSPBdKHQDnJMUh12R+vimVi/DVMsXiMPLa6BW6q3CXkaoYQv0PfJHHXXwhLf7O3u4tMgQ0HDBo9cwAVR1T80YyKY/9YpPVMNG79wu7ov2fZjqly3mIcFgDDEfkeWz2JZMfAAJNlJHH1Z1z1G9Awy26GJXAkDLw910MyiLkYfki2y34qMebDH8CgsvwKn8uWNnwLvM7Yv53yEFhha50O7A3fJ1xFpQT5hX0eSVsgHvZHDtopSJJFfKKjzmGjib1KWA87F7RU4TQmiFwiyK4FkyHucNOpr5Ui+oliPuJMzdOnexF6mIc6oQJ5QDaLGFrag/NpNnm/cTDuWdC82JK++sVsBFi4UfzVzhK7mm4LFVNHADI4Qaw6Sorpp2lVR9tw3+4MKciedI4zgPDrn+L5gKrYmstkIKPL83NoRtkBU3mEhRr1RMDO4dXS+/wdfrzGXnkzBUGEV62bi2r86s0WQ+djvbmD08AH927/iFi22xvIA7XS2lU05O60Bi8YfM5dEL2VVUB0Lu/5a1LEJnKwSx25RYqqohqQmpGXrE0mtjeMHTUY+gIhubTy9/ibSZWHrfU4nSJfj+VXOBxnSwrRSzLmZy0mRABjliyRdw7R9Ewj2FskUX11+sunoZkMkLXbQXZjIHnvw4qJKVUsKkdVVE7lvjL/U8LV2Hk7sqaWdHWDc3shdFi7t12RhJik4ZSq5l36iij84JrkL4GKTA81s/Ggxgq1IcnloyHq0kqBJm X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 079f2c37-778c-420a-7b78-08d931a96b5d X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:17.1492 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: t9njhoGB4NVelM1Q1RqU9lZPL/PJdN6UQYppzwFkL/Aio3hn+UsCfEAAUyImOKfhhTmKKefUDYlXcdkHHWnBug== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0966 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/channel.h | 187 +++++++++++++++++++++ 1 file changed, 187 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/channel.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/channel.h b/drivers/net/wireless/celeno/cl8k/channel.h new file mode 100644 index 000000000000..c31cb4f69f2a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/channel.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_CHANNEL_H +#define CL_CHANNEL_H + +#include +#include + +enum chan_idx_6g { + b6g_ch1, + b6g_ch2, + b6g_ch5, + b6g_ch9, + b6g_ch13, + b6g_ch17, + b6g_ch21, + b6g_ch25, + b6g_ch29, + b6g_ch33, + b6g_ch37, + b6g_ch41, + b6g_ch45, + b6g_ch49, + b6g_ch53, + b6g_ch57, + b6g_ch61, + b6g_ch65, + b6g_ch69, + b6g_ch73, + b6g_ch77, + b6g_ch81, + b6g_ch85, + b6g_ch89, + b6g_ch93, + b6g_ch97, + b6g_ch101, + b6g_ch105, + b6g_ch109, + b6g_ch113, + b6g_ch117, + b6g_ch121, + b6g_ch125, + b6g_ch129, + b6g_ch133, + b6g_ch137, + b6g_ch141, + b6g_ch145, + b6g_ch149, + b6g_ch153, + b6g_ch157, + b6g_ch161, + b6g_ch165, + b6g_ch169, + b6g_ch173, + b6g_ch177, + b6g_ch181, + b6g_ch185, + b6g_ch189, + b6g_ch193, + b6g_ch197, + b6g_ch201, + b6g_ch205, + b6g_ch209, + b6g_ch213, + b6g_ch217, + b6g_ch221, + b6g_ch225, + b6g_ch229, + b6g_ch233, + + NUM_CHANNELS_6G +}; + +enum chan_idx_5g { + b5g_ch36, + b5g_ch38, + b5g_ch40, + b5g_ch42, + b5g_ch44, + b5g_ch46, + b5g_ch48, + b5g_ch50, + b5g_ch52, + b5g_ch54, + b5g_ch56, + b5g_ch58, + b5g_ch60, + b5g_ch62, + b5g_ch64, + b5g_ch100, + b5g_ch102, + b5g_ch104, + b5g_ch106, + b5g_ch108, + b5g_ch110, + b5g_ch112, + b5g_ch114, + b5g_ch116, + b5g_ch118, + b5g_ch120, + b5g_ch122, + b5g_ch124, + b5g_ch126, + b5g_ch128, + b5g_ch132, + b5g_ch134, + b5g_ch136, + b5g_ch138, + b5g_ch140, + b5g_ch142, + b5g_ch144, + b5g_ch149, + b5g_ch151, + b5g_ch153, + b5g_ch155, + b5g_ch157, + b5g_ch159, + b5g_ch161, + b5g_ch165, + + NUM_CHANNELS_5G +}; + +enum chan_idx_24g { + b24g_ch1, + b24g_ch2, + b24g_ch3, + b24g_ch4, + b24g_ch5, + b24g_ch6, + b24g_ch7, + b24g_ch8, + b24g_ch9, + b24g_ch10, + b24g_ch11, + b24g_ch12, + b24g_ch13, + b24g_ch14, + + NUM_CHANNELS_24G +}; + +enum cl_ch_status { + CH_STATUS_SUCCESS, + CH_STATUS_ALREADY_ON_CHANNEL, + CH_STATUS_INVALID_PARAM = -EINVAL, + + CH_STATUS_MAX +}; + +/* 6g band has the largest list */ +#define MAX_CHANNELS NUM_CHANNELS_6G + +#define START_CHAN_IDX_6G 1 + +/* 1 ==> 5955 */ +#define FREQ6G(_chan) ((_chan) == 2 ? 5935 : 5950 + 5 * (_chan)) +/* 36 ==> 5180 */ +#define FREQ5G(_chan) (5000 + 5 * (_chan)) +/* 1 ==> 2412 */ +#define FREQ2G(_chan) ((_chan) == 14 ? 2484 : 2407 + (_chan) * 5) + +/* 6G channels - UNII-5 */ +#define START_CHAN_IDX_UNII5 1 +#define END_CHAN_IDX_UNII5 85 +/* 6G channels - UNII-6 */ +#define START_CHAN_IDX_UNII6 89 +#define END_CHAN_IDX_UNII6 109 +/* 6G channels - UNII-7 */ +#define START_CHAN_IDX_UNII7 113 +#define END_CHAN_IDX_UNII7 165 +/* 6G channels - UNII-8 */ +#define START_CHAN_IDX_UNII8 169 +#define END_CHAN_IDX_UNII8 233 + +#define INVALID_CHAN_IDX 0xff + +struct cl_hw; + +u8 cl_channel_to_index(struct cl_hw *cl_hw, u32 channel); +u16 cl_channel_idx_to_freq(struct cl_hw *cl_hw, u8 index); +bool cl_channel_is_valid(struct cl_hw *cl_hw, u8 channel); +u32 cl_channel_num(struct cl_hw *cl_hw); +bool __must_check cl_channel_is_scan_active(struct cl_hw *cl_hw); + +#endif /* CL_CHANNEL_H */ From patchwork Thu Jun 17 15:58:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0DB5C48BE5 for ; Thu, 17 Jun 2021 16:04:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B74E56120A for ; Thu, 17 Jun 2021 16:04:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233160AbhFQQGH (ORCPT ); Thu, 17 Jun 2021 12:06:07 -0400 Received: from mail-eopbgr80052.outbound.protection.outlook.com ([40.107.8.52]:15895 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233632AbhFQQFy (ORCPT ); Thu, 17 Jun 2021 12:05:54 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nudzWLh7AaVdP3lg1u5hlMwuel4Cs0bmurPKgyTLWUT1BMaIHQeNqpTHc0BPu/m2+q9PhJL0VizOVeZUJ62SYboOeKRmOtV86Kmgu3aF9Qn+0yydNzbHSMtyFAbpjZm8LiYYXhxZhfvfBhexSMqpxvtbIxb2FVRhmYAXMC1iEEH4nK6ez+9HddIS339YQevmz8SADKIQQlG73pLtzQNJIY41tgsm+fNrmoPH6+MQ8eheyYX0yLv6setgZBNxcK0xJF/1qcl4mdcIRs6LP5nFnR1DH5PvCMjOWbz5NNcpvSLXOHa296SVMwlSAONP2Uwo41mItOnYYHsXQECApV20Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c7ci08mEoxpzc9eFsgpylm42roCyy+zabf0Xk899ksU=; b=lSUtrA8KiGAngdbhlPZFB+9XmLSlgqnr0SmCWECSDGa0YTlVEEz6pnXpaGTeEKoqcMTzTS3Y56DDMprqTzaUDBoDUKQFyUXkPTid3Cw6NkM0qqlfdvaEwmy8Csh3752qVUyoPBpH4foTLKbf4HLzJ776gDBPTQgpUjjW28f5Ylbd3VQ1jtWrXjMo0LCpLKslzt8eNG33FJ1yfm22NwzpoXxW81M9/0MDWmuKnmTrmnOB+HVhj/5VQXGEuTKd4lzoYVESJtdWvx1yLpZZhU5SDnoYutV+6rsP0grx7deGof5PyLF/Q+dyjJ1v90X5h3+ZIdCRrIc4V83v+hW/6TeNiw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c7ci08mEoxpzc9eFsgpylm42roCyy+zabf0Xk899ksU=; b=pSb7FuGRENQIT+nvuGp1laKEt0eanYaWhG2B7llDKCy/eYtF8n5OvPWlgCRSou3nDl+JyQOnUtU21sbNk5pX/txZD2+nQ88CMUuaAc/2mpwdLKCLvzh2jnCZu4SjPE8SjzCXo7hVjaCgqgZ3Mw8Alc1zU00SUdMyOSrIckdCfDM= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0966.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1ce::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.25; Thu, 17 Jun 2021 16:03:41 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:03:41 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/chan_info.c | 852 +++++++++++++++++++ 1 file changed, 852 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/chan_info.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/chan_info.c b/drivers/net/wireless/celeno/cl8k/chan_info.c new file mode 100644 index 000000000000..95b09128c166 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/chan_info.c @@ -0,0 +1,852 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chan_info.h" +#include "utils/utils.h" +#include "chip.h" +#include "utils/math.h" +#include "band.h" +#include "utils/string.h" +#include "channel.h" +#include "utils/file.h" + +struct ieee80211_regdomain cl_regdom_24g = { + .n_reg_rules = 2, + .alpha2 = "99", + .reg_rules = { + REG_RULE(2412 - 10, 2472 + 10, 40, 6, 20, 0), + REG_RULE(2484 - 10, 2484 + 10, 20, 6, 20, 0), + } +}; + +struct ieee80211_regdomain cl_regdom_5g = { + .n_reg_rules = 1, + .alpha2 = "99", + .reg_rules = { + REG_RULE(5150 - 10, 5850 + 10, 80, 6, 30, 0), + } +}; + +struct ieee80211_regdomain cl_regdom_6g = { + .n_reg_rules = 1, + .alpha2 = "99", + .reg_rules = { + REG_RULE(5935 - 10, 7115 + 10, 80, 6, 30, 0), + } +}; + +static inline s32 convert_str_int_q2(s8 *str) +{ + s32 x, y; + + if (!str) + return 0; + if (sscanf(str, "%d.%2d", &x, &y) != 2) + return 0; + if (!strstr(str, ".")) + return x * 4; + if (y < 10 && (*(strstr(str, ".") + 1) != '0')) + y *= 10; + return (x * 100 + y) * 4 / 100; +} + +static int cl_parse_reg_domain(struct cl_hw *cl_hw, char **str) +{ + /* Check if current line contains "FCC" or "ETSI" */ + char *token = strsep(str, "\n"); + + if (!token) + goto err; + + if (strstr(token, "FCC")) { + cl_hw->channel_info.standard = CL_STANDARD_FCC; + cl_dbg_info(cl_hw, "Standard = FCC\n"); + return 0; + } + + if (strstr(token, "ETSI")) { + cl_hw->channel_info.standard = CL_STANDARD_ETSI; + cl_dbg_info(cl_hw, "Standard = ETSI\n"); + return 0; + } + +err: + cl_dbg_err(cl_hw, "Illegal regulatory domain\n"); + cl_hw->channel_info.standard = CL_STANDARD_NONE; + return -1; +} + +#define MAX_CC_STR 4 +#define MAX_BW_STR 8 + +static bool cl_parse_channel_info_txt(struct cl_hw *cl_hw) +{ + /* + * Example of country information in channel_info.txt: + * + * [EU (European Union)ETSI] + * 2.4GHz/20MHz: 2412(1,20) 2417(2,20) 2422(3,20) 2427(4,20) 2432(5,20) 2437(6,20) + * 2442(7,20) 2447(8,20) 2452(9,20) 2457(10,20) 2462(11,20) 2467(12,20) + * 2472(13,20) + * 2.4GHz/40MHz: 2422(1,20) 2427(2,20) 2432(3,20) 2437(4,20) 2442(5,20) 2447(6,20) + * 2452(7,20) 2457(8,20) 2462(9,20) 2467(10,20) 2472(11,20) + * 5.2GHz/20MHz: 5180(36,23) 5200(40,23) 5220(44,23) 5240(48,23) 5260(52,23) 5280(56,23) + * 5300(60,23) 5320(64,23) 5500(100,30) 5520(104,30) 5540(108,30) + * 5560(112,30)5580(116,30) 5600(120,30) 5620(124,30) 5640(128,30) + * 5660(132,30) 5680(136,30) 5700(140,30) + * 5.2GHz/40MHz: 5180(36,23) 5200(40,23) 5220(44,23) 5240(48,23) 5260(52,23) 5280(56,23) + * 5300(60,23) 5310(64,23) 5510(100,30) 5510(104,30) 5550(108,30) + * 5550(112,30) 5590(116,30) 5590(120,30) 5630(124,30) 5630(128,30) + * 5670(132,30) 5670(136,30) + * 5.2GHz/80MHz: 5180(36,23) 5200(40,23) 5220(44,23) 5240(48,23) 5260(52,23) 5280(56,23) + * 5300(60,23) 5310(64,23) 5510(100,30) 5510(104,30) 5550(108,30) + * 5550(112,30) 5590(116,30) 5590(120,30) 5630(124,30) 5630(128,30) + * 5.2GHz/160MHz: 5180(36,23) 5200(40,23) 5220(44,23) 5240(48,23) 5260(52,23) 5280(56,23) + * 5300(60,23) 5310(64,23) 5510(100,30) 5510(104,30) 5550(108,30) + * 5550(112,30) 5590(116,30) 5590(120,30) 5630(124,30) 5630(128,30) + */ + + struct cl_channel_info *channel_info = &cl_hw->channel_info; + char *buf = NULL, *ptr = NULL; + char cc_str[MAX_CC_STR] = {0}; + char bw_str[MAX_BW_STR] = {0}; + size_t size; + u8 bw, bw_mhz, bw_max, max_power, channel, i; + + /* Read channel_info.txt into buf */ + size = cl_file_open_and_read(cl_hw->chip, "channel_info.txt", &buf); + + if (!buf) + return false; + + /* Jump to the correct country in the file */ + snprintf(cc_str, sizeof(cc_str), "[%s", cl_hw->chip->conf->ce_country_code); + ptr = strstr(buf, cc_str); + if (!ptr) + goto out; + + if (cl_parse_reg_domain(cl_hw, &ptr)) + goto out; + + /* Jump to the relevant band */ + if (cl_band_is_24g(cl_hw)) { + bw_max = CHNL_BW_40; + ptr = strstr(ptr, "2.4GHz"); + } else if (cl_band_is_5g(cl_hw)) { + ptr = strstr(ptr, "5.2GHz"); + bw_max = CHNL_BW_160; + } else { + ptr = strstr(ptr, "6GHz"); + bw_max = CHNL_BW_160; + } + + for (bw = 0; bw <= bw_max; bw++) { + if (!ptr) + goto out; + + i = 0; + + /* Jump to relevant bandwidth */ + bw_mhz = BW_TO_MHZ(bw); + snprintf(bw_str, sizeof(bw_str), "%uMHz:", bw_mhz); + ptr = strstr(ptr, bw_str); + + /* Iterate until end of line and parse (channel, max_power) */ + while (ptr && (ptr + 1) && (*(ptr + 1) != '\n')) { + ptr = strstr(ptr, "("); + if (!ptr) + goto out; + + if (sscanf(ptr, "(%hhu,%hhu)", &channel, &max_power) != 2) + goto out; + + if (!cl_channel_is_valid(cl_hw, channel) || + i == cl_channel_num(cl_hw)) + goto out; + + channel_info->channels[bw][i].channel = channel; + channel_info->channels[bw][i].max_power_q2 = max_power << 2; + channel_info->channels[bw][i].country_max_power_q2 = max_power << 2; + + i++; + ptr = strstr(ptr, ")"); + } + } + + kfree(buf); + return true; + +out: + kfree(buf); + return false; +} + +static bool cl_is_parsing_success(struct cl_hw *cl_hw) +{ + /* Check that there is at least one channel in any bw */ + u8 bw; + u8 max_bw = BAND_IS_5G_6G(cl_hw) ? CHNL_BW_160 : CHNL_BW_40; + + for (bw = 0; bw <= max_bw; bw++) + if (!cl_hw->channel_info.channels[bw][0].channel) + return false; + + return true; +} + +static void cl_chan_info_set_max_bw_6g(struct cl_hw *cl_hw) +{ + u8 i, bw, bw_cnt, channel, channel_gap; + struct cl_chan_info *chan_info; + + for (bw = 0; bw < CHNL_BW_MAX; bw++) { + chan_info = cl_hw->channel_info.channels[bw]; + bw_cnt = 0; + + for (i = 0; i < NUM_CHANNELS_6G; i++) { + channel = chan_info[i].channel; + + if (channel == 0) + break; + + channel_gap = channel - START_CHAN_IDX_6G; + + /* + * Verify that we don't combine together channels + * from different 80MHz sections + */ + if ((channel_gap % CL_160MHZ_CH_GAP) == 0) + bw_cnt = 0; + + if (i > 0) + bw_cnt++; + + /* Verify that we don't make illegal 80MHz combination */ + if ((channel_gap % CL_80MHZ_CH_GAP == 0) && bw_cnt == 3) + bw_cnt = 0; + + /* Verify that we don't make illegal 40MHz combination */ + if ((channel_gap % CL_40MHZ_CH_GAP == 0) && bw_cnt == 1) + bw_cnt = 0; + + if ((((bw_cnt + 1) % CL_160MHZ_HOP) == 0) && bw == CHNL_BW_160) { + chan_info[i].max_bw = CHNL_BW_160; + chan_info[i - 1].max_bw = CHNL_BW_160; + chan_info[i - 2].max_bw = CHNL_BW_160; + chan_info[i - 3].max_bw = CHNL_BW_160; + chan_info[i - 4].max_bw = CHNL_BW_160; + chan_info[i - 5].max_bw = CHNL_BW_160; + chan_info[i - 6].max_bw = CHNL_BW_160; + chan_info[i - 7].max_bw = CHNL_BW_160; + } else if ((((bw_cnt + 1) % CL_80MHZ_HOP) == 0) && (bw == CHNL_BW_80)) { + chan_info[i].max_bw = CHNL_BW_80; + chan_info[i - 1].max_bw = CHNL_BW_80; + chan_info[i - 2].max_bw = CHNL_BW_80; + chan_info[i - 3].max_bw = CHNL_BW_80; + } else if ((((bw_cnt + 1) % CL_40MHZ_HOP) == 0) && (bw >= CHNL_BW_40)) { + chan_info[i].max_bw = CHNL_BW_40; + chan_info[i - 1].max_bw = CHNL_BW_40; + } else { + chan_info[i].max_bw = CHNL_BW_20; + } + } + } +} + +static void cl_chan_info_set_max_bw_5g(struct cl_hw *cl_hw) +{ + u8 i, bw, bw_cnt, channel, channel_gap; + struct cl_chan_info *chan_info; + + for (bw = 0; bw < CHNL_BW_MAX; bw++) { + chan_info = cl_hw->channel_info.channels[bw]; + bw_cnt = 0; + + for (i = 0; i < NUM_CHANNELS_5G; i++) { + channel = chan_info[i].channel; + + if (channel == 0) + break; + + if (channel < 149) + channel_gap = channel - 36; + else + channel_gap = channel - 149; + + /* + * Verify that we don't combine together channels from + * different 80MHz sections + * (i.e. 36-48 can be combined into 80MHz channels, unlike 40-52) + */ + if ((channel_gap % CL_160MHZ_CH_GAP) == 0) + bw_cnt = 0; + + /* Check if 20MHz channels can be combined into 40MHz or 80MHz channels */ + if (i > 0) { + /* + * Verify that we don't combine together unsecutive channels + * (like 36 and 44 when 40 is missing) + */ + if ((chan_info[i].channel - chan_info[i - 1].channel) > + CL_20MHZ_CH_GAP) + bw_cnt = 0; + else + bw_cnt++; + } + + /* Verify that we don't make illegal 80MHz combination (like 44-56) */ + if ((channel_gap % CL_80MHZ_CH_GAP == 0) && bw_cnt == 3) + bw_cnt = 0; + + /* Verify that we don't make illegal 40MHz combination (like 40-44) */ + if ((channel_gap % CL_40MHZ_CH_GAP == 0) && bw_cnt == 1) + bw_cnt = 0; + + if ((((bw_cnt + 1) % CL_160MHZ_HOP) == 0) && bw == CHNL_BW_160) { + chan_info[i].max_bw = CHNL_BW_160; + chan_info[i - 1].max_bw = CHNL_BW_160; + chan_info[i - 2].max_bw = CHNL_BW_160; + chan_info[i - 3].max_bw = CHNL_BW_160; + chan_info[i - 4].max_bw = CHNL_BW_160; + chan_info[i - 5].max_bw = CHNL_BW_160; + chan_info[i - 6].max_bw = CHNL_BW_160; + chan_info[i - 7].max_bw = CHNL_BW_160; + } else if ((((bw_cnt + 1) % CL_80MHZ_HOP) == 0) && bw == CHNL_BW_80) { + chan_info[i].max_bw = CHNL_BW_80; + chan_info[i - 1].max_bw = CHNL_BW_80; + chan_info[i - 2].max_bw = CHNL_BW_80; + chan_info[i - 3].max_bw = CHNL_BW_80; + } else if ((((bw_cnt + 1) % CL_40MHZ_HOP) == 0) && bw >= CHNL_BW_40) { + chan_info[i].max_bw = CHNL_BW_40; + chan_info[i - 1].max_bw = CHNL_BW_40; + } else { + chan_info[i].max_bw = CHNL_BW_20; + } + } + } +} + +static void cl_chan_info_set_max_bw_24g(struct cl_hw *cl_hw) +{ + u8 i, bw, channel; + struct cl_chan_info *chan_info; + + for (bw = 0; bw < CHNL_BW_80; bw++) { + chan_info = cl_hw->channel_info.channels[bw]; + + for (i = 0; i < NUM_CHANNELS_24G; i++) { + channel = chan_info[i].channel; + + if (channel == 0) + break; + + if (channel < 14) + chan_info[i].max_bw = CHNL_BW_40; + else + chan_info[i].max_bw = CHNL_BW_20; + } + } +} + +static void cl_chan_info_set_max_bw(struct cl_hw *cl_hw) +{ + if (cl_band_is_6g(cl_hw)) + cl_chan_info_set_max_bw_6g(cl_hw); + else if (cl_band_is_5g(cl_hw)) + cl_chan_info_set_max_bw_5g(cl_hw); + else + cl_chan_info_set_max_bw_24g(cl_hw); +} + +static void cl_chan_info_dbg(struct cl_hw *cl_hw) +{ + struct cl_chan_info *chan_info; + u32 max_power_integer, max_power_fraction; + u8 i, j; + + for (i = 0; i < CHNL_BW_MAX; i++) { + cl_dbg_info(cl_hw, "Bandwidth = %uMHz\n", BW_TO_MHZ(i)); + for (j = 0; j < cl_channel_num(cl_hw); j++) { + chan_info = &cl_hw->channel_info.channels[i][j]; + + if (chan_info->channel == 0) + continue; + + max_power_integer = (chan_info->max_power_q2 / 4); + max_power_fraction = + (100 * (chan_info->max_power_q2 - 4 * max_power_integer) / 4); + + cl_dbg_info(cl_hw, "Channel = %u, max EIRP = %3u.%02u, bw = %uMHz\n", + chan_info->channel, max_power_integer, + max_power_fraction, BW_TO_MHZ(chan_info->max_bw)); + } + } +} + +/* Band 6G - default power */ +#define UNII_5_POW_Q2 (27 << 2) +#define UNII_6_POW_Q2 (27 << 2) +#define UNII_7_POW_Q2 (27 << 2) +#define UNII_8_POW_Q2 (27 << 2) + +/* Band 5G - default power */ +#define UNII_1_POW_Q2 (22 << 2) +#define UNII_2_POW_Q2 (27 << 2) +#define UNII_2_EXT_POW_Q2 (27 << 2) +#define UNII_3_POW_Q2 (27 << 2) + +/* Band 2.4G - default power */ +#define BAND_24G_POW_Q2 (36 << 2) + +static void cl_fill_channel_info(struct cl_hw *cl_hw, u8 bw, u8 ch_idx, u8 channel, + u8 country_max_power_q2, u8 max_power_q2) +{ + struct cl_channel_info *channel_info = &cl_hw->channel_info; + + channel_info->channels[bw][ch_idx].channel = channel; + channel_info->channels[bw][ch_idx].country_max_power_q2 = country_max_power_q2; + channel_info->channels[bw][ch_idx].max_power_q2 = max_power_q2; +} + +static void cl_set_default_channel_info_6g(struct cl_hw *cl_hw) +{ + u8 i, j, k; + + for (i = 0; i < CHNL_BW_MAX; i++) { + k = 0; + + /* Ch2 is a special case */ + cl_fill_channel_info(cl_hw, i, k, 2, UNII_5_POW_Q2, UNII_5_POW_Q2); + k++; + + for (j = START_CHAN_IDX_UNII5; j <= END_CHAN_IDX_UNII5; j += 4) { + cl_fill_channel_info(cl_hw, i, k, j, UNII_5_POW_Q2, UNII_5_POW_Q2); + k++; + } + + for (j = START_CHAN_IDX_UNII6; j <= END_CHAN_IDX_UNII6; j += 4) { + cl_fill_channel_info(cl_hw, i, k, j, UNII_6_POW_Q2, UNII_6_POW_Q2); + k++; + } + + for (j = START_CHAN_IDX_UNII7; j <= END_CHAN_IDX_UNII7; j += 4) { + cl_fill_channel_info(cl_hw, i, k, j, UNII_7_POW_Q2, UNII_7_POW_Q2); + k++; + } + + for (j = START_CHAN_IDX_UNII8; j <= END_CHAN_IDX_UNII8; j += 4) { + /* Channel 233 is valid only in 20MHz */ + if (i != CHNL_BW_20 && j == END_CHAN_IDX_UNII8) + break; + + cl_fill_channel_info(cl_hw, i, k, j, UNII_8_POW_Q2, UNII_8_POW_Q2); + k++; + } + } +} + +static void cl_set_default_channel_info_5g(struct cl_hw *cl_hw) +{ + u8 i, j, k; + + for (i = 0; i < CHNL_BW_MAX; i++) { + k = 0; + + for (j = 36; j <= 48; j += 4) { + cl_fill_channel_info(cl_hw, i, k, j, UNII_1_POW_Q2, UNII_1_POW_Q2); + k++; + } + + for (j = 52; j <= 64; j += 4) { + cl_fill_channel_info(cl_hw, i, k, j, UNII_2_POW_Q2, UNII_2_POW_Q2); + k++; + } + + for (j = 100; j <= 144; j += 4) { + /* 160MHz is supported only in channel 36 - 64 and 100 - 128 */ + if (i == CHNL_BW_160 && j == 132) + return; + + cl_fill_channel_info(cl_hw, i, k, j, UNII_2_EXT_POW_Q2, UNII_2_EXT_POW_Q2); + k++; + } + + for (j = 149; j <= 165; j += 4) { + /* Channel 165 is valid only in 20MHz */ + if (i != CHNL_BW_20 && j == 165) + break; + + cl_fill_channel_info(cl_hw, i, k, j, UNII_3_POW_Q2, UNII_3_POW_Q2); + k++; + } + } +} + +static void cl_set_default_channel_info_24g(struct cl_hw *cl_hw) +{ + u8 i, j; + + for (i = 0; i <= CHNL_BW_40; i++) + for (j = 0; j < 13; j++) + cl_fill_channel_info(cl_hw, i, j, j + 1, BAND_24G_POW_Q2, BAND_24G_POW_Q2); +} + +static void cl_set_default_channel_info(struct cl_hw *cl_hw) +{ + struct cl_channel_info *channel_info = &cl_hw->channel_info; + + memset(channel_info->channels, 0, sizeof(channel_info->channels)); + + channel_info->standard = CL_STANDARD_FCC; + + if (cl_band_is_6g(cl_hw)) + cl_set_default_channel_info_6g(cl_hw); + else if (cl_band_is_5g(cl_hw)) + cl_set_default_channel_info_5g(cl_hw); + else + cl_set_default_channel_info_24g(cl_hw); +} + +static u8 cl_regulatory_domain_max_power(struct cl_hw *cl_hw, int idx) +{ + u8 bw = 0; + u8 max_power = 0; + struct cl_channel_info *chan_info = &cl_hw->channel_info; + + for (bw = CHNL_BW_20; bw < CHNL_BW_MAX; bw++) { + u8 power = chan_info->channels[bw][idx].country_max_power_q2; + + if (max_power < power) + max_power = power; + } + + /* Translate from country_power (.25dBm) to max_power (1dBm) */ + return (max_power >> 2); +} + +static int cl_regulatory_domain_update_rule(struct cl_hw *cl_hw, int freq, int power) +{ + struct ieee80211_regdomain *rd = cl_hw->channel_info.rd; + struct ieee80211_reg_rule *reg_rule = &rd->reg_rules[rd->n_reg_rules - 1]; + struct ieee80211_power_rule *power_rule = ®_rule->power_rule; + + reg_rule->freq_range.end_freq_khz = MHZ_TO_KHZ(freq + 10); + if (power_rule->max_eirp < DBM_TO_MBM(power)) + power_rule->max_eirp = DBM_TO_MBM(power); + + return (reg_rule->freq_range.end_freq_khz - + reg_rule->freq_range.start_freq_khz); +} + +static void cl_regulatory_domain_add_rule(struct cl_hw *cl_hw, int freq, int max_power, u8 bw) +{ + struct ieee80211_regdomain *rd = cl_hw->channel_info.rd; + struct ieee80211_reg_rule *reg_rule = &rd->reg_rules[rd->n_reg_rules]; + struct ieee80211_freq_range *freq_range = ®_rule->freq_range; + struct ieee80211_power_rule *power_rule = ®_rule->power_rule; + + freq_range->start_freq_khz = MHZ_TO_KHZ(freq - 10); + freq_range->end_freq_khz = MHZ_TO_KHZ(freq + 10); + freq_range->max_bandwidth_khz = BW_TO_KHZ(bw); + + power_rule->max_eirp = DBM_TO_MBM(max_power); + power_rule->max_antenna_gain = DBI_TO_MBI(3); + + rd->n_reg_rules++; +} + +static void cl_regulatory_domain_set(struct cl_hw *cl_hw) +{ + int j = 0; + int diff = 0; + int power = 0, prev_power = 0; + u8 bw = 0, prev_bw = 0; + int freq = 0, prev_freq = 0; + u8 chan = 0; + struct ieee80211_regdomain *rd = cl_hw->channel_info.rd; + + memcpy(rd->alpha2, cl_hw->chip->conf->ce_country_code, 2); + + if (cl_hw->channel_info.standard == CL_STANDARD_FCC) + rd->dfs_region = NL80211_DFS_FCC; + else if (cl_hw->channel_info.standard == CL_STANDARD_ETSI) + rd->dfs_region = NL80211_DFS_ETSI; + else + rd->dfs_region = NL80211_DFS_UNSET; + + for (j = 0; j < cl_channel_num(cl_hw); j++) { + chan = cl_hw->channel_info.channels[CHNL_BW_20][j].channel; + if (!chan) + continue; + power = cl_regulatory_domain_max_power(cl_hw, j); + bw = cl_chan_info_get_max_bw(cl_hw, chan); + freq = ieee80211_channel_to_frequency(chan, cl_hw->nl_band); + if (freq - prev_freq > 20 || + (prev_power != power && diff >= BW_TO_KHZ(bw)) || + prev_bw != bw) { + cl_regulatory_domain_add_rule(cl_hw, freq, power, bw); + diff = 0; + } else { + diff = cl_regulatory_domain_update_rule(cl_hw, freq, power); + } + + prev_freq = freq; + prev_power = power; + prev_bw = bw; + } +} + +/* + * cl_hardware_power_table_update: Applies individual regulatory table entry + * Inputs: cl_hw - pointer to cl_hw + * bw_mhz - current bandwidth in MHz + * chan_start - match channels greater or equal to chan_start + * chan_end - match channels less than chan_end + * reg_pwr - ensure channel_info.channels[bw][ch_idx].max_power does not exceed this + * Output: updated channel_info.channels[bw][ch_idx].max_power + * and channel_info.channels[bw][ch_idx].max_total_power + * on all channels that match specified range + */ +static void cl_hardware_power_table_update(struct cl_hw *cl_hw, u8 bw_mhz, + u8 chan_start, u8 chan_end, u8 pwr_q2) +{ + struct cl_chan_info *chan_info = NULL; + u8 bw = 0; + u8 ch_idx = 0; + bool ch_found = false; + bool is_24g = cl_band_is_24g(cl_hw); + + if (bw_mhz == 20 || bw_mhz == 40 || (!is_24g && (bw_mhz == 80 || bw_mhz == 160))) { + bw = MHZ_TO_BW(bw_mhz); + } else { + cl_dbg_err(cl_hw, "Invalid bw %u\n", bw_mhz); + return; + } + + /* Iterate through all cl_channels[bw][ch_idx] - to find all matches */ + for (ch_idx = 0; ch_idx < cl_channel_num(cl_hw); ch_idx++) { + chan_info = &cl_hw->channel_info.channels[bw][ch_idx]; + + if (chan_start <= chan_info->channel && chan_info->channel < chan_end) { + ch_found = true; + + /* + * Max-Power = + * minimum between hardware_power_table and country code definition + */ + chan_info->max_power_q2 = min(pwr_q2, chan_info->max_power_q2); + chan_info->hardware_max_power_q2 = pwr_q2; + } + } + + if (!ch_found) + cl_dbg_info(cl_hw, "Skipping invalid channel range: %u - %u\n", + chan_start, chan_end); +} + +/* + * cl_hardware_power_table_parse(): + * Iterate through hardware power table entries and apply each one. + * Expected format: + * bw1(chan1=reg_pwr1;chan2=reg_pwr2;...)#bw2(chan3=reg_pwr3;chan4=reg_pwr4;...) ... + * Example: + * 20(36=22.0;40=22.75;149=21.75)#40(36=22.5;40=23.0;149=21.75)#80(36=21.75;40=21.5;149=22.25) + */ +static void cl_hardware_power_table_parse(struct cl_hw *cl_hw) +{ + s8 *table_str = NULL; + s8 *channel_str = NULL; + s8 *bw_set = NULL; + s8 *out_tok = NULL; + s8 *saveptr1 = NULL; + s8 *saveptr2 = NULL; + s8 in_reg_pwr[16] = {0}; + u8 bw_mhz = 0; + u8 chan_start = 0; + u8 chan_end = 0; + u8 curr_pwr_q2 = 0; + u8 next_pwr_q2 = 0; + + if (strlen(cl_hw->conf->ce_hardware_power_table) == 0) + return; /* Not configured */ + + table_str = kzalloc(CL_MAX_STR_BUFFER_SIZE / 2, GFP_KERNEL); + if (!table_str) + return; + + channel_str = kzalloc(CL_MAX_STR_BUFFER_SIZE / 2, GFP_KERNEL); + if (!channel_str) { + kfree(table_str); + cl_dbg_err(cl_hw, "Failed to allocate channel_str\n"); + return; + } + + strncpy(table_str, + cl_hw->conf->ce_hardware_power_table, + (CL_MAX_STR_BUFFER_SIZE / 2) - 1); + + /* Iterate through all bandwidth sets included in table_str */ + bw_set = cl_strtok_r(table_str, "#", &saveptr1); + while (bw_set) { + if (sscanf(bw_set, "%hhu(%s)", &bw_mhz, channel_str) != 2) { + bw_set = cl_strtok_r(NULL, "#", &saveptr1); + continue; + } + + /* Iterate through each channel in this bandwidth set */ + chan_start = 0; + chan_end = 0; + curr_pwr_q2 = 0; + next_pwr_q2 = 0; + out_tok = cl_strtok_r(channel_str, ";", &saveptr2); + + while (out_tok) { + if (sscanf(out_tok, "%hhu=%s", &chan_end, in_reg_pwr) == 2) { + next_pwr_q2 = convert_str_int_q2(in_reg_pwr); + + /* Apply regulatory table rule. Skip initial case */ + if (curr_pwr_q2 != 0 && chan_start != 0) + cl_hardware_power_table_update(cl_hw, bw_mhz, chan_start, + chan_end, curr_pwr_q2); + + /* Prepare next iteration */ + chan_start = chan_end; + curr_pwr_q2 = next_pwr_q2; + } + out_tok = cl_strtok_r(NULL, ";", &saveptr2); + } + + /* Handle last channel case */ + if (next_pwr_q2 != 0 && chan_start != 0) { + u8 chan_end; + + if (cl_band_is_6g(cl_hw)) + chan_end = 234; + else if (cl_band_is_5g(cl_hw)) + chan_end = 166; + else + chan_end = 15; + + cl_hardware_power_table_update(cl_hw, bw_mhz, chan_start, + chan_end, curr_pwr_q2); + } + + bw_set = cl_strtok_r(NULL, "#", &saveptr1); + } + + kfree(table_str); + kfree(channel_str); +} + +void cl_chan_info_init(struct cl_hw *cl_hw) +{ + struct cl_channel_info *channel_info = &cl_hw->channel_info; + + channel_info->use_channel_info = !cl_hw->chip->conf->ce_production_mode; + + if (channel_info->use_channel_info) { + cl_hw->channel_info.rd = kzalloc(sizeof(*cl_hw->channel_info.rd) + + NL80211_MAX_SUPP_REG_RULES * + sizeof(struct ieee80211_reg_rule), + GFP_KERNEL); + + if (!cl_hw->channel_info.rd) { + cl_dbg_err(cl_hw, "memory allocation failed!\n"); + return; + } + + if (!cl_parse_channel_info_txt(cl_hw) || !cl_is_parsing_success(cl_hw)) { + CL_DBG_WARNING(cl_hw, "Error parsing channel_info.txt. Using default!\n"); + cl_set_default_channel_info(cl_hw); + } + + cl_chan_info_set_max_bw(cl_hw); + cl_chan_info_dbg(cl_hw); + cl_regulatory_domain_set(cl_hw); + } else { + cl_set_default_channel_info(cl_hw); + + if (cl_band_is_6g(cl_hw)) + cl_hw->channel_info.rd = &cl_regdom_6g; + else if (cl_band_is_5g(cl_hw)) + cl_hw->channel_info.rd = &cl_regdom_5g; + else + cl_hw->channel_info.rd = &cl_regdom_24g; + } + + cl_hardware_power_table_parse(cl_hw); +} + +void cl_chan_info_deinit(struct cl_hw *cl_hw) +{ + if (cl_hw->channel_info.rd && + cl_hw->channel_info.use_channel_info) + kfree(cl_hw->channel_info.rd); +} + +struct cl_chan_info *cl_chan_info_get(struct cl_hw *cl_hw, u8 channel, u8 bw) +{ + int i = 0; + struct cl_chan_info *chan_info; + + for (i = 0; i < cl_channel_num(cl_hw); i++) { + chan_info = &cl_hw->channel_info.channels[bw][i]; + + if (chan_info->channel == channel) + return chan_info; + } + + return NULL; +} + +u8 cl_chan_info_get_max_bw(struct cl_hw *cl_hw, u8 channel) +{ + s8 bw = 0; + + for (bw = CHNL_BW_160; bw > CHNL_BW_20; bw--) + if (cl_chan_info_get(cl_hw, channel, bw)) + return (u8)bw; + + return CHNL_BW_20; +} + +s16 cl_chan_info_get_eirp_limit_q8(struct cl_hw *cl_hw, u8 bw) +{ + /* Eirp_limit = min(country_limit, hw_limit) */ + struct cl_chan_info *chan_info = cl_chan_info_get(cl_hw, cl_hw->channel, bw); + + return chan_info ? (chan_info->max_power_q2 << 6) : CL_DEFAULT_CHANNEL_POWER_Q8; +} + +s16 cl_chan_info_get_country_limit_q8(struct cl_hw *cl_hw, u8 channel, u8 bw) +{ + struct cl_chan_info *chan_info = cl_chan_info_get(cl_hw, channel, bw); + + return chan_info ? (chan_info->country_max_power_q2 << 6) : CL_DEFAULT_CHANNEL_POWER_Q8; +} + +s16 cl_chan_info_get_hardware_limit_q8(struct cl_hw *cl_hw, u8 channel, u8 bw) +{ + struct cl_chan_info *chan_info = cl_chan_info_get(cl_hw, channel, bw); + + return chan_info ? (chan_info->hardware_max_power_q2 << 6) : CL_DEFAULT_CHANNEL_POWER_Q8; +} + +u8 cl_chan_info_get_max_power(struct cl_hw *cl_hw, u8 channel) +{ + struct cl_chan_info *chan_info; + u8 bw = 0; + u8 max_power_q2 = 0; + + for (bw = 0; bw < ARRAY_SIZE(cl_hw->channel_info.channels); bw++) { + chan_info = cl_chan_info_get(cl_hw, channel, bw); + + if (!chan_info) + continue; + + if (chan_info->max_power_q2 > max_power_q2) + max_power_q2 = chan_info->max_power_q2; + } + + return max_power_q2 >> 2; +} From patchwork Thu Jun 17 15:58:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 378DCC49EA2 for ; Thu, 17 Jun 2021 16:04:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CA2E6120A for ; Thu, 17 Jun 2021 16:04:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232629AbhFQQGK (ORCPT ); Thu, 17 Jun 2021 12:06:10 -0400 Received: from mail-eopbgr140040.outbound.protection.outlook.com ([40.107.14.40]:17172 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233638AbhFQQF5 (ORCPT ); Thu, 17 Jun 2021 12:05:57 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=J9AiBU9Qkt0FfvGk23stwpiNLvJKbsFHkYk70X9XrBRJPL337XpSQXTY1PeP2AG34DB9t+5BOTdzHdKDWmeXnkImDBwGvzLEc3HBxWKcRUvQZ4k92Ou4e8O5Htud0SWT9cTqBEpLb6558LkTKCMVL07hgMQRqBmvu9Mm4UeUk9G6yfWOCltfWqx24woO7dt2y/yQBnh/Rg3pyn4/cKPtLVDpKyfOM52nnXA5AFqOq4yxe0xeLnMNnHjZfeELGjAjxhOi6evRpOjZA5jInxQFIoUFD4VwpYxtJ4ZqegdKiV3Dw5wl9is5TWKmpVz11QlYYW16/Pq7nMyWka+N7h/WeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gxZxPV6qAip0we8SIiVzfX6G1NO5z9TpQg+c98DaGlw=; b=AuoJgCa+AK/mLkd5g6iK35lhFmdY5v65RB5470MQvF7txNWlWuiTZJ1bRONANQ8X0V1Ll2VhNV0mrfBodN9UJouBQxIp12I8Bvhu6ndXz3NWODiwiHRNOUdD0P/BkMyZrqugbViunsidOqug1UqjK/srEtsEcHidzGw/u1YTAsVYsFqaZ7undEm6/Cz+k/6z5yt2l1CmHVOmAv/8t/Rveb2/J/KZmoCxLt654IMlf58U1zzITMO0Hb2x2jolCYdrLG78uOYemuVPDjJvSXjmw1n9xL/GoypUGGJiMoUKFdpi2sCpHkOm3SQu29g45kEqKQotfUIYO/hm7RQssAN57A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gxZxPV6qAip0we8SIiVzfX6G1NO5z9TpQg+c98DaGlw=; b=Ys4+67i/N0UVAxELUWqFSQO52HYGkHkWKjq8kh/NQT3v4Fi2l7KHPZEbUqtEEB8CdLFq+EL3e/+qxkxcnVHQN054GmnCDaBDAa9ns3PS1Zbr+MdRizGOJofg2AhDrkTixG53K9I4UWFdhpSwsv3pJ3524uqkj4oMq6Q2L/ImTeA= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1234.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:388::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16; Thu, 17 Jun 2021 16:03:41 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:03:41 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 042/256] cl8k: add chip.c Date: Thu, 17 Jun 2021 15:58:49 +0000 Message-Id: <20210617160223.160998-43-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:19 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 05a43e5e-76ae-484f-b18b-08d931a96d50 X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2089; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iZ5qVfHUF12qS4XPdETaLxWfUHj6GA/1h4wgM62KPwzv8es5B2d3urNUBXmcuf7YZgDrB8B0JWKrp5HWn5GLpAA3l2ZaLNb1edQJdCpadocE5qf98q3cBW0s+mqpAwqATyW+JwkVgatAXxqINV9Hd6ZdIVMnGTciaOdgq4PfV3kUFrsTStajhzouddr3fJAVcMzYnSCl72ORi7qoxB8dD6ufL4VhAoi+PWVWD6mxnUYcksYxheQIbJ1NeacJKwcD4cR6WlV+ojAEsYe/TaqCv4yEt00p45xobzSGQ9fB1n8W5OGEZO1nxcoodcq7M2t+QP9fuxDak1MLkVUvLXyMbaAEOVLsHuFGyIiFWQIO96Ed5xp4G1V2kIoywTg4pB3hDbNxIuxHrvaG0G1/WLjH2nIjKFUlaH+zDDP9vOZp06WLkXNCY4SI8y31b1Sw5kaxdq2Qw8GDR3jLFPak0aQv0/ImjJi82vGbDN574gBYV7JQkj5WG1YjXA6JfloJ8HLrzkXslqDEmPSJTVVz5k8/LQROcIXoHF56Nf8WhUU4UauE9J9RzrXvFmAQVvYOtxPDknQNW2RoICZVqPZc7wQzyZIB5zLoNOqo/X6oOiGlXXDaCVVMoVJDU76/Y1ozvA2kY9pKwog7iHQZHBBXUoA66SaEaid15jLR8HUILKBgZpCw6g7swL23MLNvsp3eoZfWG8t/NrBCZsodQczmlR6HOw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XF0uVJ/UR949EM6exNksrHVSOwje4YN6dEHoGq9Un7wHAV9+/xuXUKfybNqApjDBZ3whNkXm+xEso5KaMRo0qfy3YyS68Wu93+/d5qYXAvshr8aNGNtsUFzwU/hWzMSYUTUEGUGz8LIDK2fqNuNS1UOHt5xSPYK244VIfkwJlit1MEVd40Gq5vhPt7KXjYjOiVs/KSRCCEz/QBqAS5Dlo3kfM/3vTJQyGlKKcM1I783oPPQYu6XqhFCnc9p1qi96jdHDa/WQucrLSioOmRiuGcJLtgzr7GFsA6BVnNSFo+Xt+DRyvhalSat+jycdWQ1px2wqPHctHB1g5VJEgMJImzcpgpkq6PptQzbvTk7Be/pZhMpISshsLZxBESP3/hht+OsyjCXkUZAsne7XvHPTwaTDRjZu0GxbmcHBT9K/ioCFq6OvMxlpsrb7S40VfCIlARXyW4ngMoU5sap9LekOZ9TPkDdmBJAH71yTEUvnySt7+tygVdEokSFcVurQUDWHdlOCk2cWHMCnykELZ/U8PulpF/J6ZeQL+UJitXc2NUs58zlMMRUcHtO5FvDKB0aA5iG2OkzovPrmxxBRnyGMvMP9I8o66+iZwj5hN2J2paScB7EBc0zakCTCiX8qa+KAu0r5XdZxb0NeRChTEWkKZb5XnEzpBOald3JsP/PlUVAHOpIKfApk9DYZIo9J/vXZj7sHuLGO8EzXnIaXXizSJZU8vyAaCDwDZ65ib0wNuRj+1/hSJeRbI/xr5t8bzk+T3sOZK0IajMmSB5q/do9DDssy4MCaPl8CtDFaW3EzUsK+ndgagJQVlPQZ/54UWmNs2QJyZYwnm+sVz9rLL1yHLb56quaCzKx3yfzu/RQAUGGXGptCAzjA3+LCNi+rV7lVqPBR4IO7b87lmKxTuh7RH5a7nGJDsqcXcN7CSHvCZEBJ/f57QhcclVYQVPSBYEFKWpDOIixjrI8eXgK+Ii3IuHyAFQfTh7tOVJWYEH8wVkMcuxshC//ciVqfROmZfe8QLdJ3c2ASemauNljHr9P+NAVb/No07N3thZ4DRz6w+m9H+cNh+iEm9PqjPw1xCnZ2QfdWPXWMD/eG8uL7/fD3ZMd6i9n7uFUDzWVS7yEN/7t0Idhtj63z4jU5h9hu+OB33eFK4MJBSPAEAfZO88iF8we9RjhMpMWl/bHREvgFV3Ph+oTq2nqthSaM8KRUcI+sUN2pB5LwzadYsQVaqJby6Z+ZNJt15/OAqaNcJs6/3vRmneIPtJsRUfNHabdSB3xrBRWLQVtos6EZHUHgpZkRXDeSNKm/zb7nUzhYUsh3SJNJvCw1bI2z68qjuv/bBiee X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 05a43e5e-76ae-484f-b18b-08d931a96d50 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:20.4298 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BYI6W+V8j/GLGyNAd5YPM261bBFV3gBLLlNTUeE6FpwuXMq9Ces/rp6+baasJ6GId+tSyGUF0qCYh6za9r38Xw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/chip.c | 241 ++++++++++++++++++++++++ 1 file changed, 241 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/chip.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/chip.c b/drivers/net/wireless/celeno/cl8k/chip.c new file mode 100644 index 000000000000..5876b1da1857 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/chip.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "chip.h" +#include "chip_config.h" +#include "utils/utils.h" +#include "reg/reg_access.h" +#include "reg/reg_ipc.h" +#include "temperature.h" +#include "fem.h" +#include "e2p.h" +#include "ela.h" +#include "utils/string.h" +#include "main.h" +#include "netlink.h" +#include "data_rates.h" +#ifdef CONFIG_CL_PCIE +#include "bus/pci/irq.h" +#endif + +#define CL_ALIGN_BOUND_64KB BIT(16) + +static void cl_chip_set_max_antennas(struct cl_chip *chip) +{ + switch (chip->pci_dev->device) { + case 0x8040: + case 0x8046: + chip->max_antennas = MAX_ANTENNAS_CL804X; + break; + case 0x8060: + case 0x8066: + chip->max_antennas = MAX_ANTENNAS_CL806X; + break; + case 0x8080: + case 0x8086: + default: + chip->max_antennas = MAX_ANTENNAS_CL808X; + break; + } + + cl_dbg_chip_trace(chip, "max_antennas = %u\n", chip->max_antennas); +} + +static int cl_chip_print_serial_number(struct cl_chip *chip) +{ + u8 serial_number[SIZE_GEN_SERIAL_NUMBER + 1] = {0}; + + if (cl_e2p_read(chip, (u8 *)&serial_number, SIZE_GEN_SERIAL_NUMBER, ADDR_GEN_SERIAL_NUMBER)) + return -1; + + if (strlen(serial_number) == 0) + CL_DBG_WARNING_CHIP(chip, "Serial-number in not set in EEPROM\n"); + else + cl_dbg_chip_verbose(chip, "Serial-number = %s\n", serial_number); + + return 0; +} + +static int cl_chip_ring_indices_init(struct cl_chip *chip) +{ + struct cl_ring_indices *ring_indices = &chip->ring_indices; + + ring_indices->pool = dma_pool_create("cl_ring_indices_pool", chip->dev, + (sizeof(struct cl_ipc_ring_indices) * TCV_MAX), + CL_ALIGN_BOUND_64KB, CL_ALIGN_BOUND_64KB); + + if (!ring_indices->pool) { + cl_dbg_chip_err(chip, "ring_indices pool create failed !!!\n"); + return -ENOMEM; + } + + ring_indices->params = dma_pool_alloc(ring_indices->pool, GFP_KERNEL, + &ring_indices->dma_addr); + if (!ring_indices->params) + return -ENOMEM; + + return 0; +} + +static void cl_chip_ring_indices_deinit(struct cl_chip *chip) +{ + if (chip->ring_indices.params) { + dma_pool_free(chip->ring_indices.pool, + chip->ring_indices.params, + chip->ring_indices.dma_addr); + chip->ring_indices.params = NULL; + } + + dma_pool_destroy(chip->ring_indices.pool); + chip->ring_indices.pool = NULL; +} + +struct cl_chip *cl_chip_alloc(u8 idx) +{ + struct cl_chip *chip = kzalloc(sizeof(*chip), GFP_KERNEL); + + if (!chip) + return NULL; + + chip->idx = idx; + return chip; +} + +void cl_chip_dealloc(struct cl_chip *chip) +{ + cl_chip_config_dealloc(chip); + kfree(chip); +} + +int cl_chip_init(struct cl_chip *chip) +{ + int ret = 0; + + chip->agc_table_entry = U8_MAX; + + spin_lock_init(&chip->isr_lock); + spin_lock_init(&chip->spi_lock); + + rwlock_init(&chip->cl_hw_lock); + + cl_chip_set_max_antennas(chip); + +#ifdef CONFIG_CL_PCIE + ret = cl_irq_request(chip); + if (ret) + return ret; +#endif + ipc_host_global_int_en_set(chip, 1); + + cl_temperature_init(chip); + + ret = cl_e2p_init(chip); + if (ret) { + cl_dbg_chip_err(chip, "cl_e2p_init failed %d\n", ret); + return ret; + } + + ret = cl_fem_init(chip); + if (ret) + return ret; + + ret = cl_chip_ring_indices_init(chip); + if (ret) + return ret; + + cl_chip_print_serial_number(chip); + + cl_wrs_tables_global_build(); + cl_data_rates_inverse_build(); + + return ret; +} + +void cl_chip_deinit(struct cl_chip *chip) +{ + cl_chip_ring_indices_deinit(chip); + cl_temperature_close(chip); + cl_e2p_close(chip); + ipc_host_global_int_en_set(chip, 0); + +#ifdef CONFIG_CL_PCIE + cl_irq_free(chip); +#endif +} + +bool cl_chip_is_enabled(struct cl_chip *chip) +{ + return cl_chip_is_tcv0_enabled(chip) || cl_chip_is_tcv1_enabled(chip); +} + +bool cl_chip_is_both_enabled(struct cl_chip *chip) +{ + return cl_chip_is_tcv0_enabled(chip) && cl_chip_is_tcv1_enabled(chip); +} + +bool cl_chip_is_tcv_enabled(struct cl_chip *chip, u8 tcv_idx) +{ + return chip->conf->ce_tcv_enabled[tcv_idx]; +} + +bool cl_chip_is_tcv0_enabled(struct cl_chip *chip) +{ + return chip->conf->ce_tcv_enabled[TCV0]; +} + +bool cl_chip_is_tcv1_enabled(struct cl_chip *chip) +{ + return chip->conf->ce_tcv_enabled[TCV1]; +} + +void cl_chip_set_hw(struct cl_chip *chip, struct cl_hw *cl_hw) +{ + if (cl_hw_is_tcv0(cl_hw)) + chip->cl_hw_tcv0 = cl_hw; + else + chip->cl_hw_tcv1 = cl_hw; +} + +void cl_chip_unset_hw(struct cl_chip *chip, struct cl_hw *cl_hw) +{ + if (cl_hw_is_tcv0(cl_hw)) + chip->cl_hw_tcv0 = NULL; + else + chip->cl_hw_tcv1 = NULL; +} + +bool cl_chip_is_8ant(struct cl_chip *chip) +{ + return chip->max_antennas == MAX_ANTENNAS_CL808X; +} + +bool cl_chip_is_6ant(struct cl_chip *chip) +{ + return chip->max_antennas == MAX_ANTENNAS_CL806X; +} + +bool cl_chip_is_4ant(struct cl_chip *chip) +{ + return chip->max_antennas == MAX_ANTENNAS_CL804X; +} + +static u16 cl_chip_get_device_id(struct cl_chip *chip) +{ + u16 device_id = chip->pci_dev->device; + + /* If device-id is default, set it accoridng to phy-dev. */ + if (device_id == 0x8000 || device_id == 0x8001) + device_id = IS_PHY_ATHOS(chip) ? 0x8086 : 0x8080; + + return device_id; +} + +bool cl_chip_is_6g(struct cl_chip *chip) +{ + u16 device_id = cl_chip_get_device_id(chip); + u8 band = device_id & 0xf; + + return (band == 6); +} + From patchwork Thu Jun 17 15:58:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45922C48BE5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 044/256] cl8k: add chip_config.c Date: Thu, 17 Jun 2021 15:58:51 +0000 Message-Id: <20210617160223.160998-45-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:21 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b6956fb4-65f1-49c4-e706-08d931a96e81 X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:175; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X85dDIDNdyj9hyi6U2DcBupYIxvtBU8TeA2B7nsss4aYBaB7i/W5GhBcfm+YkwZ+oFyoaYJm/uY5d/HMlfAhWNwqbtvN8ff9hTuld++rN7eckXlpHWsDe3goLJ2hJvINDmaG95gzLeKdQO0lzH8nHxD7O/o/n7h9F6KOXQTrplEIdhJHOtqaUpHFpR+CRrt+6oxeYDw/H+BmX0CvxbB7vUGKqS9KmeG9MNm3xo670RIwKnU29Dy6FLgOVNXqQ5JoGoQiwZlKa8iXJK9cUvcTk6LVLiAvLwW8jbevfkRrPwkVWc3R5xGfIHlkDOs06XjBIV0pMIs36VVpQFS1Lzxrcvf75Xig/Z9Zk+z/8pfeDEJd85v8Sns6YX1lldYabVIpUr/iqdZ1YbHz9wR51jCTcPkem3Uiah8NDyMWPe+uMd2IPWuX7nGWJrmVty8OOoOsuUHPryTnHpCK9RyXL9ZmrPGpA0AQ+NjAzcN4a1XzI8X2BPnVsgUgEFU5lrjcZ32J1m9OxxMYVpYf7FRoBAGBiriEWnZ8WPQckv9xLhFuU5IMAdFP4pytrvFpP5Opnoidnl+5ZiGsYUHUXci6RtpWunVVtO+XFcTfs+IPvhyuXJlD2R+rzwStmuK/tOQZ1DWsp/599JNXTAcomNHeUniBtOi52e00na+ThiHe597w/IWPSQjp6QJE3MOftPcoIVNmWKvtgrHgsoC5ePMEnUVFQQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K0C6txkqDb+lvVm059LKGR6T7Yw540JPrAQ/OuOAGMcFwlFPubYW/iaVtFkRa9p1JO8OoKiJhJh5Pb/GkfJVuige6724P+LNZStlxLNf93IgFoypqch1E3SYmgPdObQeuubrdcuzh1LinGtq4GY59CXEXwuoaTD+EU+1fihTBvXtNktRnFtIuVAj6HUoSwZ1z8sacW4ZE0wIy7tsA/iGRFz3Wd9ezflW12AFpOGxe+P8WzAUjJTFGYXSHiYQ6iU6O2VfQ+ys5pf9G8OvxeV4SH5klUUOB5yrb2VqYyZkFeNvRwW6iQvrnZ7uu+1Kvm4t8b+jcHie7ZSCZNlNz/ztxwHv4aKMjVj3tOI8WVugj+SjoOdtylZH0gOpP+WeJrzYAsPFj8HvsIEvxt2UQi3UknvvG4/gk/DPL+YE5EkbU8Hv0EXsUsOBX1pSJh6DYTOUDV0SWeVEstP5I6i2UbGKuVDrBjyKI0w2ZCJ77wVv3MaZadGSjGJSD4AmylpAsuj6iwHzXbt0T/DvttIuek8drHJJaQOLkUJmtoOjGZiNM8P2+ivK91DULC5jjYCgemrSlvMzXgrbKNZMEhdsYyIbshgI2iNUJunFrY09jFhAesb0GzodJHAnxAu09s5VI61S8vbR9ZDr20ZTai8EIvz6um2P9ALNZY6d73OwVdfsmfbYadsmLs3Tn5WZlqq6IwMm1afH9/J5CqXC2qxgoTyRL834YJfKOg3aUxZ/WnpwcvOVvmQbZBUGPO1hpMn2/azLy3MYUsO7jTPL74EfC/cvRkCqt/Dr9wMxCkmjfzP6oe0e0PgLwbbLabv/LXzcdoImsAyrp/aYO8wTQiK+JasJARD8AwAHZH7VqUIf8BtFBnExSGlBIArFdzBPNzvvCd+juQB818czhOMmx04UdnNE0Pg3iC5rddfGe/XxLHXal0+GSGC13Jklma/1zii3Wc5ogVSKAIlAXCL2Z6Ww1nwWxB03KvHkeuEa6DCMZVsJU/cEvNvS8NcpxmM9dMoEt/JySrk5UkqNZnJaryy2x8lVgBNTSxjVNFVpU93+DzbW8lEWHjhjNro7Sw0aqfmFwwpte0OpzbZkGk9n8s6IoxeJPl2yC933kfNk5W6+FVdfUQQdYgCwvMXhNpcgMVw35kmKBDbltj68Fzfj8PHmdjXtwTljcAX1l0WrIV67z7X6AE7stbS7gRypQUreVJ2/dpis7G0/0kweZMhyMnB3ScPYBVcbD1XIpckCE7ZT5zOCFejRKJmlgX7Oini8YYqSdU4oZtTpPIywii5BwwGUbo6dQkLCtd0h4acPWIBVYanSNgvy+E89tSa6uCPo98cPSlFy X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6956fb4-65f1-49c4-e706-08d931a96e81 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:22.4609 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YtdTNG6aWiEvNPMbjvyd3A66ONE1AGSqv4sa+2b6cK5PJUhzQ4NKaB/IibV2HrWS82QMKBRleHVtNyv8fpvkPg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/chip_config.c | 290 ++++++++++++++++++ 1 file changed, 290 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/chip_config.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/chip_config.c b/drivers/net/wireless/celeno/cl8k/chip_config.c new file mode 100644 index 000000000000..c6d60ff685d5 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/chip_config.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chip_config.h" +#include "chip.h" +#include "utils/file.h" +#include "config.h" + +#define MAX_FIRST_MASK_BIT ((ETH_ALEN * 8) - 1) + +static struct cl_chip_conf chip_conf = { + .ce_tcv_enabled = { + [TCV0] = false, + [TCV1] = false + }, + .ce_lmac = "lmacfw.bin", + .ce_smac = "smacfw.bin", + .ce_umac = "no_load", + .ce_irq_smp_affinity = -1, + .ce_eeprom_mode = E2P_MODE_BIN, + .ce_production_mode = false, + .ci_pci_msi_enable = true, + .ci_dma_lli_max_chan = { + [TCV0] = 6, + [TCV1] = 3 + }, + .ce_country_code = "EU", + .ce_ela_mode = "default", + .ci_phy_dev = PHY_DEV_OLYMPUS, + .ce_debug_level = DBG_LVL_ERROR, + .ce_host_pci_gen_ver = 3, + .ce_temp_comp_en = false, + .ce_temp_protect_en = TEMP_PROTECT_OFF, + .ce_temp_protect_delta = 0, + .ce_temp_protect_th_max = 110, + .ce_temp_protect_th_min = 100, + .ce_temp_protect_tx_period_ms = 50, + .ce_temp_protect_radio_off_th = 115, + .ce_phys_mac_addr = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .ce_lam_enable = true, + .ce_first_mask_bit = 0, + .ci_no_capture_noise_sleep = true, + .ci_dcoc_mv_thr = { + [CHNL_BW_20] = 150, + [CHNL_BW_40] = 100, + [CHNL_BW_80] = 100, + [CHNL_BW_160] = 100 + }, + .ci_lolc_db_thr = -40, + .ci_iq_db_thr = -46, + .ci_rx_resched_tasklet = false, + .ci_rx_skb_max = 10000, + .ce_calib_scan_en = false, +}; + +static int update_config(struct cl_chip *chip, char *name, char *value) +{ + struct cl_chip_conf *conf = chip->conf; + + READ_BOOL_ARR(ce_tcv_enabled, TCV_MAX); + READ_STR(ce_lmac); + READ_STR(ce_smac); + READ_STR(ce_umac); + READ_S32(ce_irq_smp_affinity); + READ_U8(ce_eeprom_mode); + READ_BOOL(ce_production_mode); + READ_BOOL(ci_pci_msi_enable); + READ_U8_ARR(ci_dma_lli_max_chan, TCV_MAX); + READ_STR(ce_country_code); + READ_STR(ce_ela_mode); + READ_U8(ci_phy_dev); + READ_S8(ce_debug_level); + READ_U8(ce_host_pci_gen_ver); + READ_BOOL(ce_temp_comp_en); + READ_U8(ce_temp_protect_en); + READ_S8(ce_temp_protect_delta); + READ_S16(ce_temp_protect_th_max); + READ_S16(ce_temp_protect_th_min); + READ_U16(ce_temp_protect_tx_period_ms); + READ_S16(ce_temp_protect_radio_off_th); + READ_MAC(ce_phys_mac_addr); + READ_BOOL(ce_lam_enable); + READ_U8(ce_first_mask_bit); + READ_BOOL(ci_no_capture_noise_sleep); + READ_U8_ARR(ci_dcoc_mv_thr, CHNL_BW_MAX); + READ_S8(ci_lolc_db_thr); + READ_S8(ci_iq_db_thr); + READ_BOOL(ci_rx_resched_tasklet); + READ_U32(ci_rx_skb_max); + READ_BOOL(ce_calib_scan_en); + + if (!cl_config_is_non_driver_param(name)) { + CL_DBG_ERROR_CHIP(chip, "No matching conf for nvram parameter %s\n", name); + return -EINVAL; + } + + return 0; +} + +static int post_configuration(struct cl_chip *chip) +{ + struct cl_chip_conf *conf = chip->conf; + + if (!conf->ce_tcv_enabled[TCV0] && conf->ce_tcv_enabled[TCV1]) { + CL_DBG_ERROR_CHIP(chip, + "TCV1 can't be enabled without enabling TCV0\n"); + return -EINVAL; + } + + if (conf->ce_eeprom_mode >= E2P_MODE_MAX) { + CL_DBG_ERROR_CHIP(chip, + "Invalid ce_eeprom_mode [%u]. Must be 0 (file) or 1 (eeprom)\n", + conf->ce_eeprom_mode); + return -EINVAL; + } + + if (conf->ce_first_mask_bit > MAX_FIRST_MASK_BIT) { + CL_DBG_ERROR_CHIP(chip, "Invalid ce_first_mask_bit (%u). Must be <= %u\n", + conf->ce_first_mask_bit, MAX_FIRST_MASK_BIT); + return -EINVAL; + } + + return 0; +} + +static int set_all_params_from_buf(struct cl_chip *chip, char *buf, loff_t size) +{ + char *line = buf; + char name[MAX_PARAM_NAME_LENGTH]; + char value[STR_LEN_256B]; + char *begin; + char *end; + int ret = 0; + int name_length = 0; + int value_length = 0; + + while (line && strlen(line) && (line != (buf + size))) { + if ((*line == '#') || (*line == '\n')) { + /* Skip comment or blank line */ + line = strstr(line, "\n") + 1; + } else if (*line) { + begin = line; + end = strstr(begin, "="); + + if (!end) { + ret = -EBADMSG; + goto exit; + } + + end++; + name_length = end - begin; + value_length = strstr(end, "\n") - end + 1; + + if (name_length >= MAX_PARAM_NAME_LENGTH) { + cl_dbg_chip_err(chip, "Name too long (%u)\n", name_length); + ret = -EBADMSG; + goto exit; + } + if (value_length >= STR_LEN_256B) { + cl_dbg_chip_err(chip, "Value too long (%u)\n", value_length); + ret = -EBADMSG; + goto exit; + } + + snprintf(name, name_length, "%s", begin); + snprintf(value, value_length, "%s", end); + + ret = update_config(chip, name, value); + if (ret) + goto exit; + + line = strstr(line, "\n") + 1; + } + } + +exit: + + return ret; +} + +int cl_chip_config_read(struct cl_chip *chip) +{ + char *buf = NULL; + loff_t size = 0; + int ret = 0; + char filename[CL_FILENAME_MAX] = {0}; + + /* Allocate cl_chip_conf */ + chip->conf = kzalloc(sizeof(*chip->conf), GFP_KERNEL); + if (!chip->conf) + return -ENOMEM; + + /* Copy default parameters */ + memcpy(chip->conf, &chip_conf, sizeof(*chip->conf)); + + snprintf(filename, sizeof(filename), "cl_chip%u.dat", chip->idx); + pr_debug("%s: %s\n", __func__, filename); + size = cl_file_open_and_read(chip, filename, &buf); + + if (!buf) { + pr_err("read %s failed !!!\n", filename); + return -ENODATA; + } + + ret = set_all_params_from_buf(chip, buf, size); + if (ret) { + kfree(buf); + return ret; + } + + kfree(buf); + + if (!cl_chip_is_enabled(chip)) { + cl_dbg_chip_verbose(chip, "Disabled\n"); + return -EOPNOTSUPP; + } + + ret = post_configuration(chip); + + return ret; +} + +int cl_chip_config_set(struct cl_chip *chip, char *buf, loff_t size) +{ + loff_t new_size = size + 1; + char *new_buf = kzalloc(new_size, GFP_KERNEL); + int ret; + + if (!new_buf) + return -ENOMEM; + + /* Add '\n' at the end of the string, before the NULL */ + memcpy(new_buf, buf, size); + new_buf[size - 1] = '\n'; + + ret = set_all_params_from_buf(chip, new_buf, new_size); + if (ret == 0) + ret = post_configuration(chip); + + kfree(new_buf); + + return ret; +} + +void cl_chip_config_dealloc(struct cl_chip *chip) +{ + kfree(chip->conf); +} + +void cl_chip_config_print(struct cl_chip *chip) +{ + struct cl_chip_conf *conf = chip->conf; + + pr_debug("=======================\n"); + pr_debug(" Chip%u configuration\n", chip->idx); + pr_debug("=======================\n"); + + print_unsigned_arr(ce_tcv_enabled, TCV_MAX); + print_str(ce_lmac); + print_str(ce_smac); + print_str(ce_umac); + print_signed(ce_irq_smp_affinity); + print_unsigned(ce_eeprom_mode); + print_bool(ce_production_mode); + print_bool(ci_pci_msi_enable); + print_unsigned_arr(ci_dma_lli_max_chan, TCV_MAX); + print_str(ce_country_code); + print_str(ce_ela_mode); + print_unsigned(ci_phy_dev); + print_signed(ce_debug_level); + print_unsigned(ce_host_pci_gen_ver); + print_bool(ce_temp_comp_en); + print_unsigned(ce_temp_protect_en); + print_signed(ce_temp_protect_delta); + print_signed(ce_temp_protect_th_max); + print_signed(ce_temp_protect_th_min); + print_unsigned(ce_temp_protect_tx_period_ms); + print_signed(ce_temp_protect_radio_off_th); + print_mac(ce_phys_mac_addr); + print_bool(ce_lam_enable); + print_unsigned(ce_first_mask_bit); + print_bool(ci_no_capture_noise_sleep); + print_unsigned_arr(ci_dcoc_mv_thr, CHNL_BW_MAX); + print_signed(ci_lolc_db_thr); + print_signed(ci_iq_db_thr); + print_bool(ci_rx_resched_tasklet); + print_unsigned(ci_rx_skb_max); + print_bool(ce_calib_scan_en); +} + From patchwork Thu Jun 17 15:58:55 2021 Content-Type: text/plain; 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Thu, 17 Jun 2021 16:03:44 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 048/256] cl8k: add coredump.c Date: Thu, 17 Jun 2021 15:58:55 +0000 Message-Id: <20210617160223.160998-49-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:25 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2f70d0a6-4c6c-45a3-3b39-08d931a970e5 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uDsU2DsoUPgnTTfWPhRegFX26+XTZUzcR9iicxapvBCcba1crylMQf9RAi0WcKaaKo9LyCpYw8PM/XACnBnf0t6iS/zbNie0Of9BN5PmyXU+0ErmoXWVB9AZBpCkEwapw0ReWlqU4UTe0SwtUa7TtRPWP/xi14qEFWl8m3JzM87X4EVEVJ9r1IFSVG7q8Nstvy+XlmXyUtqHRkoNQpGcPgV9pXwip1GXtztUmWs5/OKJgvbnIVp0grfC0eKRJTb7EAuhfBTNcBflqqnJ4SydudGUuJdu1S9mkOrdZZ9RC+S5FMN6V70bacipBvo7zvsRrn3R0+sOKOwh+QmIphwO5s3rAsR2fp3aXbd6iuUE6mxiQRe6uyuEQGivU7ddTByFjJuHe041DfrXfbqjIbUEBqCKgp4QAX6b5x0ZVCzwBtXWxAGxi6F7XohTDzmvhUyWzF9tTTTsU5Q/4NZpeK6IjNfvS9a7hieYGCmld11VFUqm6zqUILHNS3FqRU50brGP5Wa1wC1j8eLAgWkBIFROyRPl97yRLbS2gSpjvUQyTVUyu+ihFSP629chJe8f9/I1OQTG6jg8tfljzYon/X9f4QzhXZjvjHhg67RVONHi7xvyqUUU+OU3ORm2JtpyPvAxX+buusGgtUcSsp8KiC+KeUQ3b/ENCcy1C0r1lW/gcmAezpS9gRVhkSUka3yzwFskW6Ore7rkbqd1JKPbBQ2Xpw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1Tij3CB7quMuvUFGvWAJ+aSdPMqk6isZFGHGWcOhq/VVeH5M2XE5pEiMyX+Ks9cXxTBfNd8C1IbDEHuvL4AJl7ixBI4RzsHD6iYS/35rBANW4O9Iv1rxHlr2FpyM47BDmH46R3QNjNZa2jYrbyjAE6s94ivuly8uh3K4NWkeTdIGnJjuYFFzBroTbZ06IXfR/k1Exm2+U6vqzVLUvGLmUl2MLwbMBnhL2GyFgqkZwnJNZD7N3qisnTcjK0fUA3cKmITqrNIAmTHQztUrlsPUtioHIrdcSZtjA68hVIpYuLuVkGpgIYTrb21Kxwuiv4t9+Al5ZqiXbqrA9ngqBjuMF5tAVk2xRpFTcypah+Auwh9zhxq4VmFxDNAwC2svtmL+zYHeQ6MU2GJKpsulnA8l+Z4QfKxv9rzkIFBX4Li1d+x34VFlFti/HWhpGl3mOkRxGOs6oou92OW8GITiavOoFdSKvXlWrYBgKINKwLCe0SGfslYyZP1VHkl4n5X57BCpthbXNBz0JDN3vzaI4o+LT+eJrnZLzScZrzOD1BwvtBrdFTjcWXHsgooBFhsUjQHKSCaqQOVk6Jrl3KSfrT/JyDG0kK8ujn0o+dIW64w/Y6+sbprXagaiz8fdYq9Gu1hIe0XM+dSkiv2IEuKY4tKJgiDDY8eAU8/6HdYlzPZKUdKtqaLVJueUzvDnXO7r43whFaN2y8hW+FnwrCIYitrEoFzs7N5f7XEH9++cvbiF9oWtw3qljRRoGH/rjF5/K0Vhfg4Tn2AZ4+TrhY3e+vSJp0ecitILGR8S/eDxlUmJf79n7RajakZ6Zif/szpMsbkhAySJiLlxpoSxUHS88vBQw9E2KoHg76ukxhR3JwCX8KmYGyBrtZ+AoIfYls2PAY+KRu/uCYLVkZcWi/nZ4ZFJmDGhvL2AZ0W0Kh429BlAKBhPon7HayF5OUOa+jqNGYFcXU8Od1K21pX0+OYJj3Ij7o611IV2laOgTN/n1oAVYDIcaxMuEOMN3QRbIc+cpQC+gcRAHDv6ErVoC2vjdFqhWotqjaKxKMlPrpspW/cKJk2FIQLWT/TJtLdLeF7KQJX+PX4p8MuSeWzla8AUxjhNzlwsoGGjPj6nNQ/kOcSaNQDaEQvIDvvArDgi7OFe8tgzDeD0ZOx/v6PyhjyOtCm7TzMbG3DFufwz+ZOFrROD659Jjs5GzpIDCeIcHJzJcxewNASHpr5lOhac/wWtvZ1DlyUO7L6N59M4MfR90cvqmMaJiRhl9X9B/GN4r1XsKnDgs4ulvnJPOuFfSZJMeRAp2WP0gUX5z57a2erF6BqQ5vGoYIb34Vz5pfVXpTtUoKXa X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f70d0a6-4c6c-45a3-3b39-08d931a970e5 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:26.4384 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: J7sO13E117j22785IvH+3S/A+82cUGQcfHg23hwC0a4jLSqVi8c6XrnawgGqYnbRxgMFeV/ZDqsR/VKt3DiTmg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/coredump.c | 190 ++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/coredump.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/coredump.c b/drivers/net/wireless/celeno/cl8k/coredump.c new file mode 100644 index 000000000000..bf0313715f6f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/coredump.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "coredump.h" +#include "recovery.h" +#include "mib.h" +#include "ela.h" +#ifdef CONFIG_CL_PCIE +#include "bus/pci/ipc.h" +#endif +#include "chip.h" +#include "config.h" + +#include "fw/fw_dbg.h" + +#include + +static int cl_coredump_generate(struct cl_hw *cl_hw) +{ + struct cl_coredump *dump; + + dump = cl_fw_dbg_prepare_coredump(cl_hw); + if (!dump) + return -ENODATA; + + dev_coredumpv(cl_hw->chip->dev, dump, le32_to_cpu(dump->len), + GFP_KERNEL); + + return 0; +} + +static void cl_coredump_done(struct cl_hw *cl_hw) +{ + /* + * Print MIB counters only if watchdog is disabled, + * otherwise the dump of prints effects the recovery + */ + if (cl_hw->conf->ce_fw_watchdog_mode == FW_WD_DISABLE) + cl_mib_cntrs_dump(cl_hw); + + if (!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags)) + return; + + /* + * Assuming firmware cannot request next dump before we release the host buffer + * so no need to sync the following against error_ind() + */ + cl_hw->debugfs.trace_prst = false; +#ifdef CONFIG_CL_PCIE + cl_ipc_dbginfobuf_push(cl_hw->ipc_env, cl_hw->dbginfo.dma_addr); +#endif + if (cl_hw->dbginfo.buf->u.dump.general_data.error_type == DBG_ERROR_FATAL || + cl_hw->assert_info.restart_needed) { + cl_dbg_err(cl_hw, "Starting recovery due to unrecoverable assert\n"); + cl_recovery_start(cl_hw, RECOVERY_UNRECOVERABLE_ASSERT); + } +} + +static void cl_coredump_work(struct work_struct *ws) +{ + struct cl_debugfs *debugfs = container_of(ws, struct cl_debugfs, coredump_work); + struct cl_hw *cl_hw = container_of(debugfs, struct cl_hw, debugfs); + unsigned long flags; + + debugfs->coredump_call_tstamp = jiffies; + + cl_coredump_generate(cl_hw); + if (cl_ela_is_on(cl_hw->chip)) { + cl_ela_lcu_reset(cl_hw->chip); + cl_ela_lcu_apply_config(cl_hw->chip); + } + + spin_lock_irqsave(&debugfs->coredump_lock, flags); + if (!debugfs->unregistering) + cl_coredump_done(cl_hw); + debugfs->coredump_scheduled = false; + spin_unlock_irqrestore(&debugfs->coredump_lock, flags); +} + +int cl_coredump_trigger(struct cl_hw *cl_hw) +{ + struct cl_debugfs *debugfs = &cl_hw->debugfs; + unsigned long flags; + unsigned long curr_time = jiffies; + unsigned int diff_time = jiffies_to_msecs(curr_time - debugfs->coredump_call_tstamp); + + if (diff_time < cl_hw->conf->ci_coredump_diff_time_ms) { +#ifdef CONFIG_CL_PCIE + cl_ipc_dbginfobuf_push(cl_hw->ipc_env, cl_hw->dbginfo.dma_addr); +#endif + cl_dbg_verbose(cl_hw, + "Skip coredump - time from previous call=%u m-sec\n", + diff_time); + return -1; + } + + spin_lock_irqsave(&debugfs->coredump_lock, flags); + if (debugfs->coredump_scheduled) { + spin_unlock_irqrestore(&debugfs->coredump_lock, flags); + cl_dbg_verbose(cl_hw, ": Already scheduled\n"); + return -EBUSY; + } + + if (debugfs->unregistering) { + spin_unlock_irqrestore(&debugfs->coredump_lock, flags); + cl_dbg_verbose(cl_hw, ": unregistering\n"); + return -ENOENT; + } + + debugfs->coredump_scheduled = true; + debugfs->trace_prst = true; + ktime_get_real_ts64(&cl_hw->dbginfo.trigger_tstamp); + + schedule_work(&debugfs->coredump_work); + spin_unlock_irqrestore(&debugfs->coredump_lock, flags); + + return 0; +} + +bool cl_coredump_recovery(struct cl_hw *cl_hw, int reason) +{ + struct cl_debugfs *debugfs = &cl_hw->debugfs; + unsigned long flags; + bool need_restart = false; + + spin_lock_irqsave(&debugfs->coredump_lock, flags); + + if (!debugfs->coredump_scheduled) { + cl_dbg_trace(cl_hw, + "Starting recovery due to reason:%d\n", + reason); + cl_recovery_start(cl_hw, reason); + } else { + need_restart = true; + } + + spin_unlock_irqrestore(&debugfs->coredump_lock, flags); + + return need_restart; +} + +bool cl_coredump_is_scheduled(struct cl_hw *cl_hw) +{ + struct cl_debugfs *debugfs = &cl_hw->debugfs; + + return debugfs->coredump_scheduled; +} + +void cl_coredump_reset_trace(struct cl_hw *cl_hw) +{ + struct cl_debugfs *debugfs = &cl_hw->debugfs; + + debugfs->trace_prst = false; +} + +void cl_coredump_init(struct cl_hw *cl_hw, struct dentry *dir_drv) +{ + struct cl_debugfs *debugfs = &cl_hw->debugfs; + + debugfs->dir = dir_drv; + debugfs->unregistering = false; + debugfs->trace_prst = false; + debugfs->coredump_scheduled = false; + + INIT_WORK(&debugfs->coredump_work, cl_coredump_work); + + spin_lock_init(&debugfs->coredump_lock); + + /* + * Initialize coredump_call_tstamp to current time minus + * (ci_coredump_diff_time_ms + 1), so that if assert happens immediately + * coredump will be called. + */ + debugfs->coredump_call_tstamp = jiffies - + msecs_to_jiffies(cl_hw->conf->ci_coredump_diff_time_ms + 1); +} + +void cl_coredump_close(struct cl_hw *cl_hw) +{ + struct cl_debugfs *debugfs = &cl_hw->debugfs; + + flush_work(&debugfs->coredump_work); + + if (!debugfs->dir) + return; + + debugfs->unregistering = true; + debugfs_remove_recursive(debugfs->dir); + debugfs->dir = NULL; +} From patchwork Thu Jun 17 15:58:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33F83C2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 050/256] cl8k: add data_rates.c Date: Thu, 17 Jun 2021 15:58:57 +0000 Message-Id: <20210617160223.160998-51-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9836b8a5-58e5-497b-dd49-08d931a97243 X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1850; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lhsug7LJ1vyJl9YvMKqjKojYsl6EvOIHgq9k1fN27VHUhJatQeyvgHU9PwQ5PwYRJsojX1DlDjtK7JsN1qnZy12ul3wAZkdNBcIx5RHExudfOFcB0vcQ6G+F3dsFnJLJJEypXCqVaF81fF2+P17+Fjp05+taW5bUfxwy4xTGD0FXTQe2Bmlh3IAgrE3WQmJ/8NOD+yyDh/wpKkhDE0jX3gostmZxNrXAACs4VsKjokkxXo9eeNdt5oylcAVVM7hVbyISzCQMglGsSS+SFKeMaZ1C6YvnqXFmOCUzYSpLzy8YApP4Cm6MOLvYfz7HNQC46751CYKHw6PVEGKpKsij+QauEFPX9o9NyiWN2W0D1nl738Be1kmV14Lne7KEcUesf+s5tSgNEwVA6lzf9Gycv4N1FwZxykS1QfgQDZ70ypg3X4LkCQfRkvrVzUrdTuEfCGazQuBuMLZOh6tN/H8JZBeAM2y8em1+yCb8QgIacKZ54ormSRxeY0x13PVktmgJbLiJKtHEfiiXnzNted8hgHjEApamqehwu4tCX270UgRTUzPfowTXmG93F7iLhXgGi2QYiYxTIg38RHz6XNLtvIcnfVE/rI7e+S1KrgidRPS0l787w3dqYhmQawgfmya0EBw/m7Q+ZJJQuMvP2WT1hwNSScPKjf3WJODmxJbEepahwYf1c2iGW1SSUBXfdJvUAF/rejf7Now1Ix/J/0jb+A== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(30864003)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001)(579004)(559001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Jfeyf2ZE1N8fCNd/Gs835/vWTX2r7pgmupI4MNVZ4am6BGlqoB4LBMOT5IwkWgC5ULozr7yqvokLtg5aZp8ZszVOvVcFxzxEUC7XcgnPlRKPb9BP1lYIiPvXZ7rclDDrLRPosVjGVX5iVqhdqvhbhVWyOXtiUh8LvN8I5YWNz15bMRNYiwsrcqPKdfrclFb9taUg8zgivYpUrHnjKFNrgW3kN7czmcNL+tP0/bh1eia18ap/zR7cJN1RnffY4aGf/hg+kgFr5GvwtImJ411LrySgheNG/ji+Uvn1tuULBsgHOUT9bnfUEdLGkJhm01T5xV1jJpKzBcHAbMd+Ghla0R83nWec33BItjNk8AdFT8/mwtlB+98tgH7VnNchuRGghwPZV3BhJIzyPFbAFGu9lcA2Be9Ku/y0MUB4BZBlRrJnP9vKgcLhz324hp5eNw2tX6aoV228LU49VK7/tR+YBL8a118hqYKc6B7ZoexFfRYJb4rQghj8hFMeT81QF5UOuSxzrBd5MC2mPVF0Yx7cFqx5yGtXsASaBd4eOhsIss6IhyTmsfR334q2mrzMtJin5cNMd/qN81e2ubgF9l2Rj+npm/Cc2PJEgydadv2afUlbTdc16oLUIKzj62McDsSlX1IH81GVyoUuwAng3HLa1pZBrV3hq3fuCvxgFHWbH9wqK/iiuo8mKr7XR1Mt8aHqKox3Lifotpyg0SLcbbSww9siFtBxdWoxhC8fKmcl0w9FZGImGwLhuVRu0c/CqDpkhXqHwEwM9aa6kjTAltjtQc/rUSFdk3hz42/Qnvmg/Ht040LZIpV/950uxi0TmtKrplujo15pDLgZlKzGlLwxNTx1GbFyBaQ7n4jTJxCPCXqIvuFqov6BwTgOpIIfUNaB5fg5dzC5LBCzYr88DSjjIKSIEZNvCesnohGSIBZanpLCChD8mzqamQxebMZR+sEfOEqhxlJptTQRDxg81/+vlx7+z9oKNj1C4UeTfmntyOTRoWSazAFaD8ApsBlE5J2tvW+gzQ5+qazxkZUmcbNmz0UH+cO24pLth+iHNyRtEnn86e5Y8YpX/MWPlj3kQ+Q83BGB3zcyf9HXdXQeRYiop47Py9DYmzPQVp1bJhOTTC4WplaKdrxBJiF+XSNECiL+bS9TVX49JSreJ5jDkOjso3IiRIRJOr7KucNhgIopUHni4f9Yr/f4isotwCz2eYV7JYLJBhcao//y8vj0KFe7NRl9WsA98IbRQiUPUv5V9yn+8ebQDKhLfITiNvXh0qaRUTkGuuKUNhY3lYHjxKBKEo+t+d4bZsBgEKPsLUzFtBk34tX66R0HL8989JGdS7ww X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9836b8a5-58e5-497b-dd49-08d931a97243 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:28.9952 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: REF6u/bgV4FvorwxBsqjjAlX2oLrQMXCV0HCEG6ldwcy0pHZFuKDEnHnyINcvoCVZamwI5sBGwfsuW7/4n9N0w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/data_rates.c | 1019 +++++++++++++++++ 1 file changed, 1019 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/data_rates.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/data_rates.c b/drivers/net/wireless/celeno/cl8k/data_rates.c new file mode 100644 index 000000000000..64c02b9385c1 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/data_rates.c @@ -0,0 +1,1019 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "data_rates.h" + +/* + * This table of rates was taken from IEEE 802.11ax Draft v3.3, 28.5. Parameters + * for HE-HE_MCSs. The units are 1/10 Mbs. Note that we don't support DCM, so it is + * not taken into account in this table. + */ +const u16 data_rate_he_x10[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE] = { + [CHNL_BW_20][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 73, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 81, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_0][WRS_GI_VSHORT] = 86, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 146, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 163, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_1][WRS_GI_VSHORT] = 172, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 219, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 244, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_2][WRS_GI_VSHORT] = 258, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 293, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 325, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_3][WRS_GI_VSHORT] = 344, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 439, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 488, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_4][WRS_GI_VSHORT] = 516, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 585, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 650, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_5][WRS_GI_VSHORT] = 688, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 658, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 731, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_6][WRS_GI_VSHORT] = 774, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 731, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 813, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_7][WRS_GI_VSHORT] = 860, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 878, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 975, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_8][WRS_GI_VSHORT] = 1032, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 975, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 1083, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_9][WRS_GI_VSHORT] = 1147, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_10][WRS_GI_LONG] = 1097, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_10][WRS_GI_SHORT] = 1219, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_10][WRS_GI_VSHORT] = 1290, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_11][WRS_GI_LONG] = 1219, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_11][WRS_GI_SHORT] = 1354, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_11][WRS_GI_VSHORT] = 1434, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 146, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 163, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_0][WRS_GI_VSHORT] = 172, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 293, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 325, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_1][WRS_GI_VSHORT] = 344, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 439, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 488, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_2][WRS_GI_VSHORT] = 516, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 585, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 650, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_3][WRS_GI_VSHORT] = 688, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 878, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 975, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_4][WRS_GI_VSHORT] = 1032, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 1170, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 1300, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_5][WRS_GI_VSHORT] = 1376, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 1316, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 1463, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_6][WRS_GI_VSHORT] = 1549, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 1463, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 1625, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_7][WRS_GI_VSHORT] = 1721, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 1755, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 1950, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_8][WRS_GI_VSHORT] = 2065, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 1950, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 2167, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_9][WRS_GI_VSHORT] = 2294, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_10][WRS_GI_LONG] = 2194, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_10][WRS_GI_SHORT] = 2438, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_10][WRS_GI_VSHORT] = 2581, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_11][WRS_GI_LONG] = 2438, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_11][WRS_GI_SHORT] = 2708, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_11][WRS_GI_VSHORT] = 2868, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 219, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 244, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_0][WRS_GI_VSHORT] = 258, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 439, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 488, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_1][WRS_GI_VSHORT] = 516, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 658, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 731, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_2][WRS_GI_VSHORT] = 774, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 878, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 975, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_3][WRS_GI_VSHORT] = 1032, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 1316, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 1463, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_4][WRS_GI_VSHORT] = 1549, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 1755, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 1950, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_5][WRS_GI_VSHORT] = 2065, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 1974, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 2194, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_6][WRS_GI_VSHORT] = 2323, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 2194, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 2438, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_7][WRS_GI_VSHORT] = 2581, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 2633, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 2925, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_8][WRS_GI_VSHORT] = 3097, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 2925, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 3250, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_9][WRS_GI_VSHORT] = 3441, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_10][WRS_GI_LONG] = 3291, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_10][WRS_GI_SHORT] = 3656, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_10][WRS_GI_VSHORT] = 3871, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_11][WRS_GI_LONG] = 3656, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_11][WRS_GI_SHORT] = 4063, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_11][WRS_GI_VSHORT] = 4301, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 293, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 325, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_0][WRS_GI_VSHORT] = 344, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 585, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 650, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_1][WRS_GI_VSHORT] = 688, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 878, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 975, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_2][WRS_GI_VSHORT] = 1032, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 1170, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 1300, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_3][WRS_GI_VSHORT] = 1376, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 1755, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 1950, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_4][WRS_GI_VSHORT] = 2065, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 2340, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 2600, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_5][WRS_GI_VSHORT] = 2753, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 2633, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 2925, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_6][WRS_GI_VSHORT] = 3097, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 2925, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 3250, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_7][WRS_GI_VSHORT] = 3441, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 3510, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 3900, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_8][WRS_GI_VSHORT] = 4129, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 3900, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 4333, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_9][WRS_GI_VSHORT] = 4588, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_10][WRS_GI_LONG] = 4388, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_10][WRS_GI_SHORT] = 4875, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_10][WRS_GI_VSHORT] = 5162, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_11][WRS_GI_LONG] = 4875, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_11][WRS_GI_SHORT] = 5417, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_11][WRS_GI_VSHORT] = 5735, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 146, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 163, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_0][WRS_GI_VSHORT] = 172, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 293, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 325, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_1][WRS_GI_VSHORT] = 344, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 439, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 488, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_2][WRS_GI_VSHORT] = 516, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 585, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 650, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_3][WRS_GI_VSHORT] = 688, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 878, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 975, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_4][WRS_GI_VSHORT] = 1032, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 1170, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 1300, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_5][WRS_GI_VSHORT] = 1376, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 1316, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 1463, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_6][WRS_GI_VSHORT] = 1549, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 1463, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 1625, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_7][WRS_GI_VSHORT] = 1721, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 1755, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 1950, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_8][WRS_GI_VSHORT] = 2065, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 1950, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 2167, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_9][WRS_GI_VSHORT] = 2294, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_10][WRS_GI_LONG] = 2194, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_10][WRS_GI_SHORT] = 2438, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_10][WRS_GI_VSHORT] = 2581, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_11][WRS_GI_LONG] = 2438, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_11][WRS_GI_SHORT] = 2708, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_11][WRS_GI_VSHORT] = 2868, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 293, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 325, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_0][WRS_GI_VSHORT] = 344, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 585, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 650, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_1][WRS_GI_VSHORT] = 688, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 878, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 975, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_2][WRS_GI_VSHORT] = 1032, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 1170, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 1300, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_3][WRS_GI_VSHORT] = 1376, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 1755, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 1950, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_4][WRS_GI_VSHORT] = 2065, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 2340, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 2600, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_5][WRS_GI_VSHORT] = 2753, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 2633, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 2925, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_6][WRS_GI_VSHORT] = 3097, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 2925, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 3250, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_7][WRS_GI_VSHORT] = 3441, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 3510, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 3900, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_8][WRS_GI_VSHORT] = 4129, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 3900, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 4333, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_9][WRS_GI_VSHORT] = 4588, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_10][WRS_GI_LONG] = 4388, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_10][WRS_GI_SHORT] = 4875, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_10][WRS_GI_VSHORT] = 5162, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_11][WRS_GI_LONG] = 4875, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_11][WRS_GI_SHORT] = 5417, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_11][WRS_GI_VSHORT] = 5735, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 439, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 488, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_0][WRS_GI_VSHORT] = 516, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 878, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 975, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_1][WRS_GI_VSHORT] = 1032, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 1316, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 1463, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_2][WRS_GI_VSHORT] = 1549, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 1755, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 1950, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_3][WRS_GI_VSHORT] = 2065, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 2633, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 2925, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_4][WRS_GI_VSHORT] = 3097, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 3510, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 3900, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_5][WRS_GI_VSHORT] = 4129, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 3949, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 4388, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_6][WRS_GI_VSHORT] = 4646, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 4388, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 4875, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_7][WRS_GI_VSHORT] = 5162, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 5265, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 5850, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_8][WRS_GI_VSHORT] = 6194, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 5850, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 6500, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_9][WRS_GI_VSHORT] = 6882, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_10][WRS_GI_LONG] = 6581, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_10][WRS_GI_SHORT] = 7313, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_10][WRS_GI_VSHORT] = 7743, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_11][WRS_GI_LONG] = 7313, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_11][WRS_GI_SHORT] = 8125, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_11][WRS_GI_VSHORT] = 8603, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 585, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 650, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_0][WRS_GI_VSHORT] = 688, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 1170, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 1300, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_1][WRS_GI_VSHORT] = 1376, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 1755, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 1950, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_2][WRS_GI_VSHORT] = 2065, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 2340, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 2600, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_3][WRS_GI_VSHORT] = 2753, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 3510, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 3900, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_4][WRS_GI_VSHORT] = 4129, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 4680, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 5200, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_5][WRS_GI_VSHORT] = 5506, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 5265, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 5850, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_6][WRS_GI_VSHORT] = 6194, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 5850, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 6500, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_7][WRS_GI_VSHORT] = 6882, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 7020, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 7800, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_8][WRS_GI_VSHORT] = 8259, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 7800, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 8667, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_9][WRS_GI_VSHORT] = 9176, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_10][WRS_GI_LONG] = 8775, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_10][WRS_GI_SHORT] = 9750, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_10][WRS_GI_VSHORT] = 10324, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_11][WRS_GI_LONG] = 9750, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_11][WRS_GI_SHORT] = 10833, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_11][WRS_GI_VSHORT] = 11471, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 306, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 340, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_0][WRS_GI_VSHORT] = 360, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 613, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 681, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_1][WRS_GI_VSHORT] = 721, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 919, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 1021, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_2][WRS_GI_VSHORT] = 1081, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 1225, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 1361, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_3][WRS_GI_VSHORT] = 1441, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 1838, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 2042, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_4][WRS_GI_VSHORT] = 2162, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 2450, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 2722, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_5][WRS_GI_VSHORT] = 2882, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 2756, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 3063, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_6][WRS_GI_VSHORT] = 3243, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 3063, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 3403, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_7][WRS_GI_VSHORT] = 3603, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 3675, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 4083, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_8][WRS_GI_VSHORT] = 4324, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 4083, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 4537, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_9][WRS_GI_VSHORT] = 4804, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_10][WRS_GI_LONG] = 4594, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_10][WRS_GI_SHORT] = 5104, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_10][WRS_GI_VSHORT] = 5404, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_11][WRS_GI_LONG] = 5104, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_11][WRS_GI_SHORT] = 5671, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_11][WRS_GI_VSHORT] = 6004, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 613, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 681, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_0][WRS_GI_VSHORT] = 721, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 1225, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 1361, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_1][WRS_GI_VSHORT] = 1441, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 1838, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 2042, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_2][WRS_GI_VSHORT] = 2162, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 2450, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 2722, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_3][WRS_GI_VSHORT] = 2882, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 3675, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 4083, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_4][WRS_GI_VSHORT] = 4324, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 4900, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 5444, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_5][WRS_GI_VSHORT] = 5765, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 5513, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 6125, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_6][WRS_GI_VSHORT] = 6485, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 6125, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 6806, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_7][WRS_GI_VSHORT] = 7206, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 7350, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 8167, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_8][WRS_GI_VSHORT] = 8647, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 8166, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 9074, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_9][WRS_GI_VSHORT] = 9607, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_10][WRS_GI_LONG] = 9188, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_10][WRS_GI_SHORT] = 10208, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_10][WRS_GI_VSHORT] = 10809, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_11][WRS_GI_LONG] = 10208, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_11][WRS_GI_SHORT] = 11343, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_11][WRS_GI_VSHORT] = 12010, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 919, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 1021, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_0][WRS_GI_VSHORT] = 1081, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 1838, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 2042, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_1][WRS_GI_VSHORT] = 2162, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 2756, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 3063, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_2][WRS_GI_VSHORT] = 3243, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 3675, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 4083, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_3][WRS_GI_VSHORT] = 4324, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 5513, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 6125, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_4][WRS_GI_VSHORT] = 6485, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 7350, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 8167, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_5][WRS_GI_VSHORT] = 8647, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 8269, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 9188, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_6][WRS_GI_VSHORT] = 9728, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 9188, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 10208, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_7][WRS_GI_VSHORT] = 10809, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 11025, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 12250, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_8][WRS_GI_VSHORT] = 12971, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 12250, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 13611, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_9][WRS_GI_VSHORT] = 14412, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_10][WRS_GI_LONG] = 13781, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_10][WRS_GI_SHORT] = 15313, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_10][WRS_GI_VSHORT] = 16213, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_11][WRS_GI_LONG] = 15313, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_11][WRS_GI_SHORT] = 17014, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_11][WRS_GI_VSHORT] = 18015, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 1225, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 1361, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_0][WRS_GI_VSHORT] = 1441, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 2450, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 2722, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_1][WRS_GI_VSHORT] = 2882, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 3675, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 4083, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_2][WRS_GI_VSHORT] = 4324, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 4900, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 5444, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_3][WRS_GI_VSHORT] = 5765, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 7350, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 8167, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_4][WRS_GI_VSHORT] = 8647, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 9800, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 10889, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_5][WRS_GI_VSHORT] = 11529, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 11025, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 12250, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_6][WRS_GI_VSHORT] = 12971, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 12250, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 13611, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_7][WRS_GI_VSHORT] = 14412, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 14700, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 16333, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_8][WRS_GI_VSHORT] = 17294, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 16333, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 18148, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_9][WRS_GI_VSHORT] = 19215, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_10][WRS_GI_LONG] = 18375, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_10][WRS_GI_SHORT] = 20417, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_10][WRS_GI_VSHORT] = 21618, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_11][WRS_GI_LONG] = 20416, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_11][WRS_GI_SHORT] = 22685, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_11][WRS_GI_VSHORT] = 24019, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 613, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 681, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_0][WRS_GI_VSHORT] = 721, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 1225, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 1361, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_1][WRS_GI_VSHORT] = 1441, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 1838, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 2042, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_2][WRS_GI_VSHORT] = 2162, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 2450, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 2722, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_3][WRS_GI_VSHORT] = 2882, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 3675, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 4083, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_4][WRS_GI_VSHORT] = 4324, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 4900, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 5444, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_5][WRS_GI_VSHORT] = 5765, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 5513, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 6125, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_6][WRS_GI_VSHORT] = 6485, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 6125, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 6806, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_7][WRS_GI_VSHORT] = 7206, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 7350, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 8167, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_8][WRS_GI_VSHORT] = 8647, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 8166, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 9074, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_9][WRS_GI_VSHORT] = 9607, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_10][WRS_GI_LONG] = 9188, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_10][WRS_GI_SHORT] = 10208, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_10][WRS_GI_VSHORT] = 10809, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_11][WRS_GI_LONG] = 10208, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_11][WRS_GI_SHORT] = 11342, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_11][WRS_GI_VSHORT] = 12010, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 1225, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 1361, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_0][WRS_GI_VSHORT] = 1441, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 2450, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 2722, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_1][WRS_GI_VSHORT] = 2882, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 3675, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 4083, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_2][WRS_GI_VSHORT] = 4324, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 4900, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 5444, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_3][WRS_GI_VSHORT] = 5765, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 7350, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 8167, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_4][WRS_GI_VSHORT] = 8647, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 9800, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 10889, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_5][WRS_GI_VSHORT] = 11529, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 11025, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 12250, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_6][WRS_GI_VSHORT] = 12971, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 12250, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 13611, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_7][WRS_GI_VSHORT] = 14412, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 14700, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 16333, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_8][WRS_GI_VSHORT] = 17294, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 16333, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 18148, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_9][WRS_GI_VSHORT] = 19215, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_10][WRS_GI_LONG] = 18375, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_10][WRS_GI_SHORT] = 20417, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_10][WRS_GI_VSHORT] = 21618, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_11][WRS_GI_LONG] = 20416, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_11][WRS_GI_SHORT] = 22685, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_11][WRS_GI_VSHORT] = 24019, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 1838, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 2042, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_0][WRS_GI_VSHORT] = 2162, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 3675, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 4083, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_1][WRS_GI_VSHORT] = 4324, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 5513, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 6125, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_2][WRS_GI_VSHORT] = 6485, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 7350, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 8167, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_3][WRS_GI_VSHORT] = 8647, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 11025, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 12250, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_4][WRS_GI_VSHORT] = 12971, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 14700, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 16333, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_5][WRS_GI_VSHORT] = 17294, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 16538, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 18375, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_6][WRS_GI_VSHORT] = 19456, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 18375, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 20417, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_7][WRS_GI_VSHORT] = 21618, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 22050, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 24500, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_8][WRS_GI_VSHORT] = 25941, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 24500, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 27222, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_9][WRS_GI_VSHORT] = 28824, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_10][WRS_GI_LONG] = 27563, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_10][WRS_GI_SHORT] = 30625, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_10][WRS_GI_VSHORT] = 32426, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_11][WRS_GI_LONG] = 30625, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_11][WRS_GI_SHORT] = 34028, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_11][WRS_GI_VSHORT] = 36029, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 2450, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 2722, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_0][WRS_GI_VSHORT] = 2882, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 4900, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 5444, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_1][WRS_GI_VSHORT] = 5765, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 7350, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 8167, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_2][WRS_GI_VSHORT] = 8647, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 9800, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 10889, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_3][WRS_GI_VSHORT] = 11529, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 14700, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 16333, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_4][WRS_GI_VSHORT] = 17294, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 19600, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 21778, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_5][WRS_GI_VSHORT] = 23059, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 22050, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 24500, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_6][WRS_GI_VSHORT] = 25941, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 24500, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 27222, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_7][WRS_GI_VSHORT] = 28824, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 29400, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 32667, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_8][WRS_GI_VSHORT] = 34588, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 32666, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 36296, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_9][WRS_GI_VSHORT] = 38431, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_10][WRS_GI_LONG] = 36750, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_10][WRS_GI_SHORT] = 40833, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_10][WRS_GI_VSHORT] = 43235, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_11][WRS_GI_LONG] = 40833, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_11][WRS_GI_SHORT] = 45370, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_11][WRS_GI_VSHORT] = 48039, +}; + +/* + * This table of rates was taken from IEEE Std 802.11TM-2016, 21.5 Parameters + * for VHT-MCSs. The units are 1/10 Mbs. Invalid combinations are with 0's. Note + * that HT data rates are a subset of VHT data rates, so we can use a single + * table for both. + */ +const u16 data_rate_ht_vht_x10[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX_VHT][WRS_GI_MAX_VHT] = { + [CHNL_BW_20][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 65, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 72, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 130, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 144, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 195, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 217, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 260, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 289, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 390, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 433, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 520, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 578, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 585, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 650, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 650, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 722, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 780, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 867, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 0, + [CHNL_BW_20][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 0, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 130, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 144, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 260, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 289, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 390, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 433, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 520, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 578, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 780, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 867, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 1040, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 1156, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 1170, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 1303, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 1300, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 1444, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 1560, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 1733, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 0, + [CHNL_BW_20][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 0, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 195, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 217, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 390, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 433, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 585, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 650, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 780, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 867, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 1170, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 1300, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 1560, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 1733, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 1755, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 1950, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 1950, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 2167, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 2340, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 2600, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 2600, + [CHNL_BW_20][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 2889, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 260, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 288, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 520, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 576, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 780, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 868, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 1040, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 1156, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 1560, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 1732, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 2080, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 2312, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 2340, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 2600, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 2600, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 2888, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 3120, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 3468, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 0, + [CHNL_BW_20][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 0, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 135, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 150, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 270, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 300, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 405, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 450, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 540, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 600, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 810, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 900, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 1080, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 1200, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 1215, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 1350, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 1350, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 1500, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 1620, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 1800, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 1800, + [CHNL_BW_40][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 2000, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 270, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 300, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 540, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 600, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 810, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 900, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 1080, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 1200, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 1620, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 1800, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 2160, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 2400, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 2430, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 2700, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 2700, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 3000, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 3240, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 3600, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 3600, + [CHNL_BW_40][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 4000, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 405, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 450, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 810, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 900, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 1215, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 1350, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 1620, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 1800, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 2430, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 2700, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 3240, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 3600, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 3645, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 4050, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 4050, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 4500, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 4860, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 5400, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 5400, + [CHNL_BW_40][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 6000, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 540, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 600, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 1080, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 1200, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 1620, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 1800, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 2160, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 2400, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 3240, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 3600, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 4320, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 4800, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 4860, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 5400, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 5400, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 6000, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 6480, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 7200, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 7200, + [CHNL_BW_40][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 8000, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 293, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 325, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 585, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 650, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 878, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 975, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 1170, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 1300, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 1755, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 1950, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 2340, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 2600, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 2633, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 2925, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 2925, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 3250, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 3510, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 3900, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 3900, + [CHNL_BW_80][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 4333, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 585, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 650, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 1170, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 1300, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 1755, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 1950, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 2340, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 2600, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 3510, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 3900, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 4680, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 5200, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 5265, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 5850, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 5850, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 6500, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 7020, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 7800, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 7800, + [CHNL_BW_80][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 8667, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 878, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 975, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 1755, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 1950, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 2633, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 2925, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 3510, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 3900, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 5265, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 5850, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 7020, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 7800, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 0, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 0, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 8775, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 9750, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 10530, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 11700, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 11700, + [CHNL_BW_80][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 13000, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 1172, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 1300, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 2340, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 2600, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 3512, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 3900, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 4680, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 5200, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 7020, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 7800, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 9360, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 10400, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 10532, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 11700, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 11700, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 13000, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 14040, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 15600, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 15600, + [CHNL_BW_80][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 17332, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_0][WRS_GI_LONG] = 585, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_0][WRS_GI_SHORT] = 650, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_1][WRS_GI_LONG] = 1170, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_1][WRS_GI_SHORT] = 1300, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_2][WRS_GI_LONG] = 1755, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_2][WRS_GI_SHORT] = 1950, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_3][WRS_GI_LONG] = 2340, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_3][WRS_GI_SHORT] = 2600, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_4][WRS_GI_LONG] = 3510, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_4][WRS_GI_SHORT] = 3900, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_5][WRS_GI_LONG] = 4680, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_5][WRS_GI_SHORT] = 5200, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_6][WRS_GI_LONG] = 5265, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_6][WRS_GI_SHORT] = 5850, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_7][WRS_GI_LONG] = 5850, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_7][WRS_GI_SHORT] = 6500, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_8][WRS_GI_LONG] = 7020, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_8][WRS_GI_SHORT] = 7800, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_9][WRS_GI_LONG] = 7800, + [CHNL_BW_160][WRS_SS_1][WRS_MCS_9][WRS_GI_SHORT] = 8667, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_0][WRS_GI_LONG] = 1170, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_0][WRS_GI_SHORT] = 1300, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_1][WRS_GI_LONG] = 2340, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_1][WRS_GI_SHORT] = 2600, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_2][WRS_GI_LONG] = 3510, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_2][WRS_GI_SHORT] = 3900, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_3][WRS_GI_LONG] = 4680, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_3][WRS_GI_SHORT] = 5200, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_4][WRS_GI_LONG] = 7020, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_4][WRS_GI_SHORT] = 7800, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_5][WRS_GI_LONG] = 9360, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_5][WRS_GI_SHORT] = 10400, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_6][WRS_GI_LONG] = 10530, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_6][WRS_GI_SHORT] = 11700, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_7][WRS_GI_LONG] = 11700, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_7][WRS_GI_SHORT] = 13000, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_8][WRS_GI_LONG] = 14040, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_8][WRS_GI_SHORT] = 15600, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_9][WRS_GI_LONG] = 15600, + [CHNL_BW_160][WRS_SS_2][WRS_MCS_9][WRS_GI_SHORT] = 17333, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_0][WRS_GI_LONG] = 1755, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_0][WRS_GI_SHORT] = 1950, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_1][WRS_GI_LONG] = 3510, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_1][WRS_GI_SHORT] = 3900, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_2][WRS_GI_LONG] = 5265, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_2][WRS_GI_SHORT] = 5850, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_3][WRS_GI_LONG] = 7020, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_3][WRS_GI_SHORT] = 7800, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_4][WRS_GI_LONG] = 10530, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_4][WRS_GI_SHORT] = 11700, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_5][WRS_GI_LONG] = 14040, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_5][WRS_GI_SHORT] = 15600, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_6][WRS_GI_LONG] = 15795, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_6][WRS_GI_SHORT] = 17550, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_7][WRS_GI_LONG] = 17550, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_7][WRS_GI_SHORT] = 19500, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_8][WRS_GI_LONG] = 21060, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_8][WRS_GI_SHORT] = 23400, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_9][WRS_GI_LONG] = 0, + [CHNL_BW_160][WRS_SS_3][WRS_MCS_9][WRS_GI_SHORT] = 0, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_0][WRS_GI_LONG] = 2340, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_0][WRS_GI_SHORT] = 2600, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_1][WRS_GI_LONG] = 4680, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_1][WRS_GI_SHORT] = 5200, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_2][WRS_GI_LONG] = 7020, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_2][WRS_GI_SHORT] = 7800, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_3][WRS_GI_LONG] = 9360, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_3][WRS_GI_SHORT] = 10400, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_4][WRS_GI_LONG] = 10400, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_4][WRS_GI_SHORT] = 15600, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_5][WRS_GI_LONG] = 18720, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_5][WRS_GI_SHORT] = 20800, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_6][WRS_GI_LONG] = 21060, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_6][WRS_GI_SHORT] = 23400, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_7][WRS_GI_LONG] = 23400, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_7][WRS_GI_SHORT] = 26000, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_8][WRS_GI_LONG] = 28080, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_8][WRS_GI_SHORT] = 31200, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_9][WRS_GI_LONG] = 31200, + [CHNL_BW_160][WRS_SS_4][WRS_MCS_9][WRS_GI_SHORT] = 34667, +}; + +/* OFDM Data Rates - (multiplied by 10) */ +const u16 data_rate_ofdm_x10[] = { + 60, + 90, + 120, + 180, + 240, + 360, + 480, + 540, +}; + +/* CCK Data Rates - (multiplied by 10) */ +const u16 data_rate_cck_x10[] = { + 10, + 20, + 55, + 110, +}; + +struct cl_inverse_data_rate inverse_data_rate; + +static u16 cl_data_rates_inverse_he(u8 bw, u8 nss, u8 mcs, u8 gi) +{ + return (80 << DATA_RATE_INVERSE_Q) / data_rate_he_x10[bw][nss][mcs][gi]; +} + +static u16 cl_data_rates_inverse_vht(u8 bw, u8 nss, u8 mcs, u8 gi) +{ + u16 data_rate = data_rate_ht_vht_x10[bw][nss][mcs][gi]; + + if (data_rate) + return (80 << DATA_RATE_INVERSE_Q) / data_rate; + + return 0; +} + +static u16 cl_data_rates_inverse_ofdm(u8 mcs) +{ + return (80 << DATA_RATE_INVERSE_Q) / data_rate_ofdm_x10[mcs]; +} + +static u16 cl_data_rates_inverse_cck(u8 mcs) +{ + return (80 << DATA_RATE_INVERSE_Q) / data_rate_cck_x10[mcs]; +} + +void cl_data_rates_inverse_build(void) +{ + /* + * The calculation is: round((2^15[Q] * 8[bits] * 10)/rate[Mbps]) - unit (us * 2^15) + * multiply by 10 because data rates in the above tables are also multiplied by 10 + */ + u8 bw, nss, mcs, gi; + + for (bw = 0; bw < CHNL_BW_MAX; bw++) + for (nss = 0; nss < WRS_SS_MAX; nss++) { + /* HE */ + for (mcs = 0; mcs < WRS_MCS_MAX_HE; mcs++) + for (gi = 0; gi < WRS_GI_MAX_HE; gi++) + inverse_data_rate.he[bw][nss][mcs][gi] = + cl_data_rates_inverse_he(bw, nss, mcs, gi); + + /* VHT */ + for (mcs = 0; mcs < WRS_MCS_MAX_VHT; mcs++) + for (gi = 0; gi < WRS_GI_MAX_VHT; gi++) + inverse_data_rate.ht_vht[bw][nss][mcs][gi] = + cl_data_rates_inverse_vht(bw, nss, mcs, gi); + } + + /* OFDM */ + for (mcs = 0; mcs < WRS_MCS_MAX_OFDM; mcs++) + inverse_data_rate.ofdm[mcs] = cl_data_rates_inverse_ofdm(mcs); + + /* CCK */ + for (mcs = 0; mcs < WRS_MCS_MAX_CCK; mcs++) + inverse_data_rate.cck[mcs] = cl_data_rates_inverse_cck(mcs); +} + +u16 cl_data_rates_get(u8 mode, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + return cl_data_rates_get_x10(mode, bw, nss, mcs, gi) / 10; +} + +u16 cl_data_rates_get_x10(u8 mode, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + switch (mode) { + case WRS_MODE_HE: + return data_rate_he_x10[bw][nss][mcs][gi]; + case WRS_MODE_VHT: + case WRS_MODE_HT: + return data_rate_ht_vht_x10[bw][nss][mcs][gi]; + case WRS_MODE_OFDM: + return data_rate_ofdm_x10[mcs]; + case WRS_MODE_CCK: + return data_rate_cck_x10[mcs]; + default: + return 0; + } +} + From patchwork Thu Jun 17 15:58:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 051/256] cl8k: add data_rates.h Date: Thu, 17 Jun 2021 15:58:58 +0000 Message-Id: <20210617160223.160998-52-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:29 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e32cd5d6-1b56-4885-d798-08d931a97307 X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:813; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z9p1u2ZoNfQwDFBklSSYxkJkl0YqaUSJZpzkaOxHBSNi3WeLh6qauK7D2zfLDG1P/pSrA570ejORjAGZ7Z/8PT6nKVdim9XSy5wB8g7Dvy/f6KAg/m6FnFqKk+BO47ZaZhAPOtdSkQ0yfSczUZRND4YCPwYBacsbkVbg8CrcS8BJpjQw4vRidUsHnxW/Q1/j482w4A+JeAgG8oQ1NYa3Wh77djI1BwafZJEtnYDLdp8ApM+AEPrjlK8rCyjl18DUvJ0N1FO7hbsNbe2wiUKd7cBDClnFOTbG1pdwj3YOlbxMulS7VuSv43/b37SKm551Szfn23QaIa4nkbnQFshaAm0VXNvj9C9HitMDYOOdM4iLn/UzRzRNBTpOOR2prQtf8x3BaYdU8TtkpayRt1wcQ5Dn7WBgEWoX3RFs1XrnJuGtTdrVxPKgJOA0dkqGN43RMmt8SAieJ/296bL9AZ3NLtTHe+lf/ObfBnmXmYTq/ohFBvk3VNSGUZCRD8I7Bby4wR5HbQVS+Z0CKOdvXQe4JxdmFh4cxU+VzkCAtaNPRVg4jjYJHPYXY7QZdDtiT0c5/9gEbTF1gKmxVasE4lYZpx3kSA94cMPmBHsuedReZjHDcd3fDuh2U7VhMYFKeu1ILY8CYJArfqvHRdtYjZJjqZ2GcuHZWigvH8mbf9XcdtD13L+ivQ6M2oZWP6ULVRXA6ucxkCPeE9VqhyBjf4UusQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +TywhVxOCgjP+YqO7yNh5v3iN2SD4QcNtUlAmpiqssXe4SaVqbFXlJFBQj69pBAwbrK0CNFWsdXHxKR7iPcKSUmTjV9aU8/2vbJq1NN85XF5tAnaYfpYK7tR+YXyIje3pG5RAZMtMUdQTn6Jbfri5oV9MDa3wT0o86OKUo3iVVwAZYBV5vgBTqFy0hXnUbUk6gyfYySU+GeldOLom0y9wnoYb/b6J284ECBe7ES8v6oilHhSM1TX9Z2A9E7bI3Pledwj75udDi3lT4BOE94YQZfGYme6HSaPO21F1hxIG9lPDuBikehhkSrD3bN0q58DjZbMnFiukiUZGb/Fv7MqXmA1GRwybhxOmM/QXq7MMktAvTnr6uGp/3pL02i0KYQNpjbZs9ag2w5uYp6PwYwTpbiqctqxX5FtG7fTys0CAu1yBruMD9QgzsC809J0nrlbXlxeBCKQGWe+V6X07Ix0lpgpLN37C+1DWLQiSUJ1nopyFH2N8thhV9xQZTa7qZCpD9INPLUI/0PBgSjdoF+AM4/Xj8E01PP35X3Z0iaeKpr2S7rTa7pO8mEHQaMuqiAo9Tx7L4Fy1uRVVLWrTz7UhE6H7wScu7/tMwZSIBKdFDxccnYU6NTBTlPKUsF5vGwG/kHem28q9LGoSVTTDY99Kwxit6eE0h4xXZeTtrzHPtwt0gBQ5krMmrE5UbpuXPkZJ5BKmASCWFIIFV+ZiUkdhM0xKmFbLBgisk9HeusH9Viara3GACpQH17AlVBXE4ymjn7kVPX6xZqBeI2uqh0ni55Sqs88clxojT7IaU2PdQu0EnhY7oGbxtLqq3So/odAGRSGpWaUovLj9Us3g3li4fJccTupFooqaMDkhp6ZMKN8vse5Lbl4Zjbv5fNBTh9v5UGalV0cBS7L0BM1d11WNIE6sn/s+kH0/g3pGxsle//2mRBpjBNyUF2KKJ7H5hx4xoGjtXNF+MBir0sdu53N8k6tsjcYWKIxpPdjAzfZqSBUD4WMjp9AYrOVey0kWmL0e5yiTtIwNekVeEq6HWfjs2cCiFEGnhxIb1C9n6CD0ZlmpF9q+Fkurj9HWjAoPLTcTl9bJnyMSE2tOAf6JKyfczAJisSJXLHUtJPJIzYyyInwb4UOBMpE9kXJFdFUPJ90ZsXgbNHsyoIfSxAkECO2vnunxZXBh8UVTLbxR7XXcAqFmtSjwqWzmoRkIpfeJyHNTnex8M2rsCgAS7KVQWF5FMgMxA46p8X5aIB+bPMOkYIW8SnUG01jzaJtGgpo50UuwAvYfjQHtCAT246Pp2AXGShIX+4xraHvY96UMM9JsWvNOHI+jO7F0PfmMRqy6Pku X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: e32cd5d6-1b56-4885-d798-08d931a97307 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:29.9928 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ezS5yzb0w9oYnLszJRXraf9kqm8jw1ozno8TBEdfkzE+u3XWCV98VmoVbTfrGUTUxHVgPksZ3R66uKGMWfeAVA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/data_rates.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/data_rates.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/data_rates.h b/drivers/net/wireless/celeno/cl8k/data_rates.h new file mode 100644 index 000000000000..ddb027402c19 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/data_rates.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DATA_RATES_H +#define CL_DATA_RATES_H + +#include "wrs/wrs_db.h" +#include "def.h" + +#define DATA_RATE_INVERSE_Q 15 + +struct cl_inverse_data_rate { + u16 he[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE]; + u16 ht_vht[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX_VHT][WRS_GI_MAX_VHT]; + u16 ofdm[WRS_MCS_MAX_OFDM]; + u16 cck[WRS_MCS_MAX_CCK]; +}; + +extern struct cl_inverse_data_rate inverse_data_rate; + +extern const u16 data_rate_he_x10[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE]; +extern const u16 data_rate_ht_vht_x10[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX_VHT][WRS_GI_MAX_VHT]; +extern const u16 data_rate_ofdm_x10[]; +extern const u16 data_rate_cck_x10[]; + +void cl_data_rates_inverse_build(void); +u16 cl_data_rates_get(u8 mode, u8 bw, u8 nss, u8 mcs, u8 gi); +u16 cl_data_rates_get_x10(u8 mode, u8 bw, u8 nss, u8 mcs, u8 gi); + +#endif /* CL_DATA_RATES_H */ From patchwork Thu Jun 17 15:58:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7745C49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 052/256] cl8k: add dbgfile.c Date: Thu, 17 Jun 2021 15:58:59 +0000 Message-Id: <20210617160223.160998-53-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:30 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a70c3f7c-4088-4c63-4b28-08d931a9739a X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:133; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Z2o+UOROSWj5QqnQ2Pyf6Z8jf71TU1FitNOFgsUn0pWSB1MSIq9Wh42XgchWDUNzB53RiH/YRKMuEx0kASo8v6on7qoIzKfivR3e1y3YJzwEtvjQ6CM8BNbKtGxNZjs3Y8kN4vkLoDP9KyKSDzOeQK7Dch2pqag0XFVArWmyFbteEiitiDzniX56JMY1kXq/E3lzXO+dJbPP5VU8HSFBC2GE1kZIB2piklruUJOVdvkG0wRQpj9XHaSjabZzSVSf8ZVxipoxM3WhO0YsJxSHRPZ2bpUVAoKkKt/TK7QwwU0hqpEtrrUs9C8wNhaiHdP9NVYnyDKOu2l1TCshvGFBPjBNU7UsMHwo9mLtFf3otVO92AdunQJzaAim0cw2DKy0YUedY1P0NIswN6BnHaIZYHBuHVZk0CtPxuy5FQqKMzM06NBK0drofUVIlV+dPvQa65b/Ehm1tCMqRYca+q2inJ2D/I+vMJfIFhf8tULzmAi/ltk7eYMNnhg/IJjVVSaz12pPlC8AsibIloWNSDAHU/dLQFOza1EJNZgvUbmQJsVNUZ6s+hZzkPE3jTpuRuXBrg/YPU+ZUSLvIuyXFOv9Sb9rGo8PGGnhQnaOBHtjUX2Y3ycHr7P+sq8Rsyck+L1k+Es+Yf9gFIZGZDq4Z/aVoxb1ixErvYSTmmCoTay3DVux+NeziU3PHDHhRxpG7+oMnSZgZU8CwiDSw0TyADSuLQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(30864003)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DvQ028GU7VXPTthhP9RiKYgijmXdzyKc3x51HDC4otsY1fUCvS9N2RQvbIx8UGpi1nCL2LG7wwhn+VByKbCFTJLbInjiATh77jKmIvfm64UdY34j785PN0P8PoccsGf0cs1dgvPhrhMyj0QQ5p1eVTlFjZ+WGa+EDOWLQphprhSmiuQCRqjiHTLikGTq9H1nGMvfLAOSOTX0XgOScJbQiC6JwOl6NyHg/e4hYxHrqrC5U7yt4A0o0wOH12tR0AjVNkvJSGeZJitnmLStMfzMABWdd0awzyPq01RpNTC8dt62jL1nQviFB1jTerm1huJu/Y3NncnRPlBUdu0b+ojjKB6+r/ZbhYqFjwZawkyfW/YQbBMM2aPxlsMCg2vFcv2U+pS34d8Ei06Dg05d7W1Bdllfcu/MEAu56PNdm6jtu2osyR7zu34F5mgXWNO9iXuoDbgNPdoTg8dcZEgiuA7SQTLE4Z1GAzTlWhn9Bv9BF6sEUph/jv0G2PODUEg4Z59Jm3NvsJnJ/O399YC0gKzpIgsROQVmUX8gRC2XdEQ41uM02UDYvGgcyv+XocW+xfWgQZkt0HyF91aIaEVdaZSTY/Mn86x8ImVAXr1i1SHi8+r2i80B5+LjZ3eo0q9rr14jcnIRl+SerbyJ+5VXdL/HXWANrAFEoE+JO8L7hxuv4r2NX0h2R4Gg4ipHUmKQyMKuVnMHAA1b7XLkPCmJS1+mRkRiNCrtFgiflNot3Tv4+wI6o9gZbeDzlYo/huulqMbtqEc2+LHBb+/uuU1vAZPlZVD2sl8XrLbCtNaRmVppOdapSeevAhTQ+lfvZR1pnm7HDQMMXmQZu1Juwwm9rigf80vL6GiUCtBdHEZoKO+DObUbJdeXR7tHUlUkNpXsxGimrTSNijB+F+zd/BGIaZvkPpLcLhMvsdmwcwGRTOLn1jVzE5hhzZfyNDhjDeJ/IxL8rL2ag9wpX4pEYoRuCwC0rNcPjC7UFcZ255oc/U8BxGs72ib1+tMVUlGd0LQQCQTapUHhML9sZVUqR7xe+imOXM6bW1nPzxLb0irUy9I+TUbHpovKURYaDf5gVMtZnLMjoR6afZpPtY6pTcOVl4YCRGnm+BBg62NKklL+2Ime20OY8xmJbwX9xOa5oEZtEiIxDDhPda7ML48AHxlj0Md1Z7FORMWSr1ROqSbjfGKTTEDTm+NYkXcrESZ1Bc5CbCwYJoNWGlV6WxPaQ4SWqZ/kv8DaHotNGJ4ySW+Q2vIfJ5iSCyIZklw7wQoh7HM6lwAvr4N+7SUHReoOrgbInz5979jtkUwf1iG2U6nC5eECRxFV3ZnhqL0aVo4s6sf0L6GO X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: a70c3f7c-4088-4c63-4b28-08d931a9739a X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:31.0293 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: x5r54cEFvgdrV2arz3O1kbXR8v6wIDQZE1BHg3QL+rCJzhzCVcuE+dnOydxyHHAYBQQPbyTify3MzKaw3Hcbsw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/dbgfile.c | 438 +++++++++++++++++++++ 1 file changed, 438 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/dbgfile.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/dbgfile.c b/drivers/net/wireless/celeno/cl8k/dbgfile.c new file mode 100644 index 000000000000..1e8aebbe91f4 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/dbgfile.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "dbgfile.h" +#include "reg/reg_access.h" +#include "utils/utils.h" +#include "dbgfile.h" + +const char *cl_dbgfile_get_msg_txt(struct cl_dbg_data *dbg_data, int file_id, int line) +{ + /* Get the message text from the .dbg file by fileid & line number */ + int remaining_bytes = dbg_data->size; + const char *str = dbg_data->str; + char id_str[32]; + int idstr_len; + + if (!str || 0 == remaining_bytes) + return NULL; + + idstr_len = snprintf(id_str, sizeof(id_str), "%hu:%hu:", file_id, line); + + /* Skip hash */ + while (*str++ != '\n') + ; + + remaining_bytes -= (str - (char *)dbg_data->str); + + while (remaining_bytes > 0) { + if (strncmp(id_str, str, idstr_len) == 0) { + str += idstr_len; + while (*str == ' ') + ++str; + return (const char *)str; + } + + str += strnlen(str, 512) + 1; + remaining_bytes = dbg_data->size - (str - (char *)dbg_data->str); + } + + /* No match found */ + pr_err("error: file_id=%d line=%d not found in debug print file\n", file_id, line); + return NULL; +} + +void cl_dbgfile_parse(struct cl_hw *cl_hw, void *edata, u32 esize) +{ + /* Parse & store the firmware debug file */ + struct cl_dbg_data *dbg_data = &cl_hw->dbg_data; + + dbg_data->size = esize; + dbg_data->str = edata; +} + +void cl_dbgfile_release_mem(struct cl_dbg_data *dbg_data, + struct cl_str_offload_env *str_offload_env) +{ + dbg_data->str = NULL; + + str_offload_env->enabled = false; + str_offload_env->block1 = NULL; + str_offload_env->block2 = NULL; +} + +/* + * Store debug print offload data + * - part 1: offloaded block that does not exist on target + * - part 2: resident block that remains on target [optional] + */ +int cl_dbgfile_store_offload_data(struct cl_chip *chip, struct cl_hw *cl_hw, + void *data1, u32 size1, u32 base1, + void *data2, u32 size2, u32 base2, + void *data3, u32 size3, u32 base3) +{ + u32 u = size1; + struct cl_str_offload_env *str_offload_env = &cl_hw->str_offload_env; + + if (u > 200000) + goto err_too_big; + + /* TODO we modify offload data! if caller checks integrity, make a copy? */ + str_offload_env->block1 = data1; + str_offload_env->size1 = size1; + str_offload_env->base1 = base1; + + str_offload_env->block2 = data2; + str_offload_env->size2 = size2; + str_offload_env->base2 = base2; + + str_offload_env->block3 = data3; + str_offload_env->size3 = size3; + str_offload_env->base3 = base3; + + str_offload_env->enabled = true; + + cl_dbg_info(cl_hw, "%cmac%u: FW prints offload memory use = %uK\n", + cl_hw->fw_prefix, chip->idx, (size1 + size2 + 1023) / 1024); + + return 0; + +err_too_big: + pr_err("%s: size too big: %u\n", __func__, u); + return 1; +} + +static void do_print_n(struct cl_hw *cl_hw, const char *str, int n) +{ + /* Print formatted string with "band" prefix */ + if (n < 0 || n > 256) { + cl_dbg_err(cl_hw, "%cmac%u: *** FW PRINT - BAD SIZE: %d\n", + cl_hw->fw_prefix, cl_hw->chip->idx, n); + return; + } + + cl_dbg_verbose(cl_hw, "%cmac%u: %.*s\n", cl_hw->fw_prefix, cl_hw->chip->idx, n, str); +} + +static void do_hex_dump_bytes(struct cl_hw *cl_hw, u32 addr, void *data, u32 count) +{ + cl_dbg_verbose(cl_hw, "%cmac%u: hex dump:\n", cl_hw->fw_prefix, cl_hw->chip->idx); + cl_hex_dump(NULL, data, count, addr, true); +} + +#define MAGIC_PRINT_OFFLOAD 0xFA /* 1st (low) byte of signature */ +/* 2-nd signature byte */ +#define MAGIC_PRINT_OFF_XDUMP 0xD0 /* Hex dump, by bytes */ +#define MAGIC_PRINT_OFF_LIT 0x01 /* Literal/preformatted string */ +#define MAGIC_PRINT_OFF_PRINT 0x02 /* Print with 'virtual' format string */ + +#define MAX_PRINT_OFF_PARAMS 20 + +static int offload_print(struct cl_str_offload_env *str_offload_env, char *fmt, const char *params) +{ + static char buf[1024] = {0}; + const char *cur_prm = params; + char tmp; + char *fmt_end = fmt; + size_t size = sizeof(int); + int len = 0; + + union v { + u32 val32; + u64 val64; + ptrdiff_t str; + } v; + + while ((fmt_end = strchr(fmt_end, '%'))) { + fmt_end++; + + /* Skip '%%'. */ + if (*fmt_end == '%') { + fmt_end++; + continue; + } + + /* Skip flags. */ + while (strchr("-+ 0#", *fmt_end)) + fmt_end++; + + /* Skip width. */ + while (isdigit(*fmt_end)) + fmt_end++; + + /* Skip precision. */ + if (*fmt_end == '.') { + while (*fmt_end == '-' || *fmt_end == '+') + fmt_end++; + + while (isdigit(*fmt_end)) + fmt_end++; + } + + /* Get size. */ + if (*fmt_end == 'z') { + /* Remove 'z' from %zu, %zd, %zx and %zX, + * because sizeof(size_t) == 4 in the firmware. + * 'z' can only appear in front of 'd', 'u', 'x' or 'X'. + */ + if (!strchr("duxX", *(fmt_end + 1))) + return -1; + + fmt_end++; + size = 4; + } else if (*fmt_end == 'l') { + fmt_end++; + + if (*fmt_end == 'l') { + fmt_end++; + size = sizeof(long long); + } else { + size = sizeof(long); + } + + if (*fmt_end == 'p') /* %p can't get 'l' or 'll' modifiers. */ + return -1; + } else { + size = 4; + } + + /* Get parameter. */ + switch (*fmt_end) { + case 'p': /* Replace %p with %x, because the firmware's pointers are 32 bit wide */ + *fmt_end = 'x'; + fallthrough; + case 'd': + case 'u': + case 'x': + case 'X': + if (size == 4) + v.val32 = __le32_to_cpu(*(__le32 *)cur_prm); + else + v.val64 = __le64_to_cpu(*(__le64 *)cur_prm); + cur_prm += size; + break; + case 's': + v.str = __le32_to_cpu(*(__le32 *)cur_prm); + cur_prm += 4; + size = sizeof(ptrdiff_t); + + if (v.str >= str_offload_env->base3 && + v.str < str_offload_env->base3 + str_offload_env->size3) { + v.str -= str_offload_env->base3; + v.str += (ptrdiff_t)str_offload_env->block3; + } else if (v.str >= str_offload_env->base2 && + v.str < str_offload_env->base2 + str_offload_env->size2) { + v.str -= str_offload_env->base2; + v.str += (ptrdiff_t)str_offload_env->block2; + } else + return -1; + + break; + default: + return -1; + } + + /* Print into buffer. */ + fmt_end++; + tmp = *fmt_end; /* Truncate the format to the current point and then restore. */ + *fmt_end = 0; + len += snprintf(buf + len, sizeof(buf) - len, fmt, size == 4 ? v.val32 : v.val64); + *fmt_end = tmp; + fmt = fmt_end; + } + + snprintf(buf + len, sizeof(buf) - len, "%s", fmt); + + pr_debug("%s", buf); + + return 0; +} + +struct pr_off_desc { + u8 file_id; + u8 flag; + __le16 line_num; + char fmt[]; +}; + +char *strreplace(char *s, char old, char new) +{ + for (; *s; ++s) + if (*s == old) + *s = new; + return s; +} + +static int do_dprint(struct cl_hw *cl_hw, u32 fmtaddr, u32 nparams, u32 *params) +{ + /* + * fmtaddr - virtual address of format descriptor in firmware, + * must be in the offloaded segment + * nparams - size of parameters array in u32; min=0, max=MAX_PRINT_OFF_PARAMS + * params - array of parameters[nparams] + */ + struct cl_str_offload_env *str_offload_env = &cl_hw->str_offload_env; + struct pr_off_desc *pfmt = NULL; + + if (!str_offload_env->enabled) + return -1; + + if (fmtaddr & 0x3) + cl_dbg_warn(cl_hw, "FW PRINT - format not aligned on 4? %8.8X\n", fmtaddr); + + if (fmtaddr > str_offload_env->base1 && + fmtaddr < (str_offload_env->base1 + str_offload_env->size1)) { + pfmt = (void *)((fmtaddr - str_offload_env->base1) + str_offload_env->block1); + } else { + cl_dbg_err(cl_hw, "FW PRINT - format not in allowed area %8.8X\n", fmtaddr); + return -1; + } + + /* + * Current string sent by firmware is #mac@ where # is '253' and @ is '254' + * Replace '253' with 'l' or 's' according to the fw_prefix. + * Replace '254' with '0' or '1' according to chip index. + */ + strreplace(pfmt->fmt, (char)253, cl_hw->fw_prefix); + strreplace(pfmt->fmt, (char)254, (cl_hw->chip->idx == CHIP0) ? '0' : '1'); + + if (offload_print(str_offload_env, pfmt->fmt, (char *)params) == -1) { + cl_dbg_err(cl_hw, "FW PRINT - ERROR in format! (file %u:%u)\n", + pfmt->file_id, pfmt->line_num); + /* $$$ dbg dump the struct */ + cl_hex_dump(NULL, (void *)pfmt, 48, fmtaddr, true); + return -1; + } + + return 0; +} + +static int do_offload(struct cl_hw *cl_hw, u8 *data, int bytes_remaining) +{ + u8 magic2 = data[1]; + u32 nb = data[2] + (data[3] << 8); /* Following size in bytes */ + /* DATA IS UNALIGNED! REVISE if alignment required or BIG ENDIAN! */ + __le32 *dp = (__le32 *)data; + int bytes_consumed = 4; /* 1 + 1 + 2 */ + + /* Data: [0] u8 magic1, u8 magic2, u16 following size in bytes */ + if (bytes_remaining < 8) { + cl_dbg_err(cl_hw, "*** FW PRINT - OFFLOAD PACKET TOO SHORT: %d\n", + bytes_remaining); + return bytes_remaining; + } + + if (bytes_remaining < (nb + bytes_consumed)) { + cl_dbg_err(cl_hw, "*** FW PRINT - OFFLOAD PACKET %u > remainder %d??\n", + nb, bytes_remaining); + return bytes_remaining; + } + + switch (magic2) { + case MAGIC_PRINT_OFF_PRINT: { + /* + * [1] u32 format descriptor ptr + * [2] u32[] parameters + */ + u32 fmtp = dp[1]; + u32 np = (nb - 4) / 4; /* Number of printf parameters */ + + if (nb < 4 || nb & 3) { + cl_dbg_err(cl_hw, "*** FW PRINT - bad pkt size: %u\n", nb); + goto err; + } + + do_dprint(cl_hw, fmtp, np, &dp[2]); + + bytes_consumed += nb; /* Already padded to 4 bytes */ + } + break; + + case MAGIC_PRINT_OFF_LIT: { + /* [1] Remaining bytes: literal string */ + do_print_n(cl_hw, (char *)&dp[1], nb); + bytes_consumed += ((nb + 3) / 4) * 4; /* Padding to 4 bytes */ + } + break; + + case MAGIC_PRINT_OFF_XDUMP: + /* [1] bytes[nb] */ + if (nb >= 1) + do_hex_dump_bytes(cl_hw, 0, &dp[1], nb); + + bytes_consumed += ((nb + 3) / 4) * 4; /* Padding to 4 bytes */ + break; + + default: + cl_dbg_err(cl_hw, "*** FW PRINT - BAD TYPE: %4.4X\n", magic2); + goto err; + } + + return bytes_consumed; + +err: + return bytes_remaining; /* Skip all */ +} + +void cl_dbgfile_print_fw_str(struct cl_hw *cl_hw, u8 *str, int max_size) +{ + /* Handler for firmware debug prints */ + int bytes_remaining = max_size; + int i; + u8 delim = 0; + + while (bytes_remaining > 0) { + /* Scan for normal print data: */ + for (i = 0; i < bytes_remaining; i++) { + if (str[i] < ' ' || str[i] >= 0x7F) { + if (str[i] == '\t') + continue; + delim = str[i]; + break; + } + } + + if (i > 0) { + if (delim == '\n') { + bytes_remaining -= i + 1; + do_print_n(cl_hw, str, i); + str += i + 1; + continue; + } + + if (delim != MAGIC_PRINT_OFFLOAD) { + do_print_n(cl_hw, str, i); + bytes_remaining -= i; + return; /* Better stop parsing this */ + } + /* Found offload packet but previous string not terminated: */ + do_print_n(cl_hw, str, i); + cl_dbg_err(cl_hw, "*** FW PRINT - NO LINE END2\n"); + bytes_remaining -= i; + str += i; + continue; + } + + /* Delimiter at offset 0 */ + switch (delim) { + case '\n': + do_print_n(cl_hw, " ", 1); /* Print empty line */ + str++; + bytes_remaining--; + continue; + case 0: + return; + case MAGIC_PRINT_OFFLOAD: + i = do_offload(cl_hw, str, bytes_remaining); + bytes_remaining -= i; + str += i; + break; + default: + cl_dbg_err(cl_hw, "*** FW PRINT - BAD BYTE=%2.2X ! rem=%d\n", + delim, bytes_remaining); + return; /* Better stop parsing this */ + } + } +} + From patchwork Thu Jun 17 15:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28876C2B9F4 for ; Thu, 17 Jun 2021 16:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12C2161249 for ; Thu, 17 Jun 2021 16:04:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233679AbhFQQGa (ORCPT ); Thu, 17 Jun 2021 12:06:30 -0400 Received: from mail-eopbgr140040.outbound.protection.outlook.com ([40.107.14.40]:17172 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233658AbhFQQGJ (ORCPT ); Thu, 17 Jun 2021 12:06:09 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kdSthIEx294OzRDIjifh34UP/Li1boadt8BmTlxPtG3yc7ZcdhiGdzKEkkkn08laz3v2D2jaxWinWDWwZ3LAUP0HQVafoiOCZUGQdg9Qndpl2rgsBRP8HeDJzycBqqQrXnQTnaEFH+XNjUKmFRoZmO/AOsNdxc5GEdkC2L8tAK814XjEntXe5OfTfjw3hr7vnlA+cAJqzCaXIspQZeGw4ve6kT26pO+lUD3Jx/Apsh2/hKd+iZ6iyB3h988R9bgEpf6trgnyooX5LOgB35Hr6x5POgh1V3JIIRKgGZE+0kdfXeMWxwqe6JWTdwedhHE/KbHGlAG3q8bDXwL1TC9p3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qwuvoILTbpbwnCbWZuxd6YdxG2AJSdCL72/oaNg9a/E=; b=oZEpSdqlvPm6JgMMi7lKHztGRxjoFrblISvCbPCvXLwvpGp8e/7CmSxHDWwmFVUP0fKsP8YSbOWxod1uQB3F132geVcJxMPnLS0nRILaDBv4nRks5m4RFeV/nbWkug6HaBZ4aN674DaEgVRFfI0Y5/hwapJgjJtls7A3qkyPnT8ePGEaxSBPsn1CxK2qdgnOWZAvMigm4IBxREraGcFnLiQzx5QOQL/GEIznhxlD5RVTvs76TuTZSGCeE3Gvpr1d4isiQ3knAjOyGyMyB9XBz3PBpcN8LJsa3QxTLNGx5DRZULEN7ehIwopwLdv3RLycIUzISjeVeUihpNHrvhuLHw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qwuvoILTbpbwnCbWZuxd6YdxG2AJSdCL72/oaNg9a/E=; b=p/RHpLbwFSeWiWhpYhSGya1YJ0ywHLOSoF6Dhi7oIpWOQKmfQH0ft8gTBcXxeDgNmAmqfcLQRmcKpuG3AR8wzzyYzKJux0U4WjtJC73hOw9iWlqLzaIJybLAWFYV3l5eWYIhXY803xn7wxRiYavxYaSXmdEKfiziA/ECuj2MPtY= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1234.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:388::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16; Thu, 17 Jun 2021 16:03:46 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:03:46 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 054/256] cl8k: add debug.h Date: Thu, 17 Jun 2021 15:59:01 +0000 Message-Id: <20210617160223.160998-55-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:32 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 307a1a64-d557-4a01-a484-08d931a974d2 X-MS-TrafficTypeDiagnostic: AM9P192MB1234: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1148; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hoKoPKdmJy+4OgE7/I7g3ATuhjICCYIPRYp38Er/gVqpzUykOwL45iCAs0Ojlo3aDAibBRtfRo8QAol/OJaXtokVtVqKpSwc73UX8cOjQf9tpRu7W7D7yrtUTgIDBOg003WKcfqwOVGyyW608oC4fw4aPa2O+EsxMIFGXlaaaOy6S4MOIMjRDeuYGKSCQ46V/ElNznd2ivaDC+8Q39AVx8kEhuWEu+rvtpoTKoCUTKUtN61Hyud28+7z0wLX78y5AUrGE6hAHnYVjs1McCBhVvW5qI12wdoM/DUNegnO11cgQdm66qPWJ9DMVp4sErPYe0HatOx08QtYnOpGCP/X4/A8oK+hfpkJi+ACva+kFC6tbbr2VeJxNrpk0RidB1Vt1hCdX/YeUhz5RXkcuHdymf43knDGJyRmXDcuMaIocJfIU0iyx7Zskk71g60hG45SNtcwQKGgYgCOHR59I+3vEtFDZfMNWIhmwiEQDwSctTNQOtxtOBK0NJmwk4XnIFbSICYQm1ZowpdEtoAAwEnO6/EUJnxliOoCDvPqwnfgCBSMmviRlUcml49xLL07qkeQXqSXN3kEUARPCOEbXXdzeymg3kRQCE9DQXrsXDx3qCv1IwKM39tV3KImQzbdLLMZiHfmxOgf+GVTnz+sKmUe8HIYQ5ZVy/AwZlXkOxncE7j2Qp4ZMyJnV0A+lz22ca4NADbiwDD9o59qEGTEc9q6DQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(136003)(346002)(396003)(39850400004)(6666004)(107886003)(36756003)(956004)(66476007)(66556008)(2616005)(66946007)(6916009)(2906002)(26005)(9686003)(1076003)(6512007)(6486002)(16526019)(6506007)(38100700002)(52116002)(86362001)(8936002)(316002)(38350700002)(186003)(55236004)(54906003)(8676002)(5660300002)(508600001)(83380400001)(4326008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: J2glHhleHdaxWKrZmXqTXUT6fOr7avDSZwtMkp4B0g5FwgkKH+glZF8bnA3YaHFEq5Hw5jvmiPxrfzw8ZwXM8dngEktLCu8JobMNCImeic3Paz1iqhIoMtB9rGaTtxKqdwPnny+9sXfqr70ZC/jfDoXd5pUVtTYQ8WeYUVpS7+yimU//kxwAqnb9iZ6Uj2rmMlsEMasoSesthGGGznbupyjFtPJGsa+NMOYbbBynora/s/8gRDypyRydGASYHe/9sl6vu1FUbSoJd4y7xTWub0gAs/rRyjLJknA0NJMTIkWaF/A2WcakpiaVjiAopITTpG32xLfnTPIsGuZ4LfQWzpUYv79xKOvXba5GwYVzxkMOG2qrppPlxf0MlZrQJP/+wSbVi4mjPdP1uQ8PpiSV8TwiwU8qsTpt7LQUSFtN7b3qC+kzQZkisZrIpSiAlfEDf0AdggaVKi2UreyFrOFAOtb7o5TVoj6MzZjKsdl9VWvjZZQThZK7XyqAZH2a43GuTDFtS0s7MtpNPrRTM56T4azuNQwZ/b6V9O135gG4vv+5/zBanEmbmNaK5LfdlhRxA3Rm7zm6RiCPeoEqRImuGI8JfgfABJ1i0aK4jPVGdrnYow/s3b0IJuWF6AovVWphT7bhUEPlL3zCXBGqZTtxIfFmzHuG+TrIeLLwCvL5vJP8KCZ/aWDJyCCaORSGftRlLLuIabANz+x1eIX2qhcPd1u1E7RqS6+TJUpT1Uy9+NjBoN25dUQb7BGYjg4uPBwDSYLRrsBFiCXcGBD5TQcIDX5Xep0LtHQZ2RsF9nqL27SNiPbRbrpUXPUjY1BtyNPNyL1IBJi6aDThPGI8GijLmNRAbQqOmYsDKI0tbQ8A5nzkTU992ciEeSPp6omYK4nGZUIsAJ75ebBZEcJj1G6Lvz9fw7vLJTn6UfNcXh0aao46UpBGCH28EdR/7odC8lto5Xf57nLlnbMQbKttCpl0doO5D9DBwze5/FB8m2uXh5yzzz35YIZmM07Ad92eKpGQXDABHa0JLihNOOpzAH/mjSKoGeEPP36a0HB28PctmSFV57j4yXBkTrrIHb0Np1zkxjzqt60G/FyyxchOeOhZustrFgtxc9ZQwrG1ED1cPT6/jVKwL7A3G+l7tekiSXw5LLMXJiisNlXveIZCBqfn9mP8cbz/ZFZVYKy1vIcylH9d0DYGngP5yZGZZX445fGQg3Lng777F+rRdJ1EX9vMTOrb9VGAYjrgfq1+AuEeuwA9tdqKRinxmukWvy7mUv/8zmc2QoHTve4Nrf4EAOF4ywmjhZmb6aUUtKgHJzjn5FNcywZm0GhP7Yk28pXL04J3 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 307a1a64-d557-4a01-a484-08d931a974d2 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:33.0155 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: aSpTqisevZgoZxlMjfwQw1pTFxjDrR0HFHVcLYY0CHNhcC/rltMs43etGW+7OMwarfI8Ngjz/qMo8LSYawWEZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1234 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/debug.h | 121 +++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/debug.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/debug.h b/drivers/net/wireless/celeno/cl8k/debug.h new file mode 100644 index 000000000000..f51591755051 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/debug.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DEBUG_H +#define CL_DEBUG_H + +#include + +enum cl_dbg_level { + DBG_LVL_VERBOSE, + DBG_LVL_ERROR, + DBG_LVL_WARNING, + DBG_LVL_TRACE, + DBG_LVL_INFO, + + DBG_LVL_MAX, +}; + +#define CL_DBG(cl_hw, lvl, fmt, ...) \ +do { \ + if ((lvl) <= (cl_hw)->conf->ce_debug_level) \ + pr_debug("[tcv%u][%s][%d] " fmt, (cl_hw)->idx, __func__, __LINE__, ##__VA_ARGS__); \ +} while (0) + +#define CL_DBG_CHIP(chip, lvl, fmt, ...) \ +do { \ + if ((lvl) <= (chip)->conf->ce_debug_level) \ + pr_debug("[chip%u][%s][%d] " fmt, (chip)->idx, __func__, __LINE__, ##__VA_ARGS__); \ +} while (0) + +#define cl_dbg_verbose(cl_hw, ...) CL_DBG((cl_hw), DBG_LVL_VERBOSE, ##__VA_ARGS__) +#define cl_dbg_err(cl_hw, ...) CL_DBG((cl_hw), DBG_LVL_ERROR, ##__VA_ARGS__) +#define cl_dbg_warn(cl_hw, ...) CL_DBG((cl_hw), DBG_LVL_WARNING, ##__VA_ARGS__) +#define cl_dbg_trace(cl_hw, ...) CL_DBG((cl_hw), DBG_LVL_TRACE, ##__VA_ARGS__) +#define cl_dbg_info(cl_hw, ...) CL_DBG((cl_hw), DBG_LVL_INFO, ##__VA_ARGS__) + +#define cl_dbg_chip_verbose(chip, ...) CL_DBG_CHIP((chip), DBG_LVL_VERBOSE, ##__VA_ARGS__) +#define cl_dbg_chip_err(chip, ...) CL_DBG_CHIP((chip), DBG_LVL_ERROR, ##__VA_ARGS__) +#define cl_dbg_chip_warn(chip, ...) CL_DBG_CHIP((chip), DBG_LVL_WARNING, ##__VA_ARGS__) +#define cl_dbg_chip_trace(chip, ...) CL_DBG_CHIP((chip), DBG_LVL_TRACE, ##__VA_ARGS__) +#define cl_dbg_chip_info(chip, ...) CL_DBG_CHIP((chip), DBG_LVL_INFO, ##__VA_ARGS__) + +static inline char *basename(const char *filename) +{ + char *p = strrchr(filename, '/'); + + return p ? p + 1 : (char *)filename; +} + +#define TXT_ERROR \ + do { \ + pr_debug("\n"); \ + pr_debug("####### ##### ##### ##### #####\n"); \ + pr_debug("# # # # # # # # #\n"); \ + pr_debug("# # # # # # # # #\n"); \ + pr_debug("####### ##### ##### # # #####\n"); \ + pr_debug("# # # # # # # # #\n"); \ + pr_debug("# # # # # # # # #\n"); \ + pr_debug("####### # # # # ##### # #\n"); \ + } while (0) + +#define TXT_WARNING \ + do { \ + pr_debug("\n"); \ + pr_debug("# # ##### ##### # # ### # # #####\n"); \ + pr_debug("# # # # # # ## # # ## # # #\n"); \ + pr_debug("# # # # # # # # # # # # # #\n"); \ + pr_debug("# # # ####### ##### # # # # # # # # ###\n"); \ + pr_debug("# # # # # # # # # # # # # # # # #\n"); \ + pr_debug("# # # # # # # # # ## # # ## # #\n"); \ + pr_debug(" # # # # # # # # ### # # #####\n"); \ + } while (0) + +#define INFO_CL_HW(cl_hw, ...) \ + do { \ + pr_debug("\n"); \ + pr_debug("CHIP: %u\n", (cl_hw)->chip->idx); \ + pr_debug("TCV: %u\n", (cl_hw)->idx); \ + pr_debug("FILE: %s\n", basename(__FILE__)); \ + pr_debug("FUNCTION: %s\n", __func__); \ + pr_debug("LINE: %u\n", __LINE__); \ + pr_debug("DESCRIPTION: " __VA_ARGS__); \ + pr_debug("\n"); \ + } while (0) + +#define INFO_CHIP(chip, ...) \ + do { \ + pr_debug("\n"); \ + pr_debug("CHIP: %u\n", (chip)->idx); \ + pr_debug("FILE: %s\n", basename(__FILE__)); \ + pr_debug("FUNCTION: %s\n", __func__); \ + pr_debug("LINE: %u\n", __LINE__); \ + pr_debug("DESCRIPTION: " __VA_ARGS__); \ + pr_debug("\n"); \ + } while (0) + +#define CL_DBG_ERROR(cl_hw, ...) \ + do { \ + TXT_ERROR; \ + INFO_CL_HW(cl_hw, __VA_ARGS__); \ + } while (0) + +#define CL_DBG_ERROR_CHIP(chip, ...) \ + do { \ + TXT_ERROR; \ + INFO_CHIP(chip, __VA_ARGS__); \ + } while (0) + +#define CL_DBG_WARNING(cl_hw, ...) \ + do { \ + TXT_WARNING; \ + INFO_CL_HW(cl_hw, __VA_ARGS__); \ + } while (0) + +#define CL_DBG_WARNING_CHIP(chip, ...) \ + do { \ + TXT_WARNING; \ + INFO_CHIP(chip, __VA_ARGS__); \ + } while (0) + +#endif /* CL_DEBUG_H */ From patchwork Thu Jun 17 15:59:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C250C49EA2 for ; Thu, 17 Jun 2021 16:04:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 010666120A for ; Thu, 17 Jun 2021 16:04:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233628AbhFQQGS (ORCPT ); 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 056/256] cl8k: add debugfs.h Date: Thu, 17 Jun 2021 15:59:03 +0000 Message-Id: <20210617160223.160998-57-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:34 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: adc88c3d-18da-4e7f-7cd6-08d931a9761a X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yl9qovcGHtv8mVypJp1ZEeOAnqftcJMG1rNqpevKhak1aqX3GBJ4A2hGu5W9UYGcMzOrUjoxi70RJ5RJedS/pylo41UBChM3BSv1IC9kdBf9AfwOXLHzqVwA/tkyVii9KLwvfTFVJ9mlAvrGJOOpPbG759qt2UJPMK1gsgkQSu6sjsphPQKkDDzft5H80JP2FDgNLhQUOzgvN8tduVH8x5GnBHy88KdEYKvmOEc2k2KeQwgqk9OvA/O1HIxZIjD5Hr37wGpcOYuf0hp0+moIQNrfYteIrfB3eBIa0Kw37D+TdAJSI9TpWKgdFfBetzCDf+p+zAMfxIN2+6C8EpxxgFixQN23XnD2gxyM+KROjWAY7emSjUpkb18UXKD0MhWfHH76kiCarxHUsFA+COjHqPDN3pCXKlYy6VyWJ3h4W9pb2imvbg7k69FjzNKXYvAXrjJpr9zTpEyoorbr8chVwWe38ubKrG3/Ekt0mGRpkhe59SywPlEeuRBrXRJS/Qs9POi9p4XB2AMOcVcrF4qizkgW9z8tf5vfkDxX3o4AWoiAAcxR8ex084az4Sv0iDPXNTJsNt1vyn/PbBQulKXmuqnIXF7h+Knk9PqUmcZvjOnSuQyxTFjOogSTbnizwgZTm9OH3wBS5kMVbuCH4tRHz7D40GVY1bL+Ai4ZWE8ENEIABHeKy4HH7qQPsdtbi65AlDgHQjmntAZAmwSJp561QQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MRjwC2445QqtcC5szEzxYyPvJ7Vg05dujTIfPoGHgTWigzgP8/UmAo+pECbuWrYlIMu2QAaTTxtu5c/oRHHfFgUz/3lsOHwWRHXhFCtOT7Gq1dQ78ZwUeRtfXQMU3dKRtJ5y0AEXd3aZOYrvjt1KuWSN8zvAkfIc9f7QDGP7ouqrHBBDm4FvEoFvxn32FoQ9Gex/ly8Tmh8kmgKNExg+4sx/PVn12w4PD/yy+wdFIBhdjHId5l0R5rnpfqgkjbRqaWEC/qbSV4TfvVLDS2y0K0mqb8KFt8+WIzNXqymbQrSE8UikW+4BJkZleov4F+rVKEJSO51OYYZYlOOkqoJcMxqJHDAI3HiE5e2E8y6xJj/vUW9QZXxdcfeTJl3CDiOfnNBB7KMtiYVxGuw6iEmEneEv+Q4c41+mvE3k4zbJA67Ru0AM9UVLvF0FwmHIO4JbrQHWS0SOZA6FHAjx50B9pSw8LdXsH++kMSmMM7MyjWNMPRFh9SFD1H3YAOxsLjbx10g+ySOUGvp8FSBTlYZWzoeVVrl51xm/HDCuAKbjebPgETtAchnyDyIgZ6arHZljvuv7SQ3ndZeVPKFEKTLR7WDPAblfVgXgQM7YLVX9l3u9aoz/8n7jbv2bCpjyxwwkDGv4C8lCsd27KGNa+MlDZ2xPLKMgV7piXnoGfrTcd/5GX9u9eD6/zLxzAMl3/JPVBaouZxOgD/3Zki0jL6KMagxJeBoPsGtri2LgtP8UfMvqJg8XPsHC1NKpKSskcGfyLZL53rDz+Nzh2SrnjVTaRHHbD4TpMlet0qb563RaQpoQWQ6QQxzZFuYFe+X9261eS/Vn1h2jmMHHWTdDnX0hDwLsW2j7JLu/NTJA59zyB5GGWvIPwz82K95hVZio08G4f+nkIixbCrKDQFgmAO1jx4sxDBiLSfhXSaKl5Ht8ZxVDPXh5hkI4sJw6clkN6jYE9a0kjjS6RoQsW3jB0Y4xnOKzr7dhUD1B6dqgQDGZReL9oOck+23MzpQwpEnK7KRVcZ0WKnmA7qt9n9mtDprbCR4wtvnrQPOfkNDw8eLQ5bgNkcJBDP7TXwfw4ArDQps74yAVeFBpuC8PWCEA9noZaRenofUQpHNpBa3qsI53RB/iTSwpIXuAPRrJ2WXSZx3f5IQSpKBvppjSQAAv4n63z4++ArcRKxQtrwKWoMOdxaAXebj2vn/9uLHzntG0EFOBywQ6/r0TAEnI2V273nRoyDeMfENivkbjBBIXU5Mh/gCjguARSG3sLP7XEyXTC5SynHRPeeZDNadI+h5SGQao+/jW231P8FiHINp/w+8dVm5cwwfqH7QrNQHZNwZl7017 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: adc88c3d-18da-4e7f-7cd6-08d931a9761a X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:35.1800 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dwAHNiPBHxsweWVtGHoJ0mTTHXgpjXUCIlBtcxlf89KShFUyZt3i2DKp+e/KcZnVRt0R017w8hb7GzbmuyhwQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/debugfs.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/debugfs.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/debugfs.h b/drivers/net/wireless/celeno/cl8k/debugfs.h new file mode 100644 index 000000000000..1684c6aea1a9 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/debugfs.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DEBUGFS_H +#define CL_DEBUGFS_H + +#include "debugfs_defs.h" +#include "hw.h" + +#ifdef CONFIG_CL_DEBUGFS + +int cl_dbgfs_register(struct cl_hw *cl_hw, const char *name); +void cl_dbgfs_unregister(struct cl_hw *cl_hw); + +#else + +static inline int cl_dbgfs_register(struct cl_hw *cl_hw, const char *name) +{ + return 0; +} + +static inline void cl_dbgfs_unregister(struct cl_hw *cl_hw) +{ +} + +#endif /* CONFIG_CL_DEBUGFS */ + +#endif /* CL_DEBUGFS_H */ From patchwork Thu Jun 17 15:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAFB4C2B9F4 for ; Thu, 17 Jun 2021 16:04:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD0F2613E1 for ; Thu, 17 Jun 2021 16:04:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231856AbhFQQGj (ORCPT ); Thu, 17 Jun 2021 12:06:39 -0400 Received: from mail-vi1eur05on2081.outbound.protection.outlook.com ([40.107.21.81]:58626 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233644AbhFQQGJ (ORCPT ); Thu, 17 Jun 2021 12:06:09 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XVPC+T80+HyuxhzzdRCrcAx0yr9nlNjmDhqrS6yopWiS772gboFJmuwy20vLWqLz0Luxac1sWWiYvYO+3bwZVg+rTtqjknNoHKeZEZk2WZaJ6BGyb7kU9JImbIm+23XYTdKdz4g0Iey+Yc5IJo7pyiTVFqtaqK6V562nR6UPqkVNLcAcw1fJfxizpxDmDeh8YAfa8qDlO4Y6SS3xj2hSMxm/ikzWYYfBT/V7+NuWe0nO22DMnWKrPdoL5bTeu/W2qe3bzV0ETUkvpX05QRfEfdJo/W3UUow6HCfSdhrzIOrDc9hjwoqTZDEH2lXRWfUg9zJgbTk3Zmud24T/C5Topg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6GUoDSoczNNQUgumtLTp+ew/hJxs5ovMI/hnArTTsOA=; b=D9Bqi6DZoZkm9amPCC4biHWq9d/4pnsQnLrgAZXQ0FiMlTd9HGB91xfc0vsmUeAgi70QAP4zFZiZwOm5maPhS5uM3bF/p2snP0nhQh3u985K82KZX9169cBK6PkCrSgLrLitnSJzJGr4D7OwojOJAQu+TFUZZccR3fkrg3jrgdrPgcY3UYusnlATGp/Dx1mMQIkmkUdZYQW8eYC7KE0X4UfKWZzxsTOK1Nl/Ur91lVC5jlhtGAB9kEInqkisdsadhZK6XgyC0pIj2HLYHQdHngI6kODt8MUF8WB0WngPzOyDGhMP/xk0arhHVZlTKJnzqWretFjT8/96GAROmeC57g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6GUoDSoczNNQUgumtLTp+ew/hJxs5ovMI/hnArTTsOA=; b=aaJj7NKWP4ygLq74Kg1HelgTZ7UyXhjY3To4Of/uVrdBcEEwFKx6fSzVA481E8NDTYFckcbZQgIt52d/l9hic0qnoKyc9GUygrbqAH+/GuL+YAlzde4cwwtUqD+EAylF2NWvfQ5ldDlDtbk5FMCc+t02FSJHfSyhpNaRHIdHpBY= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0499.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:03:48 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:03:48 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 059/256] cl8k: add dfs/dfs.c Date: Thu, 17 Jun 2021 15:59:06 +0000 Message-Id: <20210617160223.160998-60-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:37 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ebe3e279-10d1-4606-f0fd-08d931a97818 X-MS-TrafficTypeDiagnostic: AM0P192MB0499: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zeitfKhqiu0Bm3qc9CTNjGBWK0u7TODOYAzpahDbtKf4MD1gg0m2wGkqHCuvaQvBLRku0u/i1Cq6/bPijJtfP/NdE0JwQ5jNUI8xlYzBPjpobVAclmBb0fkJrqOWUbFlZEweX05twGQRp0qnYwuZTFBPZXx68sIm4YMk3JntZxzJRTM/XIkpmldw/J3EMneZ8nJ5qbUcxEOrDVxYXFMbCCxsU3ipekv7K1m4ziB0FhRx0czl4IW0hrXS91UdORrJBj2V35tvh8jkUStSJrWGQ/eWe3nP+z5MEhUdOQvxp272NSUn4vF6SeUyNXtuKzTL8k4qrp7KAIQirEsE6XWXa9JVLF3f8CFMUdgJwMOhddfMzK5rBIwQ0GHl3BwRVuHChYFg/af1OwMDgSC2GdMOBBRBZRHbDF7oJuUL9ODgLESQzn+2WM4lK8CRhG8iNoPxDgDc6qjJ0kO4FMCtI9ORpr3quUA9rEqDi4z+Qjvx8qaHISS01Eqh6/OhAiEk4RCc/bVVHh6egkRE/YPRuuyK+ruXIpl/20lzZe8YhHNnjgrTJyZGoILAIXDQpo5Qj9/OvK/2FwVVLmlQ3ZSHOvPougHQbEiJXS1sr1iJI/bd4ypwAloJM3V+B8bCpaK1oRJFaIY+Tcw15mgHOTbXO53wsMA+kTGz5c1DLQ4EZPh9NRV0E82FZZigO2410lfP/TwFULOcCERVHqRUv47uFZPoYQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(39840400004)(396003)(376002)(366004)(346002)(86362001)(107886003)(66556008)(52116002)(83380400001)(55236004)(36756003)(4326008)(186003)(16526019)(956004)(316002)(6486002)(8676002)(54906003)(38100700002)(38350700002)(66476007)(6506007)(2906002)(26005)(9686003)(6512007)(66946007)(2616005)(5660300002)(478600001)(30864003)(1076003)(6666004)(8936002)(6916009)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bjdOby3w002dD9a044kxySNvy2qC5auFwufg4zu2Vs5TJToq4xCbZynRIGu0zqm956IpVmLlsIbZde8rhHu2ooQKLdYtkVXNIekISJ5F9C4+eN+Iss7tmTkcnXKIjop/UYSms4mcU6JSoXUT7Da+pSZ6L3Ys10I3+zCoaQ581U+8DsifsCfRjqjBAmh5UWVId+MVsuIQri5wOkdhXtFvkG8CL86PgFyapZEHYOXqXdNXDmdJdfe3UXE0zdwsItrd+TsOFjTEoy3h/1GBSdIER5OHosps784UWwKA8xl84LBHqOjfsEO9OlvTPMYlgiYjxgzn7pxG4bztfPEv4eSGeuzezQRf//7uBN2dhvmCx57JTTOV46KbEtp/PYzU6iELPSADhg+C4JJas5JhwEQisbjZxS8aHWHkSS8RweMRqLPDAEPVk+nEVngdkasZ4s+DanM4DQoe93St9YmfJpEULaEwM0BFQ9f0gnpSCa8ynDNwKNGDcI10iuNjgU/3D3fb3s9a/6naoiMm2qFq62Pl19AkbySD3chWNy8NvFb+5BR71xUCDwAEs34eUhsrVMY251WT6LBppUwaOl69mft/4CAgt8F+kvLX7MrD31fmsh7+ZQBqrnG57DSX+afEIXkrr7eiv9rIvUA7GPU3Tl3hoIUyEXosuz3naYh1Y+A1nPSZtyygqjUDfbwwySpb9JQm6AK270tmfpM33j4RDGcyD5+UJxpVUMNWAIcUdUWqB6746aPg/+b1oAh67PneWIcBPBQjI2MMitVY3A7DKCck3Oy3Ap6ZlP4OE9kbnQDRxs1JX3TIZtPEGZy37FKRas9BkQ5RTMB/DV1OqyAJwF1GV+mWVPb/JkM946o/UqnJ2IZp3W59FPLO9wb9HK7C/mDCUa460FwAj7AXo0EHpYiq43KdAD+3/r9HRLUkbBq9glNKnGkxPupfK9aMIXERPGz3XMVU2OE1mqwq8SHZnVdKStFtrU7NBBxDIlNZ5x2VgOT53JNHGulPEUO5jzphuypQ4andm3+2FcpieqGhyMEcd/gN+pFpBRC17RtyMddejOl/8eLZcUS9s8XBNcg45qArCtWgyq7RidfqoUA1cUfkq3gFaOlVMuoOi29CzgS5Z0UHW8v3FoSJ50lyQuAJ3ESxwI/MtNgvMDTkCBjxN2BPoMDW6cMrT6pk9BrV7bneOi58hylzBbrO8ZWX25WFEBD7/ulpeqvyMJlINZk723bv8T3ARAnuhD1xg9SFrzjIqIfOoR9G0URhZcgBpDIVY8B22Se3dGItEEuk25A0cLhFs4yg+Z6a6grijH+9iv9fls4E/E2husyqMq2h/ARC5rIb X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebe3e279-10d1-4606-f0fd-08d931a97818 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:38.8001 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TicE9WvpBg9s1GH312fhlIlu3aNcpNX6cpG15e0hCezBZ6CiDb01g54jw6hb5Bw7wAuFF4O6G3xLnR0ak2J4lQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0499 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/dfs/dfs.c | 977 +++++++++++++++++++++ 1 file changed, 977 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/dfs/dfs.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/dfs/dfs.c b/drivers/net/wireless/celeno/cl8k/dfs/dfs.c new file mode 100644 index 000000000000..b2717a8be26a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/dfs/dfs.c @@ -0,0 +1,977 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "dfs/dfs.h" +#include "dfs/dfs_db.h" +#include "dfs/radar.h" +#include "chip.h" +#include "channel.h" +#include "chan_info.h" +#include "env_det.h" +#include "debug.h" +#include "utils/timer.h" +#include "tx/tx.h" +#include "temperature.h" +#include "utils/math.h" +#include "calib.h" +#include "traffic.h" +#include "utils/utils.h" +#include "reg/reg_riu.h" +#include "reg/reg_mac_hw.h" +#include "band.h" +#include "chandef.h" +#include "utils/string.h" +#include "utils/file.h" +#include "config.h" + +#define dfs_pr(cl_hw, level, ...) \ + do { \ + if ((level) <= (cl_hw)->dfs_db.dbg_lvl) \ + pr_debug(__VA_ARGS__); \ + } while (0) + +#define dfs_pr_verbose(cl_hw, ...) dfs_pr((cl_hw), DBG_LVL_VERBOSE, ##__VA_ARGS__) +#define dfs_pr_err(cl_hw, ...) dfs_pr((cl_hw), DBG_LVL_ERROR, ##__VA_ARGS__) +#define dfs_pr_warn(cl_hw, ...) dfs_pr((cl_hw), DBG_LVL_WARNING, ##__VA_ARGS__) +#define dfs_pr_trace(cl_hw, ...) dfs_pr((cl_hw), DBG_LVL_TRACE, ##__VA_ARGS__) +#define dfs_pr_info(cl_hw, ...) dfs_pr((cl_hw), DBG_LVL_INFO, ##__VA_ARGS__) + +#define COUNTRY_CODE_LEN 2 + +/* + * ID Min Max Tol Min Max Tol Tol MIN PPB Trig Type + * Width Width Width PRI PRI PRI FREQ Burst Count + */ + +/* ETSI Radar Types v1.8.2 */ +static struct cl_radar_type radar_type_etsi[] = { + + {0, 1, 1, 1, 1428, 1428, 1, 1, 1, 18, 10, RADAR_WAVEFORM_SHORT}, + {1, 1, 5, 1, 1000, 5000, 1, 1, 1, 10, 5, RADAR_WAVEFORM_SHORT}, + {2, 1, 15, 1, 625, 5000, 1, 1, 1, 15, 8, RADAR_WAVEFORM_SHORT}, + {3, 1, 15, 1, 250, 435, 1, 1, 1, 25, 10, RADAR_WAVEFORM_SHORT}, + {4, 10, 30, 1, 250, 500, 1, 1, 1, 20, 10, RADAR_WAVEFORM_SHORT}, + {5, 1, 5, 1, 2500, 3334, 1, 1, 2, 10, 5, RADAR_WAVEFORM_STAGGERED}, + {6, 1, 5, 1, 833, 2500, 1, 1, 2, 15, 8, RADAR_WAVEFORM_STAGGERED}, +}; + +/* FCC Radar Types 8/14 */ +static struct cl_radar_type radar_type_fcc[] = { + {0, 1, 1, 0, 1428, 1428, 1, 1, 1, 18, 10, RADAR_WAVEFORM_SHORT}, + {1, 1, 5, 3, 518, 3066, 3, 1, 1, 18, 10, RADAR_WAVEFORM_SHORT}, + {2, 1, 5, 3, 150, 230, 3, 1, 1, 23, 10, RADAR_WAVEFORM_SHORT}, + {3, 3, 10, 3, 200, 500, 3, 1, 1, 16, 6, RADAR_WAVEFORM_SHORT}, + {4, 6, 20, 3, 200, 500, 3, 1, 1, 12, 6, RADAR_WAVEFORM_SHORT}, + {5, 50, 100, 50, 1000, 2000, 1, 1, 2, 10, 5, RADAR_WAVEFORM_LONG}, + {6, 1, 1, 0, 333, 333, 1, 1, 2, 30, 10, RADAR_WAVEFORM_LONG}, +}; + +static void cl_dfs_fw_en(struct cl_hw *cl_hw, u8 dfs_en) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + struct cl_tcv_conf *conf = cl_hw->conf; + + cl_msg_tx_set_dfs(cl_hw, dfs_en, dfs_db->dfs_standard, + conf->ci_dfs_initial_gain, conf->ci_dfs_agc_cd_th); +} + +static int cl_dfs_print_tbl(struct cl_hw *cl_hw) +{ + int i; + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "-------------------------------------------------------------------------" + "---------------\n" + "| | Min | Max | Tol | Min | Max | Tol | Tol | Min | |" + " Trig | |\n" + "| ID | Width | Width | Width | PRI | PRI | PRI | FREQ | Burst | PPB |" + " Count | Type |\n" + "-------------------------------------------------------------------------" + "---------------\n"); + + for (i = 0; i < dfs_db->radar_type_cnt; i++) { + cl_snprintf(&buf, &len, &buf_size, + "| %2u | %5d | %5d | %5d | %5d | %5d | %3d | %4d | %5u |" + " %3u | %5u | %4d |\n", + dfs_db->radar_type[i].id, + dfs_db->radar_type[i].min_width, + dfs_db->radar_type[i].max_width, + dfs_db->radar_type[i].tol_width, + dfs_db->radar_type[i].min_pri, + dfs_db->radar_type[i].max_pri, + dfs_db->radar_type[i].tol_pri, + dfs_db->radar_type[i].tol_freq, + dfs_db->radar_type[i].min_burst, + dfs_db->radar_type[i].ppb, + dfs_db->radar_type[i].trig_count, + dfs_db->radar_type[i].waveform); + cl_snprintf(&buf, &len, &buf_size, + "-----------------------------------------------------------------" + "-----------------------\n"); + } + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static bool cl_dfs_create_detection_buffer(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db, + struct cl_dfs_pulse *pulse_buffer, u8 *samples_cnt, + unsigned long time) +{ + u8 i; + u8 pulse_idx; + /* Init First index to last */ + u8 first_pulse_idx = (dfs_db->buf_idx - 1 + CL_DFS_PULSE_BUF_SIZE) & CL_DFS_PULSE_BUF_MASK; + + /* Find Start Pulse indexes */ + for (i = 0; i < CL_DFS_PULSE_BUF_SIZE; i++) { + pulse_idx = (i + dfs_db->buf_idx) & CL_DFS_PULSE_BUF_MASK; + + if ((time - dfs_db->dfs_pulse[pulse_idx].time) < dfs_db->search_window) { + first_pulse_idx = pulse_idx; + break; + } + } + + dfs_pr_info(cl_hw, "DFS: First pulse idx = %u, Last pulse idx = %u\n", + first_pulse_idx, dfs_db->buf_idx - 1); + + if (dfs_db->buf_idx - 1 >= first_pulse_idx) + if ((dfs_db->buf_idx - first_pulse_idx - 1) < (dfs_db->min_pulse_eeq - 1)) { + /* Return if buffer don't hold enough valid samples */ + dfs_pr_warn(cl_hw, "DFS: Not enough pulses in buffer\n"); + + return false; + } + + /* Copy the processed samples to local Buf to avoid index castings */ + for (i = 0; pulse_idx != ((dfs_db->buf_idx - 1 + CL_DFS_PULSE_BUF_SIZE) + & CL_DFS_PULSE_BUF_MASK); i++) { + pulse_idx = (i + first_pulse_idx) & CL_DFS_PULSE_BUF_MASK; + memcpy(&pulse_buffer[i], &dfs_db->dfs_pulse[pulse_idx], sizeof(pulse_buffer[i])); + } + *samples_cnt = i + 1; + + return true; +} + +static void cl_dfs_add_pulses_to_global_buffer(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db, + struct cl_radar_pulse *pulse, u8 pulse_cnt, + unsigned long time) +{ + int i; + + for (i = 0; i < pulse_cnt; i++) + dfs_pr_info(cl_hw, "Pulse=%d, Width=%u, PRI=%u, FREQ=%d, Time=%lu, FOM=%x\n", + i, pulse[i].len, pulse[i].rep, pulse[i].freq, time, pulse[i].fom); + + /* Maintain cyclic pulse buffer */ + for (i = 0; i < pulse_cnt; i++) { + dfs_db->dfs_pulse[dfs_db->buf_idx].freq = pulse[i].freq; + dfs_db->dfs_pulse[dfs_db->buf_idx].width = pulse[i].len; + dfs_db->dfs_pulse[dfs_db->buf_idx].pri = pulse[i].rep; + dfs_db->dfs_pulse[dfs_db->buf_idx].occ = 0; /* occ temp disabled. */ + dfs_db->dfs_pulse[dfs_db->buf_idx].time = time; + + dfs_db->buf_idx++; + dfs_db->buf_idx &= CL_DFS_PULSE_BUF_MASK; + } +} + +static bool cl_dfs_buf_maintain(struct cl_hw *cl_hw, struct cl_radar_pulse *pulse, + struct cl_dfs_pulse *pulse_buffer, u8 pulse_cnt, + unsigned long time, u8 *samples_cnt, struct cl_dfs_db *dfs_db) +{ + int i; + + cl_dfs_add_pulses_to_global_buffer(cl_hw, dfs_db, pulse, pulse_cnt, time); + if (!cl_dfs_create_detection_buffer(cl_hw, dfs_db, pulse_buffer, samples_cnt, time)) + return false; + + for (i = 0; i < *samples_cnt; i++) + dfs_pr_info(cl_hw, "DFS: pulse[%d]: width=%u, pri=%u, freq=%d\n", + i, pulse_buffer[i].width, pulse_buffer[i].pri, pulse_buffer[i].freq); + + return true; +} + +static inline bool cl_dfs_pulse_match(s32 pulse_val, s32 spec_min_val, + s32 spec_max_val, s32 spec_tol) +{ + return ((pulse_val >= (spec_min_val - spec_tol)) && + (pulse_val <= (spec_max_val + spec_tol))); +} + +static u8 cl_dfs_is_stag_pulse(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db, + struct cl_dfs_pulse *pulse) +{ + int i; + struct cl_radar_type *radar_type; + + for (i = 0; i < dfs_db->radar_type_cnt; i++) { + radar_type = &dfs_db->radar_type[i]; + + if (radar_type->waveform != RADAR_WAVEFORM_STAGGERED) + continue; + + if (cl_dfs_pulse_match((s32)pulse->width, radar_type->min_width, + radar_type->max_width, radar_type->tol_width) && + cl_dfs_pulse_match((s32)pulse->pri, radar_type->min_pri, + radar_type->max_pri, radar_type->tol_pri)) { + /* Search for the second burst */ + if (abs(pulse[0].pri - pulse[2].pri) <= dfs_db->radar_type[i].tol_pri && + abs(pulse[1].pri - pulse[3].pri) <= radar_type->tol_pri && + abs(pulse[0].pri - pulse[1].pri) > radar_type->tol_pri && + abs(pulse[2].pri - pulse[3].pri) > radar_type->tol_pri) { + dfs_pr_info(cl_hw, "DFS: Found match type %d\n", i); + return (i + 1); + } else if (abs(pulse[0].pri - pulse[3].pri) <= radar_type->tol_pri && + abs(pulse[1].pri - pulse[4].pri) <= radar_type->tol_pri && + abs(pulse[0].pri - pulse[1].pri) > radar_type->tol_pri && + abs(pulse[3].pri - pulse[4].pri) > radar_type->tol_pri) { + dfs_pr_info(cl_hw, "DFS: Found match radar %d\n", i); + return (i + 1); + } + } + } + + return 0; +} + +static u8 cl_dfs_is_non_stag_pulse(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db, + struct cl_dfs_pulse *pulse) +{ + int i; + struct cl_radar_type *radar_type; + + for (i = 0; i < dfs_db->radar_type_cnt; i++) { + radar_type = &dfs_db->radar_type[i]; + + if (radar_type->waveform == RADAR_WAVEFORM_STAGGERED) + continue; + + if (cl_dfs_pulse_match((s32)pulse->width, radar_type->min_width, + radar_type->max_width, radar_type->tol_width) && + cl_dfs_pulse_match((s32)pulse->pri, radar_type->min_pri, + radar_type->max_pri, radar_type->tol_pri)) { + dfs_pr_info(cl_hw, "DFS: Found match type %d\n", i); + return (i + 1); + } + } + + dfs_pr_warn(cl_hw, "DFS: Match not found\n"); + + return 0; +} + +static u8 cl_dfs_get_pulse_type(struct cl_hw *cl_hw, struct cl_dfs_pulse *pulse, + bool stag_candidate) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + + if (stag_candidate) { + u8 pulse_type = cl_dfs_is_stag_pulse(cl_hw, dfs_db, pulse); + + if (pulse_type) + return pulse_type; + } + + return cl_dfs_is_non_stag_pulse(cl_hw, dfs_db, pulse); +} + +static bool cl_dfs_compare_cand(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db, u8 pulse_type, + struct cl_dfs_pulse radar_cand, u8 *match, int idx, + u8 *occ_ch_cand) +{ + int i; + + if (!(abs(dfs_db->pulse_buffer[idx].width - radar_cand.width) <= + dfs_db->radar_type[pulse_type].tol_width)) + goto end; + + if (!(abs(dfs_db->pulse_buffer[idx].freq - radar_cand.freq) <= + dfs_db->radar_type[pulse_type].tol_freq)) + goto end; + + for (i = 1; i < CL_DFS_CONCEAL_CNT; i++) + if (abs(dfs_db->pulse_buffer[idx].pri - i * radar_cand.pri) <= + dfs_db->radar_type[pulse_type].tol_pri) + break; + + if (i == CL_DFS_CONCEAL_CNT) + goto end; + + (*match)++; + (*occ_ch_cand) += dfs_db->pulse_buffer[i].occ; + +end: + dfs_pr_info(cl_hw, "DFS: compared pulse - width=%u, pri=%u, freq=%u match: %u " + "trig cnt: %u\n", + dfs_db->pulse_buffer[idx].width, dfs_db->pulse_buffer[idx].pri, + dfs_db->pulse_buffer[idx].freq, *match, + dfs_db->radar_type[pulse_type].trig_count); + + if (*match < dfs_db->radar_type[pulse_type].trig_count) + return false; + + return true; +} + +static bool cl_dfs_check_cand(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db, u8 pulse_type, + struct cl_dfs_pulse radar_cand, u8 samples_cnt) +{ + u8 occ_ch_cand = 0; + u8 match = 0; + int i; + + dfs_pr_info(cl_hw, "DFS: candidate pulse - width=%u, pri=%u, freq=%u\n", + radar_cand.width, radar_cand.pri, radar_cand.freq); + + for (i = 0; i < samples_cnt; i++) { + if (!cl_dfs_compare_cand(cl_hw, dfs_db, pulse_type, radar_cand, &match, i, + &occ_ch_cand)) + continue; + + dfs_pr_verbose(cl_hw, "DFS: Radar detected - type %u\n", pulse_type); + return true; + } + + return false; +} + +static bool cl_dfs_short_pulse_search(struct cl_hw *cl_hw, struct cl_radar_pulse *pulse, + u8 pulse_cnt, unsigned long time, struct cl_dfs_db *dfs_db) +{ + int i; + bool stag_candidate; + u8 samples_cnt = 0; + u8 pulse_type; + + /* Return if not enough pulses in the buffer */ + if (!cl_dfs_buf_maintain(cl_hw, pulse, dfs_db->pulse_buffer, pulse_cnt, time, + &samples_cnt, dfs_db)) + return false; + + for (i = 0; i < samples_cnt; i++) { + struct cl_dfs_pulse radar_cand; + + stag_candidate = false; + + /* Make sure there is enough samples to staggered check */ + if (dfs_db->dfs_standard == CL_STANDARD_ETSI && + (samples_cnt - i) > CL_DFS_STAGGERED_CHEC_LEN) + stag_candidate = true; + + pulse_type = cl_dfs_get_pulse_type(cl_hw, &dfs_db->pulse_buffer[i], stag_candidate); + + if (!pulse_type) + continue; + + radar_cand.width = dfs_db->pulse_buffer[i].width; + radar_cand.pri = dfs_db->pulse_buffer[i].pri; + radar_cand.freq = dfs_db->pulse_buffer[i].freq; + + if (cl_dfs_check_cand(cl_hw, dfs_db, pulse_type - 1, radar_cand, samples_cnt)) + return true; + } + + return false; +} + +static bool cl_dfs_long_pulse_search(struct cl_hw *cl_hw, struct cl_radar_pulse *pulse, + u8 pulse_cnt, unsigned long time) +{ + u32 prev_pulse_time_diff; + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + struct cl_tcv_conf *conf = cl_hw->conf; + int i; + + for (i = 0; i < pulse_cnt; i++) { + if (pulse[i].len > CL_DFS_LONG_MIN_WIDTH) { + prev_pulse_time_diff = time - dfs_db->last_long_pulse_ts; + + if (pulse[i].rep >= dfs_db->radar_type[5].min_pri && + pulse[i].rep <= dfs_db->radar_type[5].max_pri) + dfs_db->long_pri_match_count += 1; + + dfs_pr_info(cl_hw, "DFS: Long pulse search: width = %u, delta_time = %u\n", + pulse[i].len, prev_pulse_time_diff); + + if (dfs_db->long_pulse_count == 0 || + (prev_pulse_time_diff >= conf->ci_dfs_long_pulse_min && + prev_pulse_time_diff <= conf->ci_dfs_long_pulse_max)) { + dfs_db->long_pulse_count += 1; + } else if (prev_pulse_time_diff > min(dfs_db->max_interrupt_diff, + conf->ci_dfs_long_pulse_min)) { + dfs_db->long_pulse_count = 0; + dfs_db->short_pulse_count = 0; + dfs_db->long_pri_match_count = 0; + } + dfs_db->last_long_pulse_ts = time; + } else if (pulse[i].len < CL_DFS_LONG_FALSE_WIDTH) { + dfs_db->short_pulse_count++; + + if (dfs_db->short_pulse_count > CL_DFS_LONG_FALSE_IND) { + dfs_db->long_pulse_count = 0; + dfs_db->short_pulse_count = 0; + dfs_db->long_pri_match_count = 0; + + dfs_pr_warn(cl_hw, "DFS: Restart long sequence search\n"); + } + } + } + + if (dfs_db->long_pulse_count >= dfs_db->radar_type[5].trig_count && + dfs_db->long_pri_match_count >= (dfs_db->radar_type[5].trig_count - 1)) { + dfs_db->short_pulse_count = 0; + dfs_db->long_pulse_count = 0; + dfs_db->long_pri_match_count = 0; + return true; + } else { + return false; + } +} + +static bool cl_dfs_post_detection(struct cl_hw *cl_hw) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + struct cl_tcv_conf *conf = cl_hw->conf; + + /* Make sure firmware sets the DFS registers */ + cl_radar_flush(cl_hw); + cl_msg_tx_set_dfs(cl_hw, false, dfs_db->dfs_standard, + conf->ci_dfs_initial_gain, conf->ci_dfs_agc_cd_th); + + ieee80211_radar_detected(cl_hw->hw); + + return true; +} + +bool cl_dfs_pulse_process(struct cl_hw *cl_hw, struct cl_radar_pulse *pulse, u8 pulse_cnt, + unsigned long time) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + + dfs_db->pulse_cnt += pulse_cnt; + + if (dfs_db->dfs_standard == CL_STANDARD_FCC && + cl_dfs_long_pulse_search(cl_hw, pulse, pulse_cnt, time)) { + dfs_pr_verbose(cl_hw, "DFS: Radar detected - long\n"); + return cl_dfs_post_detection(cl_hw); + } else if (cl_dfs_short_pulse_search(cl_hw, pulse, pulse_cnt, time, dfs_db)) { + dfs_pr_verbose(cl_hw, "DFS: Radar detected - short\n"); + return cl_dfs_post_detection(cl_hw); + } + + return false; +} + +static void cl_dfs_set_min_pulse(struct cl_hw *cl_hw) +{ + int i; + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + + dfs_db->min_pulse_eeq = U8_MAX; + + for (i = 0; i < dfs_db->radar_type_cnt; i++) { + if (dfs_db->radar_type[i].trig_count < dfs_db->min_pulse_eeq) + dfs_db->min_pulse_eeq = dfs_db->radar_type[i].trig_count; + } + dfs_db->min_pulse_eeq = max(dfs_db->min_pulse_eeq, (u8)CL_DFS_MIN_PULSE_TRIG); +} + +static void cl_dfs_set_region(struct cl_hw *cl_hw, enum cl_reg_standard std) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + + dfs_db->dfs_standard = std; + + if (dfs_db->dfs_standard == CL_STANDARD_FCC) { + dfs_db->csa_cnt = CL_DFS_FCC_CSA_CNT; + dfs_db->radar_type = radar_type_fcc; + dfs_db->radar_type_cnt = sizeof(radar_type_fcc) / sizeof(struct cl_radar_type); + } else { + dfs_db->csa_cnt = CL_DFS_CE_CSA_CNT; + dfs_db->radar_type = radar_type_etsi; + dfs_db->radar_type_cnt = sizeof(radar_type_etsi) / sizeof(struct cl_radar_type); + } +} + +static void cl_dfs_start_cac(struct cl_dfs_db *db) +{ + db->cac.started = true; +} + +static void cl_dfs_end_cac(struct cl_dfs_db *db) +{ + db->cac.started = false; +} + +void cl_dfs_radar_listen_start(struct cl_hw *cl_hw) +{ + set_bit(CL_DEV_RADAR_LISTEN, &cl_hw->drv_flags); + + cl_dfs_fw_en(cl_hw, true); + + dfs_pr_verbose(cl_hw, "DFS: Started radar listening\n"); +} + +void cl_dfs_radar_listen_end(struct cl_hw *cl_hw) +{ + clear_bit(CL_DEV_RADAR_LISTEN, &cl_hw->drv_flags); + + cl_dfs_fw_en(cl_hw, false); + + dfs_pr_verbose(cl_hw, "DFS: Ended radar listening\n"); +} + +void cl_dfs_force_cac_start(struct cl_hw *cl_hw) +{ + bool is_listening = test_bit(CL_DEV_RADAR_LISTEN, &cl_hw->drv_flags); + + cl_dfs_start_cac(&cl_hw->dfs_db); + + /* Reset request state upon completion */ + cl_dfs_request_cac(cl_hw, false); + + /* Disable all the TX flow - be silent */ + cl_tx_en(cl_hw, CL_TX_EN_DFS, false); + + /* If for some reason we are still not listening radar, do it */ + if (unlikely(!is_listening && cl_hw->hw->conf.radar_enabled)) + cl_dfs_radar_listen_start(cl_hw); + + dfs_pr_verbose(cl_hw, "DFS: CAC started\n"); +} + +void cl_dfs_force_cac_end(struct cl_hw *cl_hw) +{ + bool is_listening = test_bit(CL_DEV_RADAR_LISTEN, &cl_hw->drv_flags); + + /* Enable all the TX flow */ + cl_tx_en(cl_hw, CL_TX_EN_DFS, true); + + /* + * If for some reason we are still listening and mac80211 does not + * require to listen radar - disable it + */ + if (unlikely(is_listening && !cl_hw->hw->conf.radar_enabled)) + cl_dfs_radar_listen_end(cl_hw); + + cl_dfs_end_cac(&cl_hw->dfs_db); + + dfs_pr_verbose(cl_hw, "DFS: CAC ended\n"); +} + +static u16 cl_dfs_get_remain_cac_time(struct cl_hw *cl_hw) +{ + struct cl_vif *cl_vif = cl_vif_get_first_ap(cl_hw); + struct wireless_dev *wdev = cl_vif ? ieee80211_vif_to_wdev(cl_vif->vif) : NULL; + + if (wdev && wdev->cac_started) + return (jiffies_to_msecs(jiffies - wdev->cac_start_time) / 1000U); + + return 0; +} + +bool __must_check cl_dfs_is_en(struct cl_hw *cl_hw) +{ + return cl_hw->dfs_db.en; +} + +bool __must_check cl_dfs_is_in_cac(struct cl_hw *cl_hw) +{ + return cl_hw->dfs_db.cac.started; +} + +bool __must_check cl_dfs_radar_listening(struct cl_hw *cl_hw) +{ + return test_bit(CL_DEV_RADAR_LISTEN, &cl_hw->drv_flags); +} + +bool __must_check cl_dfs_requested_cac(struct cl_hw *cl_hw) +{ + return cl_hw->dfs_db.cac.requested; +} + +void cl_dfs_request_cac(struct cl_hw *cl_hw, bool should_do) +{ + cl_hw->dfs_db.cac.requested = should_do; +} + +static void cl_dfs_edit_tbl(struct cl_hw *cl_hw, u8 row, u8 line, s16 val) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + + if (row > dfs_db->radar_type_cnt) { + dfs_pr_err(cl_hw, "Invalid row number (%u) [0 - %u]\n", line, + dfs_db->radar_type_cnt - 1); + return; + } + + if (line == 0 || line > CL_DFS_MAX_TBL_LINE) { + dfs_pr_err(cl_hw, "Invalid line number (%u) [1 - %u]\n", line, + CL_DFS_MAX_TBL_LINE - 1); + return; + } + + if (line == 1) + dfs_db->radar_type[row].min_width = (s32)val; + else if (line == 2) + dfs_db->radar_type[row].max_width = (s32)val; + else if (line == 3) + dfs_db->radar_type[row].tol_width = (s32)val; + else if (line == 4) + dfs_db->radar_type[row].min_pri = (s32)val; + else if (line == 5) + dfs_db->radar_type[row].max_pri = (s32)val; + else if (line == 6) + dfs_db->radar_type[row].tol_pri = (s32)val; + else if (line == 7) + dfs_db->radar_type[row].tol_freq = (s32)val; + else if (line == 8) + dfs_db->radar_type[row].min_burst = (u8)val; + else if (line == 9) + dfs_db->radar_type[row].ppb = (u8)val; + else if (line == 10) + dfs_db->radar_type[row].trig_count = (u8)val; + else if (line == 11) + dfs_db->radar_type[row].waveform = (enum cl_radar_waveform)val; + + /* Verify if min_pulse_eeq was changed */ + cl_dfs_set_min_pulse(cl_hw); +} + +static void cl_dfs_tbl_overwrite_set(struct cl_hw *cl_hw) +{ + s8 *tok = NULL, *saveptr = NULL; + u8 param1 = 0; + u8 param2 = 0; + s16 param3 = 0; + char str[64]; + + if (strlen(cl_hw->conf->ce_dfs_tbl_overwrite) == 0) + return; + + snprintf(str, sizeof(str), cl_hw->conf->ce_dfs_tbl_overwrite); + + tok = cl_strtok_r(str, ",", &saveptr); + while (tok) { + if (sscanf(tok, "%hhd,%hhd,%hd", ¶m1, ¶m2, ¶m3) == 3) + cl_dfs_edit_tbl(cl_hw, param1, param2, param3); + tok = cl_strtok_r(NULL, ",", &saveptr); + } +} + +void cl_dfs_close(struct cl_hw *cl_hw) +{ + if (!cl_band_is_5g(cl_hw)) + return; + + cl_hw->dfs_db.en = false; +} + +void cl_dfs_init(struct cl_hw *cl_hw) +{ + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + struct cl_tcv_conf *conf = cl_hw->conf; + + if (!cl_band_is_5g(cl_hw)) + return; + + dfs_db->en = conf->ci_ieee80211h; + + /* + * Setting min window size to avoid the case where the second interrupt + * within the burst is setting the counter to 0. the max is between jiffies + * unit and max PRI in ms. + */ + dfs_db->max_interrupt_diff = max(1000 / HZ, 2); + dfs_db->search_window = CL_DFS_PULSE_WINDOW; + + cl_dfs_set_region(cl_hw, cl_hw->channel_info.standard); + cl_dfs_set_min_pulse(cl_hw); + cl_dfs_tbl_overwrite_set(cl_hw); +} + +void cl_dfs_recovery(struct cl_hw *cl_hw) +{ + /* Re-enable DFS after recovery */ + if (cl_dfs_is_in_cac(cl_hw)) { + cl_dfs_fw_en(cl_hw, true); + + /* If recovery happened during CAC make sure to disable beacon backup */ + cl_tx_en(cl_hw, CL_TX_EN_DFS, false); + } +} + +static int cl_dfs_print_pulse_buffer(struct cl_hw *cl_hw, bool clear_buf) +{ + int i; + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "DFS Pulse Count = %u\n", dfs_db->pulse_cnt); + + for (i = 0; i < ARRAY_SIZE(dfs_db->dfs_pulse); i++) { + cl_snprintf(&buf, &len, &buf_size, + "Pulse Buffer: i=%d, Width=%u, PRI=%u, FREQ=%d, OCC=%u, Time=%lu\n", + i, dfs_db->dfs_pulse[i].width, + dfs_db->dfs_pulse[i].pri, + dfs_db->dfs_pulse[i].freq, + dfs_db->dfs_pulse[i].occ, + dfs_db->dfs_pulse[i].time); + } + + if (clear_buf) { + dfs_db->pulse_cnt = 0; + memset(dfs_db->dfs_pulse, 0, sizeof(dfs_db->dfs_pulse)); + } + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static void cl_dfs_cli_force_detection(struct cl_hw *cl_hw, struct cl_dfs_db *dfs_db) +{ + dfs_pr_verbose(cl_hw, "DFS: Force Radar Detection\n"); + cl_dfs_post_detection(cl_hw); +} + +static void cl_dfs_cli_set_cac(struct cl_hw *cl_hw, bool start) +{ + if (start) + cl_dfs_force_cac_start(cl_hw); + else + cl_dfs_force_cac_end(cl_hw); +} + +static int cl_dfs_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "dfs usage:\n" + "-b : Print pulse buffer [(0)Read / (1)Read and clear]\n" + "-c : Stop/Start CAC[(0)Stop / (1)Start]\n" + "-d : DFS debug mode[0: Verbose 1: Error, 2: Warning, 3: Trace, 4: Info]\n" + "-e : Enable/Disable DFS [(0)Disable DFS / (1)Enable DFS]\n" + "-f : Force radar detection\n" + "-i : Set initial gain\n" + "-j : Set agc cd threshold\n" + "-k : return remaining cac time (in seconds)\n" + "-m : Set Min/Max Windows for Long radar types\n" + "-p : Print radar tables [0:Detection Table, 1:Channel info]\n" + "-q : Print jumpable channel list\n" + "-s : Simulate radar detection table " + "[width][pri][freq][time]\n" + "-t : Edit radar detection table [row][line][value]\n" + "-w : Set search window size\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +int cl_dfs_cli(struct cl_hw *cl_hw, struct cli_params *cli_params, u8 *ret_buf, u16 *ret_buf_len) +{ + s32 *params = cli_params->params; + u32 expected_params = 0; + struct cl_dfs_db *dfs_db = &cl_hw->dfs_db; + struct cl_tcv_conf *conf = cl_hw->conf; + bool print_buf = false; + bool dbg_lvl = false; + bool en = false; + bool force = false; + bool print_tbl = false; + bool return_remain_cac_time = false; + bool radar_sim = false; + bool edit_tbl = false; + bool win_set = false; + bool cac = false; + bool long_prms = false; + bool init_gain = false; + bool agc_cd_hh = false; + + switch (cli_params->option) { + case 'b': + print_buf = true; + expected_params = 1; + break; + case 'c': + cac = true; + expected_params = 1; + break; + case 'd': + dbg_lvl = true; + expected_params = 1; + break; + case 'e': + en = true; + expected_params = 1; + break; + case 'f': + force = true; + expected_params = 0; + break; + case 'i': + init_gain = true; + expected_params = 1; + break; + case 'j': + agc_cd_hh = true; + expected_params = 1; + break; + case 'k': + return_remain_cac_time = true; + expected_params = 0; + break; + case 'm': + long_prms = true; + expected_params = 2; + break; + case 'p': + print_tbl = true; + expected_params = 1; + break; + case 's': + radar_sim = true; + expected_params = 4; + break; + case 't': + edit_tbl = true; + expected_params = 3; + break; + case 'w': + win_set = true; + expected_params = 1; + break; + case '?': + return cl_dfs_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (cac) { + bool start = (bool)params[0]; + + cl_dfs_cli_set_cac(cl_hw, start); + return 0; + } + + if (print_buf) + return cl_dfs_print_pulse_buffer(cl_hw, (bool)params[0]); + + if (dbg_lvl) { + s32 dbg_lvl = params[0]; + + if (dbg_lvl > 0 && dbg_lvl < DBG_LVL_MAX) { + dfs_db->dbg_lvl = dbg_lvl; + dfs_pr_verbose(cl_hw, "Debug level = %d\n", dbg_lvl); + } else { + dfs_pr_err(cl_hw, "Invalid debug level (%d)\n", dbg_lvl); + } + + return 0; + } + + if (en) { + dfs_db->en = (bool)(params[0]); + dfs_pr_verbose(cl_hw, "DFS = %s\n", dfs_db->en ? "Enabled" : "Disabled"); + cl_dfs_fw_en(cl_hw, dfs_db->en); + return 0; + } + + if (force) { + cl_dfs_cli_force_detection(cl_hw, dfs_db); + return 0; + } + + if (print_tbl) { + u8 table = (u8)params[0]; + + if (table == 0) + return cl_dfs_print_tbl(cl_hw); + return 0; + } + + if (return_remain_cac_time) { + u16 cac_time = cl_dfs_get_remain_cac_time(cl_hw); + + snprintf(ret_buf, PAGE_SIZE, "%u", cac_time); + *ret_buf_len = strlen(ret_buf); + return 1; + } + + if (radar_sim) { + struct cl_radar_pulse pulse[CL_DFS_MAX_PULSE]; + unsigned long time; + + pulse[0].len = (u32)params[0]; + pulse[0].rep = (u32)params[1]; + pulse[0].freq = (s32)params[2]; + time = (unsigned long)params[3]; + cl_dfs_pulse_process(cl_hw, pulse, 1, time); + return 0; + } + + if (edit_tbl) { + cl_dfs_edit_tbl(cl_hw, (u8)params[0], (u8)params[1], (s16)params[2]); + return 0; + } + + if (win_set) { + dfs_db->search_window = (u16)params[0]; + dfs_pr_verbose(cl_hw, "Search window size = %u\n", dfs_db->search_window); + return 0; + } + + if (long_prms) { + conf->ci_dfs_long_pulse_min = (u16)params[0]; + conf->ci_dfs_long_pulse_max = (u16)params[1]; + dfs_pr_verbose(cl_hw, "Long pulse min = %u\n", conf->ci_dfs_long_pulse_min); + dfs_pr_verbose(cl_hw, "Long pulse max = %u\n", conf->ci_dfs_long_pulse_max); + return 0; + } + + if (init_gain) { + conf->ci_dfs_initial_gain = (u8)params[0]; + dfs_pr_verbose(cl_hw, "Initial gain = %u\n", conf->ci_dfs_initial_gain); + return 0; + } + + if (agc_cd_hh) { + conf->ci_dfs_agc_cd_th = (u8)params[0]; + dfs_pr_verbose(cl_hw, "AGC CD threshold = %u\n", conf->ci_dfs_agc_cd_th); + return 0; + } + +out_err: + return -EIO; +} + From patchwork Thu Jun 17 15:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 781D1C2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 061/256] cl8k: add dfs/dfs_db.h Date: Thu, 17 Jun 2021 15:59:08 +0000 Message-Id: <20210617160223.160998-62-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:40 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1a5e3331-6d43-4553-477a-08d931a979b3 X-MS-TrafficTypeDiagnostic: AM9P192MB1268: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vsMx0Uinqbby79ilE0DkbFbFkD1vWfDp2oomyrr8V5Ifz4aBke5j9p1PcH0QazVDgOlddKTDIeBEJ1RY16v6QdkFyXnPpDWkLvjMFqTlMxVN7XkQzeCm7Yip2MPX7LL3A0+dICzAjU9yiJluOByN/iDFAe962Fb6R8TTJDwjMHH/4VjzEUNJEnXqkwVd7u+SOsiCm9QDYcO673RnNmlE9vpaBRldXp0WtC4pYg72QmNNL26uo9qGKeDs2eM7wJTZHMoIeSYfUP6+AGbLNWjmWB87VDrDKYQV3iLy1XktcstItmLl4aeghQnA5fU/HAyhsC3H35Uw+2krlN+GeLd7RpeyAjFC6ZJ5xPdOywiQEKlOmrMoqIfgkuMzGSuAkXxCx4Zp4LD76ICgQnY2pqWL0lo/Hhz4EKPUDT40nllKZJsz+mGZ/gYuLQSB/FKr8IKPED0btJyqXkQAOzIFqIJUHXl2jWQLKDXlFbe5VOjjYmFUC1RwbySiQDLebLeUDlZHDGlskwBDtDVZf+DK+wvTWIkjq9vuwQhRGBRd2ZxlzEXXRyknVQ6jcKI1aN6zljpFuZv9p3H4PFNxiH6+EANewA04zLYt/Nv+AcSCVoYy4ecG9ZKekU4zPhN7Kgthb4qgfzbei9dWyF4XsyPPX9FKzaqg4rhYpc5CpwJrmrTzQHhTQqOV+m/9wjaIuaW0Q/p5Ug7+pfAnZDaLEpQzqaZz+A== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6486002)(956004)(54906003)(4326008)(2616005)(186003)(38100700002)(16526019)(8676002)(5660300002)(38350700002)(8936002)(26005)(2906002)(6512007)(9686003)(52116002)(83380400001)(6916009)(66946007)(66556008)(66476007)(86362001)(55236004)(498600001)(6666004)(6506007)(1076003)(107886003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jRQ74AMZMCkl0FxxmX5U0Ysew52eDoRmr/ygekQlNJCXRSD5g3a+7xYcWQgBWjJPW5AoeEFgFYWRHM+kTDk2Ey+3kJxt0kyxlXvd6cxpCS+QX8SsObdY4QOPcEzLXPz76JaV90adhDEGY7f67u++YsKLL/ZNaSxgvEgH0rZxJaMUmpHI/E+vO2GvPqJRJUeRZoOwnj3BYXmTVheGhaKkcZtmBAsQudsvyL8ppisHKy0HSZhQygp9IsOadsD1yUdVNA62Han304Lg6uozSBeuf5k25W/jrz28AYjGE/tjOCrf10WT7Ha+lHpA6ZjvIyTBNyNdEsaAVTlixF3IcPabfrIkfDYplsVsCECsr9JfnTouOeAdt5YPFLm0GnCPaDN0cNBsh8A7B3WRZn5A9ipuheIOMr0sIY1dqaebveXdt/M6rQM7v5jz2H76FigohVlGGktrOo2h+sIhhjQ0ngb+AdXqFdo+UX4SMF4GJxnsp2PTPUlCSjApiVFP/QsCb3vtn0UhGiQ8OnPElxNKvBPIP/IrtgrN+g1Hs33NQF2TMn9rvccYMAzcCymwRS8Pan/1EytGX8rtOdr3CRrdhi3FtOsOgPy3CxC+c73n/qSbTp3QYYmUGYUiAcUuL8ZhxVOU6lghqrbi/gfIpkPyAysypZuDiWge//jIbLpknT+zg1Wc7fbHl635NUxXd9dR7qs8dLfnjLhJ900v1LfdZW28yGPOdNqg+BQQgB1UJf0DtIltNpaMhD5DCt1OCR+pTnri2MprFA+ivNkFEBfpLFgh+31gQtkTpSuSXhYGxutiQsJNdQ9D8PfLAbOOwDF4yOy7lrPO/7m27fJ5KyYRKApzYnraicAO65l29xcJj1oRn1k7EDYIU6FXf8poIPKaNzGqY6K7ZtJTFGsgkSdjSQ/jxopMft8421SiJycHeg/fsbf883JHBw+Zr2FSugB2oKl/sCu+DQMy8SPUlWSzo4N8F5/U54gnxXhOChAXGWrPOwZ2p6Z7daC3fml5NDER9mid2rly09k4g+zCgk49ZS9xXgDx2ezvpT26/xo3XY1UiSth4drVtwp8TmtfZcPsnGbj5nuvzjS/yk1n+LDzk1rwOXTZpgnOsRqvCxKmYFUlyWyfjPZZdEz/PvpzkMvwq8r3DI9N+KFH4A7R9WIzzhDDs/eDy7L8Mh39ycap7LYjMkJivbrGVPkaWd9lvCCIplCiTl41EkggHxFhGQ7Rqt9GZ4FASeZHY7K0j+8ahStmbBczkaPZP1ptLhGomYKV5xf6MxZbktYLxntzbb64vI2W+tnKFlzRdLe+3LDeOTfQTlLoEM50vdFq7csTF6z8aPmZ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1a5e3331-6d43-4553-477a-08d931a979b3 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:41.2354 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: E3j+BW9Q9QeUeDlVky5UhapqQGQh751keF6g6EFM9btM2EHvQfxcgDAxufowvxQUPkfTe+40EZ7s9GDbzJQiyw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1268 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h b/drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h new file mode 100644 index 000000000000..43bb07cef00a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/dfs/dfs_db.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DFS_DB_H +#define CL_DFS_DB_H + +#include "dfs/radar.h" +#include "utils/timer.h" + +#define CL_DFS_MAX_TBL_LINE 11 /* Radar Table Max Line */ +#define CL_DFS_MAX_PULSE 4 /* Max Pulses per Interrupt */ +#define CL_DFS_PULSE_BUF_SIZE 64 /* Radar Pulse buffer size */ +#define CL_DFS_PULSE_BUF_MASK 0x03F /* Radar Pulse buffer cyclic mask */ +#define CL_DFS_PULSE_WINDOW 100 /* Radar Pulse search window [ms] */ +#define CL_DFS_MIN_PULSE_TRIG 1 /* Minimum Pulse trigger num */ +#define CL_DFS_MAX_20MHZ_CH 25 /* Maximum 20MHz channels */ +#define CL_DFS_MIN_CH 52 /* Min DFS channel */ +#define CL_DFS_MAX_CH 144 /* Max DFS channel */ +#define CL_DFS_MIN_WEATHER_CH 120 /* Min DFS weather channel */ +#define CL_DFS_MAX_WEATHER_CH 128 /* Max DFS weather channel */ +#define CL_DFS_CAC_TIME 60 /* DFS CAC Time */ +#define CL_DFS_WEATHER_CAC_TIME 600 /* DFS weather channel CAC Time */ +#define CL_DFS_VALIDATION_TIME 1800 /* Validation time */ +#define CL_DFS_CE_CSA_CNT 10 /* According to CE regulation must leave within 1 sec */ +#define CL_DFS_LONG_MIN_WIDTH 20 /* Min Long Pulse Width */ +#define CL_DFS_LONG_FALSE_WIDTH 10 /* Low width signals indicates of false detections */ +#define CL_DFS_LONG_FALSE_IND 6 /* False indication while searching for long sequence */ +#define CL_DFS_FCC_CSA_CNT 2 /* According to FCC regulation must leave within 200ms */ +#define CL_DFS_SAFE_WIDTH 10 /* False detection not expected for high width signals */ +#define CL_DFS_BUF_SIZE 128 /* Max buffer size for loading channels DBs from NVRAM */ +#define CL_DFS_STAGGERED_CHEC_LEN 4 /* Staggered check length */ +#define CL_DFS_ONE_MINUTE 60 /* One minute [s] */ +#define CL_DFS_ONE_MINUTE_MS 60000 /* One minute [ms] */ +#define CL_DFS_ONE_SEC_MS 1000 /* One Second in [ms] */ +#define CL_DFS_THREE_SEC_MS 3000 /* Three Second in [ms] */ +#define CL_DFS_FIVE_SEC_MS 5000 /* Five Second in [ms] */ +#define CL_DFS_TEN_SEC_MS 10000 /* Twn Seconds in [ms] */ +#define CL_DFS_MIN_IDLE 10 /* Minimum consecutive idle decisions to start OCC */ +#define CL_DFS_CONCEAL_CNT 10 /* Maximum concealed pulses search */ +#define CL_DFS_FILTER_DELAY 100 /* Delay the decision by 100ms */ +#define CL_DFS_FILTER_PRI_MARGIN 10 /* PRI search margin */ +#define CL_DFS_LTP_PPB_MARGIN 2 /* Low TP PPB margin */ +#define CL_DFS_MAX_STAGGERED 3 /* Max Staggered patterns */ + +enum cl_radar_waveform { + RADAR_WAVEFORM_SHORT, + RADAR_WAVEFORM_LONG, + RADAR_WAVEFORM_STAGGERED, + RADAR_WAVEFORM_SEVERE +}; + +struct cl_radar_type { + u8 id; + s32 min_width; + s32 max_width; + s32 tol_width; + s32 min_pri; + s32 max_pri; + s32 tol_pri; + s32 tol_freq; + u8 min_burst; + u8 ppb; + u8 trig_count; + enum cl_radar_waveform waveform; +}; + +struct cl_dfs_pulse { + s32 freq : 8; /* Radar Frequency offset [units of 4MHz] */ + u32 fom : 8; /* Figure of Merit */ + u32 width : 8; /* Pulse Width [units of 2 micro sec] */ + u32 occ : 1; /* OCC indication for Primary/Secondary channel */ + u32 res1 : 7; /* Reserve */ + u32 pri : 16; /* Pulse Repetition Frequency */ + u32 res2 : 16; + unsigned long time; /* Pulse Receive Time */ +}; + +struct cl_dfs_db { + bool en; + + struct { + bool started; + bool requested; + } cac; + + enum cl_dbg_level dbg_lvl; + enum cl_reg_standard dfs_standard; + struct cl_radar_type *radar_type; + u8 csa_cnt; + + u8 min_pulse_eeq; + u8 buf_idx; + u8 radar_type_cnt; + u16 search_window; + u16 last_pri; + u16 max_interrupt_diff; + u32 pulse_cnt; + u32 severe_env_pulse_cnt; + struct cl_dfs_pulse dfs_pulse[CL_DFS_PULSE_BUF_SIZE]; + struct cl_dfs_pulse pulse_buffer[CL_DFS_PULSE_BUF_SIZE]; + u8 long_pulse_count; + u32 last_long_pulse_ts; + u8 short_pulse_count; + u8 long_pri_match_count; +}; + +#endif /* CL_DFS_DB_H */ From patchwork Thu Jun 17 15:59:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3EE3C2B9F4 for ; Thu, 17 Jun 2021 16:04:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E6C5613EC for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/dfs/radar.h | 55 ++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/dfs/radar.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/dfs/radar.h b/drivers/net/wireless/celeno/cl8k/dfs/radar.h new file mode 100644 index 000000000000..bed037cce624 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/dfs/radar.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_RADAR_H +#define CL_RADAR_H + + #include + +/* Number of pulses in a radar event structure */ +#define RADAR_PULSE_MAX 4 + +/* + * Structure used to store information regarding + * E2A radar events in the driver + */ +struct cl_radar_elem { + struct cl_radar_pulse_array *radarbuf_ptr; + dma_addr_t dma_addr; +}; + +/* Bit mapping inside a radar pulse element */ +struct cl_radar_pulse { + u64 freq : 8; + u64 fom : 8; + u64 len : 8; /* Pulse length timer */ + u64 measure_cnt : 2; /* Measure count */ + u64 rsv1 : 6; /* Reserve1 */ + u64 rep : 16; /* PRI */ + u64 rsv2 : 16; /* Reserve2 */ +}; + +/* Definition of an array of radar pulses */ +struct cl_radar_pulse_array { + /* Buffer containing the radar pulses */ + u64 pulse[RADAR_PULSE_MAX]; + /* Number of valid pulses in the buffer */ + u32 cnt; +}; + +struct cl_radar_queue_elem { + struct list_head list; + struct cl_hw *cl_hw; + struct cl_radar_elem radar_elem; + unsigned long time; +}; + +struct cl_hw; + +void cl_radar_init(struct cl_hw *cl_hw); +void cl_radar_push(struct cl_hw *cl_hw, struct cl_radar_elem *radar_elem); +void cl_radar_tasklet_schedule(struct cl_hw *cl_hw); +void cl_radar_flush(struct cl_hw *cl_hw); +void cl_radar_close(struct cl_hw *cl_hw); + +#endif /* CL_RADAR_H */ From patchwork Thu Jun 17 15:59:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B38E1C48BE5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 064/256] cl8k: add drv_ops.h Date: Thu, 17 Jun 2021 15:59:11 +0000 Message-Id: <20210617160223.160998-65-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:43 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1e31b6cd-eeb1-4c27-221b-08d931a97b92 X-MS-TrafficTypeDiagnostic: AM9P192MB1268: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Iu/iJ5xwQ6igNQzGfnNgiaMhlIwyEEcPvuaYBMjBDFMIeoAPh/8lfZhKk6gIUMp2iMge7XNGvKLF+9V1Yp+w3lOFe2QhfayCVuk89uil+PkQIYnLGy9HlKDX4T2JGdVEEuTEoVBuOIKfexE8Jcjt6Z5sUDchJORL6AFsZhQpe/UWQ2Pt4FBItXv7nKvo8MBRScmt0F2O65slmAWLr26rp4avqP+o8hIE/XdZEPIuf6ZJZwYEjXdbx+ubnCGDraASqtPZV1TTWZkv8DrZ+xhLsClTRa75LGj1Pq9Fa6OESOQdEoth2GRkR50o7k4IenwOwtlnfOYydahE3nWI/WKbwd3IVZQsaldND+UvJiUQBQU6WlZwOLbpUU40Q6gNaE3O+BY0DzhoF3SCu6HSl/sJVpfL3koUvQPKQ3B1gc0oYWD0SIcm+wI4t2fbqgHClFk7gzCSdUb8saUYvsI3cIgz/UVoTJrEKbIND5DdqnIyjC0nksxXbg0iNBlPHnTGAFjEudLmpIh+cUlD/WryEPhFjbiMtxrt82/zVx9GVzEIIDeo50NvM3EoMTMjrjLmautoDtZRub79prZ9Vy/8Dw5pT+aBALyjc1CswH5sSdB8v4ElbRI3jL5zB2rnmzk2MzEfSsKtmXRWC7tXjhBLoW+3LPGhevyc5e9ETaEaOc+NCY0zSRf0UxgVSE/5TmpARWm2JefopipNgbI1iBPZ+tUuow== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6486002)(956004)(54906003)(4326008)(2616005)(186003)(38100700002)(16526019)(8676002)(5660300002)(38350700002)(8936002)(26005)(2906002)(6512007)(9686003)(52116002)(83380400001)(6916009)(66946007)(66556008)(66476007)(86362001)(55236004)(498600001)(6666004)(6506007)(1076003)(107886003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bx7ST5HodbKLeLLnWweVerxGAGMhQHGTpIfTJ9rjJuKLBk0/ryfwxTiXmQTZApcaXF2O/mSagW/oXfCsqPVQ6ddAlOASjxAwoBrQb8/06c2kxg+g20u6qFA4L7BPLgH7JqUIlvGrsqQG2AHqsEfQE6ksSb0xcWJqSE+6oFLLAN6ictX6fhrRnx8zpl9VmJNoqy+1he5nfM9LndcqGo7EA2HBKOYbilYAuHukpy1c+R0mug9eQYTA9hIfFPzzr7CH+OpI2QwaAodM09PGM/Cl/+k2tHMDVtVHdDa3Rv4rgkkVtcYlxHzp0zQL8KGRGIonmG57kS/uN3/UyFeY15lgO3AjuTD0WzHW7zMVTVwZHe2Pc3d/Gb8pFbZkSi/QTrNgzrwQAB7spmqH+S+cT2pUosZBLlML1lhic7znTIHv+SmSBQX0mWo26rD4idoNgMiPvmrlCg17KktZIF6Vd00TGl39GUCScSdf0vZl8Ef+Iqh2+EvRu4uxM6vvNcKZoScG/TwI0Pb5Oip1xsQgv3cEwO+9pmJJ7OHS5v5ZjA5ApWn4DezjL3Vd7l+wd9OYRDUeDc1jk46OQe5zlJJGMbC3GFCzros+eEysscqmmyQwIRgSri2hZGjtHBKoLSw8pAEtWsMvJYF/BX3B1bN4MYfVpsDQSDheetWrEB+D1r7qLk1dbSD3wrTJZ1HBkWYD/w2IQJDI32mbWvHk+VzA6cgbWwnt6K1/Phmxp5jydoibI3ongfn+Bc7gQ/BcB+Mna80U72q76cTSXVbK+GFSj/IjOcCmIzRnulmngc8JhS1VgChObbxceLEl0qxI40UeQRyFjeK14kGhbRFCspacvAmITmVt046/Pc6f/9dSS4Z00oX5sWaMunO2GTJQFK2ZPDjNiy7Cz57S4M6uUXKg3KLgDptPDttIRitGFjKSIfBNRTmn3E7C9yPywyN9ZfL2GNxDJnfRrc8SekRcOzN68l9wAIcKkXK5SbT8rrWxl+IRWbL6fOnb+pRGzkCMASsjBYAgXniZdaqW1B11+hTzDUR9vj4zjWIqmHTer05RU94p/2fpx0n0rTWgv0sBhcIOBs0vo1gkAD5F2RYB+nb/XfpGcCGDzlQXhMc/mqs+Dz1OFM+ggLUnajdknN49nODttKs01a8nKgOz2MIaJArwQeBurYsw2D9k9sFTbNDWStzQOHnUDLa/DqG0X2Rq2pLm+Y6M1HAZyvF9AtAeJa0zsLD80eDzKvhG2JxElPNUbkI1zIkChxstYf6d6BCphPfj0+7NDsMC8Hm+QKCeWEgiJ/N9IS24BtW/iioA27zQAleeZtlTTUHe3m8XfEVZ5vVunovF X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e31b6cd-eeb1-4c27-221b-08d931a97b92 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:44.4224 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hQM9hrnzsx4KE5r4CO4UWbX6EXen5pB3rBBvO8IgXKg4flnQqTkBsyWjiZNUMJdsk+/+L1NGwNZK2d+R8Rerrw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1268 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/drv_ops.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/drv_ops.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/drv_ops.h b/drivers/net/wireless/celeno/cl8k/drv_ops.h new file mode 100644 index 000000000000..3e8f56d9d6f6 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/drv_ops.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DRV_OPS_H +#define CL_DRV_OPS_H + +#include "hw.h" +#include "tx/sw_txhdr.h" + +static inline int cl_drv_ops_msg_fw_send(struct cl_hw *cl_hw, + const void *msg_params, + bool background) +{ + if (cl_hw->drv_ops->msg_fw_send) + return cl_hw->drv_ops->msg_fw_send(cl_hw, msg_params, + background); + return 0; +} + +static inline void cl_drv_ops_pkt_fw_send(struct cl_hw *cl_hw, + struct cl_sw_txhdr *sw_txhdr, + struct cl_tx_queue *tx_queue) +{ + if (cl_hw->drv_ops->pkt_fw_send) + cl_hw->drv_ops->pkt_fw_send(cl_hw, sw_txhdr, tx_queue); +} + +#endif /* CL_DRV_OPS_H */ From patchwork Thu Jun 17 15:59:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B5CDC49361 for ; Thu, 17 Jun 2021 16:05:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 17F36613EC for ; Thu, 17 Jun 2021 16:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230321AbhFQQH4 (ORCPT ); Thu, 17 Jun 2021 12:07:56 -0400 Received: from mail-eopbgr60088.outbound.protection.outlook.com ([40.107.6.88]:43502 "EHLO EUR04-DB3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230343AbhFQQHV (ORCPT ); Thu, 17 Jun 2021 12:07:21 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Uj1FxXuvWALUPEaVeJqNDG0lwLnyuYNmiN7Ikq/WM1Ac9wCANb6+k24Ej3nlHwYls00uJVCfj364obslAYKWHUEs+3oErIi0LM5LfYWcH+eS+RC2kXJP1+E9YWcftwPEzqyCBCbu/F04ASpsQBW2pxnz0B3J2TADTeqqXyjKJxQhdwxt0TvdtQf4WfmH66E8HN/cjd+2OlqDn36OgiEBDoiRF7Sdf2qVVz/HidWWtXoihqjdK2MroEvCHoh5AmRYMF5U619bBBOQN2II4GJM24qkHIem9oLjaVnOWYvG5fljGdVVGIsZeJJwfAQW4P/CDaVk2p0VZYeIaVFx5Bb5Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4cjOdv6YHHTrKvwUsD3mkmqmLXnaW2KBGs6NgRsjjgU=; b=GsePQ2c8jpT9LRwfk2vhwSRhpA/WIqMZ6ECEYYfaAAn0H02vI6TD4HuV/ZQ15t3rUwozNBSAC2KDcly1VoTsMtow0ph/flr6G1C3j69yu/B7rD1jcpwwqLgS+5MiyatE3gcNJYbIqjLvfiIN6rrpIdCH/7m6Htn08jEEbcceItrBpZ06yKscHicsyQZzy4Uw21dPma1K/Yv4MnBmvQkL9Feq3+b2RXislPvJopgn45jKpirtzR+oibBT+NJ4rY3P/2WBBitloe/SHojQC9rXRAM8F4vZ56AaOkFErL4SB83QpMdeOt4j6W6yv2nQ3actuOa1MJ/uaXLGbcPPQsl7Cw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4cjOdv6YHHTrKvwUsD3mkmqmLXnaW2KBGs6NgRsjjgU=; b=nkRxHzBDLtwbanPJsf28aiKoxY5XmUle1nyDYoMsGV15WYR/FUpS3so+BdArvAqMf4U1Xpyaog/mT/1PfRwfQuOaGA9AeY3j6sYcv13kMGKqNkdItgDdV26338hIp3wGwGu78TY6Qk2Da+t3qrrQ51LzVNzQ9mhlesbotrk+Zwo= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1268.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a9::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:04:20 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:20 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 065/256] cl8k: add dsp.c Date: Thu, 17 Jun 2021 15:59:12 +0000 Message-Id: <20210617160223.160998-66-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f010e6b-10e5-4f3a-665c-08d931a97c45 X-MS-TrafficTypeDiagnostic: AM9P192MB1268: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1417; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rqucWJ69504ceQ5GtI2SBTklHgqgHkVdcoZxi6HMRDsbIOjYxBV8DmLWs01gRXdS5OZlmlyflmBULHi3kh2eJG9JxxHxRQYoMJzQ1WLNEq3Vmfck1aAE50eMKMfplAY8ZRHioUs1I6R8EmvVPCUmj4PPLknkkMWbZbUntnIK14ZHwjMN2+ON6x8sWiAG2TsKac+dzyJC4FqCneCap3/BPu8rCD9RUBXVQXaaSGRtMukfiNUnH5PeCgCjcAR+jBrCQ9HxQOoNgrNLCSUFMm4ituCZUK57P+Ds/ZYBKGTGYR686U4pdCNv5R6HldMtujdCFmlpA1McPA+t9UzMDyKCVbGGvkMPfhoNw/Y4DJiJg31c0kJWXj0MLgYGWJSZnYLZ/gDNJK4oz6OTJHT8n7569VPByyD2jlRDyllIIqcUc3czePt2NouxPo7nIyNT5QQgc36nZvy+sHYJfLuqq7yVoqSTDnZqpC94b522deWFJF6LyZch9Dqh+yXuajWssiFdn/qst+VGHwY9KK37vQwZm7axwaCCgopf3xin6PCPqXStlZ/tBMm9zPiYHAAscJuCAwRqW7vciSrEKEaty7pA5RvQrC/izr70KKlkBN6vIqUGTnaV/S2G2D1/l4AiDZPk2penyzMVrX/xVQsGl5TIGTHXeNReCBKGJ7KXmEf81DSkAG9Vz4YmsnZfl+FuuMkaLZN0mBIKPf46dgzQmpUMNw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6486002)(956004)(54906003)(4326008)(2616005)(186003)(38100700002)(16526019)(8676002)(5660300002)(38350700002)(8936002)(26005)(2906002)(6512007)(9686003)(52116002)(83380400001)(6916009)(66946007)(66556008)(66476007)(86362001)(55236004)(498600001)(6666004)(6506007)(1076003)(30864003)(107886003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VbT2p9ZAe/wdRN6EGJTK5KigPyIbK3djF2YPCrSBk/bO3OEUkfEDMzj98lDgpKUdd0TTHgYZeBtS5WYJEvk/Xlh9zHh6yVTEkn8BprJrkDoeltxV+OH3Fijvd1qvmzQv3XdNXuH/lBwEYflN8F6WhPsi3rHX3bCExl4phFCryjdAnASLi9FHCY8F1UlWk9h199B5fTSy83SqivMomVWvarzX0uwgHqWF1zrBt+zovm2uvPMxT9jb9QDdV0y7+e2gNMc18wuo1RRlY15r+pnNRuCQ6jXUxLQKEa1fTetv/S79DgiPGOAMcDOcHwmRyDf+r7ygZpD6DrEbUL7LPVScIPXPV7elvAWtvHagyyCTqzknxIT/A5UZqXGtwJgJ3wFvxXGIe8U6Q1y/yesELRTIFTHniowM5dGbkDyqYCnReTdvyt/pxKivkK1v/SdefMVuU7dunihjSZd7QLcy9pVCptru6/E/d6dS0ve5A5W54nyOUbNnUdCb4d4ijolPDDur5E/rU1O5ozJ+YGimTEU2Z4sA4Ud47uV6X0X9QojJ4f6xVL6+r8fx1biTo0efZdQP3psl1qcHMLqdVfTCZ8TztREMQiWwuXIg0mwT1okLK+GwgbDho9XJglz06Zm1x0V1lSOzu9ezfXTGoSULtcRjQMleyySb4zzysvb9K25jfAnV7Mz87/wVqShvRieRrLrmwF/uf/ViQV3M38DmlBL1AZ5rxymj8xxxl3GDTHvPJiUMkRCg1PRbHfx5YHQwI44vpaFl1J+N64DOwEPwn6SjibLyumCTBN+5Sg2SzURxGI/nJul/r7p0N68Wfxfi6olbNEz2TEwx+USBtmkjgkORPyG7PLhfh9ydVR8ze519Papw/KTkJuJFAAFNyddCksw/ig4dAB7zLzJtEDAwbxscG5yzga+tceOSdrUu0eRdJ1/F2vncmlvMWuVsGnTy/F2Y2iqL3tJM3ya4q4XfBw5jzduvOd33aJlyHC0xm6rX9LigfVigN8YjvdzxaBbAGBBYjUxKetfrjoiNcHwSAA++l+TVLXFINeSOOlAy+x5a1ufM9EKc9b/HfeWAeY3Eht3swaYz8xlUQ/PtLyJ+1ebTzGdYfOydti5/x+81gRJdKiJgNJ7xgV3jcJxwk7dRFSYiym5LI2CLDPzdLLUyYBgW6EZKZFmpk5CsQvEXk+50G8103CgkecAc/Tbxkg9Hz2hoXyfhAsN8w00T1QMfBQTWzpLXifn50A9jKbKzPHTraks7aoP5/seleL5doPuKESAHkRSmC5Yqq1s7ChuJAbudxjYKzlfW4hd3b1t7+qrJcIu5OKOUuBaq4kt0P4sDy3VN X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f010e6b-10e5-4f3a-665c-08d931a97c45 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:45.6819 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PUXhGISd/kF68uUMeAiFNLXP0SBXX34N/Uwa5MjUetSnHl/9Z4uJeUzj2gYTX/vHe+Jqg7LFDPTUYVDmJqV9uw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1268 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/dsp.c | 611 +++++++++++++++++++++++++ 1 file changed, 611 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/dsp.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/dsp.c b/drivers/net/wireless/celeno/cl8k/dsp.c new file mode 100644 index 000000000000..cf9646cd1ed4 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/dsp.c @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "reg/reg_modem_gcu.h" +#include "reg/reg_macdsp_api.h" +#include "reg/reg_cmu.h" +#include "reg/reg_access.h" +#include "reg/ceva.h" +#include "dsp.h" +#include "hw.h" +#include + +#define BUSY_WAIT_LIMIT 10000 + +static int dsp_busy_wait(struct cl_hw *cl_hw, u32 control_reg) +{ + int i; + + for (i = 0; i < BUSY_WAIT_LIMIT; i++) { + /* Poll Bit29 to verify DMA transfer has ended. */ + if ((cl_reg_read(cl_hw, control_reg) & 0x20000000) == 0) + return 0; + + cpu_relax(); + } + + return -EIO; +} + +static void cl_dsp_boot(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + + if (cl_hw_is_tcv0(cl_hw)) { + /* Disable ceva_free_clk */ + cmu_phy_0_clk_en_ceva_0_clk_en_setf(chip, 0); + /* Assert Ceva reset */ + cmu_phy_0_rst_ceva_0_global_rst_n_setf(chip, 0); + } else { + /* Disable ceva_free_clk */ + cmu_phy_1_clk_en_ceva_1_clk_en_setf(chip, 0); + /* Assert Ceva reset */ + cmu_phy_1_rst_ceva_1_global_rst_n_setf(chip, 0); + } + + /* Set Ceva boot=1 */ + modem_gcu_ceva_ctrl_boot_setf(cl_hw, 1); + /* Set Ceva vector */ + modem_gcu_ceva_vec_set(cl_hw, 0); + + if (cl_hw_is_tcv0(cl_hw)) { + /* Enable ceva_clk */ + cmu_phy_0_clk_en_ceva_0_clk_en_setf(chip, 1); + /* Disabel ceva_clk */ + cmu_phy_0_clk_en_ceva_0_clk_en_setf(chip, 0); + /* De-Assert Ceva reset - Reset Release */ + cmu_phy_0_rst_ceva_0_global_rst_n_setf(chip, 1); + /* Enable ceva_clk */ + cmu_phy_0_clk_en_ceva_0_clk_en_setf(chip, 1); + } else { + /* Enable ceva_clk */ + cmu_phy_1_clk_en_ceva_1_clk_en_setf(chip, 1); + /* Disabel ceva_clk */ + cmu_phy_1_clk_en_ceva_1_clk_en_setf(chip, 0); + /* De-Assert Ceva reset - Reset Release */ + cmu_phy_1_rst_ceva_1_global_rst_n_setf(chip, 1); + /* Enable ceva_clk */ + cmu_phy_1_clk_en_ceva_1_clk_en_setf(chip, 1); + } + + /* Release Ceva external_wait */ + modem_gcu_ceva_ctrl_external_wait_setf(cl_hw, 0); + /* Set Ceva boot=0 */ + modem_gcu_ceva_ctrl_boot_setf(cl_hw, 0); +} + +static void config_dma_for_code_copy(struct cl_hw *cl_hw, u32 page) +{ + /* Configure Program DMA to copy FW code from Shared PMEM to internal PMEM. */ + + /* External address to read from. */ + cl_reg_write(cl_hw, CEVA_CPM_PDEA_REG, CEVA_SHARED_PMEM_BASE_ADDR_INTERNAL); + /* Internal address to write to. */ + cl_reg_write(cl_hw, CEVA_CPM_PDIA_REG, CEVA_SHARED_PMEM_SIZE * page); + /* Page size */ + cl_reg_write(cl_hw, CEVA_CPM_PDTC_REG, CEVA_SHARED_PMEM_SIZE); +} + +static void config_dma_for_external_data_copy(struct cl_hw *cl_hw) +{ + /* Configure Program DMA to copy FW code from Shared XMEM to internal XMEM. */ + + /* External address to read from. */ + cl_reg_write(cl_hw, CEVA_CPM_DDEA_REG, CEVA_SHARED_XMEM_BASE_ADDR_INTERNAL); + /* Internal address to write to. */ + cl_reg_write(cl_hw, CEVA_CPM_DDIA_REG, 0); + /* Page size + DMA direction is write */ + cl_reg_write(cl_hw, CEVA_CPM_DDTC_REG, + CEVA_SHARED_XMEM_SIZE | CEVA_CPM_DDTC_WRITE_COMMAND); +} + +static int cl_dsp_hex_load(struct cl_hw *cl_hw, const u8 *buf, + off_t offset, size_t size, size_t buf_size) +{ + u8 single_buf[4] = {0}; + u32 bin_data = 0; + u8 next_byte; + u8 byte_num = 0; + int ret = 0; + ssize_t oft = 0; + size_t real_size = min(size * 3, buf_size); + /* + * CEVA_SHARED_PMEM_BASE_ADDR_FROM_HOST is global and we don't + * want to add TCV reg offset. + */ + bool chip_reg = (offset == CEVA_SHARED_PMEM_BASE_ADDR_FROM_HOST); + + if (buf_size % 3) { + cl_dbg_err(cl_hw, "DSP size %zu must be divided by 3 !!!\n", + buf_size); + return -EINVAL; + } + + while (oft < real_size) { + memcpy(single_buf, buf + oft, 3); + /* Each line contains 2 hex digits + a line feed, i.e. 3 bytes */ + ret = kstrtou8(single_buf, 16, &next_byte); + if (ret < 0) { + cl_dbg_err(cl_hw, + "ret = %d, oft = %zu," + "single_buf = 0x%x 0x%x 0x%x 0x%x\n", + ret, oft, single_buf[0], single_buf[1], + single_buf[2], single_buf[3]); + return ret; + } + + /* Little-endian order. */ + bin_data += next_byte << (8 * byte_num); + byte_num = (byte_num + 1) % 4; + + /* Read 4 lines from the file, and then write. */ + if (byte_num == 0) { + if (chip_reg) + cl_reg_write_chip(cl_hw->chip, offset, bin_data); + else + cl_reg_write_direct(cl_hw, offset, bin_data); + offset += 4; + bin_data = 0; + } + + memset(&single_buf, 0, sizeof(single_buf)); + oft += 3; + } + + return 0; +} + +static int load_dsp_code(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + u32 real_size; + u32 page; + const struct firmware *fw; + size_t size = 0; + u8 *buf = NULL; + char path_name[CL_PATH_MAX] = {0}; + int ret; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", + cl_hw->conf->ce_dsp_code); + + cl_dbg_verbose(cl_hw, "from %s\n", cl_hw->conf->ce_dsp_code); + + ret = request_firmware(&fw, path_name, chip->dev); + + if (ret) { + cl_dbg_err(cl_hw, "Failed to get %s, with error: %x!\n", + path_name, ret); + goto out; + } + + size = fw->size; + buf = (u8 *)fw->data; + + for (page = 0; page < CEVA_MAX_PAGES; page++) { + /* Copy DSP code (one page each time) */ + ret = cl_dsp_hex_load(cl_hw, buf, + CEVA_SHARED_PMEM_BASE_ADDR_FROM_HOST, + CEVA_SHARED_PMEM_SIZE, size); + if (ret != 0) { + cl_dbg_err(cl_hw, "Failed to load pmem page 0x%x!\n", page); + break; + } + + config_dma_for_code_copy(cl_hw, page); + ret = dsp_busy_wait(cl_hw, CEVA_CPM_PDTC_REG); + + if (ret) { + cl_dbg_err(cl_hw, "dsp_busy_wait failed!\n"); + goto out; + } + + real_size = min_t(u32, CEVA_SHARED_PMEM_SIZE * 3, size); + buf += real_size; + size -= real_size; + } + +out: + release_firmware(fw); + + return ret; +} + +static int load_dsp_data(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + const struct firmware *fw; + size_t size = 0; + char path_name[CL_PATH_MAX] = {0}; + int ret; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", + cl_hw->conf->ce_dsp_data); + + cl_dbg_verbose(cl_hw, "from %s\n", cl_hw->conf->ce_dsp_data); + + ret = request_firmware(&fw, path_name, chip->dev); + if (ret) { + cl_dbg_err(cl_hw, "Failed to get %s, with error: %x!\n", + path_name, ret); + goto out; + } + + size = fw->size; + + ret = cl_dsp_hex_load(cl_hw, fw->data, REG_MACDSP_API_BASE_ADDR, + CEVA_DSP_DATA_SIZE, size); + if (ret) { + cl_dbg_err(cl_hw, "Failed to load HEX file\n"); + goto out; + } +out: + release_firmware(fw); + + return ret; +} + +static int load_dsp_external_data(struct cl_hw *cl_hw) +{ + /* + * Shared XMEM is not accessible by host. + * Copy the XMEM section to DRAM first and then use CEVA internal DMA to copy to + * SHARED XMEM. + */ + struct cl_chip *chip = cl_hw->chip; + const struct firmware *fw; + size_t size = 0; + char path_name[CL_PATH_MAX] = {0}; + int ret; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", + cl_hw->conf->ce_dsp_external_data); + + cl_dbg_verbose(cl_hw, "from %s\n", cl_hw->conf->ce_dsp_external_data); + + ret = request_firmware(&fw, path_name, chip->dev); + if (ret) { + cl_dbg_err(cl_hw, "Failed to get %s, with error: %x!\n", + path_name, ret); + goto out; + } + + size = fw->size; + + ret = cl_dsp_hex_load(cl_hw, fw->data, REG_MACDSP_API_BASE_ADDR, + CEVA_DSP_EXT_DATA_SIZE, size); + + if (ret) { + cl_dbg_err(cl_hw, "Failed to load HEX file\n"); + goto out; + } + + config_dma_for_external_data_copy(cl_hw); + ret = dsp_busy_wait(cl_hw, CEVA_CPM_DDTC_REG); + + if (ret) { + cl_dbg_err(cl_hw, "dsp_busy_wait failed!\n"); + goto out; + } + +out: + release_firmware(fw); + + return ret; +} + +static bool cl_dsp_is_universal_file(struct cl_chip *chip) +{ + return (cl_chip_is_tcv0_enabled(chip) && + cl_chip_is_tcv1_enabled(chip) && + !strcmp(chip->cl_hw_tcv0->conf->ce_dsp_code, + chip->cl_hw_tcv1->conf->ce_dsp_code)); +} + +static int load_dsp_code_dual(struct cl_chip *chip, const char *filename) +{ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + u32 real_size; + u32 page; + const struct firmware *fw; + size_t size = 0; + u8 *buf = NULL; + char path_name[CL_PATH_MAX] = {0}; + int ret; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", filename); + cl_dbg_chip_verbose(chip, "from %s\n", filename); + ret = request_firmware(&fw, path_name, chip->dev); + + if (ret) { + cl_dbg_chip_err(chip, "Failed to get %s, with error: %x!\n", + path_name, ret); + goto out; + } + + size = fw->size; + buf = (u8 *)fw->data; + + for (page = 0; page < CEVA_MAX_PAGES; page++) { + /* Copy DSP code (one page each time) */ + ret = cl_dsp_hex_load(chip->cl_hw_tcv0, buf, + CEVA_SHARED_PMEM_BASE_ADDR_FROM_HOST, + CEVA_SHARED_PMEM_SIZE, size); + if (ret) { + cl_dbg_chip_err(chip, "Failed to load pmem page 0x%x!\n", page); + break; + } + + config_dma_for_code_copy(cl_hw_tcv0, page); + ret = dsp_busy_wait(cl_hw_tcv0, CEVA_CPM_PDTC_REG); + + if (ret) { + cl_dbg_err(cl_hw_tcv0, "dsp_busy_wait failed\n"); + goto out; + } + + config_dma_for_code_copy(cl_hw_tcv1, page); + ret = dsp_busy_wait(cl_hw_tcv1, CEVA_CPM_PDTC_REG); + + if (ret) { + cl_dbg_err(cl_hw_tcv1, "dsp_busy_wait failed\n"); + goto out; + } + + real_size = min_t(u32, CEVA_SHARED_PMEM_SIZE * 3, size); + buf += real_size; + size -= real_size; + } + +out: + release_firmware(fw); + + return ret; +} + +static int load_dsp_external_data_dual(struct cl_chip *chip, const char *filename) +{ + /* + * Shared XMEM is not accessible by host. + * Copy the XMEM section to DRAM first and then use CEVA internal DMA to copy to + * SHARED XMEM. + */ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + const struct firmware *fw; + size_t size = 0; + char path_name[CL_PATH_MAX] = {0}; + int ret; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", filename); + cl_dbg_chip_verbose(chip, "from %s\n", filename); + ret = request_firmware(&fw, path_name, chip->dev); + + if (ret) { + cl_dbg_chip_err(chip, "Failed to get %s, with error: %x!\n", + path_name, ret); + goto out; + } + + size = fw->size; + + /* TCV0 */ + ret = cl_dsp_hex_load(cl_hw_tcv0, fw->data, REG_MACDSP_API_BASE_ADDR, + CEVA_DSP_EXT_DATA_SIZE, size); + + if (ret) { + cl_dbg_err(cl_hw_tcv0, "Failed to load HEX file\n"); + goto out; + } + + config_dma_for_external_data_copy(cl_hw_tcv0); + ret = dsp_busy_wait(cl_hw_tcv0, CEVA_CPM_DDTC_REG); + + if (ret) { + cl_dbg_err(cl_hw_tcv0, "dsp_busy_wait failed!\n"); + goto out; + } + + /* TCV1 */ + ret = cl_dsp_hex_load(cl_hw_tcv1, fw->data, REG_MACDSP_API_BASE_ADDR, + CEVA_DSP_EXT_DATA_SIZE, size); + + if (ret) { + cl_dbg_err(cl_hw_tcv1, "Failed to load HEX file\n"); + goto out; + } + + config_dma_for_external_data_copy(cl_hw_tcv1); + ret = dsp_busy_wait(cl_hw_tcv1, CEVA_CPM_DDTC_REG); + + if (ret) { + cl_dbg_err(cl_hw_tcv1, "dsp_busy_wait failed!\n"); + goto out; + } + +out: + release_firmware(fw); + + return ret; +} + +static int load_dsp_data_dual(struct cl_chip *chip, const char *filename) +{ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + const struct firmware *fw; + size_t size = 0; + char path_name[CL_PATH_MAX] = {0}; + int ret; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", filename); + cl_dbg_chip_verbose(chip, "from %s\n", filename); + ret = request_firmware(&fw, path_name, chip->dev); + + if (ret) { + cl_dbg_chip_err(chip, "Failed to get %s, with error: %x!\n", + path_name, ret); + goto out; + } + + size = fw->size; + + ret = cl_dsp_hex_load(cl_hw_tcv0, fw->data, + REG_MACDSP_API_BASE_ADDR, + CEVA_DSP_DATA_SIZE, size); + + if (ret != 0) { + cl_dbg_err(cl_hw_tcv0, "Failed to load HEX file\n"); + goto out; + } + + ret = cl_dsp_hex_load(cl_hw_tcv1, fw->data, + REG_MACDSP_API_BASE_ADDR, + CEVA_DSP_DATA_SIZE, size); + + if (ret != 0) { + cl_dbg_err(cl_hw_tcv1, "Failed to load HEX file\n"); + goto out; + } + +out: + release_firmware(fw); + + return ret; +} + +static void print_ceva_core_info(struct cl_hw *cl_hw) +{ + cl_dbg_trace(cl_hw, "CEVA_CORE_VERSION_ADDR=0x%X.\n", + cl_reg_read(cl_hw, CEVA_CORE_VERSION_ADDR)); + cl_dbg_trace(cl_hw, "CEVA_CORE_ID_ADDR=0x%X.\n", + cl_reg_read(cl_hw, CEVA_CORE_ID_ADDR)); +} + +static int cl_dsp_load_dual(struct cl_chip *chip) +{ + int ret = 0; + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + struct cl_tcv_conf *tcv0_conf = cl_hw_tcv0->conf; + + modem_gcu_ceva_ctrl_external_wait_setf(cl_hw_tcv0, 0x1); + modem_gcu_ceva_ctrl_external_wait_setf(cl_hw_tcv1, 0x1); + + print_ceva_core_info(cl_hw_tcv0); + print_ceva_core_info(cl_hw_tcv1); + + ret = load_dsp_code_dual(chip, tcv0_conf->ce_dsp_code); + if (ret != 0) { + cl_dbg_chip_err(chip, + "Failed to load DSP code. Error code %d.\n", + ret); + return ret; + } + + ret = load_dsp_external_data_dual(chip, tcv0_conf->ce_dsp_external_data); + if (ret != 0) { + cl_dbg_chip_err(chip, + "Failed to load DSP external data. Error code %d.\n", + ret); + return ret; + } + + ret = load_dsp_data_dual(chip, tcv0_conf->ce_dsp_data); + if (ret != 0) { + cl_dbg_chip_err(chip, + "Failed to load DSP data. Error code %d.\n", + ret); + return ret; + } + + macdsp_api_config_space_set(cl_hw_tcv0, 0); + /* Release DSP wait. */ + cl_dsp_boot(cl_hw_tcv0); + + macdsp_api_config_space_set(cl_hw_tcv1, 0); + /* Release DSP wait. */ + cl_dsp_boot(cl_hw_tcv1); + + return ret; +} + +static int _cl_dsp_load(struct cl_hw *cl_hw) +{ + int ret = 0; + + modem_gcu_ceva_ctrl_external_wait_setf(cl_hw, 0x1); + print_ceva_core_info(cl_hw); + + ret = load_dsp_code(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "Failed to load DSP code %d\n", ret); + return ret; + } + + ret = load_dsp_external_data(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "Failed to load DSP external data %d\n", ret); + return ret; + } + + ret = load_dsp_data(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "Failed to load DSP data %d\n", ret); + return ret; + } + + macdsp_api_config_space_set(cl_hw, 0); + /* Release DSP wait */ + cl_dsp_boot(cl_hw); + + return ret; +} + +int cl_dsp_load_regular(struct cl_chip *chip) +{ + int ret = 0; + + if (cl_dsp_is_universal_file(chip)) + return cl_dsp_load_dual(chip); + + if (cl_chip_is_tcv0_enabled(chip)) { + ret = _cl_dsp_load(chip->cl_hw_tcv0); + if (ret) + return ret; + } + + if (cl_chip_is_tcv1_enabled(chip)) { + ret = _cl_dsp_load(chip->cl_hw_tcv1); + if (ret) + return ret; + } + + return ret; +} + +int cl_dsp_load_recovery(struct cl_hw *cl_hw) +{ + int ret = 0; + + modem_gcu_ceva_ctrl_external_wait_setf(cl_hw, 0x1); + + ret = load_dsp_external_data(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "Failed to load DSP external data %d\n", ret); + return ret; + } + + ret = load_dsp_data(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "Failed to load DSP data %d\n", ret); + return ret; + } + + macdsp_api_config_space_set(cl_hw, 0); + /* Release DSP wait. */ + cl_dsp_boot(cl_hw); + + return ret; +} From patchwork Thu Jun 17 15:59:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97CCAC2B9F4 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/dsp.h | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/dsp.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/dsp.h b/drivers/net/wireless/celeno/cl8k/dsp.h new file mode 100644 index 000000000000..f9802c479e47 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/dsp.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DSP_H +#define CL_DSP_H + +#include "chip.h" + +/* + * cl_dsp_load_regular - Load DSP firmware for both TCV's. + * + * @chip - chip pointer. + * + * Return value: 0 upon success, negative errno code upon failure. + */ +int cl_dsp_load_regular(struct cl_chip *chip); + +/* + * cl_dsp_load_recovery - Load only DSP data for single TCV. + * + * @chip - chip pointer. + * + * Return value: 0 upon success, negative errno code upon failure. + */ +int cl_dsp_load_recovery(struct cl_hw *cl_hw); + +#endif /* CL_DSP_LOAD_H */ From patchwork Thu Jun 17 15:59:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB398C2B9F4 for ; Thu, 17 Jun 2021 16:05:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BBA72613FF for ; Thu, 17 Jun 2021 16:05:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231877AbhFQQID (ORCPT ); Thu, 17 Jun 2021 12:08:03 -0400 Received: from mail-eopbgr60049.outbound.protection.outlook.com ([40.107.6.49]:40639 "EHLO EUR04-DB3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232149AbhFQQHZ (ORCPT ); Thu, 17 Jun 2021 12:07:25 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZeScvxE6x1RupBjdKXUTHyJMBWNTMfBUgNgSyaA0etHc/pSZ+zQNRztgrZ1j1hFjvtEewb6cL2lR7GY8Vi8axew8XoVkVuM9Vp+vbm6DvM62a1oCJnZn+VbgtFul3fbpHp2o7X0VcAbyJMCkioJEkI8l0wNZ5reQTfUOBk1OB/dfarCEAhbMbOi0qhMM50vCd+Ncp4yMKEbq3bDsJuGEJCqBNTnuCnyfTL1oJT5ZLriVRYlPD2MeiqvcBkpcJc9jfACdgf1Bu5fddFAl0w0ESIwqCRhwRRePEE7gwt/t7iJj3Ivk8kLYxAjZ68tEC/GsGBIbLCqzMsq+sK17P0jzJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bN28uCS62slwZdlXsiwM8KaLfOO0AzkbFCotKTzsae0=; b=Pvf2i++pWY0fjSi6r3dSKETgUvWYdWCazkKZYH1h8RDmJW9ta4+7Du/eqoOtXrXwI55kjkPs3PIEnMk8V8pfR9bo+dejGvPxPedQChRxif0gUhsw0bj9/T+J8rxBZ3CPoPLM0sWDGeIi15nFGDcs+YCOXPH7D7tfTT7hIwlzHjStAuQRUYrFSMunK8dGrVHXMx8if5VTs0pB+DvgfBSQws2+tAxQCBbyR2UMgIukvizLWzrgEHeE7Y9ukm7Ofeg09h1ARc1Uk12x93CaDta5y1Un9UlWPs8Lt/1yNXcROmKVjJ/gVckPixF0I3BJu3dn8yMGf6VWa3UqFTTtsTiHEQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bN28uCS62slwZdlXsiwM8KaLfOO0AzkbFCotKTzsae0=; b=0TVaKUhicWCq/IgV+tviBfTXLh3AGfVeLU84uO1C8PPJsG/v9P6uYkf+LQ2sbe9E54RL3j7ZH2MQeRjgrBA2+aJJCAEWJ/TbHEg/xJ6kXvFcU4hp99j54RHIMgN+MRuqNHlCVX6jjZh8pTTbBjsuTCzmg1frJDb8IuZ9hblt6bQ= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1268.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a9::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:04:21 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:21 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/e2p.c | 664 +++++++++++++++++++++++++ 1 file changed, 664 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/e2p.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/e2p.c b/drivers/net/wireless/celeno/cl8k/e2p.c new file mode 100644 index 000000000000..0e51d88b042a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/e2p.c @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include +#include "utils/utils.h" +#include "utils/file.h" +#include "chip.h" +#include "e2p.h" +#include "reg/reg_access.h" +#include "config.h" + +#define EEPROM_VERSION 2 + +/* EEPROM Parameters - Suitable for ATMEL AT24C16BN */ +#define E2P_SIZE 0x800 /* 2KB = 16Kbit */ +#define E2P_PAGE_SIZE 0x10 /* 16 Bytes */ +#define E2P_PAGE_MASK (E2P_PAGE_SIZE - 1) /* 0xF */ +#define E2P_PAGE_SHIFT 0x4 + +#define PAGE_NUM(addr) ((addr) >> E2P_PAGE_SHIFT) +#define PAGE_OFF(addr) ((addr) & E2P_PAGE_MASK) + +enum bit_num { + BIT0, + BIT1, + BIT2, + BIT3, + BIT4, + BIT5, + BIT6, + BIT7, + BIT8, + BIT9, + BIT10, + BIT11, + BIT12, + BIT13, + BIT14, + BIT15, + BIT16, + BIT17, + BIT18, + BIT19, + BIT20, + BIT21, + BIT22, + BIT23, + BIT24, + BIT25, + BIT26, + BIT27, + BIT28, + BIT29, + BIT30, + BIT31 +}; + +/* + * MACSYS_I2C:: PRERLO (0x0) - Clock Prescale register lo-byte + * Width: 8, Access: RW, Reset: 0xff. + */ +#define I2C_PRERLO (I2C_REG_BASE_ADDR + 0x0) + +/* + * MACSYS_I2C:: PRERHI (0x4) - Clock Prescale register lo-byte + * Width: 8, Access: RW, Reset: 0xff. + */ +#define I2C_PRERHI (I2C_REG_BASE_ADDR + 0x4) + +/* + * MACSYS_I2C:: CTR (0x8) - Control Register + * Width: 8, Access: RW, Reset: 0x00. + */ +#define I2C_CTR (I2C_REG_BASE_ADDR + 0x8) + +#define EN (BIT7) /* ‘1’ the core is enabled. */ + +/* + * MACSYS_I2C:: TXR_RXR (0xC) - Transmit Register - Data + * Width: 8, Access: W, Reset: 0x00. + */ +#define I2C_TXD (I2C_REG_BASE_ADDR + 0xC) + +/* 7:0 TXD */ +#define TXD (BIT0) /* Next byte to transmit via I2C */ + +#define TXD_MASK (0xFF << TXD) + +/* + * MACSYS_I2C:: TXR_RXR (0xC) - Transmit Register - Address + * Width: 8, Access: W, Reset: 0x00. + */ +#define I2C_TXADDR (I2C_REG_BASE_ADDR + 0xC) + +/* + * 7:1 TXADDR + * 0 RDWR + */ +#define TXADDR (BIT1) /* I2C Slave Address */ +#define RDWR (BIT0) /* ‘1’ = reading from slave. ‘0’ = writing to slave. */ + +#define TXADDR_MASK (0x7F << TXADDR) + +/* + * MACSYS_I2C:: TXR_RXR (0xC) - Receive Register + * Width: 8, Access: R, Reset: 0x00. + */ +#define I2C_RXD (I2C_REG_BASE_ADDR + 0xC) + +/* 7:0 RXD */ +#define RXD (BIT0) /* Last byte received via I2C. */ +#define RXD_MASK (0xFF << RXD) + +/* + * MACSYS_I2C:: CR_SR (0x10) - Command Register + * Width: 8, Access: WC, Reset: 0x00. + */ +#define I2C_CR (I2C_REG_BASE_ADDR + 0x10) + +/* + * 7 STA + * 6 STO + * 5 RD + * 4 WR + * 3 ACK + * 2:1 RES + * 0 IACK + */ +#define STA (BIT7) /* Generate (repeated) start condition. */ +#define STO (BIT6) /* Generate stop condition. */ +#define RD (BIT5) /* Read from slave. */ +#define WR (BIT4) /* Write to slave. */ +#define ACK (BIT3) /* When a receiver, sent ACK (ACK = ‘0’) or NACK (NACK = ‘1’). */ +#define IACK (BIT0) /* Interrupt acknowledge, When set, clears a pending interrupt. */ + +/* + * MACSYS_I2C:: CR_SR (0x10) - Status Register + * Width: 8, Access: R, Reset: 0x00. + */ +#define I2C_SR (I2C_REG_BASE_ADDR + 0x10) + +/* + * 7 RX_ACK - Received acknowledge from slave - ‘1’ = No acknowledge received. + * 6 BUSY - I2C bus busy - ‘1’ after START signal detected. ‘0’ after STOP signal detected. + * 5 AL - Arbitration lost - This bit is set when the core lost arbitration. + * 4:2 RES + * 1 TIP - Transfer in progress. ‘1’ when transferring data. ‘0’ when transfer complete. + * 0 IF - Set when interrupt is pending, cause a processor interrupt if the IEN bit is set. + */ +#define RX_ACK (BIT7) +#define BUSY (BIT6) +#define AL (BIT5) +#define TIP (BIT1) +#define IF (BIT0) + +#define I2C_EEPROM_ADDR(page) (0xA0 | (((page) >> 3) & 0xE)) /* [1-0-1-0-P2-P1-P0-0] */ + +/* E2P_MAX_POLLS should not exceed 12 iterations (attemts) */ +#define E2P_MAX_POLLS 10 +#define E2P_INITIAL_DELAY 32 + +static int i2c_poll_xfer_acked(struct cl_chip *chip) +{ + u32 val = cl_reg_read_chip(chip, I2C_SR); + int cnt = E2P_MAX_POLLS; + unsigned long delay = E2P_INITIAL_DELAY; + + while ((val & BIT(TIP)) && cnt--) { + udelay(delay); + val = cl_reg_read_chip(chip, I2C_SR); + delay <<= 1; + } + ++cnt; + + while ((val & BIT(RX_ACK)) && cnt--) { + udelay(delay); + val = cl_reg_read_chip(chip, I2C_SR); + delay <<= 1; + } + + if (cnt >= 0) + return 0; + + cl_dbg_chip_err(chip, "ACK FAILED\n"); + cl_dbg_chip_trace(chip, "I2C_POLL_XFER_ACKED: val=%Xh, cnt=%d.\n", val, cnt); + + return -1; +} + +static int i2c_poll_xfer_no_acked(struct cl_chip *chip) +{ + u32 val = cl_reg_read_chip(chip, I2C_SR); + int cnt = E2P_MAX_POLLS; + unsigned long delay = E2P_INITIAL_DELAY; + + while ((val & BIT(TIP)) && cnt--) { + udelay(delay); + val = cl_reg_read_chip(chip, I2C_SR); + delay <<= 1; + } + + ++cnt; + + while (!(val & BIT(RX_ACK)) && cnt--) { + udelay(delay); + val = cl_reg_read_chip(chip, I2C_SR); + delay <<= 1; + } + + if (cnt >= 0) + return 0; + + cl_dbg_chip_err(chip, "NO ACK FAILED\n"); + cl_dbg_chip_trace(chip, "I2C_POLL_XFER_NO_ACKED: val=%Xh, cnt=%d.\n", val, cnt); + + return -1; +} + +static void i2c_write_start(struct cl_chip *chip, u16 page) +{ + u32 addr = I2C_EEPROM_ADDR(page) & TXADDR_MASK; + + cl_reg_write_chip(chip, I2C_TXADDR, addr); + cl_reg_write_chip(chip, I2C_CR, BIT(STA) | BIT(WR)); +} + +static void i2c_write(struct cl_chip *chip, u8 data) +{ + cl_reg_write_chip(chip, I2C_TXD, data & TXD_MASK); + cl_reg_write_chip(chip, I2C_CR, BIT(WR)); +} + +static void i2c_write_stop(struct cl_chip *chip, u8 data) +{ + cl_reg_write_chip(chip, I2C_TXD, data & TXD_MASK); + cl_reg_write_chip(chip, I2C_CR, BIT(STO) | BIT(WR)); +} + +static void i2c_read_start(struct cl_chip *chip, u16 page) +{ + u32 addr = (I2C_EEPROM_ADDR(page) & TXADDR_MASK) | BIT(RDWR); + + cl_reg_write_chip(chip, I2C_TXADDR, addr); + cl_reg_write_chip(chip, I2C_CR, BIT(STA) | BIT(WR)); +} + +static int i2c_read_stop(struct cl_chip *chip, u8 *data) +{ + cl_reg_write_chip(chip, I2C_CR, BIT(STO) | BIT(RD) | BIT(ACK)); + if (i2c_poll_xfer_no_acked(chip) == -1) + return -1; + *data = cl_reg_read_chip(chip, I2C_RXD) & RXD_MASK; + return 0; +} + +static void e2p_reg_set_bit(struct cl_chip *chip, u32 reg, u32 bit) +{ + u32 regval = cl_reg_read_chip(chip, reg); + + regval |= bit; + cl_reg_write_chip(chip, reg, regval); +} + +static void e2p_reg_clear_bit(struct cl_chip *chip, u32 reg, u32 bit) +{ + u32 regval = cl_reg_read_chip(chip, reg); + + regval &= ~bit; + cl_reg_write_chip(chip, reg, regval); +} + +static void e2p_enable(struct cl_chip *chip) +{ + /* Disable I2C Core */ + e2p_reg_clear_bit(chip, I2C_CTR, BIT(EN)); + + /* + * Set Pre-Scaler LO + * pclk = 240MHz, desired SCL = 400KHz. + * Prescale = [240e6 / (5*400e3) ] – 1 = 120 -1 = 119 = 77h + */ + cl_reg_write_chip(chip, I2C_PRERLO, 0x77); + + /* Set Pre-Scaler HI */ + cl_reg_write_chip(chip, I2C_PRERHI, 0x0); + + /* Enable I2C Core */ + e2p_reg_set_bit(chip, I2C_CTR, BIT(EN)); +} + +static int e2p_read_byte(struct cl_chip *chip, u16 addr, u8 *pbyte) +{ + if (addr > E2P_SIZE) { + cl_dbg_chip_err(chip, "Wrong addr or len\n"); + return -1; + } + + /* Clock in the address to read from. */ + i2c_write_start(chip, PAGE_NUM(addr)); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + + /* Addr 8 lsbits are 4 bits page lsbits or`ed with 4 bits page offset */ + i2c_write(chip, addr); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + + /* Read single byte */ + i2c_read_start(chip, PAGE_NUM(addr)); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + + return i2c_read_stop(chip, pbyte); +} + +static int e2p_write_page(struct cl_chip *chip, u16 addr, u8 *val, u16 num_of_bytes) +{ + /* This is a write page (up to 16 bytes) operation indicating the offset to write to. */ + int i; + + if (num_of_bytes > E2P_PAGE_SIZE) + return -1; + + /* Clock in the address to write to. */ + i2c_write_start(chip, PAGE_NUM(addr)); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + + /* Addr 8 lsbits are 4 bits page lsbits or`ed with 4 bits page offset */ + i2c_write(chip, addr); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + + /* Clock in the data to write. */ + for (i = 0; i < (num_of_bytes - 1); i++, val++) { + i2c_write(chip, *val); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + } + + /* Clock in the last data byte to write */ + i2c_write_stop(chip, *val); + if (i2c_poll_xfer_acked(chip) == -1) + return -1; + + /* Make sure to wait before moving to another page */ + mdelay(4); + + return 0; +} + +static int e2p_write_block(struct cl_chip *chip, u16 addr, u16 num_of_bytes, u8 *val) +{ + u16 bytes_on_curr_page = 0, bytes_left_to_write = num_of_bytes; + + do { + bytes_on_curr_page = E2P_PAGE_SIZE - PAGE_OFF(addr); + bytes_on_curr_page = min(bytes_left_to_write, bytes_on_curr_page); + bytes_left_to_write -= bytes_on_curr_page; + + if (e2p_write_page(chip, addr, val, bytes_on_curr_page) == -1) { + cl_dbg_chip_err(chip, "Error writing page %u offset %u\n", + PAGE_NUM(addr), PAGE_OFF(addr)); + /* Written less bytes than num_of_bytes */ + return 0; + } + + addr += bytes_on_curr_page; + val += bytes_on_curr_page; + } while (bytes_left_to_write); + + return num_of_bytes - bytes_left_to_write; +} + +static int e2p_load_dev(struct cl_chip *chip) +{ + u8 *cache = (u8 *)chip->eeprom_cache; + u16 i; + + for (i = 0; i < EEPROM_NUM_BYTES; i++) + if (e2p_read_byte(chip, i, &cache[i]) == -1) + return -1; + + return 0; +} + +static int e2p_dev_read_block(struct cl_chip *chip, u16 addr, u16 num_of_bytes, u8 *val) +{ + void *read_block = NULL; + + if (!val) + return -EFAULT; + + if (addr + num_of_bytes > EEPROM_NUM_BYTES) + return -ENXIO; + + read_block = (u8 *)chip->eeprom_cache + addr; + memcpy(val, read_block, num_of_bytes); + + return num_of_bytes; +} + +static int e2p_dev_write_block(struct cl_chip *chip, u16 addr, u16 num_of_bytes, u8 *val) +{ + int bytes_written = -EIO; + void *write_block = NULL; + + if (!val) + return -EFAULT; + + if (addr + num_of_bytes > EEPROM_NUM_BYTES) + return -ENXIO; + + bytes_written = e2p_write_block(chip, addr, num_of_bytes, val); + write_block = (u8 *)chip->eeprom_cache + addr; + memcpy(write_block, val, num_of_bytes); + + return bytes_written; +} + +static int e2p_load_bin(struct cl_chip *chip) +{ + char filename[CL_FILENAME_MAX]; + size_t size = 0; + + if (cl_chip_is_6g(chip)) + snprintf(filename, sizeof(filename), + "eeprom/eeprom%u_cl80x6.bin", chip->idx); + else + snprintf(filename, sizeof(filename), + "eeprom/eeprom%u_cl80x0.bin", chip->idx); + + size = cl_file_open_and_read(chip, filename, + (char **)&chip->eeprom_cache); + + if (size != EEPROM_NUM_BYTES) { + cl_dbg_chip_err(chip, + "Invalid EEPROM size - %s (actual %zu) (expected %d)\n", + filename, size, EEPROM_NUM_BYTES); + return -1; + } + + return 0; +} + +static int e2p_bin_write_block(struct cl_chip *chip, u16 addr, u16 num_of_bytes, u8 *val) +{ + return -EOPNOTSUPP; +} + +static int e2p_bin_read_block(struct cl_chip *chip, u16 addr, u16 num_of_bytes, u8 *val) +{ + u8 *base; + u16 *offset_addr; + + if (!val) + return -EFAULT; + + if (addr + num_of_bytes > EEPROM_NUM_BYTES) + return -ENXIO; + + base = (u8 *)chip->eeprom_cache; + offset_addr = (u16 *)(base + addr); + memmove(val, offset_addr, num_of_bytes); + + return num_of_bytes; +} + +static int cl_e2p_init_bin(struct cl_chip *chip) +{ + if (e2p_load_bin(chip)) + return -1; + + chip->eeprom_read_block = e2p_bin_read_block; + chip->eeprom_write_block = e2p_bin_write_block; + + return 0; +} + +static int cl_e2p_init_dev(struct cl_chip *chip) +{ + chip->eeprom_cache = kzalloc(EEPROM_NUM_BYTES, GFP_KERNEL); + + if (!chip->eeprom_cache) + return -1; + + e2p_enable(chip); + + if (e2p_load_dev(chip)) + return -1; + + chip->eeprom_read_block = e2p_dev_read_block; + chip->eeprom_write_block = e2p_dev_write_block; + + return 0; +} + +int cl_e2p_init(struct cl_chip *chip) +{ + u8 mode = chip->conf->ce_eeprom_mode; + + if (mode == E2P_MODE_BIN) + return cl_e2p_init_bin(chip); + else if (mode == E2P_MODE_EEPROM) + return cl_e2p_init_dev(chip); + + return -1; +} + +void cl_e2p_close(struct cl_chip *chip) +{ + kfree(chip->eeprom_cache); +} + +int cl_e2p_write(struct cl_chip *chip, u8 *data, u16 size, u16 addr) +{ + if (size != chip->eeprom_write_block(chip, addr, size, data)) { + cl_dbg_chip_err(chip, "Error writing eeprom addr 0x%x\n", addr); + return -1; + } + + return 0; +} + +int cl_e2p_read(struct cl_chip *chip, u8 *data, u16 size, u16 addr) +{ + if (size != chip->eeprom_read_block(chip, addr, size, data)) { + cl_dbg_chip_err(chip, "Error reading eeprom addr 0x%x\n", addr); + return -1; + } + + return 0; +} + +int cl_e2p_write_version(struct cl_chip *chip) +{ + u8 version = EEPROM_VERSION; + + if (chip->eeprom_cache->general.version != version) + return cl_e2p_write(chip, &version, + SIZE_GEN_VERSION, ADDR_GEN_VERSION); + + return 0; +} + +int cl_e2p_get_addr(struct wiphy *wiphy, struct wireless_dev *wdev, + void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u16 addr = *(u16 *)data; + u16 len = *((u16 *)data + 1); + int reply_len; + struct cl_e2p_get_reply *reply = NULL; + struct cl_chip *chip = cl_hw->chip; + int ret = 0; + u32 end = EEPROM_NUM_BYTES; + u8 mode = chip->conf->ce_eeprom_mode; + + reply_len = sizeof(struct cl_e2p_get_reply) + len; + reply = kzalloc(reply_len, GFP_KERNEL); + + if (!reply) + return -ENOMEM; + + reply->e2p_mode = mode; + + cl_dbg_trace(cl_hw, "addr %u len %u\n", addr, len); + + if (end < (addr + len)) { + cl_dbg_err(cl_hw, + "size check failed: last addr = 0x%x, eeprom memory end" + " = 0x%x, eeprom_mode = %u\n", (addr + len), + end, mode); + ret = -EINVAL; + goto e2p_fail; + } + + if (len != chip->eeprom_read_block(chip, addr, len, reply->e2p_data)) { + cl_dbg_err(cl_hw, "Error reading eeprom addr 0x%x: len %u\n", + addr, len); + ret = -EXDEV; + goto e2p_fail; + } + + ret = cl_vendor_reply(cl_hw, (void *)reply, reply_len); + +e2p_fail: + kfree(reply); + + return ret; +} + +int cl_e2p_set_addr(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + u16 addr = *(u16 *)data; + u16 len = *((u16 *)data + 1); + u8 *e2p_data = (u8 *)((u16 *)data + 2); + u32 end = EEPROM_NUM_BYTES; + + cl_dbg_trace(cl_hw, "addr %u len %u\n", addr, len); + + if (end < (addr + len)) { + cl_dbg_err(cl_hw, "Invalid E2P addr 0x%x, valid are: 0 - %u\n", + addr, end); + return -EINVAL; + } + + return cl_e2p_write(cl_hw->chip, e2p_data, len, addr); +} + +int cl_e2p_set_wiring_id(struct wiphy *wiphy, struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + struct cl_chip *chip = cl_hw->chip; + u8 wiring_id = *(u8 *)data; + + return cl_fem_set_wiring_id(chip, wiring_id); +} + +int cl_e2p_help(struct wiphy *wiphy, struct wireless_dev *wdev, + void *data, int data_len) +{ + struct cl_hw *cl_hw = WIPHY_TO_CL_HW(wiphy); + char *ret_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!ret_buf) + return -ENOMEM; + + snprintf(ret_buf, PAGE_SIZE, + "usage:\n" + "get addr
- Read value from specified addr\n" + "get mac - Read MAC address\n" + "get serial_number - Read serial number\n" + "get pwr_table_id - Read power table IDs\n" + "get freq_offset - Read frequency offset\n" + "get wiring_id - Read wiring ID\n" + "get fem_lut- Read FEM look up table\n" + "get platform_id - Read platform ID\n" + "get calib - Read calibrated offset for a given antenna and channel\n" + "get hexdump - Read entire eeprom\n" + "get table - Read entire eeprom and print in format of table\n" + "set addr
- Write value to specified address\n" + "set mac - Write MAC addr\n" + "set serial_number <32 characters> - Write serial number\n" + "set pwr_table_id - Write power table IDs\n" + "set wiring_id <0 - 255> - Write wiring-ID\n" + "set fem_lut -" + " Write FEM look up table\n" + "set platform_id - Write platform-id to eeprom\n" + "set freq_offset <0 - 959> - Write frequency offset to eeprom\n" + "set calib -" + " Write calibrated power and power offset for a given antenna and channel\n"); + + err = cl_vendor_reply(cl_hw, ret_buf, strlen(ret_buf)); + kfree(ret_buf); + + return err; +} + From patchwork Thu Jun 17 15:59:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E49A4C49361 for ; Thu, 17 Jun 2021 16:06:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF4E7613F9 for ; Thu, 17 Jun 2021 16:06:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233673AbhFQQIM (ORCPT ); Thu, 17 Jun 2021 12:08:12 -0400 Received: from mail-eopbgr60088.outbound.protection.outlook.com ([40.107.6.88]:43502 "EHLO EUR04-DB3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231326AbhFQQHc (ORCPT ); Thu, 17 Jun 2021 12:07:32 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BupSPGVRCY8IaudsdADTWSNmgqaRm/VgxO5O5QnXlsuPiBxbW3BYwZzoHYqxZfRPvHsPxclXAG6E/wwepEyRNDvJk0CUHa489cT7L2KZtzTsKG3xid0KGR7bS993Z2OsCALwhbmIiUbKphd5IJt7bL3rQzymfGXxoh6OrHQ76L+MIVgkCXKUfSE0+ND1NMQpCPuHWWSr+6P/7IxHHRlxs9Tz9myHPLUHNAol+ITGTC+rVm90+wgj7ID/DSvDGGzrRCOCnozbtXs9fg98C5aGkh91S4ohqFnPf/aaUCJ7fLmjJjLzwtac8kByGoV7RRcdp2Sde4UcVvsd6DvAp5jEoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rod/+7Qkhyw4UJhd97EfRp9Savc5EM6wA0cK5hvQA1M=; b=fnbHR4JoRcrSeYNUw0+jOqZG1nHwHgWMLVNv6G+Ps5i6zsUm9Pbm9dsx/yMKWUHijcBJcsBw5kN8QUCfiCkJ5gdVCWAO69tzxk5fJaXZX+jXNRDA9Xo1eHHayqWuf03pxF/jVMN2rrNtfXXiQQiSqAGYs8JBGOBqdW8XT5aayCayKo3VgVRqo5cJNF/LZtBa3aAMLDoiSZHyiF4smMFSNOaZ8ZbLnFZfN5pnDj1FH6dQ2LqNjpQblRmnCOcV7QRlf+5Jxt4gA7YjjfZvIST95ZyDHs6/U4+ke/PmYOKdHYkey5KFD8RRaLV25WbjyQEtdqRecheF5I3ubkefsG6CDw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rod/+7Qkhyw4UJhd97EfRp9Savc5EM6wA0cK5hvQA1M=; b=ztDNaSqDEjOWPAgCWthPhKsaQy1bYGmT40gp2PFd4UJKN+ngpebREBx1tKkPkod8uxquu7t/c5p+nJbg00nuH7NXPkgQP4qB09EQwxpjMMFkGtllJvbbyIumcDbDgoRO5ur2iMUrvjcwlZiwvwpSg3DaJr1PFcUd6AjQWJFU3HQ= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1268.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a9::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:04:21 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:21 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 069/256] cl8k: add edca.c Date: Thu, 17 Jun 2021 15:59:16 +0000 Message-Id: <20210617160223.160998-70-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:49 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 64835f21-14a9-4d31-9237-08d931a97f2e X-MS-TrafficTypeDiagnostic: AM9P192MB1268: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:480; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nLYfEJeSOXI4QoZ6JnVwyQYx50E7cio/kzYp9eu7V4Ps+Xr1gAh1dA/GXXL/EcltyK2O5M0JPb4tUn+FDlMm2NweiLlKn22esSzXdDuLnBbB4Zb5Id0BjD6RhSYTgpUzjCWmTo0i/g1DOj7RizIcNgJuXDsRCtIGN/cVgYtv0kFe4gfjUdBGqSwEIRSR+SRvnR3ZHdKooZwiRNrMGMiAn2AQhlhah8OoYQOjKV2YYWq/eevZsPBGtW4EBposoHPQzEBb1u8I7WmO5OO+/cMk+MblRgjBZE+Jacr/6Se10N1W6VxQQDo/Z+NnR7ywTyEsbLOSrWL2Kep53o4TDndhF/GnaTCxMtFSMbwwLLQ55YRX+jA3O1hnsHU+X+3FefZy/dGv9TyaENnfFFuJ+6iOC0N0CSviSxOMzLrYpnEz9xXO1pl7FJwKMnIRMuELVDDVxHCq1U/hrHGATChBIyNb3PpE7zR6zpmf0t9M8Yxy23CaWB+a8m46jmEWjqIaHF6+JDbdBGaM8dSrqRSqWT5mIu+Iw5eRXXn5ctyPmmWj1kO+WfTxb+l1C6BHTfkxZMYpb0FaZrKipDIze2uqOEKQlD+y8gjqeCZWa/Xa/23T+sPAihBcHHF+9AAuJ5xYechgxV+lg8aZRDg+xh3rjDsf/ix0qDyhCoyYmB5uLbZ1SYGl2H0jUF0UPi+832qYHIc+KOKrNit4tE36PTw+puEXzg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6486002)(956004)(54906003)(4326008)(2616005)(186003)(38100700002)(16526019)(8676002)(5660300002)(38350700002)(8936002)(26005)(2906002)(6512007)(9686003)(52116002)(83380400001)(6916009)(66946007)(66556008)(66476007)(86362001)(55236004)(498600001)(6666004)(6506007)(1076003)(107886003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ug5eYJ7T5qg+Z9/ce+bg+IIHgrdW48hr32Gr5X93bawk3wI08kLdStq75cKv1ZCarrS9hVgoUdyzkw3+0kkKViXUsl0spb6Y6DDOFUObHWDNWpukUVBzB5IpxXdw1U+PS85Tcu6jaD7NUXawwIhthtBCh1ouqbv4yAC5ALvDjdWX0kyIeDPz0xUUHFlB82owFgnXVqQwHy+3gI5oQBm30cBuqSXMz8Yg9D+fl7B1bzB5EUz9P7imx0Ihe3fKpAtrpc2pezFTZ+QcdTbfFFmSq5hFD/HQf+0ft8wA1i3ixrZkAAUHSIqYc6QqW9tCrB0N69+UjpY+UiqvDKOWFbe3gIb34tBPg1jpA+OVILr1VDNzqFqxe+RqK4HV7yYAaMj6aXqwHfVW0/RjV1QNu54uEei0erfrSl++9gLe3Fv5jeH/UAPi80/iZH8SAdqSHYhTRgoANyx84BdIHr8HMlCX1Eb2qdBe1RNszawm+W9GkTv+lcObjjhPtVUHu3BWQvVV8or8wIv3poy6gGNFZT+OqpqsKQEy8Y3UEsVwODY5ffpTGp1fRFDr1vPbFA86riwHJqqDb8lyha4XjiYoE2Lxd4CDT2VemVHLMhzZH+KKr4hR291F//AKJqTKgVS/BzLPoUmwxbPoBOz05ZRDV3CTVKiuEBncy7lxZKqhds1HiDQImvOMMh8BIPrY4MI/5ZXl5InIvCDjE90+aAfPYAdbLX83H8GqmQtVo8p0aIy7RewuvSgk9i6ZPltN4WlXJ9QsYuT5UPJnGD+B0pSjOD0JlrLkH22u0kixoVFJyzzDiH3CF9KV2SKPY1ciV9P0mh0ZsYavyAtCV+8V0xxLiobL1B63HFGb7zLS4cYN8uMSOQ4gDsO4yXL5H0rbfnmxSEvruzy9wIrgXu58toPJelweBHz9fOzClzc9KfXugknQDVoSh2Kyd73RdZ2XpE8JIne45eyCvchohfODeR4H9Ca2W3zmt/nt9k8l/ioetZugEnsrurSpWugY/xCG7LL4qMuGOQ/ooG2fHNPJKlRaQVdPzIjNkbkKyRZ3FRw3ThnBpCEPAF4oM6ynoNr4tVLVpTcVdq53qsYeHCgHBCjl+FmwKTd1qOPwM4QO5I68mGqrGyOK//anEL8g09/XhGWj0dLKUalj6pOhv1e3Ym08K4wVNxBhU8zL4L65ztXriRqJCO7YOphdSlAsy4EUJdJnMZ7dopZcRK14ZVmUgTN2jeLOw2zEcZaB62eg78MII62UkkO/j5w4SlY9+1TFuXMBXLOhuw+p9M60Q69WFpYkuMO8jDgKEEM5bvony3TvctHe5hmByfNptpby7lq4AiU0sq3r X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64835f21-14a9-4d31-9237-08d931a97f2e X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:50.4759 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 49I3VNZOMBhmIJKoatcySFbdYBXc7DDSfF7flt43+CmyAVDlCFFXr8pxhD3iGo4tqvhMaP2sal/iw8cbxmln8A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1268 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/edca.c | 265 ++++++++++++++++++++++++ 1 file changed, 265 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/edca.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/edca.c b/drivers/net/wireless/celeno/cl8k/edca.c new file mode 100644 index 000000000000..d17a7bd674c5 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/edca.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "edca.h" +#include "sta.h" +#include "vendor_cmd.h" +#include "fw/msg_tx.h" +#include "utils/utils.h" + +static u8 conv_to_fw_ac[EDCA_AC_MAX] = { + [EDCA_AC_BE] = AC_BE, + [EDCA_AC_BK] = AC_BK, + [EDCA_AC_VI] = AC_VI, + [EDCA_AC_VO] = AC_VO +}; + +static const char *edca_ac_str[EDCA_AC_MAX] = { + [EDCA_AC_BE] = "BE", + [EDCA_AC_BK] = "BK", + [EDCA_AC_VI] = "VI", + [EDCA_AC_VO] = "VO" +}; + +static int cl_edca_print(struct cl_hw *cl_hw) +{ + u8 ac = 0; + struct edca_params *params; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "---------------------------------------\n" + "| ac | aifsn | cw_min | cw_max | txop |\n" + "|----+-------+--------+--------+------|\n"); + + for (ac = 0; ac < AC_MAX; ac++) { + params = &cl_hw->edca_db.hw_params[ac]; + cl_snprintf(&buf, &len, &buf_size, + "| %s | %5u | %6u | %6u | %4u |\n", + edca_ac_str[ac], params->aifsn, params->cw_min, + params->cw_max, params->txop); + } + + cl_snprintf(&buf, &len, &buf_size, + "---------------------------------------\n\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static void cl_edca_set_conf(struct cl_hw *cl_hw, u8 ac) +{ + struct edca_params params = { + .aifsn = cl_hw->conf->ce_wmm_aifsn[ac], + .cw_min = cl_hw->conf->ce_wmm_cwmin[ac], + .cw_max = cl_hw->conf->ce_wmm_cwmax[ac], + .txop = cl_hw->conf->ce_wmm_txop[ac] + }; + + cl_edca_set(cl_hw, ac, ¶ms, NULL); +} + +static void cl_edca_ac_set(struct cl_hw *cl_hw, u8 ac, u8 aifsn, u8 cw_min, u8 cw_max, u16 txop) +{ + pr_debug("ac = %u, aifsn = %u, cw_min = %u, cw_max = %u, txop = %u\n", + ac, aifsn, cw_min, cw_max, txop); + + cl_hw->conf->ce_wmm_aifsn[ac] = aifsn; + cl_hw->conf->ce_wmm_cwmin[ac] = cw_min; + cl_hw->conf->ce_wmm_cwmax[ac] = cw_max; + cl_hw->conf->ce_wmm_txop[ac] = txop; + + cl_edca_set_conf(cl_hw, ac); +} + +static void cl_edca_aifsn_set(struct cl_hw *cl_hw, s32 aifsn[AC_MAX]) +{ + u8 ac = 0; + + pr_debug("Set aifsn: BE = %d, BK = %d, VI = %d, VO = %d\n", + aifsn[0], aifsn[1], aifsn[2], aifsn[3]); + + for (ac = 0; ac < AC_MAX; ac++) { + cl_hw->conf->ce_wmm_aifsn[ac] = (u8)aifsn[ac]; + cl_edca_set_conf(cl_hw, ac); + } +} + +static void cl_edca_cwmin_set(struct cl_hw *cl_hw, s32 cw_min[AC_MAX]) +{ + u8 ac = 0; + + pr_debug("Set cw_min: BE = %d, BK = %d, VI = %d, VO = %d\n", + cw_min[0], cw_min[1], cw_min[2], cw_min[3]); + + for (ac = 0; ac < AC_MAX; ac++) { + cl_hw->conf->ce_wmm_cwmin[ac] = (u8)cw_min[ac]; + cl_edca_set_conf(cl_hw, ac); + } +} + +static void cl_edca_cwmax_set(struct cl_hw *cl_hw, s32 cw_max[AC_MAX]) +{ + u8 ac = 0; + + pr_debug("Set cw_max: BE = %d, BK = %d, VI = %d, VO = %d\n", + cw_max[0], cw_max[1], cw_max[2], cw_max[3]); + + for (ac = 0; ac < AC_MAX; ac++) { + cl_hw->conf->ce_wmm_cwmax[ac] = (u8)cw_max[ac]; + cl_edca_set_conf(cl_hw, ac); + } +} + +static void cl_edca_txop_set(struct cl_hw *cl_hw, s32 txop[AC_MAX]) +{ + u8 ac = 0; + + pr_debug("Set txop: BE = %d, BK = %d, VI = %d, VO = %d\n", + txop[0], txop[1], txop[2], txop[3]); + + for (ac = 0; ac < AC_MAX; ac++) { + cl_hw->conf->ce_wmm_txop[ac] = (u16)txop[ac]; + cl_edca_set_conf(cl_hw, ac); + } +} + +static int cl_edca_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "edca usage:\n" + "-a : Print current configuration\n" + "-b : Set per AC [0-BE,1-BK,2-VI,3-VO].[aifsn].[cw_min]." + "[cw_max].[txop]\n" + "-c : Set aifsn [BE].[BK].[VI].[VO]\n" + "-d : Set cw_min [BE].[BK].[VI].[VO]\n" + "-e : Set cw_max [BE].[BK].[VI].[VO]\n" + "-f : Set txop [BE].[BK].[VI].[VO]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +void cl_edca_hw_conf(struct cl_hw *cl_hw) +{ + u8 ac = 0; + struct cl_tcv_conf *conf = cl_hw->conf; + + for (ac = 0; ac < AC_MAX; ac++) { + struct edca_params params = { + .aifsn = conf->ce_wmm_aifsn[ac], + .cw_min = conf->ce_wmm_cwmin[ac], + .cw_max = conf->ce_wmm_cwmax[ac], + .txop = conf->ce_wmm_txop[ac] + }; + + cl_edca_set(cl_hw, ac, ¶ms, NULL); + } +} + +void cl_edca_set(struct cl_hw *cl_hw, u8 ac, struct edca_params *params, + struct ieee80211_he_mu_edca_param_ac_rec *mu_edca) +{ + u32 edca_reg_val = 0; + + if (ac >= AC_MAX) { + pr_err("%s: Invalid AC index\n", __func__); + return; + } + + edca_reg_val = (u32)(params->aifsn); + edca_reg_val |= (u32)(params->cw_min << 4); + edca_reg_val |= (u32)(params->cw_max << 8); + edca_reg_val |= (u32)(params->txop << 12); + + memcpy(&cl_hw->edca_db.hw_params[ac], params, sizeof(struct edca_params)); + + cl_msg_tx_set_edca(cl_hw, conv_to_fw_ac[ac], edca_reg_val, mu_edca); + + cl_dbg_trace(cl_hw, "EDCA-%s: aifsn=%u, cw_min=%u, cw_max=%u, txop=%u\n", + edca_ac_str[ac], params->aifsn, params->cw_min, params->cw_max, params->txop); +} + +void cl_edca_restore_conf(struct cl_hw *cl_hw, u8 ac) +{ + cl_edca_set_conf(cl_hw, ac); +} + +void cl_edca_recovery(struct cl_hw *cl_hw) +{ + u8 ac; + + for (ac = 0; ac < AC_MAX; ac++) + cl_edca_set(cl_hw, ac, &cl_hw->edca_db.hw_params[ac], NULL); +} + +int cl_edca_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + u8 ac, aifsn, cw_min, cw_max; + u16 txop; + + switch (cli_params->option) { + case 'a': + return cl_edca_print(cl_hw); + case 'b': + if (cli_params->num_params != 5) + goto err_num_of_arg; + + ac = (u8)cli_params->params[0]; + aifsn = (u8)cli_params->params[1]; + cw_min = (u8)cli_params->params[2]; + cw_max = (u8)cli_params->params[3]; + txop = (u16)cli_params->params[4]; + + cl_edca_ac_set(cl_hw, ac, aifsn, cw_min, cw_max, txop); + break; + case 'c': + if (cli_params->num_params != AC_MAX) + goto err_num_of_arg; + + cl_edca_aifsn_set(cl_hw, cli_params->params); + break; + case 'd': + if (cli_params->num_params != AC_MAX) + goto err_num_of_arg; + + cl_edca_cwmin_set(cl_hw, cli_params->params); + break; + case 'e': + if (cli_params->num_params != AC_MAX) + goto err_num_of_arg; + + cl_edca_cwmax_set(cl_hw, cli_params->params); + break; + case 'f': + if (cli_params->num_params != AC_MAX) + goto err_num_of_arg; + + cl_edca_txop_set(cl_hw, cli_params->params); + break; + case '?': + return cl_edca_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + break; + } + + return 0; + +err_num_of_arg: + pr_err("wrong number of arguments\n"); + return 0; +} From patchwork Thu Jun 17 15:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EFBCC49EA3 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 071/256] cl8k: add ela.c Date: Thu, 17 Jun 2021 15:59:18 +0000 Message-Id: <20210617160223.160998-72-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:51 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 50d8d5a9-e88a-4aba-ff40-08d931a9806c X-MS-TrafficTypeDiagnostic: AM9P192MB1268: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:186; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MdRdv99scJbH/8RV5NYjbVPz2cGv2+0DO7cVObDWCeZINrB+vU0qHSpWdK7TK4oCVmoROwEqQLHS4DfQ3FQlL6Nl/q3MFHnSwfhNWyuwgvsCQsoepau4idGgkVSRT+gmIIg7k1/BimV74ockdDAO++vsf4DY52OZU3XyxyCmGuxLgaHdXhXSEoSeoEZuDSvoLsesdRsG6fad1LAWYIC5GG8f5yXJTOcUinieWzbLZ6g3EOVo04dMQkY0VmSpFQ3n0NVtfGXs0SdAmkH14NRlam0EszxRchZHPddMn1ust14cT7c9liFMh4qxzDujJ1HXTfHmdEmer+shcsfMu5nulJbgP0eN6IuKnI3T7HNPlbJUAW/pFim4/+APcc/jpYycURO29BJDrCdCirQSDhZdTResGtW2acz4RJgC+cvrS5ENQtmj3Z9/8xobluSG1KIRKQ5q3ewnuGrTKi9DzPluC3Q1yNmnKP4p/dpf6wZoMKpwgA8PO20jP852Wk7P4ruk94kVfMnRQW0rMUbsMdzB57inDKZRH4akq6K+/R11aVMLq9gr9bUrVNGgl8qoR4gKJtZelp94wh0gzZFgad2lFsd6ChSfwS8vpovjLw4foEuyEyZjHJTx81pdRK5WtjTtce1zo1SBcZhWTmtsFQV6wdDWBD5kcSxWRfmbTFcGAAhicxmNws9y1cKkNwjrgEUvHDs0/jAKaX+Yfw/kBCZhrdtTpLlFQFLiJ3uq/LNyCss= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(396003)(39850400004)(136003)(376002)(6486002)(956004)(54906003)(4326008)(2616005)(186003)(38100700002)(16526019)(8676002)(5660300002)(38350700002)(8936002)(26005)(2906002)(6512007)(9686003)(52116002)(83380400001)(6916009)(66946007)(66556008)(66476007)(86362001)(55236004)(6666004)(6506007)(1076003)(107886003)(508600001)(316002)(36756003)(69590400013)(32563001)(309714004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9R00sSXjGrv9/TPYgv/j6wm4c7Ju9ij5D5KNP3J7V1S8rPK2Br+Sh5y9O4pITdrPZi4Qgf009TAEKepfKHjRKq7V9pwzdlufJV4deZ8ikHtTOsA8kvGiyMa+gNkNzB2qDF9Qy9pVOFliRls+AZCxFt5HRb0hCZDbnzaMdazaEM68AoRTHIbmryaUEBqWEhgJzVigEJBpxIxXPPgsGBtP7fZTDsCLHUVJ+w3bQ1aY/uJDSF/mrb4mlHB83AKvOd4/ynwWNjVsj5PhPltb6JhEJQeEBJPwR6j/Yyw+N3YLGtYCglGADf9L4T5/SC19TBsH5w4Lpc8ZIzMXR+ooJuTpV/Udbjj3nEitYFL99gVKoP5Kj2U0L2dC+jj6QrjXaeNWWhpwkV9xu0uBiQYc4aAeuS92PDERHWTCqU3KtEixCqvzQmFM54+Q+tkEGTIcfN5iR2y+c5Ub9mjHHlBe1XqSsdfdqzm1QvIOk/Xa4xW2kqmPO/xqUifbFfQo/f6EAQ1IRWHjezXx3FDjXnwWwQp1Grx5UC34R2Dw5Ji/zDHZAzOXRz8GiCfSPTJjkgQGfFfqvXamj5Jkk9Qi+gINdwwbup9YBgVotB9oY08YFj04j6KXVGxYRkuGzzD05HSD+mFMyi7r9j5xIGjAzLuytkr/wLZ0yDkpkRuXBR4uJEIg1pkycOgcY9WcGGROn+CQnyGt2UsXcueCxd8oaLVQ0FQNXxFnvoXIExJnu7LqymxXKbUKZ40tYA5vTu3tIdP37OoRwrDlld4zmmXJkJoq4u5WoEv/YZaZIphkaahVtAMgWx6hrJZp+ejFbko51FGtD/WPOfDS/lQuK4aF2ebpWwkSu9gPrN85ARcPWMLXTYxBwyZpQSOpFOSzxeX5ACo3/weKwAEtV6kyRDRib0QtsBLoRdjUjd03W237yZwWwroZNsbL9ENgisW4+OtHllQ2GUBrBPkPJdHVaumg2qNTzv80qpHVWMjhDM2NcFMmXibvRcFldXaUJTl+tA6ZRt0xR4R0rfjcPtczYnf05cXGEOQms2MPa6JvnBiT5nVR9YpDwXN3sG99YinHK3NOo8nPVpGR97Qw6lQitAvMzbHgheQzqJaT5gnO6/7R/JyXY6d/nv0Wo69f2eOhxdse96I0+ZI0d7sTU+1hKDqqrCdvqSrDzmVuCCndxUAmeUDBjOhw6D8OvGc+Dxx+rpdfsT7cSJGgLLrN6iDBGDBCnIanBy/2Yc6DodDC/Q0KHsFuUJQUewJB3lmZG1it6AhZiCwwBcpAuC2yGk4obVi251UHgW9aLe5nJwmKYYH5YnEh3ADrjBc6WGHw4XfNSyZXlFsjq1zV X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 50d8d5a9-e88a-4aba-ff40-08d931a9806c X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:52.4830 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sKG/K6pReEcN4innO5leR25pVuIpOMSkxvYeBn8GhvniqzDA30GLIAr63WDmkQXwuGRXrTmbWgr7STAvXYoDtw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1268 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/ela.c | 227 +++++++++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ela.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ela.c b/drivers/net/wireless/celeno/cl8k/ela.c new file mode 100644 index 000000000000..49f4d2d21054 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ela.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2021, Celeno Communications Ltd. */ + +#include "ela.h" +#include "utils/file.h" +#include "reg/reg_access.h" +#include "reg/reg_lcu_common.h" +#include "reg/reg_lcu_phy.h" + +#define CL_ELA_MODE_DFLT_ALIAS "default" +#define CL_ELA_MODE_DFLT_SYMB_LINK "lcu_default.conf" +#define CL_ELA_MODE_DFLT_OFF "OFF" +#define CL_ELA_LCU_CONF_TOKENS_CNT 3 /* cmd addr1 addr2 */ +#define CL_ELA_LCU_MEM_WRITE_CMD_STR "mem_write" +#define CL_ELA_LCU_MEM_WRITE_CMD_SZ sizeof(CL_ELA_LCU_MEM_WRITE_CMD_STR) +#define CL_ELA_LCU_UNKNOWN_CMD_TYPE 0 +#define CL_ELA_LCU_MEM_WRITE_CMD_TYPE 1 +#define CL_ELA_LCU_UNKNOWN_CMD_STR "unknown" + +static int __must_check get_lcu_cmd_type(char *cmd) +{ + if (!strncmp(CL_ELA_LCU_MEM_WRITE_CMD_STR, cmd, CL_ELA_LCU_MEM_WRITE_CMD_SZ)) + return CL_ELA_LCU_MEM_WRITE_CMD_TYPE; + + return CL_ELA_LCU_UNKNOWN_CMD_TYPE; +} + +static int add_lcu_cmd(struct cl_ela_db *ed, u32 type, u32 offset, u32 value) +{ + struct cl_lcu_cmd *cmd = NULL; + + cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); + if (!cmd) + return -ENOMEM; + + cmd->type = type; + cmd->offset = offset; + cmd->value = value; + + list_add_tail(&cmd->cmd_list, &ed->cmd_head); + + return 0; +} + +static void remove_lcu_cmd(struct cl_lcu_cmd *cmd) +{ + list_del(&cmd->cmd_list); + kfree(cmd); +} + +static void reset_stats(struct cl_ela_db *db) +{ + memset(&db->stats, 0, sizeof(db->stats)); +} + +static int load_cmds_from_buf(struct cl_chip *chip, char *buf, size_t size) +{ + struct cl_ela_db *ed = &chip->ela_db; + char *line = buf; + char cmd[STR_LEN_256B]; + u32 type = CL_ELA_LCU_UNKNOWN_CMD_TYPE; + u32 offset = 0; + u32 value = 0; + int tokens_cnt = 0; + int ret = 0; + + while (line && strlen(line) && (line != (buf + size))) { + if ((*line == '#') || (*line == '\n')) { + /* Skip comment or blank line */ + line = strstr(line, "\n") + 1; + } else if (*line) { + tokens_cnt = sscanf(line, "%s %x %x\n", cmd, &offset, &value); + cl_dbg_chip_trace(chip, + "tokens(%d):cmd(%s), offset(0x%X), value(0x%X)\n", + tokens_cnt, cmd, offset, value); + + type = get_lcu_cmd_type(cmd); + if (type == CL_ELA_LCU_UNKNOWN_CMD_TYPE) { + cl_dbg_chip_trace(chip, "Detected extra token, skipping\n"); + goto newline; + } + if (tokens_cnt != CL_ELA_LCU_CONF_TOKENS_CNT) { + cl_dbg_chip_err(chip, + "Tokens count is wrong! (%d != %d)\n", + CL_ELA_LCU_CONF_TOKENS_CNT, + tokens_cnt); + ret = -EBADMSG; + goto exit; + } + + ret = add_lcu_cmd(ed, type, offset, value); + if (ret) + goto exit; + +newline: + line = strstr(line, "\n") + 1; + } + } + +exit: + ed->stats.adaptations_cnt++; + return ret; +} + +void cl_ela_lcu_reset(struct cl_chip *chip) +{ + lcu_common_sw_rst_set(chip, 0x1); + lcu_phy_lcu_sw_rst_set(chip->cl_hw_tcv0, 0x1); + lcu_phy_lcu_sw_rst_set(chip->cl_hw_tcv1, 0x1); +} + +void cl_ela_lcu_apply_config(struct cl_chip *chip) +{ + struct cl_ela_db *ed = &chip->ela_db; + struct cl_lcu_cmd *cmd = NULL; + + if (!cl_ela_lcu_is_valid_config(chip)) { + cl_dbg_chip_err(chip, "Active ELA LCU config is not valid\n"); + return; + } + + list_for_each_entry(cmd, &ed->cmd_head, cmd_list) { + cl_dbg_chip_info(chip, "Writing cmd (0x%X, 0x%X)\n", + cmd->offset, cmd->value); + cl_reg_write_chip(chip, cmd->offset, cmd->value); + } + ed->stats.applications_cnt++; +} + +bool cl_ela_is_on(struct cl_chip *chip) +{ + return !!strncmp(CL_ELA_MODE_DFLT_OFF, chip->conf->ce_ela_mode, + sizeof(chip->conf->ce_ela_mode)); +} + +bool cl_ela_is_default(struct cl_chip *chip) +{ + return !strncmp(CL_ELA_MODE_DFLT_ALIAS, chip->conf->ce_ela_mode, + sizeof(chip->conf->ce_ela_mode)); +} + +bool cl_ela_lcu_is_valid_config(struct cl_chip *chip) +{ + struct cl_ela_db *ed = &chip->ela_db; + + return ed->error_state == 0; +} + +char *cl_ela_lcu_cmd_str(u32 type) +{ + if (type == CL_ELA_LCU_MEM_WRITE_CMD_TYPE) + return CL_ELA_LCU_MEM_WRITE_CMD_STR; + + return CL_ELA_LCU_UNKNOWN_CMD_STR; +} + +char *cl_ela_lcu_config_name(struct cl_chip *chip) +{ + if (!cl_ela_is_on(chip)) + return CL_ELA_MODE_DFLT_OFF; + + if (cl_ela_is_default(chip)) + return CL_ELA_MODE_DFLT_SYMB_LINK; + + return chip->conf->ce_ela_mode; +} + +int cl_ela_lcu_config_read(struct cl_chip *chip) +{ + struct cl_ela_db *ed = &chip->ela_db; + char filename[CL_FILENAME_MAX] = {0}; + size_t size = 0; + int ret = 0; + + if (!cl_ela_is_on(chip)) { + ret = -EOPNOTSUPP; + goto exit; + } + + reset_stats(ed); + + snprintf(filename, sizeof(filename), "%s", cl_ela_lcu_config_name(chip)); + size = cl_file_open_and_read(chip, filename, &ed->raw_lcu_config); + if (!ed->raw_lcu_config) { + ret = -ENODATA; + goto exit; + } + + ret = load_cmds_from_buf(chip, ed->raw_lcu_config, size); +exit: + ed->error_state = ret; + return ret; +} + +int cl_ela_init(struct cl_chip *chip) +{ + struct cl_ela_db *ed = &chip->ela_db; + int ret = 0; + + if (!cl_ela_is_on(chip)) + return 0; + + INIT_LIST_HEAD(&ed->cmd_head); + + ret = cl_ela_lcu_config_read(chip); + if (ret == 0) { + cl_ela_lcu_reset(chip); + cl_ela_lcu_apply_config(chip); + } + + return ret; +} + +void cl_ela_deinit(struct cl_chip *chip) +{ + struct cl_ela_db *ed = &chip->ela_db; + struct cl_lcu_cmd *cmd = NULL, *cmd_tmp = NULL; + + if (!cl_ela_is_on(chip)) + return; + + kfree(ed->raw_lcu_config); + ed->raw_lcu_config = NULL; + + list_for_each_entry_safe(cmd, cmd_tmp, &ed->cmd_head, cmd_list) + remove_lcu_cmd(cmd); +} From patchwork Thu Jun 17 15:59:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F730C2B9F4 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/enhanced_tim.c | 216 ++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/enhanced_tim.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/enhanced_tim.c b/drivers/net/wireless/celeno/cl8k/enhanced_tim.c new file mode 100644 index 000000000000..da2a0cf547fc --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/enhanced_tim.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "enhanced_tim.h" +#include "bus/pci/ipc.h" +#include "utils/utils.h" + +/* + * The kernel's test_and_set_bit() gets unsigned long * as an argument, but we actually + * pass a pointer to u32, what cause to alignment fault in 64bit platforms. + * This function gets a pointer to u32 to prevent this alignment fault. + * Notice that the kernel's function sets the bit as an atomic operation, + * and our function doesn't. Vut it's not an issue since we set the bit from one context only. + */ +static int cl_test_and_set_bit(unsigned long nr, u32 *addr) +{ + u32 *new_addr, mask, old; + + new_addr = ((u32 *)addr) + (nr >> 5); + mask = 1 << (nr & 31); + old = *new_addr & mask; + *new_addr |= mask; + + return (old != 0); +} + +static int CFM_TEST_AND_CLEAR_BIT(unsigned long nr, u32 *addr) +{ + u32 *new_addr, mask, old; + + new_addr = ((u32 *)addr) + (nr >> 5); + mask = 1 << (nr & 31); + old = *new_addr & mask; + *new_addr &= ~mask; + + return (old != 0); +} + +void cl_enhanced_tim_reset(struct cl_hw *cl_hw) +{ + /* + * There is no need to reset cl_hw->ipc_env->shared->enhanced_tim. + * It is done as part of ipc_shared_env_init() + */ + memset(&cl_hw->ipc_env->enhanced_tim, 0, sizeof(struct cl_ipc_enhanced_tim)); +} + +/* + * NOTE: the UMAC DRAM starts with the enhanced TIM elements stractures. + * This is hard coded in the FW, this memory allocation should be changed in + * the driver module .ELF file. + */ + +void cl_enhanced_tim_clear_tx_agg(struct cl_hw *cl_hw, u32 ipc_queue_idx, + u8 ac, struct cl_sta *cl_sta, u8 tid) +{ + /* Pointer to HOST enhanced TIM */ + u32 *source = cl_hw->ipc_env->enhanced_tim.tx_rx_agg[ac]; + u32 ipc_queue_idx_common = IPC_TX_QUEUE_IDX_TO_COMMON_QUEUE_IDX(ipc_queue_idx); + /* + * Does the UMAC enhanced TIM need update? + * If the TIM element is set then clear it and update the UMAC TIM element + */ + if (CFM_TEST_AND_CLEAR_BIT(ipc_queue_idx_common, source)) { + /* Pointer to UMAC enhanced TIM */ + u32 *target = (u32 *)cl_hw->ipc_env->shared->enhanced_tim.tx_rx_agg[ac]; + /* Offset to UMAC encahned TIM array position */ + u32 agg_offset = ipc_queue_idx_common / (BITS_PER_BYTE * sizeof(u32)); + + /* Update tim element */ + if (cl_sta && test_sta_flag(cl_sta->stainfo, WLAN_STA_PS_STA)) + ieee80211_sta_set_buffered(&cl_sta->stainfo->sta, tid, + false); + + target[agg_offset] = cpu_to_le32(source[agg_offset]); + } +} + +void cl_enhanced_tim_clear_tx_single(struct cl_hw *cl_hw, u32 ipc_queue_idx, u8 ac, + bool no_ps_buffer, struct cl_sta *cl_sta, u8 tid) +{ + /* Pointer to HOST enhanced TIM */ + u32 *source = cl_hw->ipc_env->enhanced_tim.tx_single[ac]; + /* Staton index: 0 - 128 (do not use cl_sta->sta_idx which is 0 -127) */ + u32 sta_idx = ipc_queue_idx % FW_MAX_NUM_STA; + + /* + * Does the UMAC enhanced TIM need update? + * If the TIM element is set then clear it and update the UMAC TIM element + */ + if (CFM_TEST_AND_CLEAR_BIT(sta_idx, source)) { + /* Pointer to UMAC enhanced TIM for singles or aggregation */ + u32 *target = (u32 *)cl_hw->ipc_env->shared->enhanced_tim.tx_single[ac]; + /* Offset to UMAC encahned TIM array position */ + u32 sta_offset = sta_idx / (BITS_PER_BYTE * sizeof(u32)); + + /* Update tim element */ + if (!no_ps_buffer && cl_sta && + test_sta_flag(cl_sta->stainfo, WLAN_STA_PS_STA)) + ieee80211_sta_set_buffered(&cl_sta->stainfo->sta, tid, + false); + + target[sta_offset] = cpu_to_le32(source[sta_offset]); + } +} + +void cl_enhanced_tim_set_tx_agg(struct cl_hw *cl_hw, u32 ipc_queue_idx, u8 ac, + bool no_ps_buffer, struct cl_sta *cl_sta, u8 tid) +{ + /* Pointer to HOST enhanced TIM */ + u32 *source = cl_hw->ipc_env->enhanced_tim.tx_rx_agg[ac]; + u32 ipc_queue_idx_common = IPC_TX_QUEUE_IDX_TO_COMMON_QUEUE_IDX(ipc_queue_idx); + /* + * Does the UMAC enhanced TIM need update? + * If the TIM element is cleared then set it and update the UMAC TIM element + */ + if (!cl_test_and_set_bit(ipc_queue_idx_common, source)) { + /* Pointer to UMAC enhanced TIM */ + u32 *target = (u32 *)cl_hw->ipc_env->shared->enhanced_tim.tx_rx_agg[ac]; + /* Offset to UMAC encahned TIM array position */ + u32 agg_offset = ipc_queue_idx_common / (BITS_PER_BYTE * sizeof(u32)); + + /* Update tim element */ + if (!no_ps_buffer && cl_sta && + test_sta_flag(cl_sta->stainfo, WLAN_STA_PS_STA)) + ieee80211_sta_set_buffered(&cl_sta->stainfo->sta, tid, + true); + + target[agg_offset] = cpu_to_le32(source[agg_offset]); + } +} + +void cl_enhanced_tim_set_tx_single(struct cl_hw *cl_hw, u32 ipc_queue_idx, u8 ac, + bool no_ps_buffer, struct cl_sta *cl_sta, u8 tid) +{ + /* Pointer to HOST enhanced TIM */ + u32 *source = cl_hw->ipc_env->enhanced_tim.tx_single[ac]; + /* Staton index: 0 - 128 (do not use cl_sta->sta_idx which is 0 -127) */ + u32 sta_idx = ipc_queue_idx % FW_MAX_NUM_STA; + + /* + * Does the UMAC enhanced TIM need update? + * If the TIM element is cleared then set it and update the UMAC TIM element + */ + if (!cl_test_and_set_bit(sta_idx, source)) { + /* Pointer to UMAC enhanced TIM */ + u32 *target = (u32 *)cl_hw->ipc_env->shared->enhanced_tim.tx_single[ac]; + /* Offset to UMAC encahned TIM array position */ + u32 sta_offset = sta_idx / (BITS_PER_BYTE * sizeof(u32)); + + /* Update tim element */ + if (!no_ps_buffer && cl_sta && + test_sta_flag(cl_sta->stainfo, WLAN_STA_PS_STA)) + ieee80211_sta_set_buffered(&cl_sta->stainfo->sta, tid, + true); + + target[sta_offset] = cpu_to_le32(source[sta_offset]); + } +} + +void cl_enhanced_tim_clear_rx(struct cl_hw *cl_hw, u8 ac, u8 sta_idx) +{ + /* Pointer to HOST enhanced TIM */ + u32 *source = cl_hw->ipc_env->enhanced_tim.tx_rx_agg[ac]; + u32 ipc_queue_idx_common = IPC_RX_QUEUE_IDX_TO_COMMON_QUEUE_IDX(sta_idx); + /* + * Does the UMAC enhanced TIM need update? + * If the TIM element is set then clear it and update the UMAC TIM element + */ + if (CFM_TEST_AND_CLEAR_BIT(ipc_queue_idx_common, source)) { + /* Pointer to UMAC enhanced TIM for singles or aggregation */ + u32 *target = (u32 *)cl_hw->ipc_env->shared->enhanced_tim.tx_rx_agg[ac]; + /* Offset to UMAC encahned TIM array position */ + u32 sta_offset = ipc_queue_idx_common / (BITS_PER_BYTE * sizeof(u32)); + + target[sta_offset] = cpu_to_le32(source[sta_offset]); + } +} + +void cl_enhanced_tim_set_rx(struct cl_hw *cl_hw, u8 ac, u8 sta_idx) +{ + /* Pointer to HOST enhanced TIM */ + u32 *source = cl_hw->ipc_env->enhanced_tim.tx_rx_agg[ac]; + u32 ipc_queue_idx_common = IPC_RX_QUEUE_IDX_TO_COMMON_QUEUE_IDX(sta_idx); + /* + * Does the UMAC enhanced TIM need update? + * If the TIM element is cleared then set it and update the UMAC TIM element + */ + if (!cl_test_and_set_bit(ipc_queue_idx_common, source)) { + /* Pointer to UMAC enhanced TIM */ + u32 *target = (u32 *)cl_hw->ipc_env->shared->enhanced_tim.tx_rx_agg[ac]; + /* Offset to UMAC encahned TIM array position */ + u32 sta_offset = ipc_queue_idx_common / (BITS_PER_BYTE * sizeof(u32)); + + target[sta_offset] = cpu_to_le32(source[sta_offset]); + + cl_hw->ipc_host2xmac_trigger_set(cl_hw->chip, BIT(IPC_IRQ_A2E_RX_STA_MAP(ac))); + } +} + +void cl_enhanced_tim_clear_rx_sta(struct cl_hw *cl_hw, u8 sta_idx) +{ + u8 ac; + + for (ac = 0; ac < AC_MAX; ac++) + cl_enhanced_tim_clear_rx(cl_hw, ac, sta_idx); +} + +void cl_enhanced_tim_set_rx_sta(struct cl_hw *cl_hw, u8 sta_idx) +{ + u8 ac; + + for (ac = 0; ac < AC_MAX; ac++) + cl_enhanced_tim_set_rx(cl_hw, ac, sta_idx); +} + From patchwork Thu Jun 17 15:59:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F350C49EA6 for ; Thu, 17 Jun 2021 16:06:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A60460FDB for ; Thu, 17 Jun 2021 16:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231435AbhFQQI6 (ORCPT ); Thu, 17 Jun 2021 12:08:58 -0400 Received: from mail-eopbgr60049.outbound.protection.outlook.com ([40.107.6.49]:40639 "EHLO EUR04-DB3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231920AbhFQQIB (ORCPT ); Thu, 17 Jun 2021 12:08:01 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Q/2UGZSbDAN2IvHyeygG5FsmKyZ39IYmzlaYW9FzGcMeNz0VANL5YTiE4wCmnz/wrDdMRk44nxVvv9mTyZdvs2O+jd01FCUb/8n1eiZuBD3SCThguuwjDrreQ2lDTyVwHbAlt8094ePc9IDm6KAn9W8FX3bsJ7gyc5FPJumQ+E2gix7by4MQpxKlO3mgSQ48sx58Fzg7D1XEVJ4KFNyA3fzwYaBV26n+ux9SEM4GYEUdqfTYLpd9xUXDBwF87OsAueEy3wQ1VZn+1CJqkabCP1MChELSWQjj2RJQ1hDPnzIKbdSMKRan/GiVVQQkSO44gd31UkUHL6aTDvE/IqURjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9pBL1G3SoBkqijcB5Cgg1KaAfMOUUC8AbZyYDq6UkbI=; b=Gyb+trA2LFCdd1mk1A+b4/YjG9cswaSTb2xaNRXiG1M4qHQheyoKShjzKT5MmegigTf6MBHNwiEPysHoe4e/+CqQr6cI7QClDXHQehEFPKHxxs56D3JWwdvmx5IYImUCPQ7Hrgi/A/v1FiyxX31VrewuBUzdRXMByEukCps0OdM8KoRL6sDn9TH6mN/HfUb7EHK8Hrj+3iRSF08l1oSyXCROiIh7fsb3aVmByEnlcaj+eznIfm3ZliHqT1kDqk2dYDktCChcTGaMTlIbw+/0i3YNd3DGEGnlc4XhM8dwjhs1NElabLVnSNIki4TtFJBL8F7U/h6t6ADA//vYBYu0jA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9pBL1G3SoBkqijcB5Cgg1KaAfMOUUC8AbZyYDq6UkbI=; b=M0X4R4TLSOzUbTRVCcpe0XefJriH+62kBkgxjmGbmkSwZruwn6BgTTimLGhmTVcZ2kfJZusDgHrx9OjFe1S/kG8f88dwqzBdwYHoQ9qLSTPqW3OcHGDUvXxfBIZU6UqX5qCAKft6kPcwT/4iAxxJvNl2ocql2Ra2vfFPYAUtStM= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1268.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a9::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:04:23 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:23 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 074/256] cl8k: add enhanced_tim.h Date: Thu, 17 Jun 2021 15:59:21 +0000 Message-Id: <20210617160223.160998-75-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:03:54 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0917db54-fd6a-4252-7af7-08d931a98232 X-MS-TrafficTypeDiagnostic: AM9P192MB1268: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ky8tzbru4EF334Y8oCp6VSH4l/lMSqVZgNhpYT6H1aYGThi1gAXsfCCIfK6yDjWeG6QAn7RGPvuspaw7jPijIFlEo8SdtUbhu3DI4SkGk5mvhFQmdzTG3sqOs/4sf+MbLzvzJFB18ZkuOREJoJEv6EvvRUi2Ay0iiDLASMu7FBdYSuzjWxL6KYT+hLBpJHBJmA6tMQmbSkNBaG9FwrF7rNTNkNEMC9ZK+h0ogZxI0/txoJT9R9DdmQ2ledvvNXr7wimegy1wXeoWvh7qcfeLMm50BPpRVxd202h0Ynj+uRBeO3SzVjRs4+M9SOR3Z06mfpSgguhY9uHK7tjnnJ4T19CLf6+FG+H9UUqk0CfvVMhrxDlyAWAUpBr3de4sKqBD2m8XWCy64cr5BrHTCzvw+xm64nLnq/pD4Sk0o/2hnCyUTkFZeW9/Z7MBvcFURlHnTMLNTB/uNoE7zh3znl0kz7gld/94ixZ86OOIq9FCfObdWkHQ+p9q7CLcKOutGbFNYip0/AyxWIVuZ3C6F0lqWGgJ+MMdLFqAj2Qb3Lzpza7D2yjT3VeYFXwMhBDk2qijBI71xy9UfVHd90hskv1hrMJhzynTB9MAslb5Z5S3rML+PKIuoJPXj1BZrJVZh7GtUNz5VIuG2uqCdxz5MukdmHPYs4DiGsQm/Vlovl5cgs26wqgW+shO5m/YX6fQfuw3NrKqHSRYuREqs8RcebRKEw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(396003)(39850400004)(136003)(376002)(6486002)(956004)(54906003)(4326008)(2616005)(186003)(38100700002)(16526019)(8676002)(5660300002)(38350700002)(8936002)(26005)(2906002)(6512007)(9686003)(52116002)(83380400001)(6916009)(66946007)(66556008)(66476007)(86362001)(55236004)(6666004)(6506007)(1076003)(107886003)(508600001)(316002)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fPkAkSfajz4ySNkGkz5RgzQ6z8f5JbwBBpBPSpyJoRpeOt7Bw6BjmSaB27bqKThzx1VR89nKkpuRi+bzX+gbtCGoI19jLB5II++NguXbr/QopZxguNZ22pzo4oirnX/EbjzuoLSse08S9VjRopLxBcYuxLe8GZE+UyuxYjT8FAmI7eE6zF3ASy9L9P+FHg2FSgLthYgoQ7d7xVCu33vBleQnVcWg55matXtM+oUpLsPXAZUadMUtFjyMHgtYPtu7k/E8nEyRT+PLDQmrxjAe/zTUJGaLXnzAT3wcOA0BJqLgdU+WmLFu+igsS/XTM2cJ5WPpbCgCfH9+oQBpPqfIVDif6gSV3EVVYk0kWS+sAw0G9ZSIXS3qSc5gljbApfFG/TnR/3oDJWgLBXwHvlJuYbRes+1q+Smi+ruK2UTmQs476bBYocA599ctpbpGx6nRPb6F7iLe++aMVyRvYvLADwIyD0Q66RjcbKHX5Mk1Z9te4eu8skhxgK9dR8ejCl539AEK/TQ7CDizs83rZZMMXDTdYOgze6sVrcGwrLSmWFv4gEc6wUwwa1/qYF+lv9cemS/PhEuO++3MvqnxdefS7NjzMKGNt3fc58RBBE6wPCiJuJbDKmUbYbMQq3G0ZaDupb0t0chF/1XJSjZ1q0r1GKnQMJN8yCser2pteVgftUhKviWTiYyAN+K5WhZjIUWLRYosMl0p7mbLcwHTBr895CtoQSVxWeM/CkZrmnIQht6VVc7dyyutMyPe7kxPrHmL8C8Gnv1C0Frk8H3sGkGRDmrVI5OugcHz/OfFJ9DUVTxarnAoER7WUB4kes+CC4z19TefZCCCS8j3wK0xVtG1bnsvnRYdrwo+bOpq/jyucuF7EqNE3ewAsLBHrTznY2XhJKalezAgkDVOllTtbYTjxENesNoqas2MyyagV+aiRFgBrtSarrJssDsroFw9H85HjwVtuA2TGQ7cdAfCFLUSyRFbhF8/kA+jy8ZBN1frKYd38OO/Ao25mev65BSyL3ivDWWU5oGjqU2iiCmoi82ed9tGbQ2JBA98D+KxaNmowD2QJ2LC7zYGN8OOzxy4hDJOgZeMMNhoufwiGfZv518TjwoMofRzE9vHwbUC5XZNwS0oPP/9xq8n7F7Hh0QSEt1LtTLFfaC1cefZZB8DRoibUzDW3Qdj9nZNtbZQJiLPdda/SFoY6f/LyX9D7Xf9/zieNb0ele/FCW72pIXuEiy0h+2MVBU96NnnUAeRY7kGyR11jeI+6uLzC9kWT2ZhfaIm8GFd+pa5wfKAkjgPOz1fXOMIH3dwvxaKVlYag/Y0josZ3FE9v9kLIe3sq2+PDN5A X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0917db54-fd6a-4252-7af7-08d931a98232 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:03:55.4530 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BbZ81hHA8G1oReRcyH1IaMVpC/+RsEHSho4OfSftA6rYaIIJhlFnUcF8VBcACZ9Pn8btwLTFbIFKTfUHL8rAUw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1268 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/enhanced_tim.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/enhanced_tim.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/enhanced_tim.h b/drivers/net/wireless/celeno/cl8k/enhanced_tim.h new file mode 100644 index 000000000000..0d7b05bd28fe --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/enhanced_tim.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_ENHANCED_TIM_H +#define CL_ENHANCED_TIM_H + +#include "hw.h" +#include "sta.h" + +void cl_enhanced_tim_reset(struct cl_hw *cl_hw); +void cl_enhanced_tim_clear_tx_agg(struct cl_hw *cl_hw, u32 ipc_queue_idx, + u8 ac, struct cl_sta *cl_sta, u8 tid); +void cl_enhanced_tim_clear_tx_single(struct cl_hw *cl_hw, u32 ipc_queue_idx, u8 ac, + bool no_ps_buffer, struct cl_sta *cl_sta, u8 tid); +void cl_enhanced_tim_set_tx_agg(struct cl_hw *cl_hw, u32 ipc_queue_idx, u8 ac, + bool no_ps_buffer, struct cl_sta *cl_sta, u8 tid); +void cl_enhanced_tim_set_tx_single(struct cl_hw *cl_hw, u32 ipc_queue_idx, u8 ac, + bool no_ps_buffer, struct cl_sta *cl_sta, u8 tid); +void cl_enhanced_tim_clear_rx(struct cl_hw *cl_hw, u8 ac, u8 sta_idx); +void cl_enhanced_tim_set_rx(struct cl_hw *cl_hw, u8 ac, u8 sta_idx); +void cl_enhanced_tim_clear_rx_sta(struct cl_hw *cl_hw, u8 sta_idx); +void cl_enhanced_tim_set_rx_sta(struct cl_hw *cl_hw, u8 sta_idx); + +#endif /* CL_ENHANCED_TIM_H */ From patchwork Thu Jun 17 15:59:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BD46C49361 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/env_det.c | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/env_det.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/env_det.c b/drivers/net/wireless/celeno/cl8k/env_det.c new file mode 100644 index 000000000000..fcd2de02018b --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/env_det.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "env_det.h" +#include "hw.h" + +void cl_env_det_set_type(struct cl_hw *cl_hw, enum cl_env_type type) +{ + cl_dbg_info(cl_hw, "Changing env state from:%u to %u\n", + cl_hw->env_db.type, type); + cl_hw->env_db.type = type; +} + +bool cl_env_det_is_clean(struct cl_hw *cl_hw) +{ + return cl_hw->env_db.type == CL_ENV_TYPE_CLEAN; +} + +bool cl_env_det_is_average(struct cl_hw *cl_hw) +{ + return cl_hw->env_db.type == CL_ENV_TYPE_AVERAGE; +} + +bool cl_env_det_is_noisy(struct cl_hw *cl_hw) +{ + return cl_hw->env_db.type == CL_ENV_TYPE_NOISY; +} + +bool cl_env_det_is_very_noisy(struct cl_hw *cl_hw) +{ + return cl_hw->env_db.type == CL_ENV_TYPE_VERY_NOISY; +} From patchwork Thu Jun 17 15:59:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0B03C48BE5 for ; Thu, 17 Jun 2021 16:05:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DC23D613E9 for ; Thu, 17 Jun 2021 16:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232554AbhFQQHh (ORCPT ); Thu, 17 Jun 2021 12:07:37 -0400 Received: from mail-db8eur05on2048.outbound.protection.outlook.com ([40.107.20.48]:5985 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232781AbhFQQHJ (ORCPT ); Thu, 17 Jun 2021 12:07:09 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=a/z/9LKNIZ1EG2zRMh4GlFGA2kG4Tdi7GMl5OUWxIftGRIvSEqLSlW3O33m4NWD6EUf1ttfwc7TqbklnVJWM1BTIPSo/UaxYnciWFQS5GZ0duBrvHvuESI/f1BXK9elaboi3dQiri/6f/PAAABz/K22cyQbJRidCKWqwaIvszPAKbzs/B2J5Tpekx+GV3K8Ax2zSXYk9A5JpNOXAREZczxImSp3n8uTmtcArRn5Gxb1sSoqNFMsS+cVUbVJYPJBujPxMuwzkEXclqPHoJq6nyF62L8c7XPQPtnnd+sIeQPWPYdq8LwdQfIqqelfFN07T+DF+wrLIgOUbM3xB+0I7nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OAtcNY2+S3+ov/x9Pol1hGpCwjMyE3oUWWeweTwilQA=; b=V/XUbM5dpl6rp+G3qq/BNLO0mU61RzyKMhjhbWHQuM75GMBe+EEUq/U2t4VcUltAxJ3z4I6ekjPXEKZ7wyjnOex2q85zt6EuxqI2wOfJzCQMDZRUbaI4IjY2q0LfodebKqmsS89TBW6X9OKXhsk2z1ndKCO/b+gB046uMgFCPtpyTwp9CVpla8r+yekvY0yj3xtug1veFYk77wfUk5inYUoXkNwhStWIQVRP9Ri6MSoq51gp4qP9taEDHGXzadPoVw6Hzd2FokFU6c/PXrbsyHNN8Xg7hyS+wp/p4K+s3CLOL7P6jSyLLqfsrLjGcpTXC1+shL9PyqhtBGfAbwMOFw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OAtcNY2+S3+ov/x9Pol1hGpCwjMyE3oUWWeweTwilQA=; b=Yg3pcPYQD9PicSJHFRqEatd5ZHQAi/roxSgV6av3P9B6JAikPLbCiGk0frzn2kJ/pU2nCHrvn9A3XS+DNteVWo3KB3/S+JK3MmrAE/AsRtjxeRdCYGWFSEIbOlex1YCYH5rOxEdhrFBAcCcQqkgTUD1YApQGA2/Vp7+m6zJl7+8= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0871.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fb::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.21; Thu, 17 Jun 2021 16:04:26 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:26 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 080/256] cl8k: add ext/dyn_mcast_rate.h Date: Thu, 17 Jun 2021 15:59:27 +0000 Message-Id: <20210617160223.160998-81-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:00 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2ed1e280-961d-44d3-5ed1-08d931a985b7 X-MS-TrafficTypeDiagnostic: AM9P192MB0871: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rwdVm/M1qBSPvUDFr0wBQ6i28J8MWgG3pgc2ImvKHkm/c7kzrFvGErzGqqIIR4sGdYrV4N5EuaZ/HaOuMxR1VgmV3e4B3GSkm9tIB5l6WvMbgnQUVhrIkgs9MhJcCkeAdG7xJpHW0noaOIPgWwP9ooYzgn1sqdYV5ZzbbB0jg+Yl/k82Mk5l5tuKpzjRwBbhaOwIAWEatY45uwTkTzo9TQ0SxFB3aTog2Hoz+0l8XziY21zNF99Aaw/T5To3nDX8/KooCyXZ4sul2C2cJS8yuSTyjlgCwHzd/ZZHdfiV6w7Z176Tp+gVRy5vB8v2fJGJqWxlesxZjINcgfAqVkL+wa2OtYbeP3hCNHqpxOEqxE+T5SMpjzjbPUjsji65m3MqJ3aYdpthkKZN7XUCaAjlACTsMviHo0I4hTt6pi/xzev+XPTXoj+IA++nhht1wYrT4h2SKGPFBTLRfNoA8w7hW20IeFam30Fopezurs+zkKUQMYRSr7h5RyWuBNpqP+e1zNaYB2qAWTggJ/hcLZfVUMchK4XON7QIfTtE+FZX8cLELM/970tiuHmp5/e8Ocnbk3dCCl0gf6lMaRUF8YtF5Q0fATpD6LM55ZgyBeFaVg7EEW6I4zBD0ZsWmP9lq+VX9cl08Mowb67/PrIR2yJiogaVNnhZ+rEnTuT6JtYpOfSSrVhTyPQ2NGw+keUVbIxlIi6JGekptxROVfTCZ3G3ww== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(366004)(376002)(346002)(396003)(39840400004)(16526019)(66946007)(478600001)(26005)(66476007)(6486002)(186003)(66556008)(9686003)(316002)(86362001)(6506007)(6666004)(6512007)(55236004)(38350700002)(1076003)(38100700002)(4326008)(8676002)(83380400001)(5660300002)(52116002)(2616005)(2906002)(6916009)(956004)(8936002)(107886003)(54906003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NwyvqEOX8GSgIoQtaVTJcrLDA8qOLLv+wGFA2WKsq8Wq9ZxjP1SZ4F9neOa/wKAeaGlGEyTEMrZlyQ0vAD4qSUnSqzAqet1biUU2ZY8++T6nMJIXUh2bNydNcBB3tH3k4QkzR08rfeCRcmVpOHhxAH48ix5quEz59Fyv3cHvJWfMPPvKsAqHOfonsFKa9NbK3EG0uhWLNmozYY3FEr9sLDjUGYFwUxTKf5RcHrzayQJu790ErFKWgAOwd2AIbyV1kpA/W2cK0XFbfX9O+J75bJMCVvEdOmpoNP3TtDB+PQBX26s1AnccvQ4eTh+yOzOxOkIR7gxLlfKD3ByKjxn0anC0y5u6iy4OhtG/BLQRfF8BkJkqXPOnTI6z0BUr8+5oDOhXzghIwT3VBPoChZI4M5YiWLzRJyBQ+hM3gTt1yxOgEGgdKc5i8LrHsUqe6PdAQhZisidxpLYmNYE3cNBXe1uaxsXAgqhsFQqEcq1RBXOknCVSdhs/DlpxARVTV0G18ijAdNdlrK3T9zTxpaUE0FM34tiyqsL5Kzwync9s3Y4u2sRfmKiWYbtTDcaFEliS+YsrNdNiiQIzfk00q2CofEqmAQCzV/Uq7FYwG8qywMnAu3DJzgHEPk0CVLHc4NWH8AVsAxlgJXG1WTFaXzPLwry1a5lbIt6LGz9JI16/0aYmLEuqeKu1UyzNerUGEjTbFZTDvvogUu+o5RpOCncPrFln0iwQwDmR9CWRSRbGM2IW3g7Zz4QhTigYohvBmp5Ke3LzJwE9RCvbSIUavBaDWjAhNUuCrYtHWCyO1p+bhl7eRFNQhrD++179dEBiXRKeJLxZB7RWWIq+gQxYrj9fp8tq1kB/QmJm0wutIYgvKushlZr64WHTSQpZAJHj2piErgrRsyRJ19owzvrhCJn52PB0qGBcFlZcoF7/MoZChTmUXiMG4QSn+m3eCYzlYzqJ+UvBC+xx1hGC8EykVFck+9Jsx25uUeERu6aA+dHguGImTJhInZyUpHEy1zdQPOJuLIwVUTCg366jMAKWcFHIyVHyKeL3QkavQoIDmIgPAHAiQeLX6z/WbGUmQNhicOdr2OlfBoQlxOCwPt43HoQ16zSsxEsGRK+y2uDn5Be6eE8ZYyf8IYgRgpVzOilC9l7EADh6oePh8ImYpe+1P5Bn24/hOpxuerV5dHgQ19aVxxPnGdOAIncNnSlQVBxy6bZlLNMGXCFxscSzm+xHUEJcOltFjdOQg694kxKFcTh1igBwW12ABLYsD2ObezJzwiEBtn+QOvRGWEUCsPA1fzSC/LM4LyRoqvTsHtChLZVGnbSfMKUzsD7xyaCrnZbdoCAk X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ed1e280-961d-44d3-5ed1-08d931a985b7 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:01.3571 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IHN5EvXivvvnaVBLUmoM4USKm7jm1Ipfs0p7+D9n22vGRXI4vvQyJFlwEhtjhgf7oYkEb64nmUyL6ZbWMJwU5A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0871 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/ext/dyn_mcast_rate.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ext/dyn_mcast_rate.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ext/dyn_mcast_rate.h b/drivers/net/wireless/celeno/cl8k/ext/dyn_mcast_rate.h new file mode 100644 index 000000000000..dac8c816c5a4 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ext/dyn_mcast_rate.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_DYN_MCAST_RATE_H +#define CL_DYN_MCAST_RATE_H + +void cl_dyn_mcast_rate_init(struct cl_hw *cl_hw); +void cl_dyn_mcast_rate_set(struct cl_hw *cl_hw); +u16 cl_dyn_mcast_rate_get(struct cl_hw *cl_hw); +void cl_dyn_mcast_rate_recovery(struct cl_hw *cl_hw); +void cl_dyn_mcast_rate_update_upon_assoc(struct cl_hw *cl_hw, u8 wrs_mode, u8 num_sta); +void cl_dyn_mcast_rate_update_upon_disassoc(struct cl_hw *cl_hw, u8 wrs_mode, u8 num_sta); + +#endif /* CL_DYN_MCAST_RATE_H */ From patchwork Thu Jun 17 15:59:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E22AEC49EA2 for ; Thu, 17 Jun 2021 16:06:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BBDE561406 for ; Thu, 17 Jun 2021 16:06:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232333AbhFQQIG (ORCPT ); Thu, 17 Jun 2021 12:08:06 -0400 Received: from mail-db8eur05on2048.outbound.protection.outlook.com ([40.107.20.48]:5985 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230292AbhFQQH2 (ORCPT ); Thu, 17 Jun 2021 12:07:28 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KNt9PtzU1Fu6MkR44Xd+erdrQzjKXJBYYymTTbh/+BqlLm6e5QkclPPozeSvdGtEdEhzdySQMeYROBxSz7ujRVZzmYhWYofxGe42m3FGxvme1QzbNdDzd53Fpid3pT6e6VnQwXG5J5DQYP8Y5QHX58v4IUMeXLCCv0EWsdGIAkToITSdpqL5ADVMtmT62yFJP3wpJwCqzsXaswklLh80xvezPgeff4w3qejREeCQ3Iiqy9lJa8NCw2dXMX5z2v0fnpVGU599s3DyPAsb2KE0vo7L1A2qQ0igbEZlzQl3TOyuCt7uWzejhZIpp9CZVqMSfWwGlH2JNCJljL3YsZRKMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V4sDvID4II1JCNDW0KoGuyLuPMXRWTC5SJ7yDffNBiY=; b=JiTyTj70fJjx9WF2oOaZEJ1CU5b7EomDpY6j5xEZ4dwZoUkv2Evhbw2hV+xDiapkVfwVfVNRsGgCqZhXi/i7QVzODqg/iJ1higXr1IS5HfxXMpIF3JDlyTbig/VQ9RxjyqXzzMOK6HLQZ/hTqWq5aRq5Zdd/sEnBeRjh7eJ0zeSHckLjA2S3d4qwf1Zi2Rkxia9UjJF76zLooBqxbdacc3cmstt2flinGun27nPVZ32nIKapNGU3QUc9hqaqKoloOVyBSC/X/2qZcUc//IX/NPTpbh1A8qSNBQF+nDaqUCYP3BWTlEusISEh63v8ybgFgSL8l1fEi4AkknP1whNFjg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V4sDvID4II1JCNDW0KoGuyLuPMXRWTC5SJ7yDffNBiY=; b=OkJfAXj2Qc/C8bAVhYEWvYG1TW+6ArTi5h/lOcf7Rua6OkdLSC3cKV0QOenfhw5oEQCwg4snT5JHlZImsecjufc0snbnrKlyl5DkalaXNpDTdkMxa/s9sD6//ShzU+lfAb/umA8pzuJ1ufDE6j156dYx0iWpeajaaXW5LxKY0Rs= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0871.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fb::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.21; Thu, 17 Jun 2021 16:04:27 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:27 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fem.h | 32 ++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fem.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fem.h b/drivers/net/wireless/celeno/cl8k/fem.h new file mode 100644 index 000000000000..8fcef76c7a61 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fem.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_FEM_H +#define CL_FEM_H + +#include "fem_common.h" + +/** + * FEM (=Front End Module) + */ + +enum fem_mode { + FEM_MODE_LNA_BYPASS_ONLY = 0, + FEM_MODE_TX_ONLY = 1, + FEM_MODE_RX_ONLY = 2, + + FEM_MODE_MAX, + FEM_MODE_OPERETIONAL = 255 +}; + +struct cl_chip; + +int cl_fem_init(struct cl_chip *chip); +int cl_fem_read_wiring_id(struct cl_chip *chip); +int cl_fem_set_wiring_id(struct cl_chip *chip, u8 wiring_id); + +int cl_fem_get_registers(struct cl_hw *cl_hw, u32 fem_data[FEM_REGISTERS_AMOUNT]); +int cl_fem_set_system_mode(struct cl_hw *cl_hw, u8 fem_system_mode, u8 fem_ant); +int cl_fem_update_conf_params(struct cl_chip *chip); + +#endif /* CL_FEM_H */ From patchwork Thu Jun 17 15:59:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C433C49EA7 for ; Thu, 17 Jun 2021 16:06:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A9FE61003 for ; Thu, 17 Jun 2021 16:06:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbhFQQJD (ORCPT ); Thu, 17 Jun 2021 12:09:03 -0400 Received: from mail-db8eur05on2048.outbound.protection.outlook.com ([40.107.20.48]:5985 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229805AbhFQQIC (ORCPT ); Thu, 17 Jun 2021 12:08:02 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dwG3CwBofSEaonW7oyhPAqflszx+4urSVxKexf+G8li8PGxQMK2HJKWPlXojFn7XNelrRE+z3HS7YpLYy8nY/s4Uuy2XX9Sv1SPntTWCmhjn3SEU+69ZcoiTTa/vD8F9fpP9LUB4AaaI1NNXe5AIKIexGJKmKbWcAmAYgHKVquLmSFyMJFH6ZhWbMax1OUfzn2pu+dqJgwQEHObnv8dT5i5CgUlzo8gwcrieXvXIe88thDWGFJWgMl3G+2QCe18zuV6gkFThxj4RQdnca9oyrkiGGyHNDsPWyLlP/+CmSMUBAIC0y0GPFP6+4wP+26jn6h5cKDMZ7BGZsNOpOLtBWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nWW59LN2ZDQGaa5RSVtdOC16w8Ffj+cuIFYvIYC8uro=; b=AnopNszkU+HWqWR6oj6qJzxLM6oOTDCPyWVGV+X+O1SwNsFq8c4+Ez28JP9e872UwYRBjxuRoWwrtZXLUG2lDp3SoaoWe2qWmvKsMOZypNxPuphE5GeeAIzTpBDgkzV9bySKoDoJ4P8pW7ZjsbrS87WM63Su5HIyouOCA7cINlUJPtSOE7flqwYoercHWOO3rWTCirRyFeei179SZ1dvh3c1Zi7pnudmEho68BNWmWG7bOeV/K/bML04qol/BhUQqeP/yQDXYXXDWyIa7jl+3w/7DRAewbj9FxZiOIbJ5UOxvwEAOpo2weMxjoI0fe6HYcJ6MRvXZVk+49QBmtLZDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nWW59LN2ZDQGaa5RSVtdOC16w8Ffj+cuIFYvIYC8uro=; b=q0PKbS6rHSb7Gn81IA1yRhuZSKWD6pZkq7Yxk5NX9lgUPFdbW4ApIt7GJQ+lxwAMdo8Uc9BYhsMxcR2WloKt1OgeQtOtexoWefIoh4C7znNz64/4ILB6NNA7tEy+EUI5xQOPGKzAdI9N8/fRMyTd3hhTL4ZVpl/FhoHJ6Kxn01U= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0871.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fb::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.21; Thu, 17 Jun 2021 16:04:28 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:28 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 086/256] cl8k: add fw/fw_dbg.c Date: Thu, 17 Jun 2021 15:59:33 +0000 Message-Id: <20210617160223.160998-87-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:07 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 04f886ee-9d3b-4f62-fe95-08d931a989e8 X-MS-TrafficTypeDiagnostic: AM9P192MB0871: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:222; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tkgmy34eEN31rmpjoLP9tNIQBHL7UT1MuhyAz/G+twqbOZRhivhjDeGxnDng1WFrOxPxRCH8SGr4Ae3k3ithFm+Gq2u+V0P9VdK60mYmO+8nFcA+l9PWXiFTxHH/Siio9WQP4GfB/EMkuzMof9RmRaxPMrsxgQGSMwgWTS+cNOcu+2qFybaAhHZu1DTDJ7wE7L/poevvT8RoQjtfH9/d1CWe/qI63t5UKLLC9QBDnF/C2YE6sWCykg8G3ETh9u3gmUyYhQR8hu7lO7wUtRa3k8umdppy5KqRKXp6QURRhLbphsG+6Y3f5nkA+aEEYRj0uJC5bI0bP87O91JruqPOiytnjGUBCGa3wVI2TSgLw1V7ArZU6wSQSojBmaR9mYL3hjI7VYSyEkOJf4lM7SNxTR4Ktsa7mJXPSVlzyKZuX92qSFFaEj6dQGB5Mr2PT4qsVXzwBCsG8o88UPYVgBc6rEvwoa05b9/FPL+FvC6caAEjhuCEffPWEATpQO+7tdjRDQmVYmvj9rN7eOPi3EFclEG+Sy27y2059utY5OgbT1AomX6Xyo9HD4tfKSnEP2vpkvTCncuAJWzWAY1Wlv2J7yHr6MjKDur6+qxcJqmGzS6YvjcjhsqtgcqQQcGamrZA5oPaDVLgAw9yhdrXi1K6kolbC7GVHcAb4L7E0g72SB80t3/g9YHmWzt8V5MouUhEN9727PP41xTv2gLEd15iIw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(366004)(376002)(346002)(396003)(39840400004)(16526019)(66946007)(478600001)(26005)(66476007)(30864003)(6486002)(186003)(66556008)(9686003)(316002)(86362001)(6506007)(6666004)(6512007)(55236004)(38350700002)(1076003)(38100700002)(4326008)(8676002)(83380400001)(5660300002)(52116002)(2616005)(2906002)(6916009)(956004)(8936002)(107886003)(54906003)(36756003)(69590400013)(32563001)(579004)(559001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tLXKPHBllQL13gTyrCM1G8sJrfXbxEOcrR4v9Ywdhs6CDeuIwbm28XHcER+A4IyH7IHuyx0QHBg2UeopyrgrL4RvvPQjq4rhJWngy2WX0hw4inVpUMtjdfciuFJCxi7y7ZcHLIMB7FEe5gh9ERBen+GdsKwEM0sN1r5xEZtMIojGnioHhmIjAzMG17UgUgtvHdUK/3DP5CxmRLtmUoCIioCspIVkzqEjYts7uKqeU/wUjKPOr8OqBVlsapZaMzFKEfMhYC2UqIpNGiGEojLU482/PgbylcEpSHdyfp7LABwMskvbzfW5nMy8E3Ouj2NYwIq99vhIdsFEj0ZWo9bsDsr8K+RcbkKF7IKHleZDCil7gvF2+WoEfHfGx8H44lpuTJz/uO0Y/lqiLOU08tgMS9pQCcA5hl0eX1qTxw7nLUeY/ujK0CWErPpPAyA5mvXDNRAsU+zQGlFSFsdNZpwewhTVMZSykoVA4XmAa+Efgla/mqa7uZmoFJEimCGLmh8yqUV/xtjy9Jmiv55YWaTbyb8HTvC/jRMVDZSfRLkt9nyguHpVLIUV/qtmccxND8ZSGIo5A/m38k30AQjfMJM6R/9TO4BF5w2p3lkBwoNhaozpF85r0DeAO65FhpjZi2i3v9bGwlD9Zz3NAu1Vv3AHcXi8mUSanf7BahX9osWp1/CN2sMDrOuaBSGGUl/HrCiSSaBHpEo2hqTYMkbS5R2qgY+h18uDvpXRQecMcsX8MK1cEtWVROutyGerW6cHudREgxxrJWvPTLSoOq1WNCV8a3hPQY2yjIuRP9W+30VmwWNqxUNfjDHua9N3wKtgGOu+BJeYZHFChh00YIf5VW+dt+vSMHEOSB7ts7N6ZDMqYmuJcgPOmquhdxPVu7Y42yuy30p5QtM/7f76FMLTe3o8OKtH37NfN4cFvlyiJj1FogE29dJAShu6xugDo1Z8L83o9HOssX2R2r69IvSHqdgvz8P8ZVZK1FTOWbMjQIuco3dtPuhrtZq6gCAAVIXh9McL8K07RLgz8ecUMj9GTy8zNg5sOqM59VdwB1pXctv0vdK9vFj+BMLtCYNILk8FuzO4XwprIIYJ4F87zW6XihQ147ZJatI0GOd0oQwraRdfcPeQzddt2N4TPKYSf+WnDjwc5UH98fn6bmeEXbJSnVCLAHmmLMJ7ZED4E/M4+FPPqN/S+t3FbDkMb5N9/TYI493vhYpft7P/9poGXIU850H8qBICWaU2mPwqfG/eVyI2fKj5rk09Sf4Dp8tgMsCta52y2EeM78QyJoOmMk927zgFZUW/JMsPVOEhcraw8yHgbfKVZP9lZNpTuV+K+duc37/q X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 04f886ee-9d3b-4f62-fe95-08d931a989e8 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:08.9677 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: O7uOVgeZRhyWsAKe0R+nP1v9ntFy0FZcojvJUGngmMkor5azIsTqvgmpLzfjliAtlzWexmDf4PhLVDKj2vV7Pw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0871 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/fw_dbg.c | 2686 ++++++++++++++++++ 1 file changed, 2686 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/fw_dbg.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/fw_dbg.c b/drivers/net/wireless/celeno/cl8k/fw/fw_dbg.c new file mode 100644 index 000000000000..413f45b433c6 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/fw_dbg.c @@ -0,0 +1,2686 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ +#include + +#include "utils/utils.h" +#include "fw/fw_dbg.h" +#ifdef CONFIG_CL_PCIE +#include "bus/pci/ipc.h" +#endif +#include "band.h" +#include "chip.h" +#include "coredump.h" +#include "ela.h" +#include "utils/file.h" +#include "dbgfile.h" +#include "rx/rx.h" +#include "fw/msg_tx.h" + +/* Work struct wrapper for print statistics */ +struct cl_print_stats_work { + struct work_struct ws; + struct cl_hw *cl_hw; + u32 dbg_info_type; +}; + +#define FW_DBG_INVALID_SESSION U8_MAX + +#define PRINT_FW(cl_hw, fmt, ...) \ + pr_debug("%cmac%u " fmt, (cl_hw)->fw_prefix, (cl_hw)->chip->idx, ##__VA_ARGS__) + +/* + * Display 2 digit decimal fraction. + * Example: x = 541, y = 19 = 28.47368 + * ==> 47 + */ +#define DECIMAL_FRACTION_X2(x, y) (100 * ((x) - (y) * ((x) / (y))) / (y)) + +static void cl_print_tx_stats(struct cl_hw *cl_hw, struct cl_txl_statistics *tx_stats) +{ + int i; + u8 per = 0; + u64 total_retry = 0; + u64 total_tx = 0; + u32 total_natt = 0; + u32 avg_backoff = 0; + u32 agg_size_total = 0; + u32 agg_size_x100 = 0; + u32 total_vns_off = 0; + u32 total_vns_on = 0; + bool is_agg_in_txop = false; + struct cl_txl_agg_statistics *agg = &tx_stats->agg; + struct cl_txl_htp_statistics *htp = &tx_stats->htp; + struct cl_txl_natt_statistics *natt = &tx_stats->natt; + struct cl_txl_vns_statistics *vns = &tx_stats->vns; + struct cl_txl_fec_statistics *fec = &tx_stats->fec; + struct cl_txl_backoff_params *backoff_params = &tx_stats->backoff_params; + struct cl_txl_rts_cts_statistics *rts_cts = &tx_stats->rts_cts; + struct cl_txl_underrun_statistics *underrun = &tx_stats->underrun; + + const char *fw_tx_backoff_str[CL_MAX_FRM_TYPE] = { + [CE_BACKOFF_25] = "<25", + [CE_BACKOFF_50] = "50", + [CE_BACKOFF_100] = "100", + [CE_BACKOFF_500] = "500", + [CE_BACKOFF_1000] = "1000", + [CE_BACKOFF_5000] = "5000", + [CE_BACKOFF_10000] = "10000", + [CE_BACKOFF_20000] = "20000", + [CE_BACKOFF_20000_ABOVE] = ">20000", + }; + + /* Singles info */ + PRINT_FW(cl_hw, "TX statistics - singles\n"); + PRINT_FW(cl_hw, "------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "| q |sent |retry |lft exp |ret limit |ret lim ps|per %%|\n"); + PRINT_FW(cl_hw, "|---+----------+----------+----------+----------+----------+-----|\n"); + + for (i = 0; i < IPC_TX_QUEUE_CNT; i++) { + total_retry = tx_stats->single[i].total_rtx_cnt + + tx_stats->single[i].total_lifetime_expired_cnt + + tx_stats->single[i].total_rtx_limit_reached; + + total_tx = tx_stats->single[i].total_cnt + total_retry; + + if (total_tx == 0) + continue; + + per = (u8)div64_u64(total_retry * 100, total_tx); + + PRINT_FW(cl_hw, "|%3u|%10u|%10u|%10u|%10u|%10u|%5u|\n", + i, + tx_stats->single[i].total_cnt, + tx_stats->single[i].total_rtx_cnt, + tx_stats->single[i].total_lifetime_expired_cnt, + tx_stats->single[i].total_rtx_limit_reached, + tx_stats->single[i].total_rtx_limit_reached_ps, + per); + } + + PRINT_FW(cl_hw, "------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* Aggregation info */ + PRINT_FW(cl_hw, "TX statistics - aggregations - MAX [%u]\n", IPC_MAX_BA_SESSIONS); + PRINT_FW(cl_hw, "-----------------------------------------------------------------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "|Q |Total |Total |Lifetime|Retry |BA |BA not |BA |BA |BA |Below BA|Above BA|ACK |PS BA not|Total|\n"); + PRINT_FW(cl_hw, "| |sent |retry |expired |Limit |received |received |Cleared|Invalid|un-exp|window |window |inst BA|received |Per %%|\n"); + PRINT_FW(cl_hw, "|--+---------+---------+--------+------+---------+---------+-------+-------+------+--------+--------+-------+---------+-----|\n"); + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + total_retry = tx_stats->ba[i].total_rtx_cnt + + tx_stats->ba[i].total_lifetime_expired_cnt + + tx_stats->ba[i].total_rtx_limit_reached; + + total_tx = tx_stats->ba[i].total_cnt; + + if (total_tx == 0) + continue; + + per = (u8)div64_u64(total_retry * 100, total_tx); + + PRINT_FW(cl_hw, "|%2u|%9u|%9u|%8u|%6u|%9u|%9u|%7u|%7u|%6u|%8u|%8u|%7u|%9u|%5u|\n", + i, + tx_stats->ba[i].total_cnt, + tx_stats->ba[i].total_rtx_cnt, + tx_stats->ba[i].total_lifetime_expired_cnt, + tx_stats->ba[i].total_rtx_limit_reached, + tx_stats->ba[i].total_ba_received, + tx_stats->ba[i].total_ba_not_received_cnt, + tx_stats->ba[i].total_cleard_ba, + tx_stats->ba[i].total_invalid_ba, + tx_stats->ba[i].total_unexpected_ba, + tx_stats->ba[i].total_packets_below_baw, + tx_stats->ba[i].total_packets_above_baw, + tx_stats->ba[i].total_ack_instead_ba, + tx_stats->ba[i].total_ba_not_received_cnt_ps, + per); + } + PRINT_FW(cl_hw, "-----------------------------------------------------------------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* TID info */ + PRINT_FW(cl_hw, "----------------\n"); + PRINT_FW(cl_hw, "|TID|NumPackets|\n"); + PRINT_FW(cl_hw, "|---+----------|\n"); + + for (i = 0; i < TID_MAX; i++) { + if (tx_stats->tid[i].total_tid_desc_cnt == 0) + continue; + + PRINT_FW(cl_hw, "|%3d|%10u|\n", i, tx_stats->tid[i].total_tid_desc_cnt); + } + + PRINT_FW(cl_hw, "----------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* AC info */ + PRINT_FW(cl_hw, "---------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "| AC | 0 | 1 | 2 | 3 | 4 |\n"); + PRINT_FW(cl_hw, "|------------+----------+----------+----------+----------+----------|\n"); + PRINT_FW(cl_hw, "|Num switches|%10u|%10u|%10u|%10u|%10u|\n", + tx_stats->ac[0].total_q_switch_cnt, + tx_stats->ac[1].total_q_switch_cnt, + tx_stats->ac[2].total_q_switch_cnt, + tx_stats->ac[3].total_q_switch_cnt, + tx_stats->ac[4].total_q_switch_cnt); + PRINT_FW(cl_hw, "|Num txdesc |%10u|%10u|%10u|%10u|%10u|\n", + tx_stats->ac[0].total_ac_desc_cnt, + tx_stats->ac[1].total_ac_desc_cnt, + tx_stats->ac[2].total_ac_desc_cnt, + tx_stats->ac[3].total_ac_desc_cnt, + tx_stats->ac[4].total_ac_desc_cnt); + PRINT_FW(cl_hw, "---------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* Underrun info */ + if (underrun->length_cnt || underrun->pattern_cnt) { + PRINT_FW(cl_hw, "======== Underrun recovery statistics =======\n"); + PRINT_FW(cl_hw, "Length underrun %u\n", + underrun->length_cnt); + PRINT_FW(cl_hw, "Pattern underrun %u\n", + underrun->pattern_cnt); + PRINT_FW(cl_hw, "Total frames flushed in underrun %u\n", + underrun->flushed_frames_cnt); + PRINT_FW(cl_hw, "\n"); + } + + /* BW drop fail info */ + if (tx_stats->tx_obtain_bw_fail_cnt) { + PRINT_FW(cl_hw, "Failed to obtain BW count %u\n", tx_stats->tx_obtain_bw_fail_cnt); + PRINT_FW(cl_hw, "\n"); + } + + /* Backoff time info */ + PRINT_FW(cl_hw, "Backoff Time [us]\n"); + PRINT_FW(cl_hw, "------------------------------------------------------\n"); + PRINT_FW(cl_hw, "|Backoff | AC 0 | AC 1 | AC 2 | AC 3 |\n"); + + for (i = 0; i < CE_BACKOFF_MAX; i++) { + if (tx_stats->backoff_stats[AC_BK].backoff_hist[i] == 0 && + tx_stats->backoff_stats[AC_BE].backoff_hist[i] == 0 && + tx_stats->backoff_stats[AC_VI].backoff_hist[i] == 0 && + tx_stats->backoff_stats[AC_VO].backoff_hist[i] == 0) + continue; + + PRINT_FW(cl_hw, "|--------+----------+----------+----------+----------|\n"); + PRINT_FW(cl_hw, "| %6s |%10u|%10u|%10u|%10u|\n", + fw_tx_backoff_str[i], + tx_stats->backoff_stats[AC_BK].backoff_hist[i], + tx_stats->backoff_stats[AC_BE].backoff_hist[i], + tx_stats->backoff_stats[AC_VI].backoff_hist[i], + tx_stats->backoff_stats[AC_VO].backoff_hist[i]); + } + + PRINT_FW(cl_hw, "------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* AMSDU Packet cnt */ + PRINT_FW(cl_hw, "|--------------------|\n"); + PRINT_FW(cl_hw, "| AMSDU Packet cnt |\n"); + PRINT_FW(cl_hw, "|--------------------|\n"); + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + if (agg->amsdu_stat[i].packet_cnt_2 == 0 && + agg->amsdu_stat[i].packet_cnt_3 == 0 && + agg->amsdu_stat[i].packet_cnt_4 == 0 && + agg->amsdu_stat[i].packet_cnt_5_or_more == 0) + continue; + + PRINT_FW(cl_hw, "# session=%u\n", i); + PRINT_FW(cl_hw, "packet_cnt = 2: [%u]\n", + agg->amsdu_stat[i].packet_cnt_2); + PRINT_FW(cl_hw, "packet_cnt = 3: [%u]\n", + agg->amsdu_stat[i].packet_cnt_3); + PRINT_FW(cl_hw, "packet_cnt = 4: [%u]\n", + agg->amsdu_stat[i].packet_cnt_4); + PRINT_FW(cl_hw, "packet_cnt >= 5: [%u]\n", + agg->amsdu_stat[i].packet_cnt_5_or_more); + PRINT_FW(cl_hw, "\n"); + } + PRINT_FW(cl_hw, "\n"); + + /* Agg statistics */ + for (i = 1; i < CL_MAX_AGG_IN_TXOP; i++) { + if (agg->agg_in_txop_statistics[i]) { + is_agg_in_txop = true; + break; + } + } + + if (is_agg_in_txop) { + /* Agg in TXOP */ + PRINT_FW(cl_hw, "Agg in TXOP\n"); + PRINT_FW(cl_hw, "|----------------|\n"); + PRINT_FW(cl_hw, "| Agg | Count |\n"); + PRINT_FW(cl_hw, "|-----+----------|\n"); + + for (i = 1; i < CL_MAX_AGG_IN_TXOP; i++) { + if (!agg->agg_in_txop_statistics[i]) + continue; + + PRINT_FW(cl_hw, "|%5u|%10u|\n", + i + 1, agg->agg_in_txop_statistics[i]); + } + + PRINT_FW(cl_hw, "|----------------|\n"); + PRINT_FW(cl_hw, "\n"); + + /* Agg close reason & Agg queue switch */ + PRINT_FW(cl_hw, "Agg close reason:\n"); + PRINT_FW(cl_hw, " Not enough txdescs = %u\n", + agg->agg_in_txop_close_reason[AGG_IN_TXOP_CLOSE_REASON_NO_TXDESC]); + PRINT_FW(cl_hw, " TXOP expired = %u\n", + agg->agg_in_txop_close_reason[AGG_IN_TXOP_CLOSE_REASON_TXOP_EXPIRED]); + PRINT_FW(cl_hw, " Delba in process = %u\n", + agg->agg_in_txop_close_reason[AGG_IN_TXOP_CLOSE_REASON_ACTIVE_DELBA]); + PRINT_FW(cl_hw, "Agg queue switch:\n"); + PRINT_FW(cl_hw, " Queue switch within TXOP = %u\n", + agg->agg_in_txop_queue_switch); + PRINT_FW(cl_hw, " Queue switch abort due diff bw in TXOP = %u\n", + agg->agg_in_txop_queue_switch_abort_bw); + PRINT_FW(cl_hw, "\n"); + } + + /* RTS-CTS statistics */ + if (rts_cts->fw_rts_cnt || + rts_cts->fw_cts_cnt || + rts_cts->hw_rts_cnt || + rts_cts->hw_cts_cnt) { + PRINT_FW(cl_hw, "RTS-CTS statistics\n"); + PRINT_FW(cl_hw, "==================\n"); + PRINT_FW(cl_hw, "FW RTS frame count = %u\n", rts_cts->fw_rts_cnt); + PRINT_FW(cl_hw, "FW CTS frame count = %u\n", rts_cts->fw_cts_cnt); + PRINT_FW(cl_hw, "HW RTS frame count = %u\n", rts_cts->hw_rts_cnt); + PRINT_FW(cl_hw, "HW CTS frame count = %u\n", rts_cts->hw_cts_cnt); + PRINT_FW(cl_hw, "\n"); + } + + /* Natt statistics */ + PRINT_FW(cl_hw, "natt statistics\n"); + PRINT_FW(cl_hw, "===============\n"); + PRINT_FW(cl_hw, "agg size[0] = %u \n", agg->agg_size_statistics[0]); + PRINT_FW(cl_hw, "\n"); + + PRINT_FW(cl_hw, "-----------------------------------------------------------\n"); + PRINT_FW(cl_hw, "|agg | num sent |percent | pass per | drop per | PER per |\n"); + PRINT_FW(cl_hw, "|size| per size |per size| agg size | agg size | agg size |\n"); + PRINT_FW(cl_hw, "|----+----------+--------+----------+----------+----------|\n"); + + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) + agg_size_total += agg->agg_size_statistics[i]; + + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) { + if (agg->agg_size_statistics[i] == 0) + continue; + + total_natt = agg->packet_failed_statistics[i] + agg->packet_passed_statistics[i]; + + if (total_natt == 0) + continue; + + agg_size_x100 = 100 * agg->agg_size_statistics[i]; + + PRINT_FW(cl_hw, "|%4u|%10u|%5u.%02u|%10u|%10u|%10u|\n", + i, + agg->agg_size_statistics[i], + agg_size_x100 / agg_size_total, + DECIMAL_FRACTION_X2(agg_size_x100, agg_size_total), + agg->packet_passed_statistics[i], + agg->packet_failed_statistics[i], + ((agg->packet_failed_statistics[i] * 100) / total_natt)); + } + PRINT_FW(cl_hw, "-----------------------------------------------------------\n"); + PRINT_FW(cl_hw, "Amount of all su aggregations: %u\n", agg_size_total); + PRINT_FW(cl_hw, "\n"); + + /* Natt statistics (HTP flows) */ + PRINT_FW(cl_hw, "natt statistics HTP flows\n"); + PRINT_FW(cl_hw, "=========================\n"); + PRINT_FW(cl_hw, "-----------------------------------------------------------\n"); + PRINT_FW(cl_hw, "|agg |num sent| percent | pass per | drop per | PER per |\n"); + PRINT_FW(cl_hw, "|size|per size| per size | agg size | agg size | agg size |\n"); + PRINT_FW(cl_hw, "|----+--------+----------+----------+----------+----------|\n"); + + agg_size_total = 0; + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) + agg_size_total += agg->htp_agg_size_statistics[i]; + + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) { + if (agg->htp_agg_size_statistics[i] == 0) + continue; + + total_natt = agg->htp_packet_failed_statistics[i] + + agg->htp_packet_passed_statistics[i]; + + if (total_natt == 0) + continue; + + agg_size_x100 = 100 * agg->htp_agg_size_statistics[i]; + + PRINT_FW(cl_hw, "|%4u|%10u|%5u.%02u|%10u|%10u|%10u|\n", + i, + agg->htp_agg_size_statistics[i], + agg_size_x100 / agg_size_total, + DECIMAL_FRACTION_X2(agg_size_x100, agg_size_total), + agg->htp_packet_passed_statistics[i], + agg->htp_packet_failed_statistics[i], + (agg->htp_agg_size_statistics[i] * 100 / total_natt)); + } + PRINT_FW(cl_hw, "-----------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* Chosen frame BW */ + PRINT_FW(cl_hw, "Chosen frame BW\n"); + for (i = 0; i < NATT_BW_MAX; i++) + PRINT_FW(cl_hw, "BW[%u] = %u\n", i, natt->chosen_frame_bw[i]); + PRINT_FW(cl_hw, "\n"); + + /* Natt operation mode */ + PRINT_FW(cl_hw, "Natt operation mode\n"); + for (i = 0; i < 8; i++) + if (natt->operation_mode[i] != 0) + PRINT_FW(cl_hw, "[0x%x] = %u\n", i, natt->operation_mode[i]); + PRINT_FW(cl_hw, "\n"); + + /* Natt agg close reason */ + PRINT_FW(cl_hw, "natt agg close reason\n"); + PRINT_FW(cl_hw, "=====================\n"); + PRINT_FW(cl_hw, "Max length exceed %u\n", natt->agg_close_reason[NATT_REASON_MAX_LEN]); + PRINT_FW(cl_hw, "TXOP limit exceed %u\n", natt->agg_close_reason[NATT_REASON_TXOP_LIMIT]); + PRINT_FW(cl_hw, "MPDU number exceed %u\n", natt->agg_close_reason[NATT_REASON_MPDU_NUM]); + PRINT_FW(cl_hw, "\n"); + + /* Recovery count */ + if (tx_stats->recovery_count) { + PRINT_FW(cl_hw, "Recovery count\n"); + PRINT_FW(cl_hw, "==============\n"); + PRINT_FW(cl_hw, "Total: %u\n", tx_stats->recovery_count); + PRINT_FW(cl_hw, "\n"); + } + + /* Singelton backoff_params time */ + PRINT_FW(cl_hw, "Singelton backoff_params time:\n"); + for (i = 0; i < AC_MAX; i++) { + if (backoff_params->singelton_cnt[i]) { + avg_backoff = backoff_params->singelton_total[i] / + backoff_params->singelton_cnt[i]; + PRINT_FW(cl_hw, "ac%d avarage backoff_params %u\n", i, avg_backoff); + } else { + PRINT_FW(cl_hw, "ac%d avarage backoff_params 0\n", i); + } + } + PRINT_FW(cl_hw, "\n"); + + /* Aggregation backoff_params time */ + PRINT_FW(cl_hw, "Aggregation backoff_params time:\n"); + for (i = 0; i < AC_VO; i++) { + if (backoff_params->agg_cnt[i]) { + avg_backoff = backoff_params->agg_total[i] / + backoff_params->agg_cnt[i]; + PRINT_FW(cl_hw, "ac%d avarage backoff_params %u\n", i, avg_backoff); + } else { + PRINT_FW(cl_hw, "ac%d avarage backoff_params 0\n", i); + } + } + PRINT_FW(cl_hw, "\n"); + + /* Trigger Based traffic statistics */ + PRINT_FW(cl_hw, "Trigger Based traffic statistics:\n"); + for (i = 0; i < TID_MAX; i++) + if (htp->total_cnt[i]) + PRINT_FW(cl_hw, "TID%d total_cnt %u\n", i, htp->total_cnt[i]); + PRINT_FW(cl_hw, "\n"); + + if (htp->need_response || htp->tb_response_required) { + PRINT_FW(cl_hw, "need_response = %u\n", htp->need_response); + PRINT_FW(cl_hw, "tb_response_required = %u\n", htp->tb_response_required); + PRINT_FW(cl_hw, "ac_not_found = %u\n", htp->ac_not_found); + PRINT_FW(cl_hw, "end_of_packet_int = %u\n", htp->end_of_packet_int); + PRINT_FW(cl_hw, "tb_bw_decision = %u\n", htp->tb_bw_decision); + PRINT_FW(cl_hw, "tb_ba_thd_removed = %u\n", htp->tb_ba_thd_removed); + PRINT_FW(cl_hw, "tb_ac_unchain = %u\n", htp->tb_ac_unchain); + PRINT_FW(cl_hw, "tb_htp_unchain = %u\n", htp->tb_htp_unchain); + PRINT_FW(cl_hw, "tb_dummy_htp_tx = %u\n", htp->tb_dummy_htp_tx); + PRINT_FW(cl_hw, "tb_dummy_no_tx = %u\n", htp->tb_dummy_no_tx); + PRINT_FW(cl_hw, "msta_ba_received = %u\n", htp->msta_ba_received); + PRINT_FW(cl_hw, "msta_ba_aid_not_found = %u\n", htp->msta_ba_aid_not_found); + } + + total_vns_off = vns->off_cck + vns->off_ofdm + vns->off_ht_vht + vns->off_he; + total_vns_on = vns->on_cck + vns->on_ofdm + vns->on_ht_vht + vns->on_he; + + if (total_vns_off || total_vns_on) { + PRINT_FW(cl_hw, " -----------------------\n"); + PRINT_FW(cl_hw, " | VNS-OFF | VNS-ON |\n"); + PRINT_FW(cl_hw, "-------+----------+----------|\n"); + PRINT_FW(cl_hw, "|CCK |%10u|%10u|\n", vns->off_cck, vns->on_cck); + PRINT_FW(cl_hw, "|OFDM |%10u|%10u|\n", vns->off_ofdm, vns->on_ofdm); + PRINT_FW(cl_hw, "|HT-VHT|%10u|%10u|\n", vns->off_ht_vht, vns->on_ht_vht); + PRINT_FW(cl_hw, "|HE |%10u|%10u|\n", vns->off_he, vns->on_he); + PRINT_FW(cl_hw, "|------+----------+----------|\n"); + PRINT_FW(cl_hw, "|TOTAL |%10u|%10u|\n", total_vns_off, total_vns_on); + PRINT_FW(cl_hw, "------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + } + + if (fec->ldpc || fec->bcc) { + PRINT_FW(cl_hw, "FEC Coding:\n"); + PRINT_FW(cl_hw, "LDPC = %u\n", fec->ldpc); + PRINT_FW(cl_hw, "BCC = %u\n", fec->bcc); + PRINT_FW(cl_hw, "\n"); + } +} + +static void cl_print_tx_mu_stats(struct cl_hw *cl_hw, struct cl_txl_statistics *tx_stats) +{ + int i; + struct cl_txl_agg_statistics *agg = &tx_stats->agg; + + if (agg->mu_stats[CL_MU1_IDX].chain_cnt == 0) { + PRINT_FW(cl_hw, "~~~~~~~~~~~~~~~~~~ MU statistics - EMPTY ~~~~~~~~~~~~~~~~~~\n"); + return; + } + + PRINT_FW(cl_hw, "~~~~~~~~~~~~~~~~~~~~~~~~~ MU statistics ~~~~~~~~~~~~~~~~~~~~~~~~~\n"); + PRINT_FW(cl_hw, "\n"); + +#if (MU_MAX_STREAMS >= 4) + /* MU status statistics */ + PRINT_FW(cl_hw, "--------------------------------------------------------\n"); + PRINT_FW(cl_hw, "| | MU1 | MU2 | MU3 | MU4 | MU5 | MU6 | MU7 |\n"); + PRINT_FW(cl_hw, "|------------+-----+-----+-----+-----+-----+-----+-----|\n"); + PRINT_FW(cl_hw, "|Chain count |%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU1_IDX].chain_cnt, + agg->mu_stats[CL_MU2_IDX].chain_cnt, + agg->mu_stats[CL_MU3_IDX].chain_cnt, + agg->mu_stats[CL_MU4_IDX].chain_cnt, + agg->mu_stats[CL_MU5_IDX].chain_cnt, + agg->mu_stats[CL_MU6_IDX].chain_cnt, + agg->mu_stats[CL_MU7_IDX].chain_cnt); + PRINT_FW(cl_hw, "|Status count|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU1_IDX].status_cnt, + agg->mu_stats[CL_MU2_IDX].status_cnt, + agg->mu_stats[CL_MU3_IDX].status_cnt, + agg->mu_stats[CL_MU4_IDX].status_cnt, + agg->mu_stats[CL_MU5_IDX].status_cnt, + agg->mu_stats[CL_MU6_IDX].status_cnt, + agg->mu_stats[CL_MU7_IDX].status_cnt); + PRINT_FW(cl_hw, "--------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* MU agg-size statistics */ + PRINT_FW(cl_hw, "------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "| agg size | MU0 | MU1 | MU2 | MU3 | MU4 | MU5 | MU6 | MU7 |\n"); + PRINT_FW(cl_hw, "|----------+-----+-----+-----+-----+-----+-----+-----+-----|\n"); + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) { + if (agg->mu_agg_size_statistics[CL_MU0_IDX][i] || + agg->mu_agg_size_statistics[CL_MU1_IDX][i] || + agg->mu_agg_size_statistics[CL_MU2_IDX][i] || + agg->mu_agg_size_statistics[CL_MU3_IDX][i] || + agg->mu_agg_size_statistics[CL_MU4_IDX][i] || + agg->mu_agg_size_statistics[CL_MU5_IDX][i] || + agg->mu_agg_size_statistics[CL_MU6_IDX][i] || + agg->mu_agg_size_statistics[CL_MU7_IDX][i]) { + PRINT_FW(cl_hw, "|%10u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + i, + agg->mu_agg_size_statistics[CL_MU0_IDX][i], + agg->mu_agg_size_statistics[CL_MU1_IDX][i], + agg->mu_agg_size_statistics[CL_MU2_IDX][i], + agg->mu_agg_size_statistics[CL_MU3_IDX][i], + agg->mu_agg_size_statistics[CL_MU4_IDX][i], + agg->mu_agg_size_statistics[CL_MU5_IDX][i], + agg->mu_agg_size_statistics[CL_MU6_IDX][i], + agg->mu_agg_size_statistics[CL_MU7_IDX][i]); + } + } + PRINT_FW(cl_hw, "------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* MU BA statistics */ + PRINT_FW(cl_hw, "--------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "| MU BA statistics | MU0 | MU1 | MU2 | MU3 | MU4 | MU5 | MU6 | MU7 |\n"); + PRINT_FW(cl_hw, "|------------------+-----+-----+-----+-----+-----+-----+-----+-----|\n"); + PRINT_FW(cl_hw, "| BA Received |%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].ba_received, + agg->mu_stats[CL_MU1_IDX].ba_received, + agg->mu_stats[CL_MU2_IDX].ba_received, + agg->mu_stats[CL_MU3_IDX].ba_received, + agg->mu_stats[CL_MU4_IDX].ba_received, + agg->mu_stats[CL_MU5_IDX].ba_received, + agg->mu_stats[CL_MU6_IDX].ba_received, + agg->mu_stats[CL_MU7_IDX].ba_received); + PRINT_FW(cl_hw, "| --Unexpected BA |%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].unexpected_ba, + agg->mu_stats[CL_MU1_IDX].unexpected_ba, + agg->mu_stats[CL_MU2_IDX].unexpected_ba, + agg->mu_stats[CL_MU3_IDX].unexpected_ba, + agg->mu_stats[CL_MU4_IDX].unexpected_ba, + agg->mu_stats[CL_MU5_IDX].unexpected_ba, + agg->mu_stats[CL_MU6_IDX].unexpected_ba, + agg->mu_stats[CL_MU7_IDX].unexpected_ba); + PRINT_FW(cl_hw, "| --Cleared BA |%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].clear_ba, + agg->mu_stats[CL_MU1_IDX].clear_ba, + agg->mu_stats[CL_MU2_IDX].clear_ba, + agg->mu_stats[CL_MU3_IDX].clear_ba, + agg->mu_stats[CL_MU4_IDX].clear_ba, + agg->mu_stats[CL_MU5_IDX].clear_ba, + agg->mu_stats[CL_MU6_IDX].clear_ba, + agg->mu_stats[CL_MU7_IDX].clear_ba); + PRINT_FW(cl_hw, "| --Invalid BA |%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].invalid_ba, + agg->mu_stats[CL_MU1_IDX].invalid_ba, + agg->mu_stats[CL_MU2_IDX].invalid_ba, + agg->mu_stats[CL_MU3_IDX].invalid_ba, + agg->mu_stats[CL_MU4_IDX].invalid_ba, + agg->mu_stats[CL_MU5_IDX].invalid_ba, + agg->mu_stats[CL_MU6_IDX].invalid_ba, + agg->mu_stats[CL_MU7_IDX].invalid_ba); + PRINT_FW(cl_hw, "| --Correct BA |%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].correct_ba, + agg->mu_stats[CL_MU1_IDX].correct_ba, + agg->mu_stats[CL_MU2_IDX].correct_ba, + agg->mu_stats[CL_MU3_IDX].correct_ba, + agg->mu_stats[CL_MU4_IDX].correct_ba, + agg->mu_stats[CL_MU5_IDX].correct_ba, + agg->mu_stats[CL_MU6_IDX].correct_ba, + agg->mu_stats[CL_MU7_IDX].correct_ba); + PRINT_FW(cl_hw, "| BA not Received |%5u|%5u|%5u|%5u|%5u|%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].ba_no_received, + agg->mu_stats[CL_MU1_IDX].ba_no_received, + agg->mu_stats[CL_MU2_IDX].ba_no_received, + agg->mu_stats[CL_MU3_IDX].ba_no_received, + agg->mu_stats[CL_MU4_IDX].ba_no_received, + agg->mu_stats[CL_MU5_IDX].ba_no_received, + agg->mu_stats[CL_MU6_IDX].ba_no_received, + agg->mu_stats[CL_MU7_IDX].ba_no_received); + PRINT_FW(cl_hw, "--------------------------------------------------------------------\n"); +#elif (MU_MAX_STREAMS == 3) + /* MU status statistics */ + PRINT_FW(cl_hw, "--------------------------\n"); + PRINT_FW(cl_hw, "| | MU1 | MU2 |\n"); + PRINT_FW(cl_hw, "|------------+-----+-----|\n"); + PRINT_FW(cl_hw, "|Chain count |%5u|%5u|\n", + agg->mu_stats[CL_MU1_IDX].chain_cnt, + agg->mu_stats[CL_MU2_IDX].chain_cnt); + PRINT_FW(cl_hw, "|Status count|%5u|%5u|\n", + agg->mu_stats[CL_MU1_IDX].status_cnt, + agg->mu_stats[CL_MU2_IDX].status_cnt); + PRINT_FW(cl_hw, "--------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* MU agg-size statistics */ + PRINT_FW(cl_hw, "------------------------------\n"); + PRINT_FW(cl_hw, "| agg size | MU0 | MU1 | MU2 |\n"); + PRINT_FW(cl_hw, "|----------+-----+-----+-----|\n"); + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) { + if (agg->mu_agg_size_statistics[CL_MU0_IDX][i] || + agg->mu_agg_size_statistics[CL_MU1_IDX][i] || + agg->mu_agg_size_statistics[CL_MU2_IDX][i]) { + PRINT_FW(cl_hw, "|%10u|%5u|%5u|%5u|\n", + i, + agg->mu_agg_size_statistics[CL_MU0_IDX][i], + agg->mu_agg_size_statistics[CL_MU1_IDX][i], + agg->mu_agg_size_statistics[CL_MU2_IDX][i]); + } + } + PRINT_FW(cl_hw, "------------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* MU BA statistics */ + PRINT_FW(cl_hw, "--------------------------------------\n"); + PRINT_FW(cl_hw, "| MU BA statistics | MU0 | MU1 | MU2 |\n"); + PRINT_FW(cl_hw, "|------------------+-----+-----+-----|\n"); + PRINT_FW(cl_hw, "| BA Received |%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].ba_received, + agg->mu_stats[CL_MU1_IDX].ba_received, + agg->mu_stats[CL_MU2_IDX].ba_received); + PRINT_FW(cl_hw, "| --Unexpected BA |%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].unexpected_ba, + agg->mu_stats[CL_MU1_IDX].unexpected_ba, + agg->mu_stats[CL_MU2_IDX].unexpected_ba); + PRINT_FW(cl_hw, "| --Cleared BA |%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].clear_ba, + agg->mu_stats[CL_MU1_IDX].clear_ba, + agg->mu_stats[CL_MU2_IDX].clear_ba); + PRINT_FW(cl_hw, "| --Invalid BA |%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].invalid_ba, + agg->mu_stats[CL_MU1_IDX].invalid_ba, + agg->mu_stats[CL_MU2_IDX].invalid_ba); + PRINT_FW(cl_hw, "| --Correct BA |%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].correct_ba, + agg->mu_stats[CL_MU1_IDX].correct_ba, + agg->mu_stats[CL_MU2_IDX].correct_ba); + PRINT_FW(cl_hw, "| BA not Received |%5u|%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].ba_no_received, + agg->mu_stats[CL_MU1_IDX].ba_no_received, + agg->mu_stats[CL_MU2_IDX].ba_no_received); + PRINT_FW(cl_hw, "--------------------------------------\n"); +#else + /* MU status statistics */ + PRINT_FW(cl_hw, "--------------------\n"); + PRINT_FW(cl_hw, "| | MU1 |\n"); + PRINT_FW(cl_hw, "|------------+-----|\n"); + PRINT_FW(cl_hw, "|Chain count |%5u|\n", + agg->mu_stats[CL_MU1_IDX].chain_cnt); + PRINT_FW(cl_hw, "|Status count|%5u|\n", + agg->mu_stats[CL_MU1_IDX].status_cnt); + PRINT_FW(cl_hw, "--------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* MU agg-size statistics */ + PRINT_FW(cl_hw, "------------------------\n"); + PRINT_FW(cl_hw, "| agg size | MU0 | MU1 |\n"); + PRINT_FW(cl_hw, "|----------+-----+-----|\n"); + for (i = 1; i < DBG_STATS_MAX_AGG_SIZE; i++) { + if (agg->mu_agg_size_statistics[CL_MU0_IDX][i] || + agg->mu_agg_size_statistics[CL_MU1_IDX][i]) { + PRINT_FW(cl_hw, "|%10u|%5u|%5u|\n", + i, + agg->mu_agg_size_statistics[CL_MU0_IDX][i], + agg->mu_agg_size_statistics[CL_MU1_IDX][i]); + } + } + PRINT_FW(cl_hw, "------------------------\n"); + PRINT_FW(cl_hw, "\n"); + + /* MU BA statistics */ + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "| MU BA statistics | MU0 | MU1 |\n"); + PRINT_FW(cl_hw, "|------------------+-----+-----|\n"); + PRINT_FW(cl_hw, "| BA Received |%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].ba_received, + agg->mu_stats[CL_MU1_IDX].ba_received); + PRINT_FW(cl_hw, "| --Unexpected BA |%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].unexpected_ba, + agg->mu_stats[CL_MU1_IDX].unexpected_ba); + PRINT_FW(cl_hw, "| --Cleared BA |%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].clear_ba, + agg->mu_stats[CL_MU1_IDX].clear_ba); + PRINT_FW(cl_hw, "| --Invalid BA |%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].invalid_ba, + agg->mu_stats[CL_MU1_IDX].invalid_ba); + PRINT_FW(cl_hw, "| --Correct BA |%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].correct_ba, + agg->mu_stats[CL_MU1_IDX].correct_ba); + PRINT_FW(cl_hw, "| BA not Received |%5u|%5u|\n", + agg->mu_stats[CL_MU0_IDX].ba_no_received, + agg->mu_stats[CL_MU1_IDX].ba_no_received); + PRINT_FW(cl_hw, "--------------------------------\n"); +#endif +} + +static void cl_print_bcn_stats(struct cl_hw *cl_hw, struct cl_bcn_statistics *bcn_stats) +{ + struct beacon_timing *bcn_timing_stats = &bcn_stats->beacon_timing; + struct beacon_counters *bcn_cnt_stats = &bcn_stats->beacon_counters; + struct bcn_backup_stats *bcn_backup_stats = &bcn_stats->bcn_backup_stats; + u32 avg_time_between_bcn = 0, avg_time_bcn_chain = 0; + + if (bcn_cnt_stats->nof_time_intervals_between_beacons != 0) + avg_time_between_bcn = (bcn_timing_stats->total_bcn_time / + bcn_cnt_stats->nof_time_intervals_between_beacons); + + if (bcn_cnt_stats->bcn_chain_total_cnt != 0) + avg_time_bcn_chain = ((bcn_timing_stats->bcn_chain_total_time) / + (bcn_cnt_stats->bcn_chain_total_cnt)); + + PRINT_FW(cl_hw, "----------------------------------------\n"); + PRINT_FW(cl_hw, "Number of beacon flushed\n"); + PRINT_FW(cl_hw, "+---------+-------------+--------------+\n"); + PRINT_FW(cl_hw, "| pending | downloading | transmitting |\n"); + PRINT_FW(cl_hw, "+---------+-------------+--------------+\n"); + PRINT_FW(cl_hw, "|%-9u|%-13u|%-14u|\n", + bcn_cnt_stats->ce_txl_flushed_beacons[BCN_FLUSH_PENDING], + bcn_cnt_stats->ce_txl_flushed_beacons[BCN_FLUSH_DOWNLOADING], + bcn_cnt_stats->ce_txl_flushed_beacons[BCN_FLUSH_TRANSMITTING]); + PRINT_FW(cl_hw, "+---------+-------------+--------------+\n\n"); + + PRINT_FW(cl_hw, "----------------------------------------\n"); + PRINT_FW(cl_hw, "Time between transmission of two beacons\n"); + PRINT_FW(cl_hw, "+----------+----------+---------+----------------+\n"); + PRINT_FW(cl_hw, "| min time | max time | bcn cnt | avg time[mSec] |\n"); + PRINT_FW(cl_hw, "+----------+----------+---------+----------------+\n"); + PRINT_FW(cl_hw, "|%-10u|%-10u|%-9u|%-16u|\n", + bcn_timing_stats->min_time_from_last_bcn, + bcn_timing_stats->max_time_from_last_bcn, + bcn_cnt_stats->total_cnt, + avg_time_between_bcn); + PRINT_FW(cl_hw, "+----------+----------+---------+----------------+\n\n"); + + PRINT_FW(cl_hw, "---------------------------------------------------------------\n"); + PRINT_FW(cl_hw, "Time of beacon until chain\n"); + PRINT_FW(cl_hw, "+----------+----------+---------------+----------+\n"); + PRINT_FW(cl_hw, "| min time | max time | bcn chain cnt | avg time |\n"); + PRINT_FW(cl_hw, "+----------+----------+---------------+----------+\n"); + PRINT_FW(cl_hw, "|%-10u|%-10u|%-15u|%-10u|\n", + bcn_timing_stats->bcn_chain_min_time, + bcn_timing_stats->bcn_chain_max_time, + bcn_cnt_stats->bcn_chain_total_cnt, + avg_time_bcn_chain); + PRINT_FW(cl_hw, "+----------+----------+---------------+----------+\n\n"); + + PRINT_FW(cl_hw, "---------------------------------------------------------------------\n"); + PRINT_FW(cl_hw, " beacon pending-chain path max time = %u\n", + bcn_timing_stats->bcn_pending_2_chain_max_time); + PRINT_FW(cl_hw, " beacon pending-chain not in time count = %u\n", + bcn_cnt_stats->pending2chain_not_in_threshold_cnt); + PRINT_FW(cl_hw, " Max time until recievd beacon from driver = %u\n", + bcn_timing_stats->max_bcn_time_until_get_beacon_from_driver_in_tbtt); + PRINT_FW(cl_hw, " Total count of beacon flushed because didn't received in time = %u\n", + bcn_cnt_stats->bcn_time_from_driver_not_in_threshold_cnt); + PRINT_FW(cl_hw, " Max num of beacon not received from driver = %u\n", + bcn_cnt_stats->max_bcn_not_received_from_host); + PRINT_FW(cl_hw, "---------------------------------------------------------------------\n"); + + PRINT_FW(cl_hw, "+--------------------------------------+\n"); + PRINT_FW(cl_hw, "| Backup beacon stats |\n"); + PRINT_FW(cl_hw, "+------+------+---------+--------------+\n"); + PRINT_FW(cl_hw, "| Used | TX | flushed | Max in a row |\n"); + PRINT_FW(cl_hw, "+------+------+---------+--------------+\n"); + PRINT_FW(cl_hw, "|%6u|%6u|%9u|%14u|\n", + bcn_backup_stats->bcn_backup_used_cnt, + bcn_backup_stats->bcn_backup_tx_cnt, + bcn_backup_stats->bcn_backup_flushed_cnt, + bcn_backup_stats->bcn_backup_max_used_in_arow_cnt); + PRINT_FW(cl_hw, "+------+------+---------+--------------+\n"); +} + +static void cl_print_rate_fallback_stats(struct cl_hw *cl_hw, + struct cl_rate_drop_statistics *stats) +{ + PRINT_FW(cl_hw, "\n"); + PRINT_FW(cl_hw, "---------------------------\n"); + PRINT_FW(cl_hw, " Fallback statistics\n"); + PRINT_FW(cl_hw, "---------------------------\n"); + PRINT_FW(cl_hw, "ba_per_stats = %u\n", + stats->drop_reason[AGG_TX_RATE_DROP_MAX_BA_PER_REACHED]); + PRINT_FW(cl_hw, "ba_not_received_stats = %u\n", + stats->drop_reason[AGG_TX_RATE_DROP_MAX_BA_NOT_RECEIVED_REACHED]); + PRINT_FW(cl_hw, "max_retry_reached = %u\n", + stats->drop_reason[AGG_TX_RATE_DROP_MAX_RETRY_REACHED]); +} + +static void cl_print_rx_stats_precent(struct cl_hw *cl_hw, const char *str, u32 x, u32 y) +{ + /* + * Example: + * x = 541, y = 19 + * Result 28.4736 + */ + u32 integer = x / y; + u32 fraction = 10000 * (x - y * (x / y)) / y; + + PRINT_FW(cl_hw, "%s = %u.%04u\n", str, integer, fraction); +} + +static void cl_print_rx_stats(struct cl_hw *cl_hw, struct cl_rxl_statistics *rx_stats) +{ + int i, mu_idx, total_rx = 0; + enum format_mode fm; + + PRINT_FW(cl_hw, "=========================================\n"); + PRINT_FW(cl_hw, " Global RX stats\n"); + PRINT_FW(cl_hw, "=========================================\n"); + PRINT_FW(cl_hw, "host rxelem not ready = %u\n", + rx_stats->host_rxelem_not_ready_cnt); + PRINT_FW(cl_hw, "MSDU host rxelem not ready = %u\n", + rx_stats->msdu_host_rxelem_not_ready_cnt); + PRINT_FW(cl_hw, "MSDU dma pool not ready = %u\n", + rx_stats->dma_rx_pool_not_ready_cnt); + PRINT_FW(cl_hw, "Percent of Rx CCA busy = %u\n", + rx_stats->cca_busy_percent); + PRINT_FW(cl_hw, "Percent of Rx mine CCA busy = %u\n", + rx_stats->rx_mine_busy_percent); + PRINT_FW(cl_hw, "Percent of Tx mine busy = %u\n", + rx_stats->tx_mine_busy_percent); + PRINT_FW(cl_hw, "\n"); + + PRINT_FW(cl_hw, "=== Rx Format ==\n"); + for (fm = 0; fm < FORMATMOD_MAX; fm++) + if (rx_stats->stats_rx_format[fm]) + PRINT_FW(cl_hw, "Rx Format[%d] = %u\n", fm, rx_stats->stats_rx_format[fm]); + + PRINT_FW(cl_hw, "=== Rx Decryption errors ==\n"); + for (i = RHD_DECR_ICVFAIL_IDX; i < RHD_DECR_IDX_MAX; i++) + if (rx_stats->decrypt_err[i]) + PRINT_FW(cl_hw, "decrypt_err[%d] = %u\n", i, rx_stats->decrypt_err[i]); + + /* RX prints */ + for (mu_idx = 0; mu_idx < MU_UL_MAX; mu_idx++) { + PRINT_FW(cl_hw, "============================================\n"); + PRINT_FW(cl_hw, "===== RX MAC HW MU [%2d] =====\n", mu_idx); + PRINT_FW(cl_hw, "============================================\n"); + total_rx = rx_stats->total_rx_packets[mu_idx] + + rx_stats->fcs_error_counter[mu_idx] + + rx_stats->phy_error_counter[mu_idx] + + rx_stats->ampdu_incorrect_received_counter[mu_idx] + + rx_stats->delimiter_error_counter[mu_idx] + + rx_stats->rx_fifo_overflow_err_cnt[mu_idx]; + + if (total_rx == 0) + continue; + + for (i = 0; i < MAX_HANDLED_FRM_TYPE; i++) { + if (!rx_stats->emb_ll1_handled_frame_counter[mu_idx][i]) + continue; + + PRINT_FW(cl_hw, "emb_handled_packet[%d] - %u\n", + i, rx_stats->emb_ll1_handled_frame_counter[mu_idx][i]); + } + + PRINT_FW(cl_hw, "Total packets dropped (pckt_len > %u) %u\n", + rx_stats->max_mpdu_data_len[mu_idx], + rx_stats->rx_pckt_exceed_max_len_cnt[mu_idx]); + PRINT_FW(cl_hw, "Number of bad formated BA frames = %u\n", + rx_stats->rx_pckt_bad_ba_statinfo_cnt[mu_idx]); + PRINT_FW(cl_hw, "Max occupancy list2 = %u\n", + rx_stats->rhd_ll2_max_cnt[mu_idx]); + PRINT_FW(cl_hw, "Max occupancy list1 = %u\n", + rx_stats->rhd_ll1_max_cnt[mu_idx]); + PRINT_FW(cl_hw, "\n"); + PRINT_FW(cl_hw, "Total Qos MPDU received = %u\n", + rx_stats->total_rx_packets[mu_idx]); + PRINT_FW(cl_hw, "Total Aggregation received = %u\n", + rx_stats->total_agg_packets[mu_idx]); + PRINT_FW(cl_hw, "Number of Rx Fifo Overflow = %u\n", + rx_stats->rx_fifo_overflow_err_cnt[mu_idx]); + PRINT_FW(cl_hw, "Number of FCS ERROR = %u\n", + rx_stats->fcs_error_counter[mu_idx]); + PRINT_FW(cl_hw, "Number of PHY ERROR = %u\n", + rx_stats->phy_error_counter[mu_idx]); + PRINT_FW(cl_hw, "Number of AMPDUS = %u\n", + rx_stats->ampdu_received_counter[mu_idx]); + PRINT_FW(cl_hw, "Number of Incorrect AMPDUS = %u\n", + rx_stats->ampdu_incorrect_received_counter[mu_idx]); + PRINT_FW(cl_hw, "Number of Delimiter errors = %u\n", + rx_stats->delimiter_error_counter[mu_idx]); + + if (rx_stats->total_rx_packets[mu_idx]) { + u32 total_rx_packets = rx_stats->total_rx_packets[mu_idx] + + rx_stats->rx_fifo_overflow_err_cnt[mu_idx] + + rx_stats->fcs_error_counter[mu_idx] + + rx_stats->phy_error_counter[mu_idx] + + rx_stats->delimiter_error_counter[mu_idx]; + + cl_print_rx_stats_precent(cl_hw, + "Rx Fifo Overflow percent ", + 100 * rx_stats->rx_fifo_overflow_err_cnt[mu_idx], + total_rx_packets); + cl_print_rx_stats_precent(cl_hw, + "FCS Error percent ", + 100 * rx_stats->fcs_error_counter[mu_idx], + total_rx_packets); + cl_print_rx_stats_precent(cl_hw, + "Phy Error percent ", + 100 * rx_stats->phy_error_counter[mu_idx], + total_rx_packets); + cl_print_rx_stats_precent(cl_hw, + "Delimiter Error percent ", + 100 * rx_stats->delimiter_error_counter[mu_idx], + total_rx_packets); + } + + PRINT_FW(cl_hw, "Current NAV value = %u\n", rx_stats->nav_value[mu_idx]); + + PRINT_FW(cl_hw, "\n"); + PRINT_FW(cl_hw, "Rx LL split stats: 1st LL interrupts = %u\n", + rx_stats->counter_timer_trigger_ll1[mu_idx]); + PRINT_FW(cl_hw, "Rx LL split stats: 2nd LL interrupts = %u\n", + rx_stats->counter_timer_trigger_ll2[mu_idx]); + PRINT_FW(cl_hw, "Number of incorrect format mode received = %u\n", + rx_stats->rx_incorrect_format_mode[mu_idx]); + + for (i = 0; i < RX_CLASSIFICATION_MAX; i++) { + if (!rx_stats->rx_class_counter[mu_idx][i]) + continue; + + PRINT_FW(cl_hw, "Rx classification rules stats: Rx rule%d= %u\n", + i, rx_stats->rx_class_counter[mu_idx][i]); + } + + if (rx_stats->rx_class_int_counter[mu_idx]) + PRINT_FW(cl_hw, "Rx classification interrupts rules = %u\n", + rx_stats->rx_class_int_counter[mu_idx]); + + PRINT_FW(cl_hw, "\n"); + PRINT_FW(cl_hw, "Rx Implicit BF statistics: = %u\n", + rx_stats->rx_imp_bf_counter[mu_idx]); + PRINT_FW(cl_hw, "Rx Implicit BF interrupts stats = %u\n", + rx_stats->rx_imp_bf_int_counter[mu_idx]); + PRINT_FW(cl_hw, "RXM STATISTICS\n"); + PRINT_FW(cl_hw, "rxm_stats_overflow = %u\n", + rx_stats->rxm_stats_overflow[mu_idx]); + PRINT_FW(cl_hw, "rx_incorrect_format_mode= %u\n", + rx_stats->rx_incorrect_format_mode[mu_idx]); + PRINT_FW(cl_hw, "correct_received_mpdu = %u\n", + rx_stats->correct_received_mpdu[mu_idx]); + PRINT_FW(cl_hw, "incorrect_received_mpdu = %u\n", + rx_stats->incorrect_received_mpdu[mu_idx]); + PRINT_FW(cl_hw, "discarded_mpdu = %u\n", + rx_stats->discarded_mpdu[mu_idx]); + PRINT_FW(cl_hw, "incorrect_delimiter = %u\n", + rx_stats->incorrect_delimiter[mu_idx]); + PRINT_FW(cl_hw, "rts_bar_cnt = %u\n", + rx_stats->rts_bar_cnt[mu_idx]); + PRINT_FW(cl_hw, "rxm_mpdu_cnt = %u\n", + rx_stats->rxm_mpdu_cnt[mu_idx]); + + if (rx_stats->rxm_mpdu_cnt[mu_idx]) { + PRINT_FW(cl_hw, "rxm_rule0_match = %u\n", + rx_stats->rxm_rule0_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_rule1_match = %u\n", + rx_stats->rxm_rule1_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_rule2_match = %u\n", + rx_stats->rxm_rule2_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_rule3_match = %u\n", + rx_stats->rxm_rule3_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_rule4_match = %u\n", + rx_stats->rxm_rule4_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_rule5_match = %u\n", + rx_stats->rxm_rule5_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_rule6_match = %u\n", + rx_stats->rxm_rule6_match[mu_idx]); + PRINT_FW(cl_hw, "rxm_default_rule_match = %u\n", + rx_stats->rxm_default_rule_match[mu_idx]); + PRINT_FW(cl_hw, "RXM amsdu stat not supported. use iwcl stats instead\n"); + } + + /* RX AMSDU prints */ + PRINT_FW(cl_hw, "\n"); + PRINT_FW(cl_hw, "RX AMSDU STATS\n"); + + PRINT_FW(cl_hw, "AMSDU RX cnt = %u\n", + rx_stats->stats_tot_rx_amsdu_cnt[mu_idx]); + + for (i = 0; i < ARRAY_SIZE(rx_stats->stats_rx_amsdu_cnt[mu_idx]); i++) + if (rx_stats->stats_rx_amsdu_cnt[mu_idx][i]) + PRINT_FW(cl_hw, "A-MSDU of %d = %u\n", + i + 1, rx_stats->stats_rx_amsdu_cnt[mu_idx][i]); + + PRINT_FW(cl_hw, "A-MSDU RX errors:\n"); + for (i = 0; i < AMSDU_DEAGGREGATION_ERR_MAX; i++) + if (rx_stats->stats_rx_amsdu_err[mu_idx][i]) + PRINT_FW(cl_hw, " err_id[%d] = %u\n", + i, rx_stats->stats_rx_amsdu_err[mu_idx][i]); + } + + PRINT_FW(cl_hw, "Frequency offset:\n"); + for (i = 0; i < FREQ_OFFSET_TABLE_IDX_MAX; i++) + if (rx_stats->frequency_offset[i]) + PRINT_FW(cl_hw, "frequency_offset = %u\n", rx_stats->frequency_offset[i]); +} + +static void cl_print_trigger_flow_stats(struct cl_hw *cl_hw, + struct cl_trigger_flow_statistics *tf_stats) +{ + u16 idx; + struct cl_rx_trigger_based_stats *tb_stats = &cl_hw->tb_stats; + + if (!tb_stats->enable) { + PRINT_FW(cl_hw, "WARNING: Trigger based statistics are disabled!\n"); + return; + } + + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, " Trigger flow statistics\n"); + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "Sent trigger frames\n"); + PRINT_FW(cl_hw, "---------------|---AC0---|---AC1---|---AC2---|---AC3---|\n"); + PRINT_FW(cl_hw, "BASIC TRIGGER: |%9u|%9u|%9u|%9u|\n", + tf_stats->single_trigger_sent[TRIGGER_FLOW_BASIC_TRIGGER_TYPE][AC_BK], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BASIC_TRIGGER_TYPE][AC_BE], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BASIC_TRIGGER_TYPE][AC_VI], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BASIC_TRIGGER_TYPE][AC_VO]); + PRINT_FW(cl_hw, "BSRP: |%9u|%9u|%9u|%9u|\n", + tf_stats->single_trigger_sent[TRIGGER_FLOW_BSRP_TYPE][AC_BK], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BSRP_TYPE][AC_BE], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BSRP_TYPE][AC_VI], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BSRP_TYPE][AC_VO]); + PRINT_FW(cl_hw, "BFRP: |%9u|%9u|%9u|%9u|\n", + tf_stats->single_trigger_sent[TRIGGER_FLOW_BFRP_TYPE][AC_BK], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BFRP_TYPE][AC_BE], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BFRP_TYPE][AC_VI], + tf_stats->single_trigger_sent[TRIGGER_FLOW_BFRP_TYPE][AC_VO]); + PRINT_FW(cl_hw, "HTP FAILURE: |%9u|%9u|%9u|%9u|\n", + tf_stats->htp_rx_failure[AC_BK], + tf_stats->htp_rx_failure[AC_BE], + tf_stats->htp_rx_failure[AC_VI], + tf_stats->htp_rx_failure[AC_VO]); + + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "TRIGGER BASED MPDUs PER MAC HW\n"); + PRINT_FW(cl_hw, "--------------------------------\n"); + tf_stats->trigger_based_mpdu[0] = tb_stats->total; + + for (idx = 1; idx < MU_UL_MAX; idx++) + tf_stats->trigger_based_mpdu[0] -= tf_stats->trigger_based_mpdu[idx]; + + for (idx = 0; idx < MU_UL_MAX; idx++) + PRINT_FW(cl_hw, "MAC HW %u - %10u\n", idx, tf_stats->trigger_based_mpdu[idx]); + + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "TRIGGER BASED AGGREGATIONS SIZE\n"); + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "|-SIZE-|---TB AGGS---|\n"); + + for (idx = 1; idx < DBG_STATS_MAX_AGG_SIZE; idx++) { + if (tb_stats->data[idx] == 0) + continue; + + PRINT_FW(cl_hw, "| %4u |%13u|\n", idx, tb_stats->data[idx]); + } + + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "TRIGGER BASED QOS NULL AGGR SIZE\n"); + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "|-SIZE-|---TB AGGS---|\n"); + + for (idx = 1; idx < TID_MAX + 1; idx++) + if (tb_stats->qos_null[idx] > 0) + PRINT_FW(cl_hw, "| %4u |%13u|\n", idx, tb_stats->qos_null[idx]); + + if (tb_stats->qos_null[TID_MAX + 1] > 0) + PRINT_FW(cl_hw, "| >8 |%13u|\n", tb_stats->qos_null[TID_MAX + 1]); +} + +static void cl_print_dyn_calib_stats(struct cl_hw *cl_hw, + struct cl_dyn_calib_statistics *dyn_cal_stats) +{ + u8 i, j; + + PRINT_FW(cl_hw, "--------------------------------\n"); + PRINT_FW(cl_hw, "Dynamic Calibration Information\n"); + PRINT_FW(cl_hw, "--------------------------------\n\n"); + + PRINT_FW(cl_hw, "Default Dynamic Calibation Value = %u\n\n", + dyn_cal_stats->default_dyn_cal_val); + + for (i = dyn_cal_stats->dyn_cal_debug_info_ix, j = 0; + j < DYN_CAL_DEBUG_NUM_ITER; + (i = ((i + 1) % 3)), j++) { + struct dyn_cal_debug_info_t *dyn_cal_debug_info = + &dyn_cal_stats->dyn_cal_debug_info[i]; + + if (dyn_cal_stats->is_multi_client_mode) + PRINT_FW(cl_hw, + "calib_num = %u, min_val = %d, max_val = %d, min_config = %u, " + "max_config = %u, curr_config = %u, new_config = %u\n", + dyn_cal_debug_info->calib_num, + (s32)dyn_cal_debug_info->dyn_cal_min_val, + (s32)dyn_cal_debug_info->dyn_cal_max_val, + dyn_cal_debug_info->min_config, + dyn_cal_debug_info->max_config, + dyn_cal_debug_info->curr_config, + dyn_cal_debug_info->new_config); + else + PRINT_FW(cl_hw, + "calib_num = %u, iter_num = %u, config_val_prev = %u, " + "measured_val = %u, new_config_val = %u\n", + dyn_cal_debug_info->calib_num, + dyn_cal_debug_info->iter_num, + dyn_cal_debug_info->curr_config, + dyn_cal_debug_info->measured_val, + dyn_cal_debug_info->new_config); + } + + if (dyn_cal_stats->mac_phy_sync_err_cnt) + PRINT_FW(cl_hw, "mac_phy_sync_err_cnt = %u\n\n", + dyn_cal_stats->mac_phy_sync_err_cnt); + + PRINT_FW(cl_hw, "\n-----------------------------------------\n\n"); +} + +static void cl_print_bf_stats(struct cl_hw *cl_hw, struct cl_bf_statistics *bf_stats) +{ + u32 idx; + bool should_print = false; + u16 *tx_bf_data_err; + + for (idx = 0; idx < BF_DB_MAX; idx++) + if (bf_stats->print_active_free_list == bf_stats->stats_data[idx].is_active_list) { + should_print = true; + break; + } + + if (!should_print) + return; + + /* Info phase 1 */ + PRINT_FW(cl_hw, "List of non active BFs:\n"); + PRINT_FW(cl_hw, "============================\n"); + PRINT_FW(cl_hw, "BF_CTRL statistics\n"); + PRINT_FW(cl_hw, "+-----+----+----+-------+-------+----------------+-----------------+--------------+---------------+-----------------+---------------+--------------+------------+-------+\n"); + PRINT_FW(cl_hw, "|INDEX|#NDP|#BFP|#SU BFR|#MU BFR|#BFR_BW_MISMATCH|#BFR_NSS_MISMATCH|#SOUNDING_CHBW|#TOKEN_MISMATCH|#NDP_NDPA_TX_DROP|#BFR_RX_ERR_ACK|#BFR SEGMENTED|#RESOURCE_NA|STA_IDX|\n"); + PRINT_FW(cl_hw, "+-----+----+----+-------+-------+----------------+-----------------+--------------+---------------+-----------------+---------------+--------------+------------+-------+\n"); + + for (idx = 0; idx < BF_DB_MAX; idx++) { + if (bf_stats->print_active_free_list != bf_stats->stats_data[idx].is_active_list) + continue; + + PRINT_FW(cl_hw, + "|%5u|%4u|%4u|%7u|%7u|%16u|%17u|%14u|%15u|%17u|%15u|%14u|%12u|%7u|\n", + idx, + bf_stats->stats_data[idx].dbg.ndp_cnt, + bf_stats->stats_data[idx].dbg.bfp_cnt, + bf_stats->stats_data[idx].dbg.su_bfr_cnt, + bf_stats->stats_data[idx].dbg.mu_bfr_cnt, + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_BW_MISMATCH], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_NSS_MISMATCH], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_SOUNDING_CHBW], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_TOKEN_MISMATCH], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_NDP_DROP], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_MISS_ACK], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_SEGMENTED_DROP], + bf_stats->stats_data[idx].dbg.bf_invalid_cnt[BFR_RX_ERR_RESOURCE_NA], + bf_stats->stats_data[idx].sta_idx); + } + + PRINT_FW(cl_hw, "+-----+----+----+-------+-------+----------------+-----------------+--------------+---------------+-----------------+---------------+--------------+------------+-------+\n"); + + /* Info phase 2 */ + PRINT_FW(cl_hw, "statistic BF DATA FRAMESs:\n"); + PRINT_FW(cl_hw, "============================\n"); + PRINT_FW(cl_hw, "BF_CTRL statistics\n"); + PRINT_FW(cl_hw, "+-----+-----------+------------+-------------+-----------------+----------------+-----------------+-----------+-----------+----------+------------------+-----------------+-------+\n"); + PRINT_FW(cl_hw, "|INDEX|#ACTIVE_IDX|#PASSIVE_IDX|#ERR_BFR_MISS|#ERR_BFR_OUTDATED|#ERR_BW_MISMATCH|#ERR_NSS_MISMATCH|#BF_DATA_OK|#BUFF_IN_PS|#REL_IN_PS|#BUFF_RESOURCE_ERR|#REL_RESOURCE_ERR|STA_IDX|\n"); + PRINT_FW(cl_hw, "+-----+-----------+------------+-------------+-----------------+----------------+-----------------+-----------+-----------+----------+------------------+-----------------+-------+\n"); + + for (idx = 0; idx < BF_DB_MAX; idx++) { + if (bf_stats->print_active_free_list != bf_stats->stats_data[idx].is_active_list) + continue; + + tx_bf_data_err = bf_stats->stats_data[idx].dbg.tx_bf_data_err; + + PRINT_FW(cl_hw, + "|%5u|%11u|%12u|%13u|%17u|%16u|%17u|%11u|%11u|%10u|%18u|%17u|%7u|\n", + idx, + bf_stats->stats_data[idx].active_dsp_idx, + bf_stats->stats_data[idx].passive_dsp_idx, + tx_bf_data_err[TX_BF_DATA_ERR_BFR_MISS], + tx_bf_data_err[TX_BF_DATA_ERR_BFR_OUTDATED], + tx_bf_data_err[TX_BF_DATA_ERR_MISMATCH_BW], + tx_bf_data_err[TX_BF_DATA_ERR_MISMATCH_NSS], + tx_bf_data_err[TX_BF_DATA_OK], + tx_bf_data_err[TX_BF_DATA_BUFFERED_PS_STA], + tx_bf_data_err[TX_BF_DATA_RELEASED_PS_STA], + tx_bf_data_err[TX_BF_DATA_BUFFERED_RESOURCE_ERR], + tx_bf_data_err[TX_BF_DATA_RELEASED_RESOURCE_ERR], + bf_stats->stats_data[idx].sta_idx); + } + + PRINT_FW(cl_hw, "+-----+-----------+------------+-------------+-----------------+----------------+-----------------+-----------+-----------+----------+------------------+-----------------+-------+\n"); +} + +static void cl_print_stats_handler(struct work_struct *ws) +{ + struct cl_print_stats_work *stats_work = container_of(ws, struct cl_print_stats_work, ws); + struct cl_hw *cl_hw = stats_work->cl_hw; + u32 dbg_info_type = stats_work->dbg_info_type; + + if (dbg_info_type == DBG_INFO_TX_STATS) { + struct cl_txl_statistics *tx_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.tx_stats); + + cl_print_tx_stats(cl_hw, tx_stats); + cl_print_tx_mu_stats(cl_hw, tx_stats); + } else if (dbg_info_type == DBG_INFO_BCN_STATS) { + struct cl_bcn_statistics *bcn_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.bcn_stats); + + cl_print_bcn_stats(cl_hw, bcn_stats); + } else if (dbg_info_type == DBG_INFO_RX_STATS) { + struct cl_rxl_statistics *rx_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.rx_stats); + + cl_print_rx_stats(cl_hw, rx_stats); + } else if (dbg_info_type == DBG_INFO_DYN_CAL_STATS) { + struct cl_dyn_calib_statistics *dyn_cal_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.dyn_calib_stats); + + cl_print_dyn_calib_stats(cl_hw, dyn_cal_stats); + } else if (dbg_info_type == DBG_INFO_RATE_FALLBACK_STATS) { + struct cl_rate_drop_statistics *agg_rate_drop_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.rate_drop_stats); + + cl_print_rate_fallback_stats(cl_hw, agg_rate_drop_stats); + } else if (dbg_info_type == DBG_INFO_BF) { + struct cl_bf_statistics *bf_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.bf_stats); + + cl_print_bf_stats(cl_hw, bf_stats); + } else if (dbg_info_type == DBG_INFO_TRIGGER_FLOW) { + struct cl_trigger_flow_statistics *tf_stats = + &(((struct dbg_info *)cl_hw->dbginfo.buf)->u.trigger_flow_stats); + + cl_print_trigger_flow_stats(cl_hw, tf_stats); + } + +#ifdef CONFIG_CL_PCIE + cl_ipc_dbginfobuf_push(cl_hw->ipc_env, cl_hw->dbginfo.dma_addr); +#endif + kfree(stats_work); +} + +static void cl_schedule_print_stats(struct cl_hw *cl_hw, u32 dbg_info_type) +{ + struct cl_print_stats_work *stats_work = + kzalloc(sizeof(*stats_work), GFP_ATOMIC); + + if (stats_work) { + INIT_WORK(&stats_work->ws, cl_print_stats_handler); + stats_work->cl_hw = cl_hw; + stats_work->dbg_info_type = dbg_info_type; + + /* Schedule work, the work will be executed in the background */ + queue_work(cl_hw->drv_workqueue, &stats_work->ws); + } else { + cl_dbg_err(cl_hw, "stats_work allocation failed\n"); + } +} + +void cl_fw_dbg_handler(struct cl_hw *cl_hw) +{ + struct dbg_info *dbg_info = NULL; + + /* Function called upon DBG_INFO_IND message reception. */ + dma_sync_single_for_device(cl_hw->chip->dev, cl_hw->dbginfo.dma_addr, + cl_hw->dbginfo.bufsz, DMA_FROM_DEVICE); + dbg_info = (struct dbg_info *)cl_hw->dbginfo.buf; + + if (dbg_info->u.type == DBG_INFO_DUMP) { + cl_dbg_info(cl_hw, "type %u): dump received\n", + cl_hw->dbginfo.buf->u.dump.general_data.error_type); + cl_coredump_trigger(cl_hw); + } else if (dbg_info->u.type < DBG_INFO_MAX) { + cl_schedule_print_stats(cl_hw, dbg_info->u.type); + } else { + cl_dbg_warn(cl_hw, "Debug info wrong type - %u\n", dbg_info->u.type); + } +} + +static int cl_fw_dbg_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "fw usage:\n" + "-a : Trigger assert error (echo ASSERT_ERR > errsim)\n" + "-b : Trigger assert recovery (echo 1 > test_mode)\n" + "-d : Set trigger-based debug statistics [0-dis/1-en]\n" + "-m : Trigger firmware dump (echo 1 > mactrace)\n" + "-s : Print statistics (echo param > stat_print)\n" + "-t : Test mode command (cmd + 0 to 5 parameters)\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +int cl_fw_dbg_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + u32 expected_params = 0; + bool assert_err = false; + bool assert_rec = false; + bool dbg_tb_stats = false; + bool mactrace = false; + bool stat_print = false; + bool test_mode = false; + + switch (cli_params->option) { + case 'a': + assert_err = true; + expected_params = 0; + break; + case 'b': + assert_rec = true; + expected_params = 0; + break; + case 'd': + dbg_tb_stats = true; + expected_params = 1; + break; + case 'm': + mactrace = true; + expected_params = 0; + break; + case 's': + stat_print = true; + expected_params = 1; + break; + case 't': + test_mode = true; + break; + case '?': + return cl_fw_dbg_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if ((expected_params != cli_params->num_params) && !test_mode) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (assert_err) { + cl_msg_tx_key_del(cl_hw, 0xFF); + return 0; + } + + if (assert_rec) { + u32 params[TEST_MODE_PARAM_MAX + 1] = {1, 0, 0, 0, 0, 0}; + + cl_msg_tx_dbg_test_mode(cl_hw, params); + return 0; + } + + if (dbg_tb_stats) { + cl_hw->tb_stats.enable = (bool)cli_params->params[0]; + pr_debug("TB statistics %s\n", cl_hw->tb_stats.enable ? "enable" : "disable"); + return 0; + } + + if (mactrace) { + cl_msg_tx_dbg_trigger(cl_hw, "Force trigger"); + return 0; + } + + if (stat_print) { + u32 bitmap = (u32)cli_params->params[0]; + + cl_msg_tx_dbg_print_stats(cl_hw, bitmap, 0, 0, 0, 0); + return 0; + } + + if (test_mode) { + u32 params[TEST_MODE_PARAM_MAX + 1] = {0}; + u8 i; + + if (cli_params->num_params == 0 || + cli_params->num_params > TEST_MODE_PARAM_MAX + 1) { + cl_dbg_err(cl_hw, "Test mode expects cmd + 0 to 5 parameters\n"); + goto out_err; + } + + for (i = 0; i < cli_params->num_params; i++) + params[i] = (u32)cli_params->params[i]; + + cl_msg_tx_dbg_test_mode(cl_hw, params); + return 0; + } + +out_err: + return -EIO; +} + +static void cl_dbg_dump_check_params(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int is_mismatch = false; + struct dbg_meta_data *dbg_metadata = &dump->common_info.dbg_metadata; + + if (dbg_metadata->lmac_req_buf_size != sizeof(struct dbg_error_trace_info_drv) || + dbg_metadata->physical_queue_cnt != CL_MAX_BA_PHYSICAL_QUEUE_CNT || + dbg_metadata->agg_index_max != AGG_IDX_MAX || + dbg_metadata->ce_ac_max != CE_AC_MAX || + dbg_metadata->mu_user_max != MU_MAX_STREAMS || + dbg_metadata->txl_exch_trace_depth != DBG_TXL_FRAME_EXCH_TRACE_DEPTH || + dbg_metadata->mac_hw_regs_max != HAL_MACHW_REG_NUM || + dbg_metadata->phy_hw_regs_max != PHY_HW_DBG_REGS_CNT) + is_mismatch = true; + + if (is_mismatch) { + *pos += scnprintf(buf + *pos, bufsz - *pos, + "\nWarning!!!!\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "DBG metadata mismatch bwtween FW & DRV!!!!\n"); + } + + if (dbg_metadata->lmac_req_buf_size != (u32)(sizeof(struct dbg_error_trace_info_drv))) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "FW buf size %u expected %u\n", + dbg_metadata->lmac_req_buf_size, + (u32)(sizeof(struct dbg_error_trace_info_drv))); + + if (dbg_metadata->physical_queue_cnt != CL_MAX_BA_PHYSICAL_QUEUE_CNT) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "physical queue cn %u expected %u\n", + dbg_metadata->physical_queue_cnt, + CL_MAX_BA_PHYSICAL_QUEUE_CNT); + + if (dbg_metadata->agg_index_max != AGG_IDX_MAX) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "agg idx max %u expected %u\n", + dbg_metadata->agg_index_max, AGG_IDX_MAX); + + if (dbg_metadata->ce_ac_max != CE_AC_MAX) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "ac max %u expected %u\n", + dbg_metadata->ce_ac_max, CE_AC_MAX); + + if (dbg_metadata->mu_user_max != MU_MAX_STREAMS) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "MU MAX %u expected %u\n", + dbg_metadata->mu_user_max, MU_MAX_STREAMS); + + if (dbg_metadata->txl_exch_trace_depth != DBG_TXL_FRAME_EXCH_TRACE_DEPTH) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "txl trace depth %u expected %u\n", + dbg_metadata->txl_exch_trace_depth, + DBG_TXL_FRAME_EXCH_TRACE_DEPTH); + + if (dbg_metadata->mac_hw_regs_max != HAL_MACHW_REG_NUM) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "MAC HW regs cnt %u expected %u\n", + dbg_metadata->mac_hw_regs_max, + HAL_MACHW_REG_NUM); + + if (dbg_metadata->phy_hw_regs_max != PHY_HW_DBG_REGS_CNT) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "PHY HW regs %u expected %u\n", + dbg_metadata->phy_hw_regs_max, + PHY_HW_DBG_REGS_CNT); +} + +static void cl_dbg_policy_table_print(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct tx_policy_tbl *policy_table_ptr, + u32 policy_table_addr) +{ + *pos += scnprintf(buf + *pos, bufsz - *pos, + "=================================================" + "= Policy Table 0x%x =============================" + "============================\n", + policy_table_addr); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| upatterntx = 0x%08x| phycntrlinfo1 = 0x%08x" + "| phycntrlinfo2 = 0x%08x| maccntrlinfo1 = 0x%08x|\n", + policy_table_ptr->upatterntx, + policy_table_ptr->phycntrlinfo1, + policy_table_ptr->phycntrlinfo2, + policy_table_ptr->maccntrlinfo1); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| maccntrlinfo2 = 0x%08x| ratecntrlinfo[0] = 0x%08x" + "| ratecntrlinfo[1] = 0x%08x| ratecntrlinfo[2] = 0x%08x|\n", + policy_table_ptr->maccntrlinfo2, + policy_table_ptr->ratecntrlinfo[0], + policy_table_ptr->ratecntrlinfo[1], + policy_table_ptr->ratecntrlinfo[2]); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| ratecntrlinfo[3] = 0x%08x| phycntrlinfo3 = 0x%08x" + "| phycntrlinfo4 = 0x%08x| phycntrlinfo5 = 0x%08x|\n", + policy_table_ptr->ratecntrlinfo[3], + policy_table_ptr->phycntrlinfo3, + policy_table_ptr->phycntrlinfo4, + policy_table_ptr->phycntrlinfo5); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| stationinfo = 0x%08x| ratecntrlinfohe[0] = 0x%08x" + "| ratecntrlinfohe[1]= 0x%08x| ratecntrlinfohe[2] = 0x%08x|\n", + policy_table_ptr->stationinfo, + policy_table_ptr->ratecntrlinfohe[0], + policy_table_ptr->ratecntrlinfohe[1], + policy_table_ptr->ratecntrlinfohe[2]); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| ratecntrlinfohe[3] = 0x%08x| maccntrlinfo3 = 0x%08x" + "| triggercommoninfo = 0x%08x| trigperuserinfo[0] = 0x%08x|\n", + policy_table_ptr->ratecntrlinfohe[3], + policy_table_ptr->maccntrlinfo3, + policy_table_ptr->triggercommoninfo, + policy_table_ptr->triggerperuserinfo[0]); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| trigperuserinfo[1] = 0x%08x| trigperuserinfo[2] = 0x%08x" + "| trigperuserinfo[3]= 0x%08x| trigperuserinfo[4] = 0x%08x|\n", + policy_table_ptr->triggerperuserinfo[1], + policy_table_ptr->triggerperuserinfo[2], + policy_table_ptr->triggerperuserinfo[3], + policy_table_ptr->triggerperuserinfo[4]); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| trigperuserinfo[5] = 0x%08x| trigperuserinfo[6] = 0x%08x" + "| trigperuserinfo[7]= 0x%08x|\n", + policy_table_ptr->triggerperuserinfo[5], + policy_table_ptr->triggerperuserinfo[6], + policy_table_ptr->triggerperuserinfo[7]); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| triginforallocau0u3= 0x%08x| triginforallocau4u7= 0x%08x |\n", + policy_table_ptr->triggerinforuallocationu0u3, + policy_table_ptr->triggerinforuallocationu4u7); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "====================================================" + "====================================================" + "============================\n\n"); +} + +static void cl_dbg_thd_print(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct tx_hd *thd_ptr, u32 thd_addr) +{ + *pos += scnprintf(buf + *pos, bufsz - *pos, + "==============================================" + "= THD 0x%x ========================" + "=======================\n", + thd_addr); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| upatterntx = 0x%08x | nextfrmexseq_ptr = 0x%08x " + "| nextmpdudesc_ptr = 0x%08x | first_pbd_ptr = 0x%08x|\n", + thd_ptr->upatterntx, + thd_ptr->nextfrmexseq_ptr, + thd_ptr->nextmpdudesc_ptr, + thd_ptr->first_pbd_ptr); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| datastartptr = 0x%08x | dataendptr = 0x%08x " + "| frmlen = 0x%08x | spacinginfo = 0x%08x|\n", + thd_ptr->datastartptr, + thd_ptr->dataendptr, + thd_ptr->frmlen, + thd_ptr->spacinginfo); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| phyctrlinfo1 = 0x%08x | policyentryaddr = 0x%08x " + "| macctrlinfo1 = 0x%08x | macctrlinfo2 = 0x%08x|\n", + thd_ptr->phyctrlinfo1, + thd_ptr->policyentryaddr, + thd_ptr->macctrlinfo1, + thd_ptr->macctrlinfo2); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| statinfo = 0x%08x | phyctrlinfo2 = 0x%08x |\n", + thd_ptr->statinfo, + thd_ptr->phyctrlinfo2); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "==============================================" + "==============================================" + "=============================\n\n"); +} + +static void cl_dbg_pbd_print(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct tx_pbd *pbd_ptr, u32 pbd_addr) +{ + *pos += scnprintf(buf + *pos, bufsz - *pos, + "===============================================" + "=== PBD 0x%x =========================" + "========================\n", + pbd_addr); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| upatterntx = 0x%08x | next = 0x%08x| datastartptr = 0x%08x" + "| dataendptr = 0x%08x| bufctrlinfo = 0x%08x|\n", + pbd_ptr->upatterntx, + pbd_ptr->next, + pbd_ptr->datastartptr, + pbd_ptr->dataendptr, + pbd_ptr->bufctrlinfo); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "==============================================" + "==============================================" + "================================\n\n"); +} + +static void cl_dbg_dump_txm_regs(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int stream_idx; + struct dbg_fw_info *fw_info = &dump->common_info.fw_info; + + for (stream_idx = 0; stream_idx < ARRAY_SIZE(fw_info->txlist_info_agg); ++stream_idx) { + struct dbg_txm_regs *txm_regs; + + if (!fw_info->txlist_info_agg[stream_idx].curr_session_idx) + continue; + + txm_regs = &dump->common_info.hw_info.txm_regs[stream_idx]; + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### TXM stream %u Registers\n", stream_idx); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|--------------------------------------------------------------------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| HW state = %3u FW state = %3u SPX state = %3u free buff state = %3u|\n", + txm_regs->hw_state, txm_regs->fw_state, + txm_regs->spx_state, txm_regs->free_buf_state); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| MPDU cnt = %3u LLI cnt = %3u LLI done mpdu num = %3u reason = %3u|\n", + txm_regs->mpdu_cnt, txm_regs->lli_cnt, + txm_regs->lli_done_mpdu_num, txm_regs->lli_done_reason); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| active bytes = 0x%08x prefetch bytes = 0x%08x |\n", + txm_regs->active_bytes, txm_regs->prefetch_bytes); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| last THD: addr = 0x%x MPDU number = %3u underrun cnt = %3u |\n", + txm_regs->last_thd_done_addr, + txm_regs->last_thd_done_mpdu_num, txm_regs->underrun_cnt); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|--------------------------------------------------------------------|\n\n"); + } +} + +static void cl_dbg_dump_machw_regs(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + u8 i = 0, mu_idx; + struct dbg_hw_reg_info *hw_info = &dump->common_info.hw_info; + + const char *hal_machw_reg_str[HAL_MACHW_REG_NUM] = { + [HAL_MACHW_AGGR_STATUS] = "AGGR_STATUS", + [HAL_MACHW_DEBUG_HWSM_1] = "DBG_HWSM_1", + [HAL_MACHW_DEBUG_HWSM_2] = "DBG_HWSM_2", + [HAL_MACHW_DEBUG_HWSM_3] = "DBG_HWSM_3", + [HAL_MACHW_DMA_STATUS_1] = "DMA_STATUS_1", + [HAL_MACHW_DMA_STATUS_2] = "DMA_STATUS_2", + [HAL_MACHW_DMA_STATUS_3] = "DMA_STATUS_3", + [HAL_MACHW_DMA_STATUS_4] = "DMA_STATUS_4", + [HAL_MACHW_RX_HEADER_H_PTR] = "RX_HEADER_HEAD_PTR", + [HAL_MACHW_RX_PAYLOAD_H_PTR] = "RX_PAYLOAD_HEAD_PTR", + [HAL_MACHW_DEBUG_BCN_S_PTR] = "DBG_BCN_STATUS_PTR", + [HAL_MACHW_DEBUG_AC0_S_PTR] = "DBG_AC_0_STATUS_PTR", + [HAL_MACHW_DEBUG_AC1_S_PTR] = "DBG_AC_1_STATUS_PTR", + [HAL_MACHW_DEBUG_AC2_S_PTR] = "DBG_AC_2_STATUS_PTR", + [HAL_MACHW_DEBUG_AC3_S_PTR] = "DBG_AC_3_STATUS_PTR", + [HAL_MACHW_DEBUG_HTP_S_PTR] = "DBG_HTP_STATUS_PTR", + [HAL_MACHW_DEBUG_TX_C_PTR] = "DBG_TX_CURRENT_PTR", + [HAL_MACHW_DEBUG_RX_HDR_C_PTR] = "DBG_RX_HDR_CURRENT_PTR", + [HAL_MACHW_DEBUG_RX_PAY_C_PTR] = "DBG_RX_PAY_CURRENT_PTR", + [HAL_MACHW_MU0_TX_POWER_LEVEL_DELTA_1] = "DBG_MU0_TX_PWR_LEVEL_DELTA_1", + [HAL_MACHW_MU0_TX_POWER_LEVEL_DELTA_2] = "DBG_MU0_TX_PWR_LEVEL_DELTA_2", + [HAL_MACHW_POWER_BW_CALIB_FACTOR] = "DBG_TX_POWER_BW_CALIB_FACTOR", + [HAL_MACHW_TX_POWER_ANTENNA_FACTOR_1_ADDR] = "DBG_tX_POWER_ANT_FACTOR_1", + [HAL_MACHW_TX_POWER_ANTENNA_FACTOR_2_ADDR] = "DBG_TX_POWER_ANT_FACTOR_2" + }; + + *pos += scnprintf(buf + *pos, bufsz - *pos, "\n##### MAC HW regs ####\n"); + + for (i = 0; i < ARRAY_SIZE(hw_info->mac_hw_reg); ++i) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "%30s = 0x%08x\n", + hal_machw_reg_str[i], hw_info->mac_hw_reg[i]); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#########################\n\n"); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "############# MAC HW Secondary FSMs #############\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|---------------------------------------------------------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|MU IDX|%12s|%12s|%12s|%11s|\n", + hal_machw_reg_str[HAL_MACHW_AGGR_STATUS], + hal_machw_reg_str[HAL_MACHW_DEBUG_HWSM_1], + hal_machw_reg_str[HAL_MACHW_DEBUG_HWSM_2], + hal_machw_reg_str[HAL_MACHW_DEBUG_HWSM_3]); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|---------------------------------------------------------|\n"); + + for (i = 0; i < ARRAY_SIZE(hw_info->mac_hw_sec_fsm); ++i) { + mu_idx = CL_MU1_IDX + i; + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| MU %u | 0x%08x | 0x%08x | 0x%08x | 0x%08x|\n", + mu_idx, + hw_info->mac_hw_sec_fsm[i][HAL_MACHW_AGGR_STATUS], + hw_info->mac_hw_sec_fsm[i][HAL_MACHW_DEBUG_HWSM_1], + hw_info->mac_hw_sec_fsm[i][HAL_MACHW_DEBUG_HWSM_2], + hw_info->mac_hw_sec_fsm[i][HAL_MACHW_DEBUG_HWSM_3]); + } + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|---------------------------------------------------------|\n\n"); + + /* Write THD data if valid */ + for (i = HAL_MACHW_DEBUG_BCN_S_PTR; i <= HAL_MACHW_DEBUG_TX_C_PTR; ++i) + if (hw_info->mac_hw_reg[i]) { + u8 thd_idx = i - HAL_MACHW_DEBUG_BCN_S_PTR; + + cl_dbg_thd_print(cl_hw, buf, bufsz, pos, + &dump->machw_thd_info.thd[thd_idx], + hw_info->mac_hw_reg[i]); + } + + cl_dbg_dump_txm_regs(cl_hw, buf, bufsz, pos, dump); +} + +static void cl_dbg_dump_phyhw_regs(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int i = 0; + const char *phy_hw_mpu_reg_str[PHY_HW_DBG_REGS_CNT] = { + [MPU_COMMON_FORMAT] = "MPU_COMMON_FORMAT", + [MPU_COMMON_FIELD_CTRL] = "MPU_COMMON_FIELD_CTRL", + [MPU_COMMON_LEGACY_INFO] = "MPU_COMMON_LEGACY_INFO", + [MPU_COMMON_COMMON_CFG_1] = "MPU_COMMON_COMMON_CFG_1", + [MPU_COMMON_COMMON_CFG_2] = "MPU_COMMON_COMMON_CFG_2", + [MPU_COMMON_COMMON_CFG_3] = "MPU_COMMON_COMMON_CFG_3", + [MPU_COMMON_HE_CFG_1] = "MPU_COMMON_HE_CFG_1", + [MPU_COMMON_HE_CFG_2] = "MPU_COMMON_HE_CFG_2", + [MPU_COMMON_INT_STAT_RAW] = "MPU_COMMON_INT_STAT_RAW", + [RIU_CCAGENSTAT] = "RIU_CCAGENSTAT", + }; + + *pos += scnprintf(buf + *pos, bufsz - *pos, "##### PHY HW regs ####\n"); + + for (i = 0; i < ARRAY_SIZE(dump->common_info.hw_info.phy_mpu_hw_reg); ++i) + *pos += scnprintf(buf + *pos, bufsz - *pos, "%25s = 0x%08x\n", + phy_hw_mpu_reg_str[i], + dump->common_info.hw_info.phy_mpu_hw_reg[i]); + + *pos += scnprintf(buf + *pos, bufsz - *pos, "#########################\n\n"); +} + +static void cl_dbg_dump_ac_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int i = 0; + struct dbg_fw_info *fw_info = &dump->common_info.fw_info; + const char *fw_tx_state_str[CE_TXL_TX_PATH_MAX] = { + [CE_TXL_TX_PATH_IDLE] = "PATH_IDLE", + [CE_TXL_TX_PATH_START] = "PATH_START", + [CE_TXL_TX_PATH_POST_START_DOWNLOAD] = "POST_START_DOWNLOAD", + [CE_TXL_TX_PATH_TX_DATA_DOWNLOADING] = "TX_DATA_DOWNLOADING", + [CE_TXL_TX_PATH_MU_RECOVERY] = "MU_RECOVERY", + [CE_TXL_TX_PATH_LAST_DOWNLOADING] = "LAST_DOWNLOADING", + [CE_TXL_TX_PATH_NEXT_SESSION_PREPARED] = "NEXT_SESSION_PREP", + [CE_TXL_TX_PATH_MU_NEXT_JOB_READY] = "MU_NEXT_JOB_READY", + }; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "\n##### Per AC info ####\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|--------------------------------------------------------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|AC|MU|session|phys queue|check_state| TX path state |\n"); + + for (i = 0; i < ARRAY_SIZE(fw_info->ac_info); ++i) { + u32 mu_idx = (i >= IPC_TX_QUEUE_CNT) ? (i - IPC_TX_QUEUE_CNT + 1) : 0; + u32 session_idx = (fw_info->ac_info[i].active_session != FW_DBG_INVALID_SESSION) ? + fw_info->ac_info[i].active_session : 0; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|--+--+-------+----------+-----------+-------------------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|%2u|%2u|%7u|%10u|%11u|%19s|\n", + i, + mu_idx, + session_idx, + fw_info->ac_info[i].physical_queue_idx, + fw_info->ac_info[i].chk_state, + fw_tx_state_str[fw_info->ac_info[i].tx_path_state]); + } + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|--------------------------------------------------------|\n"); +} + +static void cl_dbg_dump_single_tx_list_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int i = 0; + struct dbg_fw_info *fw_info = &dump->common_info.fw_info; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "\n##### Singles txdesc lists info ####\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|----|---------|-------------|--------------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| AC | pending | downloading | transmitting |\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|----|---------|-------------|--------------|\n"); + + for (i = 0; i < ARRAY_SIZE(fw_info->txlist_info_singles); ++i) { + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|%4u|%9u|%13u|%14u|\n", + i, + fw_info->txlist_info_singles[i].pending_cnt, + fw_info->txlist_info_singles[i].download_cnt, + fw_info->txlist_info_singles[i].transmit_cnt); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|----|---------|-------------|--------------|\n"); + } +} + +static void cl_dbg_dump_agg_tx_list_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int i = 0; + u32 mu_idx; + struct dbg_fw_info *fw_info = &dump->common_info.fw_info; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "\n##### Agg txdesc lists info ####\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|----------------------------------------------------------------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|idx|mu|session|pending|download|transmit|wait4ba|next |next |\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "| | | | | | | |session|pending|\n"); + + for (i = 0; i < ARRAY_SIZE(fw_info->txlist_info_agg); ++i) { + mu_idx = ((i >= AGG_MU1_IDX) && (i <= AGG_MU7_IDX)) ? (i - AGG_MU1_IDX + 1) : 0; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|---+--+-------+-------+--------+--------+--" + "-----+-------+-------|\n"); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|%3u|%2u|%7u|%7u|%8u|%8u|%7u|%7u|%7u|\n", + i, + mu_idx, + fw_info->txlist_info_agg[i].curr_session_idx, + fw_info->txlist_info_agg[i].pending_cnt, + fw_info->txlist_info_agg[i].download_cnt, + fw_info->txlist_info_agg[i].transmit_cnt, + fw_info->txlist_info_agg[i].wait_for_ba_cnt, + fw_info->txlist_info_agg[i].next_session_idx, + fw_info->txlist_info_agg[i].next_pending_cnt); + } + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|----------------------------------------------------------------|\n"); +} + +static void cl_dbg_dump_thd_chains_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump, u8 ac) +{ + int i = 0; + u32 data_offset = 0; + struct dbg_thd_chains_info *chain_info = &dump->thd_chains_info[ac]; + struct dbg_thd_chains_data *chain_data = &dump->thd_chains_data[ac]; + struct tx_hd *hd; + struct tx_policy_tbl *policy_tbl; + struct tx_pbd *pbd; + + while (chain_info->type_array[i] != DBG_CHAINS_INFO_EMPTY) { + switch (chain_info->type_array[i]) { + case DBG_CHAINS_INFO_THD: + hd = (struct tx_hd *)&chain_data->data[data_offset]; + cl_dbg_thd_print(cl_hw, buf, bufsz, pos, hd, + chain_info->elem_address[i]); + data_offset += sizeof(struct tx_hd); + break; + + case DBG_CHAINS_INFO_PT: + policy_tbl = (struct tx_policy_tbl *)&chain_data->data[data_offset]; + cl_dbg_policy_table_print(cl_hw, buf, bufsz, pos, + policy_tbl, + chain_info->elem_address[i]); + data_offset += sizeof(struct tx_policy_tbl); + break; + + case DBG_CHAINS_INFO_PBD: + pbd = (struct tx_pbd *)&chain_data->data[data_offset]; + cl_dbg_pbd_print(cl_hw, buf, bufsz, pos, pbd, + chain_info->elem_address[i]); + data_offset += sizeof(struct tx_pbd); + break; + + default: + return; + } + + i++; + if (i >= DBG_CHAINS_INFO_ELEM_CNT) + break; + } +} + +static void cl_dbg_dump_agg_thd_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump, + u8 ac, u8 mu_idx) +{ + u8 agg_idx = (ac < AGG_MU1_IDX) ? ac : (mu_idx + AGG_MU1_IDX - 1); + u32 addr = dump->common_info.agg_thds_addr[agg_idx].rts_cts_thd_addr; + + if (addr) { + /* RTS CTS THD print */ + *pos += scnprintf(buf + *pos, bufsz - *pos, "\n RTS CTS THD 0x%x\n", addr); + cl_dbg_thd_print(cl_hw, buf, bufsz, pos, + &dump->agg_thd_info[agg_idx].rts_cts_thd, addr); + } + + addr = dump->common_info.agg_thds_addr[agg_idx].athd_addr; + if (addr) { + /* ATHD print */ + *pos += scnprintf(buf + *pos, bufsz - *pos, "\n ATHD 0x%x\n", addr); + cl_dbg_thd_print(cl_hw, buf, bufsz, pos, + &dump->agg_thd_info[agg_idx].athd, addr); + } + + addr = dump->common_info.agg_thds_addr[agg_idx].policy_table_addr; + if (addr) { + /* Policy Table print */ + *pos += scnprintf(buf + *pos, bufsz - *pos, " Policy Table 0x%x\n", addr); + cl_dbg_policy_table_print(cl_hw, buf, bufsz, pos, + &dump->agg_thd_info[agg_idx].policy_table, + addr); + } + + addr = dump->common_info.agg_thds_addr[agg_idx].tf_thd_addr; + if (addr) { + /* TF-THD print */ + *pos += scnprintf(buf + *pos, bufsz - *pos, " TF-THD 0x%x\n", addr); + cl_dbg_thd_print(cl_hw, buf, bufsz, pos, + &dump->agg_thd_info[agg_idx].tf_thd, addr); + } + + cl_dbg_dump_thd_chains_info(cl_hw, buf, bufsz, pos, dump, ac); + + addr = dump->common_info.agg_thds_addr[agg_idx].bar_thd_addr; + if (addr) { + /* BAR THD print */ + *pos += scnprintf(buf + *pos, bufsz - *pos, " BAR THD 0x%x\n", addr); + cl_dbg_thd_print(cl_hw, buf, bufsz, pos, + &dump->agg_thd_info[agg_idx].bar_thd, addr); + } +} + +static void cl_dbg_dump_thd_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump, + u8 ac, u8 mu_idx) +{ + u32 session_idx = dump->common_info.fw_info.ac_info[ac].active_session; + + if (session_idx != FW_DBG_INVALID_SESSION) { + bool is_agg = ((mu_idx > 0) || (session_idx >= IPC_TX_QUEUE_CNT)) ? true : false; + + if (is_agg) + cl_dbg_dump_agg_thd_info(cl_hw, buf, bufsz, pos, dump, ac, mu_idx); + else + cl_dbg_dump_thd_chains_info(cl_hw, buf, bufsz, pos, dump, ac); + } +} + +static void cl_dbg_dump_tx_trace_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int i = 0; + const char *fw_tx_frame_type_str[CL_MAX_FRM_TYPE] = { + [SING_FRM_TYPE] = "MPDU", + [AGG_FRM_TYPE] = "AMPDU", + [AGG_NEXT_IN_TXOP_FRM_TYPE] = "TXOP", + [INT_FRM_TYPE] = "INTERNAL", + [BCN_FRM_TYPE] = "BCN", + [MU_FRM_TYPE] = "MU_AMPDU", + [FRM_TYPE_BASIC_TRIGGER] = "BASIC_TF", + [FRM_TYPE_MU_BAR_TRIGGER] = "MU_BAR", + [BCK_BCN_TYPE] = "BCN_BCK", + [QOS_NULL] = "QOSNULL", + [AGG_TB] = "AGG_TB", + [RTS_TYPE] = "RTS_FW", + [CTS_TYPE] = "CTS_FW", + [TB_SINGLE_FRM_TYPE] = "TB_SMPDU", + [TF_AMPDU_TYPE] = "TF_AMPDU" + }; + + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "\n#### TX Trace ####\n"); + + for (i = 0; i < ARRAY_SIZE(dump->common_info.fw_info.txl_ac_chain_trace); ++i) { + u8 trace_idx = 0, table_idx = 0; + u32 mu_idx; + struct dbg_txl_ac_chain_trace *trace_ptr = + &dump->common_info.fw_info.txl_ac_chain_trace[i]; + struct cl_dbg_txl_chain_info *data; + + if (trace_ptr->next_chain_index == 0) + table_idx = DBG_TXL_FRAME_EXCH_TRACE_DEPTH - 1; + else + table_idx = trace_ptr->next_chain_index - 1; + + data = &trace_ptr->data[table_idx]; + + if (data->count == 0) + continue; + + mu_idx = (i >= IPC_TX_QUEUE_CNT) ? (i - IPC_TX_QUEUE_CNT + 1) : 0; + + *pos += scnprintf(buf + *pos, bufsz - *pos, "\n AC %u MU idx %u:\n", i, mu_idx); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "|========|========|==========|==========|==========" + "|======|==========|==========|=====|=======" + "|======|=========|=======|==========|\n" + "|#PPDU | Type |First THD | Last THD | Prev THD " + "|Req BW| PTalbe |PTalbe_HE |queue|Length " + "|#MPDU |Chosen BW|TX time| txstatus |\n" + "|========|========|==========|==========|==========" + "|======|==========|==========|=====|=======" + "|======|=========|=======|==========|\n"); + + for (trace_idx = 0; trace_idx < DBG_TXL_FRAME_EXCH_TRACE_DEPTH; ++trace_idx) { + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "|%8u|%8s|0x%08x|0x%08x|0x%08x|%6u|0x%08x" + "|0x%08x|%5u|%7u|%6u|%9u|%7u|0x%08x|\n", + data->count, + fw_tx_frame_type_str[data->frm_type], + data->first_thd_ptr, + data->last_thd_ptr, + data->prev_thd_ptr, + data->reqbw, + data->rate_ctrl_info, + data->rate_ctrl_info_he, + data->ce_txq_idx, + data->length, + data->mpdu_count, + data->chbw, + data->tx_time, + data->txstatus); + + if (!table_idx) + table_idx = DBG_TXL_FRAME_EXCH_TRACE_DEPTH - 1; + else + table_idx--; + + data = &trace_ptr->data[table_idx]; + } + + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "|========|========|==========|==========|===" + "=======|======|==========|==========|=====|=" + "======|======|=========|=======|==========|\n"); + + cl_dbg_dump_thd_info(cl_hw, buf, bufsz, pos, dump, i, mu_idx); + } +} + +static void cl_dbg_dump_error_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *trace) +{ + struct dbg_print_ind *ind = &trace->common_info.error_info; + const char *assert_string; + u16 file_id = le16_to_cpu(ind->file_id); + u16 line = le16_to_cpu(ind->line); + u16 has_param = le16_to_cpu(ind->has_param); + u32 param = has_param ? le32_to_cpu(ind->param) : 0; + + if (file_id && line) { + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "ASSERT_TCV%u @ FILE=%hu LINE=%hu param=0x%08X\n", + cl_hw->idx, file_id, line, param); + + /* Get assert string */ + assert_string = cl_dbgfile_get_msg_txt(&cl_hw->dbg_data, file_id, line); + if (!assert_string) + assert_string = "ASSERT STRING NOT FOUND"; + + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "%s\n", assert_string); + } else { + struct dbg_info *dbg_info = (struct dbg_info *)cl_hw->dbginfo.buf; + + *pos += snprintf(buf + *pos, + bufsz - *pos, + "%s\n", dbg_info->u.dump.general_data.error); + } +} + +static void cl_dbg_dump_fw_trace_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_error_trace_info_drv *dump) +{ + int i = 0; + + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "\n### FW trace dump ###\n" + "------------------------------------------------------" + "-----------------------------------\n" + "|idx| String | value 1 | value 2 | value 3 " + "| value 4 | value 5 | value 6 |\n" + "|---+-----------------+----------+----------+---------" + "-+----------+----------+----------|\n"); + + for (i = 0; i < ARRAY_SIZE(dump->common_info.fw_info.fw_trace); ++i) { + u8 dbg_idx = (dump->common_info.fw_info.fw_trace_idx + i) % DBG_FW_TRACE_SIZE; + struct dbg_fw_trace *trace = &dump->common_info.fw_info.fw_trace[dbg_idx]; + char *str = trace->string_ptr ? trace->string_char : "NULL"; + + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "|%3u|%17s|0x%08x|0x%08x|0x%08x|0x%08x|0x%08x|0x%08x|\n", + i, + str, + trace->var_1, + trace->var_2, + trace->var_3, + trace->var_4, + trace->var_5, + trace->var_6); + } + + *pos += scnprintf(buf + *pos, + bufsz - *pos, + "----------------------------------------------------" + "-------------------------------------\n"); +} + +static int cl_dbg_dump_host_descr(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos) +{ + struct new_utsname *nu = init_utsname(); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### KERNEL ####\n" + "release: %s\n" + "version: %s\n" + "machine: %s\n", + nu->release, + nu->version, + nu->machine); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### CPUs ####\n" + "num online : %d\n" + "num possible: %d\n" + "num present : %d\n" + "num active : %d\n", + num_online_cpus(), + num_possible_cpus(), + num_present_cpus(), + num_active_cpus()); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### ENDIANNESS ####\n" + "LE (byte) : %u\n" + "LE (bits) : %u\n" + "BE (byte) : %u\n" + "BE (bits) : %u\n", + cl_are_host_bytes_le(), + cl_are_host_bits_le(), + cl_are_host_bytes_be(), + cl_are_host_bits_be()); + return 0; +} + +static int cl_dbg_dump_chip_descr(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos) +{ + struct cl_version_db *vd = &cl_hw->version_db; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### BASE ####\n" + "chip : %u\n" + "TCV : %u\n" + "bus : %u\n", + cl_hw->chip->idx, + cl_hw->tcv_idx, + cl_hw->chip->bus_type); + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### VERSIONS ####\n" + "drv : %s\n" + "FW : %s\n" + "DSP : 0x%-.8X\n" + "RFIC SW : %u\n" + "RFIC HW : 0x%X\n", + vd->drv, + vd->fw, + vd->dsp, + vd->rfic_sw, + vd->rfic_hw); + /* TODO: AGC info */ + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### STATE ####\n" + "recoveries : %u\n" + "DRV flags : %lu\n" + "TCV-0 en : %u\n" + "TCV-1 en : %u\n", + cl_hw->fw_recovery_cntr, + cl_hw->drv_flags, + cl_chip_is_tcv0_enabled(cl_hw->chip), + cl_chip_is_tcv1_enabled(cl_hw->chip)); + return 0; +} + +static int cl_dbg_dump_ela_descr(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_ela_db *ed = &chip->ela_db; + int ret = 0; + + if (cl_ela_is_on(chip)) { + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### CONF SOURCE ####\n" + "ELA mode: %s #\n", + chip->conf->ce_ela_mode); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### CONF LIFETIME ####\n" + "adaptations : %u #\n" + "applications : %u #\n" + "error state : %d #\n", + ed->stats.adaptations_cnt, + ed->stats.applications_cnt, + ed->error_state); + } else { + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### DISABLED ####\n"); + } + return ret; +} + +static int cl_dbg_dump_raw_lcu_conf(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_ela_db *ed = &chip->ela_db; + int ret = 0; + + if (cl_ela_is_on(chip) && ed->raw_lcu_config) + *pos += scnprintf(buf + *pos, bufsz - *pos, "%s", ed->raw_lcu_config); + else + ret = -ENODATA; + return ret; +} + +static int cl_dbg_dump_adapted_lcu_conf(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_ela_db *ed = &chip->ela_db; + struct cl_lcu_cmd *cmd = NULL, *cmd_tmp = NULL; + int ret = 0; + + if (cl_ela_is_on(chip)) { + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### CONF SOURCE ####\n" + "# %s #\n", + cl_ela_lcu_config_name(chip)); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### CONF COMMANDS ####\n"); + + list_for_each_entry_safe(cmd, cmd_tmp, &ed->cmd_head, cmd_list) + *pos += scnprintf(buf + *pos, bufsz - *pos, + "%s 0x%X 0x%X\n", + cl_ela_lcu_cmd_str(cmd->type), + cmd->offset, + cmd->value); + } else { + ret = -ENODATA; + } + return ret; +} + +static int cl_dbg_dump_la_mem(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + int idx, struct dbg_info *dbg_info) +{ + size_t la_size = 0; + + if (ARRAY_SIZE(dbg_info->u.dump.la_mem) < idx + 1) + return -EINVAL; + + la_size = ARRAY_SIZE(dbg_info->u.dump.la_mem[idx]); + if (la_size > (bufsz - *pos)) + return -ENOBUFS; + + memcpy(buf + *pos, &dbg_info->u.dump.la_mem[idx], la_size); + *pos += la_size; + + return 0; +} + +static int cl_dbg_dump_la_conf(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + int idx, struct dbg_debug_info_tag *gdata) +{ + size_t la_size = 0; + + if (ARRAY_SIZE(gdata->la_conf) < idx + 1) + return -EINVAL; + + la_size = sizeof(gdata->la_conf[idx]); + if (la_size > (bufsz - *pos)) + return -ENOBUFS; + + memcpy(buf + *pos, &gdata->la_conf[idx], la_size); + *pos += la_size; + + return 0; +} + +static int cl_dbg_dump_mac_diags(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_debug_info_tag *gdata) +{ + size_t la_size = ARRAY_SIZE(gdata->diags_mac); + + if (la_size > (bufsz - *pos)) + return -ENOBUFS; + + memcpy(buf + *pos, &gdata->diags_mac, la_size); + *pos += la_size; + + return 0; +} + +static int cl_dbg_dump_hw_diags(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_debug_info_tag *gdata) +{ + *pos += scnprintf(buf + *pos, bufsz - *pos, "%08X\n", gdata->hw_diag); + + return 0; +} + +static int cl_dbg_dump_sw_diags(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_debug_info_tag *gdata) +{ + size_t la_size = min_t(size_t, ARRAY_SIZE(gdata->sw_diag), + gdata->sw_diag_len); + + if (la_size > (bufsz - *pos)) + return -ENOBUFS; + + memcpy(buf + *pos, &gdata->sw_diag, la_size); + *pos += la_size; + + return 0; +} + +static int cl_dbg_dump_chan_info(struct cl_hw *cl_hw, + u8 *buf, int bufsz, int *pos, + struct dbg_debug_info_tag *gdata) +{ + u32 info1 = le32_to_cpu(gdata->chan_info.info1); + u32 info2 = le32_to_cpu(gdata->chan_info.info2); + u8 band = info1 & 0xFF; + u8 type = (info1 >> 8) & 0xFF; + u16 prim20 = (info1 >> 16) & 0xFFFF; + u16 center1 = info2 & 0xFFFF; + + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### FW ####\n" + "band : %u\n" + "type : %u\n" + "prim20_freq : %u.%u MHz\n" + "center1_freq : %u.%u MHz\n", + band, + type, + Q2_TO_FREQ(prim20), Q2_TO_FREQ_FRAC(prim20), + Q2_TO_FREQ(center1), Q2_TO_FREQ_FRAC(center1)); + *pos += scnprintf(buf + *pos, bufsz - *pos, + "#### DRIVER ####\n" + "channel : %u\n" + "bw : %u\n" + "primary_freq : %u MHz\n" + "center_freq : %u MHz\n", + cl_hw->channel, + cl_hw->bw, + cl_hw->primary_freq, + cl_hw->center_freq); + return 0; +} + +/** + * pre_fill_hook - initialize record data in coredump container + * + * Each record presents some section of information. Since, at this stage we + * have no idea about estimated data length, we shift "pos" only for size + * of header information, actual number of written bytes should be calculated + * in the post_fill_hook. + * + * @record: (NLEV) Name-Length-Error-Values record. + * @d: Coredump to fill in. + * @name: Name to set for this specific record; + * @pos: Position of last filled in element in the coredump (equal prev_pos till + * fill in). + * @prev_pos: Position of the previous filled in element in the coredump. + * + * Returns nothing. + */ +static void pre_fill_hook(struct cl_nlev **record, struct cl_coredump *cd, + char *name, int *pos, int *prev_pos) +{ + size_t coredump_space = le32_to_cpu(cd->len) - sizeof(*cd); + size_t free_space = coredump_space - *pos; + + /* Save prev postion for NLEV length calculation in "post" hook */ + *prev_pos = *pos; + + /* Check if there is enough space for NLE (w/o V) */ + if (free_space < sizeof(**record)) + return; + + /* Set pointer of the record to proper buffer place */ + *record = (struct cl_nlev *)(cd->data + *pos); + + /* Fill type info string */ + scnprintf(cd->data + *pos, free_space, "%s", name); + + /* Adjust position as like as new NLEV was added */ + *pos += sizeof(**record); +} + +/** + * post_fill_hook - finalize record data in the coredump container + * + * @record: (NLEV) Name-Length-Error-Values record. + * @err_code: processing error indication, typical errno + * @pos: Position of last filled in element in the coredump. + * @prev_pos: Position of the previous filled in element in the coredump, + * in conjunction with "pos" is used to calculated filled in data and set + * it as "Length" in the NLEV header. + * + * Returns nothing. + */ +static void post_fill_hook(struct cl_nlev **record, int *err_code, int *pos, + int *prev_pos) +{ + /* Finalize what we know about NLEV - size (without headers) + * and processing error codeA + */ + (**record).l = cpu_to_le32(*pos - *prev_pos - sizeof(**record)); + (**record).e = cpu_to_le32(*err_code); + + /* Reset error code for further usage */ + *err_code = 0; +} + +struct cl_coredump *cl_fw_dbg_prepare_coredump(struct cl_hw *cl_hw) +{ + struct dbg_info *dbg_info = (struct dbg_info *)cl_hw->dbginfo.buf; + struct dbg_error_trace_info_drv *fdump = &dbg_info->u.dump.fw_dump; + struct dbg_debug_info_tag *gdata = &dbg_info->u.dump.general_data; + struct cl_coredump *cd; + unsigned char *buf; + /* TODO: Make this size dynamic */ + size_t len = PAGE_SIZE * 100; + size_t data_len = len - sizeof(*cd); + int pos = 0; + int prev_pos = 0; + int e = 0; + struct cl_nlev *rec = NULL; + + buf = vzalloc(len); + if (!buf) + goto out; + + cd = (typeof(cd))buf; + cd->len = cpu_to_le32(len); + cd->self_version = cpu_to_le32((CL_COREDUMP_V1 << 28) + + sizeof(*cd) + sizeof(*rec)); + /* TODO: Mask support */ + cd->dump_mask = cpu_to_le32(0); + cd->trig_tv_sec = cpu_to_le64(cl_hw->dbginfo.trigger_tstamp.tv_sec); + cd->trig_tv_nsec = cpu_to_le64(cl_hw->dbginfo.trigger_tstamp.tv_nsec); + scnprintf(cd->magic, sizeof(cd->magic), "CE_CL8K_DUMP"); + + /* Main section with dynamic dump data filling */ + mutex_lock(&cl_hw->dbginfo.mutex); + + pre_fill_hook(&rec, cd, "chip_descr", &pos, &prev_pos); + e = cl_dbg_dump_chip_descr(cl_hw, cd->data, data_len, &pos); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + pre_fill_hook(&rec, cd, "host_descr", &pos, &prev_pos); + e = cl_dbg_dump_host_descr(cl_hw, cd->data, data_len, &pos); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + pre_fill_hook(&rec, cd, "error", &pos, &prev_pos); + cl_dbg_dump_error_info(cl_hw, cd->data, data_len, &pos, fdump); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Embedded logic analyzer info */ + pre_fill_hook(&rec, cd, "ela_descr", &pos, &prev_pos); + e = cl_dbg_dump_ela_descr(cl_hw, cd->data, data_len, &pos); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + pre_fill_hook(&rec, cd, "raw_lcu_conf", &pos, &prev_pos); + e = cl_dbg_dump_raw_lcu_conf(cl_hw, cd->data, data_len, &pos); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + pre_fill_hook(&rec, cd, "adapted_lcu_conf", &pos, &prev_pos); + e = cl_dbg_dump_adapted_lcu_conf(cl_hw, cd->data, data_len, &pos); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Stringified FW state conents */ + pre_fill_hook(&rec, cd, "fw_dump", &pos, &prev_pos); + cl_dbg_dump_check_params(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_machw_regs(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_phyhw_regs(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_ac_info(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_single_tx_list_info(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_agg_tx_list_info(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_tx_trace_info(cl_hw, cd->data, data_len, &pos, fdump); + cl_dbg_dump_fw_trace_info(cl_hw, cd->data, data_len, &pos, fdump); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + pre_fill_hook(&rec, cd, "hw_diags", &pos, &prev_pos); + e = cl_dbg_dump_hw_diags(cl_hw, cd->data, data_len, &pos, gdata); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* FW/DRV-view of channel and freqs */ + pre_fill_hook(&rec, cd, "chan_info", &pos, &prev_pos); + e = cl_dbg_dump_chan_info(cl_hw, cd->data, data_len, &pos, gdata); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Logic analyzer (0) memory - MAC */ + pre_fill_hook(&rec, cd, "la_mac_trace", &pos, &prev_pos); + e = cl_dbg_dump_la_mem(cl_hw, cd->data, data_len, &pos, LA_MAC_IDX, dbg_info); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Logic analyzer (0) conf - MAC */ + pre_fill_hook(&rec, cd, "la_mac_conf", &pos, &prev_pos); + e = cl_dbg_dump_la_conf(cl_hw, cd->data, data_len, &pos, LA_MAC_IDX, gdata); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Logic analyzer (1) memory - PHY */ + pre_fill_hook(&rec, cd, "la_phy_trace", &pos, &prev_pos); + e = cl_dbg_dump_la_mem(cl_hw, cd->data, data_len, &pos, LA_PHY_IDX, dbg_info); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Logic analyzer (1) conf - PHY */ + pre_fill_hook(&rec, cd, "la_phy_conf", &pos, &prev_pos); + e = cl_dbg_dump_la_conf(cl_hw, cd->data, data_len, &pos, LA_PHY_IDX, gdata); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* Diagnotics port - MAC */ + pre_fill_hook(&rec, cd, "mac_diags", &pos, &prev_pos); + e = cl_dbg_dump_mac_diags(cl_hw, cd->data, data_len, &pos, gdata); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + /* SW diagnostics port */ + pre_fill_hook(&rec, cd, "sw_diags", &pos, &prev_pos); + e = cl_dbg_dump_sw_diags(cl_hw, cd->data, data_len, &pos, gdata); + post_fill_hook(&rec, &e, &pos, &prev_pos); + + mutex_unlock(&cl_hw->dbginfo.mutex); + + /* devcoredump will take care of memory free process */ + return cd; +out: + return NULL; +} + +#define INVALID_AMPDU_CNT U8_MAX + +void cl_fw_dbg_trigger_based_init(struct cl_hw *cl_hw) +{ + memset(&cl_hw->tb_stats, 0, sizeof(cl_hw->tb_stats)); + cl_hw->tb_stats.ampdu_cnt = INVALID_AMPDU_CNT; +} + +void cl_fw_dbg_trigger_based_update(struct cl_hw *cl_hw, struct hw_rxhdr *rxhdr, + struct ieee80211_hdr *hdr) +{ + struct cl_rx_trigger_based_stats *tb_stats = &cl_hw->tb_stats; + + if (!tb_stats->enable) + return; + + if (tb_stats->ampdu_cnt == INVALID_AMPDU_CNT) { + tb_stats->ampdu_cnt = rxhdr->ampdu_cnt; + if (rxhdr->format_mod == FORMATMOD_HE_TRIG) { + if (ieee80211_is_qos_nullfunc(hdr->frame_control)) + tb_stats->qos_null_per_agg += rxhdr->frm_successful_rx; + else + tb_stats->data_per_agg += rxhdr->frm_successful_rx; + + tb_stats->total += rxhdr->frm_successful_rx; + } + } else if (tb_stats->ampdu_cnt == rxhdr->ampdu_cnt) { + if (rxhdr->format_mod == FORMATMOD_HE_TRIG) { + if (ieee80211_is_qos_nullfunc(hdr->frame_control)) + tb_stats->qos_null_per_agg += rxhdr->frm_successful_rx; + else + tb_stats->data_per_agg += rxhdr->frm_successful_rx; + + tb_stats->total += rxhdr->frm_successful_rx; + } + } else { + tb_stats->ampdu_cnt = rxhdr->ampdu_cnt; + if (unlikely(tb_stats->data_per_agg >= DBG_STATS_MAX_AGG_SIZE)) + cl_dbg_err(cl_hw, "rx trigger_based agg size %u > 256\n", + tb_stats->data_per_agg); + else + tb_stats->data[tb_stats->data_per_agg]++; + + if (unlikely(tb_stats->qos_null_per_agg > TID_MAX)) + tb_stats->qos_null[TID_MAX + 1]++; + else + tb_stats->qos_null[tb_stats->qos_null_per_agg]++; + + tb_stats->data_per_agg = 0; + tb_stats->qos_null_per_agg = 0; + + if (rxhdr->format_mod == FORMATMOD_HE_TRIG) { + if (ieee80211_is_qos_nullfunc(hdr->frame_control)) + tb_stats->qos_null_per_agg += rxhdr->frm_successful_rx; + else + tb_stats->data_per_agg += rxhdr->frm_successful_rx; + + tb_stats->total += rxhdr->frm_successful_rx; + } + } +} + +void cl_fw_dbg_trigger_based_reset(struct cl_hw *cl_hw) +{ + u32 idx; + struct cl_rx_trigger_based_stats *tb_stats = &cl_hw->tb_stats; + + tb_stats->total = 0; + + for (idx = 0; idx < ARRAY_SIZE(tb_stats->data); idx++) + tb_stats->data[idx] = 0; + + for (idx = 0; idx < ARRAY_SIZE(tb_stats->qos_null); idx++) + tb_stats->qos_null[idx] = 0; +} From patchwork Thu Jun 17 15:59:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B38C8C49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 087/256] cl8k: add fw/fw_dbg.h Date: Thu, 17 Jun 2021 15:59:34 +0000 Message-Id: <20210617160223.160998-88-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:09 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c988c501-bf57-40ae-e0a3-08d931a98ad8 X-MS-TrafficTypeDiagnostic: AM9P192MB0871: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 31o+unXnlMMzfS0teQfA53y0Xk5Knd3C8Cv5jE0O1J4PcQrmJj0wXFhFuLmAZNsDQ8KD5Ld6pq2+KPR49d1Eogk0mjDMiPzryH/85d8ZJx2jICvEwzSgJYnp8RlhBTOWbDVYlbLWRnbmz4PshGHLUNDqzDbwr3T+fqY9UDlm/iQ86QVtuxFIuGg3XKdZ1qaLbKxSHnOjh/0Ugpe86snBn2jZZAd4e9orb8f5f+HBITO1WhzJWrDacFXi3d2qWiIs23rN9gfNbPq5QiFaOUla62a8U/bN/xGDxciwlIoS4P/zIyQnpZM7RRHov1ZD9N7Vp+hK2qIOvSRbuVzvP97V0iED8vqaoQw+/otBmGl9RJd2e/BzoJr46U6Kc5aHk6jkYEHJm8R7CmjZmISPVgCeOaXZQs3sqUAbunuUOp/uEUmsM2FKrhj/trGbSd55MMFpjp5cuO9/1beNdcu+cdfIDvhmlbqcuckAb6xbHlUC7v0OWvCLc7Y+naDIWO8khT0YnpapaQX5TCIAGzKFkba1SRK2oYqR/ePBU0SIuGOokzCL/EvSvVisRAYSYbOUN48bD4jzeXxITLgX6uHOP6Mv5KnGsY0GmZqx22ativZl65nyVq93ubbV38NXmoR1TGFw6/uPKebyyeW3qvPorw8/Gy7TjtC/4a2rDLRXyylPVKuFi05hpE1ULJOhb6/9EHal/unVm+A6KD0xcyKrlQZXZg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(136003)(366004)(376002)(346002)(396003)(39840400004)(16526019)(66946007)(478600001)(26005)(66476007)(6486002)(186003)(66556008)(9686003)(316002)(86362001)(6506007)(6666004)(6512007)(55236004)(38350700002)(1076003)(38100700002)(4326008)(8676002)(83380400001)(5660300002)(52116002)(2616005)(2906002)(6916009)(956004)(8936002)(107886003)(54906003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: joM43wIgfBIoc0T+Q//oVbBf8U96Za+r/do3i76KPLmL5fGMP6LvF6fJBQaViKeut10Iwi+IM5NPU81zcZyS2ZdGVF6JYzwUNnIPdjHl+KgQCJY5K1SQGlCT4t6wQkfsbUe3iNee9RlZhiupvnOuacuEOSuCsFJ/oPpI86Thd8SjYlZvV5dP855z9EDPeVoe6RN8xjO1wgsufoIArYNGiz7ZvSUSXAUuPofiyCJdWVvc3aaKhP8SHxEye+8xlIDMe+f+g+sxQ/BiyUS6Hk2i8gMHUfV54oJPClSR2sFjbE4e3QrjxrNe2+fmWPB+Yz335Nb7m0EBHiZhBQe2268lbLCvVL2fhi3XHequLi9fKkVq10SC8Pu10Nrq8P34AkcOOdVH34eGx0RpachEQLVizRpST7VONpkWgHuijI8igV8DveDwTfmCe+nJJ1HK31PT5jUa9sFBQm90cb9xSDDSh8/gVhlJdVt3Bziemc3U1VAP9lDfpUXS3iM9Mb34RLgO/VENren/KttfT3Ml12Ckfhvq6FnZIgUbfKVT0KyobSMbcxoUAycbpveC1Qi+fVbrcLrzCPMr9urUyBfkH10EgvxC/HRFj4F2XCjf8zHGmvAdqyuvVVhg11/xmK8fJDGOStSSg46aE1VsV07qsee9lmuZ0huOZkO27NXK8UlLlcQb5QIu90VZ7u7FEBfF3VWGlA7aLgxxFHfK94wbwmB/LhT60Pj2zBmaYrIdVSfffL7Y7ua0UTuxqmNAzAVwM93zPoNSvaDw2gSb91M7mDXTih8uyKVtk0tmszgHQI6sVcB3txq2iL0mwSYP+4hREp3JZDV5fLO89w5ODtmqrrqGvNtpBFJA5EQzUnS13aVpB8XzouyCfyeg/eyOah/kdXzxG9z4morqDfE8k6/TqumiMTn5coCBwdikSFASTUpqoZ9UC9UydemgbBwF2wr+PmhXrg5+m2s77/GZsDBs6Jn398D48BCDCUZlEBVs7t8/SVnpOc9ped3BgyKsr9nzEWaIITPptPo+44LA2IpRaRvsafNMrkKnK8H/Wta/8XR/mXysh1fH2jH8GJfRyUzCssbMWQWfCMon7WbNWvkTt7DWeaicpwdrphaYrPzm2WO2fHcxsPCkIuch56yo2L6Q5B7VlDW2jomSsuoa9PVTOugu2QWFsK4kB3YS9DKD5zV0AH3hPCdiMDLzADlDkjo7d7W7tQWzEYP2qOV4ma0Kl6YcszuAUMQsEAW3HhMRUBJbwgRSDxYU2r+tj2jXwDwPtL000qnZP3nq5mxcfgZJEQ2+RuFyCZYgJ0WFWKC04B4ZNoxvycUurcfswfVPO+zvyqkv X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: c988c501-bf57-40ae-e0a3-08d931a98ad8 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:09.9653 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4pQ/4fWxeq1Roq/V2vep42yEQ9f/gz1FyNwEnnsgNb5meL/7tbby4jzYJBzWRCcKEpJRoYDbi9PqT1uOk8v/6g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0871 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/fw_dbg.h | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/fw_dbg.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/fw_dbg.h b/drivers/net/wireless/celeno/cl8k/fw/fw_dbg.h new file mode 100644 index 000000000000..a35b63fece63 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/fw_dbg.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_FW_DBG_H +#define CL_FW_DBG_H + +#include "hw.h" + +enum { + DBG_INFO_DUMP = 1, + DBG_INFO_TX_STATS, + DBG_INFO_BCN_STATS, + DBG_INFO_RX_STATS, + DBG_INFO_DYN_CAL_STATS, + DBG_INFO_RATE_FALLBACK_STATS, + DBG_INFO_BF, + DBG_INFO_TRIGGER_FLOW, + DBG_INFO_MAX, + DBG_INFO_UNSET = DBG_INFO_MAX +}; + +void cl_fw_dbg_handler(struct cl_hw *cl_hw); +int cl_fw_dbg_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); +void cl_fw_dbg_trigger_based_init(struct cl_hw *cl_hw); +void cl_fw_dbg_trigger_based_update(struct cl_hw *cl_hw, struct hw_rxhdr *rxhdr, + struct ieee80211_hdr *hdr); +void cl_fw_dbg_trigger_based_reset(struct cl_hw *cl_hw); +struct cl_coredump *cl_fw_dbg_prepare_coredump(struct cl_hw *cl_hw); + +#endif /* CL_FW_DBG_H */ From patchwork Thu Jun 17 15:59:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D22CC2B9F4 for ; Thu, 17 Jun 2021 16:06:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F40F60FDB for ; Thu, 17 Jun 2021 16:06:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231389AbhFQQI7 (ORCPT ); Thu, 17 Jun 2021 12:08:59 -0400 Received: from mail-db8eur05on2082.outbound.protection.outlook.com ([40.107.20.82]:7360 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233607AbhFQQIB (ORCPT ); Thu, 17 Jun 2021 12:08:01 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lByKSEzocAjV8L0TLbTvJyOpDqkVePrkRqEgXq5AFRDeWdJbfXPkeVrluphadqxyGIOQooNk2GLq/fCTP59cYdo51akbQGv0L/RRhPipiqEuSdzUMSGVJNjToXeKf6RlfqsmNGU0rWNZAEalX/nMKStX2WKr5Tt1bOn9AQ/PFGb86/PItJbIHTTEQs8q4amBrJI4RAqGODyRNJitTi9I9Qup1SO/cu4g1jKVdIEyS9EyOt5xxTB/OWAweO4HDB/xeO9Bb2JAUk6rb1ivIi8SHifpxXFvvVo6vOO81NQygYRcZExz9PIPj9E4rXrYmUistz+R2Y5rbg9gGjXLD7rtmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IpCijZ28gADPwHG3G7BXjmNM+GD3YYnARVLWvgW6GgU=; b=Vfns1hZJ8Ht3IwtgCHJWKDkOwcnr04s4Z1o+tGozPyN2WNIc6q47OUhDHlFlu6ozpeNgNK7AVWgP361bS/KEVI3ojwzsSrpkH3LooBpA7MwWHdM3eYQ2Ofof+BEUFq6riPAAxQkkicTtVx9swbEtNwuy5sLGi40KMi17Nx5nRGabPWM4iOPZfrSZexNktN+kFdMidbtE69hIzYRI1z3ICt50XSq/TrUbB3LgaopfvfJS82l5OOG7tl7QemK49Lt+kx08zV4Eds9Zs4FjRjLaf+1H9+CYRIpHW0yj3KzreCM0HOHs7/CiLozOtA2Y42IUXF/xaamTAV07ZAztsYVTdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IpCijZ28gADPwHG3G7BXjmNM+GD3YYnARVLWvgW6GgU=; b=RsS/75S1VkmgGDdOPfJvOf8iz/VGKZ+tLwVkBNSS67xdUa1MiT1sZAoxtv5aqJuNnQZi38CwfgC739bG2z+lLymNDHuewC4mT54Cjqtd2sxws7N9o91yr5YxTIH7DPxQD6rKBYpMb+3dVeN8K8z+0RUlsnPWRke6Hyuo0Jz1CwA= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0871.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fb::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.21; Thu, 17 Jun 2021 16:04:29 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:04:29 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/fw_file.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/fw_file.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/fw_file.h b/drivers/net/wireless/celeno/cl8k/fw/fw_file.h new file mode 100644 index 000000000000..a9a861a615a1 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/fw_file.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_FW_FILE_H +#define CL_FW_FILE_H + +#include "hw.h" + +int cl_fw_file_load(struct cl_hw *cl_hw); +void cl_fw_file_cleanup(struct cl_hw *cl_hw); +void cl_fw_file_release(struct cl_hw *cl_hw); + +#endif /* CL_FW_FILE_H */ From patchwork Thu Jun 17 15:59:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7007C49361 for ; Thu, 17 Jun 2021 16:05:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9F9F613E1 for ; Thu, 17 Jun 2021 16:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232419AbhFQQHj (ORCPT ); Thu, 17 Jun 2021 12:07:39 -0400 Received: from mail-eopbgr80045.outbound.protection.outlook.com ([40.107.8.45]:44002 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231877AbhFQQHO (ORCPT ); Thu, 17 Jun 2021 12:07:14 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A49NijcjGZhIpQ044Zuk1L3Dvtog79usnZGxUUm5IkaBjc0QOrLrUCeaZiq4MJf4g/2wUOdTPYJyrSEkBLzdw2pdUG/47wyp9PEuog95i2sGgUMFNvGTMKoFXjyCdi/+1f7gOES4qOYySOAkVSTuA1w4fmJDs3SCGkL67gmsRQ6/0n3MwUYR+GAGFfjpLjQQLjOFutYzGS8Usa3B00U5nII7cvnoYUManFdK6ax3VtKpK4Fpi7tQpasitzGif7NEeFFPzyJaWB+K1Ow94ciHIRCdpIwTyuSKyjRPwOpNR1f10uveavz1bk7AIMBzwo0xQyMwUrnBjpAfM2cyMNXIaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=E0/MfBa4fi/a0mfwach0iLt6iWcZUZYTXh+mnovlmbA=; b=CX5HLB/S4sb+Xvjq8Q2kPSF7j6nDorQKxUSVoFMELMYl8VrxUJUtnlANmPKTN7CRphUySinKXJS5ePs194cPm0hSa+pWlOJHi5Ow1m45eU44GPzPbexCE5DAB862jtEFBLlXB40FmtYxObdhTSzKVzzw3Ymg5RWFCR5q8UAC3vWpXDMNXJP370g5hrbRYlhezX9bJydHHcUxu4t+W5gVEcurSHk1aqQateimO42icysFdxhNJEJi3pGlOteORWl5namsZSGFmWJEfpPqJoObdtWBG7o+Np7/IVr//75nrMj3YkBhM3OGQqFc8XH3kG2FUQEHULcBpwl3WO8lQgvKCg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=E0/MfBa4fi/a0mfwach0iLt6iWcZUZYTXh+mnovlmbA=; b=iKIRyaKN8AGY+2EqK05KC7JB6LbU5aRtyFVUXaELl1VCdOgI9vK37ZvxIz0bu8zpQVea/Uf7zmTRI4k4couEmIeV1GUMXTODIxMYOOcUO8I+BOQ1/ngHi/9XfL/jROf8cUj3gdyWqQAJ8LbTbf0qujZRymZf1WsS32XLCXQMBfg= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0887.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1f8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:00 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:00 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 092/256] cl8k: add fw/msg_cfm.c Date: Thu, 17 Jun 2021 15:59:39 +0000 Message-Id: <20210617160223.160998-93-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:14 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff93d86e-9b38-4fc0-b505-08d931a98e19 X-MS-TrafficTypeDiagnostic: AM9P192MB0887: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JStIhaW3iWTxKMmw2Vx/PDfb/4689W2v9fEpujWHQrP1/2pIaMCpnWo9cAd3t2FxmBoWE175lCuUJGIVOiVcuGechYEWCdMGYXZnK2bFzeH6aEFRIGIqlJ5xtvfNpb1APwjsIVTFMHwaKUbQjCdGXBqGcdeWW5u5OzCtKqS9EGI6H2OfZyENV0Q+MbSaZtglpFbxAQRHL6uRWxvqbgkFS/um6wq8a6pYH8Ge37r5mzRPVfuzRtTl/WLifqU1mex54YpDeFj5QfEwMYcnmMC2ksks1a33hRxUjPI2sgrEzkKQLR2rG24QzyVgdPB7CpnQ5MzMRk4LQyejsojyTRE+Bycl3qI9uN176VjtDgZCUBjey9V+gT4OeHv5Dgv61qhyQy7B6BowFNvUuvO+GdfKb8K9L687bXhEl7UWx8e3k5u12fkUCHzhxgyE5QLFc/GFtM8Q05ett5fU8nZ/Q1iNjmhSzyT/qWvDGMKqo9WietvPmduoUJxukmOvS23k2LIwwz2Z7VsOY3Vxi3OOTFzhJmoCkDIURH3pxF2g84tRq/Gthh7Q1Ly2AEhGPCPDrofFv9oqWEQeT5DAqNCxfFaj5Ysmc225ig3Dvgego4s+9WTMLE5SvnmcjjgN7bT/I59dEBXC8ztpxlrJf1SwRZNbRs3SFwnm8NCTEesYAHsy8HZEPx4cw8i3hA7JkTsnoz0LgvGguNgyKXD4hJpRsc7xoQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(396003)(366004)(39850400004)(136003)(346002)(83380400001)(6666004)(38350700002)(4326008)(186003)(16526019)(5660300002)(54906003)(6506007)(26005)(55236004)(38100700002)(316002)(1076003)(107886003)(30864003)(52116002)(8936002)(508600001)(66476007)(66946007)(66556008)(36756003)(6916009)(6486002)(86362001)(2616005)(956004)(2906002)(8676002)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wObvT5nW2Sr8hpg9gc1A8NjzfkCBKJbPpnCN3DI+cvVvlYTR/jIzLtYbBFQMk3uMM+DoqHyJ33ZU5zoz4VDrokGXunZgPWuNBmPmzfXJm20puPutWxRi4td8JVAgRangAhDmXjHmC5VESdCrooqShYP7bivpGTvAzBYEdikxLOqECeONMlweY6nwvEwjJ/LEDKZrEmC4JZZaW9R9ZrNLT1yOklrCCJ6665kn9IRcg14/3AvXAmBztyCNKP1ivahURozP3OszeLvDGyLdrlGyHoOWKV85ApozyysUnN2OQmMxCM/obiiE3b0HImKiNTCGPcCmrpopXCzwoXUVV0fZ9obUv8LSlGUksyFfQKJdux4BK9moJOYUShJb1LFdNDDEhh2uB/6dcyTDWmFLiip6M5cmJ7d2MGgkVN7S62+2qu9QCdwBJQ1wIVDSyzLTl6BauW6YAhn2Rh9U/fe+qJzEPXTginV5uhc3msGBReb9/4wKlcEGSGd0YJHmh2D0EPlydrGaxdVg8TsQ2l589awktNNMcqeIrs0iTQ3QfQCFhz5maad4z0azwkSrDe5X+DePeLVhXs1Sa8nQMX/yY15haeXC/13EjgCmF/7IrnaYryIoLMsz5God6gC8rze4pZzfGR2+n/pf2A/9VlMfsopNGznw3iVQW78LWoI3dGWomDyq7VhneZ+vt+Kt2m6tZ1kmMd5nMsTwFc6/em75BxPpff2JjsaTtMkGfTQiyQqRqXawE7XMiMrpIizpDsjlN3OmZMukLpn3r86pYHhMeyumcTtlw3pEG5Yq1wK99ztUU8FmYKvp1tT5VPv2SEeVlQwG19RvqCfITTuIRCHtBqwClXqOv8+ALCEeOmpG00mtBMoytnIvlPgnl81pIgKKrvo3TadTOBIPf3dFNnAqdoJUDwWUaJnwVl8/DOtpY93Gl2KT8UOGREsoZ2Wa7QXTEycKSTWrgP5GFxjvQhGw7Tug+XCt/eWZe/dpzm/LSMhBYHt5SHnpPJDCaxR/NbvOe/C1YrBaPGm6RjKl2gIzG+TqDJjHGdnhtLdv1/6UCNCYUpfsoxSADf63AE0p3/xxl8zhr0ux9sfP2P7qt6fWtIfzJ/CI1ftdRmWdRJ4xGFC5yJ0pp+TiFJR1UMVL2MmPWeXAp3Ecb5/tYSLKoAbHfS3j8nAkptIUkT6lKDaYDydHhK4asQDqd3vKEkVXUzdKcmPND6j4fVkY8iZUEShz1ZxeIl/mYOaFCBn6ZbJDyMC4IMZ65R6RxmGDH1N7HIFW09W94D/BJC0R6r+RbwS/0M0r2BfblRxrRv/9NtCsLX9y9ha2tHTe1jJriAAx0LTQGSEA X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ff93d86e-9b38-4fc0-b505-08d931a98e19 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:15.4721 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Grvn952/+6RSkge5zKzLOodbnOTim6nSw/7yjgfmdGpNLWZULHh0Htx9utAzd9/vySIFL2ZFOqah/yqNJ8MEXw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0887 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/msg_cfm.c | 316 ++++++++++++++++++ 1 file changed, 316 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/msg_cfm.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/msg_cfm.c b/drivers/net/wireless/celeno/cl8k/fw/msg_cfm.c new file mode 100644 index 000000000000..a63751d0804e --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/msg_cfm.c @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "fw/msg_cfm.h" +#include "fw/msg_rx.h" +#include "recovery.h" +#include "reg/reg_ipc.h" +#include "chip.h" +#include "hw_assert.h" +#include "config.h" +#include "coredump.h" + +static void cl_check_exception(struct cl_hw *cl_hw) +{ + /* Check if Tensilica exception occurred */ + int i; + struct cl_ipc_exception_struct *data = + (struct cl_ipc_exception_struct *)cl_hw->ipc_env->shared; + + if (data->pattern != IPC_EXCEPTION_PATTERN) + return; + + cl_dbg_err(cl_hw, "######################### firmware tensilica exception:\n"); + cl_dbg_err(cl_hw, "................................. type: "); + + switch (data->type) { + case 0: + cl_dbg_err(cl_hw, "EXCEPTION_ILLEGALINSTRUCTION\n"); + break; + case 2: + cl_dbg_err(cl_hw, "EXCEPTION_INSTRUCTIONFETCHERROR\n"); + break; + case 3: + cl_dbg_err(cl_hw, "EXCEPTION_LOADSTOREERROR\n"); + break; + case 6: + cl_dbg_err(cl_hw, "EXCEPTION_INTEGERDIVIDEBYZERO\n"); + break; + case 7: + cl_dbg_err(cl_hw, "EXCEPTION_SPECULATION\n"); + break; + case 8: + cl_dbg_err(cl_hw, "EXCEPTION_PRIVILEGED\n"); + break; + case 9: + cl_dbg_err(cl_hw, "EXCEPTION_UNALIGNED\n"); + break; + case 16: + cl_dbg_err(cl_hw, "EXCEPTION_INSTTLBMISS\n"); + break; + case 17: + cl_dbg_err(cl_hw, "EXCEPTION_INSTTLBMULTIHIT\n"); + break; + case 18: + cl_dbg_err(cl_hw, "EXCEPTION_INSTFETCHPRIVILEGE\n"); + break; + case 20: + cl_dbg_err(cl_hw, "EXCEPTION_INSTFETCHPROHIBITED\n"); + break; + case 24: + cl_dbg_err(cl_hw, "EXCEPTION_LOADSTORETLBMISS\n"); + break; + case 25: + cl_dbg_err(cl_hw, "EXCEPTION_LOADSTORETLBMULTIHIT\n"); + break; + case 26: + cl_dbg_err(cl_hw, "EXCEPTION_LOADSTOREPRIVILEGE\n"); + break; + case 28: + cl_dbg_err(cl_hw, "EXCEPTION_LOADPROHIBITED\n"); + break; + default: + cl_dbg_err(cl_hw, "unknown\n"); + break; + } + + cl_dbg_err(cl_hw, "................................. EPC: %08X\n", data->epc); + cl_dbg_err(cl_hw, "................................. EXCSAVE: %08X\n", data->excsave); + cl_dbg_err(cl_hw, "..........................BACKTRACE-PC.........................\n"); + + for (i = 0; i < IPC_BACKTRACT_DEPTH; i++) + cl_dbg_err(cl_hw, "PC#%d: 0x%08X\n", i, data->backtrace.pc[i]); +} + +static u16 cl_msg_cfm_clear_bit(u16 cfm) +{ + if (cfm < MM_REQ_CFM_MAX) + return ((cfm - 1) >> 1); + + return ((cfm - 1 - FIRST_MSG(TASK_DBG) + MM_REQ_CFM_MAX) >> 1); +} + +u16 cl_msg_cfm_set_bit(u16 req) +{ + if (req < MM_REQ_CFM_MAX) + return (req >> 1); + + return ((req - FIRST_MSG(TASK_DBG) + MM_REQ_CFM_MAX) >> 1); +} + +int cl_msg_cfm_wait(struct cl_hw *cl_hw, u16 bit, u16 req_id) +{ + /* + * Start a timeout to stop on the main waiting queue, + * and then check the result. + */ + struct cl_chip *chip = cl_hw->chip; + int timeout = 0, error = 0; + int max_timeout = 0; + + if (!cl_hw->msg_calib_timeout) + max_timeout = CL_MSG_CFM_TIMEOUT_JIFFIES; + else + max_timeout = CL_MSG_CFM_TIMEOUT_CALIB_JIFFIES; + + /* Wait for confirmation message */ + timeout = wait_event_timeout(cl_hw->wait_queue, + !CFM_TEST_BIT(bit, &cl_hw->cfm_flags), + max_timeout); + + if (timeout == 0) { + /* + * Timeout occurred! + * Make sure that confirmation wasn't received after the timeout. + */ + if (CFM_TEST_BIT(bit, &cl_hw->cfm_flags)) { + cl_dbg_verbose(cl_hw, "[WARN] Timeout occurred - %s\n", + MSG_ID_STR(req_id)); + error = -ETIMEDOUT; + } + } + + if (error) { + struct cl_irq_stats *irq_stats = &chip->irq_stats; + unsigned long now = jiffies, flags; + u32 status, raw_status; + + /* + * The interrupt was not handled in time, lets try to handle it safely. + * The spin lock protects us from the following race scenarios: + * 1) atomic read of the IPC status register, + * 2) execution on the msg handler twice from different context. + * 3) disable context switch from the same core. + */ + spin_lock_irqsave(&chip->isr_lock, flags); + + status = ipc_xmac_2_host_status_get(chip); + raw_status = ipc_xmac_2_host_raw_status_get(chip); + + cl_dbg_verbose(cl_hw, + "[INFO] status=0x%x, raw_status=0x%x, last_isr_statuses=0x%x, " + "last_rx=%ums, last_tx=%ums, last_isr=%ums\n", + status, + raw_status, + irq_stats->last_isr_statuses, + jiffies_to_msecs(now - irq_stats->last_rx), + jiffies_to_msecs(now - irq_stats->last_tx), + jiffies_to_msecs(now - irq_stats->last_isr)); + + if (status & cl_hw->ipc_e2a_irq.msg) { + /* + * WORKAROUND #1: In some cases the kernel is losing sync with the + * interrupt handler and the reason is still unknown. + * It seems that disabling master interrupt for a couple of cycles and + * then re-enabling it restores the sync with the cl interrupt handler. + */ + ipc_host_global_int_en_set(chip, 0); + + /* Acknowledge the MSG interrupt */ + ipc_xmac_2_host_ack_set(cl_hw->chip, cl_hw->ipc_e2a_irq.msg); + + /* + * Unlock before calling cl_msg_rx_tasklet() because + * spin_unlock_irqrestore() disables interrupts, but in + * cl_msg_rx_tasklet() there might be several places that + * use spin_unlock_bh() which enables soft-irqs. + */ + spin_unlock_irqrestore(&chip->isr_lock, flags); + + /* + * Call the tasklet handler (it also gives the CPU that + * is mapped to the cl_interrupt few cycle to recover) + */ + cl_msg_rx_tasklet((unsigned long)cl_hw); + + /* Re-enable master interrupts */ + ipc_host_global_int_en_set(chip, 1); + } else { + /* + * WORKAROUND #2: Try to call the handler unconditioanly. + * Maybe we cleared the "cl_hw->ipc_e2a_irq.msg" without handling it. + */ + + /* + * Unlock before calling cl_msg_rx_tasklet() because + * spin_unlock_irqrestore() disables interrupts, but in + * cl_msg_rx_tasklet() there might be several places + * that use spin_unlock_bh() which enables soft-irqs. + */ + spin_unlock_irqrestore(&chip->isr_lock, flags); + + /* Call the tasklet handler */ + cl_msg_rx_tasklet((unsigned long)cl_hw); + } + + /* Did the workarounds work? */ + if (CFM_TEST_BIT(bit, &cl_hw->cfm_flags)) { + cl_dbg_verbose(cl_hw, "[ERR] Failed to recover from timeout\n"); + } else { + cl_dbg_verbose(cl_hw, "[INFO] Managed to recover from timeout\n"); + error = 0; + goto exit; + } + + /* Failed handling the message */ + CFM_CLEAR_BIT(bit, &cl_hw->cfm_flags); + + cl_check_exception(cl_hw); + + cl_hw_assert_check(cl_hw); + + if (!strcmp(chip->conf->ce_ela_mode, "XTDEBUG") || + !strcmp(chip->conf->ce_ela_mode, "XTDEBUG_STD")) { + /* + * TODO: Special debug hack: collect debug info & skip restart + * "wait4cfm" string is expected by debug functionality + */ + goto exit; + } + + if (!test_bit(CL_DEV_HW_RESTART, &cl_hw->drv_flags) && + !test_bit(CL_DEV_SW_RESTART, &cl_hw->drv_flags) && + test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) && + !cl_hw->is_stop_context) { + /* Unlock msg mutex before restarting */ + mutex_unlock(&cl_hw->msg_tx_mutex); + + if (cl_coredump_is_scheduled(cl_hw)) + set_bit(CL_DEV_FW_ERROR, &cl_hw->drv_flags); + else + cl_recovery_start(cl_hw, RECOVERY_WAIT4CFM); + + return error; + } + } + +exit: + /* Unlock msg mutex */ + mutex_unlock(&cl_hw->msg_tx_mutex); + + return error; +} + +static void cl_msg_cfm_assign_params(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg) +{ + u32 *param; + u16 msg_id = le16_to_cpu(msg->id); + u16 msg_len = le16_to_cpu(msg->param_len); + + /* A message sent in background is not allowed to assign confirmation parameters */ + if (cl_hw->msg_background) { + cl_dbg_verbose(cl_hw, + "Background message can't assign confirmation parameters (%s)\n", + MSG_ID_STR(msg_id)); + return; + } + + if (msg->param_len) { + param = kzalloc(msg_len, GFP_ATOMIC); + if (param) { + memcpy(param, msg->param, msg_len); + if (cl_hw->msg_cfm_params[msg_id]) + cl_dbg_err(cl_hw, "msg_cfm_params is not NULL for %s\n", + MSG_ID_STR(msg_id)); + cl_hw->msg_cfm_params[msg_id] = param; + } else { + cl_dbg_err(cl_hw, "param allocation failed\n"); + } + } else { + u16 dummy_dest_id = le16_to_cpu(msg->dummy_dest_id); + u16 dummy_src_id = le16_to_cpu(msg->dummy_src_id); + + cl_dbg_err(cl_hw, "msg->param_len is 0 [%u,%u,%u]\n", + msg_id, dummy_dest_id, dummy_src_id); + } +} + +void cl_msg_cfm_assign_and_clear(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg) +{ + u16 bit = cl_msg_cfm_clear_bit(msg->id); + + if (CFM_TEST_BIT(bit, &cl_hw->cfm_flags)) { + cl_msg_cfm_assign_params(cl_hw, msg); + CFM_CLEAR_BIT(bit, &cl_hw->cfm_flags); + } else { + cl_dbg_verbose(cl_hw, "Msg ID not set in cfm_flags (%s)\n", MSG_ID_STR(msg->id)); + } +} + +void cl_msg_cfm_clear(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg) +{ + u16 bit = cl_msg_cfm_clear_bit(msg->id); + + if (!CFM_TEST_AND_CLEAR_BIT(bit, &cl_hw->cfm_flags)) + cl_dbg_verbose(cl_hw, "Msg ID not set in cfm_flags (%s)\n", MSG_ID_STR(msg->id)); +} + +void cl_msg_cfm_simulate_timeout(struct cl_hw *cl_hw) +{ + u16 bit = cl_msg_cfm_set_bit(DBG_SET_MOD_FILTER_REQ); + + mutex_lock(&cl_hw->msg_tx_mutex); + CFM_SET_BIT(bit, &cl_hw->cfm_flags); + cl_msg_cfm_wait(cl_hw, bit, DBG_STR_SHIFT(DBG_SET_MOD_FILTER_REQ)); +} + From patchwork Thu Jun 17 15:59:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30853C2B9F4 for ; Thu, 17 Jun 2021 16:05:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B9B6613E9 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 093/256] cl8k: add fw/msg_cfm.h Date: Thu, 17 Jun 2021 15:59:40 +0000 Message-Id: <20210617160223.160998-94-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:15 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f513e5ca-6734-4fea-7a42-08d931a98ebd X-MS-TrafficTypeDiagnostic: AM9P192MB0887: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fqHujkMFikTpFElOeC7CXlDCFkEIftMGJuttO3h1F+1Zj/lOzeoE5/FZcS9dKVV1ZUCmGnqMz410LzQAHWJNvV8fpFx7zH4UN2VJuHKe0QWhputJhIK0tTa0s7WGLApHY3vQd4vvKkD7X9UfP1t4Fey6+8Wfz3EV5SyTIsH9QO3AkFTTruYUbiJxix4bYI1T3E2KFr1+kEQEHUmYX3grMKTBGjvd3vYwIrmQ7XCw671wDcHaLmmNu6JzWHbl/oqC07aP9S562d+STDnf1xmI+VTfOnZerhEpu/aCyFY/kaXJhqrpOlNh1LJ9PHioFKc/uj82zOjYZSmz5yoGjmYBtKbdXn1gzfArckkKXjt1ARS2/lWfAVSLFf/+CWyKStmVQB8CQajwrfamfdMPJMFCITkzYxrpl9d19W64jRgipH/eYlTUbFJoOkNpli3W71bLWmP+NRAoV5kbjKoTGVxNq/XSNbx7P2zmNEtDLX8sovbyS0RjNdDF6DInm/GPyYYEnCH3rMh9vk44QctEw56wUrmVFAPe52a0t7RT6cLO5XxPwYWTfepN7xC8ZgrzLjaiaK3eKGUHE5wH3DPWDb+OBpBPWjwFXrHW2Tr/AArhbNTjq1ltyq1lDRHJzRhFNt8pqj6xOM5FMn9tU33WEujC9l4J14Wb2rBPe1Y6pWxUuAcUrnVkJPHzk7N3QMjSBFLLW8GSWZLQ+gnzm+qn1ohRcQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(396003)(366004)(39850400004)(136003)(346002)(83380400001)(6666004)(38350700002)(4326008)(186003)(16526019)(5660300002)(54906003)(6506007)(26005)(55236004)(38100700002)(316002)(1076003)(107886003)(52116002)(8936002)(508600001)(66476007)(66946007)(66556008)(36756003)(6916009)(6486002)(86362001)(2616005)(956004)(2906002)(8676002)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4r4Yj0mLRaSyos5muf0/MrA0wbCRkjeHpyNvl60MSFdpVjEwrl6oRgCb6BuEK/vng5mC/kZgynDsLlStHiB2kjtnCK+msAX6e7L9+CsE7MaswoKMWw+X4NREpsBOk2PPsxdsi6wk1m90df1hxvb0Q+NIroAWdHocUzIJ/k54E9v8EpmLdjtzpLxOQyA2yY3WiXRVT+r5FRaMVxQcKQydoKyzznVy0LY1Clv4OPWG15Sq5Hk49NvxLfBkiA9uNuhsv78zrY+Cdj+TQSdkSfPXqyszd6n1sfrfCD/sypGzEnu97Q/mlxTRVbjFyjLIl5zmiH24B2HcuZ5zqFmCQNwqKVjCZWH8yMR8oFbTpAK3zKZ4tmQs18ZZqBH1c/hAyCOPDICi9XPM5xRJzvc4FsJcNUS1HgKrHYi7neoWwsjiAo7TgztBZhKnz6v70Llf+JWqXpc4Nm0G6gshHnkLUK0QuMoJA8C+d3xj0z8ya8d83VOfysAnZlHWX2Oql4XfZ8bk/Aa3vCRq80LboObYwaauWljtNol5rNjI2v559KQ5xuVff8cBxyk1PJ+JdBwYLMuwUa1wGml8XZqMG9hpKV1gcfcrp6AdgRUfkPFW97zpSrsXg6woNjf391U5JyauszYZL/Etheb5u3XRPoREkfn98kAkfyNW+zmW8vgbrT9LA/qz4HxuWT/PzhaLiixyCMn4tKXVAYvwHxQgnSFF/rMWqKbFOKUba3Sw8qp70j8XUAFZBTWbw8ye9FvhelvtwAWWCTh6mAJUyVpo08LZ3zt+GlDJvn3+JNm9u2P432umtU9Y6ErjJoTWCCYGYazpqcvL1KkQqVDsarCYpZlML8kW1e24hNrQWf9YRThnYgzCA0Uh1XGu3ytHnVvv2QqCKBu106eXErvrenzzlbDW4scbej0QJskkrUof2HPfOiB0XqSRWngvtI9XljiZ+3Et0KtqaypJTd6HyTKeEjoHNCnvmA+2YdkYUHEie9rxaP9wD3dYXLWDFSOc47oA69F6jjrkRnKl0fUobo/ih+QorORWdtGe/sM5osnJTRjDFywSy1WNVJZCzN/X07D6oWO5rHlNcn+MXN2F1GR2+vWMJeFcoUD+9s9hstYKVO83ux40xJCdNoMtTXS+tyBviyPwqAuyTu2RCpW4sDlRcNlKg3ekcb0oq6rzkJ2h5nLHFQUTh4asDoNcD3BcQIhmfUY6lAm3QDx6mrvX/sN3/PMJttQRb4TD/Ntj3+vQLXdz2qa5MblxByB6YY4BgpxTs3vYEcqrOAfLX5jWNECXnTfZQzm7omocD+NsVW1Gia3PZvYHahIv07K/87n04d5OShYnpA0F X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: f513e5ca-6734-4fea-7a42-08d931a98ebd X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:16.5115 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4EheFcWgKRt5n9WdYq7dHf3vU1aQoImfJofgNNsIWfVPXM0u6NmZHq86Szbv6kBfIBFTIN6cUFG9KphFSygo+g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0887 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/msg_cfm.h | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/msg_cfm.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/msg_cfm.h b/drivers/net/wireless/celeno/cl8k/fw/msg_cfm.h new file mode 100644 index 000000000000..21c4996634ae --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/msg_cfm.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_MSG_CFM_H +#define CL_MSG_CFM_H + +#include "hw.h" +#include "fw/fw_msg.h" + +/* Timeout waiting for firmware confirmation */ +#define CL_MSG_CFM_TIMEOUT_MS 400 +#define CL_MSG_CFM_TIMEOUT_JIFFIES msecs_to_jiffies(CL_MSG_CFM_TIMEOUT_MS) + +#define CL_MSG_CFM_TIMEOUT_CALIB_MS 1800 +#define CL_MSG_CFM_TIMEOUT_CALIB_JIFFIES msecs_to_jiffies(CL_MSG_CFM_TIMEOUT_CALIB_MS) + +#define CFM_CLEAR_BIT(bit, cfm_flags) \ + clear_bit((bit) & 0x1f, *(cfm_flags) + ((bit) >> 5)) + +#define CFM_SET_BIT(bit, cfm_flags) \ + set_bit((bit) & 0x1f, *(cfm_flags) + ((bit) >> 5)) + +#define CFM_TEST_BIT(bit, cfm_flags) \ + test_bit((bit) & 0x1f, *(cfm_flags) + ((bit) >> 5)) + +#define CFM_TEST_AND_CLEAR_BIT(bit, cfm_flags) \ + test_and_clear_bit((bit) & 0x1f, *(cfm_flags) + ((bit) >> 5)) + +u16 cl_msg_cfm_set_bit(u16 req); +int cl_msg_cfm_wait(struct cl_hw *cl_hw, u16 bit, u16 req_id); +void cl_msg_cfm_assign_and_clear(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg); +void cl_msg_cfm_clear(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg); +void cl_msg_cfm_simulate_timeout(struct cl_hw *cl_hw); + +#endif /* CL_MSG_CFM_H */ From patchwork Thu Jun 17 15:59:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D15FBC49EA3 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/msg_rx.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/msg_rx.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/msg_rx.h b/drivers/net/wireless/celeno/cl8k/fw/msg_rx.h new file mode 100644 index 000000000000..14d971e81db9 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/msg_rx.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_MSG_RX_H +#define CL_MSG_RX_H + +void cl_msg_rx_tasklet(unsigned long data); +void cl_msg_rx_flush_all(struct cl_hw *cl_hw); + +#endif /* CL_MSG_RX_H */ From patchwork Thu Jun 17 15:59:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6FB1C2B9F4 for ; Thu, 17 Jun 2021 16:06:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9CF18613F9 for ; Thu, 17 Jun 2021 16:06:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230452AbhFQQI2 (ORCPT ); Thu, 17 Jun 2021 12:08:28 -0400 Received: from mail-eopbgr80045.outbound.protection.outlook.com ([40.107.8.45]:44002 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232021AbhFQQHk (ORCPT ); Thu, 17 Jun 2021 12:07:40 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Pgyw8YZ/xg+GdnqOkf98YnrARmJpBxH7nmvlIj43TKWocBeBMCpuvi1WXuvF6m/9HLXtPzmDZc+HgdI6GRjTdLoVJrVarUVtd3OYdhyM13zWZbOAwIhGOaeXqfTOaIdoptsm945v3qipVXCx7yr8oBEJv4x8/41R4XW4SmoAy6KA3mf+ZcEtrkcj8xYhTm9qtUOSosEmnclnG5CG0Rf63DLokCINJ30RN2PI9OgB75LUhY2nI2yRUcDOmprZq4Eo5atLwJDxG1z+qu0I1FO4V0Gha2fs6WFhRJrjNqmXjv1LXb58xehXitZVmfgr74oLlrklXahZhi8iGlgrkG3sIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OAeK8Te/yjbEjczLAboijJpDNnp7t37lh9x+QKRG/KU=; b=E2mZaEbwyDG38gHhZmaMD/A1ogob89beH9Jm4qm7ZD27QQ/Al4g1ElhQZtNW1KTXwCcWyMmGoplUVXY/sx+tGb+i3Pi2Q7+VszZ8QiJENMPuZ4ym3X3W2ldOUQSiAz/r2s2ormBhxm9vbnfzch1TSyH6c7RV/Fd7qP6V1228tSHJdHLxjf7T6dwH6JaSLo9LLfGNcW7LAR7DkE2l/DXwEUKSbbkyPqJgwjJqXXXzwmytiSHuMEp28UNjBPzwfvubdtkuBgBDDo6YjkpPE7k/VizJhgnpow96XfdHmtFkgiQHinCY2LIaFYBctN8YV2FokxQsBY0pDal/7jCZ0ZAFyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OAeK8Te/yjbEjczLAboijJpDNnp7t37lh9x+QKRG/KU=; b=C0e1nBsm1WqxMpOY4qE6MZb1uM+4HRHAufZX8tlsZAGaLuheBzwo9LcSWbHnJDNl03k5S1WVZKPoFzlBKbPIl1hUplUPPyH5dIGRoI4W61L8BezsE3MjWA8eVPHOumkrl2Mm5xj/2pKtWxhScUI9ckgHlYT+72c7U5DbtfaLyHE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB0887.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1f8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:02 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:02 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 096/256] cl8k: add fw/msg_tx.c Date: Thu, 17 Jun 2021 15:59:43 +0000 Message-Id: <20210617160223.160998-97-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:18 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 735f5ef6-49c5-4340-9be9-08d931a99092 X-MS-TrafficTypeDiagnostic: AM9P192MB0887: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dcN159enWILxkKxcPjZdEZWVAWkYWDvCEegUxMwQBuVs3LjBsTSrt1UEQGhLjkcDCMSagOgXq0qBVtgd0Tqie0xsuG6Np8oVvJGiGtSKzF3yN3VK36jBVVLNVlxHIwjkm35OvdCsw9R0EtdEnJCcl2X806N/PHQ6EUUglAk8e7wiBx+WLcL9RSgvb6j/aogJ3OmUocC42dMFBA4pciAqPld8ZyMtyN3snJq3yv2ct1O2TMizpIdVpXLiRM6F81P82+ohUKLoBPr+Myb6Y86MGtB+D82lwBsme05Rk5x0OAmzfBg5NENjjgX468Q2y1axd0sZRAKGj4IHuyaNClPeyDKcG5qzWcGbTEfRSrhulSZnwtZUPYaBnZBmZXdl6B72zPOfnjTw6c1pdQsrqIJJ/7KlrG9RazvgsD0pBkH3EduqXBt+7bcZWv3Moh04Y/CkXeZsL40IvenTwe4+6/ZnHev+0a+1Rhy7GS3Buhg0/64HP47RgLJzsPdZL5mwhKfSaxwGj/LOyMDMHERLmiYD9VSrK6gkE08qszIFz9a0ZIZWbbLMm/cM4jhRydHXdhZ/DngqqlHuEi4UpEV1J20ARLQICVt3QMypB16A2SEJSZaAMwRq+7YHcoU7gWhET9nk+U4C3qzRMSZWo1fb4hHbsp1I8Chcp4AT1rGaiauA9jdadenR3vClMp303GMdDktQhwxvqg8rzCokA0tpKdkUeg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(396003)(366004)(39850400004)(136003)(346002)(83380400001)(6666004)(38350700002)(4326008)(186003)(16526019)(5660300002)(54906003)(6506007)(26005)(55236004)(38100700002)(316002)(1076003)(107886003)(30864003)(52116002)(8936002)(508600001)(66476007)(66946007)(66556008)(36756003)(6916009)(6486002)(86362001)(2616005)(956004)(2906002)(8676002)(9686003)(6512007)(69590400013)(32563001)(559001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FkWm5ZFmZHs46B4E8Gcdc4d4QRUUVfYXnxroplnJc3CkhYScjYecXmcTC15rmmEZFKiv/lGBdo3kgJSkZyhCs7ouaaYVgeQmwuqnouPbHgSKiIxv5F1X5YNmnB6Hb1upl4sXLxuwhKc9Q7gEpcpUsYgJs2JbDoOq0oOpKZ3WcQhJ5iWFx2+t71dW8zyRQ8sFyRa8oK+pb212K2IvRYE3mQ2YYSNDGlSkl2/G3y47v6jBksY9tKLg7Fy/bMoXGMXuyxzYWQ49eOHeYpdsr5IHgjXsDWS+y5KSsYVVGFhUOVSxGkUXgsg3HWP68hM/Lmr2SgJ1evnuHGihJ/rtF8YvEjYqNmsGzN1rIFfnwbTVOs4282d3pIp2Ebbz/yo6QNhR6qLw2WoDQHJJ5wmmg2lcqdG4qgIZzfbhB5MJOPBZdpvw5z8ALYJ+haoIIe9RH+8Qa7vxFH5IKz8B22NNsN5P1Hgk095HlmcKH32BaDD98z9VtHzchMuCJqWkirqj1VH3unqqAVnVJYFZ09NXM/CmQyNYi84BjbOfCujt73Xi+JcyAxa0C3K6r6DXehVuPz2O16olt0RKKp3ZSn2590GvQ2yTvMQyKfbb51CgdcmRzMJ8zUd3eMNxJk6G7LL4kgBkp8HukTnIpAJKbadu2nyYjoLRecQp3fcuD6KKn8rErheBsLEIyBH4nH2hpjEmOcqSwvx5esKZgFSyWRO/8IBEjROTdjzzJSJl1+qmkWO+xqVkZf2Y+w3CsvXw2JGN4qmYXb/LmcO3L7kP1mw1WG0HbDLHXz3oEWxSTtGND+kl9Cp0oxh1CqYFQmC586Ef3MiIytQ7sWyfCkczgaeEkpVQjO9TOrP+qi6MTnEUmYPc1mc4wVRYJgiQ6+j4l4gWGjRhObs3VdDjjDeR7xNFaxMTutvYfJvxf+Er8zThWTdP7iK+39QNnYv1QN7RYcVbz5WXYeW/MsUMzIP4kHFPgNxS4EpCADIZgQ7PbO6grd+LM4bp8YGzhdaOqhjnHtNwjWMmwG9cuKeGsArkzbB0scRjOGe0RA13By89zkJfYbBYd74aMF8SXobPwS8hQzUaJBn4xAIC8vk8SXFisqYB4R59lLOfc7A5FkkrgpWS8H0idVul/3emWgKj1JmOcb+ghmsfAfjqIK8tRWVd/WchKwV6CuPs/u94yTZu3VP4OJrqMGRilhI2kjS2xxmEmitHxYnyZhrJr7W6ZDcXaCVxFFJiONuLC6BvkfGdgM6gijsiLhCLGll7IGK7BVnaMYeR/5NwFU36uGfmUr0OGDm4tM6vAjtjyoK8mYSOOBziKuEN+GOOLrY+7Td5Kfr4nkDOdkHd X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 735f5ef6-49c5-4340-9be9-08d931a99092 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:19.8967 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q34Oyn8Iq8ocIPGmkBJyLylxzirI64RCLuYDknqO7QeesAMI7TJhNG3d9An473PxPALtzh7cIscwCvWrmevkmw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0887 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/fw/msg_tx.c | 1800 ++++++++++++++++++ 1 file changed, 1800 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/fw/msg_tx.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/fw/msg_tx.c b/drivers/net/wireless/celeno/cl8k/fw/msg_tx.c new file mode 100644 index 000000000000..b63d5be24660 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/fw/msg_tx.c @@ -0,0 +1,1800 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chip.h" +#include "tx/tx.h" +#include "rx/rx.h" +#include "fw/msg_tx.h" +#include "fw/msg_cfm.h" +#include "fw/fw_msg.h" +#include "drv_ops.h" +#include "temperature.h" +#include "chan_info.h" +#include "power.h" +#include "env_det.h" +#include "rx/rx_filter.h" +#include "prot_mode.h" +#include "rate_ctrl.h" +#include "utils/utils.h" +#include "calib.h" +#include "band.h" +#include "reg/reg_riu.h" +#include "reg/reg_ricu.h" +#include "calib.h" +#include "recovery.h" +#include "utils/math.h" +#include "fem.h" +#include "agc_params.h" +#include "mac_addr.h" +#include "cap.h" +#include "ampdu.h" +#include "phy/phy_common_lut.h" +#include "channel.h" + +#define DRV_TASK_ID 100 + +#define CL_DEF_ANT_BITMAP 0x55 + +/* No scale-down on ASIC platform */ +#define CL_ASIC_FW_SCALEDOWN 1 + +struct cl_msg_tx_work { + struct work_struct ws; + + /* Background message info */ + struct cl_hw *cl_hw; + void *msg_params; +}; + +void cl_msg_tx_free_cfm_params(struct cl_hw *cl_hw, u16 id) +{ + /* Free message and set pointer to NULL */ + kfree(cl_hw->msg_cfm_params[id]); + cl_hw->msg_cfm_params[id] = NULL; +} + +static inline void *cl_msg_zalloc(struct cl_hw *cl_hw, u16 msg_id, u8 dst_task_id, u16 param_len) +{ + struct fw_msg *msg; + u32 total_size = ALIGN(sizeof(struct fw_msg) + param_len, sizeof(u32)); + u32 max_size = sizeof(u32) * IPC_A2E_MSG_BUF_SIZE; + + if (total_size > max_size) { + cl_dbg_err(cl_hw, "total size (%u) > max size (%u)\n", + total_size, max_size); + return NULL; + } + + /* msg is freed out of the scope of this function */ + msg = kzalloc(total_size, GFP_ATOMIC); + if (!msg) + return NULL; + + msg->msg_id = cpu_to_le16(msg_id); + msg->dst_kern_id = cl_hw->fw_dst_kern_id; + msg->dst_task_id = dst_task_id; + msg->src_kern_id = KERN_HOST; + msg->src_task_id = DRV_TASK_ID; + msg->param_len = cpu_to_le16(param_len); + + return msg->param; +} + +static inline void cl_msg_free(const void *msg_param) +{ + kfree(container_of((void *)msg_param, struct fw_msg, param)); +} + +static void cl_send_msg_background_handler(struct work_struct *ws) +{ + struct cl_msg_tx_work *msg_tx_work = container_of(ws, struct cl_msg_tx_work, ws); + + cl_drv_ops_msg_fw_send(msg_tx_work->cl_hw, msg_tx_work->msg_params, true); + kfree(msg_tx_work); +} + +static int cl_send_msg_background(struct cl_hw *cl_hw, + const void *msg_params) +{ + /* Generate & populate the work struct wrapper for the background msg */ + struct cl_msg_tx_work *msg_tx_work = kzalloc(sizeof(*msg_tx_work), GFP_ATOMIC); + + if (msg_tx_work) { + INIT_WORK(&msg_tx_work->ws, cl_send_msg_background_handler); + msg_tx_work->cl_hw = cl_hw; + msg_tx_work->msg_params = (void *)msg_params; + + /* Schedule work, the work will be executed in the background */ + queue_work(cl_hw->drv_workqueue, &msg_tx_work->ws); + + return 0; + } + + cl_dbg_err(cl_hw, "msg_tx_work allocation failed\n"); + cl_msg_free(msg_params); + + return -ENODATA; +} + +static int cl_send_request(struct cl_hw *cl_hw, const void *msg_params) +{ + int ret; + bool background = (preempt_count() != 0); + + if (background) { + /* + * asynchronous operation mode, message would be triggered in the background + */ + ret = cl_send_msg_background(cl_hw, msg_params); + } else { + /* + * synchronous operation mode, message would be triggered immediately + * feedback to caller given immediately + */ + ret = cl_drv_ops_msg_fw_send(cl_hw, msg_params, false); + } + + /* + * In case of synchronous mode ret success implies that the msg was successfully + * transmited where is asynchronous mode ret success implies that the msg was + * successfully pushed to background queue + */ + return ret; +} + +int cl_msg_tx_reset(struct cl_hw *cl_hw) +{ + void *void_param; + + /* RESET REQ has no parameter */ + void_param = cl_msg_zalloc(cl_hw, MM_RESET_REQ, TASK_MM, 0); + if (!void_param) + return -ENOMEM; + + return cl_send_request(cl_hw, void_param); +} + +static u8 copy_mask_bits(u8 mask, u8 num_bits) +{ + /* Copy first X bits that are set in mask to new_mask */ + u8 i = 0, cntr = 0, new_mask = 0; + + for (i = 0; i < MAX_ANTENNAS; i++) { + if (mask & (1 << i)) { + new_mask |= (1 << i); + + cntr++; + if (cntr == num_bits) + break; + } + } + + return new_mask; +} + +static void cl_fill_ant_config(struct cl_hw *cl_hw, + struct cl_antenna_config *ant_config, + u8 num_antennas, u8 mask_antennas, + u8 tx_mask_cck, u8 rx_mask_cck) +{ + struct cl_chip *chip = cl_hw->chip; + u8 ricu_cdb = 0; + u8 ant_shift = cl_hw_ant_shift(cl_hw); + + ant_config->num_tx_he = num_antennas; + ant_config->num_rx = num_antennas; + ant_config->mask_tx_he = mask_antennas << ant_shift; + ant_config->mask_rx = mask_antennas << ant_shift; + + /* Configuration for TX OFDM/HT/VHT (limited to 4 antennas) */ + if (num_antennas <= MAX_ANTENNAS_OFDM_HT_VHT) { + ant_config->num_tx_ofdm_ht_vht = num_antennas; + ant_config->mask_tx_ofdm_ht_vht = mask_antennas << ant_shift; + } else { + ant_config->num_tx_ofdm_ht_vht = MAX_ANTENNAS_OFDM_HT_VHT; + ant_config->mask_tx_ofdm_ht_vht = + copy_mask_bits(mask_antennas, MAX_ANTENNAS_OFDM_HT_VHT) << ant_shift; + } + + /* Antenna configuration for CCK */ + if (cl_band_is_24g(cl_hw)) { + ant_config->mask_tx_cck = tx_mask_cck << ant_shift; + ant_config->mask_rx_cck = rx_mask_cck << ant_shift; + } + + ricu_cdb = ricu_static_conf_0_cdb_mode_maj_getf(chip); + + /* + * In current implementation cdb_mode equals the num of ants for SX1 + * cbd_mask 0x0 -> SX0 chain. 0x1-> SX1 chain. + */ + ricu_cdb = MAX_ANTENNAS_CHIP - ricu_cdb; + ricu_cdb = ANT_MASK(ricu_cdb); + ricu_cdb = ~ricu_cdb; + + ant_config->cdb_mask = ricu_cdb; +} + +static void cl_fill_fem_config(struct cl_hw *cl_hw, struct cl_fem_config *fem_conf) +{ + int i; + + cl_fem_get_registers(cl_hw, fem_conf->reg); + + for (i = 0; i < ARRAY_SIZE(fem_conf->reg); i++) + fem_conf->reg[i] = cpu_to_le32(fem_conf->reg[i]); +} + +static void cl_fill_calib_config(struct cl_hw *cl_hw, struct cl_calib_param *calib_param, + u16 primary, u16 center, u8 mode) +{ + struct cl_hw *cl_hw_other = cl_hw_other_tcv(cl_hw); + struct cl_tcv_conf *conf = cl_hw->conf; + u8 ant = 0; + u8 calib_bitmap = cl_hw->mask_num_antennas; + u8 ant_shift = cl_hw_ant_shift(cl_hw); + + memset(calib_param->ant_tx_pairs, U8_MAX, ARRAY_SIZE(calib_param->ant_tx_pairs)); + memset(calib_param->ant_rx_pairs, U8_MAX, ARRAY_SIZE(calib_param->ant_rx_pairs)); + + ant_for_each(ant) { + if (calib_bitmap & (1 << ant)) { + calib_param->ant_tx_pairs[ant] = conf->ci_calib_ant_tx[ant - ant_shift]; + if (mode & SET_CHANNEL_MODE_CALIB_IQ) + calib_param->ant_rx_pairs[ant] = + conf->ci_calib_ant_rx[ant - ant_shift]; + } + } + + if (IS_PHY_ATHOS(cl_hw->chip)) { + calib_param->conf.initial_rx_gain = CALIB_RX_GAIN_DEFAULT_ATHOS; + calib_param->conf.rx_gain_upper_limit = CALIB_RX_GAIN_UPPER_LIMIT_ATHOS; + calib_param->conf.rx_gain_lower_limit = CALIB_RX_GAIN_LOWER_LIMIT_ATHOS; + } else { + calib_param->conf.initial_rx_gain = CALIB_RX_GAIN_DEFAULT; + calib_param->conf.rx_gain_upper_limit = CALIB_RX_GAIN_UPPER_LIMIT; + calib_param->conf.rx_gain_lower_limit = CALIB_RX_GAIN_LOWER_LIMIT; + } + + calib_param->conf.initial_tx_gain = CALIB_TX_GAIN_DEFAULT; + calib_param->conf.nco_freq = cpu_to_le16(CALIB_NCO_FREQ_DEFAULT); + calib_param->conf.nco_amp = CALIB_NCO_AMP_DEFAULT; + calib_param->conf.sleeve_trshld = GAIN_SLEEVE_TRSHLD_DEFAULT; + calib_param->conf.n_samples_exp_lolc = N_SAMPLES_EXP_LOLC; + calib_param->conf.n_samples_exp_iqc = N_SAMPLES_EXP_IQC; + calib_param->conf.p_thresh = cpu_to_le32(LO_P_THRESH); + calib_param->conf.n_bit_fir_scale = N_BIT_FIR_SCALE; + calib_param->conf.n_bit_amp_scale = N_BIT_AMP_SCALE; + calib_param->conf.n_bit_phase_scale = N_BIT_PHASE_SCALE; + + cl_calib_iq_get_tone_vector(cl_hw->bw, calib_param->conf.tone_vector); + + calib_param->conf.gp_rad_trshld = cpu_to_le32(GP_RAD_TRSHLD_DEFAULT); + calib_param->conf.ga_lin_upper_trshld = cpu_to_le32(GA_LIN_UPPER_TRSHLD_DEFAULT); + calib_param->conf.ga_lin_lower_trshld = cpu_to_le32(GA_LIN_LOWER_TRSHLD_DEFAULT); + calib_param->conf.comp_filter_len = COMP_FILTER_LEN_DEFAULT; + calib_param->conf.singletons_num = SINGLETONS_NUM_DEFAULT; + calib_param->conf.tones_num = IQ_NUM_TONES_REQ; + calib_param->conf.rampup_time = cpu_to_le16(RAMPUP_TIME); + calib_param->conf.lo_coarse_step = cpu_to_le16(LO_COARSE_STEP); + calib_param->conf.lo_fine_step = cpu_to_le16(LO_FINE_STEP); + + calib_param->other_tcv.prim20_freq = cpu_to_le16(primary + SX_FREQ_OFFSET_Q2); + cl_phy_oly_lut_update(cl_hw->nl_band, + center + SX_FREQ_OFFSET_Q2, + &calib_param->other_tcv.center1_freq_lut); + + if (cl_chip_is_both_enabled(cl_hw->chip)) { + calib_param->other_tcv.mask_tx_he = cl_hw_other->mask_num_antennas; + calib_param->other_tcv.num_tx_he = cl_hw_other->num_antennas; + calib_param->other_tcv.band = cl_band_to_fw_idx(cl_hw_other); + } else { + calib_param->other_tcv.mask_tx_he = cl_hw->mask_num_antennas; + calib_param->other_tcv.num_tx_he = cl_hw->num_antennas; + calib_param->other_tcv.band = cl_band_to_fw_idx(cl_hw); + } +} + +int cl_msg_tx_start(struct cl_hw *cl_hw) +{ + struct mm_start_req *req; + struct cl_phy_cfg *phy_cfg; + struct cl_start_param *param; + struct cl_cca_config *cca_config; + struct dbg_meta_data *dbg_metadata; + struct cl_chip *chip = cl_hw->chip; + struct cl_tcv_conf *tcv_conf = cl_hw->conf; + struct cl_chip_conf *chip_conf = chip->conf; + struct cl_ipc_host_env *ipc_env = cl_hw->ipc_env; + u8 bw = 0, ant = 0; + + req = cl_msg_zalloc(cl_hw, MM_START_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + phy_cfg = &req->phy_cfg; + param = &req->param; + cca_config = &phy_cfg->cca_config; + dbg_metadata = ¶m->dbg_metadata; + + phy_cfg->band = cl_band_to_fw_idx(cl_hw); + phy_cfg->channel_bandwidth = tcv_conf->ce_channel_bandwidth; + phy_cfg->ht_rxldpc_en = tcv_conf->ce_ht_rxldpc_en; + phy_cfg->freq_offset = cpu_to_le16(chip->eeprom_cache->calib.freq_offset); + phy_cfg->vns_tx_power_mode = chip_conf->ce_production_mode ? 0 : tcv_conf->ci_vns_pwr_mode; + phy_cfg->vns_rssi_suto_resp_th = tcv_conf->ci_vns_rssi_auto_resp_thr; + phy_cfg->afe_config_en = true; + phy_cfg->no_capture_noise_sleep = chip_conf->ci_no_capture_noise_sleep; + phy_cfg->gain_update_enable = tcv_conf->ci_gain_update_enable; + phy_cfg->mcs_sig_b = tcv_conf->ci_mcs_sig_b; + phy_cfg->ofdm_only = tcv_conf->ci_ofdm_only; + phy_cfg->hr_factor = tcv_conf->ci_hr_factor[phy_cfg->channel_bandwidth]; + phy_cfg->td_csd_en = tcv_conf->ci_csd_en; + phy_cfg->pe_duration_bcast = tcv_conf->ci_pe_duration_bcast; + phy_cfg->tx_digital_gain = cpu_to_le32(tcv_conf->ci_tx_digital_gain); + phy_cfg->tx_digital_gain_cck = cpu_to_le32(tcv_conf->ci_tx_digital_gain_cck); + phy_cfg->ofdm_cck_power_offset = (u8)tcv_conf->ci_ofdm_cck_power_offset; + phy_cfg->phy_clk_gating_en = tcv_conf->ci_phy_clk_gating_en; + + /* + * Set rx_sensitivity according to number of antennas. + * For all other antennas set 0xff which is equal to -1 + */ + memcpy(phy_cfg->rx_sensitivity, cl_hw->rx_sensitivity, cl_hw->num_antennas); + if (cl_hw->num_antennas < ARRAY_SIZE(phy_cfg->rx_sensitivity)) + memset(&phy_cfg->rx_sensitivity[cl_hw->num_antennas], U8_MAX, + MAX_ANTENNAS - cl_hw->num_antennas); + + if (!cl_hw->fw_send_start) { + cl_hw->fw_send_start = true; + phy_cfg->first_start = true; + } + + cl_fill_ant_config(cl_hw, &phy_cfg->ant_config, cl_hw->num_antennas, + cl_hw->mask_num_antennas, tcv_conf->ce_cck_tx_ant_mask, + tcv_conf->ce_cck_rx_ant_mask); + cl_fill_fem_config(cl_hw, &phy_cfg->fem_conf); + + cca_config->ed_rise_thr_dbm = (u8)tcv_conf->ci_cca_ed_rise_thr_dbm; + cca_config->ed_fall_thr_dbm = (u8)tcv_conf->ci_cca_ed_fall_thr_dbm; + cca_config->cs_en = tcv_conf->ci_cca_cs_en; + cca_config->modem_en = tcv_conf->ci_cca_modem_en; + cca_config->main_ant = tcv_conf->ci_cca_main_ant; + cca_config->second_ant = tcv_conf->ci_cca_second_ant; + cca_config->flag0_ctrl = tcv_conf->ci_cca_flag0_ctrl; + cca_config->flag1_ctrl = tcv_conf->ci_cca_flag1_ctrl; + cca_config->flag2_ctrl = tcv_conf->ci_cca_flag2_ctrl; + cca_config->flag3_ctrl = tcv_conf->ci_cca_flag3_ctrl; + cca_config->gi_rise_thr_dbm = (u8)tcv_conf->ci_cca_gi_rise_thr_dbm; + cca_config->gi_fall_thr_dbm = (u8)tcv_conf->ci_cca_gi_fall_thr_dbm; + cca_config->gi_pow_lim_dbm = (u8)tcv_conf->ci_cca_gi_pow_lim_dbm; + cca_config->ed_en = cpu_to_le16(tcv_conf->ci_cca_ed_en); + cca_config->gi_en = tcv_conf->ci_cca_gi_en; + + param->prot_log_nav_en = tcv_conf->ce_prot_log_nav_en; + param->prot_mode = cl_prot_mode_get(cl_hw); + param->prot_rate_format = tcv_conf->ce_prot_rate_format; + param->prot_rate_mcs = tcv_conf->ce_prot_rate_mcs; + param->prot_rate_pre_type = tcv_conf->ce_prot_rate_pre_type; + param->bw_signaling_mode = tcv_conf->ce_bw_signaling_mode; + param->cfm_size = cpu_to_le16(IPC_CFM_SIZE); + param->cfm_dma_base_addr = cpu_to_le32(ipc_env->cfm_dma_base_addr); + param->phy_dev = cpu_to_le16(chip_conf->ci_phy_dev); + param->fw_scale_down = cpu_to_le16(CL_ASIC_FW_SCALEDOWN); + param->hal_timeout.idle = cpu_to_le32(tcv_conf->ci_hal_idle_to); + param->hal_timeout.ac0 = cpu_to_le32(tcv_conf->ci_tx_ac0_to); + param->hal_timeout.ac1 = cpu_to_le32(tcv_conf->ci_tx_ac1_to); + param->hal_timeout.ac2 = cpu_to_le32(tcv_conf->ci_tx_ac2_to); + param->hal_timeout.ac3 = cpu_to_le32(tcv_conf->ci_tx_ac3_to); + param->hal_timeout.bcn = cpu_to_le32(tcv_conf->ci_tx_bcn_to); + + /* Update rxbuff/txqueue & ring_indices that hold the array metadata */ + param->ipc_ring_indices_base = cpu_to_le32(ipc_env->ring_indices_elem->dma_addr); + param->host_rxbuf_base_addr[CL_RX_BUF_RXM] = + ipc_env->rx_hostbuf_array[CL_RX_BUF_RXM].dma_payload_base_addr; + param->host_rxbuf_base_addr[CL_RX_BUF_FW] = + ipc_env->rx_hostbuf_array[CL_RX_BUF_FW].dma_payload_base_addr; + + /* + * The FW needs to be aware of the DMA addresses of the + * TX queues so it could fetch txdesc from the host. + */ + param->ipc_host_tx_queues_dma_addr = cpu_to_le32(cl_hw->ipc_env->tx_queues.dma_addr); + + /* + * Compilation flags match check - please add here all compilation flags + * which should be compiled on both driver and firmware. + */ + param->comp_flags = cpu_to_le32(0) | cpu_to_le32(BIT(CENX_CFG_CE_TX_CFM)); + + param->dbg_test_mode_max = DBG_TEST_MODE_MAX; + + param->ipc_rxbuf_size[CL_RX_BUF_RXM] = + cpu_to_le16(tcv_conf->ci_ipc_rxbuf_size[CL_RX_BUF_RXM]); + param->ipc_rxbuf_size[CL_RX_BUF_FW] = + cpu_to_le16(tcv_conf->ci_ipc_rxbuf_size[CL_RX_BUF_FW]); + + param->ipc_rxbuf_extra_headroom = cpu_to_le32(IPC_RXBUF_EXTRA_HEADROOM); + param->host_pci_gen_ver = chip_conf->ce_host_pci_gen_ver; + param->dma_lli_max_chan[0] = chip_conf->ci_dma_lli_max_chan[0]; + param->dma_lli_max_chan[1] = chip_conf->ci_dma_lli_max_chan[1]; + param->production_mode = chip_conf->ce_production_mode; + param->mult_ampdu_in_txop_en = tcv_conf->ci_mult_ampdu_in_txop_en; + param->cca_timeout = cpu_to_le32(tcv_conf->ci_cca_timeout); + param->long_retry_limit = tcv_conf->ce_long_retry_limit; + param->short_retry_limit = tcv_conf->ce_short_retry_limit; + param->assoc_auth_retry_limit = tcv_conf->ci_assoc_auth_retry_limit; + param->bcn_tx_path_min_time = cpu_to_le16(tcv_conf->ce_bcn_tx_path_min_time); + param->backup_bcn_en = tcv_conf->ci_backup_bcn_en; + param->tx_txop_cut_en = tcv_conf->ce_tx_txop_cut_en; + param->ac_with_bcns_flushed_cnt_thr = tcv_conf->ci_bcns_flushed_cnt_thr; + param->txl_statistics_struct_size = cpu_to_le32(sizeof(struct cl_txl_statistics)); + param->rxl_statistics_struct_size = cpu_to_le32(sizeof(struct cl_rxl_statistics)); + param->phy_err_prevents_phy_dump = tcv_conf->ci_phy_err_prevents_phy_dump; + param->tx_rx_delay = tcv_conf->ci_tx_rx_delay; + param->assert_storm_detect_thd = tcv_conf->ci_fw_assert_storm_detect_thd; + param->assert_time_diff_sec = tcv_conf->ci_fw_assert_time_diff_sec; + param->ps_ctrl_enabled = tcv_conf->ce_ps_ctrl_enabled; + param->phy_data_dma_addr = cpu_to_le32(cl_hw->phy_data_info.dma_addr); + param->phy_remote_rom_dma_addr = cpu_to_le32(cl_hw->fw_remote_rom.dma_addr); + param->iq_dcoc_calib_tables_dma_addr = cpu_to_le32(cl_hw->iq_dcoc_data_info.dma_addr); + param->power_table_dma_addr = cpu_to_le32(cl_hw->power_table_info.dma_addr); + param->tf_info_dma_addr = 0; + param->min_ant_pwr_q1 = cl_power_min_ant_q1(cl_hw); + + for (bw = 0; bw < ARRAY_SIZE(param->bw_factor_q2); bw++) { + cl_hw->power_db.bw_factor_q2[bw] = cl_power_bw_factor_q2(cl_hw, bw); + param->bw_factor_q2[bw] = + cl_convert_signed_to_reg_value(cl_hw->power_db.bw_factor_q2[bw]); + } + + for (ant = 0; ant < ARRAY_SIZE(param->ant_factor_q2); ant++) { + cl_hw->power_db.ant_factor_q2[ant] = cl_power_array_gain_q2(cl_hw, ant + 1); + param->ant_factor_q2[ant] = cl_hw->power_db.ant_factor_q2[ant]; + } + + param->default_distance.auto_resp_all = tcv_conf->ci_distance_auto_resp_all; + param->default_distance.auto_resp_msta = tcv_conf->ci_distance_auto_resp_msta; + param->su_force_min_spacing_usec = tcv_conf->ci_su_force_min_spacing; + param->mu_force_min_spacing_usec = tcv_conf->ci_mu_force_min_spacing; + param->force_tcv0_only = false; + param->rx_padding = tcv_conf->ci_rx_padding_en; + param->bar_cap_disable = tcv_conf->ci_bar_disable; + param->hw_bsr = 0; /* FIXME */ + param->drop_to_lower_bw = tcv_conf->ci_drop_to_lower_bw; + param->dra_enable = cl_chip_is_both_enabled(chip); /* DRA enable only in CDB mode */ + param->mac_clk_gating_en = tcv_conf->ci_mac_clk_gating_en; + param->imaging_blocker = tcv_conf->ci_imaging_blocker; + param->fec_coding = tcv_conf->ce_he_rxldpc_en; + param->cs_required = tcv_conf->ci_cs_required; + + if (!chip->fw_first_tcv) { + chip->fw_first_tcv = true; + param->first_tcv = true; + } + + dbg_metadata->lmac_req_buf_size = cpu_to_le32(sizeof(struct dbg_error_trace_info_drv)); + dbg_metadata->physical_queue_cnt = CL_MAX_BA_PHYSICAL_QUEUE_CNT; + dbg_metadata->agg_index_max = AGG_IDX_MAX; + dbg_metadata->ce_ac_max = CE_AC_MAX; + dbg_metadata->mu_user_max = MU_MAX_STREAMS; + dbg_metadata->txl_exch_trace_depth = DBG_TXL_FRAME_EXCH_TRACE_DEPTH; + dbg_metadata->mac_hw_regs_max = cpu_to_le16(HAL_MACHW_REG_NUM); + dbg_metadata->phy_hw_regs_max = cpu_to_le16(PHY_HW_DBG_REGS_CNT); + dbg_metadata->thd_chains_data_size = cpu_to_le16(DBG_THD_CHAINS_INFO_ARRAY_SIZE); + dbg_metadata->chains_info_elem_cnt = DBG_CHAINS_INFO_ELEM_CNT; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_version(struct cl_hw *cl_hw) +{ + void *void_param; + + /* VERSION REQ has no parameter */ + void_param = cl_msg_zalloc(cl_hw, MM_VERSION_REQ, TASK_MM, 0); + if (!void_param) + return -ENOMEM; + + return cl_send_request(cl_hw, void_param); +} + +int cl_msg_tx_add_if(struct cl_hw *cl_hw, struct ieee80211_vif *vif, + u8 vif_index) +{ + struct mm_add_if_req *req; + + req = cl_msg_zalloc(cl_hw, MM_ADD_IF_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + cl_mac_addr_copy(req->addr.array, vif->addr); + + switch (vif->type) { + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_P2P_CLIENT: + req->type = MM_STA; + break; + + case NL80211_IFTYPE_ADHOC: + req->type = MM_IBSS; + break; + + case NL80211_IFTYPE_AP: + case NL80211_IFTYPE_P2P_GO: + req->type = MM_AP; + break; + + case NL80211_IFTYPE_MONITOR: + req->type = MM_MONITOR; + break; + + case NL80211_IFTYPE_MESH_POINT: + req->type = MM_MESH_POINT; + break; + + default: + req->type = MM_STA; + break; + } + + req->tx_strip_vlan = 1; + req->mac_addr_hi_mask = cpu_to_le32(cl_hw->mask_hi); + req->mac_addr_low_mask = cpu_to_le32(cl_hw->mask_low); + req->inst_nbr = vif_index; + + if (vif->type == NL80211_IFTYPE_AP) { + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); + struct ps_data *ps = &sdata->u.ap.ps; + + req->start_dtim_count = (u8)(ps->dtim_count); + } + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_remove_if(struct cl_hw *cl_hw, u8 vif_index) +{ + struct mm_remove_if_req *req; + + req = cl_msg_zalloc(cl_hw, MM_REMOVE_IF_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->inst_nbr = vif_index; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_sta_add(struct cl_hw *cl_hw, struct ieee80211_sta *sta, + struct cl_vif *cl_vif, u8 recovery_sta_idx, + u32 rate_ctrl_info) +{ + struct mm_sta_add_req *req; + struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap; + struct ieee80211_sta_vht_cap *vht_cap = &sta->vht_cap; + struct ieee80211_sta_he_cap *he_cap = &sta->he_cap; + u16 my_aid = 0; + u8 inst_nbr = cl_vif->vif_index; + bool is_6g = cl_band_is_6g(cl_hw); + struct cl_sta *cl_sta = IEEE80211_STA_TO_CL_STA(sta); + + req = cl_msg_zalloc(cl_hw, MM_STA_ADD_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + cl_mac_addr_copy(req->mac_addr.array, sta->addr); + + if (cl_vif->vif->type == NL80211_IFTYPE_STATION) + my_aid = cl_vif->vif->bss_conf.aid; + + if (is_6g) { + u8 mac_cap_info4 = he_cap->he_cap_elem.mac_cap_info[4]; + + req->su_bfee = (mac_cap_info4 & IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE) ? 1 : 0; + req->mu_bfee = (mac_cap_info4 & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER) ? 1 : 0; + } else if (vht_cap->vht_supported) { + req->su_bfee = (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) ? 1 : 0; + req->mu_bfee = (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) ? 1 : 0; + } + + req->ampdu_min_spacing = cl_sta->ampdu_min_spacing; + + if (he_cap->has_he) { + u8 mac_cap_info1 = he_cap->he_cap_elem.mac_cap_info[1]; + u8 mac_cap_info3 = he_cap->he_cap_elem.mac_cap_info[3]; + + req->he_tf_mac_padding_duration = + (mac_cap_info1 & IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_MASK); + + req->he_rx_ctrl_frm_to_mbss = + (mac_cap_info3 & IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS) ? + true : false; + + /* Fill PE duration table */ + cl_cap_ppe_duration(cl_hw, sta, req->pe_duration); + } + + cl_ampdu_size_exp(cl_hw, sta, &req->ampdu_size_exp_he, + &req->ampdu_size_exp_vht, &req->ampdu_size_exp_ht); + + if (cl_hw->conf->ce_txldpc_en) { + if (he_cap->has_he) + req->ldpc_enabled = (he_cap->he_cap_elem.phy_cap_info[1] & + IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) ? 1 : 0; + else if (vht_cap->vht_supported) + req->ldpc_enabled = (vht_cap->cap & IEEE80211_VHT_CAP_RXLDPC) ? 1 : 0; + else if (ht_cap->ht_supported) + req->ldpc_enabled = (ht_cap->cap & IEEE80211_HT_CAP_LDPC_CODING) ? 1 : 0; + } + + /* TODO Set the interface index from the vif structure */ + req->inst_nbr = inst_nbr; + + req->aid = cpu_to_le16(sta->aid); + req->my_aid = cpu_to_le16(my_aid); + req->recovery_sta_idx = recovery_sta_idx; + + /* Station power save configuration */ + req->uapsd_queues = sta->uapsd_queues; + req->max_sp = sta->max_sp; + + /* Set WRS default parameters for rate control */ + req->tx_params.rate = cpu_to_le32(rate_ctrl_info); + + /* Fill TX antenna with default value */ + req->tx_params.ant_set = CL_DEF_ANT_BITMAP; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_sta_del(struct cl_hw *cl_hw, u8 sta_idx) +{ + struct mm_sta_del_req *req; + + req = cl_msg_zalloc(cl_hw, MM_STA_DEL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = sta_idx; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_filter(struct cl_hw *cl_hw, u32 filter, bool force) +{ + struct mm_set_filter_req *req; + u32 rx_filter = 0; + + if (cl_channel_is_scan_active(cl_hw)) { + cl_dbg_trace(cl_hw, "Set filter ignored due to active channel scan\n"); + return 0; + } + + if (force) + rx_filter = filter; + else + rx_filter = cl_rx_filter_update_flags(cl_hw, filter); + + if (rx_filter == cl_hw->rx_filter) { + cl_dbg_trace(cl_hw, "Rx filter 0x%x already set - return\n", rx_filter); + return 0; + } + + req = cl_msg_zalloc(cl_hw, MM_SET_FILTER_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + /* Now copy all the flags into the message parameter */ + req->filter = cpu_to_le32(rx_filter); + cl_hw->rx_filter = rx_filter; + + cl_dbg_trace(cl_hw, "new total_flags = 0x%08x\nrx filter set to 0x%08x\n", + filter, rx_filter); + + return cl_send_request(cl_hw, req); +} + +u8 cl_mark_calib_flags(struct cl_hw *cl_hw, u8 mode) +{ + int lna = 0; + int ant = 0; + u8 calib_info_set = 0; + struct cl_iq_dcoc_info *iq_dcoc_db = &cl_hw->phy_data_info.data->iq_dcoc_db; + + /* In case DCOC is going to be calibrated, no need to raise any calibration flag. */ + if (mode & SET_CHANNEL_MODE_CALIB_DCOC) + return calib_info_set; + + /* Check if DCOC flag should be marked */ + for (lna = 0; lna < ARRAY_SIZE(iq_dcoc_db->dcoc); lna++) { + for (ant = 0; ant < cl_hw->num_antennas; ant++) { + if (iq_dcoc_db->dcoc[lna][ant].i || iq_dcoc_db->dcoc[lna][ant].q) { + calib_info_set |= SET_PHY_DATA_FLAGS_DCOC; + break; + } + } + } + + /* Check if IQ Tx LOLC flag should be marked */ + for (ant = 0; ant < cl_hw->num_antennas; ant++) { + if (iq_dcoc_db->iq_tx_lolc[ant]) { + calib_info_set |= SET_PHY_DATA_FLAGS_IQ_TX_LOLC; + break; + } + } + + /* Check if IQ Tx flag should be marked */ + for (ant = 0; ant < cl_hw->num_antennas; ant++) { + if (iq_dcoc_db->iq_tx[ant].coef0 || iq_dcoc_db->iq_tx[ant].coef1 || + iq_dcoc_db->iq_tx[ant].coef2 || iq_dcoc_db->iq_tx[ant].gain) { + calib_info_set |= SET_PHY_DATA_FLAGS_IQ_TX; + break; + } + } + + /* Check if IQ Rx flag should be marked */ + for (ant = 0; ant < cl_hw->num_antennas; ant++) { + if (iq_dcoc_db->iq_rx[ant].coef0 || iq_dcoc_db->iq_rx[ant].coef1 || + iq_dcoc_db->iq_rx[ant].coef2 || iq_dcoc_db->iq_rx[ant].gain) { + calib_info_set |= SET_PHY_DATA_FLAGS_IQ_RX; + return calib_info_set; + } + } + return calib_info_set; +} + +static int __cl_msg_tx_set_channel(struct cl_hw *cl_hw, u32 channel, u8 bw, u16 primary, + u16 center, u8 mode) +{ + struct mm_set_channel_req *req; + int res = 0; + struct cl_phy_data *data = cl_hw->phy_data_info.data; + + /* Fill AGC parameters - check before we start building the message */ + if ((res = cl_agc_params_fill(cl_hw, &data->agc_params))) + return res; + + req = cl_msg_zalloc(cl_hw, MM_SET_CHANNEL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->band = cl_band_to_fw_idx(cl_hw); + req->bandwidth = bw; + req->prim20_freq = cpu_to_le16(primary); + cl_phy_oly_lut_update(cl_hw->nl_band, center, &req->center1_freq_lut); + req->hr_factor = cl_hw->conf->ci_hr_factor[bw]; + req->signal_ext = cl_hw->conf->ci_signal_extension_en; + + /* Set power per mcs offset after EIRP truncation */ + cl_power_tables_update(cl_hw, &data->pwr_tables); + + /* Get antenna power offset from eeprom */ + cl_calib_power_offset_fill(cl_hw, channel, bw, req->ant_pwr_offset); + + cl_calib_fill_phy_data(cl_hw, &data->iq_dcoc_db, SET_PHY_DATA_FLAGS_ALL); + + if (mode == SET_CHANNEL_MODE_CALIB) + req->calib_info_set = SET_PHY_DATA_FLAGS_ALL; + else + req->calib_info_set = SET_PHY_DATA_FLAGS_NONE; + + req->calib_param.mode = mode; + + if (mode & (SET_CHANNEL_MODE_CALIB_LOLC | SET_CHANNEL_MODE_CALIB_IQ)) { + req->sx_freq_offset_mhz = SX_FREQ_OFFSET_Q2; + cl_fill_calib_config(cl_hw, &req->calib_param, primary, center, mode); + } + + if (mode & SET_CHANNEL_MODE_CALIB_DCOC) { + if (IS_PHY_ATHOS(cl_hw->chip)) + req->calib_param.dcoc_max_vga = DCOC_MAX_VGA_ATHOS; + else + req->calib_param.dcoc_max_vga = DCOC_MAX_VGA; + } + + /* Antenna configuration */ + cl_fill_ant_config(cl_hw, &req->ant_config, cl_hw->num_antennas, cl_hw->mask_num_antennas, + cl_hw->conf->ce_cck_tx_ant_mask, cl_hw->conf->ce_cck_rx_ant_mask); + /* FEM configuration */ + cl_fill_fem_config(cl_hw, &req->fem_conf); + + res = cl_send_request(cl_hw, req); + + cl_temperature_comp_update_calib(cl_hw); + + cl_dbg_info(cl_hw, + "band=%u, channel=%u, bw=%u, primary=%u.%u, center=%u.%u, sx_index=%u\n", + cl_hw->conf->ci_band_num, channel, bw, GET_FREQ_INT(primary), + GET_FREQ_FRAC(primary), GET_FREQ_INT(center), GET_FREQ_FRAC(center), + cl_hw->tcv_idx); + + return res; +} + +int _cl_msg_tx_set_channel(struct cl_hw *cl_hw, u32 channel, u8 bw, u32 primary, + u32 center, u8 mode) +{ + int res = 0; + u32 primary_q2 = FREQ_TO_Q2(primary); + u32 center_q2 = FREQ_TO_Q2(center); + + /* + * Need to take mutex lock to ensure that no one touching the phy_data + * DMA before FW is reading all its values. + * The mutex is unlocked right after the iq_dcoc_data_info DMA is + * handled in cl_calib_handle_set_channel_cfm. + */ + res = mutex_lock_interruptible(&cl_hw->set_channel_mutex); + + if (res != 0) { + cl_dbg_verbose(cl_hw, "Error - mutex_lock_interruptible (%d)\n", res); + return res; + } + + cl_hw->channel = channel; + cl_hw->bw = bw; + cl_hw->primary_freq = primary; + cl_hw->center_freq = center; + + if (mode & SET_CHANNEL_MODE_CALIB) + cl_hw->msg_calib_timeout = true; + + res = __cl_msg_tx_set_channel(cl_hw, channel, bw, primary_q2, center_q2, mode); + + if (mode & SET_CHANNEL_MODE_CALIB) { + cl_hw->msg_calib_timeout = false; + + if (!res) + res = cl_calib_handle_cfm(cl_hw, mode); + } + + mutex_unlock(&cl_hw->set_channel_mutex); + + return res; +} + +int cl_msg_tx_set_channel(struct cl_hw *cl_hw, u32 channel, u8 bw, u32 primary, u32 center) +{ + if (cl_calib_is_needed(cl_hw, channel, bw)) + return cl_calib_set_channel(cl_hw, channel, bw, primary, center); + else + return _cl_msg_tx_set_channel(cl_hw, channel, bw, primary, center, + SET_CHANNEL_MODE_OPERETIONAL); +} + +int cl_msg_tx_dtim(struct cl_hw *cl_hw, u8 dtim_period) +{ + struct mm_set_dtim_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_DTIM_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->dtim_period = dtim_period; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_beacon_int(struct cl_hw *cl_hw, u16 beacon_int, u8 vif_idx) +{ + struct mm_set_beacon_int_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_BEACON_INT_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->beacon_int = cpu_to_le16(beacon_int); + req->inst_nbr = vif_idx; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_basic_rates(struct cl_hw *cl_hw, u32 basic_rates) +{ + struct mm_set_basic_rates_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_BASIC_RATES_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->rates = cpu_to_le32(basic_rates); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_bssid(struct cl_hw *cl_hw, const u8 *bssid, u8 vif_idx) +{ + struct mm_set_bssid_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_BSSID_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + cl_mac_addr_copy(req->bssid.array, bssid); + req->inst_nbr = vif_idx; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_edca(struct cl_hw *cl_hw, u8 hw_queue, u32 param, + struct ieee80211_he_mu_edca_param_ac_rec *mu_edca) +{ + struct mm_set_edca_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_EDCA_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->ac_param = cpu_to_le32(param); + req->hw_queue = hw_queue; + + if (mu_edca) { + req->mu_edca_aifsn = mu_edca->aifsn; + req->mu_edca_ecw_min_max = mu_edca->ecw_min_max; + req->mu_edca_timer = mu_edca->mu_edca_timer; + } + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_associated(struct cl_hw *cl_hw, + struct ieee80211_bss_conf *bss_conf) +{ + struct mm_set_associated_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_ASSOCIATED_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->aid = cpu_to_le16(bss_conf->aid); + + /* Multiple BSSID feature support */ + if (bss_conf->nontransmitted && bss_conf->assoc) { + u8 i = 0; + u8 mask_addr[ETH_ALEN] = {0}; + u32 bssid_hi_mask = 0; + u32 bssid_low_mask = 0; + + for (i = 0; i < ARRAY_SIZE(mask_addr); i++) + mask_addr[i] = (bss_conf->transmitter_bssid[i] ^ + bss_conf->bssid[i]); + cl_mac_addr_array_to_nxmac(mask_addr, &bssid_low_mask, + &bssid_hi_mask); + /* Set mask to allow the transmitter BSSID Rx reception */ + req->bssid_hi_mask = cpu_to_le32(bssid_hi_mask); + req->bssid_low_mask = cpu_to_le32(bssid_low_mask); + } + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_slottime(struct cl_hw *cl_hw, bool use_short_slot) +{ + struct mm_set_slottime_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_SLOTTIME_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->slottime = use_short_slot ? 9 : 20; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_idle(struct cl_hw *cl_hw, u8 idle) +{ + struct mm_set_idle_req *req; + + if (cl_fem_read_wiring_id(cl_hw->chip)) { + cl_dbg_err(cl_hw, "!!! Invalid wiring id [%u] !!! Aborting\n", + cl_hw->chip->fem.wiring_id); + return -EINVAL; + } + + /* + * Rearm last_tbtt_ind so that error message will + * not be printed in cl_irq_status_tbtt() + */ + if (!idle) + cl_hw->last_tbtt_irq = jiffies; + + req = cl_msg_zalloc(cl_hw, MM_SET_IDLE_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->hw_idle = idle; + + cl_dbg_info(cl_hw, "idle = %s\n", idle ? "True" : "False"); + + return cl_send_request(cl_hw, req); +} + +void cl_msg_tx_idle_async(struct cl_hw *cl_hw) +{ + cl_hw->idle_async_set = true; + cl_msg_tx_set_idle(cl_hw, MAC_IDLE_ASYNC); +} + +int cl_msg_tx_key_add(struct cl_hw *cl_hw, struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key_conf, + u8 cipher_suite) +{ + struct mm_key_add_req *req; + + req = cl_msg_zalloc(cl_hw, MM_KEY_ADD_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + if (sta) { + /* Pairwise key */ + req->sta_idx = ((struct cl_sta *)sta->drv_priv)->sta_idx; + } else { + /* Default key */ + req->sta_idx = 0xFF; + req->key_idx = (u8)(key_conf->keyidx); /* Only useful for default keys */ + } + + req->inst_nbr = ((struct cl_vif *)vif->drv_priv)->vif_index; + req->key.length = key_conf->keylen; + + /* TODO: check if this works well in Big endian platforms */ + memcpy(req->key.array, key_conf->key, key_conf->keylen); + + req->cipher_suite = cipher_suite; + req->spp = cl_hw->conf->ci_spp_ksr_value; + + cl_dbg_info(cl_hw, "sta_idx:%u, key_idx:%u, inst_nbr:%u, cipher:%u, key_len:%u, spp:%u\n", + req->sta_idx, req->key_idx, req->inst_nbr, + req->cipher_suite, req->key.length, req->spp); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_key_del(struct cl_hw *cl_hw, u8 hw_key_idx) +{ + struct mm_key_del_req *req; + + req = cl_msg_zalloc(cl_hw, MM_KEY_DEL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->hw_key_idx = hw_key_idx; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_ba_add(struct cl_hw *cl_hw, u8 type, u8 sta_idx, + u16 tid, u16 bufsz, u16 ssn) +{ + struct mm_ba_add_req *req; + u16 msg_id = ((type == BA_AGMT_TX) ? MM_BA_ADD_TX_REQ : MM_BA_ADD_RX_REQ); + + req = cl_msg_zalloc(cl_hw, msg_id, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->type = type; + req->sta_idx = sta_idx; + req->tid = (u8)tid; + req->bufsz = cpu_to_le16(bufsz); + req->ssn = cpu_to_le16(ssn); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_ba_del(struct cl_hw *cl_hw, u8 sta_idx, u16 tid) +{ + struct mm_ba_del_req *req; + + req = cl_msg_zalloc(cl_hw, MM_BA_DEL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = sta_idx; + req->tid = (u8)tid; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_phy_reset(struct cl_hw *cl_hw) +{ + struct mm_phy_reset_req *req; + + req = cl_msg_zalloc(cl_hw, MM_PHY_RESET_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_available_ba_txq(struct cl_hw *cl_hw, u8 sta_idx, u16 tid) +{ + struct mm_available_ba_txq_req *req; + + req = cl_msg_zalloc(cl_hw, MM_AVAILABLE_BA_TXQ_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = sta_idx; + req->tid = (u8)tid; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_update_rate_dl(struct cl_hw *cl_hw, u8 sta_idx, u32 rate, u32 rate_fallback, + u8 req_bw_tx, u8 op_mode, u8 ltf, u8 ltf_fallback, u32 rate_he) +{ + struct mm_update_rate_dl_req *req; + + cl_dbg_info(cl_hw, "sta_idx=%u, rate=0x%x, rate_fallback=0x%x, req_bw_tx=%u, " + "op_mode=%u, ltf=%u, ltf_fallback=%u, rate_he=0x%x\n", + sta_idx, rate, rate_fallback, req_bw_tx, op_mode, + ltf, ltf_fallback, rate_he); + + req = cl_msg_zalloc(cl_hw, MM_UPDATE_RATE_DL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + /* Populate tx_params */ + req->tx_params.rate = cpu_to_le32(rate); + req->tx_params.rate_he = cpu_to_le32(rate_he); + req->tx_params.req_bw_tx = req_bw_tx; + req->tx_params.ant_set = CL_DEF_ANT_BITMAP; + req->tx_params.ltf = ltf; + + req->op_mode = op_mode; + req->sta_idx = sta_idx; + req->rate_fallback = cpu_to_le32(rate_fallback); + req->ltf_fallback = ltf_fallback; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_vns(struct cl_hw *cl_hw, u8 sta_idx, u8 is_vns) +{ + struct mm_set_vns_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_VNS_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = sta_idx; + req->is_vns = is_vns; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_tx_bf(struct cl_hw *cl_hw, u8 sta_idx, u8 is_on, u8 is_on_fallback) +{ + struct mm_set_tx_bf_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_TX_BF_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = sta_idx; + req->is_on = is_on; + req->is_on_fallback = is_on_fallback; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_sounding(struct cl_hw *cl_hw, + struct mm_sounding_req *sounding_req) +{ + struct mm_sounding_req *req; + u8 i; + + req = cl_msg_zalloc(cl_hw, MM_SOUNDING_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + /* Populate mm_sounding_req */ + memcpy(req, sounding_req, sizeof(struct mm_sounding_req)); + + /* In case of non-TB HE SU/CQI, nc should be set to 0 */ + if (req->sounding_type == SOUNDING_TYPE_HE_CQI || + req->sounding_type == SOUNDING_TYPE_HE_SU) + for (i = 0; i < req->sta_num; i++) + req->info_per_sta[i].nc = 0; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_sounding_pairing(struct cl_hw *cl_hw, u8 sounding_id, u8 sounding_type, + u8 gid, u8 sta_idx) +{ + struct mm_sounding_pairing *req; + + req = cl_msg_zalloc(cl_hw, MM_SOUNDING_PAIRING_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sounding_type = sounding_type; + req->sta_idx = sta_idx; + req->gid = gid; + req->sounding_id = sounding_id; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_sounding_interval(struct cl_hw *cl_hw, u16 interval, u16 lifetime, + u8 sounding_type, u8 sta_idx) +{ + struct mm_sounding_interval_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SOUNDING_INTERVAL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->interval = cpu_to_le16(interval); + req->bfr_lifetime = cpu_to_le16(lifetime); + req->sounding_type = sounding_type; + req->sta_idx = sta_idx; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_config_cca(struct cl_hw *cl_hw, bool enable) +{ + struct mm_config_cca_req *req; + + req = cl_msg_zalloc(cl_hw, MM_CONFIG_CCA_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->enable = enable; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_dfs(struct cl_hw *cl_hw, bool enable, u8 standard, + u8 initial_gain, u8 agc_cd_th) +{ + struct mm_set_dfs_req *req; + + req = cl_msg_zalloc(cl_hw, MM_SET_DFS_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->enable = enable; + req->standard_fcc = (standard == CL_STANDARD_FCC) ? true : false; + req->initial_gain = initial_gain; + req->agc_cd_th = agc_cd_th; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_ant_bitmap(struct cl_hw *cl_hw, u8 bitmap) +{ + struct mm_set_ant_bitmap_req *req; + u8 num_antennas = hweight8(bitmap); + u8 bitmap_cck = 0; + + req = cl_msg_zalloc(cl_hw, MM_SET_ANT_BITMAP_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + if (cl_band_is_24g(cl_hw)) { + if (num_antennas > MAX_ANTENNAS_CCK) + bitmap_cck = copy_mask_bits(bitmap, MAX_ANTENNAS_CCK); + else + bitmap_cck = bitmap; + } + + cl_fill_ant_config(cl_hw, &req->ant_config, num_antennas, bitmap, bitmap_cck, bitmap_cck); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_ndp_tx_control(struct cl_hw *cl_hw, u8 chain_mask, u8 bw, u8 format, u8 num_ltf) +{ + struct mm_ndp_tx_control_req *req; + + req = cl_msg_zalloc(cl_hw, MM_NDP_TX_CONTROL_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->chain_mask = chain_mask; + req->bw = bw; + req->format = format; + req->num_ltf = num_ltf; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_reg_write(struct cl_hw *cl_hw, u32 address, u32 value, u32 mask) +{ + struct mm_reg_write_req *req; + + req = cl_msg_zalloc(cl_hw, MM_REG_WRITE_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->address = cpu_to_le32(address); + req->value = cpu_to_le32(value); + req->mask = cpu_to_le32(mask); + + cl_dbg_info(cl_hw, "address=0x%x, value=0x%x, mask=0x%x\n", address, value, mask); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_prot_mode(struct cl_hw *cl_hw, u8 log_nav_en, u8 mode, u8 rate_format, + u8 rate_mcs, u8 rate_pre_type) +{ + struct mm_prot_mode_req *req; + + req = cl_msg_zalloc(cl_hw, MM_PROT_MODE_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->log_nav_en = log_nav_en; + req->mode = mode; + req->rate_format = rate_format; + req->rate_mcs = rate_mcs; + req->rate_pre_type = rate_pre_type; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_goto_power_reduction(struct cl_hw *cl_hw, u8 mode) +{ + struct mm_goto_power_reduction_req *req; + + req = cl_msg_zalloc(cl_hw, MM_GOTO_POWER_REDUCTION_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->goto_power_reduction_mode = mode; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_backup_bcn_en(struct cl_hw *cl_hw, bool backup_bcn_en) +{ + struct mm_set_backup_bcn_en_req *req; + + req = cl_msg_zalloc(cl_hw, MM_BACKUP_BCN_EN_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->backup_bcn_en = backup_bcn_en; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_start_periodic_tx_time(struct cl_hw *cl_hw, u16 periodic_tx_time_off, + u16 periodic_tx_time_on) +{ + struct mm_start_periodic_tx_time_req *req; + + req = cl_msg_zalloc(cl_hw, MM_START_PERIODIC_TX_TIME_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->periodic_tx_time_off = cpu_to_le16(periodic_tx_time_off); + req->periodic_tx_time_on = cpu_to_le16(periodic_tx_time_on); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_anamon_read(struct cl_hw *cl_hw, u8 mode, u8 param1, u8 param2) +{ + struct mm_anamon_read_req *req; + + req = cl_msg_zalloc(cl_hw, MM_ANAMON_READ_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->mode = mode; + req->param1 = param1; + req->param2 = param2; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_refresh_power(struct cl_hw *cl_hw) +{ + void *void_param; + + /* MM_REFRESH_PWR_REQ has no parameter */ + void_param = cl_msg_zalloc(cl_hw, MM_REFRESH_PWR_REQ, TASK_MM, 0); + if (!void_param) + return -ENOMEM; + + return cl_send_request(cl_hw, void_param); +} + +int cl_msg_tx_set_ant_pwr_offset(struct cl_hw *cl_hw, s8 pwr_offset[MAX_ANTENNAS]) +{ + struct mm_set_ant_pwr_offset_req *req; + u8 i = 0; + + req = cl_msg_zalloc(cl_hw, MM_SET_ANT_PWR_OFFSET_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(req->pwr_offset); i++) { + pwr_offset[i] = cl_power_offset_check_margin(cl_hw, cl_hw->bw, i, pwr_offset[i]); + req->pwr_offset[i] = cl_convert_signed_to_reg_value(pwr_offset[i]); + } + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_rate_fallback(struct cl_hw *cl_hw) +{ + struct mm_rate_fallback_req *req; + u8 *fb_conf = cl_hw->conf->ci_rate_fallback; + + req = cl_msg_zalloc(cl_hw, MM_SET_RATE_FALLBACK_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->fallback_count_su = fb_conf[CL_RATE_FALLBACK_COUNT_SU]; + req->fallback_count_mu = fb_conf[CL_RATE_FALLBACK_COUNT_MU]; + req->retry_count_thr = fb_conf[CL_RATE_FALLBACK_RETRY_COUNT_THR]; + req->ba_per_thr = fb_conf[CL_RATE_FALLBACK_BA_PER_THR]; + req->ba_not_received_thr = fb_conf[CL_RATE_FALLBACK_BA_NOT_RECEIVED_THR]; + req->disable_mcs0 = fb_conf[CL_RATE_FALLBACK_DISABLE_MCS]; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_twt_setup(struct cl_hw *cl_hw, struct mm_twt_setup_req *params) +{ + struct mm_twt_setup_req *req; + + req = cl_msg_zalloc(cl_hw, MM_TWT_SETUP_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = params->sta_idx; + req->twt_flow_id = params->twt_flow_id; + req->announced = params->announced; + req->triggered = params->triggered; + req->min_wake_duration_us = cpu_to_le32(params->min_wake_duration_us); + req->twt_interval_us = cpu_to_le64(params->twt_interval_us); + req->twt_start_time_tsf = cpu_to_le64(params->twt_start_time_tsf); + + cl_dbg_info(cl_hw, + "sta_idx %u, flow_id %u, interval_us %llu, min_wake_duration_us %u," + "start_time %llu, announced %u, triggered %u\n", + req->sta_idx, req->twt_flow_id, req->twt_interval_us, + req->min_wake_duration_us, req->twt_start_time_tsf, + req->announced, req->triggered); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_twt_teardown(struct cl_hw *cl_hw, struct mm_twt_teardown_req *params) +{ + struct mm_twt_teardown_req *req; + + req = cl_msg_zalloc(cl_hw, MM_TWT_TEARDOWN_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sta_idx = params->sta_idx; + req->twt_flow_id = params->twt_flow_id; + + cl_dbg_info(cl_hw, "sta_idx %u, flow_id %u\n", + req->sta_idx, req->twt_flow_id); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_rsrc_mgmt_traffic_event(struct cl_hw *cl_hw, u8 event_type, + enum cl_traffic_level level, + enum cl_traffic_direction direction, + u8 active_sta_cnt) +{ + struct mm_rsrc_mgmt_req *req = NULL; + struct cl_sta *cl_sta = NULL; + int curr_cnt = 0; + size_t size = sizeof(*req) + active_sta_cnt * sizeof(struct mm_rsrc_mgmt_active_sta); + + req = cl_msg_zalloc(cl_hw, MM_RSRC_MGMT_REQ, TASK_MM, size); + if (!req) + return -ENOMEM; + + req->subtype = event_type; + req->u.traffic_event.level = level; + req->u.traffic_event.direction = direction; + + cl_sta_lock_bh(cl_hw); + list_for_each_entry(cl_sta, &cl_hw->cl_sta_db.head, list) { + struct cl_wrs_rate *max_rate_cap = &cl_sta->wrs_sta.max_rate_cap; + struct cl_wrs_tx_params *su_tx_params = &cl_sta->wrs_sta.su_params.tx_params; + + if (!cl_sta->traffic_db[direction].activity_db[level].is_active) + continue; + + if (req->u.traffic_event.active_sta.cnt == active_sta_cnt) { + WARN_ONCE(active_sta_cnt != 0, + "Synchronization failure between actual and " + "preallocated station entities!"); + break; + } + + req->u.traffic_event.active_sta.list[curr_cnt] = (struct mm_rsrc_mgmt_active_sta) { + .idx = cl_sta->sta_idx, + .su_rate = { + .bw = su_tx_params->bw, + .nss = su_tx_params->nss, + .mcs = su_tx_params->mcs + }, + .max_rate = { + .bw = max_rate_cap->bw, + .nss = max_rate_cap->nss, + .mcs = max_rate_cap->mcs + }, + }; + + curr_cnt++; + } + req->u.traffic_event.active_sta.cnt = curr_cnt; + cl_sta_unlock_bh(cl_hw); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_rsrc_mgmt_rates_event(struct cl_hw *cl_hw, u8 event_type, + struct cl_sta *cl_sta) +{ + struct mm_rsrc_mgmt_req *req = NULL; + struct cl_wrs_rate *max_rate_cap = &cl_sta->wrs_sta.max_rate_cap; + struct cl_wrs_tx_params *su_tx_params = &cl_sta->wrs_sta.su_params.tx_params; + + req = cl_msg_zalloc(cl_hw, MM_RSRC_MGMT_REQ, TASK_MM, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->subtype = event_type; + req->u.rate_event.sta = (struct mm_rsrc_mgmt_active_sta) { + .idx = cl_sta->sta_idx, + .su_rate = { + .bw = su_tx_params->bw, + .nss = su_tx_params->nss, + .mcs = su_tx_params->mcs + }, + .max_rate = { + .bw = max_rate_cap->bw, + .nss = max_rate_cap->nss, + .mcs = max_rate_cap->mcs + }, + }; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_set_freq_offset(struct cl_hw *cl_hw, u16 val) +{ + struct mm_set_freq_offset_req *req; + + /* Build the MM_SET_FREQ_OFFSET_REQ message */ + req = cl_msg_zalloc(cl_hw, MM_SET_FREQ_OFFSET_REQ, TASK_MM, + sizeof(struct mm_set_freq_offset_req)); + + if (!req) + return -ENOMEM; + + /* Set parameters for the MM_SET_FREQ_OFFSET_REQ message */ + req->val = cpu_to_le16(val); + + /* Send the MM_SET_FREQ_OFFSET_REQ message to firmware */ + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_mod_filter(struct cl_hw *cl_hw, u32 filter) +{ + struct dbg_set_mod_filter_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_SET_MOD_FILTER_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->mod_filter = cpu_to_le32(filter); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_ce_mod_filter(struct cl_hw *cl_hw, u32 filter) +{ + struct dbg_set_mod_filter_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_CE_SET_MOD_FILTER_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->mod_filter = cpu_to_le32(filter); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_sev_filter(struct cl_hw *cl_hw, u32 filter) +{ + struct dbg_set_sev_filter_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_SET_SEV_FILTER_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->sev_filter = cpu_to_le32(filter); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_beamforming_tx(struct cl_hw *cl_hw, u32 param32) +{ + struct dbg_beamforming_tx_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_BEAMFORMING_TX_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->bf_cmd = cpu_to_le32(param32); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_get_e2w_stats(struct cl_hw *cl_hw, bool clear) +{ + struct dbg_e2w_stats_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_GET_E2W_STATS_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->clear = cpu_to_le32(clear); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_la_mpif_mask(struct cl_hw *cl_hw, u32 mask) +{ + struct dbg_set_la_mpif_mask_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_SET_LA_MPIF_MASK_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->mpif_mask = cpu_to_le32(mask); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_la_trig_point(struct cl_hw *cl_hw, u32 trigger_point) +{ + struct dbg_set_la_trig_point_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_SET_LA_TRIG_POINT_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->trigger_point = cpu_to_le32(trigger_point); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_la_mpif_debug_mode(struct cl_hw *cl_hw, u8 mode) +{ + struct dbg_set_la_mpif_debug_mode_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_SET_LA_MPIF_DEBUG_MODE_REQ, TASK_DBG, + sizeof(*req)); + if (!req) + return -ENOMEM; + + req->mode = mode; + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_set_la_trig_rule(struct cl_hw *cl_hw, u8 idx, bool enable, u32 address, + u8 oper, u32 value, u32 mask, u32 duration) +{ + struct dbg_set_la_trig_rule_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_SET_LA_TRIG_RULE_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->rule_id = idx; + req->oper = oper; + req->enable = enable; + req->address = cpu_to_le32(address); + req->value = cpu_to_le32(value); + req->mask = cpu_to_le32(mask); + req->duration = cpu_to_le32(duration); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_tx_trace_debug_flag(struct cl_hw *cl_hw, u32 bitmap, u8 w_r_cmd) +{ + struct dbg_tx_trace_debug_flag_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_TX_TRACE_DEBUG_FLAG_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->read_write_flag = w_r_cmd; + req->bitmap = cpu_to_le32(bitmap); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_print_stats(struct cl_hw *cl_hw, u32 command, + u32 param0, u32 param1, u32 param2, u32 param3) +{ + struct dbg_print_stats_req *req; + + req = cl_msg_zalloc(cl_hw, DBG_PRINT_STATS_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->command = cpu_to_le32(command); + req->param[0] = cpu_to_le32(param0); + req->param[1] = cpu_to_le32(param1); + req->param[2] = cpu_to_le32(param2); + req->param[3] = cpu_to_le32(param3); + + cl_dbg_verbose(cl_hw, "param0 = 0x%x, param1 = 0x%x, param2 = 0x%x, param3 = 0x%x\n", + req->param[0], req->param[1], req->param[2], req->param[3]); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_trigger(struct cl_hw *cl_hw, char *msg) +{ + struct dbg_trigger_req *req; + u8 msg_len = min(strlen(msg), sizeof(req->error) - 1); + + req = cl_msg_zalloc(cl_hw, DBG_TRIGGER_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + strncpy(req->error, msg, msg_len); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_test_mode(struct cl_hw *cl_hw, u32 *params) +{ + struct dbg_test_mode_req *req; + int i = 0; + + req = cl_msg_zalloc(cl_hw, DBG_TEST_MODE_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + req->command = cpu_to_le32(params[0]); + + /* Param[0] is the command, therefore start from param[i + 1] */ + for (i = 0; i < ARRAY_SIZE(req->params); i++) + req->params[i] = cpu_to_le32(params[i + 1]); + + return cl_send_request(cl_hw, req); +} + +int cl_msg_tx_dbg_sounding_cmd(struct cl_hw *cl_hw, struct dbg_sounding_cmd_param *params) +{ + struct dbg_sounding_cmd_param *req; + int i; + + req = cl_msg_zalloc(cl_hw, DBG_SOUNDING_CMD_REQ, TASK_DBG, sizeof(*req)); + if (!req) + return -ENOMEM; + + memcpy(req, params, sizeof(struct dbg_sounding_cmd_param)); + req->sounding_cmd_index = cpu_to_le32(params->sounding_cmd_index); + + for (i = 0; i < ARRAY_SIZE(req->param); i++) + req->param[i] = cpu_to_le32(params->param[i]); + + return cl_send_request(cl_hw, req); +} From patchwork Thu Jun 17 15:59:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE595C49361 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 099/256] cl8k: add hw.h Date: Thu, 17 Jun 2021 15:59:46 +0000 Message-Id: <20210617160223.160998-100-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:22 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: debbfd1a-92ab-48c9-2d50-08d931a992e9 X-MS-TrafficTypeDiagnostic: AM9P192MB0887: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:792; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W8alwTrzAmVJ2Md1n7a1+LkhWQUuxUXZ0I4eh7ADc56+Hx+kUVaDv617MiFcRt3gs5TLGvMTXq2EXHYinNFuGceZlD5ZSHzlmWTx61yGdWv90+RIqjRAyyBkwj42v/0wqDHlYH76wASRPHFwO8y19Qo0WuUiU52LeWyaHVgVz1UEZJ6/m3Jdr4ZWsf2Zt2eYoAy9dtZmhqCFqPNuSGfD6CGbzjwKyp6bYeLXZp86cneZ/gsaNyEA5eraSm4YFJA07lQjMXU6a6e/bfak16ziEk6BwX9GVmR6BfuP0bx2iCKF60KsZwZmvAdzkVX+6RkKMJhAVqh0Ydt+0kaqGC4mdqQUbN/rMEQ8JN+5abtGFs7Rz4u92E4vHf3gTpQ8teCVrjpBx+dkFIG30hRVcc7PM1S/tztW9KVwM4J8nDfG2B/b8G53PVMzYL1/acdBmyNXj2xeCJsqOs6lXvfutkjzwuram9VX6In8dACRyW6WXndHNJdGDmE+IoQ0anj02QoQWQEEiI30lqERqPY++KTI+F9zynNO8K5fL9T+yZJFzQjzPUK9Pfbmy6U8aRsH1u1ILsKz4pBbIjMuFJyETkD+7EA9+4/4u1byoE8RtyeAOU58De8eAcLF2MNzVk2ROfJn2VwptOHYrCRSDU+PN9YGOZyGVJtYPL3TEm56SddxTL5oQq/XmClQ021TCaRovEA9DvSHkvi8Bd9z5ec13ei19g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(396003)(366004)(39850400004)(136003)(346002)(83380400001)(6666004)(38350700002)(4326008)(186003)(16526019)(5660300002)(54906003)(6506007)(26005)(55236004)(38100700002)(316002)(1076003)(107886003)(30864003)(52116002)(8936002)(508600001)(66476007)(66946007)(66556008)(36756003)(6916009)(6486002)(86362001)(2616005)(956004)(2906002)(8676002)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9FGft5+QP+AuMS1YmhEcmhfSxtXPIHJ7Q4Cxs1w/GAzfiYWOgvD1qsKXyENGZuVFOxEZV5SHHWPk/8o9KafuQmyxbQlMUz9ouWKbvtwjV2vTq6Es1TebX3LvQJqZhVazFjsMMoJbyXJupU9+Ti7zedc0W4dXuB785qBl6aBTLQ3jrSz2BttTIDzRZmTGSdL4HdEQ5AHwKWgrNKuIZSo2lG4IdwMnmAfNGFslyMsawdOJugdZU3mcVkCb/An0XUbdA+WcdfWnKs5EZAUhlqVrraakHFY13WKJCEgJLLAEeZmwt2v6IVxqx4j9LmEHEkMYqV7LbNg9iAejahX1KOngo3xQAUp8sLO5LkpwsbzgF/BqktsXpq0yq26IUR/v+/D6f956fP4QQZoL/GSa2C/qv/0ef4NQbZmmthGHqs5pzRFSnHt53pl9jlCToTt35XQiQPqFyFc6CLtkS2yAKNISHGuxC6AQ0QkeliVpSoTUefouyeApfNG9t8FYGFlpIOP9r+8eFUw2jSX2NladwFvLiPQv/APts24I53HfDjRBvLnFTgXJe/AwJp5CzMkUH6T/xH4gWp4yg5XAz9UBkDTj6TtbRzFfBEMvxLIlFhdW7FodsUejtmAsXlm5CXlMzFGpjzh5kYz9CUifAgxugugthVManVxhw0jyp5gmwbQCcilYAIkHsMo2e8s5IdLTi5dsHKS9A6z1wSY33986xrhvd2abMMr3jRKVHPBrdu3ZM8Sp7fkP480ayCBQrcJUxB1yqihUmJRjxpH4EkW1ML8Iyg6YAVroTHjV4MR6sEnNLyr9XbufAWg9+t3/A5WwSTviU2A8QpbYKX4YapNT1M4NtVLGGiTBeqsoXaN1Q5RxN5NaxR9bsgzkKb94b0gJP7a6rxCAJj93fBIY6E+PgEzL46YyE0J/Kav4LchLFK2Dj3qgIp2q92cxgDNRI8v18mtCLxWygEcEglk60wtDyv/4P3giwmv0W5ICqFlyAkvAiu6+BkMxW5SGYaGK8HcCSFVpcaCHNnNCwLCrEsKRIJMVR7xEcqRoxINz6YCRFAroJEDG3zhGJ1CiwejYXE1CgFnn+JoNMcj2ZkNmMGc9AgxgDZ75NDarkgH1Oj45AwQITKPUR3hvwjB7uBW30CAVvQoGeZLHnk4ZW4k2hjukbA5Dytm92bDLyIemIDH/E3va9ASKC7pLIEuatNw+3PGcIBmhy29IF8UmTyjsca2HJCPGmniJR1gZWtXvtpsPU+yTr5dH6e/5JnQJxYupSpRjAg4/gknzQpIANSQzU51OvFUjzYe/KJ7g0Lw3du47gnXXPthiOWvmAMVUwRzWy2ycnwJ8 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: debbfd1a-92ab-48c9-2d50-08d931a992e9 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:23.6203 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3ORoGdU8R7fe+fmeejr+GEj7/+Xg/joNSdGwGkF+jfxFiRtxveUe8GPlrikIokpPKnj8phkhpAXqhvlnhQnTFg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0887 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/hw.h | 797 ++++++++++++++++++++++++++ 1 file changed, 797 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/hw.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/hw.h b/drivers/net/wireless/celeno/cl8k/hw.h new file mode 100644 index 000000000000..17f8f14b9891 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/hw.h @@ -0,0 +1,797 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_HW_H +#define CL_HW_H + +#include "wrs/wrs_db.h" +#include "traffic.h" +#include "edca.h" +#include "env_det.h" +#include "temperature.h" +#include "dfs/dfs_db.h" +#include "chan_info.h" +#include "calib.h" +#include "debugfs_defs.h" +#include "ipc_shared.h" +#include "fw/fw_msg.h" +#include "dfs/radar.h" +#include "rate_ctrl.h" +#include "power_table.h" +#include "cca.h" +#include "def.h" +#include "noise.h" +#include "mac80211.h" +#include "tcv_config.h" +#include "sounding.h" +#include "rsrc_mgmt.h" +#include "channel.h" +#include +#include + +/* Max flags for driver status description is defined as 32 * MAX_CFM_FLAGS */ +#define MAX_CFM_FLAGS 2 + +enum cl_radio_stats { + CL_RADIO_FCS_ERROR = 0, + CL_RADIO_PHY_ERROR, + CL_RADIO_RX_FIFO_OVERFLOW, + CL_RADIO_ADDRESS_MISMATCH, + CL_RADIO_UNDEFINED_ERROR, + CL_RADIO_ERRORS_MAX +}; + +struct cl_rx_path_info { + u32 rx_desc[CL_RX_BUF_MAX]; + u32 elem_alloc_fail; + u32 skb_null; + u32 pkt_drop_amsdu_corrupted; + u32 pkt_drop_sub_amsdu_corrupted; + u32 pkt_drop_amsdu_len_error; + u32 pkt_drop_sub_amsdu_len_error; + u32 pkt_drop_wrong_pattern; + u32 pkt_drop_not_success; + u32 pkt_drop_unencrypted; + u32 pkt_drop_decrypt_fail; + u32 pkt_drop_rxhdr_len_error; + u32 pkt_drop_sta_null; + u32 pkt_drop_host_limit; + u32 netif_rx; + u32 remote_cpu[CPU_MAX_NUM]; + u32 exceed_pkt_budget; + u32 pkt_handle_bucket_rxm[IPC_RXBUF_NUM_BUCKETS_RXM]; + u32 pkt_handle_bucket_fw[IPC_RXBUF_NUM_BUCKETS_FW]; + u32 amsdu_cnt[RX_MAX_MSDU_IN_AMSDU]; + u32 non_amsdu; + u32 buffer_process_irq; + u32 buffer_process_tasklet; +}; + +/* Structure used to store information regarding E2A msg buffers in the driver */ +struct cl_e2a_msg_elem { + struct cl_ipc_e2a_msg *msgbuf_ptr; + dma_addr_t dma_addr; +}; + +/* Structure used to store information regarding Debug msg buffers in the driver */ +struct cl_dbg_elem { + struct cl_ipc_dbg_msg *dbgbuf_ptr; + dma_addr_t dma_addr; +}; + +struct cl_tx_power_info { + s8 power; + s8 offset; + s8 temperature; +}; + +struct cl_rx_elem { + int passed; + struct sk_buff *skb; + dma_addr_t dma_addr; +}; + +struct cl_dbg_info { + struct mutex mutex; + struct dbg_info *buf; + dma_addr_t dma_addr; + int bufsz; + struct timespec64 trigger_tstamp; +}; + +struct cl_dbg_data { + char *str; /* Pointer to debug strings start address */ + int size; /* Size of debug strings pool */ +}; + +struct cl_phy_data_info { + struct cl_phy_data *data; + u32 dma_addr; +}; + +struct cl_sec_phy_chan { + u16 prim20_freq; + u16 center_freq1; + u16 center_freq2; + enum nl80211_band band; + u8 type; +}; + +struct cl_amsdu_rx_state { + u8 msdu_cnt; + u8 msdu_remaining_cnt; + /* + * MSDU padding - all MSDU pkt within A-MSDU are 4byte aligned (this + * value holds the alignment value) + * According to ieee80211 spec all MSDU share the same alignment + */ + u8 msdu_dma_align; + u8 amsdu_error; + u8 encrypt_len; + u8 sta_idx; + u8 tid; + u32 packet_len; + struct hw_rxhdr *rxhdr; + struct sk_buff *first_skb; + struct sk_buff_head frames; +}; + +struct cl_tx_queue { + struct list_head sched_list; + struct list_head hdrs; + struct cl_sta *cl_sta; + bool sched; + u16 fw_free_space; + u16 fw_max_size; + u8 type; + u8 tid; + u8 hw_index; + u16 index; + u16 max_packets; + u16 num_packets; + u32 total_packets; + u32 total_fw_push_desc; + u32 total_fw_push_skb; + u32 total_fw_cfm; + u32 dump_queue_full; + u32 dump_dma_map_fail; + u32 stats_hw_amsdu_cnt[CL_AMSDU_TX_PAYLOAD_MAX]; + u32 stats_sw_amsdu_cnt[MAX_TX_SW_AMSDU_PACKET]; +}; + +struct cl_req_agg_db { + bool is_used; + u8 sta_idx; + u8 tid; +}; + +/* + * struct cl_tx_queues: + * This structure holds all driver TX queues, + * The queues buffer frames pushed by upper layer and push them to lower IPC layer. + */ +struct cl_tx_queues { + struct cl_tx_queue agg[IPC_MAX_BA_SESSIONS]; + struct cl_tx_queue single[MAX_SINGLE_QUEUES]; + struct cl_tx_queue bcmc; +}; + +struct cl_prot_mode { + u8 current_val; + u8 default_val; + u8 dynamic_val; +}; + +struct mac_entry { + struct cl_hw *cl_hw; + struct list_head list; + time64_t kt_sec; + u8 addr[ETH_ALEN]; + u8 state; + bool assoc_flag; + unsigned long allow_time; + spinlock_t entry_lock; + struct cl_timer timer; + struct cl_timer allow_timer; + struct work_struct cross_allow_time_work; +}; + +struct mac_drv { + struct mac_entry mac; + u16 list_size; +}; + +struct cl_hw_asserts_info { + + /* Timestamp (jiffies) of the last CL_MIN_ASSERT_CNT hw assert. */ + unsigned long timestamp[CL_MIN_ASSERT_CNT]; + /* Hw assert index. */ + u8 index; + /* Indicate if hw_restart was schedule */ + u8 restart_sched; + /* Indicate if hw_restart is needed due to unrecoverable assert. */ + u8 restart_needed; +}; + +struct cl_ate_db { + bool active; + s8 tx_power; + s8 tx_power_offset[MAX_ANTENNAS]; + u8 ant_mask; + u8 mode; + u8 bw; + u8 nss; + u8 mcs; + u8 gi; + u8 ltf; + struct ate_stats stats; +}; + +struct cl_agg_cfm_queue { + struct list_head head; + struct cl_tx_queue *tx_queue; + u16 ssn; +}; + +struct cl_single_cfm_queue { + struct list_head head; +}; + +struct cl_assoc_queue { + struct list_head list; + spinlock_t lock; +}; + +struct cl_agc_cd { + /* Configuration */ + u32 period; + bool debug; + /* Internal parameters */ + bool is_on; + bool use_hystersis; + u32 maintenance; +}; + +struct cl_dyn_mcast_rate { + u8 wrs_mode_default; + u8 wrs_mode_curr; +}; + +struct cl_dyn_bcast_rate { + u8 sta_min_mcs; + u8 bcast_mcs; + u8 wrs_mode; + u8 ltf; +}; + +struct cl_power_db { + u8 curr_percentage; + s8 curr_offset; + /* Used to validate margins of MAC power */ + s8 bw_factor_q2[CHNL_BW_MAX]; + s8 ant_factor_q2[MAX_ANTENNAS]; +}; + +struct cl_bf_db { + bool force; + enum cl_dbg_level dbg_level; +}; + +struct cl_vns_rssi_entry { + struct list_head list_all; + struct list_head list_addr; + unsigned long timestamp; + s8 strongset_rssi; + u8 addr[ETH_ALEN]; +}; + +#define STA_HASH_SIZE 256 + +struct cl_vns_mgmt_db { + u32 num_entries; + struct list_head list_all; + struct list_head list_addr[STA_HASH_SIZE]; +}; + +struct cl_vns_db { + bool enable; + bool dbg; + bool dbg_per_packet; + u16 interval_period; + spinlock_t lock; + struct cl_vns_mgmt_db mgmt_db; +}; + +/* Cl_dbgfile.c - offload data */ +struct cl_str_offload_env { + char *block1; + u32 size1; + u32 base1; + char *block2; + u32 size2; + u32 base2; + char *block3; + u32 size3; + u32 base3; + bool enabled; + char buf[512]; +}; + +struct cl_dma_accessed { + void *drv_v_addr; + u32 size; + u32 fw_v_addr; + u32 dma_addr; +}; + +struct cl_radar_queue { + struct list_head head; + spinlock_t lock; +}; + +struct cl_recovery_db { + unsigned long last_restart; + u32 restart_cnt; + + u32 ela_en; + u32 ela_sel_a; + u32 ela_sel_b; + u32 ela_sel_c; + + bool in_recovery; +}; + +struct cl_noise_reg { + struct list_head list; + u32 np_prim20_per_ant; + u32 np_prim20_per_ant2; + u32 nasp_prim20_per_ant; + u32 nasp_prim20_per_ant2; + u32 np_sub20_per_chn; + u32 np_sub20_per_chn2; + u32 nasp_sub20_per_chn; + u32 nasp_sub20_per_chn2; + u32 np_sec20_dens_per_ant; + u32 nasp_sec20_dens_per_ant; +}; + +struct cl_noise_db { + struct list_head reg_list; + bool hist_record; + u8 active_ant; + u8 sample_cnt; +}; + +struct cl_chan_info { + u8 channel; + u8 max_bw; + /* Resolution of 0.25dB */ + u8 max_power_q2; /* MIN(country_max_power_q2, hardware_max_power_q2) */ + u8 country_max_power_q2; + u8 hardware_max_power_q2; +}; + +struct cl_channel_info { + bool use_channel_info; + struct cl_chan_info channels[CHNL_BW_MAX][MAX_CHANNELS]; + enum cl_reg_standard standard; + struct ieee80211_regdomain *rd; +}; + +#define CL_STA_HASH_SIZE (CL_MAX_NUM_STA / 2) +#define CL_STA_HASH_MASK (CL_STA_HASH_SIZE - 1) +#define CL_STA_HASH_IDX(x) ((x) & CL_STA_HASH_MASK) + +struct cl_sta_db { + struct list_head head; + struct cl_sta *lut[CL_MAX_NUM_STA]; + struct list_head hash[CL_STA_HASH_SIZE]; + rwlock_t lock; + u32 num; +}; + +struct cl_tx_inject { + bool continuous; + bool is_running; + bool aggressive_edca; + u32 alloc_counter; + u32 current_counter; + u32 max_counter; + u32 packet_len; + struct cl_sta *cl_sta; + struct tasklet_struct tasklet; +}; + +#define CL_USER_PRIO_VALS 8 +#define CL_USER_DSCP_VALS 64 + +struct cl_vid_user { + u16 vid; + u8 user_prio; +}; + +struct cl_vlan_dhcp_params { + /* DSCP to user priority mapping */ + u8 dscp_to_up[CL_USER_DSCP_VALS]; + /* VLAN to user priority mapping */ + u8 vlan_to_up[CL_USER_PRIO_VALS]; + /* + * Vid-pbit to user priority mapping + * First index is the pbit. Second index is a running index 0 + */ + struct cl_vid_user vlan_pbit_to_up[CL_USER_PRIO_VALS][CL_USER_PRIO_VALS]; + /* 2 - "VLAN" VLAN based only, 3 - "DSCP" DSCP based only. Any other number - Automatic */ + u8 up_layer_based; + u8 default_vlan_up; +}; + +struct cl_vlan_dscp { + struct cl_vlan_dhcp_params vlan_dhcp_params[MAX_BSS_NUM]; + bool enable[MAX_BSS_NUM]; + bool debug; +}; + +struct cl_controller_reg { + u32 breset; + u32 debug_enable; + u32 dreset; + u32 ocd_halt_on_reset; + u32 run_stall; +}; + +struct cl_busytime_stats { + u32 rx_mine_time_us; + u32 tx_mine_time_us; + u32 edca_cca_busy_us; +}; + +#define CCA_MAX_SAMPLE 21 + +struct cl_edca_hist_db { + u16 air_util[CCA_MAX_SAMPLE]; + u16 wifi_air_util[CCA_MAX_SAMPLE]; + u16 not_mine_rx_wifi[CCA_MAX_SAMPLE]; + u16 mine[CCA_MAX_SAMPLE]; + u16 not_mine[CCA_MAX_SAMPLE]; + u16 non_wifi_util[CCA_MAX_SAMPLE]; + u16 not_mine_busy[CCA_MAX_SAMPLE]; + u16 sample_cnt; +}; + +struct cl_cca_db { + struct cl_edca_hist_db edca_hist; + unsigned long time; + u32 edca_busy; + u32 edca_busy_sec20; + u32 edca_busy_sec40; + u32 edca_busy_sec80; + u32 cca_busy_nav; + u32 cca_intra_bss_nav; + u32 cca_inter_bss_nav; + u32 tx_mine; + u32 rx_mine; + u32 print_tx_mine; + u32 print_rx_mine; + enum cl_cca_opt cca_opt; +}; + +struct cl_cpu_cntr { + u32 tx_agg[CPU_MAX_NUM]; + u32 tx_single[CPU_MAX_NUM]; +}; + +struct cl_tx_drop_cntr { + u32 wd_restart; + u32 radio_off; + u32 in_recovery; + u32 short_length; + u32 pending_full; + u32 packet_limit; + u32 dev_flags; + u32 tx_disable; + u32 length_limit; + u32 txhdr_alloc_fail; + u32 queue_null; + u32 amsdu_alloc_fail; + u32 amsdu_dma_map_err; + u32 build_hdr_fail; + u32 key_disable; + u32 queue_flush; + u32 sta_null_in_agg; +}; + +struct cl_tx_forward_cntr { + u32 tx_start; + u32 drv_fast_agg; + u32 drv_fast_single; + u32 to_mac; + u32 from_mac_single; + u32 from_mac_agg; +}; + +struct cl_tx_transfer_cntr { + u32 single_to_agg; + u32 agg_to_single; +}; + +struct cl_tx_packet_cntr { + struct cl_tx_forward_cntr forward; + struct cl_tx_drop_cntr drop; + struct cl_tx_transfer_cntr transfer; +}; + +struct cl_power_truncate { + u8 he[CHNL_BW_MAX][WRS_MCS_MAX_HE][PWR_TBL_HE_BF_SIZE]; + u8 ht_vht[CHNL_BW_MAX][WRS_MCS_MAX_VHT][PWR_TBL_VHT_BF_SIZE]; + u8 ofdm[WRS_MCS_MAX_OFDM]; + u8 cck[WRS_MCS_MAX_CCK]; +}; + +#define CL_TWT_MAX_SESSIONS 8 + +struct cl_twt_session_db { + struct cl_sta *cl_sta; + struct ieee80211_twt_individual_elem twt_setup; +}; + +struct cl_twt_db { + struct cl_twt_session_db cl_twt_sessions[CL_TWT_MAX_SESSIONS]; + u8 num_sessions; + u8 dialog_token; +}; + +struct cl_vif_db { + struct list_head head; + u8 num_iface_bcn; +}; + +enum cl_rx_stats_flag { + RX_STATS_CCK = 0x01, + RX_STATS_OFDM = 0x02, + RX_STATS_HT = 0x04, + RX_STATS_VHT = 0x08, + RX_STATS_HE_SU = 0x10, + RX_STATS_HE_MU = 0x20, + RX_STATS_HE_EXT = 0x40, + RX_STATS_HE_TRIG = 0x80, +}; + +struct cl_rx_stats { + u32 he_trig[CHNL_BW_MAX_HE][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE]; + u32 he_ext[CHNL_BW_MAX_HE][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE]; + u32 he_mu[CHNL_BW_MAX_HE][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE]; + u32 he_su[CHNL_BW_MAX_HE][WRS_SS_MAX][WRS_MCS_MAX_HE][WRS_GI_MAX_HE]; + u32 vht[CHNL_BW_MAX_VHT][WRS_SS_MAX][WRS_MCS_MAX_VHT][WRS_GI_MAX_VHT]; + u32 ht[CHNL_BW_MAX_HT][WRS_SS_MAX][WRS_MCS_MAX_HT][WRS_GI_MAX_HT]; + u32 ofdm[WRS_MCS_MAX_OFDM]; + u32 cck[WRS_MCS_MAX_CCK]; + u8 flag; +}; + +struct cl_fw_dbg { + char *buf; + int len; +}; + +struct cl_rx_trigger_based_stats { + bool enable; + u8 ampdu_cnt; + u16 data_per_agg; + u16 qos_null_per_agg; + u32 total; + u32 data[DBG_STATS_MAX_AGG_SIZE]; + u32 qos_null[TID_MAX + 2]; +}; + +enum cl_iface_conf { + CL_IFCONF_AP, + CL_IFCONF_STA, + CL_IFCONF_REPEATER, + CL_IFCONF_MESH_AP, + CL_IFCONF_MESH_ONLY, + + CL_IFCONF_MAX +}; + +struct cl_vendor_msg { + u8 *buf; + u16 len; + u16 offset; + bool in_process; +}; + +struct cl_driver_ops { + int (*msg_fw_send)(struct cl_hw *cl_hw, + const void *msg_params, + bool background); + void (*pkt_fw_send)(struct cl_hw *cl_hw, + struct cl_sw_txhdr *sw_txhdr, + struct cl_tx_queue *tx_queue); +}; + +struct cl_version_db { + u32 dsp; + u32 rfic_sw; + u32 rfic_hw; + u32 agcram; + char fw[CL_VERSION_STR_SIZE]; + char drv[CL_VERSION_STR_SIZE]; + unsigned long last_update; +}; + +struct cl_cached_fw { + void *data; + size_t size; +}; + +struct cl_hw { + u8 idx; /* Global index (0-3) */ + u8 tcv_idx; /* Transceiver index (0-1) */ + struct cl_tcv_conf *conf; + struct cl_chip *chip; + struct ieee80211_hw *hw; + const struct cl_driver_ops *drv_ops; + struct cl_vif_db vif_db; + struct cl_fw_dbg fw_dbg; + enum cl_iface_conf iface_conf; + u32 num_ap_started; + u8 tx_power_version; + struct cl_vif *mc_vif; + u8 bw; + u32 channel; + u32 primary_freq; + u32 center_freq; + enum nl80211_band nl_band; + u8 num_antennas; + u8 mask_num_antennas; + u8 first_ant; + u8 last_ant; + u8 max_antennas; + u8 max_mu_cnt; + struct cl_sta_db cl_sta_db; + struct cl_ipc_e2a_irq ipc_e2a_irq; + struct cl_controller_reg controller_reg; + struct ieee80211_supported_band sband; + void (*ipc_host2xmac_trigger_set)(struct cl_chip *chip, u32 value); + unsigned long drv_flags; + unsigned long tx_disable_flags; + struct cl_ipc_host_env *ipc_env; + spinlock_t tx_lock_agg; + spinlock_t tx_lock_cfm_agg; + spinlock_t tx_lock_single; + spinlock_t tx_lock_bcmc; + struct mutex msg_tx_mutex; + wait_queue_head_t wait_queue; /* Synchronize driver<-->firmware message exchanges */ + unsigned long cfm_flags[MAX_CFM_FLAGS]; + void *msg_cfm_params[MM_MAX + DBG_MAX]; /* Array of pointers per received msg CFM */ + bool msg_background; + wait_queue_head_t fw_sync_wq; + wait_queue_head_t radio_wait_queue; + struct cl_rx_elem *rx_elems; + struct cl_e2a_msg_elem *e2a_msg_elems; + struct cl_dbg_elem *dbg_elems; + struct cl_radar_elem *radar_elems; + struct dma_pool *txdesc_pool; + struct dma_pool *dbg_pool; + struct dma_pool *e2a_msg_pool; + struct dma_pool *radar_pool; + struct cl_dbg_info dbginfo; + struct cl_debugfs debugfs; + struct cl_hw_asserts_info assert_info; + char fw_prefix; /* Single character for fw prefix - l/u/s */ + u8 fw_dst_kern_id; /* Firmware destination (LMAC/SMAC) */ + bool fw_active; + bool fw_send_start; /* Did driver already send a start request message to firmware? */ + struct cl_tx_inject tx_inject; + bool chandef_set; + struct cl_dbg_data dbg_data; + bool set_calib; + struct cl_tx_power_info tx_pow_info[MAX_CHANNELS][MAX_ANTENNAS]; + struct cl_channel_info channel_info; + struct cl_phy_data_info phy_data_info; + u32 mask_hi; + u32 mask_low; + struct cl_timer maintenance_slow_timer; + struct cl_timer maintenance_fast_timer; + struct tasklet_struct tx_task; + struct list_head list_sched_q_agg; + struct list_head list_sched_q_single; + struct cl_ate_db ate_db; + struct cl_env_db env_db; + struct cl_req_agg_db req_agg_db[IPC_MAX_BA_SESSIONS]; + u8 req_agg_queues; + u8 used_agg_queues; + u16 max_agg_tx_q_size; + bool wd_restart_drv; + bool is_stop_context; + struct workqueue_struct *drv_workqueue; + struct cl_amsdu_rx_state amsdu_rx_state; + struct cl_tx_queues tx_queues; + struct kmem_cache *sw_txhdr_cache; + struct kmem_cache *amsdu_txhdr_cache; + u32 radio_stats[CL_RADIO_ERRORS_MAX]; + atomic_t tx_packet_count; + struct cl_rx_path_info rx_info; + struct cl_prot_mode prot_mode; + struct cl_agg_cfm_queue agg_cfm_queues[IPC_MAX_BA_SESSIONS]; + struct cl_single_cfm_queue single_cfm_queues[MAX_SINGLE_QUEUES]; + struct cl_single_cfm_queue bcmc_cfm_queue; + atomic_t radio_lock; + struct cl_assoc_queue assoc_queue; + struct cl_agc_cd agc_cd; + struct cl_wrs_db wrs_db; + struct cl_traffic_main traffic_db; + struct cl_rsrc_mgmt_db rsrc_mgmt_db; + struct cl_power_db power_db; + struct cl_bf_db bf_db; + struct cl_edca_db edca_db; + struct cl_vns_db vns_db; + struct cl_str_offload_env str_offload_env; + struct cl_dma_accessed fw_remote_rom; + struct cl_recovery_db recovery_db; + struct cl_radar_queue radar_queue; + struct tasklet_struct radar_tasklet; + struct cl_cached_fw cached_fw; + s8 rx_sensitivity[MAX_ANTENNAS]; + struct cl_cca_db cca_db; + struct cl_noise_db noise_db; + struct cl_temp_comp_db temp_comp_db; + struct cl_sounding_db sounding; + struct cl_dyn_mcast_rate dyn_mcast_rate; + struct cl_dyn_bcast_rate dyn_bcast_rate; + struct cl_dfs_db dfs_db; + struct cl_version_db version_db; + bool entry_fixed_rate; + struct cl_vlan_dscp vlan_dscp; + unsigned long last_tbtt_irq; + u32 tbtt_cnt; + u8 mesh_tbtt_div; + struct tasklet_struct tx_mesh_bcn_task; + u32 fw_recovery_cntr; + u32 rx_filter; + ptrdiff_t mac_hw_regs_offset; + ptrdiff_t phy_regs_offset; + struct sk_buff_head tx_remote_queue; + struct sk_buff_head rx_remote_queue_mac; + struct sk_buff_head rx_skb_queue; + struct tasklet_struct rx_tasklet; + struct tasklet_struct rx_resched_tasklet; + u8 fem_system_mode; + u8 fem_ant; + struct cl_tx_packet_cntr tx_packet_cntr; + struct cl_cpu_cntr cpu_cntr; + struct cl_iq_dcoc_data_info iq_dcoc_data_info; + struct cl_power_table_info power_table_info; + struct ieee80211_sband_iftype_data iftype_data[3]; + bool motion_sense_dbg; + struct cl_power_truncate pwr_trunc; + struct mutex set_channel_mutex; + u8 radio_status; + u8 rf_crystal_mhz; + bool calib_ready; + struct cl_twt_db twt_db; + struct mac_address addresses[MAX_BSS_NUM]; + struct cl_rx_stats *rx_stats; /* RX statistics for production mode. */ + spinlock_t lock_stats; + u16 n_addresses; + u8 txamsdu_en; + bool reg_dbg; + struct cl_rx_trigger_based_stats tb_stats; + bool idle_async_set; + struct cl_vendor_msg vendor_msg; + struct cl_timer vendor_timer; + bool msg_calib_timeout; + struct cl_calib_work *calib_work; +}; + +void cl_hw_init(struct cl_chip *chip, struct cl_hw *cl_hw, u8 tcv_idx); +void cl_hw_deinit(struct cl_hw *cl_hw, u8 tcv_idx); +void cl_hw_lock(struct cl_hw *cl_hw); +void cl_hw_unlock(struct cl_hw *cl_hw); +struct cl_hw *cl_hw_other_tcv(struct cl_hw *cl_hw); +bool cl_hw_is_tcv0(struct cl_hw *cl_hw); +bool cl_hw_is_tcv1(struct cl_hw *cl_hw); +int cl_hw_set_antennas(struct cl_hw *cl_hw); +u8 cl_hw_ant_shift(struct cl_hw *cl_hw); + +#endif /* CL_HW_H */ From patchwork Thu Jun 17 15:59:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08AD1C49EA4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 103/256] cl8k: add key.c Date: Thu, 17 Jun 2021 15:59:50 +0000 Message-Id: <20210617160223.160998-104-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:27 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d50d0b62-c35e-47d5-c5ac-08d931a995a4 X-MS-TrafficTypeDiagnostic: AM9P192MB0887: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LGvNm/dr9L5qccGwiUqVsPvdRCPKp4x4ASjPCOfFTJg6dwtMXpYZ+yJ0BMUxSl+C3UY4JLWPBsswXZE2DWj+pKqjd96uEr1xoZRRk9j6KSbi65SR5W7RQhnbWfvdpiVMDOLUbUT8ZGGXd8G3LFh7DZCy9UO2ZN+HHol4OLNSbN0D1FiQYIGVp0yu4xxGPbDawDMzpkW5I5SCBEJtxfXq2vb/s+ybpGlfJxh6fKMykbVPLQrHvI8NFBbaxn7GVwWyd/rJ3BP3/yBu3oE+4ZF2A4kUxZKurnu+8E28EmD+FDnP0bojbeXpFa2Ej7EaFModHkyBDxDHwYthk9WqH1/4bCPxdncWkZNrdC+sGUMoWB8MwDD26saC1CnzFOyogne014tAw6r1pAKRl5wMI4YrCj0liTfLVLz8ANMDWtxBjiLGfDkUg016ThbpmLXefjrHWnvFarqwnASoDGJ92HIn16HIkFym7ADycLAes+fApTICfPVorHjx1QX64lJ6LYvXk3p0erYg7B+nMoseyFBqs66HW6F13hGazQz8o1v2vtIExOYEFepoSfDGYlpTyMpFCbUfteszybfa3S+XnV5lABAJHM6eonR1Xs/aOP+av2+crJ2d22AaVRiiegfUKndYzXSNwBSBFWXTkaRu1t+2R2GTzIt7c4SsuNlu1n2Nk4wowsvcjULs6P0CFfcVpJ6ogYleSDy0XTc8xNwkOawDpg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(396003)(366004)(39850400004)(136003)(346002)(83380400001)(6666004)(38350700002)(4326008)(186003)(16526019)(5660300002)(54906003)(6506007)(26005)(55236004)(38100700002)(316002)(1076003)(107886003)(52116002)(8936002)(508600001)(66476007)(66946007)(66556008)(36756003)(6916009)(6486002)(86362001)(2616005)(956004)(2906002)(8676002)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: h//KKRFudclNsPTFZcTVuOeH0MsjAyXinfZsw544vDopgT6eTGBg+Vho4UbWmasR3LlSX/wza/PP3Z7skJxjbcEdPm3YA9GzrYPJdvqdKQY/U68anOlXyUi383olqE+RDGTFGxDZ4Id7z70NOfHqz7ae1qPPZiLGtrp9scBf7mmXFaDP9/NvWIi4ZWg8GwoVD47fyErsZIUbwPgkx8Owk2ntGMwUToLavQJ2p3QgeRAyYuN0GjFnLp+IRjBLWxP4khGp6qOXQ/HbRRQFzXaNDXuGQSlCcBc/JUyw4Swl1yZfKX8uf6Hr3V44Cc748XvabeNPFJ+HvUk3rUKmXbILG8k4MX0uOEW60dmM3PmmyGm7HjKsjpX4LCC47Eg5KDJi2JenUWLUaAtUDah9FnsyUi7JUDdcWQSXqAU0aOeCLn+vccALB2rkYHaZhdmhLPi6CyjgVZodZ4gVRvQhSAZtigKBElYg1hnKRIZoN5c9XQljUk5S91FIsaEU01/js6Kwo++HjFnPJqsS/QJKnNW4lfJ79BM8+dJLIYMTZXJ4QPooAKphVXT+Bbkqv0XPhgYDHtgzwGMtCulv4IyKOJrywqYgWuUkwcb01AfcZWj6oYDgGyXGQ9vzuo+TSC7jghedRg/3OCpTesbXnp55BaJKffu09AfVVBZTPSG/2MOHjA2Z+x5ACfpbcNRgJcVtwrq1EGJH70oYMVb2+aH8ogwAKEl1AXw+lp5l4JU7KRVg5r0eviORCetfzu3gOyMudtYhdAtFyYkpA5++TSaYBh+NZ7uVk7XeZ+HkKPEqzFDmDxwNE+Aj5+m/9hVsHBpcmymxTxIGbVvSsdOptMNoN0LYy5nF4hTtYUG72ifOxgpLkXhMzuVEKqXnKvaJ2JBrWY+/4GOKzKnGdmsAxboUnl5pEgtWwvaADNHRlFTDf5uD97UTaya2bXQsDo2ECP8CYwm/7XaSoSTjglSQiGTLmJQmv2eJ0LZ+gqwLyfksJVD8XRpbsXCKvxdrUXZPOHYdexWwfaLeiMs2p75vHnd7JYDwufh1brKjEzHsN3q3/9NxR21BOsZdPUzV3nPFPi/VQKDZAHQMvdVCyrNSuXeTNQJ5tV5VlL+EW8X9exfPRGkupEtskTxqpatMR36ekztY4dYUJtjMfKWN7mGvLuVcm4NeCPGrvhamcUKg6DkynqiIrCNeWJ/4UClexA5cObdgpzpey3XhUs/F6ZAZCCnjWsUVFL3PNb8GiDENjkYExJ4P2so2Mo2DdJRXsbdUZlIQRrPvwILS53fx5KyxfTSaNv/+Ii82XixZp1Y34vBZ04SalZyKI5V52nIKwOAJFEW9oUp/ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: d50d0b62-c35e-47d5-c5ac-08d931a995a4 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:28.1006 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: an8Van5D0PXptXOce+1UFGmOU3VUJwxYGI4WN+vv79pb/7rDJucCpx2vSEJsl+9eJBSlCg5ePhVtNwzj0QUR+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0887 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/key.c | 197 +++++++++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/key.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/key.c b/drivers/net/wireless/celeno/cl8k/key.c new file mode 100644 index 000000000000..276c2e76e126 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/key.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "key.h" +#include "fw/msg_tx.h" +#include "fw/fw_msg.h" +#include "sta.h" +#include "tx/single_cfm.h" +#include "tx/agg_cfm.h" +#include "tx/tx_queue.h" + +static int cmd_set_key(struct cl_hw *cl_hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + int error = 0; + struct mm_key_add_cfm *key_add_cfm; + u8 cipher_suite = 0; + + /* Retrieve the cipher suite selector */ + switch (key->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + cipher_suite = MAC_CIPHER_SUITE_WEP40; + break; + case WLAN_CIPHER_SUITE_WEP104: + cipher_suite = MAC_CIPHER_SUITE_WEP104; + break; + case WLAN_CIPHER_SUITE_TKIP: + cipher_suite = MAC_CIPHER_SUITE_TKIP; + break; + case WLAN_CIPHER_SUITE_CCMP: + cipher_suite = MAC_CIPHER_SUITE_CCMP; + break; + case WLAN_CIPHER_SUITE_GCMP: + case WLAN_CIPHER_SUITE_GCMP_256: + cipher_suite = MAC_CIPHER_SUITE_GCMP; + break; + case WLAN_CIPHER_SUITE_AES_CMAC: + return -EOPNOTSUPP; + default: + return -EINVAL; + } + + error = cl_msg_tx_key_add(cl_hw, vif, sta, key, cipher_suite); + if (error) + return error; + + key_add_cfm = (struct mm_key_add_cfm *)(cl_hw->msg_cfm_params[MM_KEY_ADD_CFM]); + if (!key_add_cfm) + return -ENOMSG; + + if (key_add_cfm->status != 0) { + cl_dbg_verbose(cl_hw, "Status Error (%u)\n", key_add_cfm->status); + cl_msg_tx_free_cfm_params(cl_hw, MM_KEY_ADD_CFM); + return -EIO; + } + + /* Save the index retrieved from firmware */ + key->hw_key_idx = key_add_cfm->hw_key_idx; + + cl_msg_tx_free_cfm_params(cl_hw, MM_KEY_ADD_CFM); + + /* + * Now inform mac80211 about our choices regarding header fields generation: + * we let mac80211 take care of all generations + */ + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; + if (key->cipher == WLAN_CIPHER_SUITE_TKIP) + key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; + + if (sta) { + struct cl_sta *cl_sta = (struct cl_sta *)sta->drv_priv; + + cl_sta->key_conf = key; + } else { + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + + cl_vif->key_conf = key; + } + + return error; +} + +static int cmd_disable_key(struct cl_hw *cl_hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + if (sta) { + struct cl_sta *cl_sta = (struct cl_sta *)sta->drv_priv; + + cl_sta->key_conf = NULL; + cl_sta->key_disable = true; + + /* + * Make sure there aren't any packets in firmware before deleting the key, + * otherwise they will be transmitted without encryption. + */ + cl_txq_flush_sta(cl_hw, cl_sta); + cl_single_cfm_poll_empty_sta(cl_hw, cl_sta->sta_idx); + cl_agg_cfm_poll_empty_sta(cl_hw, cl_sta); + } else { + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + + cl_vif->key_conf = NULL; + } + + return cl_msg_tx_key_del(cl_hw, key->hw_key_idx); +} + +int cl_key_set(struct cl_hw *cl_hw, + enum set_key_cmd cmd, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + int error = 0; + + switch (cmd) { + case SET_KEY: + error = cmd_set_key(cl_hw, vif, sta, key); + break; + + case DISABLE_KEY: + error = cmd_disable_key(cl_hw, vif, sta, key); + break; + + default: + error = -EINVAL; + break; + } + + return error; +} + +struct ieee80211_key_conf *cl_key_get(struct cl_sta *cl_sta) +{ + if (cl_sta->key_conf) + return cl_sta->key_conf; + + if (cl_sta->cl_vif->key_conf) + return cl_sta->cl_vif->key_conf; + + return NULL; +} + +bool cl_key_is_cipher_ccmp_gcmp(struct ieee80211_key_conf *keyconf) +{ + u32 cipher; + + if (!keyconf) + return false; + + cipher = keyconf->cipher; + + return ((cipher == WLAN_CIPHER_SUITE_CCMP) || + (cipher == WLAN_CIPHER_SUITE_GCMP) || + (cipher == WLAN_CIPHER_SUITE_GCMP_256)); +} + +void cl_key_ccmp_gcmp_pn_to_hdr(u8 *hdr, u64 pn, int key_id) +{ + hdr[0] = pn; + hdr[1] = pn >> 8; + hdr[2] = 0; + hdr[3] = 0x20 | (key_id << 6); + hdr[4] = pn >> 16; + hdr[5] = pn >> 24; + hdr[6] = pn >> 32; + hdr[7] = pn >> 40; +} + +u8 cl_key_get_cipher_len(struct sk_buff *skb) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + struct ieee80211_key_conf *key_conf = tx_info->control.hw_key; + + if (key_conf) { + switch (key_conf->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + return IEEE80211_WEP_IV_LEN; + case WLAN_CIPHER_SUITE_TKIP: + return IEEE80211_TKIP_IV_LEN; + case WLAN_CIPHER_SUITE_CCMP: + return IEEE80211_CCMP_HDR_LEN; + case WLAN_CIPHER_SUITE_CCMP_256: + return IEEE80211_CCMP_256_HDR_LEN; + case WLAN_CIPHER_SUITE_GCMP: + case WLAN_CIPHER_SUITE_GCMP_256: + return IEEE80211_GCMP_HDR_LEN; + } + } + + return 0; +} From patchwork Thu Jun 17 15:59:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21E2CC49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 104/256] cl8k: add key.h Date: Thu, 17 Jun 2021 15:59:51 +0000 Message-Id: <20210617160223.160998-105-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b00ddd4-18ac-411c-56cb-08d931a99640 X-MS-TrafficTypeDiagnostic: AM9P192MB0887: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zMbpuL42G1CEo1u3C4kBRLkvOKwQ14OEfg+EEvvgYbiPZM0SdMGHFktXKGkCC9pT+y4t/wvZsfDXHs3Qv2Rzv7BRMmmlib8Hjh37h4TcPoDW5iKHDOs8WSHnXcNPkEGUbZ8gQQGLl6OIxHBbpV4CuetVcsT0SAz33+OuFYBS/P/lVRQ5R+tejMkyTBCJU5VlqG2YDnkWVdONW0sByR5g7Sdf5nhaqgCq6dj1lU6A23CdzXVZCHpPFitkJydgIgeXTA+74+cacZqdc7dS/TQvr8SXZB8SPromOenCBZs2AwRRloGjWmQtjOuUL6TIi1cUQYXTuuSsEVCqx3XiTMmNxcQUVBG9ax8X5GGgDRR18/qii+SXj+cjIybDthVOXrIvc9rg7dKEem+BZ2jt4f1yUz8qmqZC3ew1WACIpH7SX7UetBJsatQsE5y/hYhOlt/gdfNGUYt3/5HwDY2wcRRbSWpbYtC/mkhyoBkF7u7jYmwGNJxWI3jIvJB+THxkOSx484SAidAgF3kNiTeLuVtJa+avB7brSQrqPjZnYMJ+6UPWTKJEasZiH7+15b9mCnPAFmpd4vLYKfhJxlgJIEIs+1CbXDrX07gao0lw7QDroWD0N9NvPvX2c9+ghv4KjZfCEmPd0pPG3IaTuXtq5Hs9ZW/kypuj1kpe8vYLzVDAPkmxL1Ft7Qr0m3CjCaxmPyjrv++jm8XhNModn0MSU1Pe8w== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(396003)(366004)(39850400004)(136003)(346002)(83380400001)(6666004)(38350700002)(4326008)(186003)(16526019)(5660300002)(54906003)(6506007)(26005)(55236004)(38100700002)(316002)(1076003)(107886003)(52116002)(8936002)(508600001)(66476007)(66946007)(66556008)(36756003)(6916009)(6486002)(86362001)(2616005)(956004)(2906002)(8676002)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HUfsLb+ABJ5RDbPV6pCQJhdc3JKaJ4DFiNYOYj9hMX67mf/jMCtO1/W2BtYtjig5tDhVj3aeNai22CjUjvdWeoA8DaIYONHk331X8XASmQ+kYliNAKIesbFj1CInrpqcMg8q1eL5EV5BRYvSYxkB2qs1wKLx65ldUWjyskYZva0IKD1q3oIjojHxbk+KpIwVQT9YqvkQMbwEj1En3CPcJ/m2OTVKJMigzNSY8sELg/opWY5XPJn8YZUV2FdyAud1iXjoCx4y2kEhwQ8iDDsQEOYUyyTuBRPbxjLMA73u6MSAWr8lD726LY8HWKtF1VIYBJ8mFYTBl1xoDKRN/bfSaY06aWn5/8Sk7NKPv9kgfNq5xZlIxlyHe9CGEpLJFxymfDd5g+mze8Xmr77h2DW5E0coqJre+LB24mQRiCfXDHYxry1U9hj17rBLU+aQgQkVMBKpD6px0J13B71qsQllAtI/FlOZlXV5zDh5xVvx7y/Ah3llLP3khBXugVfteEuBNWRslzQpzohw8YawUGBXbeTN+4Ivf/wZsNnPHT7Xnh+0qvkBa1GWYTiLij9Z04F7gJcEDWFjd4hB/YOXi2hkGA1Dor8afG3ZBJFpoGG4m/ksZUkhssoh6tRTHkBOFw4PICQNA1DNZy+0fqgP73HBx7BC+kNI5myGzebx2spUvZASdJZ1/X8pvB2AgamVGtuvV7cryQIgDZr4bZ8W5dVV4QGlAaF3nv2U7/K2l8lnleFXDhAslYQJtfAQz+TNpj3fk4+fTE29TW4IvpXr1IrDB05TZVDh6k75sJchNvohYHh+9jCKWnAjyaUUO93fL9UIST0q0Y1DDwNDw1IbafpXLPc01e8+UwjxS0GzJGM4+Naj0cPY6fZiRsDFMAYMrk3iFTjlV0Vi6S3avuduYdCztLK3QF7/QYN2GTdYoFqmp4Zn5v3SavUSLemuJyD/RcT9bJxRsGu1K3AUzuAhTIHxvN4whvH7FKbLhHGNYPRJzgHdDXqpLH8srcbQqlopJNR4QMp6lw4AhTe9gkcOWJ3hy2a5fzbkPfxmlsiiul+ISS+Yi2LpVg5as6VBvf9mCeM3SRE3c+Ym20GFpyWzZw489m3lr9VrN6tIQit2VjOV4PiNyhqIVCfVJ1HBt37gRDzbGXE5ikJnAme9J3Mir0lOGYcWpPqlDLOpjjxjYoWVTy/YXwwiXAxrPPUMDl0aMF51XyFKpnU1xhmLH69sdLCOJfxxJCK1a2FFDZZgWL3TUcIx5Yn+cQx2mBVGM86DZm0ZZqKhxvMyTbrJpwplGqisFmvvZEzhqGT+NEqDwJ8xoo5/ygKefuNQuea+JKHmnxQH X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6b00ddd4-18ac-411c-56cb-08d931a99640 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:29.2207 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wol6SIld8xDfqorQSqSCU7rZTyEx3csYnn7hR1qnSDyjhaYw5qHhstO3RGOr94tbpBbG70uuNXhbTEBTs6MXvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0887 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/key.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/key.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/key.h b/drivers/net/wireless/celeno/cl8k/key.h new file mode 100644 index 000000000000..9c9b9fe122f0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/key.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_KEY_H +#define CL_KEY_H + +#include "hw.h" + +int cl_key_set(struct cl_hw *cl_hw, + enum set_key_cmd cmd, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key); +struct ieee80211_key_conf *cl_key_get(struct cl_sta *cl_sta); +bool cl_key_is_cipher_ccmp_gcmp(struct ieee80211_key_conf *keyconf); +void cl_key_ccmp_gcmp_pn_to_hdr(u8 *hdr, u64 pn, int key_id); +u8 cl_key_get_cipher_len(struct sk_buff *skb); + +#endif /* CL_KEY_H */ From patchwork Thu Jun 17 15:59:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CDE0C2B9F4 for ; Thu, 17 Jun 2021 16:05:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 539F3613E1 for ; Thu, 17 Jun 2021 16:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232645AbhFQQH7 (ORCPT ); Thu, 17 Jun 2021 12:07:59 -0400 Received: from mail-am6eur05on2057.outbound.protection.outlook.com ([40.107.22.57]:62080 "EHLO EUR05-AM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231559AbhFQQHX (ORCPT ); Thu, 17 Jun 2021 12:07:23 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=k+BceLuENAo34FcbcLoTUlxXN2pSBsYUswtIj5F3BdHRGz4R7DhJ20vAeM8xolUQYDEozqGX8FtKRxNWTNGotjQ46PN4gtHB/pqQuFC+knrp/XOUYCa/rfxUaKDdsBT8jTyqzdhD+xyjEReVaTBGDz1ZETHKpVo99VtjPNJfzzGq2XKyQO83pr+VYxCIt0NgX9UWYeFMtzlbBiMC1fdGLrN8+8EEy1f4bRt9W8jWGuhS35mY9PJP+l5BUVaVLKYcQmgZ35t7EEkBEetdS7e+WQ5sqt5z81MZl4+a4jSEWA405SR9cMyMpeszJ5/c2yHNQIbvLw3TIGc/MMcRMGuS6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jl6JxYhmqbp3u5CCWpGW+uUeAQzKLLI1FyiAFS27b6Y=; b=B/ntojuf6MYk2ZajsWc4TKMkQd0GKdBUhAWrKjySNVElk2mKpjSyV7JuFApphK5N12Rlke/9qdTDOL+ags+vlEBn7UtwwzlEenCsPW2zIzw+CSSH/F6KTtuSKPcLdI8JXwEVwBk6QXINgKrZ9dq7Qy9sRAhFL9bdf7ZfBzKcaA7B+OdOCR8pfgV3puO7w3U1agsauB6uj/xiG89nJGisBbXpE/LWslSg2vbzScbDOOBr0isuJ4Qlj/HX3dKBQkHoDaf0TbTugdc/TEbOfoEZF2FYv2Ue6IGAfDKRCX5pFRCwNJ9Qn/y5NtM9XpQIeSi3ti6Xj2Vu2rc2vDz0FXFf8w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jl6JxYhmqbp3u5CCWpGW+uUeAQzKLLI1FyiAFS27b6Y=; b=w4sEFBdQRzTPiiYroxY9cLBnN/Ric+69rr3nf3aslkIJK8P/L6UqdQOqlZNoOUkI5Kq8nE9dFw5WdZmTd5RFsqjnsH1eGXD5y4VREuJJmnSaURK6D6PhGffGphqXvKuJOki3EG9KPJyekaWdarPJZncaghWr1H3EhC4/E4YpmWQ= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0402.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:46::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18; Thu, 17 Jun 2021 16:05:07 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:07 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 107/256] cl8k: add mac_addr.c Date: Thu, 17 Jun 2021 15:59:54 +0000 Message-Id: <20210617160223.160998-108-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:31 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 772691f1-2c04-4729-8623-08d931a99829 X-MS-TrafficTypeDiagnostic: AM0P192MB0402: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ifSzfGMHI0YO8Jp4chRo0xFsXex6Cwu4lp9MH/zkMe8InvwWOWYxPYrjjUGOeWRwYZ7nz8LIg2mfn4OPt7drRwMiMisgVQyTN0KGj1Zf0DkBG0Ouf0O+Ix0mnWiAUwaLXD0lIelJVOmP0Y5LWUBPRFl8ZGAWSKhmUQBfeAl9zL/BeIWz7L37Q3NvNWoo25WwGLRajxLCkHDWMhe/lLLKPkppJ12XO70rxz89NDdmBMTflT1TfD6vaTMUYkd4r8/ebw6UVFjKFsltfKH/zOW7LV+/9wQiq4L9C9nJ+9E5MGS2zedWLm6QbH6HeqhOVpsT3zx6rNt6TAes3z7v3LXx4xNzBpPYJs1gT+1o4I0kVMPEXc3q9sSGJreZgfaQ3vRtfk/Pe2rLjDV5wmErdjCXa1IGX9Eu3Mw8HtOofn0iev9KaZbGN8Wtj1ux0XPxwcfeg91V7hKceX1yEL4z9/HxSnmCSIT/xjgWp/GH3ntcJKDye84C/IYDJuu9SlO/1hRGtEBtIKwjiZjemb0NPJGWQEFu57LYpgFpnsTFqWBNIPK3M9BgUdjPYuehuI9IDH4wIUGte4BtqdZ5QUQNzEouAMjRXFf+yj2tndT7ieo2ia5bLT3CejTYHyLV3p3yulnmKDt0P4ONGuVLuEvQqQJA98029nf3x3wgm80/x3h9lw9dMExhuvMCuT2r6pXHTjTshVOrflxLsEXNOSa7DXCx4A== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39850400004)(136003)(376002)(396003)(366004)(346002)(6916009)(6512007)(9686003)(6666004)(52116002)(2616005)(186003)(16526019)(38100700002)(38350700002)(1076003)(6506007)(5660300002)(107886003)(55236004)(86362001)(6486002)(8936002)(956004)(26005)(8676002)(30864003)(508600001)(2906002)(36756003)(54906003)(316002)(66946007)(66556008)(4326008)(66476007)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dcqA/cDDiOyJl3Dzsi7VD5FOYIMaf4lm7jf5ioTkr6cZ4cr2ttY4TjDSux7MjG0ChufHPpIJfdfQdO1Yvj0oWGqsPdUV1dpOAiDTZgxd0+ImnYkcwHDauZYRsBgPLFajDbVjOMtti1aMAZT1qTE9GSK8lg+ZEuGby+4+tN9ClMXgl4uXxYvLg9CdA0Q+1nz2yzJZBS/WCkX+1aIN7lM4VhVdQPoI/WebjAo2w/RKmjc0BQJPB4QyVnVohNTVxd1S4Qi5jLMlOmjEycAlOmsQMDJlvUIhypG6l9iPSWc2h7XulkOj1XZJHiB23+7gcyhsL8yXGahVYxFVc3q628lEtLO58+nboiw9PssSHzG7f69h6Wq9gzZDfyo2MTX1VLHBI09n3Z6XRKXizp9zG+PPhabT9uThtOK/1S4BaqxJMbs7kKzfECFo3cHJT/OXQgO9fx+BQtp9Bu4I+EzkHecg+LAdPjzlPq18WyS51q58/zPNtHHflTb32z0p2Hu++pQJJTZEp6H3jyd95Ppgbbj/uKxCSVkFC0iRXnfV2OirdO5pxPnF2S46DSkUliBIS1YVDtfwTQUXXxZcf2iMyXCqCMA5vqwguBoRuenw7HmocycR5TBTJqSMQMnC9nqIAbJtPWr+mw9nClD3gp+W3QOLi3SCfySWLT4DOAh7WdhD1cUK4jDDwCYcrZB2tBiDCpw/07xCideIlLDH5VYNf9N9TC3A2x2/bpAS3pCRHB3+KCRIM8584qT3sZp4POzNc0SpGv44aI0b3WSHD8hKVQh+aNkb8bZdeh3xWu5oxAFyD0qB8VVRaLYExOrzD9NoinSqc0wehevvGtcZoGV+cw7Gx/18MbgeMeu+ZyaAzpaf5msatD0BK+G+vc/BUl2QvYJFrTlWD8XK6vfkrGRduflzdZqeZFYGgzvdf4j9zKNlPPwKUJmGleldTN5pRqloNvP6Q6HdEaj4CKM4BUPqC1DFt3eyqBrYOhPDW9hQRACYoG3aon4SPBWK7N3HnlCx0sP2yyqQuvl/ELLh3n+2MmcFquTix6ss3nxQ2nhHFZJBdQVuKmmmgnXNh7NTZPfun66r5aSoMg4QY2nPAUaQ8imRqS+Zi2nMQY/X3tzxLAwKy0IVDxQ4TS3sCJO9pmqlqusepR9Xwlxjgdy2pyF9XbLZvjeNOp5cmW5SIFNGUnVBywgb0lNA5+K638HQcyaniVTbZqz17Ukeg+BP7NHM0Fgxh+RxDW2Lm05m+/BvjsHIYG52Mi7VvFkXulZm663p7NlOUY323p+LemletJtmpmam59DZvJ+4gtjUTOnPNdDziHb+gBIFbETDNknOn10jrOfY X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 772691f1-2c04-4729-8623-08d931a99829 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:32.3669 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QW7HelxPmMD4scFUYh7W1P2wl91MnzTx4l8xemi2poarB6IgJImPkX1sPRqC31yNYglcZBxNqjomTM6vSfBcUg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0402 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/mac_addr.c | 331 ++++++++++++++++++++ 1 file changed, 331 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/mac_addr.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/mac_addr.c b/drivers/net/wireless/celeno/cl8k/mac_addr.c new file mode 100644 index 000000000000..eeb3ce294111 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/mac_addr.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "mac_addr.h" +#include "utils/utils.h" +#include "chip.h" + +static int set_mask_addr_without_zeroing_bits(struct cl_hw *cl_hw, u64 mac64, u8 bss_num, + u8 first_mask_bit, u8 *mask_addr) +{ + u64 mask = mac64; + s8 idx = 0; + + mask >>= first_mask_bit; + mask += (bss_num - 1); + + /* + * After the following line the mask will contain the changed + * bits between the first BSS MAC and the last BSS MAC + */ + mask ^= (mac64 >> first_mask_bit); + + /* Find leftmost set bit */ + for (idx = 47 - first_mask_bit; (idx >= 0) && (!(mask & (1ULL << idx))); idx--) + ; + + if (idx < 0) { + cl_dbg_err(cl_hw, "Invalid mask (mac=0x%02llx, first_mask_bit=%u, bss_num=%u)\n", + mac64, first_mask_bit, bss_num); + mask = 0; + eth_zero_addr(mask_addr); + + return -1; + } + + mask = (1ULL << idx); + mask |= (mask - 1); + mask <<= first_mask_bit; + + for (idx = 0; idx < ETH_ALEN; idx++) { + u8 shift = (8 * (ETH_ALEN - 1 - idx)); + + mask_addr[idx] = (mask & ((u64)0xff << shift)) >> shift; + } + + return 0; +} + +static int mask_mac_by_bss_num(struct cl_hw *cl_hw, u8 *mac_addr, u8 *mask_addr, + bool use_lam, bool random_mac) +{ + u8 bss_num = cl_hw->conf->ce_bss_num; + u8 first_mask_bit = cl_hw->chip->conf->ce_first_mask_bit; + u8 i; + /* Determine the bits necessary to cover the number of BSSIDs. */ + u8 num_bits_to_mask[MAX_BSS_NUM * 2 + 1] = { + 0, 0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4 + }; + u8 mask_size = 0; + u8 byte_num = ETH_ALEN - 1 - (first_mask_bit / 8); + u8 bit_in_byte = first_mask_bit % 8; /* Referring to the index of the bit */ + + if ((first_mask_bit + num_bits_to_mask[bss_num]) > (ETH_ALEN * 8)) { + pr_err("Invalid combination of first_mask_bit + bss_num. " + "must be lower than 48 bit in total\n"); + return -1; + } + + if (cl_hw_is_tcv0(cl_hw)) { + mask_size = num_bits_to_mask[bss_num - 1]; + } else { + u64 mac64 = ether_addr_to_u64(mac_addr); + u8 tcv0_bss_num = cl_hw->chip->cl_hw_tcv0->conf->ce_bss_num; + u8 bit_mask = (1 << num_bits_to_mask[bss_num + tcv0_bss_num - 1]) - 1; + + /* + * If we need to zero bits due to lack of room for the MAC addresses + * of all BSSs of TCV1, then the mask is the number of zeroed bits + */ + if (((u64)bit_mask - ((mac64 >> first_mask_bit) & (u64)bit_mask) + 1) < bss_num) { + mask_size = num_bits_to_mask[bss_num + tcv0_bss_num - 1]; + } else { + /* + * Otherwise the mask is the different bits between the + * addresses of the first and the last BSSs + */ + set_mask_addr_without_zeroing_bits(cl_hw, mac64, bss_num, + first_mask_bit, mask_addr); + return 0; + } + } + + /* Build mac and mask addr */ + for (i = 0; i < mask_size; i++) { + /* + * Build mask - Convert to "1" the relevant bits in the mask + * addr in order to support the desired number of BSSIDs + */ + mask_addr[byte_num] |= (0x01 << bit_in_byte); + + /* + * Build mac -convert to "0" the relevant bits in the mac addr + * in order to support the desired number of BSSIDs + */ + if (random_mac && !use_lam) + mac_addr[byte_num] &= ~(0x01 << bit_in_byte); + + bit_in_byte++; + + /* Support cases where the mask bits are not at the same byte. */ + if (bit_in_byte == 8) { + byte_num--; + bit_in_byte = 0; + } + } + + if (use_lam) { + /* Mask LAM bit (Locally Administered Mac) */ + if (cl_hw_is_tcv0(cl_hw)) + mask_addr[0] |= 0x02; + } else { + /* + * When not using LAM we do not zero the MAC address of the second BSS, + * so the mask (the modified bits between the first and last BSS) depends + * on initial MAC + */ + u64 mac64 = ether_addr_to_u64(mac_addr); + + set_mask_addr_without_zeroing_bits(cl_hw, mac64, bss_num, + first_mask_bit, mask_addr); + } + + return 0; +} + +#define MAC_FILTER_BITS 4 +#define MAC_FILTER_MASK ((1 << MAC_FILTER_BITS) - 1) + +static bool is_valid_mac_addr(u64 mac64, u8 first_mask_bit, u8 bss_num) +{ + u8 mac_bits = (mac64 >> first_mask_bit) & MAC_FILTER_MASK; + u8 mac_diff = 0; + u8 i; + + for (i = 0; i < bss_num; i++) { + mac_diff |= mac_bits; + mac_bits++; + } + + return hweight8(mac_diff) <= MAC_FILTER_BITS; +} + +static int cl_mac_addr_set_addresses(struct cl_hw *cl_hw, bool use_lam, + u8 *mask_addr) +{ + u8 first_mask_bit = cl_hw->chip->conf->ce_first_mask_bit; + int i = 0; + u8 bss_num = cl_hw->conf->ce_bss_num; + u64 mac64 = ether_addr_to_u64(cl_hw->hw->wiphy->perm_addr); + u64 mask64 = 0; + u8 new_addr[ETH_ALEN] = {0}; + + if (!use_lam && !is_valid_mac_addr(mac64, first_mask_bit, bss_num)) { + cl_dbg_err(cl_hw, + "perm_addr %pM is invalid for bss_num %d without LAM\n", + cl_hw->hw->wiphy->perm_addr, bss_num); + return -1; + } + + cl_mac_addr_copy(cl_hw->addresses[i].addr, + cl_hw->hw->wiphy->perm_addr); + for (i = 1; i < bss_num; i++) { + u8 *prev_addr = cl_hw->addresses[i - 1].addr; + + if (use_lam) { + mac64 = ether_addr_to_u64(prev_addr); + mask64 = ether_addr_to_u64(mask_addr); + if (cl_hw_is_tcv0(cl_hw)) { + if (i == 1) + mac64 &= ~mask64; + else + mac64 += 1 << first_mask_bit; + u64_to_ether_addr(mac64, new_addr); + new_addr[0] |= 0x02; + } else { + if ((mac64 & mask64) == mask64) + mac64 &= ~mask64; + else + mac64 += 1 << first_mask_bit; + u64_to_ether_addr(mac64, new_addr); + } + cl_mac_addr_copy(cl_hw->addresses[i].addr, new_addr); + } else { + mac64 = ether_addr_to_u64(prev_addr); + mac64 += 1 << first_mask_bit; + u64_to_ether_addr(mac64, cl_hw->addresses[i].addr); + } + } + cl_hw->n_addresses = bss_num; + + return 0; +} + +int cl_mac_addr_set_tcv0(struct cl_hw *cl_hw, u8 *dflt_mac, u8 *dflt_mask, bool *random_mac) +{ + struct cl_chip *chip = cl_hw->chip; + + if (!cl_mac_addr_is_zero(chip->conf->ce_phys_mac_addr)) { + /* Read MAC from NVRAM file */ + cl_mac_addr_copy(dflt_mac, chip->conf->ce_phys_mac_addr); + cl_dbg_verbose(cl_hw, "Read MAC address from NVRAM [%pM]\n", dflt_mac); + } else { + /* Read MAC from EEPROM */ + if (chip->eeprom_read_block(chip, ADDR_GEN_MAC_ADDR, + ETH_ALEN, dflt_mac) != ETH_ALEN) { + CL_DBG_ERROR(cl_hw, "Error reading MAC address from EEPROM\n"); + return -1; + } + + cl_dbg_verbose(cl_hw, "Read MAC address from EEPROM [%pM]\n", dflt_mac); + } + + /* Test if the new mac address is 00:00:00:00:00:00 or ff:ff:ff:ff:ff:ff */ + if (cl_mac_addr_is_zero(dflt_mac) || cl_mac_addr_is_broadcast(dflt_mac)) { + /* Set celeno oui */ + dflt_mac[0] = 0x00; + dflt_mac[1] = 0x1c; + dflt_mac[2] = 0x51; + get_random_bytes(&dflt_mac[3], 3); + cl_dbg_verbose(cl_hw, "Random MAC address [%pM]\n", dflt_mac); + *random_mac = true; + } + + return 0; +} + +void cl_mac_addr_set_tcv1(struct cl_hw *cl_hw, u8 *dflt_mac, u8 *dflt_mask) +{ + struct cl_chip *chip = cl_hw->chip; + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + u8 tcv0_bss_num = cl_hw_tcv0->conf->ce_bss_num; + u8 first_mask_bit = chip->conf->ce_first_mask_bit; + u64 mac64; + u8 idx; + u8 bss_num = cl_hw->conf->ce_bss_num; + u8 bit_mask[MAX_BSS_NUM + 1] = {0x0, 0x0, 0x1, 0x3, 0x3, 0x7, 0x7, 0x7, 0x7}; + + mac64 = ether_addr_to_u64(cl_hw_tcv0->hw->wiphy->perm_addr); + + if (chip->conf->ce_lam_enable) { + /* Find the first address of TCV1 */ + if (tcv0_bss_num == 1) { + /* + * For tcv0 bss num = 1, we have to zero the necessary bits + * since it hasn't been done in TCV0 + */ + mac64 &= ~((u64)bit_mask[bss_num] << first_mask_bit); + } else { + u8 total_bss_to_mask = bss_num + tcv0_bss_num - 1; + + mac64 &= ~((u64)bit_mask[tcv0_bss_num - 1] << first_mask_bit); + /* + * Get the first MAC address of TCV1 by incrementing the MAC + * address of the last BSS of TCV0. + * After the instruction below mac64 will hold the MAC of TCV0's + * last BSS. + */ + mac64 += ((u64)(tcv0_bss_num - 2) << first_mask_bit); + /* + * If there is no more room for another address in TCV0's mask + * address then we have to zero bits else increment the last + * address of TCV0 + */ + if (((mac64 >> first_mask_bit) & (u64)bit_mask[total_bss_to_mask]) == + (u64)bit_mask[total_bss_to_mask]) + mac64 &= ~((u64)bit_mask[total_bss_to_mask] << first_mask_bit); + else + mac64 += (1ULL << first_mask_bit); + } + + /* Enable LAM bit */ + mac64 += (0x2ULL << 40); + } else { + mac64 += ((u64)tcv0_bss_num << first_mask_bit); + } + + for (idx = 0; idx < ETH_ALEN; idx++) { + u8 shift = (8 * (ETH_ALEN - 1 - idx)); + + dflt_mac[idx] = (mac64 & ((u64)0xFF << shift)) >> shift; + } +} + +int cl_mac_addr_set(struct cl_hw *cl_hw) +{ + bool random_mac = false; + u8 dflt_mac[ETH_ALEN] = {0, 28, 81, 81, 81, 81}; + u8 dflt_mask[ETH_ALEN] = {0}; + bool use_lam = cl_hw->chip->conf->ce_lam_enable; + struct wiphy *wiphy = cl_hw->hw->wiphy; + + if (cl_hw_is_tcv0(cl_hw)) { + if (cl_mac_addr_set_tcv0(cl_hw, dflt_mac, dflt_mask, &random_mac)) + return -1; + } else { + cl_mac_addr_set_tcv1(cl_hw, dflt_mac, dflt_mask); + } + + /* For single BSS mask should be 0 */ + if (cl_hw->conf->ce_bss_num > 1) + if (mask_mac_by_bss_num(cl_hw, dflt_mac, dflt_mask, use_lam, random_mac)) + return -1; + + /* Permanent address MAC (the MAC of the first BSS) */ + SET_IEEE80211_PERM_ADDR(cl_hw->hw, dflt_mac); + + /* + * MAX_BSS_NUM must be power of 2 + * mac80211 doesn't handle non-contiguous masks + */ + if (!WARN_ON(MAX_BSS_NUM & (MAX_BSS_NUM - 1))) + cl_mac_addr_array_to_nxmac(dflt_mask, &cl_hw->mask_low, &cl_hw->mask_hi); + + if (cl_mac_addr_set_addresses(cl_hw, use_lam, dflt_mask)) + return -1; + + wiphy->addresses = cl_hw->addresses; + wiphy->n_addresses = cl_hw->n_addresses; + + return 0; +} From patchwork Thu Jun 17 15:59:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC93C49EA2 for ; Thu, 17 Jun 2021 16:06:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D22FF61406 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 109/256] cl8k: add main.c Date: Thu, 17 Jun 2021 15:59:56 +0000 Message-Id: <20210617160223.160998-110-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:33 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cacc9468-8023-4cd7-5798-08d931a99967 X-MS-TrafficTypeDiagnostic: AM0P192MB0402: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1060; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZB4TltUDCS7oiOdmqBOeN1eD4fEavSeK1J36GB3CMUDDDY2sW9ln4ScbeMZzMMTnpwi5qFa8lFMeKXnPJB9PruDjShRFU6imTPKvybdmSAdZCl8fmaEjAgOpCi3Xd2r4iibAzW2eliCsAlu4dGAf1oMkTY9w3GaCnA4F/8HEuGsI/EQiYkK9mex6Ouur6MlddtdHK6qKzVEeEIDm1Z9t/tGywYxD2HUXhA0YMJ9cnqdXq7F0K4Mm0akhgF9hkWs9pSjmpJaDQDBOPZJ1b4nYonaMMMqBBU3ZpG6vD+0L+AUk3xNZaQ/Coh/ZKhqsMPVXmrYOOCgcxJIgbTexdSkI0+OVBWRMV0CbEtM/AEQ0E/wvvhNlTVV0bFUFkPZ7Gr1DSV2xlyTqPFARUiK5dUJV+XBIGacrixgGrD0tOt0jTgej+rBQEN0NE3wRDXYb66qphsPtU/8mLS1OBqyKqZh0zUBVHHgSq68WkawYVUfIWSAmbqFDbZtL8bGi3tRpnzjcLj8X14I0ARW8HupHJGoKoO9vPhrI7LxpLCDuuscSe6Tdij1LZgZ1CU2FF1qoJa58iCcbgxc5QlsB+rWh98awdWGSeu5+pmYft3IbLGuUxFEBBt1xBuOs6a1hQsaERwAIInMxs+94AYpDdYRwpbbT9eq4qaEyvxYC7UDWvHKejthMO0PF563oUbNgJcllQhVUTGQQGrGy7IXjRmBpCHQsKw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39850400004)(136003)(376002)(396003)(366004)(346002)(6916009)(6512007)(9686003)(6666004)(52116002)(2616005)(186003)(16526019)(38100700002)(38350700002)(1076003)(6506007)(5660300002)(107886003)(55236004)(86362001)(6486002)(8936002)(956004)(26005)(8676002)(30864003)(508600001)(2906002)(36756003)(54906003)(316002)(66946007)(66556008)(4326008)(66476007)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xf91LVnPlDXVoEH1EA7sygL7ROjMofx0iog0AUWPYRwOhjh60uGnCyVRABO4gqoo8BZXCmCvgiOm8b06VNDcQgNsamPupOrn3wLrsn1CdHe0Is/eAWBZIOskWTKFm36qVMXtpBQmIp9Lzyq/0PNwroQwm+3soPlOuqrKqeIC8+OqleZS1y+ZS44yl9NzZ62RD2IkT+HeuyuvekVW1qmXX91vBs2KJlmbkcUKtuLeLtNjtua1hm37XiXA5gxduOgshPQF13YiVg5g+xIBGCclE3186IP2kDCusAes4zkGmNCfcZW8oUPfqlwKt6jMO3Cd2YhmzVYHocqplU37+QPFLoyoVwFdN85pA2PvtVQ7ZXTT1jt3hAYALdvL31/jfDbebg0Q5Rl+4GgKieP0c4TvSXBcC7Ebf7nhDaaCGxW77fSOSfjh2IUZzB7WpablvHd3fwbvt+sqzWspLe5YsKrXs/M+n/1yoo86OkXiWpO+B12oW9i8LFBVHWxuCl/WYqZITKGK8Po3NycemTqZvaDldWs4b/hDS5Oo2pKC4WxxExv1Q1MErd9iBt3BCTzKgHImAd5X1KNqhNFKg+txGFIBVc9Wpq4cQ5UjR8iYY4wsLWbexjNQkjP1ZjduMKv412RikGTzws8XZteTCwnP0sdBrcoe/LWV1OTYWzLc2x0/omuuPYIyucBPnx/3rELeYUuolzsbL25WRAYhjQTsSpZ5zp+kNLzvkKmF9IQ6IKnlr37TBAET7tr/aL/MuDawYNX1s2X9YnUxhDXR69JDOfeq7ejj0tS1jdG4ZZ9Hc9YpG4bycjguYkIiRQGo7GNYqa2jc6/TsaR0ZCvLwRoCy6dd1OU34Oa5DZlEUQ0Dx9z0kvcuhiKJ3xNVy8Xg7CK/Zzj0QevmodQzc73VSHaxuhtTxE3Ir2NSZree+n+MNzwPAWp/CZj21hXhfpZcTs6RpL2Tn9B+5W7q08eSZfEN4MGXm0AtSW1NzzAqdIMunNJ9FzmsEwZ2xHUo6Uzd1FOqlDn5lorSAuP4UGQpjtyYmzkPlKqKDv6OHxa1X8skmrnshWhmT03XIDVIPPe2p6/rpJBRQRqW+0EFhXYg2UhYBBZPc3/81lpQl2cyqNkSmUvTbTm1oKLDuAuzcaqaVViXaDXCoHPw3wutQrTURZQeNXRuAnadgpUnpcX6riSN1it3ZkUuXAXgg14z2svIObijyAsOXqk0MfEgZVNBDTw+OMn34G6UmyEYxTDKzZsmLcx0DWXJpYWLVBjnUAH7BSYLlXys4M41xuEQXGmrKVnGxYUlAeIfoxHp6vYsJ8lLNQvGore2rhI9wkpfcJrSpaquWAKY X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: cacc9468-8023-4cd7-5798-08d931a99967 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:34.5065 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ogQbqX7dj1y4BIUn2aZXqe04gkkSgPfm0vA9tw1IwBP2AUTkFWC1UOJBqDo6lDhyqIkoAzp5YTlZkBhGTa6WIw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0402 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/main.c | 584 ++++++++++++++++++++++++ 1 file changed, 584 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/main.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/main.c b/drivers/net/wireless/celeno/cl8k/main.c new file mode 100644 index 000000000000..0b37ae8a03e1 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/main.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chip.h" +#include "main.h" +#include "ops.h" +#include "dfs/radar.h" +#include "fw/msg_tx.h" +#include "tx/tx.h" +#include "reg/reg_access.h" +#include "stats.h" +#include "debugfs.h" +#include "vendor_cmd.h" +#include "chan_info.h" +#include "tx/agg_cfm.h" +#include "tx/single_cfm.h" +#include "tx/bcmc_cfm.h" +#include "tx/tx_queue.h" +#include "rssi.h" +#include "maintenance.h" +#include "vns.h" +#include "traffic.h" +#include "ext/vlan_dscp.h" +#include "sounding.h" +#include "recovery.h" +#include "rate_ctrl.h" +#include "ext/dyn_mcast_rate.h" +#include "ext/dyn_bcast_rate.h" +#include "tx/tx_amsdu.h" +#include "prot_mode.h" +#include "utils/utils.h" +#include "band.h" +#include "phy/phy.h" +#include "rf_boot.h" +#include "dsp.h" +#include "calib.h" +#include "reg/reg_macsys_gcu.h" +#include "dfs/dfs.h" +#include "tx/sw_txhdr.h" +#include "tx/tx_inject.h" +#include "fem.h" +#include "fw/fw_file.h" +#include "cap.h" +#include "tcv_config.h" +#include "mac_addr.h" +#include "hw_assert.h" +#include "power_table.h" +#include "noise.h" +#include "twt.h" +#include "fw/fw_dbg.h" +#include "wrs/wrs_api.h" +#ifdef CONFIG_CL_PCIE +#include "fw/msg_rx.h" +#include "bus/pci/irq.h" +#include "reg/reg_ipc.h" +#include "bus/pci/ipc.h" +#endif + +MODULE_DESCRIPTION("Celeno 11ax driver for Linux"); +MODULE_VERSION("8.1.x"); +MODULE_AUTHOR("Copyright(c) 2021 Celeno Communications Ltd"); +MODULE_LICENSE("MIT"); + +#define MAX_MU_CNT_LMAC 8 +#define MAX_MU_CNT_SMAC 8 + +static struct ieee80211_ops cl_ops = { + .tx = cl_ops_tx, + .start = cl_ops_start, + .stop = cl_ops_stop, + .add_interface = cl_ops_add_interface, + .remove_interface = cl_ops_remove_interface, + .config = cl_ops_config, + .bss_info_changed = cl_ops_bss_info_changed, + .start_ap = cl_ops_start_ap, + .stop_ap = cl_ops_stop_ap, + .prepare_multicast = cl_ops_prepare_multicast, + .configure_filter = cl_ops_configure_filter, + .set_key = cl_ops_set_key, + .sw_scan_start = cl_ops_sw_scan_start, + .sta_state = cl_ops_sta_state, + .sta_notify = cl_ops_sta_notify, + .conf_tx = cl_ops_conf_tx, + .sta_rc_update = cl_ops_sta_rc_update, + .ampdu_action = cl_ops_ampdu_action, + .post_channel_switch = cl_ops_post_channel_switch, + .flush = cl_ops_flush, + .tx_frames_pending = cl_ops_tx_frames_pending, + .reconfig_complete = cl_ops_reconfig_complete, + .get_txpower = cl_ops_get_txpower, + .set_rts_threshold = cl_ops_set_rts_threshold, + .event_callback = cl_ops_event_callback, + .set_tim = cl_ops_set_tim, +}; + +static void cl_drv_workqueue_create(struct cl_hw *cl_hw) +{ + if (!cl_hw->drv_workqueue) + cl_hw->drv_workqueue = create_singlethread_workqueue("drv_workqueue"); +} + +static void cl_drv_workqueue_destroy(struct cl_hw *cl_hw) +{ + if (cl_hw->drv_workqueue) { + destroy_workqueue(cl_hw->drv_workqueue); + cl_hw->drv_workqueue = NULL; + } +} + +static int cl_main_alloc(struct cl_hw *cl_hw) +{ + int ret = 0; + + ret = cl_phy_data_alloc(cl_hw); + if (ret) + return ret; + + ret = cl_calib_tables_alloc(cl_hw); + if (ret) + return ret; + + ret = cl_power_table_alloc(cl_hw); + if (ret) + return ret; + + return ret; +} + +static void cl_main_free(struct cl_hw *cl_hw) +{ + cl_phy_data_free(cl_hw); + cl_calib_tables_free(cl_hw); + cl_power_table_free(cl_hw); +} + +static void cl_free_hw(struct cl_hw *cl_hw) +{ + struct ieee80211_hw *hw = cl_hw->hw; + + cl_tcv_config_free(cl_hw); + + if (hw->wiphy->registered) + ieee80211_unregister_hw(hw); + + cl_chip_unset_hw(cl_hw->chip, cl_hw); + ieee80211_free_hw(hw); +} + +static void cl_free_chip(struct cl_chip *chip) +{ + cl_free_hw(chip->cl_hw_tcv0); + cl_free_hw(chip->cl_hw_tcv1); +} + +static int cl_prepare_hw(struct cl_chip *chip, u8 tcv_idx, + const struct cl_driver_ops *drv_ops) +{ + struct cl_hw *cl_hw = NULL; + struct ieee80211_hw *hw; + int ret = 0; + + hw = ieee80211_alloc_hw(sizeof(struct cl_hw), &cl_ops); + if (!hw) { + cl_dbg_chip_err(chip, ": ieee80211_alloc_hw failed\n"); + return -ENOMEM; + } + + cl_hw_init(chip, hw->priv, tcv_idx); + + cl_hw = hw->priv; + cl_hw->hw = hw; + cl_hw->tcv_idx = tcv_idx; + cl_hw->chip = chip; + + /* + * chip0, tcv0 --> 0 + * chip0, tcv1 --> 1 + * chip1, tcv0 --> 2 + * chip1, tcv1 --> 3 + */ + cl_hw->idx = chip->idx * CHIP_MAX + tcv_idx; + + cl_hw->drv_ops = drv_ops; + + if (cl_hw_is_tcv0(cl_hw)) + cl_hw->max_mu_cnt = MAX_MU_CNT_LMAC; + else + cl_hw->max_mu_cnt = MAX_MU_CNT_SMAC; + + SET_IEEE80211_DEV(hw, chip->dev); + + ret = cl_tcv_config_alloc(cl_hw); + if (ret) + goto out_free_hw; + + ret = cl_hw_set_antennas(cl_hw); + if (ret) + goto out_free_hw; + + ret = cl_tcv_config_read(cl_hw); + if (ret) + goto out_free_hw; + + cl_chip_set_hw(chip, cl_hw); + + ret = cl_mac_addr_set(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "cl_mac_addr_set failed\n"); + goto out_free_hw; + } + + if (cl_band_is_6g(cl_hw)) + cl_hw->nl_band = NL80211_BAND_6GHZ; + else if (cl_band_is_5g(cl_hw)) + cl_hw->nl_band = NL80211_BAND_5GHZ; + else + cl_hw->nl_band = NL80211_BAND_2GHZ; + + cl_cap_dyn_params(cl_hw); + cl_vendor_cmds_init(hw->wiphy); + + /* + * ieee80211_register_hw() will take care of calling wiphy_register() and + * also ieee80211_if_add() (because IFTYPE_STATION is supported) + * which will internally call register_netdev() + */ + ret = ieee80211_register_hw(hw); + if (ret) { + cl_dbg_err(cl_hw, "ieee80211_register_hw failed\n"); + goto out_free_hw; + } + + if (hw->wiphy->regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED) { + ret = regulatory_set_wiphy_regd(hw->wiphy, cl_hw->channel_info.rd); + if (ret) + cl_dbg_err(cl_hw, "regulatory failed\n"); + } + + cl_dbg_verbose(cl_hw, "cl_hw created\n"); + + return 0; + +out_free_hw: + cl_free_hw(cl_hw); + + return ret; +} + +void cl_main_off(struct cl_hw *cl_hw) +{ +#ifdef CONFIG_CL_PCIE + cl_irq_disable(cl_hw, cl_hw->ipc_e2a_irq.all); + cl_ipc_stop(cl_hw); +#endif + + if (!test_bit(CL_DEV_INIT, &cl_hw->drv_flags)) { + cl_tx_off(cl_hw); + cl_rx_off(cl_hw); +#ifdef CONFIG_CL_PCIE + cl_msg_rx_flush_all(cl_hw); +#endif + } + + cl_fw_file_cleanup(cl_hw); +} + +static void _cl_main_deinit(struct cl_hw *cl_hw) +{ + /* First bring down all interfaces */ + cl_vif_bring_all_interfaces_down(cl_hw); + + cl_hw->is_stop_context = true; + + cl_drv_workqueue_destroy(cl_hw); + + cl_noise_close(cl_hw); + cl_maintenance_close(cl_hw); + cl_vns_close(cl_hw); + cl_rssi_assoc_exit(cl_hw); + cl_radar_close(cl_hw); + cl_sounding_close(cl_hw); + cl_chan_info_deinit(cl_hw); + cl_wrs_api_close(cl_hw); + cl_dfs_close(cl_hw); + cl_twt_close(cl_hw); + cl_tx_inject_close(cl_hw); + cl_dbgfs_unregister(cl_hw); + cl_main_off(cl_hw); + /* These 2 must be called after cl_tx_off() (which is called from cl_main_off) */ + cl_tx_amsdu_txhdr_deinit(cl_hw); + cl_sw_txhdr_deinit(cl_hw); + cl_stats_deinit(cl_hw); + cl_main_free(cl_hw); + cl_fw_file_release(cl_hw); + cl_vendor_timer_close(cl_hw); +#ifdef CONFIG_CL_PCIE + cl_ipc_deinit(cl_hw); +#endif + cl_hw_deinit(cl_hw, cl_hw->tcv_idx); +} + +void cl_main_deinit(struct cl_chip *chip) +{ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + + if (cl_chip_is_tcv1_enabled(chip) && cl_hw_tcv1) + _cl_main_deinit(cl_hw_tcv1); + + if (cl_chip_is_tcv0_enabled(chip) && cl_hw_tcv0) + _cl_main_deinit(cl_hw_tcv0); + + if (cl_hw_tcv1) { + cl_phy_off(cl_hw_tcv1); + cl_free_hw(cl_hw_tcv1); + } + + if (cl_hw_tcv0) { + cl_phy_off(cl_hw_tcv0); + cl_free_hw(cl_hw_tcv0); + } +} + +struct cl_controller_reg all_controller_reg = { + .breset = XMAC_BRESET, + .debug_enable = XMAC_DEBUG_ENABLE, + .dreset = XMAC_DRESET, + .ocd_halt_on_reset = XMAC_OCD_HALT_ON_RESET, + .run_stall = XMAC_RUN_STALL +}; + +void cl_main_reset(struct cl_chip *chip, struct cl_controller_reg *controller_reg) +{ + /* Release TRST & BReset to enable JTAG connection to FPGA A */ + u32 regval; + + /* 1. return to reset value */ + regval = macsys_gcu_xt_control_get(chip); + regval |= controller_reg->ocd_halt_on_reset; + regval &= ~(controller_reg->dreset | controller_reg->run_stall | controller_reg->breset); + macsys_gcu_xt_control_set(chip, regval); + + regval = macsys_gcu_xt_control_get(chip); + regval |= controller_reg->dreset; + macsys_gcu_xt_control_set(chip, regval); + + /* 2. stall xtensa & release ocd */ + regval = macsys_gcu_xt_control_get(chip); + regval |= controller_reg->run_stall; + regval &= ~controller_reg->ocd_halt_on_reset; + macsys_gcu_xt_control_set(chip, regval); + + /* 3. breset release & debug enable */ + regval = macsys_gcu_xt_control_get(chip); + regval |= (controller_reg->debug_enable | controller_reg->breset); + macsys_gcu_xt_control_set(chip, regval); + + msleep(100); +} + +int cl_main_on(struct cl_hw *cl_hw) +{ + struct cl_chip *chip = cl_hw->chip; + int ret; + u32 regval; + + cl_hw->fw_active = false; + + cl_txq_init(cl_hw); + + cl_hw_assert_info_init(cl_hw); + + if (cl_recovery_in_progress(cl_hw)) + cl_main_reset(chip, &cl_hw->controller_reg); + + ret = cl_fw_file_load(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "cl_fw_file_load failed %d\n", ret); + return ret; + } + + /* Clear CL_DEV_FW_ERROR after firmware loaded */ + clear_bit(CL_DEV_FW_ERROR, &cl_hw->drv_flags); + +#ifdef CONFIG_CL_PCIE + if (cl_recovery_in_progress(cl_hw)) + cl_ipc_recovery(cl_hw); +#endif + + regval = macsys_gcu_xt_control_get(chip); + + /* Set fw to run */ + if (cl_hw->fw_active) + regval &= ~cl_hw->controller_reg.run_stall; + +#ifdef CONFIG_CL_PCIE + /* Ack all possibly pending IRQs */ + ipc_xmac_2_host_ack_set(chip, cl_hw->ipc_e2a_irq.all); +#endif + + macsys_gcu_xt_control_set(chip, regval); + +#ifdef CONFIG_CL_PCIE + cl_irq_enable(cl_hw, cl_hw->ipc_e2a_irq.all); +#endif + + /* + * cl_irq_status_sync will set CL_DEV_FW_SYNC when fw raises IPC_IRQ_E2A_SYNC + * (indicate its ready to accept interrupts) + */ + ret = wait_event_interruptible_timeout(cl_hw->fw_sync_wq, + test_and_clear_bit(CL_DEV_FW_SYNC, + &cl_hw->drv_flags), + msecs_to_jiffies(5000)); + + if (ret == 0) { + pr_err("[%s]: FW synchronization timeout.\n", __func__); + cl_hw_assert_check(cl_hw); + ret = -ETIMEDOUT; + goto out_free_cached_fw; + } else if (ret == -ERESTARTSYS) { + goto out_free_cached_fw; + } + + return 0; + +out_free_cached_fw: + cl_fw_file_release(cl_hw); + return ret; +} + +static int __cl_main_init(struct cl_hw *cl_hw) +{ + int ret = 0; + + set_bit(CL_DEV_INIT, &cl_hw->drv_flags); + + /* By default, set FEM mode to operational mode. */ + cl_hw->fem_system_mode = FEM_MODE_OPERETIONAL; + + cl_vif_init(cl_hw); + + cl_drv_workqueue_create(cl_hw); + + init_waitqueue_head(&cl_hw->wait_queue); + init_waitqueue_head(&cl_hw->fw_sync_wq); + init_waitqueue_head(&cl_hw->radio_wait_queue); + + mutex_init(&cl_hw->dbginfo.mutex); + mutex_init(&cl_hw->msg_tx_mutex); + mutex_init(&cl_hw->set_channel_mutex); + + spin_lock_init(&cl_hw->tx_lock_agg); + spin_lock_init(&cl_hw->tx_lock_cfm_agg); + spin_lock_init(&cl_hw->tx_lock_single); + spin_lock_init(&cl_hw->tx_lock_bcmc); + +#ifdef CONFIG_CL_PCIE + ret = cl_ipc_init(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "cl_ipc_init failed %d\n", ret); + return ret; + } +#endif + ret = cl_main_on(cl_hw); + if (ret) { + cl_dbg_err(cl_hw, "cl_main_on failed %d\n", ret); +#ifdef CONFIG_CL_PCIE + cl_ipc_deinit(cl_hw); +#endif + return ret; + } + + ret = cl_main_alloc(cl_hw); + if (ret) + goto out_free; + + /* Reset firmware */ + ret = cl_msg_tx_reset(cl_hw); + if (ret) + goto out_free; + + cl_calib_power_read(cl_hw); + cl_dbgfs_register(cl_hw, "cl"); + cl_sta_init(cl_hw); + cl_sw_txhdr_init(cl_hw); + cl_tx_amsdu_txhdr_init(cl_hw); + cl_tx_init(cl_hw); + cl_rx_init(cl_hw); + cl_prot_mode_init(cl_hw); + cl_radar_init(cl_hw); + cl_sounding_init(cl_hw); + cl_vlan_dscp_init(cl_hw); + cl_traffic_init(cl_hw); + cl_rsrc_mgmt_init(cl_hw); + cl_vns_init(cl_hw); + cl_maintenance_init(cl_hw); + cl_rssi_assoc_init(cl_hw); + cl_agg_cfm_init(cl_hw); + cl_single_cfm_init(cl_hw); + cl_bcmc_cfm_init(cl_hw); + cl_dyn_mcast_rate_init(cl_hw); + cl_dyn_bcast_rate_init(cl_hw); + cl_wrs_api_init(cl_hw); + cl_dfs_init(cl_hw); + cl_tx_inject_init(cl_hw); + cl_noise_init(cl_hw); + cl_twt_init(cl_hw); + cl_fw_dbg_trigger_based_init(cl_hw); + cl_stats_init(cl_hw); + cl_vendor_timer_init(cl_hw); + + return 0; + +out_free: + cl_main_free(cl_hw); + + return ret; +} + +static int _cl_main_init(struct cl_chip *chip, struct cl_hw *cl_hw) +{ + int ret = 0; + + if (cl_chip_is_tcv_enabled(chip, cl_hw->tcv_idx)) { + ret = __cl_main_init(cl_hw); + if (ret) { + cl_dbg_chip_err(chip, "TCV%u failed (%d)\n", cl_hw->tcv_idx, ret); + return ret; + } + } else { + ieee80211_unregister_hw(cl_hw->hw); + } + + return ret; +} + +int cl_main_init(struct cl_chip *chip, const struct cl_driver_ops *drv_ops) +{ + int ret = 0; + + /* All cores needs to be reset first (once per chip) */ + cl_main_reset(chip, &all_controller_reg); + + ret = cl_prepare_hw(chip, TCV0, drv_ops); + if (ret) { + cl_dbg_chip_err(chip, "cl_prepare_hw for TCV0 failed %d\n", ret); + return ret; + } + + ret = cl_prepare_hw(chip, TCV1, drv_ops); + if (ret) { + cl_dbg_chip_err(chip, "cl_prepare_hw for TCV1 failed %d\n", ret); + cl_free_hw(chip->cl_hw_tcv0); + return ret; + } + + ret = cl_rf_boot(chip); + if (ret) { + cl_dbg_chip_err(chip, "cl_rf_boot failed %d\n", ret); + return ret; + } + + ret = cl_dsp_load_regular(chip); + if (ret) { + cl_dbg_chip_err(chip, "cl_dsp_load_regular failed %d\n", ret); + return ret; + } + + ret = _cl_main_init(chip, chip->cl_hw_tcv0); + if (ret) { + cl_free_chip(chip); + return ret; + } + + ret = _cl_main_init(chip, chip->cl_hw_tcv1); + if (ret) { + _cl_main_deinit(chip->cl_hw_tcv0); + cl_free_chip(chip); + return ret; + } + + return ret; +} From patchwork Thu Jun 17 15:59:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4169DC49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 110/256] cl8k: add main.h Date: Thu, 17 Jun 2021 15:59:57 +0000 Message-Id: <20210617160223.160998-111-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:34 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 40c7516c-8c6a-4a8a-0346-08d931a99a13 X-MS-TrafficTypeDiagnostic: AM0P192MB0402: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Daz+ZZS0my/7hL4VKQt+nf39k9nISlu/HLv9jVCMXO52UIET7Pyhx3LG0WxTAFRQRVoRuK+RlmJTitaWhp9Mx64qHRJcLZGfBCU/9ZMCDmxih7697j2MAib3eZ4377P70DSQUpjWv8M5FsuvdxSHyOLdAyHEDr6YfVpN94sSS8DTJreQgeZJXQQNcq7UGivS+Wib8bP8Er0CpzT1Sbjqms2z8BykGKdP+1/Y7Uzs9SVMDjMs5dKbA9n/sI8/7uexcQBxP2bfHoKH7i7XCF6XE8npJg07EhzP79YYcSZXF++Fl7rtCmgtiKPMfNIddj9Ke0BNSA7xrnneMcIVKqipJ8mdpa5uAXxnJtj6K6c2bL9sWaZCwDLAAh5qD/X3R6uf7LhyWpUIRcfzkHIMtD97sZTre74LQYeF94LldWMs3h5HhGrPBEmkApQwBBSIvXavh2iZb7NjKDdvACZJ8nFzN0hyCqKSKj17OeyZPeMG+vWLPxFxBS07Zs/NYMDbqk2lhyj3hgngKS59H2G52vBw5K4xZtZbsOZO8wSQBpPq6wU5hiwbyWlWpMARMCaVJBNGO9npvWMtgURWwwet6BnMXT4DM4l53j5qO6CPxWOw/v7GIURXgZ8xSwLhMjtJwmKlldGsmQ9oIGJMPOJFIuc6N6ZrPj5TzUK541Est8c7VVGQeLdWhbPVJILt2+Qe3DumxV0zZzWBiCDPPOsizwkjKA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39850400004)(136003)(376002)(396003)(366004)(346002)(6916009)(6512007)(9686003)(6666004)(52116002)(2616005)(186003)(16526019)(38100700002)(38350700002)(1076003)(6506007)(5660300002)(107886003)(55236004)(86362001)(6486002)(8936002)(956004)(26005)(8676002)(508600001)(2906002)(36756003)(54906003)(316002)(66946007)(66556008)(4326008)(66476007)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 24JqpNsTa3i+V26dr2tzCK75M1+jbTkzX/mT/lqPrymxcm6s/ryLpCRCP+WWVFLDNZB57lut5iCHtW1nTzsbwC1Dfs2Tg5rttjSCvCk0YbwTgN/BkLKxzCS8rTfyP6tECZ7OkBOpZWncL6shyfzrhjj6ovKdV/0bGaiR9ngLfAZs71/1Fx+sKZkYhGXGPE73hwgbZZ6HUCbJ6FGervZuSw+hvXkxiwmtXtBUmpOhLzTGZIXST2b3O729zUFPHYfoNJjM1c09YbP/zWvEvF5ujwNcwj0fb1s87equjJIjMtP2pgb/JiBM4PxxOjPIHbeebH2CU96O3foywNBislYw7w1RSpHOekl1E4oilwb2iDQBVv1Hca9Xaq6EXsoM2cDMgjyGR0e9BOBuayBLONJVPB9GTIDiwI8oVKig+lyg7WLhjfaipr2tkoSkyv5VoTsghd+aL4nof0WPSOLNIfHENXeqdm2IYnBIt2mdDKj+C/g60iR6c29OCypY1YgOQOhgisq/x90ocqnvYJ7oxxGP87hlfX3FyCTLLaUPmDLPBQzJIB9JI/Tx3VJG6iqA+FnrA69iZluisRf6UJrwpn26xKmAK5v4yjnZliMR82hWwy6nWLsAvMtQQXvCrj8DB9fOm7lI8xHONqt0haZwYRQsmfrR9D2rO64xUYUdG4msAn6fJSd1x+xEhDtrVOz1YsUZJerulMYlgTBlXPviY1S6/xk1QyTqGZJ36bcb0+YKxVV4xeHt5UNA1DHfI1Q/o1V/MHxQ8xnKJP2AtFMjuw76tn1OreNYQ6mdw7d0JIJJpB7xC6HgIkdTCZSTjZP8OAy4bKc87ExD4N8B9vovpyw4URBYeRZH6nkgJqdzvMjH2Jvz6ablnP9qAPg1pMGL8WihUVfssSw4EGpWvmEoCQXsFF2QmPrfWwmFk8DrPRPtUelYBlinCUVbW6Hr6kNypiLTgtyEtWwfE7DtPj5kQS8vNnM8CPbTO0uvZ4qoZ6WPWMTbE3k3mrmzu9AHEebrEUotMyP90INLmbLEZzXZpfPBlC5yhq98402nRbPtgYpvLVOmnoZV0GRBnOEsZSOvlBw/KHcln52KaWQQg9EittD+9rTvqnpa00vr8N/dI6+4UKv6H0EZfNim6sfPeJ88tzDXetNzhVsPCvzlR7rXkEtRBtIMtpkS8rLMcFIcxuOWqhS84GJMbArD2p8SKnJJgef2/G4P8PBmOL1cZtPMwBhh6ivc9pF+BhG02onTcjiwLpoeTfBw1FEzXGPIpXj6ESVwpWZhNsxpAWL5Kbn4PSV5urrnu7nDGsxUSAaMfskmFGC4wo14qrQY2h7gW5J57MbX X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40c7516c-8c6a-4a8a-0346-08d931a99a13 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:35.5161 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: w//oo8B3xMbujRjDxS4xOSUbdSFPmfubiVkigoW3lT+y2c+wW0HrPA3MSja8/t2mjvpxmMbQdujUmOuFdLnnwg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0402 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/main.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/main.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/main.h b/drivers/net/wireless/celeno/cl8k/main.h new file mode 100644 index 000000000000..8fab87e715f5 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/main.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_MAIN_H +#define CL_MAIN_H + +#include "chip.h" +#include "hw.h" + +int cl_main_init(struct cl_chip *chip, const struct cl_driver_ops *drv_ops); +void cl_main_deinit(struct cl_chip *chip); +void cl_main_reset(struct cl_chip *chip, struct cl_controller_reg *controller_reg); +int cl_main_on(struct cl_hw *cl_hw); +void cl_main_off(struct cl_hw *cl_hw); + +#endif /* CL_MAIN_H */ From patchwork Thu Jun 17 15:59:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4805EC48BE5 for ; Thu, 17 Jun 2021 16:06:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3350761003 for ; Thu, 17 Jun 2021 16:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230438AbhFQQIp (ORCPT ); Thu, 17 Jun 2021 12:08:45 -0400 Received: from mail-eopbgr70075.outbound.protection.outlook.com ([40.107.7.75]:41442 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231876AbhFQQHu (ORCPT ); Thu, 17 Jun 2021 12:07:50 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cHTac60/se8wEN4f86nfZ6E8cxBdIjYNi9Bvw5bhXbJyhHwrw6TGSXJW7xKmCNeTyk6POhTy6UkmlFhXQXulzeOyhG6xzkoXpikbaNpDym1tWvEOftpBh3KFq/JbA8adPuFWoXPhjP7nb9JR0U35KleNSyFDZLXzT8GicGUr6rbm2ndyYXgSjRu3vRq1iX+AC2VD0BOV/GwbU7kCxfjA5gbG5fJTcyrhn+x5BVOlSHvnU/ZkMJ11Wxzo9/H2A4uVdvf0wcBy2VOR7ty9ua/dzVB/UltOrcYdzfW2QB7nfT/OZhEPExo+aqXMJVze4Dj65LOzocNoPn+HrK2BRkMdAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iIUeCH1SRGvG0645fMOYbUAFw+2xRJhEtIcsZO2qp/A=; b=W529/7WtP8YfQi0pusrKsTuR3c6HgfNyQh9YRnbvjZKtPA4Jw+P18mpfTm5S1tviG49GtwmhyIaz1mSedP/F0rVBJnaC5GY7ZIxvx8geS+AQVET4oJGBdLPh0GqZNxS19MB7c+6HcPJdSdKB6saqzidTjcVydD6sxyjFZl597EvU7VWipftNDLxA12JqMy8UDkPCsFyi6MmsCDoW036PKEAqGBzjeb9Dfd9Ovm7Lm1r6a/jNdS4mHVLHdrxVv01HryRKxcB2BY+01xrpxSFK7u5xDrcgFF8YkQ+Iut0pe0binfOYmgXPBniuSvzmLaq3VJyIQHW3XFMlcEZeuTgsEw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iIUeCH1SRGvG0645fMOYbUAFw+2xRJhEtIcsZO2qp/A=; b=yzV/+oo2XegmO4RdtC4AwwSxD1RYKyf5+WYfaLaK2SgVRaeyZs2vBJhbuE/t3iO5n2wLngH01fVQqPaHtTwX6M7PknK7y+zgTZhoeH9xV6DWFPs5oDeJ0JMex5tNqR7fiseINfPEzrfe/gRHc8lMczKvXEJ2OI+iNymPjPrTLSM= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0402.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:46::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18; Thu, 17 Jun 2021 16:05:09 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:09 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 112/256] cl8k: add maintenance.h Date: Thu, 17 Jun 2021 15:59:59 +0000 Message-Id: <20210617160223.160998-113-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:37 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac3a67ab-d5ab-4204-bf04-08d931a99b69 X-MS-TrafficTypeDiagnostic: AM0P192MB0402: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BnqxaMRwA0xPuP6ZAEK+/RVc0vAk/pX1xwGKeqUiQG7NVrfrhbtveFvxvnISTrItyXJf0Awx1G7/l2xW6Q2E59lpidTZ4cTmVpmA+L+xRW6qkeRYf9A4zUq60QLdKrjiUYdhunuXfKYo84GCpFTaoRgOXZI+yudyMyMEcpT5HKBUVj8jNfF1gdPAGX4plNKso7l8eV84gbrCd0ssdtYW5JDttpSfyMXG1ehgAS3AKnVx9JYwveuf7GhCOgzkhEykJrZ323AebUQd4DoGBvnjbLlpRRGWDkxSjZJuQ9LI36sw7lD9Ob3pN3RlJFA/RSJL20S25sPw43IAShsLG4IpF8jVCUzMpVuOZJAv80Od+CrRbI43Va7HrEY+xiNnyPIPRbOIlSgrhZx8qNR8bJVpECciZ17AERq6R6mgiUMvlYq6GC/lAPWDQOzSi6MWDnuqG+xYFGCVQ3k8qATaLzi9amLJjGLiJ4YE4khLU4EBxl2pxzCGAKF1uv8tFcwLjdNBKirDE9g8vNRBvfHsMjPRfLAF0R3i+uZTfX/Nv0YL6UmEUf8u4K7bcMjU504RARFSssk8tjEsDHyMTJ7gLUnw5K40pIF9Lg3ZXIyqlX/X+TKxZsIEZf0B2+9PJtDlPI73QLgGV138cZQTjB2l4sun5YZkgVuHEGUxDXVy2p2/wY3lRICxIFtuTt3u/gfkCZpolEnmzZdUYIGLJs21qH4vdg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39850400004)(136003)(376002)(396003)(366004)(346002)(6916009)(6512007)(9686003)(6666004)(52116002)(2616005)(186003)(16526019)(38100700002)(38350700002)(1076003)(6506007)(5660300002)(107886003)(55236004)(86362001)(6486002)(8936002)(956004)(26005)(8676002)(508600001)(2906002)(36756003)(54906003)(316002)(66946007)(66556008)(4326008)(66476007)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: McWpxNSHq8+HJqQegxhZmWfooulImwu9Nuw4s5UjuPttJCwWWWbxy0swj42a5wj22tT6AB0KIonQVgJRDC8zaNbaL+Sc9u+Y2R6bWPWLeYHcBt2iuYbOJVfmjIiyZ8RKPWwDgZRQ1lXtsDetRpvMoyRVfABd3UVeelohigyTG8rrJRrbl0u1zmvf2e4JN83orOzSI5I6RPdalvwYQ6V92A+YDCAeIMjFIIVagPbaRyBPnrKDA8HfSky8Qv724EZCDEeZ9VJdcsF7NnKewibEFMKZvjEwFi0E9ZCWdPAQdHxNh4cD7JDqlHoO64N8+Kk7isawt+1c/TArti6kV/2kdijRXDlOmYU8NKZQjfbxYV+nbOnKIGkjxiKDm4E9zNUwQmwIk/BZOXUtBhf3SMdW5XrySCFo9lzmpH0PZfdVl54gkBXk8dk2hCSPwBCt22rmOEMrOooHG9TB7QvABa6tCYhfOxgoz0toXdLHpNPRGo6oGhPAKgrtNQ1fYHhgv7Bu2LHkJedoIX6ZX5MUZq+M4difwN155JoTrl4MTrX136A+w8aM8uroXvCLFJiKMDek3OachTPEq9VFE3UBWVe8LgNtlhoFShAuEjW81EIAXvTg+ERlaOv525Hm+oaUvdJkv8A1XcbFFJ+eIbzcK7jQvw5stCCG1e2B488nzqv76MPVe9mjI+98Et/m/H47Bk3QfnkqYfYonLUc4axkZT6H0XXAU6TEUyYSeWSyx1QCy6/fum+zQ7VJRH6iRVEYR/AgH69H1zp0u8F/lPLNrlhXXPnoOwGT+hcjbmoblsrNC2TWuF2TMX2kY6rEYFlt0Yf9cKnrIzWXK6DTE9IAICbGTk5HdOu9oMhejQA75esr+7towFqH7Z1hqq+pen9ATkURMyS3M05p6qDq3NtM2P4AFbLK2dtHDsKlX2xdH5azgQKvZIUQ0pHlGfzQKttjM/OFnTRvl0KjxioWWQFCWZw/SCxkpblsVA2V1Yfgc3eFx4Rtyh4kn+CVgC3pGMlIXg83vfC0KFmM79lVOuVFd1GvVTB6gB9kKyA9MuOkw+HnBukADl28j72n6mY35Tjp9sEX/UU3CW42LWEHEBjGHPzIoVcZLfssyElLwXFNiInKDZBEfv3F5FndGWhWcy5j8bO14D6MZphB6j9ta3qRnNvhWdc/DarR3M82JsJhp9YXtzEfSAO2Bjs2tJo1861gCKYpEf5odB/Tgo4cYCVZnF6Lu20ra1SogEWwl6Hy9jEoxhcRWwCnOT7Fkos0r6PJlDkGDoMcTPcvBGEk7ua2bsgKfWXXGktTVi7uYD1AQvoiybLhjy7/UNIuN6m57Hsg4lWZ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ac3a67ab-d5ab-4204-bf04-08d931a99b69 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:37.7592 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IZh1hRDTsavOcvB2/iE+/WRUlaFQ0nZw3u8rghHAvNG1U8O3ED0gn5DOw7eXDsQZFiAOIPi9QqoSbV9wkOAAEQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0402 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/maintenance.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/maintenance.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/maintenance.h b/drivers/net/wireless/celeno/cl8k/maintenance.h new file mode 100644 index 000000000000..456aa4e75d4b --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/maintenance.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_MAINTENANCE_H +#define CL_MAINTENANCE_H + +#include "hw.h" + +#define CL_MAINTENANCE_PERIOD_SLOW_MS 1000 +#define CL_MAINTENANCE_PERIOD_FAST_MS 100 + +void cl_maintenance_init(struct cl_hw *cl_hw); +void cl_maintenance_close(struct cl_hw *cl_hw); +void cl_maintenance_stop(struct cl_hw *cl_hw); +void cl_maintenance_start(struct cl_hw *cl_hw); + +#endif /* CL_MAINTENANCE_H */ From patchwork Thu Jun 17 16:00:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A729C49EAF for ; Thu, 17 Jun 2021 16:07:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E413760FDB for ; Thu, 17 Jun 2021 16:07:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232601AbhFQQJH (ORCPT ); Thu, 17 Jun 2021 12:09:07 -0400 Received: from mail-eopbgr70049.outbound.protection.outlook.com ([40.107.7.49]:64480 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229887AbhFQQIE (ORCPT ); Thu, 17 Jun 2021 12:08:04 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eqcV8oIHjUw2ZaWBOqlwZ3AMSjm27Wy4zYDs7yjEAl0vBZGXsxXR59ikZuJyNJCesZqOtSE+DGCZdIGFe5sK12Vq4pS5ESzKBWOkqMXGlDHNUB0oDsNrwS2kek18tyMNJW9yaOe74rSD07S3eVJOs8aFRNc7BCEb1pf16HipYKEISQmRSY96S9YhqI6XFFXDkDn/JZYpo9h+x3zawPtLeJ2qPQ8kisfsOHof0m27dAkPz64N2bASaFduvDgiSA6jz8NXSpDoJKBN5lFxwprwdHd5lsmExo5R4hOn5Hzm++hLFYw/DY7dzqHYUIFUO81wD7zT238x/cBwtYlGWcGhig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=y7GxUjyVSKRB3T9Jz0l2e05mJwcScmezLW9VAr0NSTU=; b=FNoeXKn5PPlhJmdTLK4jh0Pqc1+L2wZeZOB0TmcK8juYNTRy+TGcZ0vicZunTTsEtpAGjsJzn0XIHb3c0TFRcbwKnkUp9+OWriTSoDoaa4O4mmAQVXIJRoOWGBhgpNvSt6oZ9sT91X6ogYa8+Ndm8GWJ+Fq+UIypU7y7qh/eVD6B9GFQ7ll3NHgNdS74xaVuftmvAf1GPxy674+iph8AoUqLMqZPQ+ZZwmtQgABS0gZUZt6qNLqcYpKVSQbg88deBuoA0FhZb7Ssklf3JqlblPRFYj9WINd17w14n+G7BezBbFl1mLLWAE4MbHsZRgL4HUjMUrd5vjLm7oti3u4QPQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=y7GxUjyVSKRB3T9Jz0l2e05mJwcScmezLW9VAr0NSTU=; b=P5m6T2n4i9c3xcgsHXCk2JTsWdD1nJ24hJzkL6pB8LU6DW+zVbDbaL1c1Xjaeatth+J7kfgSgc7iZNe1iZJUUOReVbSdcQ0+UbRF8brgmyThiXW95g9db7kHfLLwJ5nrROKlmoyuXA+KyYNB3Um8j9xnmuTE0e1xHNwEF/oEpCo= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0402.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:46::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18; Thu, 17 Jun 2021 16:05:09 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:09 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 113/256] cl8k: add mib.c Date: Thu, 17 Jun 2021 16:00:00 +0000 Message-Id: <20210617160223.160998-114-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:38 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1e7e0d40-0710-4e00-e848-08d931a99c00 X-MS-TrafficTypeDiagnostic: AM0P192MB0402: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YRWcXAf9uu9tlxPYpFttzHs9oSHFx0oM9PfmiKLAjJPzPT3I0FQ8fH+xubXhzRRfqeQYHgQ6P0o0B0fJv3U4/P2KNBSj59LBTgaJ/v6P+X6HL5AhxmpxiHnqNrTAHT/Lqu1I4a8oT5F3nKwhry58ZLFeFtDEsrE2JHCIY3PTE3SN/czdiEjgR6F03CEzjqD5pftOHVGqF9YUFrog9hI27ykri1QSLP0Oog0PBZz5+O8bQm7dx/TSL04fOUNYINwRe8nqV/2zLrqsmxGtzJQOQjSlFriUGPnZVy8KZfrdop8G1ekUKoJc2DaFUlxc6f8ARPePj57EYMOg86quoBpONnRztOOYPw1dTIVgEGTeJn4hqXcKOEvs/io29TGAAPzAFi653WuB5Y7NlzBkqnHdcFKCXjHt8cbeGXw1u69xfFH0TzKjBDazItGOk4NkmNdscxzWEmh/gXd2ysujoFiSQQ5b+9ADxiLHD+73ScDA0z0UIlTMyyFIxb4tzQoP/M7rQJy0vbHEKWZcOwfvf7p2BbeL9BNlG16ndpnPM/tJMAgTy3WXQ2m5ewntKU39HjNo3Q0UyhgzmOR8u/xGSuutpf/+qjvC1kjmAetWJKCONuC31HlhGymxcb/mYvXd7lHQX58kFjdf/kz2lxEZq8c1ZbhdFElyrFB1/LvERp8B5d7ziZidFpOgWBs8m+8GLPPbO0FwM9Np1JdMcfySsZ77bA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39850400004)(136003)(376002)(396003)(366004)(346002)(6916009)(6512007)(9686003)(6666004)(52116002)(2616005)(186003)(16526019)(38100700002)(38350700002)(1076003)(6506007)(5660300002)(107886003)(55236004)(86362001)(6486002)(8936002)(956004)(26005)(8676002)(30864003)(508600001)(2906002)(36756003)(54906003)(316002)(66946007)(66556008)(4326008)(66476007)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /6iEEqoM2bElpVMFc5lCW9PP/9pQFgZkERQtsZZBUzVOL71FRG2IaQKqYAeYSDz+SaMcXeR9MNl295lFITIC8gCMZ4ufBhJNMAlE25GthEm4Dhv+LaPZ8Q8V1OBi0bxctaS13iJNdLLxLlOUh3268C39tqOHTWmelXRO/dC4X8iAIpAfgj7IbA3Pk0pEUxIMBFI4CstRIRGqb5ahNJLJRrVpHrtHdrV07rAjxbSuMNUAjNRPnXv+HFKMPpe+aAtXb6XMcUIMomRtaC2XfZwSFSJgeQmzspNkIvIfhcWjwet0Sf9TkfXQ549rbr0mEHObji9IICsGY/QP4ve14d6t8KM7evaMZJFU7KHrSdBFOR0Zw1v4AYSk8l1b4GKJwEvY0QxRsNQAk79TgWiRpIc+bBtDUD2I4q9YvfCXyDYpbXAHXYj7RLxyf5eKQTwwNLfhU5VG61FQJGCOjbuGVvFnDOhl2WEyVYMriaYsumFlSZcXaY78hjj3uZkqcGa80i4Q99nTdF2I+x+gK+8zN4eA074a0OlLHMJRwCZqOLuZUCd7MYX1LRGX2XvNO0syp1YdcDP3Fne5dRYQ9EpG2A4LVGjj/8qjFSwoAeJohT4tmSHV5C0L/z/xCaR729GdPQEY8J4i+i3OOPSq8gh+99gqZLE6zlZsbI+qSjpVM9X2b1RklrANK/mBt3IeJ5wRFaOoskvERe+xhsgn7KB67YVzTDpiDom5EssFIJ8IWY9TI4Dn/XnrGvoRbi7kjdSyugGJ2FzUoOnWIHc3Kn7kQdhbDegDfO9o3Fx25mzFNa0YTw27+KwXc8ZXPFwpRf/uaz4GzLeqFyrpVf8uWrlG5k/RBIxOx5uK2OImN56APmEYO76SI+r6/xoUneL4QrUcKR/pFhSkK8mP6ZLgnlppOKK5aLSaht7I1q5EJbc2vRs4zrj4zcvUytWleC6pQjCivl/lvKPOnqdrOZq/Hnn6sUt0g3DbCdyq12MFz7VEw/mmS1g0MxOGUY2Rahe3HE/HqcRqjAE3pU200D6f3phpBLePM70CzCPZ6EZjMQCCjgjj4u7OuGHcaeauRGGGDybgVAsi911rMqK/ad4TKASG7xnKAJbqBbyZ80o79nhDQ/ndsU0p81e/gT5Olcq6w8Y0XkeANWEpFam2nF8gsaAkp7XDcsCFcIrXNaFnkOovObczBZ3I64GxToZUS1TePWOayzCRZ00JB+8mR21aO/P2sbSErtyXqYQhBW/VETvYrheixZAG59RpZnNH370wzlwdxaNw4dQLx6Q3rU//4I/xfthO4F7GnC7aLDSFmP8/A6n06rNJB5FT6LkS5sPWfTVRkdN3 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e7e0d40-0710-4e00-e848-08d931a99c00 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:38.8544 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cIEiP9lhLCczHLtygNjx8Ma3wPddeUsmVUZpKclHNrxUBcLhx9f8Ydd4iWavSu6DO/vhcieN2yPkawLrNErgvg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0402 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/mib.c | 437 +++++++++++++++++++++++++ 1 file changed, 437 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/mib.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/mib.c b/drivers/net/wireless/celeno/cl8k/mib.c new file mode 100644 index 000000000000..946043dddd5d --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/mib.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "mib.h" +#include "reg/reg_access.h" + +#define NUM_OF_MIB_COUNTERS 254 +#define MIB_REG_OFFSET 0x800 + +static void init_mib_counter_arr(char *mib_counter_names_arr[NUM_OF_MIB_COUNTERS]) +{ + /* + * MIB element to count the number of unencrypted frames that have been + * discarded + */ + mib_counter_names_arr[0] = "dot11_wep_excluded_count"; + + /* MIB element to count the receive FCS errors */ + mib_counter_names_arr[1] = "dot11_fcs_error_count"; + /* + * MIB element to count the number of PHY Errors reported during a + * receive transaction. + */ + mib_counter_names_arr[2] = "nx_rx_phy_error_count"; + /* + * MIB element to count the number of times the receive FIFO has + * overflowed + */ + mib_counter_names_arr[3] = "nx_rx_Discard_RHD"; + /* + * MIB element to count the number of times underrun has occurred on the + * transmit side + */ + mib_counter_names_arr[4] = "nx_tx_underrun_count"; + + /* MIB element to count unicast transmitted MPDU */ + mib_counter_names_arr[5] = "nx_qos_utransmitted_mpdu_count[0]"; + mib_counter_names_arr[6] = "nx_qos_utransmitted_mpdu_count[1]"; + mib_counter_names_arr[7] = "nx_qos_utransmitted_mpdu_count[2]"; + mib_counter_names_arr[8] = "nx_qos_utransmitted_mpdu_count[3]"; + mib_counter_names_arr[9] = "nx_qos_utransmitted_mpdu_count[4]"; + mib_counter_names_arr[10] = "nx_qos_utransmitted_mpdu_count[5]"; + mib_counter_names_arr[11] = "nx_qos_utransmitted_mpdu_count[6]"; + mib_counter_names_arr[12] = "nx_qos_utransmitted_mpdu_count[7]"; + /* MIB element to count group addressed transmitted MPDU */ + mib_counter_names_arr[13] = "nx_qos_gtransmitted_mpdu_count[0]"; + mib_counter_names_arr[14] = "nx_qos_gtransmitted_mpdu_count[1]"; + mib_counter_names_arr[15] = "nx_qos_gtransmitted_mpdu_count[2]"; + mib_counter_names_arr[16] = "nx_qos_gtransmitted_mpdu_count[3]"; + mib_counter_names_arr[17] = "nx_qos_gtransmitted_mpdu_count[4]"; + mib_counter_names_arr[18] = "nx_qos_gtransmitted_mpdu_count[5]"; + mib_counter_names_arr[19] = "nx_qos_gtransmitted_mpdu_count[6]"; + mib_counter_names_arr[20] = "nx_qos_gtransmitted_mpdu_count[7]"; + /* + * MIB element to count the number of MSDUs or MMPDUs discarded + * because of retry-limit reached + */ + mib_counter_names_arr[21] = "dot11_qos_failed_count[0]"; + mib_counter_names_arr[22] = "dot11_qos_failed_count[1]"; + mib_counter_names_arr[23] = "dot11_qos_failed_count[2]"; + mib_counter_names_arr[24] = "dot11_qos_failed_count[3]"; + mib_counter_names_arr[25] = "dot11_qos_failed_count[4]"; + mib_counter_names_arr[26] = "dot11_qos_failed_count[5]"; + mib_counter_names_arr[27] = "dot11_qos_failed_count[6]"; + mib_counter_names_arr[28] = "dot11_qos_failed_count[7]"; + /* + * MIB element to count number of unfragmented MSDU's or MMPDU's + * transmitted successfully after 1 or more transmission + */ + mib_counter_names_arr[29] = "dot11_qos_retry_count[0]"; + mib_counter_names_arr[30] = "dot11_qos_retry_count[1]"; + mib_counter_names_arr[31] = "dot11_qos_retry_count[2]"; + mib_counter_names_arr[32] = "dot11_qos_retry_count[3]"; + mib_counter_names_arr[33] = "dot11_qos_retry_count[4]"; + mib_counter_names_arr[34] = "dot11_qos_retry_count[5]"; + mib_counter_names_arr[35] = "dot11_qos_retry_count[6]"; + mib_counter_names_arr[36] = "dot11_qos_retry_count[7]"; + /* MIB element to count number of successful RTS Frame transmission */ + mib_counter_names_arr[37] = "dot11_qos_rts_success_count[0]"; + mib_counter_names_arr[38] = "dot11_qos_rts_success_count[1]"; + mib_counter_names_arr[39] = "dot11_qos_rts_success_count[2]"; + mib_counter_names_arr[40] = "dot11_qos_rts_success_count[3]"; + mib_counter_names_arr[41] = "dot11_qos_rts_success_count[4]"; + mib_counter_names_arr[42] = "dot11_qos_rts_success_count[5]"; + mib_counter_names_arr[43] = "dot11_qos_rts_success_count[6]"; + mib_counter_names_arr[44] = "dot11_qos_rts_success_count[7]"; + /* MIB element to count number of unsuccessful RTS Frame transmission */ + mib_counter_names_arr[45] = "dot11_qos_rts_failure_count[0]"; + mib_counter_names_arr[46] = "dot11_qos_rts_failure_count[1]"; + mib_counter_names_arr[47] = "dot11_qos_rts_failure_count[2]"; + mib_counter_names_arr[48] = "dot11_qos_rts_failure_count[3]"; + mib_counter_names_arr[49] = "dot11_qos_rts_failure_count[4]"; + mib_counter_names_arr[50] = "dot11_qos_rts_failure_count[5]"; + mib_counter_names_arr[51] = "dot11_qos_rts_failure_count[6]"; + mib_counter_names_arr[52] = "dot11_qos_rts_failure_count[7]"; + /* MIB element to count number of MPDU's not received ACK */ + mib_counter_names_arr[53] = "nx_qos_ack_failure_count[0]"; + mib_counter_names_arr[54] = "nx_qos_ack_failure_count[1]"; + mib_counter_names_arr[55] = "nx_qos_ack_failure_count[2]"; + mib_counter_names_arr[56] = "nx_qos_ack_failure_count[3]"; + mib_counter_names_arr[57] = "nx_qos_ack_failure_count[4]"; + mib_counter_names_arr[58] = "nx_qos_ack_failure_count[5]"; + mib_counter_names_arr[59] = "nx_qos_ack_failure_count[6]"; + mib_counter_names_arr[60] = "nx_qos_ack_failure_count[7]"; + /* MIB element to count number of unicast MPDU's received successfully */ + mib_counter_names_arr[61] = "nx_qos_ureceived_mpdu_count[0]"; + mib_counter_names_arr[62] = "nx_qos_ureceived_mpdu_count[1]"; + mib_counter_names_arr[63] = "nx_qos_ureceived_mpdu_count[2]"; + mib_counter_names_arr[64] = "nx_qos_ureceived_mpdu_count[3]"; + mib_counter_names_arr[65] = "nx_qos_ureceived_mpdu_count[4]"; + mib_counter_names_arr[66] = "nx_qos_ureceived_mpdu_count[5]"; + mib_counter_names_arr[67] = "nx_qos_ureceived_mpdu_count[6]"; + mib_counter_names_arr[68] = "nx_qos_ureceived_mpdu_count[7]"; + /* + * MIB element to count number of group addressed MPDU's received + * successfully + */ + mib_counter_names_arr[69] = "nx_qos_greceived_mpdu_count[0]"; + mib_counter_names_arr[70] = "nx_qos_greceived_mpdu_count[1]"; + mib_counter_names_arr[71] = "nx_qos_greceived_mpdu_count[2]"; + mib_counter_names_arr[72] = "nx_qos_greceived_mpdu_count[3]"; + mib_counter_names_arr[73] = "nx_qos_greceived_mpdu_count[4]"; + mib_counter_names_arr[74] = "nx_qos_greceived_mpdu_count[5]"; + mib_counter_names_arr[75] = "nx_qos_greceived_mpdu_count[6]"; + mib_counter_names_arr[76] = "nx_qos_greceived_mpdu_count[7]"; + /* + * MIB element to count the number of unicast MPDUs not destined to + * this device received successfully. + */ + mib_counter_names_arr[77] = "nx_qos_ureceived_other_mpdu[0]"; + mib_counter_names_arr[78] = "nx_qos_ureceived_other_mpdu[1]"; + mib_counter_names_arr[79] = "nx_qos_ureceived_other_mpdu[2]"; + mib_counter_names_arr[80] = "nx_qos_ureceived_other_mpdu[3]"; + mib_counter_names_arr[81] = "nx_qos_ureceived_other_mpdu[4]"; + mib_counter_names_arr[82] = "nx_qos_ureceived_other_mpdu[5]"; + mib_counter_names_arr[83] = "nx_qos_ureceived_other_mpdu[6]"; + mib_counter_names_arr[84] = "nx_qos_ureceived_other_mpdu[7]"; + /* + * MIB element to count the number of MPDUs received with retry bit + * set + */ + mib_counter_names_arr[85] = "dot11_qos_retries_received_count[0]"; + mib_counter_names_arr[86] = "dot11_qos_retries_received_count[1]"; + mib_counter_names_arr[87] = "dot11_qos_retries_received_count[2]"; + mib_counter_names_arr[88] = "dot11_qos_retries_received_count[3]"; + mib_counter_names_arr[89] = "dot11_qos_retries_received_count[4]"; + mib_counter_names_arr[90] = "dot11_qos_retries_received_count[5]"; + mib_counter_names_arr[91] = "dot11_qos_retries_received_count[6]"; + mib_counter_names_arr[92] = "dot11_qos_retries_received_count[7]"; + /* + * MIB element to count the number of unicast A-MSDUs that were + * transmitted successfully + */ + mib_counter_names_arr[93] = "nx_utransmitted_amsdu_count[0]"; + mib_counter_names_arr[94] = "nx_utransmitted_amsdu_count[1]"; + mib_counter_names_arr[95] = "nx_utransmitted_amsdu_count[2]"; + mib_counter_names_arr[96] = "nx_utransmitted_amsdu_count[3]"; + mib_counter_names_arr[97] = "nx_utransmitted_amsdu_count[4]"; + mib_counter_names_arr[98] = "nx_utransmitted_amsdu_count[5]"; + mib_counter_names_arr[99] = "nx_utransmitted_amsdu_count[6]"; + mib_counter_names_arr[100] = "nx_utransmitted_amsdu_count[7]"; + /* + * MIB element to count the number of group-addressed A-MSDUs that were + * transmitted successfully + */ + mib_counter_names_arr[101] = "nx_gtransmitted_amsdu_count[0]"; + mib_counter_names_arr[102] = "nx_gtransmitted_amsdu_count[1]"; + mib_counter_names_arr[103] = "nx_gtransmitted_amsdu_count[2]"; + mib_counter_names_arr[104] = "nx_gtransmitted_amsdu_count[3]"; + mib_counter_names_arr[105] = "nx_gtransmitted_amsdu_count[4]"; + mib_counter_names_arr[106] = "nx_gtransmitted_amsdu_count[5]"; + mib_counter_names_arr[107] = "nx_gtransmitted_amsdu_count[6]"; + mib_counter_names_arr[108] = "nx_gtransmitted_amsdu_count[7]"; + /* + * MIB element to count number of AMSDU's discarded because of retry + * limit reached + */ + mib_counter_names_arr[109] = "dot11_failed_amsdu_count[0]"; + mib_counter_names_arr[110] = "dot11_failed_amsdu_count[1]"; + mib_counter_names_arr[111] = "dot11_failed_amsdu_count[2]"; + mib_counter_names_arr[112] = "dot11_failed_amsdu_count[3]"; + mib_counter_names_arr[113] = "dot11_failed_amsdu_count[4]"; + mib_counter_names_arr[114] = "dot11_failed_amsdu_count[5]"; + mib_counter_names_arr[115] = "dot11_failed_amsdu_count[6]"; + mib_counter_names_arr[116] = "dot11_failed_amsdu_count[7]"; + /* + * MIB element to count number of A-MSDU's transmitted successfully + * with retry + */ + mib_counter_names_arr[117] = "dot11_retry_amsdu_count[0]"; + mib_counter_names_arr[118] = "dot11_retry_amsdu_count[1]"; + mib_counter_names_arr[119] = "dot11_retry_amsdu_count[2]"; + mib_counter_names_arr[120] = "dot11_retry_amsdu_count[3]"; + mib_counter_names_arr[121] = "dot11_retry_amsdu_count[4]"; + mib_counter_names_arr[122] = "dot11_retry_amsdu_count[5]"; + mib_counter_names_arr[123] = "dot11_retry_amsdu_count[6]"; + mib_counter_names_arr[124] = "dot11_retry_amsdu_count[7]"; + /* + * MIB element to count number of bytes of an A-MSDU that was + * transmitted successfully + */ + mib_counter_names_arr[125] = "dot11_transmitted_octets_in_amsdu[0]"; + mib_counter_names_arr[126] = "dot11_transmitted_octets_in_amsdu[1]"; + mib_counter_names_arr[127] = "dot11_transmitted_octets_in_amsdu[2]"; + mib_counter_names_arr[128] = "dot11_transmitted_octets_in_amsdu[3]"; + mib_counter_names_arr[129] = "dot11_transmitted_octets_in_amsdu[4]"; + mib_counter_names_arr[130] = "dot11_transmitted_octets_in_amsdu[5]"; + mib_counter_names_arr[131] = "dot11_transmitted_octets_in_amsdu[6]"; + mib_counter_names_arr[132] = "dot11_transmitted_octets_in_amsdu[7]"; + /* + * MIB element to counts the number of A-MSDUs that did not receive an + * ACK frame successfully in response + */ + mib_counter_names_arr[133] = "dot11_amsdu_ack_failure_count[0]"; + mib_counter_names_arr[134] = "dot11_amsdu_ack_failure_count[1]"; + mib_counter_names_arr[135] = "dot11_amsdu_ack_failure_count[2]"; + mib_counter_names_arr[136] = "dot11_amsdu_ack_failure_count[3]"; + mib_counter_names_arr[137] = "dot11_amsdu_ack_failure_count[4]"; + mib_counter_names_arr[138] = "dot11_amsdu_ack_failure_count[5]"; + mib_counter_names_arr[139] = "dot11_amsdu_ack_failure_count[6]"; + mib_counter_names_arr[140] = "dot11_amsdu_ack_failure_count[7]"; + /* + * MIB element to count number of unicast A-MSDUs received + * successfully + */ + mib_counter_names_arr[141] = "nx_ureceived_amsdu_count[0]"; + mib_counter_names_arr[142] = "nx_ureceived_amsdu_count[1]"; + mib_counter_names_arr[143] = "nx_ureceived_amsdu_count[2]"; + mib_counter_names_arr[144] = "nx_ureceived_amsdu_count[3]"; + mib_counter_names_arr[145] = "nx_ureceived_amsdu_count[4]"; + mib_counter_names_arr[146] = "nx_ureceived_amsdu_count[5]"; + mib_counter_names_arr[147] = "nx_ureceived_amsdu_count[6]"; + mib_counter_names_arr[148] = "nx_ureceived_amsdu_count[7]"; + /* + * MIB element to count number of group addressed A-MSDUs received + * successfully + */ + mib_counter_names_arr[149] = "nx_greceived_amsdu_count[0]"; + mib_counter_names_arr[150] = "nx_greceived_amsdu_count[1]"; + mib_counter_names_arr[151] = "nx_greceived_amsdu_count[2]"; + mib_counter_names_arr[152] = "nx_greceived_amsdu_count[3]"; + mib_counter_names_arr[153] = "nx_greceived_amsdu_count[4]"; + mib_counter_names_arr[154] = "nx_greceived_amsdu_count[5]"; + mib_counter_names_arr[155] = "nx_greceived_amsdu_count[6]"; + mib_counter_names_arr[156] = "nx_greceived_amsdu_count[7]"; + /* + * MIB element to count number of unicast A-MSDUs not destined to + * this device received successfully + */ + mib_counter_names_arr[157] = "nx_ureceived_other_amsdu[0]"; + mib_counter_names_arr[158] = "nx_ureceived_other_amsdu[1]"; + mib_counter_names_arr[159] = "nx_ureceived_other_amsdu[2]"; + mib_counter_names_arr[160] = "nx_ureceived_other_amsdu[3]"; + mib_counter_names_arr[161] = "nx_ureceived_other_amsdu[4]"; + mib_counter_names_arr[162] = "nx_ureceived_other_amsdu[5]"; + mib_counter_names_arr[163] = "nx_ureceived_other_amsdu[6]"; + mib_counter_names_arr[164] = "nx_ureceived_other_amsdu[7]"; + /* MIB element to count number of bytes in an A-MSDU is received */ + mib_counter_names_arr[165] = "dot11_received_octets_in_amsdu_count[0]"; + mib_counter_names_arr[166] = "dot11_received_octets_in_amsdu_count[1]"; + mib_counter_names_arr[167] = "dot11_received_octets_in_amsdu_count[2]"; + mib_counter_names_arr[168] = "dot11_received_octets_in_amsdu_count[3]"; + mib_counter_names_arr[169] = "dot11_received_octets_in_amsdu_count[4]"; + mib_counter_names_arr[170] = "dot11_received_octets_in_amsdu_count[5]"; + mib_counter_names_arr[171] = "dot11_received_octets_in_amsdu_count[6]"; + mib_counter_names_arr[172] = "dot11_received_octets_in_amsdu_count[7]"; + /* Reserved */ + mib_counter_names_arr[173] = "reserved"; + mib_counter_names_arr[174] = "reserved"; + mib_counter_names_arr[175] = "reserved"; + + mib_counter_names_arr[176] = "dot11_beamforming_frame_count"; + mib_counter_names_arr[177] = "beamforming_received_frame_count"; + mib_counter_names_arr[178] = "su_bfr_transmitted_count"; + mib_counter_names_arr[179] = "mu_bfr_transmitted_count"; + mib_counter_names_arr[180] = "bfr_received_count"; + mib_counter_names_arr[181] = "mu_received_frame_count"; + mib_counter_names_arr[182] = "respSetByFW"; + mib_counter_names_arr[183] = "respForcedByFW"; + mib_counter_names_arr[184] = "respForcedByHW"; + mib_counter_names_arr[185] = "respForcedByHW"; + mib_counter_names_arr[186] = "rxUnexpectedFrameTypeInAmpdu"; + mib_counter_names_arr[187] = "rxMultiTid"; + mib_counter_names_arr[188] = "ksrMissQosDataInAmpdu"; + mib_counter_names_arr[189] = "ksrMissMultiTid"; + mib_counter_names_arr[190] = "ksrMissQosDataInAmpduHeTB"; + mib_counter_names_arr[191] = "rxUnassociatedMgmtInHeTB"; + mib_counter_names_arr[192] = "HtpFailedMeduimCheckCount"; + mib_counter_names_arr[193] = "mibRxErrorVector[0]"; + mib_counter_names_arr[194] = "mibRxErrorVector[1]"; + mib_counter_names_arr[195] = "mibRxErrorVector[2]"; + mib_counter_names_arr[196] = "mibRxErrorVector[3]"; + mib_counter_names_arr[197] = "mibRxErrorVector[4]"; + mib_counter_names_arr[198] = "mibRxErrorVector[5]"; + mib_counter_names_arr[199] = "mibRxErrorVector[6]"; + mib_counter_names_arr[200] = "mibRxErrorVector[7]"; + mib_counter_names_arr[201] = "mibRxErrorVector[8]"; + mib_counter_names_arr[202] = "mibRxErrorVector[9]"; + mib_counter_names_arr[203] = "mibRxErrorVector[10]"; + + /* MIB element to count number of A-MPDUs transmitted successfully */ + mib_counter_names_arr[204] = "dot11_transmitted_ampdu_count"; + /* MIB element to count number of MPDUs transmitted in an A-MPDU */ + mib_counter_names_arr[205] = "dot11_transmitted_mpdus_in_ampdu_count"; + /* MIB element to count the number of bytes in a transmitted A-MPDU */ + mib_counter_names_arr[206] = "dot11_transmitted_octets_in_ampdu_count"; + /* MIB element to count number of unicast A-MPDU's received */ + mib_counter_names_arr[207] = "wnlu_ampdu_received_count"; + /* MIB element to count number of group addressed A-MPDU's received */ + mib_counter_names_arr[208] = "nx_gampdu_received_count"; + /* + * MIB element to count number of unicast A-MPDUs received not destined + * to this device + */ + mib_counter_names_arr[209] = "nx_other_ampdu_received_count"; + /* MIB element to count number of MPDUs received in an A-MPDU */ + mib_counter_names_arr[210] = "dot11_mpdu_in_received_ampdu_count"; + /* MIB element to count number of bytes received in an A-MPDU */ + mib_counter_names_arr[211] = "dot11_received_octets_in_ampdu_count"; + /* MIB element to count number of CRC errors in MPDU delimeter of and A-MPDU */ + mib_counter_names_arr[212] = "dot11_ampdu_delimiter_crc_error_count"; + /* + * MIB element to count number of implicit BAR frames that did not received + * BA frame successfully in response + */ + mib_counter_names_arr[213] = "dot11_implicit_bar_failure_count"; + /* + * MIB element to count number of explicit BAR frames that did not received + * BA frame successfully in response + */ + mib_counter_names_arr[214] = "dot11_explicit_bar_failure_count"; + mib_counter_names_arr[215] = "mibRxErrorVector[11]"; + mib_counter_names_arr[216] = "mibRxErrorVector[12]"; + mib_counter_names_arr[217] = "mibRxErrorVector[13]"; + mib_counter_names_arr[218] = "mibRxErrorVector[14]"; + mib_counter_names_arr[219] = "mibRxErrorVector[15]"; + /* MIB element to count the number of frames transmitted at 20 MHz BW */ + mib_counter_names_arr[220] = "dot11_20mhz_frame_transmitted_count"; + /* MIB element to count the number of frames transmitted at 40 MHz BW */ + mib_counter_names_arr[221] = "dot11_40mhz_frame_transmitted_count"; + mib_counter_names_arr[222] = "dot11_80mhz_frame_transmitted_count"; + mib_counter_names_arr[223] = "dot11_160mhz_frame_transmitted_count"; + /* MIB element to count the number of frames received at 20 MHz BW */ + mib_counter_names_arr[224] = "dot11_20mhz_frame_received_count"; + /* MIB element to count the number of frames received at 40 MHz BW */ + mib_counter_names_arr[225] = "dot11_40mhz_frame_received_count"; + mib_counter_names_arr[226] = "dot11_80mhz_frame_received_count"; + mib_counter_names_arr[227] = "dot11_160mhz_frame_received_count"; + /* MIB element to count the number of attempts made to acquire a 40 MHz TXOP */ + mib_counter_names_arr[228] = "nx_failed_20mhz_txop"; + mib_counter_names_arr[229] = "nx_succsessful_20mhz_txop"; + + mib_counter_names_arr[230] = "nx_failed_40mhz_txop"; + mib_counter_names_arr[231] = "nx_succsessful_40mhz_txop"; + + mib_counter_names_arr[232] = "nx_failed_80mhz_txop"; + mib_counter_names_arr[233] = "nx_succsessful_80mhz_txop"; + + mib_counter_names_arr[234] = "nx_failed_160mhz_txop"; + mib_counter_names_arr[235] = "nx_succsessful_160mhz_txop"; + + mib_counter_names_arr[236] = "dynamic_bw_drop_count"; + mib_counter_names_arr[237] = "static_bw_failed_count"; + + /* Reserved */ + mib_counter_names_arr[238] = "reserved"; + mib_counter_names_arr[239] = "reserved"; + + /* MIB element to count the number of times the dual CTS fails */ + mib_counter_names_arr[240] = "dot11_dualcts_success_count"; + /* + * MIB element to count the number of times the AP does not detect a collision + * PIFS after transmitting a STBC CTS frame + */ + mib_counter_names_arr[241] = "dot11_stbc_cts_success_count"; + /* + * MIB element to count the number of times the AP detects a collision PIFS after + * transmitting a STBC CTS frame + */ + mib_counter_names_arr[242] = "dot11_stbc_cts_failure_count"; + /* + * MIB element to count the number of times the AP does not detect a collision PIFS + * after transmitting a non-STBC CTS frame + */ + mib_counter_names_arr[243] = "dot11_non_stbc_cts_success_count"; + /* + * MIB element to count the number of times the AP detects a collision PIFS after + * transmitting a non-STBC CTS frame + */ + mib_counter_names_arr[244] = "dot11_non_stbc_cts_failure_count"; + mib_counter_names_arr[245] = "dot11_txund_discard_fcs_count"; + mib_counter_names_arr[246] = "dot11_rx_ampdu_incorrect_received_count"; + mib_counter_names_arr[247] = "cl_rx_class_match_count[0]"; + mib_counter_names_arr[248] = "cl_rx_class_match_count[1]"; + mib_counter_names_arr[249] = "cl_rx_class_match_count[2]"; + mib_counter_names_arr[250] = "cl_rx_class_match_count[3]"; + mib_counter_names_arr[251] = "cl_rx_class_match_count[4]"; + mib_counter_names_arr[252] = "cl_rx_class_match_count[5]"; + mib_counter_names_arr[253] = "dot11_rx_mpif_overflow_count"; +} + +void cl_mib_cntrs_dump(struct cl_hw *cl_hw) +{ + static char *mib_counter_names_arr[NUM_OF_MIB_COUNTERS]; + int i = 0; + u32 mib_reg_addr = 0; + u32 mib_reg_val = 0; + + init_mib_counter_arr(mib_counter_names_arr); + + pr_debug("------------------------------------------------------------\n"); + pr_debug("Counter Address Value\n"); + pr_debug("------------------------------------------------------------\n"); + + for (i = 0; i < NUM_OF_MIB_COUNTERS; i++) { + /* Reserved registers */ + if (i == 173 || i == 174 || i == 175 || i == 238 || i == 239) + continue; + + mib_reg_addr = MIB_REG_OFFSET + (i * 4); + mib_reg_val = cl_mib_cntr_read(cl_hw, mib_reg_addr); + + if (mib_reg_val == 0) + continue; + + pr_debug("%-40s 0x%X %u\n", + mib_counter_names_arr[i], mib_reg_addr, mib_reg_val); + } + + pr_debug("------------------------------------------------------------\n"); +} + +u32 cl_mib_cntr_read(struct cl_hw *cl_hw, u32 addr) +{ + return cl_reg_read(cl_hw, REG_MAC_HW_BASE_ADDR + addr); +} + From patchwork Thu Jun 17 16:00:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B47FCC2B9F4 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/netlink.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/netlink.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/netlink.h b/drivers/net/wireless/celeno/cl8k/netlink.h new file mode 100644 index 000000000000..7bc7f0404a73 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/netlink.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_NETLINK_H +#define CL_NETLINK_H + +#include "hw.h" +#include "vif.h" + +#define CL_NL_MAX_PAYLOAD 512 + +struct cl_nl_event { + char event_id; + char tcv_idx; + char data[CL_NL_MAX_PAYLOAD]; +}; + +enum cl_nl_event_id { + CL_NL_EVENT_ID_UNSPEC, + CL_NL_EVENT_ID_CO_LOCATE_UPDATE, + + CL_NL_EVENT_ID_MAX +}; + +void cl_netlink_send_async(struct cl_hw *cl_hw, struct cl_nl_event *event); +void cl_netlink_send_event_co_locate_update(struct cl_hw *cl_hw); + +#endif /* CL_NETLINK_H */ From patchwork Thu Jun 17 16:00:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA836C49EA4 for ; Thu, 17 Jun 2021 16:07:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A10BF60FDB for ; Thu, 17 Jun 2021 16:07:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233834AbhFQQJx (ORCPT ); Thu, 17 Jun 2021 12:09:53 -0400 Received: from mail-am6eur05on2057.outbound.protection.outlook.com ([40.107.22.57]:62080 "EHLO EUR05-AM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230292AbhFQQIi (ORCPT ); Thu, 17 Jun 2021 12:08:38 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l0qKz1F5dFw683zn1h+gOVn780kC1lsGbWiEQNSDe9iMtLcnvzczWk8DzruiCzIX5zH+64C+kkyxRy+/2cBSAdkXIJsWXKquMXMk3vVlFAZykULg8KQ2EaU3UY/MSwcg5p4tNqMhuC8cBdO4fZHlarMvidxWXrJY0Kg9XHVcSLPrVakU5OOmquHcyvpi+4fOPIiUcY3Q+nU5ZJxYGE/t7t4nUOy3y8MsydFkXbFzhgZSZNMjJPQSlp0MI/0/XisCwp/XuDRlNS7cVX2+pieyBq6tFW7L11t9ivmTz92fXsBUDXSgCzPGqAVtmyrosCVNEG+eukiLGyuCOcskFNkXmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JAG28DIo4QVVSDNtJ3nWkShyRvWvM2f8U3sApPWgAOg=; b=MN4wRqFv40Ayxywfr3EtFFqXcC7xfJYS/O4l9xRpCgQWAKGeTtQfQXy08tOrEA0fWxd+pA8cWHdIqG+vlY+uLk2ppVOViOryhegIHORWUj9QSikt7h5p0epfXPBfDsX1a1aM4O4jIxIthVifNJZIEyT/b0khnSi57G1hT6euLNRKEJWfbBbFOqHl4zyyg0tTuy693DbbVl71yc7gdgiVitNNcRZ7f4neBCrgRTl1Zp37RnCu8JG4DlwuPvj5w2yj535Fwb4Cat3XEyuPnbKHAusfVcU0lWc8z0u0GAVUickZwU+zop4alUKyg/gcw/BC/ZSMlt7z+99i8KJNnFCSkw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JAG28DIo4QVVSDNtJ3nWkShyRvWvM2f8U3sApPWgAOg=; b=m9mTLk3kw7c+c3fACaIaxPjnsTUamxR8eYcAMh3yls6oW6LveqyQkOygorEghDrgloJrL+SSVjHBcyNDZGBXVqVrzt4ny4kLfKiXmyVvp/OkVwZNJkCx1ufCq+77E1i9Hy7MtTCe40Boi5dBsE0/gUIijLRElRbxj5FTvUXBdts= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0402.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:46::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18; Thu, 17 Jun 2021 16:05:12 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:12 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 119/256] cl8k: add noise.c Date: Thu, 17 Jun 2021 16:00:06 +0000 Message-Id: <20210617160223.160998-120-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ae1a978f-3db3-4e9b-804c-08d931a9a010 X-MS-TrafficTypeDiagnostic: AM0P192MB0402: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1728; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: npY8sgtAUnDfjeGyQ1GYPEazoO2eH9s/KNjZu7ZHpEEfT8x8OjtSSG3yqpNnJuTzP+wKcKwmQnp26qSEGj5NgJNpNa/7SCUNipmDo2+YdAGOuQqFfXirT8Ia5recdlUdhh/MjHEcsfdR72As43YX503xbDdKI97agtzLu+yNgX0lEQrw9tLPwS5Xd2R6394WAC8X0Fk3HSadTJv4RpZtsFp5v5+xI79Jp0fla/31/i5K3m9jsW1BnO6UyNVVtZet6NhttfSdwaC+CIwygCYsbdh5AG6hLW72C9d6JPbXK3lTHQpCIquS1TUZaWuj94tzOAClTkd/X76cKowSaAUZP5kngcCX5nDk8jb2PMZCCv2rjTj/Dbj7nAeCbmTDEVGcnN1nSik+iIxmP/aRWiBj+gaf7h+fNMINqYqU8Cn7dbTNQ2E+5QCEGlYVTovuxSJlnk9lfybymQNknyC0rFKi+s+qySwEp6jdeG85comoWY6x6OntmnhpZ8+09Xqm0MU2jOHpvK9aKReZQEda4Srdg0oSdrrKzJ4UAHJq6EyAZ5EV68IAGFnhQ0nSxIh8FHO2LBWCblK6G3IcPQ17cqpMAxFcadcCsGsoCZ9W4tHyeHyuFrinYOZxNeOPMVIfkPRlvQrUze7CVkZ2gbNb969gaKGI1YdmfZYfDK6B8NlntPa8C1fjC2g0CSCJK4Iwl+XfKLQdyWe9Fz7so6WndtyMwg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39850400004)(136003)(376002)(396003)(366004)(346002)(6916009)(6512007)(9686003)(6666004)(52116002)(2616005)(186003)(16526019)(38100700002)(38350700002)(1076003)(6506007)(5660300002)(107886003)(55236004)(86362001)(6486002)(8936002)(956004)(26005)(8676002)(30864003)(508600001)(2906002)(36756003)(54906003)(316002)(66946007)(66556008)(4326008)(66476007)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: O4LKxvcLejaRCH/Nd1ClBNkMS7ldymbA3XIq/iDmMm46hD1Ljhqd8AHR5La5mDiZVihEpclRzfG0ZK0v6m+6RPO9AK+mUc0KJzYvAS8vxBhynXDPmW0tKzT3FdPvb3SGCR47XiQrP+ti0ta9RvT7vN8CBfL8BbUAUuyOWxQhYueSFQVLFtmBm5hMBognqWcqqCkX1GS9uZPnDg1cRjJivHzgDIOS/P4khSjrhSAmpYrriFs0HGOpaA4othN4wOBPLPfnmjomR8R2RVdEk1TwOKdQtY2WD/o1Pc15XtOqP12YiiBx1QomJpYUG7HkvEPCjCUVx2HKrkrjV5HRjI24JI8g0ifNyv1SpbV5/sdWxCTa8CIpQ6NmK2eK7DwWEni+auPK17FOQmvxL37QBqCOq5WPz41hfrCZKBe9HC3ghwWS+j/+fveYKC+ivD1Sexq5xfWlQ8rBXN9VmVi/uhMhiov7Uru5xOlblnn5fAG5ono+j6fJzOVVyOTZEs3GmPmIo3+jLCZnRJqWatj/SX/vJzu8424RJFa30zAViAQGrZS0kSMiX8WIgzf2RAjj/7c0YjONHsVefFi+i9Gq3tWt+fGNSQLdIPQE+qUN+KFUrcC6a8Cny/m447o1HbFIq4MAbLWjSj/sHhjCSdqz7YTrb66LhYJL0gejc0ZYDnwFSZhAi2NcMiwQQw+VDCK0B3jixKDtXmhjZqMLfJecfsKVUwO1N1LnXWiMLVqkMRJy/rzTvhshJs1NTRAu3jP7zguMymN0MZEkcqg4tJl4yAcqNpJKrmqzModvol2W64c1ymhmNN6cTFs8uKv1nQBDph8vF1WzCbah7L3PAlM2IKYqSMfSlFApeMgqTlaUgRxiynI87l/HYvXj+kOWABoij1Jb//aOn8qZH3wZ7PBnJaaVaOvSEnX1gC8lgbss7Xuy+E/drlhGe1dOfz3cnLC2E6a0RF3Nl0yPyv0fGHDDilSgtlj9KgTxTeSlxm9qzaVzSaXSlCPGrzo6dYz3bGF2d03dltZp/rcTRJaAxYHHCeW+EmSYgdmO8DVIgjRy1BJD2itd3NyaqgyqoD6aizEOKpygpmJ+9Vcw6uU04J3I24UKBOsQwkQVdkk8Gn+wgQOa8QQePV5QyOTe0rzhcVmRP+UZFyb/xPGvZzvT6JDTlDPlBLVXFyKmDzRvyIKV99UEl3o/RviFXTpuWzBhTCFBL+VEIDsYUkRWlA0rJglZgGpy+GtLU2TqJzM1srCgATrY0jy1WZ+FjsyU0iLC1urC+5wnnyfSsoeOL6kHVQi3fm9JDWxI60NJKGEFkjhVYU/ugLZafajFHoUfewf5c99WXJ63 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ae1a978f-3db3-4e9b-804c-08d931a9a010 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:45.6775 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BkvsIGkLwVBXYnh+hFJUvneVE/5oaamlotXyMYjN9yR+UFK3C6Zl6BoX2S0fk9Jg/w5fS7hYkONwwbx3ID0ekg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0402 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/noise.c | 499 +++++++++++++++++++++++ 1 file changed, 499 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/noise.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/noise.c b/drivers/net/wireless/celeno/cl8k/noise.c new file mode 100644 index 000000000000..0bfd025196a6 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/noise.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "hw.h" +#include "noise.h" +#include "reg/reg_riu.h" +#include "utils/utils.h" + +#define NOISE_LOWER_LIMIT -100 +#define NOISE_UPPER_LIMIT -30 +/* Range is -100dBm to -30dBm */ +#define NOISE_SCALE_RANGE (NOISE_UPPER_LIMIT - NOISE_LOWER_LIMIT + 1) +#define NOISE_MAX_SAMPLES U8_MAX +#define MAX_20M_SUB_BAND 8 +#define MAX_SEC_BW_CNT 3 +#define MAX_ANT_PER_REG 4 + +static s8 cl_noise_process_sample(u32 sample, u8 cnt) +{ + s8 val = (s8)((sample >> (8 * cnt)) & 0xff); + + if (val < NOISE_LOWER_LIMIT) + val = NOISE_LOWER_LIMIT; + else if (val > NOISE_UPPER_LIMIT) + val = NOISE_UPPER_LIMIT; + + return val; +} + +static bool cl_noise_is_hist_line_empty(u8 *hist, u8 cnt) +{ + u8 i; + + for (i = 0; i < cnt; i++) + if (hist[i] != 0) + return false; + + return true; +} + +static int cl_noise_print_hist(struct cl_hw *cl_hw, bool nasp_stats) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + struct cl_noise_reg *reg = NULL; + u8 hist[NOISE_SCALE_RANGE][MAX_ANTENNAS] = { { 0 } }; + u8 num_antennas = cl_hw->num_antennas; + s8 val_stat; + u8 i = 0, j = 0; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + if (list_empty(&noise_db->reg_list)) + return 0; + + list_for_each_entry(reg, &noise_db->reg_list, list) { + for (i = 0; i < min_t(u8, num_antennas, MAX_ANT_PER_REG); i++) { + if (nasp_stats) + val_stat = cl_noise_process_sample(reg->nasp_prim20_per_ant, i); + else + val_stat = cl_noise_process_sample(reg->np_prim20_per_ant, i); + + hist[(val_stat * -1) + NOISE_UPPER_LIMIT][i]++; + } + + if (num_antennas <= MAX_ANT_PER_REG) + continue; + + for (i = 0; i < num_antennas - MAX_ANT_PER_REG; i++) { + if (nasp_stats) + val_stat = cl_noise_process_sample(reg->nasp_prim20_per_ant2, i); + else + val_stat = cl_noise_process_sample(reg->np_prim20_per_ant2, i); + + hist[(val_stat * -1) + NOISE_UPPER_LIMIT][i + MAX_ANT_PER_REG]++; + } + } + + cl_snprintf(&buf, &len, &buf_size, + "Noise %sstrength histogram (dBm):\n", nasp_stats ? "and signal " : ""); + + cl_snprintf(&buf, &len, &buf_size, "------------------"); + for (j = 0; j < num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "-------"); + + cl_snprintf(&buf, &len, &buf_size, "\n| Noise Strength "); + + for (j = 0; j < num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "| Ant%u ", j); + + cl_snprintf(&buf, &len, &buf_size, "|\n|----------------"); + + for (j = 0; j < num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "+------"); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + for (i = 0; i < NOISE_SCALE_RANGE; i++) { + if (cl_noise_is_hist_line_empty(hist[i], num_antennas)) + continue; + + cl_snprintf(&buf, &len, &buf_size, "|%9d ", -i + NOISE_UPPER_LIMIT); + for (j = 0; j < num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "| %3u ", hist[i][j]); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + } + + cl_snprintf(&buf, &len, &buf_size, "|----------------"); + for (j = 0; j < num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "+------"); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_noise_print_hist_per_channel(struct cl_hw *cl_hw, + bool nasp_stats) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + struct cl_noise_reg *reg = NULL; + u8 ch_bw = cl_hw->conf->ce_channel_bandwidth; + u8 ch_cnt = 1 << ch_bw; + u8 hist[NOISE_SCALE_RANGE][MAX_20M_SUB_BAND] = { { 0 } }; + s8 val1, val2; + u8 i = 0, j = 0; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + if (list_empty(&noise_db->reg_list)) + return 0; + + list_for_each_entry(reg, &noise_db->reg_list, list) { + for (i = 0; i < min_t(u8, ch_cnt, MAX_ANT_PER_REG); i++) { + if (nasp_stats) { + val1 = cl_noise_process_sample(reg->nasp_sub20_per_chn, i); + + if (ch_bw == CHNL_BW_160) + val2 = cl_noise_process_sample(reg->nasp_sub20_per_chn2, i); + } else { + val1 = cl_noise_process_sample(reg->np_sub20_per_chn, i); + + if (ch_bw == CHNL_BW_160) + val2 = cl_noise_process_sample(reg->np_sub20_per_chn2, i); + } + + hist[(val1 * -1) + NOISE_UPPER_LIMIT][i]++; + if (ch_bw == CHNL_BW_160) + hist[(val2 * -1) + NOISE_UPPER_LIMIT][i + MAX_ANT_PER_REG]++; + } + } + + cl_snprintf(&buf, &len, &buf_size, + "Noise %sstrength per 20 Mhz channel histogram ant %u (dBm):\n" + "------------------", + nasp_stats ? "and signal " : "", noise_db->active_ant); + + for (j = 0; j < ch_cnt; j++) + cl_snprintf(&buf, &len, &buf_size, "--------"); + + cl_snprintf(&buf, &len, &buf_size, "\n| Noise Strength "); + for (j = 0; j < ch_cnt; j++) + cl_snprintf(&buf, &len, &buf_size, "| Chan%u ", j); + + cl_snprintf(&buf, &len, &buf_size, "|\n|----------------"); + + for (j = 0; j < ch_cnt; j++) + cl_snprintf(&buf, &len, &buf_size, "+-------"); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + for (i = 0; i < NOISE_SCALE_RANGE; i++) { + if (cl_noise_is_hist_line_empty(hist[i], ch_cnt)) + continue; + + cl_snprintf(&buf, &len, &buf_size, "|%9d ", -i + NOISE_UPPER_LIMIT); + + for (j = 0; j < ch_cnt; j++) + cl_snprintf(&buf, &len, &buf_size, "| %3u ", hist[i][j]); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + } + + cl_snprintf(&buf, &len, &buf_size, "|----------------"); + + for (j = 0; j < ch_cnt; j++) + cl_snprintf(&buf, &len, &buf_size, "+-------"); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_noise_print_hist_dens(struct cl_hw *cl_hw, bool nasp_stats) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + struct cl_noise_reg *reg = NULL; + u8 hist[NOISE_SCALE_RANGE][MAX_SEC_BW_CNT] = { { 0 } }; + u8 ch_bw = cl_hw->conf->ce_channel_bandwidth; + s8 val; + u8 i = 0, j = 0; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + if (list_empty(&noise_db->reg_list) || ch_bw == 0) + return 0; + + list_for_each_entry(reg, &noise_db->reg_list, list) { + for (i = 0; i < ch_bw; i++) { + if (nasp_stats) + val = cl_noise_process_sample(reg->nasp_sec20_dens_per_ant, i); + else + val = cl_noise_process_sample(reg->np_sec20_dens_per_ant, i); + + hist[(val * -1) + NOISE_UPPER_LIMIT][i]++; + } + } + + cl_snprintf(&buf, &len, &buf_size, + "Noise %spower density histogram ant %u (dBm/20Mhz):\n", + nasp_stats ? "and signal " : "", noise_db->active_ant); + + cl_snprintf(&buf, &len, &buf_size, "-----------------"); + + for (j = 0; j < ch_bw; j++) + cl_snprintf(&buf, &len, &buf_size, "--------"); + + cl_snprintf(&buf, &len, &buf_size, "\n| Noise Density "); + + for (j = 0; j < ch_bw; j++) + cl_snprintf(&buf, &len, &buf_size, "| SEC%u ", 20 * (1 << j)); + + cl_snprintf(&buf, &len, &buf_size, "|\n|---------------"); + for (j = 0; j < ch_bw; j++) + cl_snprintf(&buf, &len, &buf_size, "+-------"); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + for (i = 0; i < NOISE_SCALE_RANGE; i++) { + if (cl_noise_is_hist_line_empty(hist[i], ch_bw)) + continue; + + cl_snprintf(&buf, &len, &buf_size, "|%9d ", -i + NOISE_UPPER_LIMIT); + for (j = 0; j < ch_bw; j++) + cl_snprintf(&buf, &len, &buf_size, "| %3u ", hist[i][j]); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + } + + cl_snprintf(&buf, &len, &buf_size, "|---------------"); + for (j = 0; j < ch_bw; j++) + cl_snprintf(&buf, &len, &buf_size, "+-------"); + + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_noise_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "stats usage:\n" + "-a : Set antenna\n" + "-b : En/Dis noise histogram [0-stop, max samples-255]\n" + "-c : Print 20Mhz channels noise power\n" + "-d : Print 20Mhz channels noise and signal power\n" + "-e : Print noise density histogram\n" + "-f : Print noise and signal density histogram\n" + "-g : Print noise power histogram\n" + "-h : Print noise and signal power histogram\n" + "-r : Reset histogram\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static void cl_noise_set_ant(struct cl_hw *cl_hw, u8 active_ant) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + u8 max_ant = cl_hw->num_antennas - 1; + + if (noise_db->sample_cnt != 0) { + pr_warn("Can't set antenna during statistics collection\n"); + return; + } + + if (active_ant > max_ant) { + pr_err("Invalid antennas configuration. Should be 0-%u!\n", max_ant); + return; + } + + if (active_ant == noise_db->active_ant) { + pr_warn("Ant %u already set!\n", active_ant); + return; + } + + /* Antenna is different now so clear all stats */ + cl_noise_close(cl_hw); + + riu_rwnxagcccactrl_cca_main_ant_sel_setf(cl_hw, active_ant); + + noise_db->active_ant = active_ant; + + pr_debug("Antenna selected : %u\n", active_ant); +} + +void cl_noise_init(struct cl_hw *cl_hw) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + + INIT_LIST_HEAD(&noise_db->reg_list); +} + +void cl_noise_close(struct cl_hw *cl_hw) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + struct cl_noise_reg *elem = NULL; + struct cl_noise_reg *tmp = NULL; + + list_for_each_entry_safe(elem, tmp, &noise_db->reg_list, list) { + list_del(&elem->list); + kfree(elem); + } +} + +void cl_noise_maintenance(struct cl_hw *cl_hw) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + struct cl_noise_reg *reg = NULL; + u8 ch_bw = cl_hw->conf->ce_channel_bandwidth; + + if (noise_db->sample_cnt == 0) + return; + + reg = kzalloc(sizeof(*reg), GFP_ATOMIC); + + if (!reg) + return; + + /*collect statistics */ + reg->np_prim20_per_ant = riu_agcinbdpow_20_pnoisestat_get(cl_hw); + reg->np_sub20_per_chn = riu_agcinbdpownoiseper_20_stat_0_get(cl_hw); + reg->np_sec20_dens_per_ant = riu_agcinbdpowsecnoisestat_get(cl_hw); + reg->nasp_prim20_per_ant = riu_inbdpowformac_0_get(cl_hw); + reg->nasp_sub20_per_chn = riu_inbdpowformac_3_get(cl_hw); + reg->nasp_sec20_dens_per_ant = riu_inbdpowformac_2_get(cl_hw); + + if (ch_bw == CHNL_BW_160) { + reg->np_sub20_per_chn2 = riu_agcinbdpownoiseper_20_stat_1_get(cl_hw); + reg->nasp_sub20_per_chn2 = riu_inbdpowformac_4_get(cl_hw); + } + + if (cl_hw->num_antennas > MAX_ANT_PER_REG) { + reg->np_prim20_per_ant2 = riu_agcinbdpow_20_pnoisestat_2_get(cl_hw); + reg->nasp_prim20_per_ant2 = riu_inbdpowformac_1_get(cl_hw); + } + + list_add(®->list, &noise_db->reg_list); + + noise_db->sample_cnt--; + + if (noise_db->sample_cnt == 0) + pr_debug("record done\n"); +} + +int cl_noise_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + struct cl_noise_db *noise_db = &cl_hw->noise_db; + bool set_ant = false; + bool hist_enable = false; + bool hist_per_channel = false; + bool hist_mac_per_channel = false; + bool hist_dens = false; + bool hist_mac_dens = false; + bool hist_pwr_print = false; + bool hist_mac_pwr_print = false; + bool hist_reset = false; + u32 param = (u32)cli_params->params[0]; + u32 expected_params = -1; + + switch (cli_params->option) { + case 'a': + set_ant = true; + expected_params = 1; + break; + case 'b': + hist_enable = true; + expected_params = 1; + break; + case 'c': + hist_per_channel = true; + expected_params = 0; + break; + case 'd': + hist_mac_per_channel = true; + expected_params = 0; + break; + case 'e': + hist_dens = true; + expected_params = 0; + break; + case 'f': + hist_mac_dens = true; + expected_params = 0; + break; + case 'g': + hist_pwr_print = true; + expected_params = 0; + break; + case 'h': + hist_mac_pwr_print = true; + expected_params = 0; + break; + case 'r': + hist_reset = true; + expected_params = 0; + break; + case '?': + return cl_noise_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (set_ant) { + cl_noise_set_ant(cl_hw, (u8)param); + + return 0; + } + + if (hist_enable) { + if (param > NOISE_MAX_SAMPLES) { + pr_err("Error! Max samples should be < %u\n", NOISE_MAX_SAMPLES); + } else { + pr_debug("%s record histogram\n", param ? "Start" : "Stop"); + noise_db->sample_cnt = param; + } + + return 0; + } + + if (hist_per_channel) + return cl_noise_print_hist_per_channel(cl_hw, false); + + if (hist_mac_per_channel) + return cl_noise_print_hist_per_channel(cl_hw, true); + + if (hist_dens) + return cl_noise_print_hist_dens(cl_hw, false); + + if (hist_mac_dens) + return cl_noise_print_hist_dens(cl_hw, true); + + if (hist_pwr_print) + return cl_noise_print_hist(cl_hw, false); + + if (hist_mac_pwr_print) + return cl_noise_print_hist(cl_hw, true); + + if (hist_reset) { + pr_debug("Clear histogram\n"); + cl_noise_close(cl_hw); + return 0; + } + +out_err: + return -EIO; +} + From patchwork Thu Jun 17 16:00:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5405C2B9F4 for ; Thu, 17 Jun 2021 16:06:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6ED361407 for ; Thu, 17 Jun 2021 16:06:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230352AbhFQQIi (ORCPT ); Thu, 17 Jun 2021 12:08:38 -0400 Received: from mail-vi1eur05on2083.outbound.protection.outlook.com ([40.107.21.83]:50945 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233183AbhFQQHw (ORCPT ); Thu, 17 Jun 2021 12:07:52 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AbVt36DkPhdHQYnQYLwEPv9zkTNQIplY6MNfaaUjKiYTxV1EZJB07yWAMXTKN8GT4Ug/HTwriJbApKtnUuxgmsUQ1czvgZ98z9kMZ6UUAT2bmfDs/19tbJlp9oFYwUXYluHDMI1EmRzkpsAPNea+XTIKnZ3QWkx1sXqKmZXU/4RCN2XUdDHSpBog2zLSpxPt2SAeMSU5GWDcnPmuL2BUePTWIjajPwLGi4+NMKgX7Ndu4KIMvBQanv1UoFkPZrrk9skbr4x6Z2auFBIOlTPEOoSCjSFjT1jqOYHQBFJ+xS40VITf7mOgt5W7TYxihFiJRJdnuSWL1HTJ41ycEg/F5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R/5qmQoWFPiy8R9C+f6iEOzvfsXzdnQsd9C6CF8XK6Y=; b=G/d8fcQotwMoe+jDTs4+6AWV/V3Mp/4ltlsJ49xsxTG3udgSbrpFUupV/5xaEQmwfw+SNd+adbaTZVkw3YKQAgoQRTIRXjwKrZyPCF3dQYUZljgL4qdASvrseVs2sLUZ2PZdOMO4FkyUdrj2U8uOaKpHzXmaV3JyCPZfWW0SrdBur8XQE5M82NZ3toGf5JaXKbbC7PYexRwv33r+n/FB7STigjIspT2DgF8hM0R6HQRdHWPUw4SYnbI7FDVmdtNo41RTRxPm9aNKHj5aW3W99RtUc2u/4loWkxpEY38CVdKOfcBKzT8wzfYxFs8nolsNSihHlqFDLjOKOVVC+jH/YQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R/5qmQoWFPiy8R9C+f6iEOzvfsXzdnQsd9C6CF8XK6Y=; b=e8LIDnTpxgQniPeI4sDhztdGOn/hcRRKD7/QeofCsGwW3UL5OZbMLJxQCPaNqTWcEvMtRElc7J9vLhBiO71rpY0j3dYPY5zqrWjE/51W580+KxDDGuSa08ihpfj9LJmmUNxMIvgYZFsIL+jXxvJPt/ga1k51VK2BTKkFHByMzh0= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1314.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:42 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:42 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/noise.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/noise.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/noise.h b/drivers/net/wireless/celeno/cl8k/noise.h new file mode 100644 index 000000000000..292705e60925 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/noise.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_NOISE_H +#define CL_NOISE_H + +struct cl_hw; +struct cli_params; + +void cl_noise_init(struct cl_hw *cl_hw); +void cl_noise_close(struct cl_hw *cl_hw); +void cl_noise_maintenance(struct cl_hw *cl_hw); +int cl_noise_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_NOISE_H */ From patchwork Thu Jun 17 16:00:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE80AC2B9F4 for ; Thu, 17 Jun 2021 16:06:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C04D461003 for ; Thu, 17 Jun 2021 16:06:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233675AbhFQQIq (ORCPT ); Thu, 17 Jun 2021 12:08:46 -0400 Received: from mail-vi1eur05on2070.outbound.protection.outlook.com ([40.107.21.70]:44832 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233602AbhFQQH4 (ORCPT ); Thu, 17 Jun 2021 12:07:56 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=chVlNi4Jn+T8IKw8ooZpEN4hVcL38wyp+n90g+CixeCGYoEuon/8C0Kf05SDx8B+c05Oy1p0OLSTdTiUx4FYsrQB6h5o+O1PY0xbTVdhyqcxi2QBTKojuIz5C1DI+tkjVEaUgyTTOfy9XYRhKFRvRvWiByyQKHvGwK3PMKG3iX/14WW4oIL3fx81nDhEu7B78R5u4p+Lstkzj7SmS5C2rjiIi92KTWR1Uy6E0ExGeNtMkqoLXnP+Tfe4hwiNBCUxqB7Vwifrwf27FsxPc+o0iDDaB0u6OlmE2Tii5mtfk+Ibub5zC1DzShWHf1i3qhxIJ1n3cZ786APnTJIv42z4KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AUqbG7SYbnCnFrDvAFYozASwVN4rIMw0yy3/EWAB52o=; b=K18/r0SahYyXWNxDIDr07mob1MUTXkEppxsRWemSzPl/OIX/7iSEzqbpB6yMpvfnGGCHSRPtAPGBIe/x0pFnVh0j72dYC6ZH3jX1oV6Gkfii5PPdkvRQSDulGkhm/TS9SKVjn8ul35cTMek6/1iOiZZockwzzuccTOWpZn5dP+G64ZTowCooI4HZd7fmtRc8ocYVc+vjiG9/6WvH2Qzp0L7AtQ8cE8gpnMZlj0soG0xABTQ5lU2NumE84qxkh+vmHUhjhcV96VBVSFumxQPDxBosXnQTbgvRs60uKCk6gUD215GW77n+5pZ/IlmGA/aSZfVD91MOqo4ZoDg30KPs0A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AUqbG7SYbnCnFrDvAFYozASwVN4rIMw0yy3/EWAB52o=; b=cpa+zYZnAy916x9wEGIDtGev3aCqK5KMad9uL2tCyLlzXHybQaYCqOY4hck3+tv3QdwINhw0nnKieAt+kJFg7iM1WHMCh5uAb7jOZM4J0wUKNQf95JA37iqWAJCio3FvigoojmYNh3DgnvmP53os9xs1lRD+6KLmC4+kQoFNeWg= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1314.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:43 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:43 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/omi.c | 214 +++++++++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/omi.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/omi.c b/drivers/net/wireless/celeno/cl8k/omi.c new file mode 100644 index 000000000000..d25cbc12ac7a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/omi.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "omi.h" +#include "mac80211.h" +#include "sta.h" +#include "mac_addr.h" +#include "tx/tx.h" +#include "wrs/wrs_api.h" +#include "enhanced_tim.h" + +#define MAX_OMI_NSTS (WRS_SS_MAX - 1) + +static int cl_omi_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "omi usage:\n" + "-e : Enable/Disable OMI [0-dis, 1-en]\n" + "-s : Send OM control frame [sta_idx].[bw].[nss].[mu_ul_dis]." + "[mu_ul_data_dis].[tx_nsts]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static bool cl_omi_validate_parms(u8 bw, u8 nss, u8 ul_mu_dis, u8 ul_mu_data_dis, u8 tx_nsts) +{ + return (bw < CHNL_BW_MAX && nss < WRS_SS_MAX && tx_nsts <= MAX_OMI_NSTS); +} + +static int cl_omi_send(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u8 bw, u8 nss, u8 ul_mu_dis, + u8 ul_mu_data_dis, u8 tx_nsts) +{ + struct ieee80211_sub_if_data *sdata = NULL; + struct sk_buff *skb = NULL; + struct ieee80211_qos_htc_hdr *hdr = NULL; + struct cl_om_ctrl om_ctrl; + struct ieee80211_vif *vif = NULL; + int hdr_len = offsetof(struct ieee80211_qos_htc_hdr, a_ctrl) + sizeof(hdr->a_ctrl); + + if (!cl_hw->conf->ce_omi_en || !cl_sta) + return -1; + + vif = cl_sta->cl_vif->vif; + sdata = cl_sta->stainfo->sdata; + + if (!cl_omi_validate_parms(bw, nss, ul_mu_dis, ul_mu_data_dis, tx_nsts) || + vif->type != NL80211_IFTYPE_STATION) + return -1; + + skb = dev_alloc_skb(cl_hw->hw->extra_tx_headroom + hdr_len); + + if (!skb) + return -ENOMEM; + + skb_reserve(skb, cl_hw->hw->extra_tx_headroom); + + hdr = (struct ieee80211_qos_htc_hdr *)skb_put_zero(skb, hdr_len); + cl_mac_addr_copy(hdr->addr1, cl_sta->addr); + cl_mac_addr_copy(hdr->addr2, sdata->vif.addr); + cl_mac_addr_copy(hdr->addr3, sdata->u.mgd.bssid); + + hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_ACTION | + IEEE80211_FCTL_ORDER); + + om_ctrl.u.fields.chan_width = bw; + om_ctrl.u.fields.rx_nss = nss; + om_ctrl.u.fields.ul_mu_dis = ul_mu_dis; + om_ctrl.u.fields.ul_mu_data_dis = ul_mu_data_dis; + om_ctrl.u.fields.tx_nsts = tx_nsts; + + /* Set A-control subfield */ + hdr->a_ctrl.u.fields.b0 = 1; + hdr->a_ctrl.u.fields.b1 = 1; + hdr->a_ctrl.u.fields.control_id = IEEE80211_CTRL_A_CTRL_ID_OM; + hdr->a_ctrl.u.fields.control_info = om_ctrl.u.value; + + if (!ieee80211_tx_prepare_skb(cl_hw->hw, vif, skb, cl_hw->nl_band, NULL)) + return -1; + + /* Send the OMI frame */ + cl_tx_single(cl_hw, cl_sta, skb, false, true); + pr_debug("OM control frame was sent!\n"); + + return 0; +} + +static void cl_omi_set_tb_mode(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + u8 ul_mu_dis, u8 ul_mu_data_dis) +{ + struct ieee80211_sta_he_cap *he_cap = &cl_hw->iftype_data[1].he_cap; + bool mu_dis_rx_sup = (he_cap->he_cap_elem.mac_cap_info[5] & + IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX) ? true : false; + u8 ac; + + /* + * According to Table 9-24a - UL MU Disable and UL MU Data Disable subfields encoding + * At this point we need to suspend/resume trigger base flow + */ + + for (ac = 0; ac < AC_MAX; ac++) + cl_sta->data_pending[ac] = 0; + + if (!ul_mu_dis && !ul_mu_data_dis) { + pr_debug("All trigger based UL MU transmissions are enabled!\n"); + } else if (!ul_mu_dis && ul_mu_data_dis && mu_dis_rx_sup) { + cl_enhanced_tim_clear_rx_sta(cl_hw, cl_sta->sta_idx); + pr_debug("Basic Trigger is suspended!\n"); + } else if (ul_mu_dis && !ul_mu_data_dis) { + cl_enhanced_tim_clear_rx_sta(cl_hw, cl_sta->sta_idx); + pr_debug("All trigger based UL MU transmissions are suspended!\n"); + } +} + +void cl_omi_parse_om_ctrl_frm(struct cl_hw *cl_hw, struct cl_sta *cl_sta, struct sk_buff *skb) +{ + struct ieee80211_qos_htc_hdr *hdr = (struct ieee80211_qos_htc_hdr *)skb->data; + struct cl_wrs_rate *wrs_rate = &cl_sta->wrs_sta.max_rate_cap; + struct cl_om_ctrl om_ctrl; + u8 nss, bw, ul_mu_dis, ul_mu_data_dis, tx_nsts; + + if (!cl_hw->conf->ce_omi_en) + return; + + om_ctrl.u.value = hdr->a_ctrl.u.fields.control_info; + nss = om_ctrl.u.fields.rx_nss; + bw = om_ctrl.u.fields.chan_width; + ul_mu_dis = om_ctrl.u.fields.ul_mu_dis; + ul_mu_data_dis = om_ctrl.u.fields.ul_mu_data_dis; + tx_nsts = om_ctrl.u.fields.tx_nsts; + + if (!cl_omi_validate_parms(bw, nss, ul_mu_dis, ul_mu_data_dis, tx_nsts)) + return; + + /* Set TB mode */ + cl_omi_set_tb_mode(cl_hw, cl_sta, ul_mu_dis, ul_mu_data_dis); + + if (nss != wrs_rate->nss) + cl_wrs_api_nss_changed(cl_hw, &cl_sta->stainfo->sta, nss); + + if (bw != wrs_rate->bw) + cl_wrs_api_bw_changed(cl_hw, &cl_sta->stainfo->sta, bw); +} + +int cl_omi_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + u32 expected_params = 0; + bool send_om_ctrl = false; + bool enable = false; + + switch (cli_params->option) { + case 'e': + enable = true; + expected_params = 1; + break; + case 's': + send_om_ctrl = true; + expected_params = 6; + break; + case '?': + return cl_omi_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (enable) { + bool enable = (bool)cli_params->params[0]; + + if (enable != cl_hw->conf->ce_omi_en) { + cl_hw->conf->ce_omi_en = enable; + pr_debug("OMI %s\n", enable ? "Enabled" : "Disabled"); + } else { + pr_debug("OMI already %s\n", enable ? "Enabled" : "Disabled"); + } + } + + if (send_om_ctrl) { + u8 sta_idx = (u8)cli_params->params[0]; + u8 bw = (u8)cli_params->params[1]; + u8 nss = (u8)cli_params->params[2]; + bool ul_mu_dis = (bool)cli_params->params[3]; + bool ul_mu_data_dis = (bool)cli_params->params[4]; + u8 tx_nsts = (u8)cli_params->params[5]; + struct cl_sta *cl_sta; + + cl_sta_lock_bh(cl_hw); + cl_sta = cl_sta_get(cl_hw, sta_idx); + + if (cl_omi_send(cl_hw, cl_sta, bw, nss, ul_mu_dis, ul_mu_data_dis, tx_nsts)) + pr_warn("Failed to send OM control frame!\n"); + + cl_sta_unlock_bh(cl_hw); + + return 0; + } + +out_err: + return -EIO; +} From patchwork Thu Jun 17 16:00:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF3BAC2B9F4 for ; Thu, 17 Jun 2021 16:07:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD0B661003 for ; Thu, 17 Jun 2021 16:07:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232904AbhFQQJP (ORCPT ); Thu, 17 Jun 2021 12:09:15 -0400 Received: from mail-vi1eur05on2083.outbound.protection.outlook.com ([40.107.21.83]:50945 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232833AbhFQQIH (ORCPT ); Thu, 17 Jun 2021 12:08:07 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lJioXfCvZqMZKjuW7gV0ElPaTZ3WSbD5Vpc/3C7HLfDg1zAGdh/OZfzkpTuYIQd/Tpkq0FixfCfwG8DSpydQWo//qnXWIt7q8DcFhLjYL4czFsUMTSvf5CZ4Zd9KzFsMxSm5U1Q89LoVvmVv95t54PYDMw9ork7QDmlmydYuCRVddZo8hkg7aVHgEMpUZSCazvnP/g+RQCMfjK7F3u11OfK1Kp2mpA933zBpLrY6aoJYMXny3w8W5sZtsBHY8GQYTfwH9wDwWTnbHeIZ72h3ZfXpuJjH8eGPpFeaKV1CR4IydmsfPc3MMvqTitLjULN/W39ZnjX0ezCRr9Efv95wVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qtQYq0WVrZRxrf+pN/SEZ0Aa1A1/0rdC9OXHpQTJoj8=; b=EWrTzv2N3Iu9whcbjqfKoqL9fw07pN8YsDfxYIcAs6PrqhX9PwvhOfjhq+rf1Sn/viXsQ1FeNSjpNljji6bUof/ENp3PygL/bPggJC4eZmLBXUqCU5sqOKS/zt2WtY85VIOMvbTQ3oHeiLmPO3184VRgGdF8pHkeTF7E+M1RoyE4RvlWhEjx5ZRssgRGZIbX33TpST+hv4Qc8dptNB0hhnPa5YMnt+RWeEP0VlhxDjzy6nx7lcNeyNw3Sy0D9GNEaoZnB5ETzyagYI7ugFtOHvEzCvTrblK9aqDMFDb3+dp0/WPwqhsak0XT/nkKtmyKGEphXlrlNGw8jnyAG7P5Gw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qtQYq0WVrZRxrf+pN/SEZ0Aa1A1/0rdC9OXHpQTJoj8=; b=3z1LFHHk6u30Y19stUzlJ98X0GwN2hpQ4LSqBmQ3yWfQTF21aStOPkWjzvMX1sFq6euxI4NhgsMR2Cz7L1Y5r7IhMxM0ctaWqvqAVgwzaLihdfxueqdwvIVkDDAknG4cgBm/c5H2kceCF1w1jUMJhk5e8bL9KXHbGQFj/ifOXCg= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1314.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:43 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:43 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 122/256] cl8k: add omi.h Date: Thu, 17 Jun 2021 16:00:09 +0000 Message-Id: <20210617160223.160998-123-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:47 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 52a641b5-cf47-4db7-43f5-08d931a9a1e4 X-MS-TrafficTypeDiagnostic: AM9P192MB1314: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: w2JIVrjyDLm016BysSIGcUfXhQ88pW7IPvKtaCPN+t+kCv0u6FM1CpAGm/uOavOoOSc00HiovWABNjODiwilF1qctljPvhaOsEvd6vqbOLgqZ5P3nwq5/KDcYWXF8InsJz3/DhMJyF12PuTnPpzQLHJaBSL9WDdwAS17K1r5mgX2GIjO5U6aEYL1AOeDtvWFyow6EOqJoxB6ifTEH96+/TiYadrvEg0PqctjgG2gUoPNKtE5+b3XrEFkXsmIk1yHenAi/nQK80hkCuXvR7GjmnwE1BWJNnDjKSqnYJS7MP8XtntjdwShvg+VPxQpUE4aPB23wCMeUjCMl6Hg9itKpDOez2eCba12fcqR2gffrUZs7LBvx2++hkNtgbqhce7QhOiey3rDI06ZvFlyGSMwrWIMy+7LO3LJIG1MHW8AU5EhgiuwBGLZPg4tahmhPDTLxUK7FDU+RcwEd63NbdQEwT1p1j/PRZIEEV7W5FZ1jprGFVwDTZN/vm+xHjb+LZ8IVGgQSE71dOy38/uSw7w79jtBCA/PfQgWjEag1bf4rbtM8oObiBgWflgSmNGVTtfAnW0A7fR/4TrQsssoiSnF8nyWlJWHVScWGJxuQlunTySNDmrCybwEVbKBMm310JbAr3CYwZ1UGa6TzuLg2goMO/9o/z2RqNnV2fkA2FwfAupGVHVX8jzHLf978olhQAxQPsrAfs/qc87sS1AoHtHn8w== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(39840400004)(366004)(376002)(136003)(346002)(8936002)(66946007)(83380400001)(186003)(5660300002)(26005)(36756003)(86362001)(8676002)(55236004)(1076003)(6916009)(2906002)(6506007)(66476007)(478600001)(6666004)(38350700002)(52116002)(66556008)(956004)(4326008)(107886003)(54906003)(38100700002)(6486002)(2616005)(316002)(16526019)(6512007)(9686003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wt5YQnTOSWo4tNeFgQFiiML+doZuRNqUvqG9SYjtOf1VXm4M2Tmet0XymZgpM4klzYukoudon9wFH6n0+js9bvFWHeZpkTab2Z0ubjhprZb9CUZVMyvY51JISiKgMtlDFlnhfEmldAdcMbpyA8ByC6Epbe4D8AuSxEh2UHpvstDlPQCvyShd5HcPxaPY+jTq9qfBYtr19fwwwxI5ytq7ZJLH8cV8nkf07G63RBkNxP7R8Hg5AaFGBjafwmQLl5kwjBoq4PxAOQjDn0YpyzH0b1nnZXQODGpoGmmM5zNkSHi+GZvoS33OMa/Hd9KP2EUGP4FpNbakW3AtM034PyF+mUoDHv/xqC2YGkjRHeBUFP1kh6JSDvOCGpbYfcvFw0olIW4v2pRV8og9GmngRIVTe6GzS1Lr6IRhLlr7sjtEnLkGCibtWWCMIn8yUiNn8A8AfbMWB8QXGXlFPTgmejCn0nEvfaMT7YBB7hVj/WdvMYiOODgbuy1wiUf6LoJPwC6fFecYUl2qDzoGEz8lO7qmn3y7Y9NJe7DPnhfaccqhwHvTsRNjEBL0BhGvY4lH7ZTkB+DLaPzGg288Ef448i2mL+m+u7KcfrRbGutdgTQ/6G2wwdKAex2zgyUQgnRuxtucI1anUL15N3H/ZnoOmZ7+8U7xPWO45gwcaHRdaBYAOEY+gr7Kv2ETMNaWM1UVr6VXTPydG9PhS4yMcMBtQ9gu43jKxxcU6uU+wFrEkOQzr91ozobnMyMjtQ1xO94kANyJWNg7WB6UiRWaV2mnJuCEmM1o9rzHGiu6wydDdRwIX1MpC60/dP26XORtFQW+aEZff+z89AlE7kzb3xdSjWGXP+LWk3K/iFDHs61WiRboTwjTkobF/TR/Gv3n+r1HIlyIH9LngGsLRYvGrkZ66Peji8eoIU/8Ok9HaI62luX7hqD8yYs5NVY+ZFXLJTl5KjKTdr2FUewjbg2uz1oUDMIAna7oMk7lDYZ0IKaGLnBEv9XDmeJvDzmLnH1nnmOhEAN36b/ee8SL8pI/1lVRWl8m923igdLQDutNJ+nqLqJwjLHD6AhBs2yDh/iDSMbfsSXEvhmgV3zJwXM/OG/FCV52qKuERlLWDKD9lYzKaRsBqTcBfv4PO/VcL8wIC9tfmHhBdLQ+B8Hz4bU9aTAwJparrMtG9VDscOHdDkDYN3iAk8zVkQUUKU1aJQgp1DAUz1U8jJFj4nUAaowR2CLt1WOaME05Hvh1KiIQUkY7dywC5WQ7nDBeSql8l+4fbGZP9w6BtpdsgzLijmR4hdXcrQ9uGnmNhpB9HEKwCgP8meLJyQxVa4EMpJPOmLPG3QcB7bku X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 52a641b5-cf47-4db7-43f5-08d931a9a1e4 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:48.6245 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jWak8VGjSKtRroLkMI2F3SXB7RdlPVcAAImrX71sC1gPu1GtDjwREoKgGdIDslGs+VPT11jds4mhIrUamNK2gA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1314 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/omi.h | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/omi.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/omi.h b/drivers/net/wireless/celeno/cl8k/omi.h new file mode 100644 index 000000000000..dfcb13f0f476 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/omi.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_OMI_H +#define CL_OMI_H + +#include "hw.h" + +/** + * OMI (=Operating Mode Indication, 802.11ax) + */ + +struct cl_om_ctrl { + union { + struct { + u32 rx_nss : 3, + chan_width : 2, + ul_mu_dis : 1, + tx_nsts : 3, + er_su_dis : 1, + dl_mu_mimo_resound : 1, + ul_mu_data_dis : 1; + } __packed fields; + u32 value; + } u; +} __packed; + +void cl_omi_parse_om_ctrl_frm(struct cl_hw *cl_hw, struct cl_sta *cl_sta, struct sk_buff *skb); +int cl_omi_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_OMI_H */ From patchwork Thu Jun 17 16:00:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 918BDC2B9F4 for ; Thu, 17 Jun 2021 16:07:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A05E61003 for ; Thu, 17 Jun 2021 16:07:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233081AbhFQQJm (ORCPT ); Thu, 17 Jun 2021 12:09:42 -0400 Received: from mail-vi1eur05on2083.outbound.protection.outlook.com ([40.107.21.83]:50945 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233705AbhFQQIW (ORCPT ); Thu, 17 Jun 2021 12:08:22 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c6EUZERT0592Kk6OIbQ+v6EM9wDSqXGjsV2wkEH0/mI5duYVyugaJV/NbDxmUHddm/hc9L2vZoB2ET4Pyv7FSOlSWFq6RMJGfsGTI+JGbOtFYf9qQJO+gI0tar2NdPEbvzhlRb5DSFiKGUS5e+ZaRLya1uT2/ph3FOLhDtXWuDFclMEcZE0I0ZJk7KGh00RLrLbYgb7tHTA9Rfsx7AyGd4pndA9EmUik3ujivt9oW41a9FPXvl8QImzA/VloynyP0w0mYgad6dKVwVGW8L9prK7dY5ClhJ/u9k9hEkNRlr6E6+fPOaZzLR1IDPb2kAE2FQtjk1C/DIvOGzxAHxFddw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=v99y19SRFAwJfpsm7qePqFhZRMUlwRl5E73B24WyBJk=; b=YMMABnJLukw/33d94K+bl1qvxq2Q/Hxi019zPsdKE9OImhqBRAJPUyRa1wODBBcYZpEGXElx+tkmSSppQNL+DrRDbSYS3ZROuoeQ+6Z6CopOVlPDYyMWgp00jmWb8bGu6qPFMFRHB+Y/gxNzoopWwWL5sVs2fSiU4/UmUE+ZlwgutiVvpqeK2CWSEJrMXEwTphho72bDkHAg42gsWIeNTesdeRd5kBYNcXsbTkyHlG4ChMbuJ9U48cSm3heCWdOpPEXL2CQtZZL9MNkM9eTm9IaWT7x+y1GNgZSxxgyreZdxZCZ10MTeBMmUW0qE9Ft0wLnkfWq1PliVGCsmVDxqcQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=v99y19SRFAwJfpsm7qePqFhZRMUlwRl5E73B24WyBJk=; b=Uci5dqauKWZLdTLX2CNxj8lOGHIgp8i2ErbNEYdrbP4rHZDxveXzqR0z5NoL5qhZEWW0egXqQ3Ff+unPJPsreXar7kfkzorDA2FvW+QMPqI0EpaMjOtRuoFDRN4UN0Qgwb1akCurrZhVYr9hpf35Agh86oAPquoOACVFbNtzAc4= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1314.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:43 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:43 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 123/256] cl8k: add ops.c Date: Thu, 17 Jun 2021 16:00:10 +0000 Message-Id: <20210617160223.160998-124-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:48 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f33eff4-85c0-4855-d1ab-08d931a9a27a X-MS-TrafficTypeDiagnostic: AM9P192MB1314: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HRo+T7bVt36qdf2jlgSPCAA4O68HeWypoddj3wLDlt7OBUJ4e6deOeNrUufcHKCdP7P1+vXMo60ZePfOL0WOl3kaAs2LPxIN8tQfmI99uBk7g4v0dULPAAzduSkG7g2wL6EXmzmnSz80iuqr6TcxudSWZ1diW3K9w+TweZnJyP9IbubTCRCy/L8sweoz8URWef1tQpw/ab0Lul9k1Uher3kptJcuS2B3XWVO3sY19GOvJmEkovJ36Rol+vhMvC9P//Mf6rmsOgyw/q+ZrhAw5GkhuIe7i2blhkwiiGOAchBrlGURar7l3Kn4F2EwOT8sm/MRAVuhk/FA4qFDLgpR6rTG34tDuyKjb13qUzFtFY3dMbHtMMZs+XzHKs6jXrDKIfGEPLhMPGwe2jgAf/iPiT3ggSwuXoCyfC05xNOl3MRaDo5jwUZFHNnSyIQf0iTbs7PwSQ8tOndh+EOkBBrfrql8nvHRWAc/Yc9mr9LqOsPEVux/UiFFDUpI+9xgNH+BPTQS7uF5dmzdddtOnloB2lWvrtTxj4AJQYPvuoVcnLTAfSlGM/4sSS0M5p/Aq9TvIwy7rT/RNBCVHeyGioVPFGKQT/BsMFXnvWfkDnz35IUKy2+1P208f3gS58VANR50etC5qI244htLxYpBR3r4kVYb4m8rZzkSlfHOK3PnnYzCezhKajivy2FBFIfDpzNgfgA0OCViih+AvNbNX71Ubw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(39840400004)(366004)(376002)(136003)(346002)(8936002)(66946007)(83380400001)(186003)(5660300002)(26005)(36756003)(86362001)(8676002)(55236004)(1076003)(6916009)(2906002)(6506007)(66476007)(478600001)(6666004)(30864003)(38350700002)(52116002)(66556008)(956004)(4326008)(107886003)(54906003)(38100700002)(6486002)(2616005)(316002)(16526019)(6512007)(9686003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HKtydAGnaTDpcMQZkAKSpox5AbyZCKIvbM83ROvQ9HB6QVrJWMfOcNiNXJ2VMjBKJDV5UVndIbgY6HhfYh1KvHSinFnSsxMAv4mGZqXyTGNvsYxMHb3K1dcH3NWpt3NLNE1DYQi/0wu/pEAnKpni0ntBtwJKadYs+e3/CC+CiJmieWgLoR3oES7sElneukNORlOMa05x+v9pbr0zCiEB3XW/sQ8cVSjTbXBhJmBuz0jQ8bTFdHMgY3KRnG08I8+z2dQuxJCozWBVoPQNWA6CsbnwZE9/m96Sp8MW0tpMQFt8aFb10vGqQPqKsCzmNmkRpZRjrCzWl4PKw9NVMG7Fz2PzXdZ51yM5l/Ao0h6uW2AWGqWjA1/Skme3jfK/lZVNv75oH90ffBDIjm1ERPD2JrWHFlmN44BSryffaGcaiTIQTVE4aJqkfzgTv3HcYPEv2dCBZt6Ougthh1rViFwdVar4eHv+Hf6gCykRDgn+8YDZD1XZJoyQ/RYtxJaCmlMDfFCeePesjZvoY9jqwopxk79BbI1F8flc9dVeIAt1Rw/7BCJ2szrI4zuYeJDfxAharXg6mYLzXKvaPqeMN85yVjL/FYu0EK357Aij2zffphWIE5Kh8ABFoC/PiVHy7FCZt3UGe2p94fxxFRHcw0JZI3Uu8bYaV/54Br7yORveuQr0yF35jRt6PLjerWBZrV/hYmCs3rW8ulLtEIrXHDWn0SvM604THbsK0JcJFITYT3bJv6wHCmOXjVzQzGWWQr6OVFRnuEcTofFd13VJGpZ073OfxthXjbifRyUCcYan5YdLSf60J3sM8LcE1RYTtSGS18DlLAsf9FLBeZNnPkXQNQPhD29Jo4pbPf5lqp3qRZ6rhBEbKIzqwUntgBIFpRXAFRywYKrN3AYI1i2ZRg4s5sab2TtcbLEMhUnZ2B6Cn1C1UcIjjx+tunqzcs5YSDyPLuIdgf8kLb11q2fDCnhnFgpvAYHVARbljuUAHhjDaEOgpruKQ6sZYQGG5nnE1cvRu8D8lP1ntZMCfzPCB89gD3O/PAd+avcfk1ZHo81woMcHYdD4pPJLmCKcMrn5kL/nTKhkNdJAiySeYi5UFzbt1vQQyTuAJIELIwFPzYXp93HegT92jwaXcnkqPHd7i3wl1jwEeoFMJ49K6dZw8PkVPIznxFX/DlXH5LiTb0S/23hTa+DEYRrbEEvZ75bgQLn44x5Wl/41neBWbACT+JkaEZj6A/WzeMBlbclFgCqEZI8m3xAZTyYDZF1tIo54DDru/97xdAAcngF66RkGWMACV3ilWNtmPXpFUZCQl3uPp/L4Cpidn4XihN4k5jgyWHu1 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f33eff4-85c0-4855-d1ab-08d931a9a27a X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:49.7864 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NrLEvHQviqq2hPKrVTL20bqxyLRV3YQISiYgUloV+7Ml9q6BOB/BYYxOSTK36t8gwFLqcTRSqlZSx/0SZFl+5A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1314 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/ops.c | 889 +++++++++++++++++++++++++ 1 file changed, 889 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ops.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ops.c b/drivers/net/wireless/celeno/cl8k/ops.c new file mode 100644 index 000000000000..16934984b7cd --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ops.c @@ -0,0 +1,889 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "ops.h" +#include "utils/ip.h" +#include "chip.h" +#include "ampdu.h" +#include "fw/msg_tx.h" +#include "tx/tx.h" +#include "tx/tx_queue.h" +#include "radio.h" +#include "recovery.h" +#include "rate_ctrl.h" +#include "temperature.h" +#include "band.h" +#include "rx/rx.h" +#include "edca.h" +#include "utils/math.h" +#include "utils/utils.h" +#include "ext/dyn_mcast_rate.h" +#include "ext/dyn_bcast_rate.h" +#include "vns.h" +#include "dfs/dfs.h" +#include "key.h" +#include "temperature.h" +#include "calib.h" +#include "wrs/wrs_api.h" +#include "chandef.h" +#include "version.h" +#include "power.h" +#include "tx/tx_inject.h" +#include "stats.h" +#include "netlink.h" +#include "calib.h" +#ifdef CONFIG_CL_PCIE +#include "bus/pci/ipc.h" +#endif + +static const int cl_ac2hwq[AC_MAX] = { + [NL80211_TXQ_Q_VO] = CL_HWQ_VO, + [NL80211_TXQ_Q_VI] = CL_HWQ_VI, + [NL80211_TXQ_Q_BE] = CL_HWQ_BE, + [NL80211_TXQ_Q_BK] = CL_HWQ_BK +}; + +static const int cl_ac2edca[AC_MAX] = { + [NL80211_TXQ_Q_VO] = EDCA_AC_VO, + [NL80211_TXQ_Q_VI] = EDCA_AC_VI, + [NL80211_TXQ_Q_BE] = EDCA_AC_BE, + [NL80211_TXQ_Q_BK] = EDCA_AC_BK +}; + +static void cl_ops_tx_agg(struct cl_hw *cl_hw, + struct sk_buff *skb, + struct ieee80211_tx_info *tx_info, + struct cl_sta *cl_sta) +{ + cl_hw->tx_packet_cntr.forward.from_mac_agg++; + + if (!cl_sta) { + kfree_skb(skb); + cl_dbg_err(cl_hw, "cl_sta null in agg packet\n"); + cl_hw->tx_packet_cntr.drop.sta_null_in_agg++; + return; + } + + /* AMSDU in HW can work only with header conversion. */ + tx_info->control.flags &= ~IEEE80211_TX_CTRL_AMSDU; + cl_tx_agg(cl_hw, cl_sta, skb, false, true); +} + +static void cl_ops_tx_single(struct cl_hw *cl_hw, + struct sk_buff *skb, + struct ieee80211_tx_info *tx_info, + struct cl_sta *cl_sta) +{ + bool is_vns = cl_vns_is_very_near(cl_hw, cl_sta, skb); + + cl_hw->tx_packet_cntr.forward.from_mac_single++; + + cl_tx_single(cl_hw, cl_sta, skb, is_vns, true); +} + +void cl_ops_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) +{ + /* + * Almost all traffic passing here is singles. + * Only when opening a BA session some packets with + * IEEE80211_TX_CTL_AMPDU set can pass here. + * All skbs passing here did header conversion. + */ + struct cl_hw *cl_hw = (struct cl_hw *)hw->priv; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + struct ieee80211_sta *sta = control->sta; + struct cl_sta *cl_sta = NULL; + + if (sta) { + cl_sta = IEEE80211_STA_TO_CL_STA(sta); + + /* + * Prior to STA connection sta can be set but we don't + * want cl_sta to be used since it's not initialized yet + */ + if (cl_sta->sta_idx == STA_IDX_INVALID) + cl_sta = NULL; + } + + if (cl_recovery_in_progress(cl_hw)) { + cl_hw->tx_packet_cntr.drop.in_recovery++; + cl_tx_drop_dkb(skb); + return; + } + + if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) + cl_ops_tx_agg(cl_hw, skb, tx_info, cl_sta); + else + cl_ops_tx_single(cl_hw, skb, tx_info, cl_sta); +} + +int cl_ops_start(struct ieee80211_hw *hw) +{ + /* + * Called before the first netdevice attached to the hardware + * is enabled. This should turn on the hardware and must turn on + * frame reception (for possibly enabled monitor interfaces.) + * Returns negative error codes, these may be seen in userspace, + * or zero. + * When the device is started it should not have a MAC address + * to avoid acknowledging frames before a non-monitor device + * is added. + * Must be implemented and can sleep. + * It does not return until the firmware is up and running. + */ + int error = 0; + struct cl_hw *cl_hw = hw->priv; + struct cl_tcv_conf *conf = cl_hw->conf; + +#ifdef CONFIG_CL_PCIE + if (!cl_hw->ipc_env) { + CL_DBG_ERROR(cl_hw, "ipc_env is NULL! 'no_dhcpcd' is missing in nvram folder\n"); + return -1; + } +#endif + + /* Exits if device is already started */ + if (WARN_ON(test_bit(CL_DEV_STARTED, &cl_hw->drv_flags))) + return -EBUSY; + + /* Start firmware */ + error = cl_msg_tx_start(cl_hw); + if (error) + return error; + + /* Device is now started. + * Set CL_DEV_STARTED bit before the calls to other messages sent to + * firmware, to prevent them from being blocked* + */ + set_bit(CL_DEV_STARTED, &cl_hw->drv_flags); + + if (!cl_recovery_in_progress(cl_hw)) { + /* Read version */ + error = cl_version_update(cl_hw); + if (error) + return error; + + error = cl_temperature_diff_e2p_read(cl_hw); + if (error) + return error; + } + + /* Set firmware debug module filter */ + error = cl_msg_tx_dbg_set_ce_mod_filter(cl_hw, conf->ci_fw_dbg_module); + if (error) + return error; + + /* Set firmware debug severity level */ + error = cl_msg_tx_dbg_set_sev_filter(cl_hw, conf->ci_fw_dbg_severity); + if (error) + return error; + + /* Set firmware rate fallbacks */ + error = cl_msg_tx_set_rate_fallback(cl_hw); + if (error) + return error; + + error = cl_msg_tx_ndp_tx_control(cl_hw, + conf->ci_ndp_tx_chain_mask, + conf->ci_ndp_tx_bw, + conf->ci_ndp_tx_format, + conf->ci_ndp_tx_num_ltf); + if (error) + return error; + + /* Set default, multicast, broadcast rate */ + cl_rate_ctrl_set_default(cl_hw); + cl_dyn_mcast_rate_set(cl_hw); + cl_dyn_bcast_rate_set(cl_hw, 0); + + ieee80211_wake_queues(hw); + + cl_calib_start(cl_hw); + + clear_bit(CL_DEV_INIT, &cl_hw->drv_flags); + + cl_edca_hw_conf(cl_hw); + + return error; +} + +void cl_ops_stop(struct ieee80211_hw *hw) +{ + /* + * Called after last netdevice attached to the hardware + * is disabled. This should turn off the hardware (at least + * it must turn off frame reception.) + * May be called right after add_interface if that rejects + * an interface. If you added any work onto the mac80211 workqueue + * you should ensure to cancel it on this callback. + * Must be implemented and can sleep. + */ + struct cl_hw *cl_hw = hw->priv; + + /* Go to idle */ + cl_msg_tx_set_idle(cl_hw, MAC_IDLE_SYNC); + + /* + * Clear CL_DEV_STARTED to prevent message to be sent (besides reset and start). + * It also blocks transmission of new packets + */ + clear_bit(CL_DEV_STARTED, &cl_hw->drv_flags); + + /* Stop mac80211 queues */ + ieee80211_stop_queues(hw); + + /* Send reset message to firmware */ + cl_msg_tx_reset(cl_hw); + +#ifdef CONFIG_CL_PCIE + /* Reset IPC */ + cl_ipc_reset(cl_hw); +#endif + + cl_hw->num_ap_started = 0; + cl_hw->radio_status = RADIO_STATUS_OFF; +} + +static int add_interface_to_firmware(struct cl_hw *cl_hw, struct ieee80211_vif *vif, u8 vif_index) +{ + struct mm_add_if_cfm *add_if_cfm; + int ret = 0; + + /* Forward the information to the firmware */ + ret = cl_msg_tx_add_if(cl_hw, vif, vif_index); + if (ret) + return ret; + + add_if_cfm = (struct mm_add_if_cfm *)(cl_hw->msg_cfm_params[MM_ADD_IF_CFM]); + if (!add_if_cfm) + return -ENOMSG; + + if (add_if_cfm->status != 0) { + cl_dbg_verbose(cl_hw, "Status Error (%u)\n", add_if_cfm->status); + ret = -EIO; + } + + cl_msg_tx_free_cfm_params(cl_hw, MM_ADD_IF_CFM); + + return ret; +} + +int cl_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + /* + * Called when a netdevice attached to the hardware is + * enabled. Because it is not called for monitor mode devices, start + * and stop must be implemented. + * The driver should perform any initialization it needs before + * the device can be enabled. The initial configuration for the + * interface is given in the conf parameter. + * The callback may refuse to add an interface by returning a + * negative error code (which will be seen in userspace.) + * Must be implemented and can sleep. + */ + struct cl_hw *cl_hw = hw->priv; + struct cl_chip *chip = cl_hw->chip; + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + struct ieee80211_sub_if_data *sdata = container_of(vif, struct ieee80211_sub_if_data, vif); + struct net_device *dev = sdata->dev; + u8 ac; + + if (!dev) + return -1; + + /* + * In recovery just send the message to firmware and exit + * (also make sure cl_vif already exists). + */ + if (cl_recovery_in_progress(cl_hw) && cl_vif_get_by_dev(cl_hw, dev)) + return add_interface_to_firmware(cl_hw, vif, cl_vif->vif_index); + + cl_vif->cl_hw = cl_hw; + cl_vif->vif = vif; + cl_vif->dev = dev; + + if (chip->conf->ce_production_mode) + cl_vif->tx_en = true; + + /* Copy dev ops and change ndo_start_xmit to point at cl_tx_start() */ + cl_vif->orig_dev_ops = dev->netdev_ops; + memcpy(&cl_vif->dev_ops, dev->netdev_ops, sizeof(struct net_device_ops)); + cl_vif->dev_ops.ndo_start_xmit = cl_tx_start; + dev->netdev_ops = &cl_vif->dev_ops; + + if (chip->idx == CHIP0) { + if (cl_hw_is_tcv0(cl_hw)) + sscanf(dev->name, CL_IFACE_PREFIX "0_%hhu", &cl_vif->vif_index); + else + sscanf(dev->name, CL_IFACE_PREFIX "1_%hhu", &cl_vif->vif_index); + } else { + if (cl_hw_is_tcv0(cl_hw)) + sscanf(dev->name, CL_IFACE_PREFIX "2_%hhu", &cl_vif->vif_index); + else + sscanf(dev->name, CL_IFACE_PREFIX "3_%hhu", &cl_vif->vif_index); + } + + if (add_interface_to_firmware(cl_hw, vif, cl_vif->vif_index)) + return -1; + + if (vif->type != NL80211_IFTYPE_STATION) + vif->cab_queue = CL_HWQ_VO; + + cl_vif_add(cl_hw, cl_vif); + + for (ac = 0; ac < AC_MAX; ac++) + vif->hw_queue[ac] = cl_ac2hwq[ac]; + + if (vif->type == NL80211_IFTYPE_MESH_POINT) { + tasklet_init(&cl_hw->tx_mesh_bcn_task, cl_tx_bcn_mesh_task, + (unsigned long)cl_vif); + cl_radio_on(cl_hw); + cl_vif->tx_en = true; + } + + /* Set active state in station mode after ifconfig down and up */ + if (cl_radio_is_on(cl_hw) && vif->type == NL80211_IFTYPE_STATION) + cl_msg_tx_set_idle(cl_hw, MAC_ACTIVE); + + return 0; +} + +void cl_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + /* + * Notifies a driver that an interface is going down. + * The stop callback is called after this if it is the last interface + * and no monitor interfaces are present. + * When all interfaces are removed, the MAC address in the hardware + * must be cleared so the device no longer acknowledges packets, + * the mac_addr member of the conf structure is, however, set to the + * MAC address of the device going away. + * Hence, this callback must be implemented. It can sleep. + */ + struct cl_hw *cl_hw = hw->priv; + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + + if (vif->type == NL80211_IFTYPE_MESH_POINT) + tasklet_kill(&cl_hw->tx_mesh_bcn_task); + + if (!cl_recovery_in_progress(cl_hw)) { + cl_vif_remove(cl_hw, cl_vif); + cl_msg_tx_remove_if(cl_hw, cl_vif->vif_index); + } else { + cl_vif_remove(cl_hw, cl_vif); + } + + /* Return netdev_ops back to it's original configuration */ + cl_vif->dev->netdev_ops = cl_vif->orig_dev_ops; + + cl_vif->cl_hw = NULL; + cl_vif->vif = NULL; + cl_vif->dev = NULL; +} + +static int cl_ops_conf_change_channel(struct ieee80211_hw *hw) +{ + struct cl_hw *cl_hw = hw->priv; + struct cl_chip *chip = cl_hw->chip; + struct cfg80211_chan_def *chandef = &hw->conf.chandef; + enum nl80211_chan_width width = chandef->width; + u32 primary = chandef->chan->center_freq; + u32 center = chandef->center_freq1; + u8 channel = ieee80211_frequency_to_channel(primary); + u8 bw; + + if (!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) || + test_bit(CL_DEV_INIT, &cl_hw->drv_flags)) + return -EBUSY; + + /* WA: for the first set-channel in production mode use the nvram values */ + if (chip->conf->ce_production_mode && !cl_hw->chandef_set) { + cl_hw->chandef_set = true; + cl_chandef_get_default(cl_hw, &width, &primary, ¢er); + channel = cl_hw->conf->ha_channel; + } + + bw = width_to_bw(width); + + if (cl_hw->channel == channel && + cl_hw->bw == bw && + cl_hw->primary_freq == primary && + cl_hw->center_freq == center) + goto check_cac; + + /* + * Flush the pending data to ensure that we will finish the pending + * transmissions before changing the channel + */ + cl_ops_flush(hw, NULL, -1, false); + + if (cl_band_is_6g(cl_hw)) + cl_netlink_send_event_co_locate_update(cl_hw); + + if (cl_msg_tx_set_channel(cl_hw, channel, bw, primary, center)) + return -EIO; + +check_cac: + /* + * TODO: This callback is being spawned even in STA mode, moreover, + * "start_ap" comes later - it is unclear whether we are an AP at this + * stage. Likely, may be solved by moving "force_cac_*" states to beginning + * of "start_ap", but the request should stay in current callback + */ + if (!cl_band_is_5g(cl_hw)) + return 0; + + /* + * Radar listening may occur at DFS channels during in-service mode, + * so CAC may clear the channels, but radar listening should be + * still active, and should start it as soon as we can. + */ + if (hw->conf.radar_enabled) { + /* If channel policy demans to be in CAC - need to request it */ + if (!cl_dfs_is_in_cac(cl_hw) && + chandef->chan->dfs_state == NL80211_DFS_USABLE) + cl_dfs_request_cac(cl_hw, true); + + if (!cl_dfs_radar_listening(cl_hw)) + cl_dfs_radar_listen_start(cl_hw); + } else { + /* + * No sense to continue be in silent mode if the channel was + * cleared + */ + if (cl_dfs_is_in_cac(cl_hw) && + chandef->chan->dfs_state == NL80211_DFS_AVAILABLE) + cl_dfs_request_cac(cl_hw, false); + + if (cl_dfs_radar_listening(cl_hw)) + cl_dfs_radar_listen_end(cl_hw); + } + + /* + * We have just finished channel switch. + * Now, check what to do with CAC. + */ + if (cl_dfs_requested_cac(cl_hw)) + cl_dfs_force_cac_start(cl_hw); + else if (cl_dfs_is_in_cac(cl_hw)) + cl_dfs_force_cac_end(cl_hw); + + return 0; +} + +int cl_ops_config(struct ieee80211_hw *hw, u32 changed) +{ + /* + * Handler for configuration requests. IEEE 802.11 code calls this + * function to change hardware configuration, e.g., channel. + * This function should never fail but returns a negative error code + * if it does. The callback can sleep + */ + int error = 0; + + if (changed & IEEE80211_CONF_CHANGE_CHANNEL) + error = cl_ops_conf_change_channel(hw); + + return error; +} + +/* + * @bss_info_changed: Handler for configuration requests related to BSS + * parameters that may vary during BSS's lifespan, and may affect low + * level driver (e.g. assoc/disassoc status, erp parameters). + * This function should not be used if no BSS has been set, unless + * for association indication. The @changed parameter indicates which + * of the bss parameters has changed when a call is made. The callback + * can sleep. + */ +void cl_ops_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *info, + u32 changed) +{ + struct cl_hw *cl_hw = hw->priv; + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + + if (changed & BSS_CHANGED_ASSOC) { + if (cl_msg_tx_set_associated(cl_hw, info)) + return; + } + + if (changed & BSS_CHANGED_BSSID) { + if (cl_msg_tx_set_bssid(cl_hw, info->bssid, cl_vif->vif_index)) + return; + } + + if (changed & BSS_CHANGED_BEACON_INT) { + if (vif->type == NL80211_IFTYPE_AP || + cl_hw->iface_conf == CL_IFCONF_MESH_ONLY) { + if (cl_msg_tx_set_beacon_int(cl_hw, info->beacon_int, + cl_vif->vif_index)) + return; + if (cl_msg_tx_dtim(cl_hw, info->dtim_period)) + return; + } + + if (vif->type == NL80211_IFTYPE_MESH_POINT && + cl_hw->iface_conf == CL_IFCONF_MESH_AP) + cl_hw->mesh_tbtt_div = (info->beacon_int / + cl_hw->conf->ha_beacon_int); + } + + if (changed & BSS_CHANGED_BASIC_RATES) { + int shift = hw->wiphy->bands[hw->conf.chandef.chan->band]->bitrates[0].hw_value; + + if (cl_msg_tx_set_basic_rates(cl_hw, info->basic_rates << shift)) + return; + /* TODO: check if cl_msg_tx_set_mode() should be called */ + } + + if (changed & BSS_CHANGED_ERP_SLOT) { + /* + * We must be in 11g mode here + * TODO: we can add a check on the mode + */ + if (cl_msg_tx_set_slottime(cl_hw, info->use_short_slot)) + return; + } + + if (changed & BSS_CHANGED_BANDWIDTH) + cl_wrs_api_bss_set_bw(cl_hw, width_to_bw(info->chandef.width)); +} + +int cl_ops_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct cl_hw *cl_hw = hw->priv; + u8 num_ap = cl_tcv_config_get_num_ap(cl_hw); + + /* + * Increase num_ap_started counter and turn radio on only after + * all AP's were started. + */ + cl_hw->num_ap_started++; + + if (num_ap == cl_hw->num_ap_started && + cl_hw->conf->ce_radio_on) { + cl_radio_on(cl_hw); + + return 0; + } + + /* + * Set active state when cl_ops_start_ap() is called not during first driver start + * but rather after removing all interfaces and then doing up again to one interface. + */ + if (cl_radio_is_on(cl_hw) && !cl_recovery_in_progress(cl_hw)) + cl_msg_tx_set_idle(cl_hw, MAC_ACTIVE); + + return 0; +} + +void cl_ops_stop_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct cl_hw *cl_hw = hw->priv; + + cl_hw->num_ap_started--; +} + +u64 cl_ops_prepare_multicast(struct ieee80211_hw *hw, struct netdev_hw_addr_list *mc_list) +{ + return netdev_hw_addr_list_count(mc_list); +} + +void cl_ops_configure_filter(struct ieee80211_hw *hw, u32 changed_flags, + u32 *total_flags, u64 multicast) +{ + /* + * configure_filter: Configure the device's RX filter. + * See the section "Frame filtering" for more information. + * This callback must be implemented and can sleep. + */ + struct cl_hw *cl_hw = hw->priv; + + cl_dbg_trace(cl_hw, "total_flags = 0x%08x\n", *total_flags); + + /* + * Reset our filter flags since our start/stop ops reset + * the programmed settings + */ + if (!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags)) { + *total_flags = 0; + return; + } + + if (multicast) + *total_flags |= FIF_ALLMULTI; + else + *total_flags &= ~FIF_ALLMULTI; + + /* TODO optimize with changed_flags vs multicast */ + cl_msg_tx_set_filter(cl_hw, *total_flags, false); + + /* TODO update total_flags with truly set flags */ + *total_flags &= ~(1 << 31); +} + +int cl_ops_set_key(struct ieee80211_hw *hw, + enum set_key_cmd cmd, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + struct cl_hw *cl_hw = hw->priv; + + return cl_key_set(cl_hw, cmd, vif, sta, key); +} + +void cl_ops_sw_scan_start(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + const u8 *mac_addr) +{ + struct cl_hw *cl_hw = hw->priv; + + if (cl_hw->conf->ce_radio_on && + cl_radio_is_off(cl_hw) && + vif->type == NL80211_IFTYPE_STATION) + cl_radio_on(cl_hw); +} + +int cl_ops_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, + enum ieee80211_sta_state old_state, enum ieee80211_sta_state new_state) +{ + struct cl_hw *cl_hw = hw->priv; + int error = 0; + + if (old_state == new_state) + return 0; + + if (old_state == IEEE80211_STA_NOTEXIST && + new_state == IEEE80211_STA_NONE) { + struct sta_info *stainfo = container_of(sta, struct sta_info, sta); + + cl_sta_init_stainfo(cl_hw, stainfo); + } else if (old_state == IEEE80211_STA_AUTH && + new_state == IEEE80211_STA_ASSOC) { + error = cl_sta_add(cl_hw, vif, sta); + } else if (old_state == IEEE80211_STA_ASSOC && + new_state == IEEE80211_STA_AUTH) { + cl_sta_remove(cl_hw, vif, sta); + } else if (old_state == IEEE80211_STA_ASSOC && + new_state == IEEE80211_STA_AUTHORIZED) { + /* Do nothing, yet */ + } + + return error; +} + +void cl_ops_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + enum sta_notify_cmd cmd, struct ieee80211_sta *sta) +{ + struct cl_hw *cl_hw = (struct cl_hw *)hw->priv; + struct cl_sta *cl_sta = IEEE80211_STA_TO_CL_STA(sta); + bool is_ps = (bool)!cmd; + + cl_sta_ps_notify(cl_hw, cl_sta, is_ps); +} + +int cl_ops_conf_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u16 ac_queue, + const struct ieee80211_tx_queue_params *params) +{ + /* + * Configure TX queue parameters (EDCF (aifs, cw_min, cw_max), + * bursting) for a hardware TX queue. + * Returns a negative error code on failure. + * The callback can sleep. + */ + + /* We only handle STA edca here */ + if (vif->type == NL80211_IFTYPE_STATION) { + struct cl_hw *cl_hw = hw->priv; + struct ieee80211_he_mu_edca_param_ac_rec mu_edca = {0}; + struct edca_params edca_params = { + .aifsn = (u8)(params->aifs), + .cw_min = (u8)(ilog2(params->cw_min + 1)), + .cw_max = (u8)(ilog2(params->cw_max + 1)), + .txop = (u8)(params->txop) + }; + + if (cl_hw->conf->ce_wireless_mode > WIRELESS_MODE_HT_VHT) + memcpy(&mu_edca, ¶ms->mu_edca_param_rec, sizeof(mu_edca)); + + cl_edca_set(cl_hw, cl_ac2edca[ac_queue], &edca_params, &mu_edca); + } + return 0; +} + +void cl_ops_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + u32 changed) +{ + struct cl_hw *cl_hw = (struct cl_hw *)hw->priv; + + if (changed & IEEE80211_RC_BW_CHANGED) + cl_wrs_api_bw_changed(cl_hw, sta, sta->bandwidth); + + if (changed & IEEE80211_RC_SMPS_CHANGED) { + struct sta_info *stainfo = container_of(sta, struct sta_info, sta); + + cl_wrs_api_set_smps_mode(cl_hw, sta, stainfo->cur_max_bandwidth); + } + + WARN_ON(sta->rx_nss == 0); + if (changed & IEEE80211_RC_NSS_CHANGED) { + u8 nss = min_t(u8, sta->rx_nss, WRS_SS_MAX) - 1; + + cl_wrs_api_nss_changed(cl_hw, sta, nss); + } +} + +int cl_ops_ampdu_action(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_ampdu_params *params) +{ + struct cl_hw *cl_hw = (struct cl_hw *)hw->priv; + struct cl_sta *cl_sta = IEEE80211_STA_TO_CL_STA(params->sta); + int ret = 0; + + switch (params->action) { + case IEEE80211_AMPDU_RX_START: + ret = cl_ampdu_rx_start(cl_hw, cl_sta, params->tid, + params->ssn, params->buf_size); + break; + case IEEE80211_AMPDU_RX_STOP: + cl_ampdu_rx_stop(cl_hw, cl_sta, params->tid); + break; + case IEEE80211_AMPDU_TX_START: + ret = cl_ampdu_tx_start(cl_hw, vif, cl_sta, params->tid, + params->ssn); + break; + case IEEE80211_AMPDU_TX_OPERATIONAL: + ret = cl_ampdu_tx_operational(cl_hw, cl_sta, params->tid, + params->buf_size, params->amsdu); + break; + case IEEE80211_AMPDU_TX_STOP_CONT: + case IEEE80211_AMPDU_TX_STOP_FLUSH: + case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: + ret = cl_ampdu_tx_stop(cl_hw, vif, params->action, cl_sta, + params->tid); + break; + default: + pr_warn("Error: Unknown AMPDU action (%d)\n", params->action); + } + + return ret; +} + +int cl_ops_post_channel_switch(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + /* TODO: Handle event */ + + return 0; +} + +void cl_ops_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u32 queues, bool drop) +{ + struct cl_hw *cl_hw = hw->priv; + int flush_duration; + + if (test_bit(CL_DEV_HW_RESTART, &cl_hw->drv_flags)) { + cl_dbg_verbose(cl_hw, ": bypassing (CL_DEV_HW_RESTART set)\n"); + return; + } + + /* Wait for a maximum time of 200ms until all pending frames are flushed */ + for (flush_duration = 0; flush_duration < 200; flush_duration++) { + if (!cl_txq_frames_pending(cl_hw)) + return; + + /* Lets sleep and hope for the best */ + usleep_range(1000, 2000); + } +} + +bool cl_ops_tx_frames_pending(struct ieee80211_hw *hw) +{ + struct cl_hw *cl_hw = hw->priv; + + return cl_txq_frames_pending(cl_hw); +} + +void cl_ops_reconfig_complete(struct ieee80211_hw *hw, + enum ieee80211_reconfig_type reconfig_type) +{ + struct cl_hw *cl_hw = hw->priv; + + cl_recovery_reconfig_complete(cl_hw); +} + +int cl_ops_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, int *dbm) +{ + struct cl_hw *cl_hw = hw->priv; + + if (cl_hw->phy_data_info.data) + *dbm = cl_power_get_max(cl_hw); + else + *dbm = 0; + + return 0; +} + +int cl_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value) +{ + return 0; +} + +static void cl_ops_mgd_assoc(struct cl_hw *cl_hw, struct ieee80211_vif *vif) +{ + struct ieee80211_sub_if_data *sdata = container_of(vif, struct ieee80211_sub_if_data, vif); + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + struct ieee80211_sta *sta = ieee80211_find_sta(vif, sdata->u.mgd.bssid); + + if (!sta) { + /* Should never happen */ + cl_dbg_verbose(cl_hw, "sta is NULL !!!\n"); + return; + } + + cl_sta_mgd_add(cl_hw, cl_vif, sta); + + if (cl_hw->iface_conf == CL_IFCONF_REPEATER) { + cl_vif_ap_tx_enable(cl_hw, true); + set_bit(CL_DEV_REPEATER, &cl_hw->drv_flags); + } +} + +static void cl_ops_mgd_disassoc(struct cl_hw *cl_hw) +{ + if (cl_hw->iface_conf == CL_IFCONF_REPEATER) { + cl_sta_disassociate_ap_iface(cl_hw); + cl_vif_ap_tx_enable(cl_hw, false); + clear_bit(CL_DEV_REPEATER, &cl_hw->drv_flags); + } +} + +void cl_ops_event_callback(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + const struct ieee80211_event *event) +{ + struct cl_hw *cl_hw = hw->priv; + + if (event->type == MLME_EVENT) { + if (event->u.mlme.data == ASSOC_EVENT && + event->u.mlme.status == MLME_SUCCESS) + cl_ops_mgd_assoc(cl_hw, vif); + else if (event->u.mlme.data == DEAUTH_TX_EVENT || + event->u.mlme.data == DEAUTH_RX_EVENT) + cl_ops_mgd_disassoc(cl_hw); + } +} + +/* This function is required for PS flow - do not remove */ +int cl_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set) +{ + return 0; +} From patchwork Thu Jun 17 16:00:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DF9AC49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 124/256] cl8k: add ops.h Date: Thu, 17 Jun 2021 16:00:11 +0000 Message-Id: <20210617160223.160998-125-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:50 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 16a6c21d-1104-4644-872a-08d931a9a329 X-MS-TrafficTypeDiagnostic: AM9P192MB1314: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Q14HuzLLe3dHRIulo3hLbbA8XnqUqUdSz/2zCnIKPACTpcMbC27ZnTDEmUW2QEquRFuKpGQe3xteW2DRoWspBMAHIRXviRUze6/4EzM2TE3vLii66sR168OavPi6Ok8uMiuN8m97ywy/FyGdAakhLflIbBPbNwrv55zPX+A9DV+gl8X9gAs/2ANO2alw5pSV+Bphx0vHvFl8E2rE2fwUzNn0SsSScOUrPqqoUC5lF5+d2t0uthOBYlGEVrTqLdrinBW0PSC7JQG6Aei3Gf5LPw/iI3ALkUmd8MpWS28W5aYe9gDnFbACvL6pBq8sGTzAtz9aOIoX1G4qHLbcgIDYy/+QTg0HgcO0L71o5Ev9sGsgyrgl9n69SRbJh5IKBLYu8rGQqFP8ifC+U21UZzcmihuJMs/PtcEKQxqd7Sz4P+duR9pp4FfrSJDAXrNvuv3FxfZrDeGDE9NUv8N9Hrh8LcD6xXhKMvzIPOfHvyo/r9CsOZ6NAprWIHOE5PaPQ273YJht1TLgXthdJRtUyMKmP65AI6xtINZCcQfVfTfgqsHdIY0tD1fJB4fwb4i0i1QlYfl/KdODaVHZQ0P9CnMuRYuVxwJQ24Hx8mrx8jHWcvRM3izds9A9J9496KoeiN6uS51+0kjiWtma7LGYMuDVRtLR0ozQBfz/xq01vuVdY/QgpUpwYfaN0JCwZiqvXt69u4jgFlpDoLyp+owAxoXfCg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(39840400004)(366004)(376002)(136003)(346002)(8936002)(66946007)(83380400001)(186003)(5660300002)(26005)(36756003)(86362001)(8676002)(55236004)(1076003)(6916009)(2906002)(6506007)(66476007)(478600001)(6666004)(38350700002)(52116002)(66556008)(956004)(4326008)(107886003)(54906003)(38100700002)(6486002)(2616005)(316002)(16526019)(6512007)(9686003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XGVYlggI2F5+9xf5T7bEledj4boVUNtYvDYi5EEClHvqkjGp8688ap/79FKUa2sQp+U1zL/v7/1m3n3LZf1hU0g+g4PVSvCr55nmeib28hc96EU5ydORWKPJx5iMNdBXWdnreokKAOiX3OfeCIp3hDP/OsS4G+rbpNOYztNW/1nw/H6Uhh3UrdVEOtMvVpBfT9dAjVPj27K+57gB8lLPGANf6J2s4C8s/qGajuxSn1XVXJnNphryNX9Yt3BuMedG3O4tejmhwNW+LGlx5FUoP4osRgowIsJk88/tAIH7I6GlKx6/tn6AzSCLqb4+SPXuTyZkqq5hXPOI/QYBjXLuATnpRA4IH4gVLT6Ws/6BI9+lXUwd0mNPiUv/uQCyUZLaOCK0Cgem3JADP1bT9QBzgioNcwLV6XT1+wvtcW4UbwIkUXHllRm4eU+GWAXAi8XIB0tIF8VXFYYmMhPJ3sZQtdEg8rJQcl27ZPWbrO1GF1fzcv9WMNr1eZK5xcvj25CbhDsoEUjIt+NQ5AZoDLJ3HHG/a2qDWTo89PC2byxHVZYpOCwULCxBBz7gcwsV//9Awl55DkIT6WjsBqlAqHR242cCJmOSMMp3k9vq6I5dslEc1TeLDFh7F4R2oin9zzUa20b1aTGQi3HB1C4Orkjxjgc3GFpfuH84ms2luuDZwgyi8gtSUrMcdTP4r8oqvC1Ig+UIhCFivna5qvxTVfEsv/p4FruQZtGM3Hqm4hH9ZfGMVblCPmOpqlDBXIhTEghnct1l9KH06hR29fC32AYovIthBipJrI8h0pt98l1G4uNYBLaDcZkA2J0S+qk/OHqQA2MK6zG5zbgLk7frjy5SQ25wfvu/8cAKRTxFn+zYhSrxxwNV5v1tWTrLnf/lNFxxJYr2AVFHpsr86Qg94Ze+kSMqiTw527lDG9rs5GqNKI1eTLzmFE9g/kt5RB7axCDRWY+nNzJDRhk+evfh98mGGIo6/ULjlxmLp7lYRGrkrwUGugZKlASf0MMKa0ZpTGbGz/aPW466SwANxpJ6+U1xAUJY8GUVqqxD2/gBA5OkZfzDPYF0KYGyjDmqolLpx1S0zxUYF88lHeZtUhExm1tkO/RoAXTomir66udYTQ+2dwa7v5WPPxtDqX+UlHTUJVHYrMBGsndPlnAXnsXyAZqGRdpacAEsP14+DQan5Gh5MSZsa7pk9F03J3Yyji2qVBXM4ai0Y1iKH/hE6gaeM+khBSuZgdE56KFwybMfnc6MKRc7vOB0aGCIXR4H27sBsdC048swOpn4O/lWONqDuljPzQ2YooY4maawEJAxAY7cNaRYfvugTrWAdOyoEAvpjsxS X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 16a6c21d-1104-4644-872a-08d931a9a329 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:50.7571 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6MeHRiXItLwaObbqF/qDelC7g61IqJIi9JlviAGYom57WHv65DRi/oTyfE3v+MSYdHvfnMnFfQReYy5Q4C/cUg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1314 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/ops.h | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/ops.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/ops.h b/drivers/net/wireless/celeno/cl8k/ops.h new file mode 100644 index 000000000000..24532f9efacc --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/ops.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_OPS_H +#define CL_OPS_H + +#include + +void cl_ops_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb); +int cl_ops_start(struct ieee80211_hw *hw); +void cl_ops_stop(struct ieee80211_hw *hw); +int cl_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +void cl_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +int cl_ops_config(struct ieee80211_hw *hw, u32 changed); +void cl_ops_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *info, + u32 changed); +int cl_ops_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +void cl_ops_stop_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif); +u64 cl_ops_prepare_multicast(struct ieee80211_hw *hw, struct netdev_hw_addr_list *mc_list); +void cl_ops_configure_filter(struct ieee80211_hw *hw, u32 changed_flags, + u32 *total_flags, u64 multicast); +int cl_ops_set_key(struct ieee80211_hw *hw, + enum set_key_cmd cmd, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key); +void cl_ops_sw_scan_start(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + const u8 *mac_addr); +int cl_ops_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, + enum ieee80211_sta_state old_state, enum ieee80211_sta_state new_state); +void cl_ops_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + enum sta_notify_cmd cmd, struct ieee80211_sta *sta); +int cl_ops_conf_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u16 ac_queue, + const struct ieee80211_tx_queue_params *params); +void cl_ops_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + u32 changed); +int cl_ops_ampdu_action(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_ampdu_params *params); +int cl_ops_post_channel_switch(struct ieee80211_hw *hw, + struct ieee80211_vif *vif); +void cl_ops_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u32 queues, bool drop); +bool cl_ops_tx_frames_pending(struct ieee80211_hw *hw); +void cl_ops_reconfig_complete(struct ieee80211_hw *hw, + enum ieee80211_reconfig_type reconfig_type); +int cl_ops_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, int *dbm); +int cl_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value); +void cl_ops_event_callback(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + const struct ieee80211_event *event); +int cl_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); + +#endif /* CL_OPS_H */ From patchwork Thu Jun 17 16:00:13 2021 Content-Type: text/plain; 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Thu, 17 Jun 2021 16:05:44 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 126/256] cl8k: add phy/phy.h Date: Thu, 17 Jun 2021 16:00:13 +0000 Message-Id: <20210617160223.160998-127-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:04:52 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4dc8198a-9579-4055-e684-08d931a9a453 X-MS-TrafficTypeDiagnostic: AM9P192MB1314: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7UDPCl8fG56JMcNIlGLWX1ZV6oPDJviVJ3Q5WT0JZwJACUsKmux0Dc+lrMtc8CXzjxK69I1Z5lCpfR23OzSrEYZfOgnqUdbPLKt+l36gwDhcvxydggK4Pap8jo7lkq1Mmrxm9g42bV8jZLaThFuhjoqMoJFJX6/CXVF0pRZw//Xp7M6CdA6BfsXpHHZPIF6IO+JCpcuTnMJ5dt0NB0GG3Gmfr0ErNsMNi0xDMiJ3tSQ/5w3exdkxfQmiJ0pAwbF9Ufa8ozPBZeD3iofivuTJeGNxkBZMA2JQrIsi94qauAl8hlsLQM0ACwYE1KG9Oa9PaeVKmaYDDxctIWm1XwTqzWEELD1Io0eRhYh9D1bFd6NAlD2CrVSAPhyvH9+l2Wvc9jYUeUQlBfCl8RSe9egkjwNz4dqhBBIc6M9xfbk8U2trF6x55gOVmj65c1JTcFzxzxsQe1HvWAkqeXkbRef3hKye8vW5RGVkufVj40/sPAw9mzAPRgPao9L0GcvvdI+c5+J/xyLCojrYz7bgty+se2PUemPpN7Isqx3n74C7IVRxm5t6EPwS1PTtFUNBCMB0Bmp+JRxdzC1IoR/IzkC+zgDn7PgMvPkoH0fs5flfCqRdDyaLpM/5oziLYOJrbaEscPPIOi3cRvJ/iRhqUA2CScGAtZwfWWZOTg6jnKddfw8DSw5+rteUngk6BDPTgmfQDMo2zP+bq3B4ajdBpWq5Fw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(39840400004)(366004)(376002)(136003)(346002)(8936002)(66946007)(83380400001)(186003)(5660300002)(26005)(36756003)(86362001)(8676002)(55236004)(1076003)(6916009)(2906002)(6506007)(66476007)(478600001)(6666004)(38350700002)(52116002)(66556008)(956004)(4326008)(107886003)(54906003)(38100700002)(6486002)(2616005)(316002)(16526019)(6512007)(9686003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YCx+sg2hj/XH0pi4P57B58NpnQngvLHy8f76dNXZpb5DvTHf/eImqmCWJ11FQjEJM44xeQ8g/u/Gpf/J7s8bL3Oxr2WevNAkyQy4rb+UVCBd2u//pjdUb4fNojlz5uFB8u8ZYtTeQm0cu2CMJdnQfPWCpFoeuP3P3OxptCqjnkxl//kRR/gdFDbk9f2WzKZaYwC7Nc4bVMu/3beHJoyoodu9NQHRZbPIukU5PaqP44tw+DKgHvfzu06pxWH6poByn0BcHw0A81U1zTh5nicBS1FSqTTGAzRzErkBYd0WLc/Lw/3/KLY9toEpLsVE8ybU3VxSe3R/w+cEyolywkeuft6uCBtFZsCqYnnzMvPSXm3MfRq7yZlkd1QgtWZJgZzBdMNjnBtD/VpUTTJ+rqpUcMMryDzod4KxDldn6N3rhpMrTJ1udfmX1bnlKgcCCjr+eNl8Yk6O4uWuf4i+qOpYOs/Q5tdYXqJ1dVDSw6dBiZIsC00/qRb3aoggqSF2p1inDX5DWuIB3MikNMy8uSmvd05yESuOGAg4Gud+oIIITjfAWvaWXGttaeswl1DcI5ut1zM8wMT3T1Q7yKbN+DSSuZiKVtor3DSFtLnl94f88ZCJA83XlwTwmq5nAdgq915LVRLCvl4u0R03+x2Xm7pUi+iLm/vbzaSviQB0dGwkNX5VNn+qcifjaY+c1W+YXbHu/mx1V1Bqfr5OD/9GR8xv6hzWMKZE5gP1gkefnes53d8nKU79RlvpnjkK2qAP4LX1+7Xxwxn/iQlXWCSxMrFJsQuabmpDnJc9Vheald9399oW/kivyV6pqFiozFib51Kp368BmQSDbsSat2VoiNTbnX+pdU5hdkROcClcNt5L7POzv4T+44Z9KKTcl9cNDuGa9D1YhfRlZt6dj3q8+6DUkYaA40tvdMvQdNQvjWj9tygHMl+oZhymwQ9Dxq3wTvDCRt1VO+K1USEeNaia7zJG7cMYzCE6z79rOhB/+psTnr/kT4G1Mq+U1TKgAvZiNYzhIJtktEe40FqWN18ihYZcG6h7e1HWoPfLDpS8lb3QhBegD0hjRHqao3qJe8V7d9bPyDBwxYaTjUsSaLKbDOrxJ3Lgqxp+RPlflaVonV/NcJQHsME1t0nHl8TbQmG7BJHpHI/xXkKlWIqjeSgEaXJqsOO4vj3IPKfAzvgQY9juN1/WEnbZEkfyk4mdqm2c6m0nQfl1kPZeDBWM9ZaP+p48F/rRqWQbLxS4uoE7Ep+RvG1X6JzE/C5xZ+VxdAfPx0NDe+HFCByTh+SJGZlD12uSN/x2mSE/qzXzs1mpjgVYIDX1j/DqCUoqI0B7++5WtE/r X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4dc8198a-9579-4055-e684-08d931a9a453 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:04:52.7215 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: abX4lO6BGvLBl3ca1wKLNEuDI3p4l3hKB3LwUU4wQVGnOvNss0Z0ikD0qxtZJm0lFHW/56DLO0FalhSnabfTZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1314 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/phy/phy.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/phy/phy.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/phy/phy.h b/drivers/net/wireless/celeno/cl8k/phy/phy.h new file mode 100644 index 000000000000..6a58faf2cfd8 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/phy/phy.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_PHY_H +#define CL_PHY_H + +#include "hw.h" +#include "chip.h" + +void cl_phy_reset(struct cl_hw *cl_hw); +void cl_phy_off(struct cl_hw *cl_hw); +int cl_phy_load_recovery(struct cl_hw *cl_hw); +int cl_phy_data_alloc(struct cl_hw *cl_hw); +void cl_phy_data_free(struct cl_hw *cl_hw); +void cl_phy_enable(struct cl_hw *cl_hw); + +#endif /* CL_PHY_H */ From patchwork Thu Jun 17 16:00:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E28EBC48BE5 for ; Thu, 17 Jun 2021 16:09:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A03B761407 for ; Thu, 17 Jun 2021 16:09:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230457AbhFQQLn (ORCPT ); Thu, 17 Jun 2021 12:11:43 -0400 Received: from mail-vi1eur05on2070.outbound.protection.outlook.com ([40.107.21.70]:44832 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232409AbhFQQKY (ORCPT ); Thu, 17 Jun 2021 12:10:24 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aXHu6ga++UixHDaa8HPALjcQ2s2fUrNAVPyBx1gXuhXxTJhbRjduFGxJbntqV9LszSILCE8iVkgg+Leo2Q5MEjB6CSelxu2Uq9Y1A+oG1HtOcOnoukBbNZNtKyHiXGD4SQL+8Hi2w1ou5xfjMGKHjdoGeL01DkGcAK8R1kZ6tOVnZdpl7X1O+SNj62GjQvEzcs24yURsDbxdpU0q40Onr/V594vpjfSbSf1A1uRvvy/rRaKljmeGR/12bJvNnmeTupVUZHmqVvihOCarsJJLR9MBJ5lywg8NUPhdqEc+kPuqOu/4iyyGCUal/MkBzU2CeG3EYyq2QutFId0oIv5UvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6wlKRKAdnKD89wbNrDPAizfC2atXSF8LgyT/uOpRZk0=; b=NdyYofNfxPz39siPMRojEySLDrDtupCSCFcl9Sqv0+Omgrkv2LIkGqUZrOcKAY0jqbNFHAjqLEgkuNMkvQGLN2K0kBEbsfOzBW+QjOYHKIA1AyA1VH99sTQ0iSopAP53qWZ3b6lGigshCEsNkBJKdhNfGzH9DoYbj00U0HfW7qyJhGVhGAsN3RjKy06GXRm1j28HK35e5ryLUnN4dSx/uI4wbvduTgdjJqMSGlZ0+2pD25+Y4FL6pq/ewhqV9YZ9t4kGzVnWnXBPybHt6CQ+l5I9OU0hLQRrWnhgUbAGAa2mWbt1BUnTae9giM17GRlQas4p6Cdtzeb7QFSttH3+Pw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6wlKRKAdnKD89wbNrDPAizfC2atXSF8LgyT/uOpRZk0=; b=F/6sS1mG+TDblRx9mVvKn7nWARUr7IsBm7t5LLmIA9lfRUK0O1TzQiXhUvYzt3qTfMnSAvew/NH5QBynZwV9nbolUPilezcX9+AfDys6dH+YbKa1HWiqMKMIaw9qnZOJG8dAGklnHly2pdHLSNl599k+nenwX9KjrWU5JobGMk8= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1314.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3a6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:05:45 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:45 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/phy/phy_athos_lut.c | 2069 +++++++++++++++++ 1 file changed, 2069 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/phy/phy_athos_lut.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/phy/phy_athos_lut.c b/drivers/net/wireless/celeno/cl8k/phy/phy_athos_lut.c new file mode 100644 index 000000000000..5a42e55116c0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/phy/phy_athos_lut.c @@ -0,0 +1,2069 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "phy_athos_lut.h" + +const struct athos_lut_line athos_lut_6g_40_mhz[ATHOS_LUT_CHAN_6G_MAX] = { + [ATHOS_LUT_CHAN_593000_IDX] = { 23720, 0x0, 0x62, 0x1AAAAB, 0x7B9 }, + [ATHOS_LUT_CHAN_593125_IDX] = { 23725, 0x0, 0x62, 0x1B5555, 0x7B9 }, + [ATHOS_LUT_CHAN_593250_IDX] = { 23730, 0x0, 0x62, 0x1C0000, 0x7BA }, + [ATHOS_LUT_CHAN_593375_IDX] = { 23735, 0x0, 0x62, 0x1CAAAB, 0x7BA }, + [ATHOS_LUT_CHAN_593500_IDX] = { 23740, 0x0, 0x62, 0x1D5555, 0x7BA }, + [ATHOS_LUT_CHAN_593625_IDX] = { 23745, 0x0, 0x62, 0x1E0000, 0x7BB }, + [ATHOS_LUT_CHAN_593750_IDX] = { 23750, 0x0, 0x62, 0x1EAAAB, 0x7BB }, + [ATHOS_LUT_CHAN_593875_IDX] = { 23755, 0x0, 0x62, 0x1F5555, 0x7BC }, + [ATHOS_LUT_CHAN_594000_IDX] = { 23760, 0x0, 0x63, 0x0, 0x7BC }, + [ATHOS_LUT_CHAN_594125_IDX] = { 23765, 0x0, 0x63, 0xAAAB, 0x7BC }, + [ATHOS_LUT_CHAN_594250_IDX] = { 23770, 0x0, 0x63, 0x15555, 0x7BD }, + [ATHOS_LUT_CHAN_594375_IDX] = { 23775, 0x0, 0x63, 0x20000, 0x7BD }, + [ATHOS_LUT_CHAN_594500_IDX] = { 23780, 0x0, 0x63, 0x2AAAB, 0x7BE }, + [ATHOS_LUT_CHAN_594625_IDX] = { 23785, 0x0, 0x63, 0x35555, 0x7BE }, + [ATHOS_LUT_CHAN_594750_IDX] = { 23790, 0x0, 0x63, 0x40000, 0x7BF }, + [ATHOS_LUT_CHAN_594875_IDX] = { 23795, 0x0, 0x63, 0x4AAAB, 0x7BF }, + [ATHOS_LUT_CHAN_595000_IDX] = { 23800, 0x0, 0x63, 0x55555, 0x7BF }, + [ATHOS_LUT_CHAN_595125_IDX] = { 23805, 0x0, 0x63, 0x60000, 0x7C0 }, + [ATHOS_LUT_CHAN_595250_IDX] = { 23810, 0x0, 0x63, 0x6AAAB, 0x7C0 }, + [ATHOS_LUT_CHAN_595375_IDX] = { 23815, 0x0, 0x63, 0x75555, 0x7C1 }, + [ATHOS_LUT_CHAN_595500_IDX] = { 23820, 0x0, 0x63, 0x80000, 0x7C1 }, + [ATHOS_LUT_CHAN_595625_IDX] = { 23825, 0x0, 0x63, 0x8AAAB, 0x7C1 }, + [ATHOS_LUT_CHAN_595750_IDX] = { 23830, 0x0, 0x63, 0x95555, 0x7C2 }, + [ATHOS_LUT_CHAN_595875_IDX] = { 23835, 0x0, 0x63, 0xA0000, 0x7C2 }, + [ATHOS_LUT_CHAN_596000_IDX] = { 23840, 0x0, 0x63, 0xAAAAB, 0x7C3 }, + [ATHOS_LUT_CHAN_596125_IDX] = { 23845, 0x0, 0x63, 0xB5555, 0x7C3 }, + [ATHOS_LUT_CHAN_596250_IDX] = { 23850, 0x0, 0x63, 0xC0000, 0x7C4 }, + [ATHOS_LUT_CHAN_596375_IDX] = { 23855, 0x0, 0x63, 0xCAAAB, 0x7C4 }, + [ATHOS_LUT_CHAN_596500_IDX] = { 23860, 0x0, 0x63, 0xD5555, 0x7C4 }, + [ATHOS_LUT_CHAN_596625_IDX] = { 23865, 0x0, 0x63, 0xE0000, 0x7C5 }, + [ATHOS_LUT_CHAN_596750_IDX] = { 23870, 0x0, 0x63, 0xEAAAB, 0x7C5 }, + [ATHOS_LUT_CHAN_596875_IDX] = { 23875, 0x0, 0x63, 0xF5555, 0x7C6 }, + [ATHOS_LUT_CHAN_597000_IDX] = { 23880, 0x0, 0x63, 0x100000, 0x7C6 }, + [ATHOS_LUT_CHAN_597125_IDX] = { 23885, 0x0, 0x63, 0x10AAAB, 0x7C6 }, + [ATHOS_LUT_CHAN_597250_IDX] = { 23890, 0x0, 0x63, 0x115555, 0x7C7 }, + [ATHOS_LUT_CHAN_597375_IDX] = { 23895, 0x0, 0x63, 0x120000, 0x7C7 }, + [ATHOS_LUT_CHAN_597500_IDX] = { 23900, 0x0, 0x63, 0x12AAAB, 0x7C8 }, + [ATHOS_LUT_CHAN_597625_IDX] = { 23905, 0x0, 0x63, 0x135555, 0x7C8 }, + [ATHOS_LUT_CHAN_597750_IDX] = { 23910, 0x0, 0x63, 0x140000, 0x7C9 }, + [ATHOS_LUT_CHAN_597875_IDX] = { 23915, 0x0, 0x63, 0x14AAAB, 0x7C9 }, + [ATHOS_LUT_CHAN_598000_IDX] = { 23920, 0x0, 0x63, 0x155555, 0x7C9 }, + [ATHOS_LUT_CHAN_598125_IDX] = { 23925, 0x0, 0x63, 0x160000, 0x7CA }, + [ATHOS_LUT_CHAN_598250_IDX] = { 23930, 0x0, 0x63, 0x16AAAB, 0x7CA }, + [ATHOS_LUT_CHAN_598375_IDX] = { 23935, 0x0, 0x63, 0x175555, 0x7CB }, + [ATHOS_LUT_CHAN_598500_IDX] = { 23940, 0x0, 0x63, 0x180000, 0x7CB }, + [ATHOS_LUT_CHAN_598625_IDX] = { 23945, 0x0, 0x63, 0x18AAAB, 0x7CB }, + [ATHOS_LUT_CHAN_598750_IDX] = { 23950, 0x0, 0x63, 0x195555, 0x7CC }, + [ATHOS_LUT_CHAN_598875_IDX] = { 23955, 0x0, 0x63, 0x1A0000, 0x7CC }, + [ATHOS_LUT_CHAN_599000_IDX] = { 23960, 0x0, 0x63, 0x1AAAAB, 0x7CD }, + [ATHOS_LUT_CHAN_599125_IDX] = { 23965, 0x0, 0x63, 0x1B5555, 0x7CD }, + [ATHOS_LUT_CHAN_599250_IDX] = { 23970, 0x0, 0x63, 0x1C0000, 0x7CE }, + [ATHOS_LUT_CHAN_599375_IDX] = { 23975, 0x0, 0x63, 0x1CAAAB, 0x7CE }, + [ATHOS_LUT_CHAN_599500_IDX] = { 23980, 0x0, 0x63, 0x1D5555, 0x7CE }, + [ATHOS_LUT_CHAN_599625_IDX] = { 23985, 0x0, 0x63, 0x1E0000, 0x7CF }, + [ATHOS_LUT_CHAN_599750_IDX] = { 23990, 0x0, 0x63, 0x1EAAAB, 0x7CF }, + [ATHOS_LUT_CHAN_599875_IDX] = { 23995, 0x0, 0x63, 0x1F5555, 0x7D0 }, + [ATHOS_LUT_CHAN_600000_IDX] = { 24000, 0x0, 0x64, 0x0, 0x7D0 }, + [ATHOS_LUT_CHAN_600125_IDX] = { 24005, 0x0, 0x64, 0xAAAB, 0x7D0 }, + [ATHOS_LUT_CHAN_600250_IDX] = { 24010, 0x0, 0x64, 0x15555, 0x7D1 }, + [ATHOS_LUT_CHAN_600375_IDX] = { 24015, 0x0, 0x64, 0x20000, 0x7D1 }, + [ATHOS_LUT_CHAN_600500_IDX] = { 24020, 0x0, 0x64, 0x2AAAB, 0x7D2 }, + [ATHOS_LUT_CHAN_600625_IDX] = { 24025, 0x0, 0x64, 0x35555, 0x7D2 }, + [ATHOS_LUT_CHAN_600750_IDX] = { 24030, 0x0, 0x64, 0x40000, 0x7D3 }, + [ATHOS_LUT_CHAN_600875_IDX] = { 24035, 0x0, 0x64, 0x4AAAB, 0x7D3 }, + [ATHOS_LUT_CHAN_601000_IDX] = { 24040, 0x0, 0x64, 0x55555, 0x7D3 }, + [ATHOS_LUT_CHAN_601125_IDX] = { 24045, 0x0, 0x64, 0x60000, 0x7D4 }, + [ATHOS_LUT_CHAN_601250_IDX] = { 24050, 0x0, 0x64, 0x6AAAB, 0x7D4 }, + [ATHOS_LUT_CHAN_601375_IDX] = { 24055, 0x0, 0x64, 0x75555, 0x7D5 }, + [ATHOS_LUT_CHAN_601500_IDX] = { 24060, 0x0, 0x64, 0x80000, 0x7D5 }, + [ATHOS_LUT_CHAN_601625_IDX] = { 24065, 0x0, 0x64, 0x8AAAB, 0x7D5 }, + [ATHOS_LUT_CHAN_601750_IDX] = { 24070, 0x0, 0x64, 0x95555, 0x7D6 }, + [ATHOS_LUT_CHAN_601875_IDX] = { 24075, 0x0, 0x64, 0xA0000, 0x7D6 }, + [ATHOS_LUT_CHAN_602000_IDX] = { 24080, 0x0, 0x64, 0xAAAAB, 0x7D7 }, + [ATHOS_LUT_CHAN_602125_IDX] = { 24085, 0x0, 0x64, 0xB5555, 0x7D7 }, + [ATHOS_LUT_CHAN_602250_IDX] = { 24090, 0x0, 0x64, 0xC0000, 0x7D8 }, + [ATHOS_LUT_CHAN_602375_IDX] = { 24095, 0x0, 0x64, 0xCAAAB, 0x7D8 }, + [ATHOS_LUT_CHAN_602500_IDX] = { 24100, 0x0, 0x64, 0xD5555, 0x7D8 }, + [ATHOS_LUT_CHAN_602625_IDX] = { 24105, 0x0, 0x64, 0xE0000, 0x7D9 }, + [ATHOS_LUT_CHAN_602750_IDX] = { 24110, 0x0, 0x64, 0xEAAAB, 0x7D9 }, + [ATHOS_LUT_CHAN_602875_IDX] = { 24115, 0x0, 0x64, 0xF5555, 0x7DA }, + [ATHOS_LUT_CHAN_603000_IDX] = { 24120, 0x0, 0x64, 0x100000, 0x7DA }, + [ATHOS_LUT_CHAN_603125_IDX] = { 24125, 0x0, 0x64, 0x10AAAB, 0x7DA }, + [ATHOS_LUT_CHAN_603250_IDX] = { 24130, 0x0, 0x64, 0x115555, 0x7DB }, + [ATHOS_LUT_CHAN_603375_IDX] = { 24135, 0x0, 0x64, 0x120000, 0x7DB }, + [ATHOS_LUT_CHAN_603500_IDX] = { 24140, 0x0, 0x64, 0x12AAAB, 0x7DC }, + [ATHOS_LUT_CHAN_603625_IDX] = { 24145, 0x0, 0x64, 0x135555, 0x7DC }, + [ATHOS_LUT_CHAN_603750_IDX] = { 24150, 0x0, 0x64, 0x140000, 0x7DD }, + [ATHOS_LUT_CHAN_603875_IDX] = { 24155, 0x0, 0x64, 0x14AAAB, 0x7DD }, + [ATHOS_LUT_CHAN_604000_IDX] = { 24160, 0x0, 0x64, 0x155555, 0x7DD }, + [ATHOS_LUT_CHAN_604125_IDX] = { 24165, 0x0, 0x64, 0x160000, 0x7DE }, + [ATHOS_LUT_CHAN_604250_IDX] = { 24170, 0x0, 0x64, 0x16AAAB, 0x7DE }, + [ATHOS_LUT_CHAN_604375_IDX] = { 24175, 0x0, 0x64, 0x175555, 0x7DF }, + [ATHOS_LUT_CHAN_604500_IDX] = { 24180, 0x0, 0x64, 0x180000, 0x7DF }, + [ATHOS_LUT_CHAN_604625_IDX] = { 24185, 0x0, 0x64, 0x18AAAB, 0x7DF }, + [ATHOS_LUT_CHAN_604750_IDX] = { 24190, 0x0, 0x64, 0x195555, 0x7E0 }, + [ATHOS_LUT_CHAN_604875_IDX] = { 24195, 0x0, 0x64, 0x1A0000, 0x7E0 }, + [ATHOS_LUT_CHAN_605000_IDX] = { 24200, 0x0, 0x64, 0x1AAAAB, 0x7E1 }, + [ATHOS_LUT_CHAN_605125_IDX] = { 24205, 0x0, 0x64, 0x1B5555, 0x7E1 }, + [ATHOS_LUT_CHAN_605250_IDX] = { 24210, 0x0, 0x64, 0x1C0000, 0x7E2 }, + [ATHOS_LUT_CHAN_605375_IDX] = { 24215, 0x0, 0x64, 0x1CAAAB, 0x7E2 }, + [ATHOS_LUT_CHAN_605500_IDX] = { 24220, 0x0, 0x64, 0x1D5555, 0x7E2 }, + [ATHOS_LUT_CHAN_605625_IDX] = { 24225, 0x0, 0x64, 0x1E0000, 0x7E3 }, + [ATHOS_LUT_CHAN_605750_IDX] = { 24230, 0x0, 0x64, 0x1EAAAB, 0x7E3 }, + [ATHOS_LUT_CHAN_605875_IDX] = { 24235, 0x0, 0x64, 0x1F5555, 0x7E4 }, + [ATHOS_LUT_CHAN_606000_IDX] = { 24240, 0x0, 0x65, 0x0, 0x7E4 }, + [ATHOS_LUT_CHAN_606125_IDX] = { 24245, 0x0, 0x65, 0xAAAB, 0x7E4 }, + [ATHOS_LUT_CHAN_606250_IDX] = { 24250, 0x0, 0x65, 0x15555, 0x7E5 }, + [ATHOS_LUT_CHAN_606375_IDX] = { 24255, 0x0, 0x65, 0x20000, 0x7E5 }, + [ATHOS_LUT_CHAN_606500_IDX] = { 24260, 0x0, 0x65, 0x2AAAB, 0x7E6 }, + [ATHOS_LUT_CHAN_606625_IDX] = { 24265, 0x0, 0x65, 0x35555, 0x7E6 }, + [ATHOS_LUT_CHAN_606750_IDX] = { 24270, 0x0, 0x65, 0x40000, 0x7E7 }, + [ATHOS_LUT_CHAN_606875_IDX] = { 24275, 0x0, 0x65, 0x4AAAB, 0x7E7 }, + [ATHOS_LUT_CHAN_607000_IDX] = { 24280, 0x0, 0x65, 0x55555, 0x7E7 }, + [ATHOS_LUT_CHAN_607125_IDX] = { 24285, 0x0, 0x65, 0x60000, 0x7E8 }, + [ATHOS_LUT_CHAN_607250_IDX] = { 24290, 0x0, 0x65, 0x6AAAB, 0x7E8 }, + [ATHOS_LUT_CHAN_607375_IDX] = { 24295, 0x0, 0x65, 0x75555, 0x7E9 }, + [ATHOS_LUT_CHAN_607500_IDX] = { 24300, 0x0, 0x65, 0x80000, 0x7E9 }, + [ATHOS_LUT_CHAN_607625_IDX] = { 24305, 0x0, 0x65, 0x8AAAB, 0x7E9 }, + [ATHOS_LUT_CHAN_607750_IDX] = { 24310, 0x0, 0x65, 0x95555, 0x7EA }, + [ATHOS_LUT_CHAN_607875_IDX] = { 24315, 0x0, 0x65, 0xA0000, 0x7EA }, + [ATHOS_LUT_CHAN_608000_IDX] = { 24320, 0x0, 0x65, 0xAAAAB, 0x7EB }, + [ATHOS_LUT_CHAN_608125_IDX] = { 24325, 0x0, 0x65, 0xB5555, 0x7EB }, + [ATHOS_LUT_CHAN_608250_IDX] = { 24330, 0x0, 0x65, 0xC0000, 0x7EC }, + [ATHOS_LUT_CHAN_608375_IDX] = { 24335, 0x0, 0x65, 0xCAAAB, 0x7EC }, + [ATHOS_LUT_CHAN_608500_IDX] = { 24340, 0x0, 0x65, 0xD5555, 0x7EC }, + [ATHOS_LUT_CHAN_608625_IDX] = { 24345, 0x0, 0x65, 0xE0000, 0x7ED }, + [ATHOS_LUT_CHAN_608750_IDX] = { 24350, 0x0, 0x65, 0xEAAAB, 0x7ED }, + [ATHOS_LUT_CHAN_608875_IDX] = { 24355, 0x0, 0x65, 0xF5555, 0x7EE }, + [ATHOS_LUT_CHAN_609000_IDX] = { 24360, 0x0, 0x65, 0x100000, 0x7EE }, + [ATHOS_LUT_CHAN_609125_IDX] = { 24365, 0x0, 0x65, 0x10AAAB, 0x7EE }, + [ATHOS_LUT_CHAN_609250_IDX] = { 24370, 0x0, 0x65, 0x115555, 0x7EF }, + [ATHOS_LUT_CHAN_609375_IDX] = { 24375, 0x0, 0x65, 0x120000, 0x7EF }, + [ATHOS_LUT_CHAN_609500_IDX] = { 24380, 0x0, 0x65, 0x12AAAB, 0x7F0 }, + [ATHOS_LUT_CHAN_609625_IDX] = { 24385, 0x0, 0x65, 0x135555, 0x7F0 }, + [ATHOS_LUT_CHAN_609750_IDX] = { 24390, 0x0, 0x65, 0x140000, 0x7F1 }, + [ATHOS_LUT_CHAN_609875_IDX] = { 24395, 0x0, 0x65, 0x14AAAB, 0x7F1 }, + [ATHOS_LUT_CHAN_610000_IDX] = { 24400, 0x1, 0x65, 0x155555, 0x7F1 }, + [ATHOS_LUT_CHAN_610125_IDX] = { 24405, 0x1, 0x65, 0x160000, 0x7F2 }, + [ATHOS_LUT_CHAN_610250_IDX] = { 24410, 0x1, 0x65, 0x16AAAB, 0x7F2 }, + [ATHOS_LUT_CHAN_610375_IDX] = { 24415, 0x1, 0x65, 0x175555, 0x7F3 }, + [ATHOS_LUT_CHAN_610500_IDX] = { 24420, 0x1, 0x65, 0x180000, 0x7F3 }, + [ATHOS_LUT_CHAN_610625_IDX] = { 24425, 0x1, 0x65, 0x18AAAB, 0x7F3 }, + [ATHOS_LUT_CHAN_610750_IDX] = { 24430, 0x1, 0x65, 0x195555, 0x7F4 }, + [ATHOS_LUT_CHAN_610875_IDX] = { 24435, 0x1, 0x65, 0x1A0000, 0x7F4 }, + [ATHOS_LUT_CHAN_611000_IDX] = { 24440, 0x1, 0x65, 0x1AAAAB, 0x7F5 }, + [ATHOS_LUT_CHAN_611125_IDX] = { 24445, 0x1, 0x65, 0x1B5555, 0x7F5 }, + [ATHOS_LUT_CHAN_611250_IDX] = { 24450, 0x1, 0x65, 0x1C0000, 0x7F6 }, + [ATHOS_LUT_CHAN_611375_IDX] = { 24455, 0x1, 0x65, 0x1CAAAB, 0x7F6 }, + [ATHOS_LUT_CHAN_611500_IDX] = { 24460, 0x1, 0x65, 0x1D5555, 0x7F6 }, + [ATHOS_LUT_CHAN_611625_IDX] = { 24465, 0x1, 0x65, 0x1E0000, 0x7F7 }, + [ATHOS_LUT_CHAN_611750_IDX] = { 24470, 0x1, 0x65, 0x1EAAAB, 0x7F7 }, + [ATHOS_LUT_CHAN_611875_IDX] = { 24475, 0x1, 0x65, 0x1F5555, 0x7F8 }, + [ATHOS_LUT_CHAN_612000_IDX] = { 24480, 0x1, 0x66, 0x0, 0x7F8 }, + [ATHOS_LUT_CHAN_612125_IDX] = { 24485, 0x1, 0x66, 0xAAAB, 0x7F8 }, + [ATHOS_LUT_CHAN_612250_IDX] = { 24490, 0x1, 0x66, 0x15555, 0x7F9 }, + [ATHOS_LUT_CHAN_612375_IDX] = { 24495, 0x1, 0x66, 0x20000, 0x7F9 }, + [ATHOS_LUT_CHAN_612500_IDX] = { 24500, 0x1, 0x66, 0x2AAAB, 0x7FA }, + [ATHOS_LUT_CHAN_612625_IDX] = { 24505, 0x1, 0x66, 0x35555, 0x7FA }, + [ATHOS_LUT_CHAN_612750_IDX] = { 24510, 0x1, 0x66, 0x40000, 0x7FB }, + [ATHOS_LUT_CHAN_612875_IDX] = { 24515, 0x1, 0x66, 0x4AAAB, 0x7FB }, + [ATHOS_LUT_CHAN_613000_IDX] = { 24520, 0x1, 0x66, 0x55555, 0x7FB }, + [ATHOS_LUT_CHAN_613125_IDX] = { 24525, 0x1, 0x66, 0x60000, 0x7FC }, + [ATHOS_LUT_CHAN_613250_IDX] = { 24530, 0x1, 0x66, 0x6AAAB, 0x7FC }, + [ATHOS_LUT_CHAN_613375_IDX] = { 24535, 0x1, 0x66, 0x75555, 0x7FD }, + [ATHOS_LUT_CHAN_613500_IDX] = { 24540, 0x1, 0x66, 0x80000, 0x7FD }, + [ATHOS_LUT_CHAN_613625_IDX] = { 24545, 0x1, 0x66, 0x8AAAB, 0x7FD }, + [ATHOS_LUT_CHAN_613750_IDX] = { 24550, 0x1, 0x66, 0x95555, 0x7FE }, + [ATHOS_LUT_CHAN_613875_IDX] = { 24555, 0x1, 0x66, 0xA0000, 0x7FE }, + [ATHOS_LUT_CHAN_614000_IDX] = { 24560, 0x1, 0x66, 0xAAAAB, 0x7FF }, + [ATHOS_LUT_CHAN_614125_IDX] = { 24565, 0x1, 0x66, 0xB5555, 0x7FF }, + [ATHOS_LUT_CHAN_614250_IDX] = { 24570, 0x1, 0x66, 0xC0000, 0x800 }, + [ATHOS_LUT_CHAN_614375_IDX] = { 24575, 0x1, 0x66, 0xCAAAB, 0x800 }, + [ATHOS_LUT_CHAN_614500_IDX] = { 24580, 0x1, 0x66, 0xD5555, 0x800 }, + [ATHOS_LUT_CHAN_614625_IDX] = { 24585, 0x1, 0x66, 0xE0000, 0x801 }, + [ATHOS_LUT_CHAN_614750_IDX] = { 24590, 0x1, 0x66, 0xEAAAB, 0x801 }, + [ATHOS_LUT_CHAN_614875_IDX] = { 24595, 0x1, 0x66, 0xF5555, 0x802 }, + [ATHOS_LUT_CHAN_615000_IDX] = { 24600, 0x1, 0x66, 0x100000, 0x802 }, + [ATHOS_LUT_CHAN_615125_IDX] = { 24605, 0x1, 0x66, 0x10AAAB, 0x802 }, + [ATHOS_LUT_CHAN_615250_IDX] = { 24610, 0x1, 0x66, 0x115555, 0x803 }, + [ATHOS_LUT_CHAN_615375_IDX] = { 24615, 0x1, 0x66, 0x120000, 0x803 }, + [ATHOS_LUT_CHAN_615500_IDX] = { 24620, 0x1, 0x66, 0x12AAAB, 0x804 }, + [ATHOS_LUT_CHAN_615625_IDX] = { 24625, 0x1, 0x66, 0x135555, 0x804 }, + [ATHOS_LUT_CHAN_615750_IDX] = { 24630, 0x1, 0x66, 0x140000, 0x805 }, + [ATHOS_LUT_CHAN_615875_IDX] = { 24635, 0x1, 0x66, 0x14AAAB, 0x805 }, + [ATHOS_LUT_CHAN_616000_IDX] = { 24640, 0x1, 0x66, 0x155555, 0x805 }, + [ATHOS_LUT_CHAN_616125_IDX] = { 24645, 0x1, 0x66, 0x160000, 0x806 }, + [ATHOS_LUT_CHAN_616250_IDX] = { 24650, 0x1, 0x66, 0x16AAAB, 0x806 }, + [ATHOS_LUT_CHAN_616375_IDX] = { 24655, 0x1, 0x66, 0x175555, 0x807 }, + [ATHOS_LUT_CHAN_616500_IDX] = { 24660, 0x1, 0x66, 0x180000, 0x807 }, + [ATHOS_LUT_CHAN_616625_IDX] = { 24665, 0x1, 0x66, 0x18AAAB, 0x807 }, + [ATHOS_LUT_CHAN_616750_IDX] = { 24670, 0x1, 0x66, 0x195555, 0x808 }, + [ATHOS_LUT_CHAN_616875_IDX] = { 24675, 0x1, 0x66, 0x1A0000, 0x808 }, + [ATHOS_LUT_CHAN_617000_IDX] = { 24680, 0x1, 0x66, 0x1AAAAB, 0x809 }, + [ATHOS_LUT_CHAN_617125_IDX] = { 24685, 0x1, 0x66, 0x1B5555, 0x809 }, + [ATHOS_LUT_CHAN_617250_IDX] = { 24690, 0x1, 0x66, 0x1C0000, 0x80A }, + [ATHOS_LUT_CHAN_617375_IDX] = { 24695, 0x1, 0x66, 0x1CAAAB, 0x80A }, + [ATHOS_LUT_CHAN_617500_IDX] = { 24700, 0x1, 0x66, 0x1D5555, 0x80A }, + [ATHOS_LUT_CHAN_617625_IDX] = { 24705, 0x1, 0x66, 0x1E0000, 0x80B }, + [ATHOS_LUT_CHAN_617750_IDX] = { 24710, 0x1, 0x66, 0x1EAAAB, 0x80B }, + [ATHOS_LUT_CHAN_617875_IDX] = { 24715, 0x1, 0x66, 0x1F5555, 0x80C }, + [ATHOS_LUT_CHAN_618000_IDX] = { 24720, 0x1, 0x67, 0x0, 0x80C }, + [ATHOS_LUT_CHAN_618125_IDX] = { 24725, 0x1, 0x67, 0xAAAB, 0x80C }, + [ATHOS_LUT_CHAN_618250_IDX] = { 24730, 0x1, 0x67, 0x15555, 0x80D }, + [ATHOS_LUT_CHAN_618375_IDX] = { 24735, 0x1, 0x67, 0x20000, 0x80D }, + [ATHOS_LUT_CHAN_618500_IDX] = { 24740, 0x1, 0x67, 0x2AAAB, 0x80E }, + [ATHOS_LUT_CHAN_618625_IDX] = { 24745, 0x1, 0x67, 0x35555, 0x80E }, + [ATHOS_LUT_CHAN_618750_IDX] = { 24750, 0x1, 0x67, 0x40000, 0x80F }, + [ATHOS_LUT_CHAN_618875_IDX] = { 24755, 0x1, 0x67, 0x4AAAB, 0x80F }, + [ATHOS_LUT_CHAN_619000_IDX] = { 24760, 0x1, 0x67, 0x55555, 0x80F }, + [ATHOS_LUT_CHAN_619125_IDX] = { 24765, 0x1, 0x67, 0x60000, 0x810 }, + [ATHOS_LUT_CHAN_619250_IDX] = { 24770, 0x1, 0x67, 0x6AAAB, 0x810 }, + [ATHOS_LUT_CHAN_619375_IDX] = { 24775, 0x1, 0x67, 0x75555, 0x811 }, + [ATHOS_LUT_CHAN_619500_IDX] = { 24780, 0x1, 0x67, 0x80000, 0x811 }, + [ATHOS_LUT_CHAN_619625_IDX] = { 24785, 0x1, 0x67, 0x8AAAB, 0x811 }, + [ATHOS_LUT_CHAN_619750_IDX] = { 24790, 0x1, 0x67, 0x95555, 0x812 }, + [ATHOS_LUT_CHAN_619875_IDX] = { 24795, 0x1, 0x67, 0xA0000, 0x812 }, + [ATHOS_LUT_CHAN_620000_IDX] = { 24800, 0x1, 0x67, 0xAAAAB, 0x813 }, + [ATHOS_LUT_CHAN_620125_IDX] = { 24805, 0x1, 0x67, 0xB5555, 0x813 }, + [ATHOS_LUT_CHAN_620250_IDX] = { 24810, 0x1, 0x67, 0xC0000, 0x814 }, + [ATHOS_LUT_CHAN_620375_IDX] = { 24815, 0x1, 0x67, 0xCAAAB, 0x814 }, + [ATHOS_LUT_CHAN_620500_IDX] = { 24820, 0x1, 0x67, 0xD5555, 0x814 }, + [ATHOS_LUT_CHAN_620625_IDX] = { 24825, 0x1, 0x67, 0xE0000, 0x815 }, + [ATHOS_LUT_CHAN_620750_IDX] = { 24830, 0x1, 0x67, 0xEAAAB, 0x815 }, + [ATHOS_LUT_CHAN_620875_IDX] = { 24835, 0x1, 0x67, 0xF5555, 0x816 }, + [ATHOS_LUT_CHAN_621000_IDX] = { 24840, 0x1, 0x67, 0x100000, 0x816 }, + [ATHOS_LUT_CHAN_621125_IDX] = { 24845, 0x1, 0x67, 0x10AAAB, 0x816 }, + [ATHOS_LUT_CHAN_621250_IDX] = { 24850, 0x1, 0x67, 0x115555, 0x817 }, + [ATHOS_LUT_CHAN_621375_IDX] = { 24855, 0x1, 0x67, 0x120000, 0x817 }, + [ATHOS_LUT_CHAN_621500_IDX] = { 24860, 0x1, 0x67, 0x12AAAB, 0x818 }, + [ATHOS_LUT_CHAN_621625_IDX] = { 24865, 0x1, 0x67, 0x135555, 0x818 }, + [ATHOS_LUT_CHAN_621750_IDX] = { 24870, 0x1, 0x67, 0x140000, 0x819 }, + [ATHOS_LUT_CHAN_621875_IDX] = { 24875, 0x1, 0x67, 0x14AAAB, 0x819 }, + [ATHOS_LUT_CHAN_622000_IDX] = { 24880, 0x1, 0x67, 0x155555, 0x819 }, + [ATHOS_LUT_CHAN_622125_IDX] = { 24885, 0x1, 0x67, 0x160000, 0x81A }, + [ATHOS_LUT_CHAN_622250_IDX] = { 24890, 0x1, 0x67, 0x16AAAB, 0x81A }, + [ATHOS_LUT_CHAN_622375_IDX] = { 24895, 0x1, 0x67, 0x175555, 0x81B }, + [ATHOS_LUT_CHAN_622500_IDX] = { 24900, 0x1, 0x67, 0x180000, 0x81B }, + [ATHOS_LUT_CHAN_622625_IDX] = { 24905, 0x1, 0x67, 0x18AAAB, 0x81B }, + [ATHOS_LUT_CHAN_622750_IDX] = { 24910, 0x1, 0x67, 0x195555, 0x81C }, + [ATHOS_LUT_CHAN_622875_IDX] = { 24915, 0x1, 0x67, 0x1A0000, 0x81C }, + [ATHOS_LUT_CHAN_623000_IDX] = { 24920, 0x1, 0x67, 0x1AAAAB, 0x81D }, + [ATHOS_LUT_CHAN_623125_IDX] = { 24925, 0x1, 0x67, 0x1B5555, 0x81D }, + [ATHOS_LUT_CHAN_623250_IDX] = { 24930, 0x1, 0x67, 0x1C0000, 0x81E }, + [ATHOS_LUT_CHAN_623375_IDX] = { 24935, 0x1, 0x67, 0x1CAAAB, 0x81E }, + [ATHOS_LUT_CHAN_623500_IDX] = { 24940, 0x1, 0x67, 0x1D5555, 0x81E }, + [ATHOS_LUT_CHAN_623625_IDX] = { 24945, 0x1, 0x67, 0x1E0000, 0x81F }, + [ATHOS_LUT_CHAN_623750_IDX] = { 24950, 0x1, 0x67, 0x1EAAAB, 0x81F }, + [ATHOS_LUT_CHAN_623875_IDX] = { 24955, 0x1, 0x67, 0x1F5555, 0x820 }, + [ATHOS_LUT_CHAN_624000_IDX] = { 24960, 0x1, 0x68, 0x0, 0x820 }, + [ATHOS_LUT_CHAN_624125_IDX] = { 24965, 0x1, 0x68, 0xAAAB, 0x820 }, + [ATHOS_LUT_CHAN_624250_IDX] = { 24970, 0x1, 0x68, 0x15555, 0x821 }, + [ATHOS_LUT_CHAN_624375_IDX] = { 24975, 0x1, 0x68, 0x20000, 0x821 }, + [ATHOS_LUT_CHAN_624500_IDX] = { 24980, 0x1, 0x68, 0x2AAAB, 0x822 }, + [ATHOS_LUT_CHAN_624625_IDX] = { 24985, 0x1, 0x68, 0x35555, 0x822 }, + [ATHOS_LUT_CHAN_624750_IDX] = { 24990, 0x1, 0x68, 0x40000, 0x823 }, + [ATHOS_LUT_CHAN_624875_IDX] = { 24995, 0x1, 0x68, 0x4AAAB, 0x823 }, + [ATHOS_LUT_CHAN_625000_IDX] = { 25000, 0x1, 0x68, 0x55555, 0x823 }, + [ATHOS_LUT_CHAN_625125_IDX] = { 25005, 0x1, 0x68, 0x60000, 0x824 }, + [ATHOS_LUT_CHAN_625250_IDX] = { 25010, 0x1, 0x68, 0x6AAAB, 0x824 }, + [ATHOS_LUT_CHAN_625375_IDX] = { 25015, 0x1, 0x68, 0x75555, 0x825 }, + [ATHOS_LUT_CHAN_625500_IDX] = { 25020, 0x1, 0x68, 0x80000, 0x825 }, + [ATHOS_LUT_CHAN_625625_IDX] = { 25025, 0x1, 0x68, 0x8AAAB, 0x825 }, + [ATHOS_LUT_CHAN_625750_IDX] = { 25030, 0x1, 0x68, 0x95555, 0x826 }, + [ATHOS_LUT_CHAN_625875_IDX] = { 25035, 0x1, 0x68, 0xA0000, 0x826 }, + [ATHOS_LUT_CHAN_626000_IDX] = { 25040, 0x1, 0x68, 0xAAAAB, 0x827 }, + [ATHOS_LUT_CHAN_626125_IDX] = { 25045, 0x1, 0x68, 0xB5555, 0x827 }, + [ATHOS_LUT_CHAN_626250_IDX] = { 25050, 0x1, 0x68, 0xC0000, 0x828 }, + [ATHOS_LUT_CHAN_626375_IDX] = { 25055, 0x1, 0x68, 0xCAAAB, 0x828 }, + [ATHOS_LUT_CHAN_626500_IDX] = { 25060, 0x1, 0x68, 0xD5555, 0x828 }, + [ATHOS_LUT_CHAN_626625_IDX] = { 25065, 0x1, 0x68, 0xE0000, 0x829 }, + [ATHOS_LUT_CHAN_626750_IDX] = { 25070, 0x1, 0x68, 0xEAAAB, 0x829 }, + [ATHOS_LUT_CHAN_626875_IDX] = { 25075, 0x1, 0x68, 0xF5555, 0x82A }, + [ATHOS_LUT_CHAN_627000_IDX] = { 25080, 0x1, 0x68, 0x100000, 0x82A }, + [ATHOS_LUT_CHAN_627125_IDX] = { 25085, 0x1, 0x68, 0x10AAAB, 0x82A }, + [ATHOS_LUT_CHAN_627250_IDX] = { 25090, 0x1, 0x68, 0x115555, 0x82B }, + [ATHOS_LUT_CHAN_627375_IDX] = { 25095, 0x1, 0x68, 0x120000, 0x82B }, + [ATHOS_LUT_CHAN_627500_IDX] = { 25100, 0x1, 0x68, 0x12AAAB, 0x82C }, + [ATHOS_LUT_CHAN_627625_IDX] = { 25105, 0x1, 0x68, 0x135555, 0x82C }, + [ATHOS_LUT_CHAN_627750_IDX] = { 25110, 0x1, 0x68, 0x140000, 0x82D }, + [ATHOS_LUT_CHAN_627875_IDX] = { 25115, 0x1, 0x68, 0x14AAAB, 0x82D }, + [ATHOS_LUT_CHAN_628000_IDX] = { 25120, 0x1, 0x68, 0x155555, 0x82D }, + [ATHOS_LUT_CHAN_628125_IDX] = { 25125, 0x1, 0x68, 0x160000, 0x82E }, + [ATHOS_LUT_CHAN_628250_IDX] = { 25130, 0x1, 0x68, 0x16AAAB, 0x82E }, + [ATHOS_LUT_CHAN_628375_IDX] = { 25135, 0x1, 0x68, 0x175555, 0x82F }, + [ATHOS_LUT_CHAN_628500_IDX] = { 25140, 0x1, 0x68, 0x180000, 0x82F }, + [ATHOS_LUT_CHAN_628625_IDX] = { 25145, 0x1, 0x68, 0x18AAAB, 0x82F }, + [ATHOS_LUT_CHAN_628750_IDX] = { 25150, 0x1, 0x68, 0x195555, 0x830 }, + [ATHOS_LUT_CHAN_628875_IDX] = { 25155, 0x1, 0x68, 0x1A0000, 0x830 }, + [ATHOS_LUT_CHAN_629000_IDX] = { 25160, 0x1, 0x68, 0x1AAAAB, 0x831 }, + [ATHOS_LUT_CHAN_629125_IDX] = { 25165, 0x1, 0x68, 0x1B5555, 0x831 }, + [ATHOS_LUT_CHAN_629250_IDX] = { 25170, 0x1, 0x68, 0x1C0000, 0x832 }, + [ATHOS_LUT_CHAN_629375_IDX] = { 25175, 0x1, 0x68, 0x1CAAAB, 0x832 }, + [ATHOS_LUT_CHAN_629500_IDX] = { 25180, 0x1, 0x68, 0x1D5555, 0x832 }, + [ATHOS_LUT_CHAN_629625_IDX] = { 25185, 0x1, 0x68, 0x1E0000, 0x833 }, + [ATHOS_LUT_CHAN_629750_IDX] = { 25190, 0x1, 0x68, 0x1EAAAB, 0x833 }, + [ATHOS_LUT_CHAN_629875_IDX] = { 25195, 0x1, 0x68, 0x1F5555, 0x834 }, + [ATHOS_LUT_CHAN_630000_IDX] = { 25200, 0x1, 0x69, 0x0, 0x834 }, + [ATHOS_LUT_CHAN_630125_IDX] = { 25205, 0x1, 0x69, 0xAAAB, 0x834 }, + [ATHOS_LUT_CHAN_630250_IDX] = { 25210, 0x1, 0x69, 0x15555, 0x835 }, + [ATHOS_LUT_CHAN_630375_IDX] = { 25215, 0x1, 0x69, 0x20000, 0x835 }, + [ATHOS_LUT_CHAN_630500_IDX] = { 25220, 0x1, 0x69, 0x2AAAB, 0x836 }, + [ATHOS_LUT_CHAN_630625_IDX] = { 25225, 0x1, 0x69, 0x35555, 0x836 }, + [ATHOS_LUT_CHAN_630750_IDX] = { 25230, 0x1, 0x69, 0x40000, 0x837 }, + [ATHOS_LUT_CHAN_630875_IDX] = { 25235, 0x1, 0x69, 0x4AAAB, 0x837 }, + [ATHOS_LUT_CHAN_631000_IDX] = { 25240, 0x1, 0x69, 0x55555, 0x837 }, + [ATHOS_LUT_CHAN_631125_IDX] = { 25245, 0x1, 0x69, 0x60000, 0x838 }, + [ATHOS_LUT_CHAN_631250_IDX] = { 25250, 0x1, 0x69, 0x6AAAB, 0x838 }, + [ATHOS_LUT_CHAN_631375_IDX] = { 25255, 0x1, 0x69, 0x75555, 0x839 }, + [ATHOS_LUT_CHAN_631500_IDX] = { 25260, 0x1, 0x69, 0x80000, 0x839 }, + [ATHOS_LUT_CHAN_631625_IDX] = { 25265, 0x1, 0x69, 0x8AAAB, 0x839 }, + [ATHOS_LUT_CHAN_631750_IDX] = { 25270, 0x1, 0x69, 0x95555, 0x83A }, + [ATHOS_LUT_CHAN_631875_IDX] = { 25275, 0x1, 0x69, 0xA0000, 0x83A }, + [ATHOS_LUT_CHAN_632000_IDX] = { 25280, 0x1, 0x69, 0xAAAAB, 0x83B }, + [ATHOS_LUT_CHAN_632125_IDX] = { 25285, 0x1, 0x69, 0xB5555, 0x83B }, + [ATHOS_LUT_CHAN_632250_IDX] = { 25290, 0x1, 0x69, 0xC0000, 0x83C }, + [ATHOS_LUT_CHAN_632375_IDX] = { 25295, 0x1, 0x69, 0xCAAAB, 0x83C }, + [ATHOS_LUT_CHAN_632500_IDX] = { 25300, 0x1, 0x69, 0xD5555, 0x83C }, + [ATHOS_LUT_CHAN_632625_IDX] = { 25305, 0x1, 0x69, 0xE0000, 0x83D }, + [ATHOS_LUT_CHAN_632750_IDX] = { 25310, 0x1, 0x69, 0xEAAAB, 0x83D }, + [ATHOS_LUT_CHAN_632875_IDX] = { 25315, 0x1, 0x69, 0xF5555, 0x83E }, + [ATHOS_LUT_CHAN_633000_IDX] = { 25320, 0x1, 0x69, 0x100000, 0x83E }, + [ATHOS_LUT_CHAN_633125_IDX] = { 25325, 0x1, 0x69, 0x10AAAB, 0x83E }, + [ATHOS_LUT_CHAN_633250_IDX] = { 25330, 0x1, 0x69, 0x115555, 0x83F }, + [ATHOS_LUT_CHAN_633375_IDX] = { 25335, 0x1, 0x69, 0x120000, 0x83F }, + [ATHOS_LUT_CHAN_633500_IDX] = { 25340, 0x1, 0x69, 0x12AAAB, 0x840 }, + [ATHOS_LUT_CHAN_633625_IDX] = { 25345, 0x1, 0x69, 0x135555, 0x840 }, + [ATHOS_LUT_CHAN_633750_IDX] = { 25350, 0x1, 0x69, 0x140000, 0x841 }, + [ATHOS_LUT_CHAN_633875_IDX] = { 25355, 0x1, 0x69, 0x14AAAB, 0x841 }, + [ATHOS_LUT_CHAN_634000_IDX] = { 25360, 0x1, 0x69, 0x155555, 0x841 }, + [ATHOS_LUT_CHAN_634125_IDX] = { 25365, 0x1, 0x69, 0x160000, 0x842 }, + [ATHOS_LUT_CHAN_634250_IDX] = { 25370, 0x1, 0x69, 0x16AAAB, 0x842 }, + [ATHOS_LUT_CHAN_634375_IDX] = { 25375, 0x1, 0x69, 0x175555, 0x843 }, + [ATHOS_LUT_CHAN_634500_IDX] = { 25380, 0x1, 0x69, 0x180000, 0x843 }, + [ATHOS_LUT_CHAN_634625_IDX] = { 25385, 0x1, 0x69, 0x18AAAB, 0x843 }, + [ATHOS_LUT_CHAN_634750_IDX] = { 25390, 0x1, 0x69, 0x195555, 0x844 }, + [ATHOS_LUT_CHAN_634875_IDX] = { 25395, 0x1, 0x69, 0x1A0000, 0x844 }, + [ATHOS_LUT_CHAN_635000_IDX] = { 25400, 0x1, 0x69, 0x1AAAAB, 0x845 }, + [ATHOS_LUT_CHAN_635125_IDX] = { 25405, 0x1, 0x69, 0x1B5555, 0x845 }, + [ATHOS_LUT_CHAN_635250_IDX] = { 25410, 0x1, 0x69, 0x1C0000, 0x846 }, + [ATHOS_LUT_CHAN_635375_IDX] = { 25415, 0x1, 0x69, 0x1CAAAB, 0x846 }, + [ATHOS_LUT_CHAN_635500_IDX] = { 25420, 0x1, 0x69, 0x1D5555, 0x846 }, + [ATHOS_LUT_CHAN_635625_IDX] = { 25425, 0x1, 0x69, 0x1E0000, 0x847 }, + [ATHOS_LUT_CHAN_635750_IDX] = { 25430, 0x1, 0x69, 0x1EAAAB, 0x847 }, + [ATHOS_LUT_CHAN_635875_IDX] = { 25435, 0x1, 0x69, 0x1F5555, 0x848 }, + [ATHOS_LUT_CHAN_636000_IDX] = { 25440, 0x1, 0x6A, 0x0, 0x848 }, + [ATHOS_LUT_CHAN_636125_IDX] = { 25445, 0x1, 0x6A, 0xAAAB, 0x848 }, + [ATHOS_LUT_CHAN_636250_IDX] = { 25450, 0x1, 0x6A, 0x15555, 0x849 }, + [ATHOS_LUT_CHAN_636375_IDX] = { 25455, 0x1, 0x6A, 0x20000, 0x849 }, + [ATHOS_LUT_CHAN_636500_IDX] = { 25460, 0x1, 0x6A, 0x2AAAB, 0x84A }, + [ATHOS_LUT_CHAN_636625_IDX] = { 25465, 0x1, 0x6A, 0x35555, 0x84A }, + [ATHOS_LUT_CHAN_636750_IDX] = { 25470, 0x1, 0x6A, 0x40000, 0x84B }, + [ATHOS_LUT_CHAN_636875_IDX] = { 25475, 0x1, 0x6A, 0x4AAAB, 0x84B }, + [ATHOS_LUT_CHAN_637000_IDX] = { 25480, 0x1, 0x6A, 0x55555, 0x84B }, + [ATHOS_LUT_CHAN_637125_IDX] = { 25485, 0x1, 0x6A, 0x60000, 0x84C }, + [ATHOS_LUT_CHAN_637250_IDX] = { 25490, 0x1, 0x6A, 0x6AAAB, 0x84C }, + [ATHOS_LUT_CHAN_637375_IDX] = { 25495, 0x1, 0x6A, 0x75555, 0x84D }, + [ATHOS_LUT_CHAN_637500_IDX] = { 25500, 0x1, 0x6A, 0x80000, 0x84D }, + [ATHOS_LUT_CHAN_637625_IDX] = { 25505, 0x1, 0x6A, 0x8AAAB, 0x84D }, + [ATHOS_LUT_CHAN_637750_IDX] = { 25510, 0x1, 0x6A, 0x95555, 0x84E }, + [ATHOS_LUT_CHAN_637875_IDX] = { 25515, 0x1, 0x6A, 0xA0000, 0x84E }, + [ATHOS_LUT_CHAN_638000_IDX] = { 25520, 0x1, 0x6A, 0xAAAAB, 0x84F }, + [ATHOS_LUT_CHAN_638125_IDX] = { 25525, 0x1, 0x6A, 0xB5555, 0x84F }, + [ATHOS_LUT_CHAN_638250_IDX] = { 25530, 0x1, 0x6A, 0xC0000, 0x850 }, + [ATHOS_LUT_CHAN_638375_IDX] = { 25535, 0x1, 0x6A, 0xCAAAB, 0x850 }, + [ATHOS_LUT_CHAN_638500_IDX] = { 25540, 0x1, 0x6A, 0xD5555, 0x850 }, + [ATHOS_LUT_CHAN_638625_IDX] = { 25545, 0x1, 0x6A, 0xE0000, 0x851 }, + [ATHOS_LUT_CHAN_638750_IDX] = { 25550, 0x1, 0x6A, 0xEAAAB, 0x851 }, + [ATHOS_LUT_CHAN_638875_IDX] = { 25555, 0x1, 0x6A, 0xF5555, 0x852 }, + [ATHOS_LUT_CHAN_639000_IDX] = { 25560, 0x1, 0x6A, 0x100000, 0x852 }, + [ATHOS_LUT_CHAN_639125_IDX] = { 25565, 0x1, 0x6A, 0x10AAAB, 0x852 }, + [ATHOS_LUT_CHAN_639250_IDX] = { 25570, 0x1, 0x6A, 0x115555, 0x853 }, + [ATHOS_LUT_CHAN_639375_IDX] = { 25575, 0x1, 0x6A, 0x120000, 0x853 }, + [ATHOS_LUT_CHAN_639500_IDX] = { 25580, 0x1, 0x6A, 0x12AAAB, 0x854 }, + [ATHOS_LUT_CHAN_639625_IDX] = { 25585, 0x1, 0x6A, 0x135555, 0x854 }, + [ATHOS_LUT_CHAN_639750_IDX] = { 25590, 0x1, 0x6A, 0x140000, 0x855 }, + [ATHOS_LUT_CHAN_639875_IDX] = { 25595, 0x1, 0x6A, 0x14AAAB, 0x855 }, + [ATHOS_LUT_CHAN_640000_IDX] = { 25600, 0x1, 0x6A, 0x155555, 0x855 }, + [ATHOS_LUT_CHAN_640125_IDX] = { 25605, 0x1, 0x6A, 0x160000, 0x856 }, + [ATHOS_LUT_CHAN_640250_IDX] = { 25610, 0x1, 0x6A, 0x16AAAB, 0x856 }, + [ATHOS_LUT_CHAN_640375_IDX] = { 25615, 0x1, 0x6A, 0x175555, 0x857 }, + [ATHOS_LUT_CHAN_640500_IDX] = { 25620, 0x1, 0x6A, 0x180000, 0x857 }, + [ATHOS_LUT_CHAN_640625_IDX] = { 25625, 0x1, 0x6A, 0x18AAAB, 0x857 }, + [ATHOS_LUT_CHAN_640750_IDX] = { 25630, 0x1, 0x6A, 0x195555, 0x858 }, + [ATHOS_LUT_CHAN_640875_IDX] = { 25635, 0x1, 0x6A, 0x1A0000, 0x858 }, + [ATHOS_LUT_CHAN_641000_IDX] = { 25640, 0x1, 0x6A, 0x1AAAAB, 0x859 }, + [ATHOS_LUT_CHAN_641125_IDX] = { 25645, 0x1, 0x6A, 0x1B5555, 0x859 }, + [ATHOS_LUT_CHAN_641250_IDX] = { 25650, 0x1, 0x6A, 0x1C0000, 0x85A }, + [ATHOS_LUT_CHAN_641375_IDX] = { 25655, 0x1, 0x6A, 0x1CAAAB, 0x85A }, + [ATHOS_LUT_CHAN_641500_IDX] = { 25660, 0x1, 0x6A, 0x1D5555, 0x85A }, + [ATHOS_LUT_CHAN_641625_IDX] = { 25665, 0x1, 0x6A, 0x1E0000, 0x85B }, + [ATHOS_LUT_CHAN_641750_IDX] = { 25670, 0x1, 0x6A, 0x1EAAAB, 0x85B }, + [ATHOS_LUT_CHAN_641875_IDX] = { 25675, 0x1, 0x6A, 0x1F5555, 0x85C }, + [ATHOS_LUT_CHAN_642000_IDX] = { 25680, 0x1, 0x6B, 0x0, 0x85C }, + [ATHOS_LUT_CHAN_642125_IDX] = { 25685, 0x1, 0x6B, 0xAAAB, 0x85C }, + [ATHOS_LUT_CHAN_642250_IDX] = { 25690, 0x1, 0x6B, 0x15555, 0x85D }, + [ATHOS_LUT_CHAN_642375_IDX] = { 25695, 0x1, 0x6B, 0x20000, 0x85D }, + [ATHOS_LUT_CHAN_642500_IDX] = { 25700, 0x1, 0x6B, 0x2AAAB, 0x85E }, + [ATHOS_LUT_CHAN_642625_IDX] = { 25705, 0x1, 0x6B, 0x35555, 0x85E }, + [ATHOS_LUT_CHAN_642750_IDX] = { 25710, 0x1, 0x6B, 0x40000, 0x85F }, + [ATHOS_LUT_CHAN_642875_IDX] = { 25715, 0x1, 0x6B, 0x4AAAB, 0x85F }, + [ATHOS_LUT_CHAN_643000_IDX] = { 25720, 0x1, 0x6B, 0x55555, 0x85F }, + [ATHOS_LUT_CHAN_643125_IDX] = { 25725, 0x1, 0x6B, 0x60000, 0x860 }, + [ATHOS_LUT_CHAN_643250_IDX] = { 25730, 0x1, 0x6B, 0x6AAAB, 0x860 }, + [ATHOS_LUT_CHAN_643375_IDX] = { 25735, 0x1, 0x6B, 0x75555, 0x861 }, + [ATHOS_LUT_CHAN_643500_IDX] = { 25740, 0x1, 0x6B, 0x80000, 0x861 }, + [ATHOS_LUT_CHAN_643625_IDX] = { 25745, 0x1, 0x6B, 0x8AAAB, 0x861 }, + [ATHOS_LUT_CHAN_643750_IDX] = { 25750, 0x1, 0x6B, 0x95555, 0x862 }, + [ATHOS_LUT_CHAN_643875_IDX] = { 25755, 0x1, 0x6B, 0xA0000, 0x862 }, + [ATHOS_LUT_CHAN_644000_IDX] = { 25760, 0x1, 0x6B, 0xAAAAB, 0x863 }, + [ATHOS_LUT_CHAN_644125_IDX] = { 25765, 0x1, 0x6B, 0xB5555, 0x863 }, + [ATHOS_LUT_CHAN_644250_IDX] = { 25770, 0x1, 0x6B, 0xC0000, 0x864 }, + [ATHOS_LUT_CHAN_644375_IDX] = { 25775, 0x1, 0x6B, 0xCAAAB, 0x864 }, + [ATHOS_LUT_CHAN_644500_IDX] = { 25780, 0x1, 0x6B, 0xD5555, 0x864 }, + [ATHOS_LUT_CHAN_644625_IDX] = { 25785, 0x1, 0x6B, 0xE0000, 0x865 }, + [ATHOS_LUT_CHAN_644750_IDX] = { 25790, 0x1, 0x6B, 0xEAAAB, 0x865 }, + [ATHOS_LUT_CHAN_644875_IDX] = { 25795, 0x1, 0x6B, 0xF5555, 0x866 }, + [ATHOS_LUT_CHAN_645000_IDX] = { 25800, 0x1, 0x6B, 0x100000, 0x866 }, + [ATHOS_LUT_CHAN_645125_IDX] = { 25805, 0x1, 0x6B, 0x10AAAB, 0x866 }, + [ATHOS_LUT_CHAN_645250_IDX] = { 25810, 0x1, 0x6B, 0x115555, 0x867 }, + [ATHOS_LUT_CHAN_645375_IDX] = { 25815, 0x1, 0x6B, 0x120000, 0x867 }, + [ATHOS_LUT_CHAN_645500_IDX] = { 25820, 0x1, 0x6B, 0x12AAAB, 0x868 }, + [ATHOS_LUT_CHAN_645625_IDX] = { 25825, 0x1, 0x6B, 0x135555, 0x868 }, + [ATHOS_LUT_CHAN_645750_IDX] = { 25830, 0x1, 0x6B, 0x140000, 0x869 }, + [ATHOS_LUT_CHAN_645875_IDX] = { 25835, 0x1, 0x6B, 0x14AAAB, 0x869 }, + [ATHOS_LUT_CHAN_646000_IDX] = { 25840, 0x1, 0x6B, 0x155555, 0x869 }, + [ATHOS_LUT_CHAN_646125_IDX] = { 25845, 0x1, 0x6B, 0x160000, 0x86A }, + [ATHOS_LUT_CHAN_646250_IDX] = { 25850, 0x1, 0x6B, 0x16AAAB, 0x86A }, + [ATHOS_LUT_CHAN_646375_IDX] = { 25855, 0x1, 0x6B, 0x175555, 0x86B }, + [ATHOS_LUT_CHAN_646500_IDX] = { 25860, 0x1, 0x6B, 0x180000, 0x86B }, + [ATHOS_LUT_CHAN_646625_IDX] = { 25865, 0x1, 0x6B, 0x18AAAB, 0x86B }, + [ATHOS_LUT_CHAN_646750_IDX] = { 25870, 0x1, 0x6B, 0x195555, 0x86C }, + [ATHOS_LUT_CHAN_646875_IDX] = { 25875, 0x1, 0x6B, 0x1A0000, 0x86C }, + [ATHOS_LUT_CHAN_647000_IDX] = { 25880, 0x1, 0x6B, 0x1AAAAB, 0x86D }, + [ATHOS_LUT_CHAN_647125_IDX] = { 25885, 0x1, 0x6B, 0x1B5555, 0x86D }, + [ATHOS_LUT_CHAN_647250_IDX] = { 25890, 0x1, 0x6B, 0x1C0000, 0x86E }, + [ATHOS_LUT_CHAN_647375_IDX] = { 25895, 0x1, 0x6B, 0x1CAAAB, 0x86E }, + [ATHOS_LUT_CHAN_647500_IDX] = { 25900, 0x1, 0x6B, 0x1D5555, 0x86E }, + [ATHOS_LUT_CHAN_647625_IDX] = { 25905, 0x1, 0x6B, 0x1E0000, 0x86F }, + [ATHOS_LUT_CHAN_647750_IDX] = { 25910, 0x1, 0x6B, 0x1EAAAB, 0x86F }, + [ATHOS_LUT_CHAN_647875_IDX] = { 25915, 0x1, 0x6B, 0x1F5555, 0x870 }, + [ATHOS_LUT_CHAN_648000_IDX] = { 25920, 0x1, 0x6C, 0x0, 0x870 }, + [ATHOS_LUT_CHAN_648125_IDX] = { 25925, 0x1, 0x6C, 0xAAAB, 0x870 }, + [ATHOS_LUT_CHAN_648250_IDX] = { 25930, 0x1, 0x6C, 0x15555, 0x871 }, + [ATHOS_LUT_CHAN_648375_IDX] = { 25935, 0x1, 0x6C, 0x20000, 0x871 }, + [ATHOS_LUT_CHAN_648500_IDX] = { 25940, 0x1, 0x6C, 0x2AAAB, 0x872 }, + [ATHOS_LUT_CHAN_648625_IDX] = { 25945, 0x1, 0x6C, 0x35555, 0x872 }, + [ATHOS_LUT_CHAN_648750_IDX] = { 25950, 0x1, 0x6C, 0x40000, 0x873 }, + [ATHOS_LUT_CHAN_648875_IDX] = { 25955, 0x1, 0x6C, 0x4AAAB, 0x873 }, + [ATHOS_LUT_CHAN_649000_IDX] = { 25960, 0x1, 0x6C, 0x55555, 0x873 }, + [ATHOS_LUT_CHAN_649125_IDX] = { 25965, 0x1, 0x6C, 0x60000, 0x874 }, + [ATHOS_LUT_CHAN_649250_IDX] = { 25970, 0x1, 0x6C, 0x6AAAB, 0x874 }, + [ATHOS_LUT_CHAN_649375_IDX] = { 25975, 0x1, 0x6C, 0x75555, 0x875 }, + [ATHOS_LUT_CHAN_649500_IDX] = { 25980, 0x1, 0x6C, 0x80000, 0x875 }, + [ATHOS_LUT_CHAN_649625_IDX] = { 25985, 0x1, 0x6C, 0x8AAAB, 0x875 }, + [ATHOS_LUT_CHAN_649750_IDX] = { 25990, 0x1, 0x6C, 0x95555, 0x876 }, + [ATHOS_LUT_CHAN_649875_IDX] = { 25995, 0x1, 0x6C, 0xA0000, 0x876 }, + [ATHOS_LUT_CHAN_650000_IDX] = { 26000, 0x1, 0x6C, 0xAAAAB, 0x877 }, + [ATHOS_LUT_CHAN_650125_IDX] = { 26005, 0x1, 0x6C, 0xB5555, 0x877 }, + [ATHOS_LUT_CHAN_650250_IDX] = { 26010, 0x1, 0x6C, 0xC0000, 0x878 }, + [ATHOS_LUT_CHAN_650375_IDX] = { 26015, 0x1, 0x6C, 0xCAAAB, 0x878 }, + [ATHOS_LUT_CHAN_650500_IDX] = { 26020, 0x1, 0x6C, 0xD5555, 0x878 }, + [ATHOS_LUT_CHAN_650625_IDX] = { 26025, 0x1, 0x6C, 0xE0000, 0x879 }, + [ATHOS_LUT_CHAN_650750_IDX] = { 26030, 0x1, 0x6C, 0xEAAAB, 0x879 }, + [ATHOS_LUT_CHAN_650875_IDX] = { 26035, 0x1, 0x6C, 0xF5555, 0x87A }, + [ATHOS_LUT_CHAN_651000_IDX] = { 26040, 0x1, 0x6C, 0x100000, 0x87A }, + [ATHOS_LUT_CHAN_651125_IDX] = { 26045, 0x1, 0x6C, 0x10AAAB, 0x87A }, + [ATHOS_LUT_CHAN_651250_IDX] = { 26050, 0x1, 0x6C, 0x115555, 0x87B }, + [ATHOS_LUT_CHAN_651375_IDX] = { 26055, 0x1, 0x6C, 0x120000, 0x87B }, + [ATHOS_LUT_CHAN_651500_IDX] = { 26060, 0x1, 0x6C, 0x12AAAB, 0x87C }, + [ATHOS_LUT_CHAN_651625_IDX] = { 26065, 0x1, 0x6C, 0x135555, 0x87C }, + [ATHOS_LUT_CHAN_651750_IDX] = { 26070, 0x1, 0x6C, 0x140000, 0x87D }, + [ATHOS_LUT_CHAN_651875_IDX] = { 26075, 0x1, 0x6C, 0x14AAAB, 0x87D }, + [ATHOS_LUT_CHAN_652000_IDX] = { 26080, 0x1, 0x6C, 0x155555, 0x87D }, + [ATHOS_LUT_CHAN_652125_IDX] = { 26085, 0x1, 0x6C, 0x160000, 0x87E }, + [ATHOS_LUT_CHAN_652250_IDX] = { 26090, 0x1, 0x6C, 0x16AAAB, 0x87E }, + [ATHOS_LUT_CHAN_652375_IDX] = { 26095, 0x1, 0x6C, 0x175555, 0x87F }, + [ATHOS_LUT_CHAN_652500_IDX] = { 26100, 0x1, 0x6C, 0x180000, 0x87F }, + [ATHOS_LUT_CHAN_652625_IDX] = { 26105, 0x1, 0x6C, 0x18AAAB, 0x87F }, + [ATHOS_LUT_CHAN_652750_IDX] = { 26110, 0x1, 0x6C, 0x195555, 0x880 }, + [ATHOS_LUT_CHAN_652875_IDX] = { 26115, 0x1, 0x6C, 0x1A0000, 0x880 }, + [ATHOS_LUT_CHAN_653000_IDX] = { 26120, 0x1, 0x6C, 0x1AAAAB, 0x881 }, + [ATHOS_LUT_CHAN_653125_IDX] = { 26125, 0x1, 0x6C, 0x1B5555, 0x881 }, + [ATHOS_LUT_CHAN_653250_IDX] = { 26130, 0x1, 0x6C, 0x1C0000, 0x882 }, + [ATHOS_LUT_CHAN_653375_IDX] = { 26135, 0x1, 0x6C, 0x1CAAAB, 0x882 }, + [ATHOS_LUT_CHAN_653500_IDX] = { 26140, 0x1, 0x6C, 0x1D5555, 0x882 }, + [ATHOS_LUT_CHAN_653625_IDX] = { 26145, 0x1, 0x6C, 0x1E0000, 0x883 }, + [ATHOS_LUT_CHAN_653750_IDX] = { 26150, 0x1, 0x6C, 0x1EAAAB, 0x883 }, + [ATHOS_LUT_CHAN_653875_IDX] = { 26155, 0x1, 0x6C, 0x1F5555, 0x884 }, + [ATHOS_LUT_CHAN_654000_IDX] = { 26160, 0x1, 0x6D, 0x0, 0x884 }, + [ATHOS_LUT_CHAN_654125_IDX] = { 26165, 0x1, 0x6D, 0xAAAB, 0x884 }, + [ATHOS_LUT_CHAN_654250_IDX] = { 26170, 0x1, 0x6D, 0x15555, 0x885 }, + [ATHOS_LUT_CHAN_654375_IDX] = { 26175, 0x1, 0x6D, 0x20000, 0x885 }, + [ATHOS_LUT_CHAN_654500_IDX] = { 26180, 0x1, 0x6D, 0x2AAAB, 0x886 }, + [ATHOS_LUT_CHAN_654625_IDX] = { 26185, 0x1, 0x6D, 0x35555, 0x886 }, + [ATHOS_LUT_CHAN_654750_IDX] = { 26190, 0x1, 0x6D, 0x40000, 0x887 }, + [ATHOS_LUT_CHAN_654875_IDX] = { 26195, 0x1, 0x6D, 0x4AAAB, 0x887 }, + [ATHOS_LUT_CHAN_655000_IDX] = { 26200, 0x1, 0x6D, 0x55555, 0x887 }, + [ATHOS_LUT_CHAN_655125_IDX] = { 26205, 0x1, 0x6D, 0x60000, 0x888 }, + [ATHOS_LUT_CHAN_655250_IDX] = { 26210, 0x1, 0x6D, 0x6AAAB, 0x888 }, + [ATHOS_LUT_CHAN_655375_IDX] = { 26215, 0x1, 0x6D, 0x75555, 0x889 }, + [ATHOS_LUT_CHAN_655500_IDX] = { 26220, 0x1, 0x6D, 0x80000, 0x889 }, + [ATHOS_LUT_CHAN_655625_IDX] = { 26225, 0x1, 0x6D, 0x8AAAB, 0x889 }, + [ATHOS_LUT_CHAN_655750_IDX] = { 26230, 0x1, 0x6D, 0x95555, 0x88A }, + [ATHOS_LUT_CHAN_655875_IDX] = { 26235, 0x1, 0x6D, 0xA0000, 0x88A }, + [ATHOS_LUT_CHAN_656000_IDX] = { 26240, 0x1, 0x6D, 0xAAAAB, 0x88B }, + [ATHOS_LUT_CHAN_656125_IDX] = { 26245, 0x1, 0x6D, 0xB5555, 0x88B }, + [ATHOS_LUT_CHAN_656250_IDX] = { 26250, 0x1, 0x6D, 0xC0000, 0x88C }, + [ATHOS_LUT_CHAN_656375_IDX] = { 26255, 0x1, 0x6D, 0xCAAAB, 0x88C }, + [ATHOS_LUT_CHAN_656500_IDX] = { 26260, 0x1, 0x6D, 0xD5555, 0x88C }, + [ATHOS_LUT_CHAN_656625_IDX] = { 26265, 0x1, 0x6D, 0xE0000, 0x88D }, + [ATHOS_LUT_CHAN_656750_IDX] = { 26270, 0x1, 0x6D, 0xEAAAB, 0x88D }, + [ATHOS_LUT_CHAN_656875_IDX] = { 26275, 0x1, 0x6D, 0xF5555, 0x88E }, + [ATHOS_LUT_CHAN_657000_IDX] = { 26280, 0x1, 0x6D, 0x100000, 0x88E }, + [ATHOS_LUT_CHAN_657125_IDX] = { 26285, 0x1, 0x6D, 0x10AAAB, 0x88E }, + [ATHOS_LUT_CHAN_657250_IDX] = { 26290, 0x1, 0x6D, 0x115555, 0x88F }, + [ATHOS_LUT_CHAN_657375_IDX] = { 26295, 0x1, 0x6D, 0x120000, 0x88F }, + [ATHOS_LUT_CHAN_657500_IDX] = { 26300, 0x1, 0x6D, 0x12AAAB, 0x890 }, + [ATHOS_LUT_CHAN_657625_IDX] = { 26305, 0x1, 0x6D, 0x135555, 0x890 }, + [ATHOS_LUT_CHAN_657750_IDX] = { 26310, 0x1, 0x6D, 0x140000, 0x891 }, + [ATHOS_LUT_CHAN_657875_IDX] = { 26315, 0x1, 0x6D, 0x14AAAB, 0x891 }, + [ATHOS_LUT_CHAN_658000_IDX] = { 26320, 0x1, 0x6D, 0x155555, 0x891 }, + [ATHOS_LUT_CHAN_658125_IDX] = { 26325, 0x1, 0x6D, 0x160000, 0x892 }, + [ATHOS_LUT_CHAN_658250_IDX] = { 26330, 0x1, 0x6D, 0x16AAAB, 0x892 }, + [ATHOS_LUT_CHAN_658375_IDX] = { 26335, 0x1, 0x6D, 0x175555, 0x893 }, + [ATHOS_LUT_CHAN_658500_IDX] = { 26340, 0x1, 0x6D, 0x180000, 0x893 }, + [ATHOS_LUT_CHAN_658625_IDX] = { 26345, 0x1, 0x6D, 0x18AAAB, 0x893 }, + [ATHOS_LUT_CHAN_658750_IDX] = { 26350, 0x1, 0x6D, 0x195555, 0x894 }, + [ATHOS_LUT_CHAN_658875_IDX] = { 26355, 0x1, 0x6D, 0x1A0000, 0x894 }, + [ATHOS_LUT_CHAN_659000_IDX] = { 26360, 0x1, 0x6D, 0x1AAAAB, 0x895 }, + [ATHOS_LUT_CHAN_659125_IDX] = { 26365, 0x1, 0x6D, 0x1B5555, 0x895 }, + [ATHOS_LUT_CHAN_659250_IDX] = { 26370, 0x1, 0x6D, 0x1C0000, 0x896 }, + [ATHOS_LUT_CHAN_659375_IDX] = { 26375, 0x1, 0x6D, 0x1CAAAB, 0x896 }, + [ATHOS_LUT_CHAN_659500_IDX] = { 26380, 0x1, 0x6D, 0x1D5555, 0x896 }, + [ATHOS_LUT_CHAN_659625_IDX] = { 26385, 0x1, 0x6D, 0x1E0000, 0x897 }, + [ATHOS_LUT_CHAN_659750_IDX] = { 26390, 0x1, 0x6D, 0x1EAAAB, 0x897 }, + [ATHOS_LUT_CHAN_659875_IDX] = { 26395, 0x1, 0x6D, 0x1F5555, 0x898 }, + [ATHOS_LUT_CHAN_660000_IDX] = { 26400, 0x1, 0x6E, 0x0, 0x898 }, + [ATHOS_LUT_CHAN_660125_IDX] = { 26405, 0x1, 0x6E, 0xAAAB, 0x898 }, + [ATHOS_LUT_CHAN_660250_IDX] = { 26410, 0x1, 0x6E, 0x15555, 0x899 }, + [ATHOS_LUT_CHAN_660375_IDX] = { 26415, 0x1, 0x6E, 0x20000, 0x899 }, + [ATHOS_LUT_CHAN_660500_IDX] = { 26420, 0x1, 0x6E, 0x2AAAB, 0x89A }, + [ATHOS_LUT_CHAN_660625_IDX] = { 26425, 0x1, 0x6E, 0x35555, 0x89A }, + [ATHOS_LUT_CHAN_660750_IDX] = { 26430, 0x1, 0x6E, 0x40000, 0x89B }, + [ATHOS_LUT_CHAN_660875_IDX] = { 26435, 0x1, 0x6E, 0x4AAAB, 0x89B }, + [ATHOS_LUT_CHAN_661000_IDX] = { 26440, 0x1, 0x6E, 0x55555, 0x89B }, + [ATHOS_LUT_CHAN_661125_IDX] = { 26445, 0x1, 0x6E, 0x60000, 0x89C }, + [ATHOS_LUT_CHAN_661250_IDX] = { 26450, 0x1, 0x6E, 0x6AAAB, 0x89C }, + [ATHOS_LUT_CHAN_661375_IDX] = { 26455, 0x1, 0x6E, 0x75555, 0x89D }, + [ATHOS_LUT_CHAN_661500_IDX] = { 26460, 0x1, 0x6E, 0x80000, 0x89D }, + [ATHOS_LUT_CHAN_661625_IDX] = { 26465, 0x1, 0x6E, 0x8AAAB, 0x89D }, + [ATHOS_LUT_CHAN_661750_IDX] = { 26470, 0x1, 0x6E, 0x95555, 0x89E }, + [ATHOS_LUT_CHAN_661875_IDX] = { 26475, 0x1, 0x6E, 0xA0000, 0x89E }, + [ATHOS_LUT_CHAN_662000_IDX] = { 26480, 0x1, 0x6E, 0xAAAAB, 0x89F }, + [ATHOS_LUT_CHAN_662125_IDX] = { 26485, 0x1, 0x6E, 0xB5555, 0x89F }, + [ATHOS_LUT_CHAN_662250_IDX] = { 26490, 0x1, 0x6E, 0xC0000, 0x8A0 }, + [ATHOS_LUT_CHAN_662375_IDX] = { 26495, 0x1, 0x6E, 0xCAAAB, 0x8A0 }, + [ATHOS_LUT_CHAN_662500_IDX] = { 26500, 0x1, 0x6E, 0xD5555, 0x8A0 }, + [ATHOS_LUT_CHAN_662625_IDX] = { 26505, 0x1, 0x6E, 0xE0000, 0x8A1 }, + [ATHOS_LUT_CHAN_662750_IDX] = { 26510, 0x1, 0x6E, 0xEAAAB, 0x8A1 }, + [ATHOS_LUT_CHAN_662875_IDX] = { 26515, 0x1, 0x6E, 0xF5555, 0x8A2 }, + [ATHOS_LUT_CHAN_663000_IDX] = { 26520, 0x1, 0x6E, 0x100000, 0x8A2 }, + [ATHOS_LUT_CHAN_663125_IDX] = { 26525, 0x1, 0x6E, 0x10AAAB, 0x8A2 }, + [ATHOS_LUT_CHAN_663250_IDX] = { 26530, 0x1, 0x6E, 0x115555, 0x8A3 }, + [ATHOS_LUT_CHAN_663375_IDX] = { 26535, 0x1, 0x6E, 0x120000, 0x8A3 }, + [ATHOS_LUT_CHAN_663500_IDX] = { 26540, 0x1, 0x6E, 0x12AAAB, 0x8A4 }, + [ATHOS_LUT_CHAN_663625_IDX] = { 26545, 0x1, 0x6E, 0x135555, 0x8A4 }, + [ATHOS_LUT_CHAN_663750_IDX] = { 26550, 0x1, 0x6E, 0x140000, 0x8A5 }, + [ATHOS_LUT_CHAN_663875_IDX] = { 26555, 0x1, 0x6E, 0x14AAAB, 0x8A5 }, + [ATHOS_LUT_CHAN_664000_IDX] = { 26560, 0x1, 0x6E, 0x155555, 0x8A5 }, + [ATHOS_LUT_CHAN_664125_IDX] = { 26565, 0x1, 0x6E, 0x160000, 0x8A6 }, + [ATHOS_LUT_CHAN_664250_IDX] = { 26570, 0x1, 0x6E, 0x16AAAB, 0x8A6 }, + [ATHOS_LUT_CHAN_664375_IDX] = { 26575, 0x1, 0x6E, 0x175555, 0x8A7 }, + [ATHOS_LUT_CHAN_664500_IDX] = { 26580, 0x1, 0x6E, 0x180000, 0x8A7 }, + [ATHOS_LUT_CHAN_664625_IDX] = { 26585, 0x1, 0x6E, 0x18AAAB, 0x8A7 }, + [ATHOS_LUT_CHAN_664750_IDX] = { 26590, 0x1, 0x6E, 0x195555, 0x8A8 }, + [ATHOS_LUT_CHAN_664875_IDX] = { 26595, 0x1, 0x6E, 0x1A0000, 0x8A8 }, + [ATHOS_LUT_CHAN_665000_IDX] = { 26600, 0x1, 0x6E, 0x1AAAAB, 0x8A9 }, + [ATHOS_LUT_CHAN_665125_IDX] = { 26605, 0x1, 0x6E, 0x1B5555, 0x8A9 }, + [ATHOS_LUT_CHAN_665250_IDX] = { 26610, 0x1, 0x6E, 0x1C0000, 0x8AA }, + [ATHOS_LUT_CHAN_665375_IDX] = { 26615, 0x1, 0x6E, 0x1CAAAB, 0x8AA }, + [ATHOS_LUT_CHAN_665500_IDX] = { 26620, 0x1, 0x6E, 0x1D5555, 0x8AA }, + [ATHOS_LUT_CHAN_665625_IDX] = { 26625, 0x1, 0x6E, 0x1E0000, 0x8AB }, + [ATHOS_LUT_CHAN_665750_IDX] = { 26630, 0x1, 0x6E, 0x1EAAAB, 0x8AB }, + [ATHOS_LUT_CHAN_665875_IDX] = { 26635, 0x1, 0x6E, 0x1F5555, 0x8AC }, + [ATHOS_LUT_CHAN_666000_IDX] = { 26640, 0x1, 0x6F, 0x0, 0x8AC }, + [ATHOS_LUT_CHAN_666125_IDX] = { 26645, 0x1, 0x6F, 0xAAAB, 0x8AC }, + [ATHOS_LUT_CHAN_666250_IDX] = { 26650, 0x1, 0x6F, 0x15555, 0x8AD }, + [ATHOS_LUT_CHAN_666375_IDX] = { 26655, 0x1, 0x6F, 0x20000, 0x8AD }, + [ATHOS_LUT_CHAN_666500_IDX] = { 26660, 0x1, 0x6F, 0x2AAAB, 0x8AE }, + [ATHOS_LUT_CHAN_666625_IDX] = { 26665, 0x1, 0x6F, 0x35555, 0x8AE }, + [ATHOS_LUT_CHAN_666750_IDX] = { 26670, 0x1, 0x6F, 0x40000, 0x8AF }, + [ATHOS_LUT_CHAN_666875_IDX] = { 26675, 0x1, 0x6F, 0x4AAAB, 0x8AF }, + [ATHOS_LUT_CHAN_667000_IDX] = { 26680, 0x1, 0x6F, 0x55555, 0x8AF }, + [ATHOS_LUT_CHAN_667125_IDX] = { 26685, 0x1, 0x6F, 0x60000, 0x8B0 }, + [ATHOS_LUT_CHAN_667250_IDX] = { 26690, 0x1, 0x6F, 0x6AAAB, 0x8B0 }, + [ATHOS_LUT_CHAN_667375_IDX] = { 26695, 0x1, 0x6F, 0x75555, 0x8B1 }, + [ATHOS_LUT_CHAN_667500_IDX] = { 26700, 0x1, 0x6F, 0x80000, 0x8B1 }, + [ATHOS_LUT_CHAN_667625_IDX] = { 26705, 0x1, 0x6F, 0x8AAAB, 0x8B1 }, + [ATHOS_LUT_CHAN_667750_IDX] = { 26710, 0x1, 0x6F, 0x95555, 0x8B2 }, + [ATHOS_LUT_CHAN_667875_IDX] = { 26715, 0x1, 0x6F, 0xA0000, 0x8B2 }, + [ATHOS_LUT_CHAN_668000_IDX] = { 26720, 0x1, 0x6F, 0xAAAAB, 0x8B3 }, + [ATHOS_LUT_CHAN_668125_IDX] = { 26725, 0x1, 0x6F, 0xB5555, 0x8B3 }, + [ATHOS_LUT_CHAN_668250_IDX] = { 26730, 0x1, 0x6F, 0xC0000, 0x8B4 }, + [ATHOS_LUT_CHAN_668375_IDX] = { 26735, 0x1, 0x6F, 0xCAAAB, 0x8B4 }, + [ATHOS_LUT_CHAN_668500_IDX] = { 26740, 0x1, 0x6F, 0xD5555, 0x8B4 }, + [ATHOS_LUT_CHAN_668625_IDX] = { 26745, 0x1, 0x6F, 0xE0000, 0x8B5 }, + [ATHOS_LUT_CHAN_668750_IDX] = { 26750, 0x1, 0x6F, 0xEAAAB, 0x8B5 }, + [ATHOS_LUT_CHAN_668875_IDX] = { 26755, 0x1, 0x6F, 0xF5555, 0x8B6 }, + [ATHOS_LUT_CHAN_669000_IDX] = { 26760, 0x1, 0x6F, 0x100000, 0x8B6 }, + [ATHOS_LUT_CHAN_669125_IDX] = { 26765, 0x1, 0x6F, 0x10AAAB, 0x8B6 }, + [ATHOS_LUT_CHAN_669250_IDX] = { 26770, 0x1, 0x6F, 0x115555, 0x8B7 }, + [ATHOS_LUT_CHAN_669375_IDX] = { 26775, 0x1, 0x6F, 0x120000, 0x8B7 }, + [ATHOS_LUT_CHAN_669500_IDX] = { 26780, 0x1, 0x6F, 0x12AAAB, 0x8B8 }, + [ATHOS_LUT_CHAN_669625_IDX] = { 26785, 0x1, 0x6F, 0x135555, 0x8B8 }, + [ATHOS_LUT_CHAN_669750_IDX] = { 26790, 0x1, 0x6F, 0x140000, 0x8B9 }, + [ATHOS_LUT_CHAN_669875_IDX] = { 26795, 0x1, 0x6F, 0x14AAAB, 0x8B9 }, + [ATHOS_LUT_CHAN_670000_IDX] = { 26800, 0x1, 0x6F, 0x155555, 0x8B9 }, + [ATHOS_LUT_CHAN_670125_IDX] = { 26805, 0x1, 0x6F, 0x160000, 0x8BA }, + [ATHOS_LUT_CHAN_670250_IDX] = { 26810, 0x1, 0x6F, 0x16AAAB, 0x8BA }, + [ATHOS_LUT_CHAN_670375_IDX] = { 26815, 0x1, 0x6F, 0x175555, 0x8BB }, + [ATHOS_LUT_CHAN_670500_IDX] = { 26820, 0x1, 0x6F, 0x180000, 0x8BB }, + [ATHOS_LUT_CHAN_670625_IDX] = { 26825, 0x1, 0x6F, 0x18AAAB, 0x8BB }, + [ATHOS_LUT_CHAN_670750_IDX] = { 26830, 0x1, 0x6F, 0x195555, 0x8BC }, + [ATHOS_LUT_CHAN_670875_IDX] = { 26835, 0x1, 0x6F, 0x1A0000, 0x8BC }, + [ATHOS_LUT_CHAN_671000_IDX] = { 26840, 0x1, 0x6F, 0x1AAAAB, 0x8BD }, + [ATHOS_LUT_CHAN_671125_IDX] = { 26845, 0x1, 0x6F, 0x1B5555, 0x8BD }, + [ATHOS_LUT_CHAN_671250_IDX] = { 26850, 0x1, 0x6F, 0x1C0000, 0x8BE }, + [ATHOS_LUT_CHAN_671375_IDX] = { 26855, 0x1, 0x6F, 0x1CAAAB, 0x8BE }, + [ATHOS_LUT_CHAN_671500_IDX] = { 26860, 0x1, 0x6F, 0x1D5555, 0x8BE }, + [ATHOS_LUT_CHAN_671625_IDX] = { 26865, 0x1, 0x6F, 0x1E0000, 0x8BF }, + [ATHOS_LUT_CHAN_671750_IDX] = { 26870, 0x1, 0x6F, 0x1EAAAB, 0x8BF }, + [ATHOS_LUT_CHAN_671875_IDX] = { 26875, 0x1, 0x6F, 0x1F5555, 0x8C0 }, + [ATHOS_LUT_CHAN_672000_IDX] = { 26880, 0x1, 0x70, 0x0, 0x8C0 }, + [ATHOS_LUT_CHAN_672125_IDX] = { 26885, 0x1, 0x70, 0xAAAB, 0x8C0 }, + [ATHOS_LUT_CHAN_672250_IDX] = { 26890, 0x1, 0x70, 0x15555, 0x8C1 }, + [ATHOS_LUT_CHAN_672375_IDX] = { 26895, 0x1, 0x70, 0x20000, 0x8C1 }, + [ATHOS_LUT_CHAN_672500_IDX] = { 26900, 0x1, 0x70, 0x2AAAB, 0x8C2 }, + [ATHOS_LUT_CHAN_672625_IDX] = { 26905, 0x1, 0x70, 0x35555, 0x8C2 }, + [ATHOS_LUT_CHAN_672750_IDX] = { 26910, 0x1, 0x70, 0x40000, 0x8C3 }, + [ATHOS_LUT_CHAN_672875_IDX] = { 26915, 0x1, 0x70, 0x4AAAB, 0x8C3 }, + [ATHOS_LUT_CHAN_673000_IDX] = { 26920, 0x1, 0x70, 0x55555, 0x8C3 }, + [ATHOS_LUT_CHAN_673125_IDX] = { 26925, 0x1, 0x70, 0x60000, 0x8C4 }, + [ATHOS_LUT_CHAN_673250_IDX] = { 26930, 0x1, 0x70, 0x6AAAB, 0x8C4 }, + [ATHOS_LUT_CHAN_673375_IDX] = { 26935, 0x1, 0x70, 0x75555, 0x8C5 }, + [ATHOS_LUT_CHAN_673500_IDX] = { 26940, 0x1, 0x70, 0x80000, 0x8C5 }, + [ATHOS_LUT_CHAN_673625_IDX] = { 26945, 0x1, 0x70, 0x8AAAB, 0x8C5 }, + [ATHOS_LUT_CHAN_673750_IDX] = { 26950, 0x1, 0x70, 0x95555, 0x8C6 }, + [ATHOS_LUT_CHAN_673875_IDX] = { 26955, 0x1, 0x70, 0xA0000, 0x8C6 }, + [ATHOS_LUT_CHAN_674000_IDX] = { 26960, 0x1, 0x70, 0xAAAAB, 0x8C7 }, + [ATHOS_LUT_CHAN_674125_IDX] = { 26965, 0x1, 0x70, 0xB5555, 0x8C7 }, + [ATHOS_LUT_CHAN_674250_IDX] = { 26970, 0x1, 0x70, 0xC0000, 0x8C8 }, + [ATHOS_LUT_CHAN_674375_IDX] = { 26975, 0x1, 0x70, 0xCAAAB, 0x8C8 }, + [ATHOS_LUT_CHAN_674500_IDX] = { 26980, 0x1, 0x70, 0xD5555, 0x8C8 }, + [ATHOS_LUT_CHAN_674625_IDX] = { 26985, 0x1, 0x70, 0xE0000, 0x8C9 }, + [ATHOS_LUT_CHAN_674750_IDX] = { 26990, 0x1, 0x70, 0xEAAAB, 0x8C9 }, + [ATHOS_LUT_CHAN_674875_IDX] = { 26995, 0x1, 0x70, 0xF5555, 0x8CA }, + [ATHOS_LUT_CHAN_675000_IDX] = { 27000, 0x1, 0x70, 0x100000, 0x8CA }, + [ATHOS_LUT_CHAN_675125_IDX] = { 27005, 0x1, 0x70, 0x10AAAB, 0x8CA }, + [ATHOS_LUT_CHAN_675250_IDX] = { 27010, 0x1, 0x70, 0x115555, 0x8CB }, + [ATHOS_LUT_CHAN_675375_IDX] = { 27015, 0x1, 0x70, 0x120000, 0x8CB }, + [ATHOS_LUT_CHAN_675500_IDX] = { 27020, 0x1, 0x70, 0x12AAAB, 0x8CC }, + [ATHOS_LUT_CHAN_675625_IDX] = { 27025, 0x1, 0x70, 0x135555, 0x8CC }, + [ATHOS_LUT_CHAN_675750_IDX] = { 27030, 0x1, 0x70, 0x140000, 0x8CD }, + [ATHOS_LUT_CHAN_675875_IDX] = { 27035, 0x1, 0x70, 0x14AAAB, 0x8CD }, + [ATHOS_LUT_CHAN_676000_IDX] = { 27040, 0x1, 0x70, 0x155555, 0x8CD }, + [ATHOS_LUT_CHAN_676125_IDX] = { 27045, 0x1, 0x70, 0x160000, 0x8CE }, + [ATHOS_LUT_CHAN_676250_IDX] = { 27050, 0x1, 0x70, 0x16AAAB, 0x8CE }, + [ATHOS_LUT_CHAN_676375_IDX] = { 27055, 0x1, 0x70, 0x175555, 0x8CF }, + [ATHOS_LUT_CHAN_676500_IDX] = { 27060, 0x1, 0x70, 0x180000, 0x8CF }, + [ATHOS_LUT_CHAN_676625_IDX] = { 27065, 0x1, 0x70, 0x18AAAB, 0x8CF }, + [ATHOS_LUT_CHAN_676750_IDX] = { 27070, 0x1, 0x70, 0x195555, 0x8D0 }, + [ATHOS_LUT_CHAN_676875_IDX] = { 27075, 0x1, 0x70, 0x1A0000, 0x8D0 }, + [ATHOS_LUT_CHAN_677000_IDX] = { 27080, 0x1, 0x70, 0x1AAAAB, 0x8D1 }, + [ATHOS_LUT_CHAN_677125_IDX] = { 27085, 0x1, 0x70, 0x1B5555, 0x8D1 }, + [ATHOS_LUT_CHAN_677250_IDX] = { 27090, 0x1, 0x70, 0x1C0000, 0x8D2 }, + [ATHOS_LUT_CHAN_677375_IDX] = { 27095, 0x1, 0x70, 0x1CAAAB, 0x8D2 }, + [ATHOS_LUT_CHAN_677500_IDX] = { 27100, 0x1, 0x70, 0x1D5555, 0x8D2 }, + [ATHOS_LUT_CHAN_677625_IDX] = { 27105, 0x1, 0x70, 0x1E0000, 0x8D3 }, + [ATHOS_LUT_CHAN_677750_IDX] = { 27110, 0x1, 0x70, 0x1EAAAB, 0x8D3 }, + [ATHOS_LUT_CHAN_677875_IDX] = { 27115, 0x1, 0x70, 0x1F5555, 0x8D4 }, + [ATHOS_LUT_CHAN_678000_IDX] = { 27120, 0x1, 0x71, 0x0, 0x8D4 }, + [ATHOS_LUT_CHAN_678125_IDX] = { 27125, 0x1, 0x71, 0xAAAB, 0x8D4 }, + [ATHOS_LUT_CHAN_678250_IDX] = { 27130, 0x1, 0x71, 0x15555, 0x8D5 }, + [ATHOS_LUT_CHAN_678375_IDX] = { 27135, 0x1, 0x71, 0x20000, 0x8D5 }, + [ATHOS_LUT_CHAN_678500_IDX] = { 27140, 0x1, 0x71, 0x2AAAB, 0x8D6 }, + [ATHOS_LUT_CHAN_678625_IDX] = { 27145, 0x1, 0x71, 0x35555, 0x8D6 }, + [ATHOS_LUT_CHAN_678750_IDX] = { 27150, 0x1, 0x71, 0x40000, 0x8D7 }, + [ATHOS_LUT_CHAN_678875_IDX] = { 27155, 0x1, 0x71, 0x4AAAB, 0x8D7 }, + [ATHOS_LUT_CHAN_679000_IDX] = { 27160, 0x1, 0x71, 0x55555, 0x8D7 }, + [ATHOS_LUT_CHAN_679125_IDX] = { 27165, 0x1, 0x71, 0x60000, 0x8D8 }, + [ATHOS_LUT_CHAN_679250_IDX] = { 27170, 0x1, 0x71, 0x6AAAB, 0x8D8 }, + [ATHOS_LUT_CHAN_679375_IDX] = { 27175, 0x1, 0x71, 0x75555, 0x8D9 }, + [ATHOS_LUT_CHAN_679500_IDX] = { 27180, 0x1, 0x71, 0x80000, 0x8D9 }, + [ATHOS_LUT_CHAN_679625_IDX] = { 27185, 0x1, 0x71, 0x8AAAB, 0x8D9 }, + [ATHOS_LUT_CHAN_679750_IDX] = { 27190, 0x1, 0x71, 0x95555, 0x8DA }, + [ATHOS_LUT_CHAN_679875_IDX] = { 27195, 0x1, 0x71, 0xA0000, 0x8DA }, + [ATHOS_LUT_CHAN_680000_IDX] = { 27200, 0x1, 0x71, 0xAAAAB, 0x8DB }, + [ATHOS_LUT_CHAN_680125_IDX] = { 27205, 0x1, 0x71, 0xB5555, 0x8DB }, + [ATHOS_LUT_CHAN_680250_IDX] = { 27210, 0x1, 0x71, 0xC0000, 0x8DC }, + [ATHOS_LUT_CHAN_680375_IDX] = { 27215, 0x1, 0x71, 0xCAAAB, 0x8DC }, + [ATHOS_LUT_CHAN_680500_IDX] = { 27220, 0x1, 0x71, 0xD5555, 0x8DC }, + [ATHOS_LUT_CHAN_680625_IDX] = { 27225, 0x1, 0x71, 0xE0000, 0x8DD }, + [ATHOS_LUT_CHAN_680750_IDX] = { 27230, 0x1, 0x71, 0xEAAAB, 0x8DD }, + [ATHOS_LUT_CHAN_680875_IDX] = { 27235, 0x1, 0x71, 0xF5555, 0x8DE }, + [ATHOS_LUT_CHAN_681000_IDX] = { 27240, 0x1, 0x71, 0x100000, 0x8DE }, + [ATHOS_LUT_CHAN_681125_IDX] = { 27245, 0x1, 0x71, 0x10AAAB, 0x8DE }, + [ATHOS_LUT_CHAN_681250_IDX] = { 27250, 0x1, 0x71, 0x115555, 0x8DF }, + [ATHOS_LUT_CHAN_681375_IDX] = { 27255, 0x1, 0x71, 0x120000, 0x8DF }, + [ATHOS_LUT_CHAN_681500_IDX] = { 27260, 0x1, 0x71, 0x12AAAB, 0x8E0 }, + [ATHOS_LUT_CHAN_681625_IDX] = { 27265, 0x1, 0x71, 0x135555, 0x8E0 }, + [ATHOS_LUT_CHAN_681750_IDX] = { 27270, 0x1, 0x71, 0x140000, 0x8E1 }, + [ATHOS_LUT_CHAN_681875_IDX] = { 27275, 0x1, 0x71, 0x14AAAB, 0x8E1 }, + [ATHOS_LUT_CHAN_682000_IDX] = { 27280, 0x1, 0x71, 0x155555, 0x8E1 }, + [ATHOS_LUT_CHAN_682125_IDX] = { 27285, 0x1, 0x71, 0x160000, 0x8E2 }, + [ATHOS_LUT_CHAN_682250_IDX] = { 27290, 0x1, 0x71, 0x16AAAB, 0x8E2 }, + [ATHOS_LUT_CHAN_682375_IDX] = { 27295, 0x1, 0x71, 0x175555, 0x8E3 }, + [ATHOS_LUT_CHAN_682500_IDX] = { 27300, 0x1, 0x71, 0x180000, 0x8E3 }, + [ATHOS_LUT_CHAN_682625_IDX] = { 27305, 0x1, 0x71, 0x18AAAB, 0x8E3 }, + [ATHOS_LUT_CHAN_682750_IDX] = { 27310, 0x1, 0x71, 0x195555, 0x8E4 }, + [ATHOS_LUT_CHAN_682875_IDX] = { 27315, 0x1, 0x71, 0x1A0000, 0x8E4 }, + [ATHOS_LUT_CHAN_683000_IDX] = { 27320, 0x1, 0x71, 0x1AAAAB, 0x8E5 }, + [ATHOS_LUT_CHAN_683125_IDX] = { 27325, 0x1, 0x71, 0x1B5555, 0x8E5 }, + [ATHOS_LUT_CHAN_683250_IDX] = { 27330, 0x1, 0x71, 0x1C0000, 0x8E6 }, + [ATHOS_LUT_CHAN_683375_IDX] = { 27335, 0x1, 0x71, 0x1CAAAB, 0x8E6 }, + [ATHOS_LUT_CHAN_683500_IDX] = { 27340, 0x1, 0x71, 0x1D5555, 0x8E6 }, + [ATHOS_LUT_CHAN_683625_IDX] = { 27345, 0x1, 0x71, 0x1E0000, 0x8E7 }, + [ATHOS_LUT_CHAN_683750_IDX] = { 27350, 0x1, 0x71, 0x1EAAAB, 0x8E7 }, + [ATHOS_LUT_CHAN_683875_IDX] = { 27355, 0x1, 0x71, 0x1F5555, 0x8E8 }, + [ATHOS_LUT_CHAN_684000_IDX] = { 27360, 0x1, 0x72, 0x0, 0x8E8 }, + [ATHOS_LUT_CHAN_684125_IDX] = { 27365, 0x1, 0x72, 0xAAAB, 0x8E8 }, + [ATHOS_LUT_CHAN_684250_IDX] = { 27370, 0x1, 0x72, 0x15555, 0x8E9 }, + [ATHOS_LUT_CHAN_684375_IDX] = { 27375, 0x1, 0x72, 0x20000, 0x8E9 }, + [ATHOS_LUT_CHAN_684500_IDX] = { 27380, 0x1, 0x72, 0x2AAAB, 0x8EA }, + [ATHOS_LUT_CHAN_684625_IDX] = { 27385, 0x1, 0x72, 0x35555, 0x8EA }, + [ATHOS_LUT_CHAN_684750_IDX] = { 27390, 0x1, 0x72, 0x40000, 0x8EB }, + [ATHOS_LUT_CHAN_684875_IDX] = { 27395, 0x1, 0x72, 0x4AAAB, 0x8EB }, + [ATHOS_LUT_CHAN_685000_IDX] = { 27400, 0x1, 0x72, 0x55555, 0x8EB }, + [ATHOS_LUT_CHAN_685125_IDX] = { 27405, 0x1, 0x72, 0x60000, 0x8EC }, + [ATHOS_LUT_CHAN_685250_IDX] = { 27410, 0x1, 0x72, 0x6AAAB, 0x8EC }, + [ATHOS_LUT_CHAN_685375_IDX] = { 27415, 0x1, 0x72, 0x75555, 0x8ED }, + [ATHOS_LUT_CHAN_685500_IDX] = { 27420, 0x1, 0x72, 0x80000, 0x8ED }, + [ATHOS_LUT_CHAN_685625_IDX] = { 27425, 0x1, 0x72, 0x8AAAB, 0x8ED }, + [ATHOS_LUT_CHAN_685750_IDX] = { 27430, 0x1, 0x72, 0x95555, 0x8EE }, + [ATHOS_LUT_CHAN_685875_IDX] = { 27435, 0x1, 0x72, 0xA0000, 0x8EE }, + [ATHOS_LUT_CHAN_686000_IDX] = { 27440, 0x1, 0x72, 0xAAAAB, 0x8EF }, + [ATHOS_LUT_CHAN_686125_IDX] = { 27445, 0x1, 0x72, 0xB5555, 0x8EF }, + [ATHOS_LUT_CHAN_686250_IDX] = { 27450, 0x1, 0x72, 0xC0000, 0x8F0 }, + [ATHOS_LUT_CHAN_686375_IDX] = { 27455, 0x1, 0x72, 0xCAAAB, 0x8F0 }, + [ATHOS_LUT_CHAN_686500_IDX] = { 27460, 0x1, 0x72, 0xD5555, 0x8F0 }, + [ATHOS_LUT_CHAN_686625_IDX] = { 27465, 0x1, 0x72, 0xE0000, 0x8F1 }, + [ATHOS_LUT_CHAN_686750_IDX] = { 27470, 0x1, 0x72, 0xEAAAB, 0x8F1 }, + [ATHOS_LUT_CHAN_686875_IDX] = { 27475, 0x1, 0x72, 0xF5555, 0x8F2 }, + [ATHOS_LUT_CHAN_687000_IDX] = { 27480, 0x1, 0x72, 0x100000, 0x8F2 }, + [ATHOS_LUT_CHAN_687125_IDX] = { 27485, 0x1, 0x72, 0x10AAAB, 0x8F2 }, + [ATHOS_LUT_CHAN_687250_IDX] = { 27490, 0x1, 0x72, 0x115555, 0x8F3 }, + [ATHOS_LUT_CHAN_687375_IDX] = { 27495, 0x1, 0x72, 0x120000, 0x8F3 }, + [ATHOS_LUT_CHAN_687500_IDX] = { 27500, 0x1, 0x72, 0x12AAAB, 0x8F4 }, + [ATHOS_LUT_CHAN_687625_IDX] = { 27505, 0x1, 0x72, 0x135555, 0x8F4 }, + [ATHOS_LUT_CHAN_687750_IDX] = { 27510, 0x1, 0x72, 0x140000, 0x8F5 }, + [ATHOS_LUT_CHAN_687875_IDX] = { 27515, 0x1, 0x72, 0x14AAAB, 0x8F5 }, + [ATHOS_LUT_CHAN_688000_IDX] = { 27520, 0x1, 0x72, 0x155555, 0x8F5 }, + [ATHOS_LUT_CHAN_688125_IDX] = { 27525, 0x1, 0x72, 0x160000, 0x8F6 }, + [ATHOS_LUT_CHAN_688250_IDX] = { 27530, 0x1, 0x72, 0x16AAAB, 0x8F6 }, + [ATHOS_LUT_CHAN_688375_IDX] = { 27535, 0x1, 0x72, 0x175555, 0x8F7 }, + [ATHOS_LUT_CHAN_688500_IDX] = { 27540, 0x1, 0x72, 0x180000, 0x8F7 }, + [ATHOS_LUT_CHAN_688625_IDX] = { 27545, 0x1, 0x72, 0x18AAAB, 0x8F7 }, + [ATHOS_LUT_CHAN_688750_IDX] = { 27550, 0x1, 0x72, 0x195555, 0x8F8 }, + [ATHOS_LUT_CHAN_688875_IDX] = { 27555, 0x1, 0x72, 0x1A0000, 0x8F8 }, + [ATHOS_LUT_CHAN_689000_IDX] = { 27560, 0x1, 0x72, 0x1AAAAB, 0x8F9 }, + [ATHOS_LUT_CHAN_689125_IDX] = { 27565, 0x1, 0x72, 0x1B5555, 0x8F9 }, + [ATHOS_LUT_CHAN_689250_IDX] = { 27570, 0x1, 0x72, 0x1C0000, 0x8FA }, + [ATHOS_LUT_CHAN_689375_IDX] = { 27575, 0x1, 0x72, 0x1CAAAB, 0x8FA }, + [ATHOS_LUT_CHAN_689500_IDX] = { 27580, 0x1, 0x72, 0x1D5555, 0x8FA }, + [ATHOS_LUT_CHAN_689625_IDX] = { 27585, 0x1, 0x72, 0x1E0000, 0x8FB }, + [ATHOS_LUT_CHAN_689750_IDX] = { 27590, 0x1, 0x72, 0x1EAAAB, 0x8FB }, + [ATHOS_LUT_CHAN_689875_IDX] = { 27595, 0x1, 0x72, 0x1F5555, 0x8FC }, + [ATHOS_LUT_CHAN_690000_IDX] = { 27600, 0x1, 0x73, 0x0, 0x8FC }, + [ATHOS_LUT_CHAN_690125_IDX] = { 27605, 0x1, 0x73, 0xAAAB, 0x8FC }, + [ATHOS_LUT_CHAN_690250_IDX] = { 27610, 0x1, 0x73, 0x15555, 0x8FD }, + [ATHOS_LUT_CHAN_690375_IDX] = { 27615, 0x1, 0x73, 0x20000, 0x8FD }, + [ATHOS_LUT_CHAN_690500_IDX] = { 27620, 0x1, 0x73, 0x2AAAB, 0x8FE }, + [ATHOS_LUT_CHAN_690625_IDX] = { 27625, 0x1, 0x73, 0x35555, 0x8FE }, + [ATHOS_LUT_CHAN_690750_IDX] = { 27630, 0x1, 0x73, 0x40000, 0x8FF }, + [ATHOS_LUT_CHAN_690875_IDX] = { 27635, 0x1, 0x73, 0x4AAAB, 0x8FF }, + [ATHOS_LUT_CHAN_691000_IDX] = { 27640, 0x1, 0x73, 0x55555, 0x8FF }, + [ATHOS_LUT_CHAN_691125_IDX] = { 27645, 0x1, 0x73, 0x60000, 0x900 }, + [ATHOS_LUT_CHAN_691250_IDX] = { 27650, 0x1, 0x73, 0x6AAAB, 0x900 }, + [ATHOS_LUT_CHAN_691375_IDX] = { 27655, 0x1, 0x73, 0x75555, 0x901 }, + [ATHOS_LUT_CHAN_691500_IDX] = { 27660, 0x1, 0x73, 0x80000, 0x901 }, + [ATHOS_LUT_CHAN_691625_IDX] = { 27665, 0x1, 0x73, 0x8AAAB, 0x901 }, + [ATHOS_LUT_CHAN_691750_IDX] = { 27670, 0x1, 0x73, 0x95555, 0x902 }, + [ATHOS_LUT_CHAN_691875_IDX] = { 27675, 0x1, 0x73, 0xA0000, 0x902 }, + [ATHOS_LUT_CHAN_692000_IDX] = { 27680, 0x1, 0x73, 0xAAAAB, 0x903 }, + [ATHOS_LUT_CHAN_692125_IDX] = { 27685, 0x1, 0x73, 0xB5555, 0x903 }, + [ATHOS_LUT_CHAN_692250_IDX] = { 27690, 0x1, 0x73, 0xC0000, 0x904 }, + [ATHOS_LUT_CHAN_692375_IDX] = { 27695, 0x1, 0x73, 0xCAAAB, 0x904 }, + [ATHOS_LUT_CHAN_692500_IDX] = { 27700, 0x1, 0x73, 0xD5555, 0x904 }, + [ATHOS_LUT_CHAN_692625_IDX] = { 27705, 0x1, 0x73, 0xE0000, 0x905 }, + [ATHOS_LUT_CHAN_692750_IDX] = { 27710, 0x1, 0x73, 0xEAAAB, 0x905 }, + [ATHOS_LUT_CHAN_692875_IDX] = { 27715, 0x1, 0x73, 0xF5555, 0x906 }, + [ATHOS_LUT_CHAN_693000_IDX] = { 27720, 0x1, 0x73, 0x100000, 0x906 }, + [ATHOS_LUT_CHAN_693125_IDX] = { 27725, 0x1, 0x73, 0x10AAAB, 0x906 }, + [ATHOS_LUT_CHAN_693250_IDX] = { 27730, 0x1, 0x73, 0x115555, 0x907 }, + [ATHOS_LUT_CHAN_693375_IDX] = { 27735, 0x1, 0x73, 0x120000, 0x907 }, + [ATHOS_LUT_CHAN_693500_IDX] = { 27740, 0x1, 0x73, 0x12AAAB, 0x908 }, + [ATHOS_LUT_CHAN_693625_IDX] = { 27745, 0x1, 0x73, 0x135555, 0x908 }, + [ATHOS_LUT_CHAN_693750_IDX] = { 27750, 0x1, 0x73, 0x140000, 0x909 }, + [ATHOS_LUT_CHAN_693875_IDX] = { 27755, 0x1, 0x73, 0x14AAAB, 0x909 }, + [ATHOS_LUT_CHAN_694000_IDX] = { 27760, 0x1, 0x73, 0x155555, 0x909 }, + [ATHOS_LUT_CHAN_694125_IDX] = { 27765, 0x1, 0x73, 0x160000, 0x90A }, + [ATHOS_LUT_CHAN_694250_IDX] = { 27770, 0x1, 0x73, 0x16AAAB, 0x90A }, + [ATHOS_LUT_CHAN_694375_IDX] = { 27775, 0x1, 0x73, 0x175555, 0x90B }, + [ATHOS_LUT_CHAN_694500_IDX] = { 27780, 0x1, 0x73, 0x180000, 0x90B }, + [ATHOS_LUT_CHAN_694625_IDX] = { 27785, 0x1, 0x73, 0x18AAAB, 0x90B }, + [ATHOS_LUT_CHAN_694750_IDX] = { 27790, 0x1, 0x73, 0x195555, 0x90C }, + [ATHOS_LUT_CHAN_694875_IDX] = { 27795, 0x1, 0x73, 0x1A0000, 0x90C }, + [ATHOS_LUT_CHAN_695000_IDX] = { 27800, 0x1, 0x73, 0x1AAAAB, 0x90D }, + [ATHOS_LUT_CHAN_695125_IDX] = { 27805, 0x1, 0x73, 0x1B5555, 0x90D }, + [ATHOS_LUT_CHAN_695250_IDX] = { 27810, 0x1, 0x73, 0x1C0000, 0x90E }, + [ATHOS_LUT_CHAN_695375_IDX] = { 27815, 0x1, 0x73, 0x1CAAAB, 0x90E }, + [ATHOS_LUT_CHAN_695500_IDX] = { 27820, 0x1, 0x73, 0x1D5555, 0x90E }, + [ATHOS_LUT_CHAN_695625_IDX] = { 27825, 0x1, 0x73, 0x1E0000, 0x90F }, + [ATHOS_LUT_CHAN_695750_IDX] = { 27830, 0x1, 0x73, 0x1EAAAB, 0x90F }, + [ATHOS_LUT_CHAN_695875_IDX] = { 27835, 0x1, 0x73, 0x1F5555, 0x910 }, + [ATHOS_LUT_CHAN_696000_IDX] = { 27840, 0x1, 0x74, 0x0, 0x910 }, + [ATHOS_LUT_CHAN_696125_IDX] = { 27845, 0x1, 0x74, 0xAAAB, 0x910 }, + [ATHOS_LUT_CHAN_696250_IDX] = { 27850, 0x1, 0x74, 0x15555, 0x911 }, + [ATHOS_LUT_CHAN_696375_IDX] = { 27855, 0x1, 0x74, 0x20000, 0x911 }, + [ATHOS_LUT_CHAN_696500_IDX] = { 27860, 0x1, 0x74, 0x2AAAB, 0x912 }, + [ATHOS_LUT_CHAN_696625_IDX] = { 27865, 0x1, 0x74, 0x35555, 0x912 }, + [ATHOS_LUT_CHAN_696750_IDX] = { 27870, 0x1, 0x74, 0x40000, 0x913 }, + [ATHOS_LUT_CHAN_696875_IDX] = { 27875, 0x1, 0x74, 0x4AAAB, 0x913 }, + [ATHOS_LUT_CHAN_697000_IDX] = { 27880, 0x1, 0x74, 0x55555, 0x913 }, + [ATHOS_LUT_CHAN_697125_IDX] = { 27885, 0x1, 0x74, 0x60000, 0x914 }, + [ATHOS_LUT_CHAN_697250_IDX] = { 27890, 0x1, 0x74, 0x6AAAB, 0x914 }, + [ATHOS_LUT_CHAN_697375_IDX] = { 27895, 0x1, 0x74, 0x75555, 0x915 }, + [ATHOS_LUT_CHAN_697500_IDX] = { 27900, 0x1, 0x74, 0x80000, 0x915 }, + [ATHOS_LUT_CHAN_697625_IDX] = { 27905, 0x1, 0x74, 0x8AAAB, 0x915 }, + [ATHOS_LUT_CHAN_697750_IDX] = { 27910, 0x1, 0x74, 0x95555, 0x916 }, + [ATHOS_LUT_CHAN_697875_IDX] = { 27915, 0x1, 0x74, 0xA0000, 0x916 }, + [ATHOS_LUT_CHAN_698000_IDX] = { 27920, 0x1, 0x74, 0xAAAAB, 0x917 }, + [ATHOS_LUT_CHAN_698125_IDX] = { 27925, 0x1, 0x74, 0xB5555, 0x917 }, + [ATHOS_LUT_CHAN_698250_IDX] = { 27930, 0x1, 0x74, 0xC0000, 0x918 }, + [ATHOS_LUT_CHAN_698375_IDX] = { 27935, 0x1, 0x74, 0xCAAAB, 0x918 }, + [ATHOS_LUT_CHAN_698500_IDX] = { 27940, 0x1, 0x74, 0xD5555, 0x918 }, + [ATHOS_LUT_CHAN_698625_IDX] = { 27945, 0x1, 0x74, 0xE0000, 0x919 }, + [ATHOS_LUT_CHAN_698750_IDX] = { 27950, 0x1, 0x74, 0xEAAAB, 0x919 }, + [ATHOS_LUT_CHAN_698875_IDX] = { 27955, 0x1, 0x74, 0xF5555, 0x91A }, + [ATHOS_LUT_CHAN_699000_IDX] = { 27960, 0x1, 0x74, 0x100000, 0x91A }, + [ATHOS_LUT_CHAN_699125_IDX] = { 27965, 0x1, 0x74, 0x10AAAB, 0x91A }, + [ATHOS_LUT_CHAN_699250_IDX] = { 27970, 0x1, 0x74, 0x115555, 0x91B }, + [ATHOS_LUT_CHAN_699375_IDX] = { 27975, 0x1, 0x74, 0x120000, 0x91B }, + [ATHOS_LUT_CHAN_699500_IDX] = { 27980, 0x1, 0x74, 0x12AAAB, 0x91C }, + [ATHOS_LUT_CHAN_699625_IDX] = { 27985, 0x1, 0x74, 0x135555, 0x91C }, + [ATHOS_LUT_CHAN_699750_IDX] = { 27990, 0x1, 0x74, 0x140000, 0x91D }, + [ATHOS_LUT_CHAN_699875_IDX] = { 27995, 0x1, 0x74, 0x14AAAB, 0x91D }, + [ATHOS_LUT_CHAN_700000_IDX] = { 28000, 0x1, 0x74, 0x155555, 0x91D }, + [ATHOS_LUT_CHAN_700125_IDX] = { 28005, 0x1, 0x74, 0x160000, 0x91E }, + [ATHOS_LUT_CHAN_700250_IDX] = { 28010, 0x1, 0x74, 0x16AAAB, 0x91E }, + [ATHOS_LUT_CHAN_700375_IDX] = { 28015, 0x1, 0x74, 0x175555, 0x91F }, + [ATHOS_LUT_CHAN_700500_IDX] = { 28020, 0x1, 0x74, 0x180000, 0x91F }, + [ATHOS_LUT_CHAN_700625_IDX] = { 28025, 0x1, 0x74, 0x18AAAB, 0x91F }, + [ATHOS_LUT_CHAN_700750_IDX] = { 28030, 0x1, 0x74, 0x195555, 0x920 }, + [ATHOS_LUT_CHAN_700875_IDX] = { 28035, 0x1, 0x74, 0x1A0000, 0x920 }, + [ATHOS_LUT_CHAN_701000_IDX] = { 28040, 0x1, 0x74, 0x1AAAAB, 0x921 }, + [ATHOS_LUT_CHAN_701125_IDX] = { 28045, 0x1, 0x74, 0x1B5555, 0x921 }, + [ATHOS_LUT_CHAN_701250_IDX] = { 28050, 0x1, 0x74, 0x1C0000, 0x922 }, + [ATHOS_LUT_CHAN_701375_IDX] = { 28055, 0x1, 0x74, 0x1CAAAB, 0x922 }, + [ATHOS_LUT_CHAN_701500_IDX] = { 28060, 0x1, 0x74, 0x1D5555, 0x922 }, + [ATHOS_LUT_CHAN_701625_IDX] = { 28065, 0x1, 0x74, 0x1E0000, 0x923 }, + [ATHOS_LUT_CHAN_701750_IDX] = { 28070, 0x1, 0x74, 0x1EAAAB, 0x923 }, + [ATHOS_LUT_CHAN_701875_IDX] = { 28075, 0x1, 0x74, 0x1F5555, 0x924 }, + [ATHOS_LUT_CHAN_702000_IDX] = { 28080, 0x1, 0x75, 0x0, 0x924 }, + [ATHOS_LUT_CHAN_702125_IDX] = { 28085, 0x1, 0x75, 0xAAAB, 0x924 }, + [ATHOS_LUT_CHAN_702250_IDX] = { 28090, 0x1, 0x75, 0x15555, 0x925 }, + [ATHOS_LUT_CHAN_702375_IDX] = { 28095, 0x1, 0x75, 0x20000, 0x925 }, + [ATHOS_LUT_CHAN_702500_IDX] = { 28100, 0x1, 0x75, 0x2AAAB, 0x926 }, + [ATHOS_LUT_CHAN_702625_IDX] = { 28105, 0x1, 0x75, 0x35555, 0x926 }, + [ATHOS_LUT_CHAN_702750_IDX] = { 28110, 0x1, 0x75, 0x40000, 0x927 }, + [ATHOS_LUT_CHAN_702875_IDX] = { 28115, 0x1, 0x75, 0x4AAAB, 0x927 }, + [ATHOS_LUT_CHAN_703000_IDX] = { 28120, 0x1, 0x75, 0x55555, 0x927 }, + [ATHOS_LUT_CHAN_703125_IDX] = { 28125, 0x1, 0x75, 0x60000, 0x928 }, + [ATHOS_LUT_CHAN_703250_IDX] = { 28130, 0x1, 0x75, 0x6AAAB, 0x928 }, + [ATHOS_LUT_CHAN_703375_IDX] = { 28135, 0x1, 0x75, 0x75555, 0x929 }, + [ATHOS_LUT_CHAN_703500_IDX] = { 28140, 0x1, 0x75, 0x80000, 0x929 }, + [ATHOS_LUT_CHAN_703625_IDX] = { 28145, 0x1, 0x75, 0x8AAAB, 0x929 }, + [ATHOS_LUT_CHAN_703750_IDX] = { 28150, 0x1, 0x75, 0x95555, 0x92A }, + [ATHOS_LUT_CHAN_703875_IDX] = { 28155, 0x1, 0x75, 0xA0000, 0x92A }, + [ATHOS_LUT_CHAN_704000_IDX] = { 28160, 0x1, 0x75, 0xAAAAB, 0x92B }, + [ATHOS_LUT_CHAN_704125_IDX] = { 28165, 0x1, 0x75, 0xB5555, 0x92B }, + [ATHOS_LUT_CHAN_704250_IDX] = { 28170, 0x1, 0x75, 0xC0000, 0x92C }, + [ATHOS_LUT_CHAN_704375_IDX] = { 28175, 0x1, 0x75, 0xCAAAB, 0x92C }, + [ATHOS_LUT_CHAN_704500_IDX] = { 28180, 0x1, 0x75, 0xD5555, 0x92C }, + [ATHOS_LUT_CHAN_704625_IDX] = { 28185, 0x1, 0x75, 0xE0000, 0x92D }, + [ATHOS_LUT_CHAN_704750_IDX] = { 28190, 0x1, 0x75, 0xEAAAB, 0x92D }, + [ATHOS_LUT_CHAN_704875_IDX] = { 28195, 0x1, 0x75, 0xF5555, 0x92E }, + [ATHOS_LUT_CHAN_705000_IDX] = { 28200, 0x1, 0x75, 0x100000, 0x92E }, + [ATHOS_LUT_CHAN_705125_IDX] = { 28205, 0x1, 0x75, 0x10AAAB, 0x92E }, + [ATHOS_LUT_CHAN_705250_IDX] = { 28210, 0x1, 0x75, 0x115555, 0x92F }, + [ATHOS_LUT_CHAN_705375_IDX] = { 28215, 0x1, 0x75, 0x120000, 0x92F }, + [ATHOS_LUT_CHAN_705500_IDX] = { 28220, 0x1, 0x75, 0x12AAAB, 0x930 }, + [ATHOS_LUT_CHAN_705625_IDX] = { 28225, 0x1, 0x75, 0x135555, 0x930 }, + [ATHOS_LUT_CHAN_705750_IDX] = { 28230, 0x1, 0x75, 0x140000, 0x931 }, + [ATHOS_LUT_CHAN_705875_IDX] = { 28235, 0x1, 0x75, 0x14AAAB, 0x931 }, + [ATHOS_LUT_CHAN_706000_IDX] = { 28240, 0x1, 0x75, 0x155555, 0x931 }, + [ATHOS_LUT_CHAN_706125_IDX] = { 28245, 0x1, 0x75, 0x160000, 0x932 }, + [ATHOS_LUT_CHAN_706250_IDX] = { 28250, 0x1, 0x75, 0x16AAAB, 0x932 }, + [ATHOS_LUT_CHAN_706375_IDX] = { 28255, 0x1, 0x75, 0x175555, 0x933 }, + [ATHOS_LUT_CHAN_706500_IDX] = { 28260, 0x1, 0x75, 0x180000, 0x933 }, + [ATHOS_LUT_CHAN_706625_IDX] = { 28265, 0x1, 0x75, 0x18AAAB, 0x933 }, + [ATHOS_LUT_CHAN_706750_IDX] = { 28270, 0x1, 0x75, 0x195555, 0x934 }, + [ATHOS_LUT_CHAN_706875_IDX] = { 28275, 0x1, 0x75, 0x1A0000, 0x934 }, + [ATHOS_LUT_CHAN_707000_IDX] = { 28280, 0x1, 0x75, 0x1AAAAB, 0x935 }, + [ATHOS_LUT_CHAN_707125_IDX] = { 28285, 0x1, 0x75, 0x1B5555, 0x935 }, + [ATHOS_LUT_CHAN_707250_IDX] = { 28290, 0x1, 0x75, 0x1C0000, 0x936 }, + [ATHOS_LUT_CHAN_707375_IDX] = { 28295, 0x1, 0x75, 0x1CAAAB, 0x936 }, + [ATHOS_LUT_CHAN_707500_IDX] = { 28300, 0x1, 0x75, 0x1D5555, 0x936 }, + [ATHOS_LUT_CHAN_707625_IDX] = { 28305, 0x1, 0x75, 0x1E0000, 0x937 }, + [ATHOS_LUT_CHAN_707750_IDX] = { 28310, 0x1, 0x75, 0x1EAAAB, 0x937 }, + [ATHOS_LUT_CHAN_707875_IDX] = { 28315, 0x1, 0x75, 0x1F5555, 0x938 }, + [ATHOS_LUT_CHAN_708000_IDX] = { 28320, 0x1, 0x76, 0x0, 0x938 }, + [ATHOS_LUT_CHAN_708125_IDX] = { 28325, 0x1, 0x76, 0xAAAB, 0x938 }, + [ATHOS_LUT_CHAN_708250_IDX] = { 28330, 0x1, 0x76, 0x15555, 0x939 }, + [ATHOS_LUT_CHAN_708375_IDX] = { 28335, 0x1, 0x76, 0x20000, 0x939 }, + [ATHOS_LUT_CHAN_708500_IDX] = { 28340, 0x1, 0x76, 0x2AAAB, 0x93A }, + [ATHOS_LUT_CHAN_708625_IDX] = { 28345, 0x1, 0x76, 0x35555, 0x93A }, + [ATHOS_LUT_CHAN_708750_IDX] = { 28350, 0x1, 0x76, 0x40000, 0x93B }, + [ATHOS_LUT_CHAN_708875_IDX] = { 28355, 0x1, 0x76, 0x4AAAB, 0x93B }, + [ATHOS_LUT_CHAN_709000_IDX] = { 28360, 0x1, 0x76, 0x55555, 0x93B }, + [ATHOS_LUT_CHAN_709125_IDX] = { 28365, 0x1, 0x76, 0x60000, 0x93C }, + [ATHOS_LUT_CHAN_709250_IDX] = { 28370, 0x1, 0x76, 0x6AAAB, 0x93C }, + [ATHOS_LUT_CHAN_709375_IDX] = { 28375, 0x1, 0x76, 0x75555, 0x93D }, + [ATHOS_LUT_CHAN_709500_IDX] = { 28380, 0x1, 0x76, 0x80000, 0x93D }, + [ATHOS_LUT_CHAN_709625_IDX] = { 28385, 0x1, 0x76, 0x8AAAB, 0x93D }, + [ATHOS_LUT_CHAN_709750_IDX] = { 28390, 0x1, 0x76, 0x95555, 0x93E }, + [ATHOS_LUT_CHAN_709875_IDX] = { 28395, 0x1, 0x76, 0xA0000, 0x93E }, + [ATHOS_LUT_CHAN_710000_IDX] = { 28400, 0x1, 0x76, 0xAAAAB, 0x93F }, + [ATHOS_LUT_CHAN_710125_IDX] = { 28405, 0x1, 0x76, 0xB5555, 0x93F }, + [ATHOS_LUT_CHAN_710250_IDX] = { 28410, 0x1, 0x76, 0xC0000, 0x940 }, + [ATHOS_LUT_CHAN_710375_IDX] = { 28415, 0x1, 0x76, 0xCAAAB, 0x940 }, + [ATHOS_LUT_CHAN_710500_IDX] = { 28420, 0x1, 0x76, 0xD5555, 0x940 }, + [ATHOS_LUT_CHAN_710625_IDX] = { 28425, 0x1, 0x76, 0xE0000, 0x941 }, + [ATHOS_LUT_CHAN_710750_IDX] = { 28430, 0x1, 0x76, 0xEAAAB, 0x941 }, + [ATHOS_LUT_CHAN_710875_IDX] = { 28435, 0x1, 0x76, 0xF5555, 0x942 }, + [ATHOS_LUT_CHAN_711000_IDX] = { 28440, 0x1, 0x76, 0x100000, 0x942 }, + [ATHOS_LUT_CHAN_711125_IDX] = { 28445, 0x1, 0x76, 0x10AAAB, 0x942 }, + [ATHOS_LUT_CHAN_711250_IDX] = { 28450, 0x1, 0x76, 0x115555, 0x943 }, + [ATHOS_LUT_CHAN_711375_IDX] = { 28455, 0x1, 0x76, 0x120000, 0x943 }, + [ATHOS_LUT_CHAN_711500_IDX] = { 28460, 0x1, 0x76, 0x12AAAB, 0x944 }, + [ATHOS_LUT_CHAN_711625_IDX] = { 28465, 0x1, 0x76, 0x135555, 0x944 }, + [ATHOS_LUT_CHAN_711750_IDX] = { 28470, 0x1, 0x76, 0x140000, 0x945 }, + [ATHOS_LUT_CHAN_711875_IDX] = { 28475, 0x1, 0x76, 0x14AAAB, 0x945 }, + [ATHOS_LUT_CHAN_712000_IDX] = { 28480, 0x1, 0x76, 0x155555, 0x945 }, + [ATHOS_LUT_CHAN_712125_IDX] = { 28485, 0x1, 0x76, 0x160000, 0x946 }, + [ATHOS_LUT_CHAN_712250_IDX] = { 28490, 0x1, 0x76, 0x16AAAB, 0x946 }, + [ATHOS_LUT_CHAN_712375_IDX] = { 28495, 0x1, 0x76, 0x175555, 0x947 }, + [ATHOS_LUT_CHAN_712500_IDX] = { 28500, 0x1, 0x76, 0x180000, 0x947 }, + [ATHOS_LUT_CHAN_712625_IDX] = { 28505, 0x1, 0x76, 0x18AAAB, 0x947 }, + [ATHOS_LUT_CHAN_712750_IDX] = { 28510, 0x1, 0x76, 0x195555, 0x948 }, + [ATHOS_LUT_CHAN_712875_IDX] = { 28515, 0x1, 0x76, 0x1A0000, 0x948 }, + [ATHOS_LUT_CHAN_713000_IDX] = { 28520, 0x1, 0x76, 0x1AAAAB, 0x949 }, + [ATHOS_LUT_CHAN_713125_IDX] = { 28525, 0x1, 0x76, 0x1B5555, 0x949 }, + [ATHOS_LUT_CHAN_713250_IDX] = { 28530, 0x1, 0x76, 0x1C0000, 0x94A }, + [ATHOS_LUT_CHAN_713375_IDX] = { 28535, 0x1, 0x76, 0x1CAAAB, 0x94A }, + [ATHOS_LUT_CHAN_713500_IDX] = { 28540, 0x1, 0x76, 0x1D5555, 0x94A }, + [ATHOS_LUT_CHAN_713625_IDX] = { 28545, 0x1, 0x76, 0x1E0000, 0x94B }, + [ATHOS_LUT_CHAN_713750_IDX] = { 28550, 0x1, 0x76, 0x1EAAAB, 0x94B }, + [ATHOS_LUT_CHAN_713875_IDX] = { 28555, 0x1, 0x76, 0x1F5555, 0x94C }, + [ATHOS_LUT_CHAN_714000_IDX] = { 28560, 0x1, 0x77, 0x0, 0x94C }, + [ATHOS_LUT_CHAN_714125_IDX] = { 28565, 0x1, 0x77, 0xAAAB, 0x94C }, + [ATHOS_LUT_CHAN_714250_IDX] = { 28570, 0x1, 0x77, 0x15555, 0x94D }, + [ATHOS_LUT_CHAN_714375_IDX] = { 28575, 0x1, 0x77, 0x20000, 0x94D }, + [ATHOS_LUT_CHAN_714500_IDX] = { 28580, 0x1, 0x77, 0x2AAAB, 0x94E }, + [ATHOS_LUT_CHAN_714625_IDX] = { 28585, 0x1, 0x77, 0x35555, 0x94E }, + [ATHOS_LUT_CHAN_714750_IDX] = { 28590, 0x1, 0x77, 0x40000, 0x94F }, + [ATHOS_LUT_CHAN_714875_IDX] = { 28595, 0x1, 0x77, 0x4AAAB, 0x94F }, + [ATHOS_LUT_CHAN_715000_IDX] = { 28600, 0x1, 0x77, 0x55555, 0x94F }, + [ATHOS_LUT_CHAN_715125_IDX] = { 28605, 0x1, 0x77, 0x60000, 0x950 }, + [ATHOS_LUT_CHAN_715250_IDX] = { 28610, 0x1, 0x77, 0x6AAAB, 0x950 }, + [ATHOS_LUT_CHAN_715375_IDX] = { 28615, 0x1, 0x77, 0x75555, 0x951 }, + [ATHOS_LUT_CHAN_715500_IDX] = { 28620, 0x1, 0x77, 0x80000, 0x951 }, + [ATHOS_LUT_CHAN_715625_IDX] = { 28625, 0x1, 0x77, 0x8AAAB, 0x951 }, + [ATHOS_LUT_CHAN_715750_IDX] = { 28630, 0x1, 0x77, 0x95555, 0x952 }, + [ATHOS_LUT_CHAN_715875_IDX] = { 28635, 0x1, 0x77, 0xA0000, 0x952 }, + [ATHOS_LUT_CHAN_716000_IDX] = { 28640, 0x1, 0x77, 0xAAAAB, 0x953 }, + [ATHOS_LUT_CHAN_716125_IDX] = { 28645, 0x1, 0x77, 0xB5555, 0x953 }, + [ATHOS_LUT_CHAN_716250_IDX] = { 28650, 0x1, 0x77, 0xC0000, 0x954 }, + [ATHOS_LUT_CHAN_716375_IDX] = { 28655, 0x1, 0x77, 0xCAAAB, 0x954 }, + [ATHOS_LUT_CHAN_716500_IDX] = { 28660, 0x1, 0x77, 0xD5555, 0x954 }, + [ATHOS_LUT_CHAN_716625_IDX] = { 28665, 0x1, 0x77, 0xE0000, 0x955 }, + [ATHOS_LUT_CHAN_716750_IDX] = { 28670, 0x1, 0x77, 0xEAAAB, 0x955 }, + [ATHOS_LUT_CHAN_716875_IDX] = { 28675, 0x1, 0x77, 0xF5555, 0x956 }, + [ATHOS_LUT_CHAN_717000_IDX] = { 28680, 0x1, 0x77, 0x100000, 0x956 }, + [ATHOS_LUT_CHAN_717125_IDX] = { 28685, 0x1, 0x77, 0x10AAAB, 0x956 }, + [ATHOS_LUT_CHAN_717250_IDX] = { 28690, 0x1, 0x77, 0x115555, 0x957 }, + [ATHOS_LUT_CHAN_717375_IDX] = { 28695, 0x1, 0x77, 0x120000, 0x957 }, + [ATHOS_LUT_CHAN_717500_IDX] = { 28700, 0x1, 0x77, 0x12AAAB, 0x958 }, + [ATHOS_LUT_CHAN_717625_IDX] = { 28705, 0x1, 0x77, 0x135555, 0x958 }, + [ATHOS_LUT_CHAN_717750_IDX] = { 28710, 0x1, 0x77, 0x140000, 0x959 }, + [ATHOS_LUT_CHAN_717875_IDX] = { 28715, 0x1, 0x77, 0x14AAAB, 0x959 }, + [ATHOS_LUT_CHAN_718000_IDX] = { 28720, 0x1, 0x77, 0x155555, 0x959 }, + [ATHOS_LUT_CHAN_718125_IDX] = { 28725, 0x1, 0x77, 0x160000, 0x95A }, + [ATHOS_LUT_CHAN_718250_IDX] = { 28730, 0x1, 0x77, 0x16AAAB, 0x95A }, + [ATHOS_LUT_CHAN_718375_IDX] = { 28735, 0x1, 0x77, 0x175555, 0x95B }, + [ATHOS_LUT_CHAN_718500_IDX] = { 28740, 0x1, 0x77, 0x180000, 0x95B }, + [ATHOS_LUT_CHAN_718625_IDX] = { 28745, 0x1, 0x77, 0x18AAAB, 0x95B }, + [ATHOS_LUT_CHAN_718750_IDX] = { 28750, 0x1, 0x77, 0x195555, 0x95C }, + [ATHOS_LUT_CHAN_718875_IDX] = { 28755, 0x1, 0x77, 0x1A0000, 0x95C }, + [ATHOS_LUT_CHAN_719000_IDX] = { 28760, 0x1, 0x77, 0x1AAAAB, 0x95D }, + [ATHOS_LUT_CHAN_719125_IDX] = { 28765, 0x1, 0x77, 0x1B5555, 0x95D }, + [ATHOS_LUT_CHAN_719250_IDX] = { 28770, 0x1, 0x77, 0x1C0000, 0x95E }, + [ATHOS_LUT_CHAN_719375_IDX] = { 28775, 0x1, 0x77, 0x1CAAAB, 0x95E }, + [ATHOS_LUT_CHAN_719500_IDX] = { 28780, 0x1, 0x77, 0x1D5555, 0x95E }, + [ATHOS_LUT_CHAN_719625_IDX] = { 28785, 0x1, 0x77, 0x1E0000, 0x95F }, + [ATHOS_LUT_CHAN_719750_IDX] = { 28790, 0x1, 0x77, 0x1EAAAB, 0x95F }, + [ATHOS_LUT_CHAN_719875_IDX] = { 28795, 0x1, 0x77, 0x1F5555, 0x960 }, + [ATHOS_LUT_CHAN_720000_IDX] = { 28800, 0x1, 0x78, 0x0, 0x960 }, + [ATHOS_LUT_CHAN_720125_IDX] = { 28805, 0x1, 0x78, 0xAAAB, 0x960 }, + [ATHOS_LUT_CHAN_720250_IDX] = { 28810, 0x1, 0x78, 0x15555, 0x961 }, + [ATHOS_LUT_CHAN_720375_IDX] = { 28815, 0x1, 0x78, 0x20000, 0x961 }, + [ATHOS_LUT_CHAN_720500_IDX] = { 28820, 0x1, 0x78, 0x2AAAB, 0x962 }, + [ATHOS_LUT_CHAN_720625_IDX] = { 28825, 0x1, 0x78, 0x35555, 0x962 }, + [ATHOS_LUT_CHAN_720750_IDX] = { 28830, 0x1, 0x78, 0x40000, 0x963 }, + [ATHOS_LUT_CHAN_720875_IDX] = { 28835, 0x1, 0x78, 0x4AAAB, 0x963 }, + [ATHOS_LUT_CHAN_721000_IDX] = { 28840, 0x1, 0x78, 0x55555, 0x963 }, + [ATHOS_LUT_CHAN_721125_IDX] = { 28845, 0x1, 0x78, 0x60000, 0x964 }, + [ATHOS_LUT_CHAN_721250_IDX] = { 28850, 0x1, 0x78, 0x6AAAB, 0x964 }, + [ATHOS_LUT_CHAN_721375_IDX] = { 28855, 0x1, 0x78, 0x75555, 0x965 }, + [ATHOS_LUT_CHAN_721500_IDX] = { 28860, 0x1, 0x78, 0x80000, 0x965 } +}; + +const struct athos_lut_line athos_lut_6g_60_mhz[ATHOS_LUT_CHAN_6G_MAX] = { + [ATHOS_LUT_CHAN_593000_IDX] = { 23720, 0x0, 0x41, 0x1C71C7, 0x7B9 }, + [ATHOS_LUT_CHAN_593125_IDX] = { 23725, 0x0, 0x41, 0x1CE38E, 0x7B9 }, + [ATHOS_LUT_CHAN_593250_IDX] = { 23730, 0x0, 0x41, 0x1D5555, 0x7BA }, + [ATHOS_LUT_CHAN_593375_IDX] = { 23735, 0x0, 0x41, 0x1DC71C, 0x7BA }, + [ATHOS_LUT_CHAN_593500_IDX] = { 23740, 0x0, 0x41, 0x1E38E4, 0x7BA }, + [ATHOS_LUT_CHAN_593625_IDX] = { 23745, 0x0, 0x41, 0x1EAAAB, 0x7BB }, + [ATHOS_LUT_CHAN_593750_IDX] = { 23750, 0x0, 0x41, 0x1F1C72, 0x7BB }, + [ATHOS_LUT_CHAN_593875_IDX] = { 23755, 0x0, 0x41, 0x1F8E39, 0x7BC }, + [ATHOS_LUT_CHAN_594000_IDX] = { 23760, 0x0, 0x42, 0x0, 0x7BC }, + [ATHOS_LUT_CHAN_594125_IDX] = { 23765, 0x0, 0x42, 0x71C7, 0x7BC }, + [ATHOS_LUT_CHAN_594250_IDX] = { 23770, 0x0, 0x42, 0xE38E, 0x7BD }, + [ATHOS_LUT_CHAN_594375_IDX] = { 23775, 0x0, 0x42, 0x15555, 0x7BD }, + [ATHOS_LUT_CHAN_594500_IDX] = { 23780, 0x0, 0x42, 0x1C71C, 0x7BE }, + [ATHOS_LUT_CHAN_594625_IDX] = { 23785, 0x0, 0x42, 0x238E4, 0x7BE }, + [ATHOS_LUT_CHAN_594750_IDX] = { 23790, 0x0, 0x42, 0x2AAAB, 0x7BF }, + [ATHOS_LUT_CHAN_594875_IDX] = { 23795, 0x0, 0x42, 0x31C72, 0x7BF }, + [ATHOS_LUT_CHAN_595000_IDX] = { 23800, 0x0, 0x42, 0x38E39, 0x7BF }, + [ATHOS_LUT_CHAN_595125_IDX] = { 23805, 0x0, 0x42, 0x40000, 0x7C0 }, + [ATHOS_LUT_CHAN_595250_IDX] = { 23810, 0x0, 0x42, 0x471C7, 0x7C0 }, + [ATHOS_LUT_CHAN_595375_IDX] = { 23815, 0x0, 0x42, 0x4E38E, 0x7C1 }, + [ATHOS_LUT_CHAN_595500_IDX] = { 23820, 0x0, 0x42, 0x55555, 0x7C1 }, + [ATHOS_LUT_CHAN_595625_IDX] = { 23825, 0x0, 0x42, 0x5C71C, 0x7C1 }, + [ATHOS_LUT_CHAN_595750_IDX] = { 23830, 0x0, 0x42, 0x638E4, 0x7C2 }, + [ATHOS_LUT_CHAN_595875_IDX] = { 23835, 0x0, 0x42, 0x6AAAB, 0x7C2 }, + [ATHOS_LUT_CHAN_596000_IDX] = { 23840, 0x0, 0x42, 0x71C72, 0x7C3 }, + [ATHOS_LUT_CHAN_596125_IDX] = { 23845, 0x0, 0x42, 0x78E39, 0x7C3 }, + [ATHOS_LUT_CHAN_596250_IDX] = { 23850, 0x0, 0x42, 0x80000, 0x7C4 }, + [ATHOS_LUT_CHAN_596375_IDX] = { 23855, 0x0, 0x42, 0x871C7, 0x7C4 }, + [ATHOS_LUT_CHAN_596500_IDX] = { 23860, 0x0, 0x42, 0x8E38E, 0x7C4 }, + [ATHOS_LUT_CHAN_596625_IDX] = { 23865, 0x0, 0x42, 0x95555, 0x7C5 }, + [ATHOS_LUT_CHAN_596750_IDX] = { 23870, 0x0, 0x42, 0x9C71C, 0x7C5 }, + [ATHOS_LUT_CHAN_596875_IDX] = { 23875, 0x0, 0x42, 0xA38E4, 0x7C6 }, + [ATHOS_LUT_CHAN_597000_IDX] = { 23880, 0x0, 0x42, 0xAAAAB, 0x7C6 }, + [ATHOS_LUT_CHAN_597125_IDX] = { 23885, 0x0, 0x42, 0xB1C72, 0x7C6 }, + [ATHOS_LUT_CHAN_597250_IDX] = { 23890, 0x0, 0x42, 0xB8E39, 0x7C7 }, + [ATHOS_LUT_CHAN_597375_IDX] = { 23895, 0x0, 0x42, 0xC0000, 0x7C7 }, + [ATHOS_LUT_CHAN_597500_IDX] = { 23900, 0x0, 0x42, 0xC71C7, 0x7C8 }, + [ATHOS_LUT_CHAN_597625_IDX] = { 23905, 0x0, 0x42, 0xCE38E, 0x7C8 }, + [ATHOS_LUT_CHAN_597750_IDX] = { 23910, 0x0, 0x42, 0xD5555, 0x7C9 }, + [ATHOS_LUT_CHAN_597875_IDX] = { 23915, 0x0, 0x42, 0xDC71C, 0x7C9 }, + [ATHOS_LUT_CHAN_598000_IDX] = { 23920, 0x0, 0x42, 0xE38E4, 0x7C9 }, + [ATHOS_LUT_CHAN_598125_IDX] = { 23925, 0x0, 0x42, 0xEAAAB, 0x7CA }, + [ATHOS_LUT_CHAN_598250_IDX] = { 23930, 0x0, 0x42, 0xF1C72, 0x7CA }, + [ATHOS_LUT_CHAN_598375_IDX] = { 23935, 0x0, 0x42, 0xF8E39, 0x7CB }, + [ATHOS_LUT_CHAN_598500_IDX] = { 23940, 0x0, 0x42, 0x100000, 0x7CB }, + [ATHOS_LUT_CHAN_598625_IDX] = { 23945, 0x0, 0x42, 0x1071C7, 0x7CB }, + [ATHOS_LUT_CHAN_598750_IDX] = { 23950, 0x0, 0x42, 0x10E38E, 0x7CC }, + [ATHOS_LUT_CHAN_598875_IDX] = { 23955, 0x0, 0x42, 0x115555, 0x7CC }, + [ATHOS_LUT_CHAN_599000_IDX] = { 23960, 0x0, 0x42, 0x11C71C, 0x7CD }, + [ATHOS_LUT_CHAN_599125_IDX] = { 23965, 0x0, 0x42, 0x1238E4, 0x7CD }, + [ATHOS_LUT_CHAN_599250_IDX] = { 23970, 0x0, 0x42, 0x12AAAB, 0x7CE }, + [ATHOS_LUT_CHAN_599375_IDX] = { 23975, 0x0, 0x42, 0x131C72, 0x7CE }, + [ATHOS_LUT_CHAN_599500_IDX] = { 23980, 0x0, 0x42, 0x138E39, 0x7CE }, + [ATHOS_LUT_CHAN_599625_IDX] = { 23985, 0x0, 0x42, 0x140000, 0x7CF }, + [ATHOS_LUT_CHAN_599750_IDX] = { 23990, 0x0, 0x42, 0x1471C7, 0x7CF }, + [ATHOS_LUT_CHAN_599875_IDX] = { 23995, 0x0, 0x42, 0x14E38E, 0x7D0 }, + [ATHOS_LUT_CHAN_600000_IDX] = { 24000, 0x0, 0x42, 0x155555, 0x7D0 }, + [ATHOS_LUT_CHAN_600125_IDX] = { 24005, 0x0, 0x42, 0x15C71C, 0x7D0 }, + [ATHOS_LUT_CHAN_600250_IDX] = { 24010, 0x0, 0x42, 0x1638E4, 0x7D1 }, + [ATHOS_LUT_CHAN_600375_IDX] = { 24015, 0x0, 0x42, 0x16AAAB, 0x7D1 }, + [ATHOS_LUT_CHAN_600500_IDX] = { 24020, 0x0, 0x42, 0x171C72, 0x7D2 }, + [ATHOS_LUT_CHAN_600625_IDX] = { 24025, 0x0, 0x42, 0x178E39, 0x7D2 }, + [ATHOS_LUT_CHAN_600750_IDX] = { 24030, 0x0, 0x42, 0x180000, 0x7D3 }, + [ATHOS_LUT_CHAN_600875_IDX] = { 24035, 0x0, 0x42, 0x1871C7, 0x7D3 }, + [ATHOS_LUT_CHAN_601000_IDX] = { 24040, 0x0, 0x42, 0x18E38E, 0x7D3 }, + [ATHOS_LUT_CHAN_601125_IDX] = { 24045, 0x0, 0x42, 0x195555, 0x7D4 }, + [ATHOS_LUT_CHAN_601250_IDX] = { 24050, 0x0, 0x42, 0x19C71C, 0x7D4 }, + [ATHOS_LUT_CHAN_601375_IDX] = { 24055, 0x0, 0x42, 0x1A38E4, 0x7D5 }, + [ATHOS_LUT_CHAN_601500_IDX] = { 24060, 0x0, 0x42, 0x1AAAAB, 0x7D5 }, + [ATHOS_LUT_CHAN_601625_IDX] = { 24065, 0x0, 0x42, 0x1B1C72, 0x7D5 }, + [ATHOS_LUT_CHAN_601750_IDX] = { 24070, 0x0, 0x42, 0x1B8E39, 0x7D6 }, + [ATHOS_LUT_CHAN_601875_IDX] = { 24075, 0x0, 0x42, 0x1C0000, 0x7D6 }, + [ATHOS_LUT_CHAN_602000_IDX] = { 24080, 0x0, 0x42, 0x1C71C7, 0x7D7 }, + [ATHOS_LUT_CHAN_602125_IDX] = { 24085, 0x0, 0x42, 0x1CE38E, 0x7D7 }, + [ATHOS_LUT_CHAN_602250_IDX] = { 24090, 0x0, 0x42, 0x1D5555, 0x7D8 }, + [ATHOS_LUT_CHAN_602375_IDX] = { 24095, 0x0, 0x42, 0x1DC71C, 0x7D8 }, + [ATHOS_LUT_CHAN_602500_IDX] = { 24100, 0x0, 0x42, 0x1E38E4, 0x7D8 }, + [ATHOS_LUT_CHAN_602625_IDX] = { 24105, 0x0, 0x42, 0x1EAAAB, 0x7D9 }, + [ATHOS_LUT_CHAN_602750_IDX] = { 24110, 0x0, 0x42, 0x1F1C72, 0x7D9 }, + [ATHOS_LUT_CHAN_602875_IDX] = { 24115, 0x0, 0x42, 0x1F8E39, 0x7DA }, + [ATHOS_LUT_CHAN_603000_IDX] = { 24120, 0x0, 0x43, 0x0, 0x7DA }, + [ATHOS_LUT_CHAN_603125_IDX] = { 24125, 0x0, 0x43, 0x71C7, 0x7DA }, + [ATHOS_LUT_CHAN_603250_IDX] = { 24130, 0x0, 0x43, 0xE38E, 0x7DB }, + [ATHOS_LUT_CHAN_603375_IDX] = { 24135, 0x0, 0x43, 0x15555, 0x7DB }, + [ATHOS_LUT_CHAN_603500_IDX] = { 24140, 0x0, 0x43, 0x1C71C, 0x7DC }, + [ATHOS_LUT_CHAN_603625_IDX] = { 24145, 0x0, 0x43, 0x238E4, 0x7DC }, + [ATHOS_LUT_CHAN_603750_IDX] = { 24150, 0x0, 0x43, 0x2AAAB, 0x7DD }, + [ATHOS_LUT_CHAN_603875_IDX] = { 24155, 0x0, 0x43, 0x31C72, 0x7DD }, + [ATHOS_LUT_CHAN_604000_IDX] = { 24160, 0x0, 0x43, 0x38E39, 0x7DD }, + [ATHOS_LUT_CHAN_604125_IDX] = { 24165, 0x0, 0x43, 0x40000, 0x7DE }, + [ATHOS_LUT_CHAN_604250_IDX] = { 24170, 0x0, 0x43, 0x471C7, 0x7DE }, + [ATHOS_LUT_CHAN_604375_IDX] = { 24175, 0x0, 0x43, 0x4E38E, 0x7DF }, + [ATHOS_LUT_CHAN_604500_IDX] = { 24180, 0x0, 0x43, 0x55555, 0x7DF }, + [ATHOS_LUT_CHAN_604625_IDX] = { 24185, 0x0, 0x43, 0x5C71C, 0x7DF }, + [ATHOS_LUT_CHAN_604750_IDX] = { 24190, 0x0, 0x43, 0x638E4, 0x7E0 }, + [ATHOS_LUT_CHAN_604875_IDX] = { 24195, 0x0, 0x43, 0x6AAAB, 0x7E0 }, + [ATHOS_LUT_CHAN_605000_IDX] = { 24200, 0x0, 0x43, 0x71C72, 0x7E1 }, + [ATHOS_LUT_CHAN_605125_IDX] = { 24205, 0x0, 0x43, 0x78E39, 0x7E1 }, + [ATHOS_LUT_CHAN_605250_IDX] = { 24210, 0x0, 0x43, 0x80000, 0x7E2 }, + [ATHOS_LUT_CHAN_605375_IDX] = { 24215, 0x0, 0x43, 0x871C7, 0x7E2 }, + [ATHOS_LUT_CHAN_605500_IDX] = { 24220, 0x0, 0x43, 0x8E38E, 0x7E2 }, + [ATHOS_LUT_CHAN_605625_IDX] = { 24225, 0x0, 0x43, 0x95555, 0x7E3 }, + [ATHOS_LUT_CHAN_605750_IDX] = { 24230, 0x0, 0x43, 0x9C71C, 0x7E3 }, + [ATHOS_LUT_CHAN_605875_IDX] = { 24235, 0x0, 0x43, 0xA38E4, 0x7E4 }, + [ATHOS_LUT_CHAN_606000_IDX] = { 24240, 0x0, 0x43, 0xAAAAB, 0x7E4 }, + [ATHOS_LUT_CHAN_606125_IDX] = { 24245, 0x0, 0x43, 0xB1C72, 0x7E4 }, + [ATHOS_LUT_CHAN_606250_IDX] = { 24250, 0x0, 0x43, 0xB8E39, 0x7E5 }, + [ATHOS_LUT_CHAN_606375_IDX] = { 24255, 0x0, 0x43, 0xC0000, 0x7E5 }, + [ATHOS_LUT_CHAN_606500_IDX] = { 24260, 0x0, 0x43, 0xC71C7, 0x7E6 }, + [ATHOS_LUT_CHAN_606625_IDX] = { 24265, 0x0, 0x43, 0xCE38E, 0x7E6 }, + [ATHOS_LUT_CHAN_606750_IDX] = { 24270, 0x0, 0x43, 0xD5555, 0x7E7 }, + [ATHOS_LUT_CHAN_606875_IDX] = { 24275, 0x0, 0x43, 0xDC71C, 0x7E7 }, + [ATHOS_LUT_CHAN_607000_IDX] = { 24280, 0x0, 0x43, 0xE38E4, 0x7E7 }, + [ATHOS_LUT_CHAN_607125_IDX] = { 24285, 0x0, 0x43, 0xEAAAB, 0x7E8 }, + [ATHOS_LUT_CHAN_607250_IDX] = { 24290, 0x0, 0x43, 0xF1C72, 0x7E8 }, + [ATHOS_LUT_CHAN_607375_IDX] = { 24295, 0x0, 0x43, 0xF8E39, 0x7E9 }, + [ATHOS_LUT_CHAN_607500_IDX] = { 24300, 0x0, 0x43, 0x100000, 0x7E9 }, + [ATHOS_LUT_CHAN_607625_IDX] = { 24305, 0x0, 0x43, 0x1071C7, 0x7E9 }, + [ATHOS_LUT_CHAN_607750_IDX] = { 24310, 0x0, 0x43, 0x10E38E, 0x7EA }, + [ATHOS_LUT_CHAN_607875_IDX] = { 24315, 0x0, 0x43, 0x115555, 0x7EA }, + [ATHOS_LUT_CHAN_608000_IDX] = { 24320, 0x0, 0x43, 0x11C71C, 0x7EB }, + [ATHOS_LUT_CHAN_608125_IDX] = { 24325, 0x0, 0x43, 0x1238E4, 0x7EB }, + [ATHOS_LUT_CHAN_608250_IDX] = { 24330, 0x0, 0x43, 0x12AAAB, 0x7EC }, + [ATHOS_LUT_CHAN_608375_IDX] = { 24335, 0x0, 0x43, 0x131C72, 0x7EC }, + [ATHOS_LUT_CHAN_608500_IDX] = { 24340, 0x0, 0x43, 0x138E39, 0x7EC }, + [ATHOS_LUT_CHAN_608625_IDX] = { 24345, 0x0, 0x43, 0x140000, 0x7ED }, + [ATHOS_LUT_CHAN_608750_IDX] = { 24350, 0x0, 0x43, 0x1471C7, 0x7ED }, + [ATHOS_LUT_CHAN_608875_IDX] = { 24355, 0x0, 0x43, 0x14E38E, 0x7EE }, + [ATHOS_LUT_CHAN_609000_IDX] = { 24360, 0x0, 0x43, 0x155555, 0x7EE }, + [ATHOS_LUT_CHAN_609125_IDX] = { 24365, 0x0, 0x43, 0x15C71C, 0x7EE }, + [ATHOS_LUT_CHAN_609250_IDX] = { 24370, 0x0, 0x43, 0x1638E4, 0x7EF }, + [ATHOS_LUT_CHAN_609375_IDX] = { 24375, 0x0, 0x43, 0x16AAAB, 0x7EF }, + [ATHOS_LUT_CHAN_609500_IDX] = { 24380, 0x0, 0x43, 0x171C72, 0x7F0 }, + [ATHOS_LUT_CHAN_609625_IDX] = { 24385, 0x0, 0x43, 0x178E39, 0x7F0 }, + [ATHOS_LUT_CHAN_609750_IDX] = { 24390, 0x0, 0x43, 0x180000, 0x7F1 }, + [ATHOS_LUT_CHAN_609875_IDX] = { 24395, 0x0, 0x43, 0x1871C7, 0x7F1 }, + [ATHOS_LUT_CHAN_610000_IDX] = { 24400, 0x1, 0x43, 0x18E38E, 0x7F1 }, + [ATHOS_LUT_CHAN_610125_IDX] = { 24405, 0x1, 0x43, 0x195555, 0x7F2 }, + [ATHOS_LUT_CHAN_610250_IDX] = { 24410, 0x1, 0x43, 0x19C71C, 0x7F2 }, + [ATHOS_LUT_CHAN_610375_IDX] = { 24415, 0x1, 0x43, 0x1A38E4, 0x7F3 }, + [ATHOS_LUT_CHAN_610500_IDX] = { 24420, 0x1, 0x43, 0x1AAAAB, 0x7F3 }, + [ATHOS_LUT_CHAN_610625_IDX] = { 24425, 0x1, 0x43, 0x1B1C72, 0x7F3 }, + [ATHOS_LUT_CHAN_610750_IDX] = { 24430, 0x1, 0x43, 0x1B8E39, 0x7F4 }, + [ATHOS_LUT_CHAN_610875_IDX] = { 24435, 0x1, 0x43, 0x1C0000, 0x7F4 }, + [ATHOS_LUT_CHAN_611000_IDX] = { 24440, 0x1, 0x43, 0x1C71C7, 0x7F5 }, + [ATHOS_LUT_CHAN_611125_IDX] = { 24445, 0x1, 0x43, 0x1CE38E, 0x7F5 }, + [ATHOS_LUT_CHAN_611250_IDX] = { 24450, 0x1, 0x43, 0x1D5555, 0x7F6 }, + [ATHOS_LUT_CHAN_611375_IDX] = { 24455, 0x1, 0x43, 0x1DC71C, 0x7F6 }, + [ATHOS_LUT_CHAN_611500_IDX] = { 24460, 0x1, 0x43, 0x1E38E4, 0x7F6 }, + [ATHOS_LUT_CHAN_611625_IDX] = { 24465, 0x1, 0x43, 0x1EAAAB, 0x7F7 }, + [ATHOS_LUT_CHAN_611750_IDX] = { 24470, 0x1, 0x43, 0x1F1C72, 0x7F7 }, + [ATHOS_LUT_CHAN_611875_IDX] = { 24475, 0x1, 0x43, 0x1F8E39, 0x7F8 }, + [ATHOS_LUT_CHAN_612000_IDX] = { 24480, 0x1, 0x44, 0x0, 0x7F8 }, + [ATHOS_LUT_CHAN_612125_IDX] = { 24485, 0x1, 0x44, 0x71C7, 0x7F8 }, + [ATHOS_LUT_CHAN_612250_IDX] = { 24490, 0x1, 0x44, 0xE38E, 0x7F9 }, + [ATHOS_LUT_CHAN_612375_IDX] = { 24495, 0x1, 0x44, 0x15555, 0x7F9 }, + [ATHOS_LUT_CHAN_612500_IDX] = { 24500, 0x1, 0x44, 0x1C71C, 0x7FA }, + [ATHOS_LUT_CHAN_612625_IDX] = { 24505, 0x1, 0x44, 0x238E4, 0x7FA }, + [ATHOS_LUT_CHAN_612750_IDX] = { 24510, 0x1, 0x44, 0x2AAAB, 0x7FB }, + [ATHOS_LUT_CHAN_612875_IDX] = { 24515, 0x1, 0x44, 0x31C72, 0x7FB }, + [ATHOS_LUT_CHAN_613000_IDX] = { 24520, 0x1, 0x44, 0x38E39, 0x7FB }, + [ATHOS_LUT_CHAN_613125_IDX] = { 24525, 0x1, 0x44, 0x40000, 0x7FC }, + [ATHOS_LUT_CHAN_613250_IDX] = { 24530, 0x1, 0x44, 0x471C7, 0x7FC }, + [ATHOS_LUT_CHAN_613375_IDX] = { 24535, 0x1, 0x44, 0x4E38E, 0x7FD }, + [ATHOS_LUT_CHAN_613500_IDX] = { 24540, 0x1, 0x44, 0x55555, 0x7FD }, + [ATHOS_LUT_CHAN_613625_IDX] = { 24545, 0x1, 0x44, 0x5C71C, 0x7FD }, + [ATHOS_LUT_CHAN_613750_IDX] = { 24550, 0x1, 0x44, 0x638E4, 0x7FE }, + [ATHOS_LUT_CHAN_613875_IDX] = { 24555, 0x1, 0x44, 0x6AAAB, 0x7FE }, + [ATHOS_LUT_CHAN_614000_IDX] = { 24560, 0x1, 0x44, 0x71C72, 0x7FF }, + [ATHOS_LUT_CHAN_614125_IDX] = { 24565, 0x1, 0x44, 0x78E39, 0x7FF }, + [ATHOS_LUT_CHAN_614250_IDX] = { 24570, 0x1, 0x44, 0x80000, 0x800 }, + [ATHOS_LUT_CHAN_614375_IDX] = { 24575, 0x1, 0x44, 0x871C7, 0x800 }, + [ATHOS_LUT_CHAN_614500_IDX] = { 24580, 0x1, 0x44, 0x8E38E, 0x800 }, + [ATHOS_LUT_CHAN_614625_IDX] = { 24585, 0x1, 0x44, 0x95555, 0x801 }, + [ATHOS_LUT_CHAN_614750_IDX] = { 24590, 0x1, 0x44, 0x9C71C, 0x801 }, + [ATHOS_LUT_CHAN_614875_IDX] = { 24595, 0x1, 0x44, 0xA38E4, 0x802 }, + [ATHOS_LUT_CHAN_615000_IDX] = { 24600, 0x1, 0x44, 0xAAAAB, 0x802 }, + [ATHOS_LUT_CHAN_615125_IDX] = { 24605, 0x1, 0x44, 0xB1C72, 0x802 }, + [ATHOS_LUT_CHAN_615250_IDX] = { 24610, 0x1, 0x44, 0xB8E39, 0x803 }, + [ATHOS_LUT_CHAN_615375_IDX] = { 24615, 0x1, 0x44, 0xC0000, 0x803 }, + [ATHOS_LUT_CHAN_615500_IDX] = { 24620, 0x1, 0x44, 0xC71C7, 0x804 }, + [ATHOS_LUT_CHAN_615625_IDX] = { 24625, 0x1, 0x44, 0xCE38E, 0x804 }, + [ATHOS_LUT_CHAN_615750_IDX] = { 24630, 0x1, 0x44, 0xD5555, 0x805 }, + [ATHOS_LUT_CHAN_615875_IDX] = { 24635, 0x1, 0x44, 0xDC71C, 0x805 }, + [ATHOS_LUT_CHAN_616000_IDX] = { 24640, 0x1, 0x44, 0xE38E4, 0x805 }, + [ATHOS_LUT_CHAN_616125_IDX] = { 24645, 0x1, 0x44, 0xEAAAB, 0x806 }, + [ATHOS_LUT_CHAN_616250_IDX] = { 24650, 0x1, 0x44, 0xF1C72, 0x806 }, + [ATHOS_LUT_CHAN_616375_IDX] = { 24655, 0x1, 0x44, 0xF8E39, 0x807 }, + [ATHOS_LUT_CHAN_616500_IDX] = { 24660, 0x1, 0x44, 0x100000, 0x807 }, + [ATHOS_LUT_CHAN_616625_IDX] = { 24665, 0x1, 0x44, 0x1071C7, 0x807 }, + [ATHOS_LUT_CHAN_616750_IDX] = { 24670, 0x1, 0x44, 0x10E38E, 0x808 }, + [ATHOS_LUT_CHAN_616875_IDX] = { 24675, 0x1, 0x44, 0x115555, 0x808 }, + [ATHOS_LUT_CHAN_617000_IDX] = { 24680, 0x1, 0x44, 0x11C71C, 0x809 }, + [ATHOS_LUT_CHAN_617125_IDX] = { 24685, 0x1, 0x44, 0x1238E4, 0x809 }, + [ATHOS_LUT_CHAN_617250_IDX] = { 24690, 0x1, 0x44, 0x12AAAB, 0x80A }, + [ATHOS_LUT_CHAN_617375_IDX] = { 24695, 0x1, 0x44, 0x131C72, 0x80A }, + [ATHOS_LUT_CHAN_617500_IDX] = { 24700, 0x1, 0x44, 0x138E39, 0x80A }, + [ATHOS_LUT_CHAN_617625_IDX] = { 24705, 0x1, 0x44, 0x140000, 0x80B }, + [ATHOS_LUT_CHAN_617750_IDX] = { 24710, 0x1, 0x44, 0x1471C7, 0x80B }, + [ATHOS_LUT_CHAN_617875_IDX] = { 24715, 0x1, 0x44, 0x14E38E, 0x80C }, + [ATHOS_LUT_CHAN_618000_IDX] = { 24720, 0x1, 0x44, 0x155555, 0x80C }, + [ATHOS_LUT_CHAN_618125_IDX] = { 24725, 0x1, 0x44, 0x15C71C, 0x80C }, + [ATHOS_LUT_CHAN_618250_IDX] = { 24730, 0x1, 0x44, 0x1638E4, 0x80D }, + [ATHOS_LUT_CHAN_618375_IDX] = { 24735, 0x1, 0x44, 0x16AAAB, 0x80D }, + [ATHOS_LUT_CHAN_618500_IDX] = { 24740, 0x1, 0x44, 0x171C72, 0x80E }, + [ATHOS_LUT_CHAN_618625_IDX] = { 24745, 0x1, 0x44, 0x178E39, 0x80E }, + [ATHOS_LUT_CHAN_618750_IDX] = { 24750, 0x1, 0x44, 0x180000, 0x80F }, + [ATHOS_LUT_CHAN_618875_IDX] = { 24755, 0x1, 0x44, 0x1871C7, 0x80F }, + [ATHOS_LUT_CHAN_619000_IDX] = { 24760, 0x1, 0x44, 0x18E38E, 0x80F }, + [ATHOS_LUT_CHAN_619125_IDX] = { 24765, 0x1, 0x44, 0x195555, 0x810 }, + [ATHOS_LUT_CHAN_619250_IDX] = { 24770, 0x1, 0x44, 0x19C71C, 0x810 }, + [ATHOS_LUT_CHAN_619375_IDX] = { 24775, 0x1, 0x44, 0x1A38E4, 0x811 }, + [ATHOS_LUT_CHAN_619500_IDX] = { 24780, 0x1, 0x44, 0x1AAAAB, 0x811 }, + [ATHOS_LUT_CHAN_619625_IDX] = { 24785, 0x1, 0x44, 0x1B1C72, 0x811 }, + [ATHOS_LUT_CHAN_619750_IDX] = { 24790, 0x1, 0x44, 0x1B8E39, 0x812 }, + [ATHOS_LUT_CHAN_619875_IDX] = { 24795, 0x1, 0x44, 0x1C0000, 0x812 }, + [ATHOS_LUT_CHAN_620000_IDX] = { 24800, 0x1, 0x44, 0x1C71C7, 0x813 }, + [ATHOS_LUT_CHAN_620125_IDX] = { 24805, 0x1, 0x44, 0x1CE38E, 0x813 }, + [ATHOS_LUT_CHAN_620250_IDX] = { 24810, 0x1, 0x44, 0x1D5555, 0x814 }, + [ATHOS_LUT_CHAN_620375_IDX] = { 24815, 0x1, 0x44, 0x1DC71C, 0x814 }, + [ATHOS_LUT_CHAN_620500_IDX] = { 24820, 0x1, 0x44, 0x1E38E4, 0x814 }, + [ATHOS_LUT_CHAN_620625_IDX] = { 24825, 0x1, 0x44, 0x1EAAAB, 0x815 }, + [ATHOS_LUT_CHAN_620750_IDX] = { 24830, 0x1, 0x44, 0x1F1C72, 0x815 }, + [ATHOS_LUT_CHAN_620875_IDX] = { 24835, 0x1, 0x44, 0x1F8E39, 0x816 }, + [ATHOS_LUT_CHAN_621000_IDX] = { 24840, 0x1, 0x45, 0x0, 0x816 }, + [ATHOS_LUT_CHAN_621125_IDX] = { 24845, 0x1, 0x45, 0x71C7, 0x816 }, + [ATHOS_LUT_CHAN_621250_IDX] = { 24850, 0x1, 0x45, 0xE38E, 0x817 }, + [ATHOS_LUT_CHAN_621375_IDX] = { 24855, 0x1, 0x45, 0x15555, 0x817 }, + [ATHOS_LUT_CHAN_621500_IDX] = { 24860, 0x1, 0x45, 0x1C71C, 0x818 }, + [ATHOS_LUT_CHAN_621625_IDX] = { 24865, 0x1, 0x45, 0x238E4, 0x818 }, + [ATHOS_LUT_CHAN_621750_IDX] = { 24870, 0x1, 0x45, 0x2AAAB, 0x819 }, + [ATHOS_LUT_CHAN_621875_IDX] = { 24875, 0x1, 0x45, 0x31C72, 0x819 }, + [ATHOS_LUT_CHAN_622000_IDX] = { 24880, 0x1, 0x45, 0x38E39, 0x819 }, + [ATHOS_LUT_CHAN_622125_IDX] = { 24885, 0x1, 0x45, 0x40000, 0x81A }, + [ATHOS_LUT_CHAN_622250_IDX] = { 24890, 0x1, 0x45, 0x471C7, 0x81A }, + [ATHOS_LUT_CHAN_622375_IDX] = { 24895, 0x1, 0x45, 0x4E38E, 0x81B }, + [ATHOS_LUT_CHAN_622500_IDX] = { 24900, 0x1, 0x45, 0x55555, 0x81B }, + [ATHOS_LUT_CHAN_622625_IDX] = { 24905, 0x1, 0x45, 0x5C71C, 0x81B }, + [ATHOS_LUT_CHAN_622750_IDX] = { 24910, 0x1, 0x45, 0x638E4, 0x81C }, + [ATHOS_LUT_CHAN_622875_IDX] = { 24915, 0x1, 0x45, 0x6AAAB, 0x81C }, + [ATHOS_LUT_CHAN_623000_IDX] = { 24920, 0x1, 0x45, 0x71C72, 0x81D }, + [ATHOS_LUT_CHAN_623125_IDX] = { 24925, 0x1, 0x45, 0x78E39, 0x81D }, + [ATHOS_LUT_CHAN_623250_IDX] = { 24930, 0x1, 0x45, 0x80000, 0x81E }, + [ATHOS_LUT_CHAN_623375_IDX] = { 24935, 0x1, 0x45, 0x871C7, 0x81E }, + [ATHOS_LUT_CHAN_623500_IDX] = { 24940, 0x1, 0x45, 0x8E38E, 0x81E }, + [ATHOS_LUT_CHAN_623625_IDX] = { 24945, 0x1, 0x45, 0x95555, 0x81F }, + [ATHOS_LUT_CHAN_623750_IDX] = { 24950, 0x1, 0x45, 0x9C71C, 0x81F }, + [ATHOS_LUT_CHAN_623875_IDX] = { 24955, 0x1, 0x45, 0xA38E4, 0x820 }, + [ATHOS_LUT_CHAN_624000_IDX] = { 24960, 0x1, 0x45, 0xAAAAB, 0x820 }, + [ATHOS_LUT_CHAN_624125_IDX] = { 24965, 0x1, 0x45, 0xB1C72, 0x820 }, + [ATHOS_LUT_CHAN_624250_IDX] = { 24970, 0x1, 0x45, 0xB8E39, 0x821 }, + [ATHOS_LUT_CHAN_624375_IDX] = { 24975, 0x1, 0x45, 0xC0000, 0x821 }, + [ATHOS_LUT_CHAN_624500_IDX] = { 24980, 0x1, 0x45, 0xC71C7, 0x822 }, + [ATHOS_LUT_CHAN_624625_IDX] = { 24985, 0x1, 0x45, 0xCE38E, 0x822 }, + [ATHOS_LUT_CHAN_624750_IDX] = { 24990, 0x1, 0x45, 0xD5555, 0x823 }, + [ATHOS_LUT_CHAN_624875_IDX] = { 24995, 0x1, 0x45, 0xDC71C, 0x823 }, + [ATHOS_LUT_CHAN_625000_IDX] = { 25000, 0x1, 0x45, 0xE38E4, 0x823 }, + [ATHOS_LUT_CHAN_625125_IDX] = { 25005, 0x1, 0x45, 0xEAAAB, 0x824 }, + [ATHOS_LUT_CHAN_625250_IDX] = { 25010, 0x1, 0x45, 0xF1C72, 0x824 }, + [ATHOS_LUT_CHAN_625375_IDX] = { 25015, 0x1, 0x45, 0xF8E39, 0x825 }, + [ATHOS_LUT_CHAN_625500_IDX] = { 25020, 0x1, 0x45, 0x100000, 0x825 }, + [ATHOS_LUT_CHAN_625625_IDX] = { 25025, 0x1, 0x45, 0x1071C7, 0x825 }, + [ATHOS_LUT_CHAN_625750_IDX] = { 25030, 0x1, 0x45, 0x10E38E, 0x826 }, + [ATHOS_LUT_CHAN_625875_IDX] = { 25035, 0x1, 0x45, 0x115555, 0x826 }, + [ATHOS_LUT_CHAN_626000_IDX] = { 25040, 0x1, 0x45, 0x11C71C, 0x827 }, + [ATHOS_LUT_CHAN_626125_IDX] = { 25045, 0x1, 0x45, 0x1238E4, 0x827 }, + [ATHOS_LUT_CHAN_626250_IDX] = { 25050, 0x1, 0x45, 0x12AAAB, 0x828 }, + [ATHOS_LUT_CHAN_626375_IDX] = { 25055, 0x1, 0x45, 0x131C72, 0x828 }, + [ATHOS_LUT_CHAN_626500_IDX] = { 25060, 0x1, 0x45, 0x138E39, 0x828 }, + [ATHOS_LUT_CHAN_626625_IDX] = { 25065, 0x1, 0x45, 0x140000, 0x829 }, + [ATHOS_LUT_CHAN_626750_IDX] = { 25070, 0x1, 0x45, 0x1471C7, 0x829 }, + [ATHOS_LUT_CHAN_626875_IDX] = { 25075, 0x1, 0x45, 0x14E38E, 0x82A }, + [ATHOS_LUT_CHAN_627000_IDX] = { 25080, 0x1, 0x45, 0x155555, 0x82A }, + [ATHOS_LUT_CHAN_627125_IDX] = { 25085, 0x1, 0x45, 0x15C71C, 0x82A }, + [ATHOS_LUT_CHAN_627250_IDX] = { 25090, 0x1, 0x45, 0x1638E4, 0x82B }, + [ATHOS_LUT_CHAN_627375_IDX] = { 25095, 0x1, 0x45, 0x16AAAB, 0x82B }, + [ATHOS_LUT_CHAN_627500_IDX] = { 25100, 0x1, 0x45, 0x171C72, 0x82C }, + [ATHOS_LUT_CHAN_627625_IDX] = { 25105, 0x1, 0x45, 0x178E39, 0x82C }, + [ATHOS_LUT_CHAN_627750_IDX] = { 25110, 0x1, 0x45, 0x180000, 0x82D }, + [ATHOS_LUT_CHAN_627875_IDX] = { 25115, 0x1, 0x45, 0x1871C7, 0x82D }, + [ATHOS_LUT_CHAN_628000_IDX] = { 25120, 0x1, 0x45, 0x18E38E, 0x82D }, + [ATHOS_LUT_CHAN_628125_IDX] = { 25125, 0x1, 0x45, 0x195555, 0x82E }, + [ATHOS_LUT_CHAN_628250_IDX] = { 25130, 0x1, 0x45, 0x19C71C, 0x82E }, + [ATHOS_LUT_CHAN_628375_IDX] = { 25135, 0x1, 0x45, 0x1A38E4, 0x82F }, + [ATHOS_LUT_CHAN_628500_IDX] = { 25140, 0x1, 0x45, 0x1AAAAB, 0x82F }, + [ATHOS_LUT_CHAN_628625_IDX] = { 25145, 0x1, 0x45, 0x1B1C72, 0x82F }, + [ATHOS_LUT_CHAN_628750_IDX] = { 25150, 0x1, 0x45, 0x1B8E39, 0x830 }, + [ATHOS_LUT_CHAN_628875_IDX] = { 25155, 0x1, 0x45, 0x1C0000, 0x830 }, + [ATHOS_LUT_CHAN_629000_IDX] = { 25160, 0x1, 0x45, 0x1C71C7, 0x831 }, + [ATHOS_LUT_CHAN_629125_IDX] = { 25165, 0x1, 0x45, 0x1CE38E, 0x831 }, + [ATHOS_LUT_CHAN_629250_IDX] = { 25170, 0x1, 0x45, 0x1D5555, 0x832 }, + [ATHOS_LUT_CHAN_629375_IDX] = { 25175, 0x1, 0x45, 0x1DC71C, 0x832 }, + [ATHOS_LUT_CHAN_629500_IDX] = { 25180, 0x1, 0x45, 0x1E38E4, 0x832 }, + [ATHOS_LUT_CHAN_629625_IDX] = { 25185, 0x1, 0x45, 0x1EAAAB, 0x833 }, + [ATHOS_LUT_CHAN_629750_IDX] = { 25190, 0x1, 0x45, 0x1F1C72, 0x833 }, + [ATHOS_LUT_CHAN_629875_IDX] = { 25195, 0x1, 0x45, 0x1F8E39, 0x834 }, + [ATHOS_LUT_CHAN_630000_IDX] = { 25200, 0x1, 0x46, 0x0, 0x834 }, + [ATHOS_LUT_CHAN_630125_IDX] = { 25205, 0x1, 0x46, 0x71C7, 0x834 }, + [ATHOS_LUT_CHAN_630250_IDX] = { 25210, 0x1, 0x46, 0xE38E, 0x835 }, + [ATHOS_LUT_CHAN_630375_IDX] = { 25215, 0x1, 0x46, 0x15555, 0x835 }, + [ATHOS_LUT_CHAN_630500_IDX] = { 25220, 0x1, 0x46, 0x1C71C, 0x836 }, + [ATHOS_LUT_CHAN_630625_IDX] = { 25225, 0x1, 0x46, 0x238E4, 0x836 }, + [ATHOS_LUT_CHAN_630750_IDX] = { 25230, 0x1, 0x46, 0x2AAAB, 0x837 }, + [ATHOS_LUT_CHAN_630875_IDX] = { 25235, 0x1, 0x46, 0x31C72, 0x837 }, + [ATHOS_LUT_CHAN_631000_IDX] = { 25240, 0x1, 0x46, 0x38E39, 0x837 }, + [ATHOS_LUT_CHAN_631125_IDX] = { 25245, 0x1, 0x46, 0x40000, 0x838 }, + [ATHOS_LUT_CHAN_631250_IDX] = { 25250, 0x1, 0x46, 0x471C7, 0x838 }, + [ATHOS_LUT_CHAN_631375_IDX] = { 25255, 0x1, 0x46, 0x4E38E, 0x839 }, + [ATHOS_LUT_CHAN_631500_IDX] = { 25260, 0x1, 0x46, 0x55555, 0x839 }, + [ATHOS_LUT_CHAN_631625_IDX] = { 25265, 0x1, 0x46, 0x5C71C, 0x839 }, + [ATHOS_LUT_CHAN_631750_IDX] = { 25270, 0x1, 0x46, 0x638E4, 0x83A }, + [ATHOS_LUT_CHAN_631875_IDX] = { 25275, 0x1, 0x46, 0x6AAAB, 0x83A }, + [ATHOS_LUT_CHAN_632000_IDX] = { 25280, 0x1, 0x46, 0x71C72, 0x83B }, + [ATHOS_LUT_CHAN_632125_IDX] = { 25285, 0x1, 0x46, 0x78E39, 0x83B }, + [ATHOS_LUT_CHAN_632250_IDX] = { 25290, 0x1, 0x46, 0x80000, 0x83C }, + [ATHOS_LUT_CHAN_632375_IDX] = { 25295, 0x1, 0x46, 0x871C7, 0x83C }, + [ATHOS_LUT_CHAN_632500_IDX] = { 25300, 0x1, 0x46, 0x8E38E, 0x83C }, + [ATHOS_LUT_CHAN_632625_IDX] = { 25305, 0x1, 0x46, 0x95555, 0x83D }, + [ATHOS_LUT_CHAN_632750_IDX] = { 25310, 0x1, 0x46, 0x9C71C, 0x83D }, + [ATHOS_LUT_CHAN_632875_IDX] = { 25315, 0x1, 0x46, 0xA38E4, 0x83E }, + [ATHOS_LUT_CHAN_633000_IDX] = { 25320, 0x1, 0x46, 0xAAAAB, 0x83E }, + [ATHOS_LUT_CHAN_633125_IDX] = { 25325, 0x1, 0x46, 0xB1C72, 0x83E }, + [ATHOS_LUT_CHAN_633250_IDX] = { 25330, 0x1, 0x46, 0xB8E39, 0x83F }, + [ATHOS_LUT_CHAN_633375_IDX] = { 25335, 0x1, 0x46, 0xC0000, 0x83F }, + [ATHOS_LUT_CHAN_633500_IDX] = { 25340, 0x1, 0x46, 0xC71C7, 0x840 }, + [ATHOS_LUT_CHAN_633625_IDX] = { 25345, 0x1, 0x46, 0xCE38E, 0x840 }, + [ATHOS_LUT_CHAN_633750_IDX] = { 25350, 0x1, 0x46, 0xD5555, 0x841 }, + [ATHOS_LUT_CHAN_633875_IDX] = { 25355, 0x1, 0x46, 0xDC71C, 0x841 }, + [ATHOS_LUT_CHAN_634000_IDX] = { 25360, 0x1, 0x46, 0xE38E4, 0x841 }, + [ATHOS_LUT_CHAN_634125_IDX] = { 25365, 0x1, 0x46, 0xEAAAB, 0x842 }, + [ATHOS_LUT_CHAN_634250_IDX] = { 25370, 0x1, 0x46, 0xF1C72, 0x842 }, + [ATHOS_LUT_CHAN_634375_IDX] = { 25375, 0x1, 0x46, 0xF8E39, 0x843 }, + [ATHOS_LUT_CHAN_634500_IDX] = { 25380, 0x1, 0x46, 0x100000, 0x843 }, + [ATHOS_LUT_CHAN_634625_IDX] = { 25385, 0x1, 0x46, 0x1071C7, 0x843 }, + [ATHOS_LUT_CHAN_634750_IDX] = { 25390, 0x1, 0x46, 0x10E38E, 0x844 }, + [ATHOS_LUT_CHAN_634875_IDX] = { 25395, 0x1, 0x46, 0x115555, 0x844 }, + [ATHOS_LUT_CHAN_635000_IDX] = { 25400, 0x1, 0x46, 0x11C71C, 0x845 }, + [ATHOS_LUT_CHAN_635125_IDX] = { 25405, 0x1, 0x46, 0x1238E4, 0x845 }, + [ATHOS_LUT_CHAN_635250_IDX] = { 25410, 0x1, 0x46, 0x12AAAB, 0x846 }, + [ATHOS_LUT_CHAN_635375_IDX] = { 25415, 0x1, 0x46, 0x131C72, 0x846 }, + [ATHOS_LUT_CHAN_635500_IDX] = { 25420, 0x1, 0x46, 0x138E39, 0x846 }, + [ATHOS_LUT_CHAN_635625_IDX] = { 25425, 0x1, 0x46, 0x140000, 0x847 }, + [ATHOS_LUT_CHAN_635750_IDX] = { 25430, 0x1, 0x46, 0x1471C7, 0x847 }, + [ATHOS_LUT_CHAN_635875_IDX] = { 25435, 0x1, 0x46, 0x14E38E, 0x848 }, + [ATHOS_LUT_CHAN_636000_IDX] = { 25440, 0x1, 0x46, 0x155555, 0x848 }, + [ATHOS_LUT_CHAN_636125_IDX] = { 25445, 0x1, 0x46, 0x15C71C, 0x848 }, + [ATHOS_LUT_CHAN_636250_IDX] = { 25450, 0x1, 0x46, 0x1638E4, 0x849 }, + [ATHOS_LUT_CHAN_636375_IDX] = { 25455, 0x1, 0x46, 0x16AAAB, 0x849 }, + [ATHOS_LUT_CHAN_636500_IDX] = { 25460, 0x1, 0x46, 0x171C72, 0x84A }, + [ATHOS_LUT_CHAN_636625_IDX] = { 25465, 0x1, 0x46, 0x178E39, 0x84A }, + [ATHOS_LUT_CHAN_636750_IDX] = { 25470, 0x1, 0x46, 0x180000, 0x84B }, + [ATHOS_LUT_CHAN_636875_IDX] = { 25475, 0x1, 0x46, 0x1871C7, 0x84B }, + [ATHOS_LUT_CHAN_637000_IDX] = { 25480, 0x1, 0x46, 0x18E38E, 0x84B }, + [ATHOS_LUT_CHAN_637125_IDX] = { 25485, 0x1, 0x46, 0x195555, 0x84C }, + [ATHOS_LUT_CHAN_637250_IDX] = { 25490, 0x1, 0x46, 0x19C71C, 0x84C }, + [ATHOS_LUT_CHAN_637375_IDX] = { 25495, 0x1, 0x46, 0x1A38E4, 0x84D }, + [ATHOS_LUT_CHAN_637500_IDX] = { 25500, 0x1, 0x46, 0x1AAAAB, 0x84D }, + [ATHOS_LUT_CHAN_637625_IDX] = { 25505, 0x1, 0x46, 0x1B1C72, 0x84D }, + [ATHOS_LUT_CHAN_637750_IDX] = { 25510, 0x1, 0x46, 0x1B8E39, 0x84E }, + [ATHOS_LUT_CHAN_637875_IDX] = { 25515, 0x1, 0x46, 0x1C0000, 0x84E }, + [ATHOS_LUT_CHAN_638000_IDX] = { 25520, 0x1, 0x46, 0x1C71C7, 0x84F }, + [ATHOS_LUT_CHAN_638125_IDX] = { 25525, 0x1, 0x46, 0x1CE38E, 0x84F }, + [ATHOS_LUT_CHAN_638250_IDX] = { 25530, 0x1, 0x46, 0x1D5555, 0x850 }, + [ATHOS_LUT_CHAN_638375_IDX] = { 25535, 0x1, 0x46, 0x1DC71C, 0x850 }, + [ATHOS_LUT_CHAN_638500_IDX] = { 25540, 0x1, 0x46, 0x1E38E4, 0x850 }, + [ATHOS_LUT_CHAN_638625_IDX] = { 25545, 0x1, 0x46, 0x1EAAAB, 0x851 }, + [ATHOS_LUT_CHAN_638750_IDX] = { 25550, 0x1, 0x46, 0x1F1C72, 0x851 }, + [ATHOS_LUT_CHAN_638875_IDX] = { 25555, 0x1, 0x46, 0x1F8E39, 0x852 }, + [ATHOS_LUT_CHAN_639000_IDX] = { 25560, 0x1, 0x47, 0x0, 0x852 }, + [ATHOS_LUT_CHAN_639125_IDX] = { 25565, 0x1, 0x47, 0x71C7, 0x852 }, + [ATHOS_LUT_CHAN_639250_IDX] = { 25570, 0x1, 0x47, 0xE38E, 0x853 }, + [ATHOS_LUT_CHAN_639375_IDX] = { 25575, 0x1, 0x47, 0x15555, 0x853 }, + [ATHOS_LUT_CHAN_639500_IDX] = { 25580, 0x1, 0x47, 0x1C71C, 0x854 }, + [ATHOS_LUT_CHAN_639625_IDX] = { 25585, 0x1, 0x47, 0x238E4, 0x854 }, + [ATHOS_LUT_CHAN_639750_IDX] = { 25590, 0x1, 0x47, 0x2AAAB, 0x855 }, + [ATHOS_LUT_CHAN_639875_IDX] = { 25595, 0x1, 0x47, 0x31C72, 0x855 }, + [ATHOS_LUT_CHAN_640000_IDX] = { 25600, 0x1, 0x47, 0x38E39, 0x855 }, + [ATHOS_LUT_CHAN_640125_IDX] = { 25605, 0x1, 0x47, 0x40000, 0x856 }, + [ATHOS_LUT_CHAN_640250_IDX] = { 25610, 0x1, 0x47, 0x471C7, 0x856 }, + [ATHOS_LUT_CHAN_640375_IDX] = { 25615, 0x1, 0x47, 0x4E38E, 0x857 }, + [ATHOS_LUT_CHAN_640500_IDX] = { 25620, 0x1, 0x47, 0x55555, 0x857 }, + [ATHOS_LUT_CHAN_640625_IDX] = { 25625, 0x1, 0x47, 0x5C71C, 0x857 }, + [ATHOS_LUT_CHAN_640750_IDX] = { 25630, 0x1, 0x47, 0x638E4, 0x858 }, + [ATHOS_LUT_CHAN_640875_IDX] = { 25635, 0x1, 0x47, 0x6AAAB, 0x858 }, + [ATHOS_LUT_CHAN_641000_IDX] = { 25640, 0x1, 0x47, 0x71C72, 0x859 }, + [ATHOS_LUT_CHAN_641125_IDX] = { 25645, 0x1, 0x47, 0x78E39, 0x859 }, + [ATHOS_LUT_CHAN_641250_IDX] = { 25650, 0x1, 0x47, 0x80000, 0x85A }, + [ATHOS_LUT_CHAN_641375_IDX] = { 25655, 0x1, 0x47, 0x871C7, 0x85A }, + [ATHOS_LUT_CHAN_641500_IDX] = { 25660, 0x1, 0x47, 0x8E38E, 0x85A }, + [ATHOS_LUT_CHAN_641625_IDX] = { 25665, 0x1, 0x47, 0x95555, 0x85B }, + [ATHOS_LUT_CHAN_641750_IDX] = { 25670, 0x1, 0x47, 0x9C71C, 0x85B }, + [ATHOS_LUT_CHAN_641875_IDX] = { 25675, 0x1, 0x47, 0xA38E4, 0x85C }, + [ATHOS_LUT_CHAN_642000_IDX] = { 25680, 0x1, 0x47, 0xAAAAB, 0x85C }, + [ATHOS_LUT_CHAN_642125_IDX] = { 25685, 0x1, 0x47, 0xB1C72, 0x85C }, + [ATHOS_LUT_CHAN_642250_IDX] = { 25690, 0x1, 0x47, 0xB8E39, 0x85D }, + [ATHOS_LUT_CHAN_642375_IDX] = { 25695, 0x1, 0x47, 0xC0000, 0x85D }, + [ATHOS_LUT_CHAN_642500_IDX] = { 25700, 0x1, 0x47, 0xC71C7, 0x85E }, + [ATHOS_LUT_CHAN_642625_IDX] = { 25705, 0x1, 0x47, 0xCE38E, 0x85E }, + [ATHOS_LUT_CHAN_642750_IDX] = { 25710, 0x1, 0x47, 0xD5555, 0x85F }, + [ATHOS_LUT_CHAN_642875_IDX] = { 25715, 0x1, 0x47, 0xDC71C, 0x85F }, + [ATHOS_LUT_CHAN_643000_IDX] = { 25720, 0x1, 0x47, 0xE38E4, 0x85F }, + [ATHOS_LUT_CHAN_643125_IDX] = { 25725, 0x1, 0x47, 0xEAAAB, 0x860 }, + [ATHOS_LUT_CHAN_643250_IDX] = { 25730, 0x1, 0x47, 0xF1C72, 0x860 }, + [ATHOS_LUT_CHAN_643375_IDX] = { 25735, 0x1, 0x47, 0xF8E39, 0x861 }, + [ATHOS_LUT_CHAN_643500_IDX] = { 25740, 0x1, 0x47, 0x100000, 0x861 }, + [ATHOS_LUT_CHAN_643625_IDX] = { 25745, 0x1, 0x47, 0x1071C7, 0x861 }, + [ATHOS_LUT_CHAN_643750_IDX] = { 25750, 0x1, 0x47, 0x10E38E, 0x862 }, + [ATHOS_LUT_CHAN_643875_IDX] = { 25755, 0x1, 0x47, 0x115555, 0x862 }, + [ATHOS_LUT_CHAN_644000_IDX] = { 25760, 0x1, 0x47, 0x11C71C, 0x863 }, + [ATHOS_LUT_CHAN_644125_IDX] = { 25765, 0x1, 0x47, 0x1238E4, 0x863 }, + [ATHOS_LUT_CHAN_644250_IDX] = { 25770, 0x1, 0x47, 0x12AAAB, 0x864 }, + [ATHOS_LUT_CHAN_644375_IDX] = { 25775, 0x1, 0x47, 0x131C72, 0x864 }, + [ATHOS_LUT_CHAN_644500_IDX] = { 25780, 0x1, 0x47, 0x138E39, 0x864 }, + [ATHOS_LUT_CHAN_644625_IDX] = { 25785, 0x1, 0x47, 0x140000, 0x865 }, + [ATHOS_LUT_CHAN_644750_IDX] = { 25790, 0x1, 0x47, 0x1471C7, 0x865 }, + [ATHOS_LUT_CHAN_644875_IDX] = { 25795, 0x1, 0x47, 0x14E38E, 0x866 }, + [ATHOS_LUT_CHAN_645000_IDX] = { 25800, 0x1, 0x47, 0x155555, 0x866 }, + [ATHOS_LUT_CHAN_645125_IDX] = { 25805, 0x1, 0x47, 0x15C71C, 0x866 }, + [ATHOS_LUT_CHAN_645250_IDX] = { 25810, 0x1, 0x47, 0x1638E4, 0x867 }, + [ATHOS_LUT_CHAN_645375_IDX] = { 25815, 0x1, 0x47, 0x16AAAB, 0x867 }, + [ATHOS_LUT_CHAN_645500_IDX] = { 25820, 0x1, 0x47, 0x171C72, 0x868 }, + [ATHOS_LUT_CHAN_645625_IDX] = { 25825, 0x1, 0x47, 0x178E39, 0x868 }, + [ATHOS_LUT_CHAN_645750_IDX] = { 25830, 0x1, 0x47, 0x180000, 0x869 }, + [ATHOS_LUT_CHAN_645875_IDX] = { 25835, 0x1, 0x47, 0x1871C7, 0x869 }, + [ATHOS_LUT_CHAN_646000_IDX] = { 25840, 0x1, 0x47, 0x18E38E, 0x869 }, + [ATHOS_LUT_CHAN_646125_IDX] = { 25845, 0x1, 0x47, 0x195555, 0x86A }, + [ATHOS_LUT_CHAN_646250_IDX] = { 25850, 0x1, 0x47, 0x19C71C, 0x86A }, + [ATHOS_LUT_CHAN_646375_IDX] = { 25855, 0x1, 0x47, 0x1A38E4, 0x86B }, + [ATHOS_LUT_CHAN_646500_IDX] = { 25860, 0x1, 0x47, 0x1AAAAB, 0x86B }, + [ATHOS_LUT_CHAN_646625_IDX] = { 25865, 0x1, 0x47, 0x1B1C72, 0x86B }, + [ATHOS_LUT_CHAN_646750_IDX] = { 25870, 0x1, 0x47, 0x1B8E39, 0x86C }, + [ATHOS_LUT_CHAN_646875_IDX] = { 25875, 0x1, 0x47, 0x1C0000, 0x86C }, + [ATHOS_LUT_CHAN_647000_IDX] = { 25880, 0x1, 0x47, 0x1C71C7, 0x86D }, + [ATHOS_LUT_CHAN_647125_IDX] = { 25885, 0x1, 0x47, 0x1CE38E, 0x86D }, + [ATHOS_LUT_CHAN_647250_IDX] = { 25890, 0x1, 0x47, 0x1D5555, 0x86E }, + [ATHOS_LUT_CHAN_647375_IDX] = { 25895, 0x1, 0x47, 0x1DC71C, 0x86E }, + [ATHOS_LUT_CHAN_647500_IDX] = { 25900, 0x1, 0x47, 0x1E38E4, 0x86E }, + [ATHOS_LUT_CHAN_647625_IDX] = { 25905, 0x1, 0x47, 0x1EAAAB, 0x86F }, + [ATHOS_LUT_CHAN_647750_IDX] = { 25910, 0x1, 0x47, 0x1F1C72, 0x86F }, + [ATHOS_LUT_CHAN_647875_IDX] = { 25915, 0x1, 0x47, 0x1F8E39, 0x870 }, + [ATHOS_LUT_CHAN_648000_IDX] = { 25920, 0x1, 0x48, 0x0, 0x870 }, + [ATHOS_LUT_CHAN_648125_IDX] = { 25925, 0x1, 0x48, 0x71C7, 0x870 }, + [ATHOS_LUT_CHAN_648250_IDX] = { 25930, 0x1, 0x48, 0xE38E, 0x871 }, + [ATHOS_LUT_CHAN_648375_IDX] = { 25935, 0x1, 0x48, 0x15555, 0x871 }, + [ATHOS_LUT_CHAN_648500_IDX] = { 25940, 0x1, 0x48, 0x1C71C, 0x872 }, + [ATHOS_LUT_CHAN_648625_IDX] = { 25945, 0x1, 0x48, 0x238E4, 0x872 }, + [ATHOS_LUT_CHAN_648750_IDX] = { 25950, 0x1, 0x48, 0x2AAAB, 0x873 }, + [ATHOS_LUT_CHAN_648875_IDX] = { 25955, 0x1, 0x48, 0x31C72, 0x873 }, + [ATHOS_LUT_CHAN_649000_IDX] = { 25960, 0x1, 0x48, 0x38E39, 0x873 }, + [ATHOS_LUT_CHAN_649125_IDX] = { 25965, 0x1, 0x48, 0x40000, 0x874 }, + [ATHOS_LUT_CHAN_649250_IDX] = { 25970, 0x1, 0x48, 0x471C7, 0x874 }, + [ATHOS_LUT_CHAN_649375_IDX] = { 25975, 0x1, 0x48, 0x4E38E, 0x875 }, + [ATHOS_LUT_CHAN_649500_IDX] = { 25980, 0x1, 0x48, 0x55555, 0x875 }, + [ATHOS_LUT_CHAN_649625_IDX] = { 25985, 0x1, 0x48, 0x5C71C, 0x875 }, + [ATHOS_LUT_CHAN_649750_IDX] = { 25990, 0x1, 0x48, 0x638E4, 0x876 }, + [ATHOS_LUT_CHAN_649875_IDX] = { 25995, 0x1, 0x48, 0x6AAAB, 0x876 }, + [ATHOS_LUT_CHAN_650000_IDX] = { 26000, 0x1, 0x48, 0x71C72, 0x877 }, + [ATHOS_LUT_CHAN_650125_IDX] = { 26005, 0x1, 0x48, 0x78E39, 0x877 }, + [ATHOS_LUT_CHAN_650250_IDX] = { 26010, 0x1, 0x48, 0x80000, 0x878 }, + [ATHOS_LUT_CHAN_650375_IDX] = { 26015, 0x1, 0x48, 0x871C7, 0x878 }, + [ATHOS_LUT_CHAN_650500_IDX] = { 26020, 0x1, 0x48, 0x8E38E, 0x878 }, + [ATHOS_LUT_CHAN_650625_IDX] = { 26025, 0x1, 0x48, 0x95555, 0x879 }, + [ATHOS_LUT_CHAN_650750_IDX] = { 26030, 0x1, 0x48, 0x9C71C, 0x879 }, + [ATHOS_LUT_CHAN_650875_IDX] = { 26035, 0x1, 0x48, 0xA38E4, 0x87A }, + [ATHOS_LUT_CHAN_651000_IDX] = { 26040, 0x1, 0x48, 0xAAAAB, 0x87A }, + [ATHOS_LUT_CHAN_651125_IDX] = { 26045, 0x1, 0x48, 0xB1C72, 0x87A }, + [ATHOS_LUT_CHAN_651250_IDX] = { 26050, 0x1, 0x48, 0xB8E39, 0x87B }, + [ATHOS_LUT_CHAN_651375_IDX] = { 26055, 0x1, 0x48, 0xC0000, 0x87B }, + [ATHOS_LUT_CHAN_651500_IDX] = { 26060, 0x1, 0x48, 0xC71C7, 0x87C }, + [ATHOS_LUT_CHAN_651625_IDX] = { 26065, 0x1, 0x48, 0xCE38E, 0x87C }, + [ATHOS_LUT_CHAN_651750_IDX] = { 26070, 0x1, 0x48, 0xD5555, 0x87D }, + [ATHOS_LUT_CHAN_651875_IDX] = { 26075, 0x1, 0x48, 0xDC71C, 0x87D }, + [ATHOS_LUT_CHAN_652000_IDX] = { 26080, 0x1, 0x48, 0xE38E4, 0x87D }, + [ATHOS_LUT_CHAN_652125_IDX] = { 26085, 0x1, 0x48, 0xEAAAB, 0x87E }, + [ATHOS_LUT_CHAN_652250_IDX] = { 26090, 0x1, 0x48, 0xF1C72, 0x87E }, + [ATHOS_LUT_CHAN_652375_IDX] = { 26095, 0x1, 0x48, 0xF8E39, 0x87F }, + [ATHOS_LUT_CHAN_652500_IDX] = { 26100, 0x1, 0x48, 0x100000, 0x87F }, + [ATHOS_LUT_CHAN_652625_IDX] = { 26105, 0x1, 0x48, 0x1071C7, 0x87F }, + [ATHOS_LUT_CHAN_652750_IDX] = { 26110, 0x1, 0x48, 0x10E38E, 0x880 }, + [ATHOS_LUT_CHAN_652875_IDX] = { 26115, 0x1, 0x48, 0x115555, 0x880 }, + [ATHOS_LUT_CHAN_653000_IDX] = { 26120, 0x1, 0x48, 0x11C71C, 0x881 }, + [ATHOS_LUT_CHAN_653125_IDX] = { 26125, 0x1, 0x48, 0x1238E4, 0x881 }, + [ATHOS_LUT_CHAN_653250_IDX] = { 26130, 0x1, 0x48, 0x12AAAB, 0x882 }, + [ATHOS_LUT_CHAN_653375_IDX] = { 26135, 0x1, 0x48, 0x131C72, 0x882 }, + [ATHOS_LUT_CHAN_653500_IDX] = { 26140, 0x1, 0x48, 0x138E39, 0x882 }, + [ATHOS_LUT_CHAN_653625_IDX] = { 26145, 0x1, 0x48, 0x140000, 0x883 }, + [ATHOS_LUT_CHAN_653750_IDX] = { 26150, 0x1, 0x48, 0x1471C7, 0x883 }, + [ATHOS_LUT_CHAN_653875_IDX] = { 26155, 0x1, 0x48, 0x14E38E, 0x884 }, + [ATHOS_LUT_CHAN_654000_IDX] = { 26160, 0x1, 0x48, 0x155555, 0x884 }, + [ATHOS_LUT_CHAN_654125_IDX] = { 26165, 0x1, 0x48, 0x15C71C, 0x884 }, + [ATHOS_LUT_CHAN_654250_IDX] = { 26170, 0x1, 0x48, 0x1638E4, 0x885 }, + [ATHOS_LUT_CHAN_654375_IDX] = { 26175, 0x1, 0x48, 0x16AAAB, 0x885 }, + [ATHOS_LUT_CHAN_654500_IDX] = { 26180, 0x1, 0x48, 0x171C72, 0x886 }, + [ATHOS_LUT_CHAN_654625_IDX] = { 26185, 0x1, 0x48, 0x178E39, 0x886 }, + [ATHOS_LUT_CHAN_654750_IDX] = { 26190, 0x1, 0x48, 0x180000, 0x887 }, + [ATHOS_LUT_CHAN_654875_IDX] = { 26195, 0x1, 0x48, 0x1871C7, 0x887 }, + [ATHOS_LUT_CHAN_655000_IDX] = { 26200, 0x1, 0x48, 0x18E38E, 0x887 }, + [ATHOS_LUT_CHAN_655125_IDX] = { 26205, 0x1, 0x48, 0x195555, 0x888 }, + [ATHOS_LUT_CHAN_655250_IDX] = { 26210, 0x1, 0x48, 0x19C71C, 0x888 }, + [ATHOS_LUT_CHAN_655375_IDX] = { 26215, 0x1, 0x48, 0x1A38E4, 0x889 }, + [ATHOS_LUT_CHAN_655500_IDX] = { 26220, 0x1, 0x48, 0x1AAAAB, 0x889 }, + [ATHOS_LUT_CHAN_655625_IDX] = { 26225, 0x1, 0x48, 0x1B1C72, 0x889 }, + [ATHOS_LUT_CHAN_655750_IDX] = { 26230, 0x1, 0x48, 0x1B8E39, 0x88A }, + [ATHOS_LUT_CHAN_655875_IDX] = { 26235, 0x1, 0x48, 0x1C0000, 0x88A }, + [ATHOS_LUT_CHAN_656000_IDX] = { 26240, 0x1, 0x48, 0x1C71C7, 0x88B }, + [ATHOS_LUT_CHAN_656125_IDX] = { 26245, 0x1, 0x48, 0x1CE38E, 0x88B }, + [ATHOS_LUT_CHAN_656250_IDX] = { 26250, 0x1, 0x48, 0x1D5555, 0x88C }, + [ATHOS_LUT_CHAN_656375_IDX] = { 26255, 0x1, 0x48, 0x1DC71C, 0x88C }, + [ATHOS_LUT_CHAN_656500_IDX] = { 26260, 0x1, 0x48, 0x1E38E4, 0x88C }, + [ATHOS_LUT_CHAN_656625_IDX] = { 26265, 0x1, 0x48, 0x1EAAAB, 0x88D }, + [ATHOS_LUT_CHAN_656750_IDX] = { 26270, 0x1, 0x48, 0x1F1C72, 0x88D }, + [ATHOS_LUT_CHAN_656875_IDX] = { 26275, 0x1, 0x48, 0x1F8E39, 0x88E }, + [ATHOS_LUT_CHAN_657000_IDX] = { 26280, 0x1, 0x49, 0x0, 0x88E }, + [ATHOS_LUT_CHAN_657125_IDX] = { 26285, 0x1, 0x49, 0x71C7, 0x88E }, + [ATHOS_LUT_CHAN_657250_IDX] = { 26290, 0x1, 0x49, 0xE38E, 0x88F }, + [ATHOS_LUT_CHAN_657375_IDX] = { 26295, 0x1, 0x49, 0x15555, 0x88F }, + [ATHOS_LUT_CHAN_657500_IDX] = { 26300, 0x1, 0x49, 0x1C71C, 0x890 }, + [ATHOS_LUT_CHAN_657625_IDX] = { 26305, 0x1, 0x49, 0x238E4, 0x890 }, + [ATHOS_LUT_CHAN_657750_IDX] = { 26310, 0x1, 0x49, 0x2AAAB, 0x891 }, + [ATHOS_LUT_CHAN_657875_IDX] = { 26315, 0x1, 0x49, 0x31C72, 0x891 }, + [ATHOS_LUT_CHAN_658000_IDX] = { 26320, 0x1, 0x49, 0x38E39, 0x891 }, + [ATHOS_LUT_CHAN_658125_IDX] = { 26325, 0x1, 0x49, 0x40000, 0x892 }, + [ATHOS_LUT_CHAN_658250_IDX] = { 26330, 0x1, 0x49, 0x471C7, 0x892 }, + [ATHOS_LUT_CHAN_658375_IDX] = { 26335, 0x1, 0x49, 0x4E38E, 0x893 }, + [ATHOS_LUT_CHAN_658500_IDX] = { 26340, 0x1, 0x49, 0x55555, 0x893 }, + [ATHOS_LUT_CHAN_658625_IDX] = { 26345, 0x1, 0x49, 0x5C71C, 0x893 }, + [ATHOS_LUT_CHAN_658750_IDX] = { 26350, 0x1, 0x49, 0x638E4, 0x894 }, + [ATHOS_LUT_CHAN_658875_IDX] = { 26355, 0x1, 0x49, 0x6AAAB, 0x894 }, + [ATHOS_LUT_CHAN_659000_IDX] = { 26360, 0x1, 0x49, 0x71C72, 0x895 }, + [ATHOS_LUT_CHAN_659125_IDX] = { 26365, 0x1, 0x49, 0x78E39, 0x895 }, + [ATHOS_LUT_CHAN_659250_IDX] = { 26370, 0x1, 0x49, 0x80000, 0x896 }, + [ATHOS_LUT_CHAN_659375_IDX] = { 26375, 0x1, 0x49, 0x871C7, 0x896 }, + [ATHOS_LUT_CHAN_659500_IDX] = { 26380, 0x1, 0x49, 0x8E38E, 0x896 }, + [ATHOS_LUT_CHAN_659625_IDX] = { 26385, 0x1, 0x49, 0x95555, 0x897 }, + [ATHOS_LUT_CHAN_659750_IDX] = { 26390, 0x1, 0x49, 0x9C71C, 0x897 }, + [ATHOS_LUT_CHAN_659875_IDX] = { 26395, 0x1, 0x49, 0xA38E4, 0x898 }, + [ATHOS_LUT_CHAN_660000_IDX] = { 26400, 0x1, 0x49, 0xAAAAB, 0x898 }, + [ATHOS_LUT_CHAN_660125_IDX] = { 26405, 0x1, 0x49, 0xB1C72, 0x898 }, + [ATHOS_LUT_CHAN_660250_IDX] = { 26410, 0x1, 0x49, 0xB8E39, 0x899 }, + [ATHOS_LUT_CHAN_660375_IDX] = { 26415, 0x1, 0x49, 0xC0000, 0x899 }, + [ATHOS_LUT_CHAN_660500_IDX] = { 26420, 0x1, 0x49, 0xC71C7, 0x89A }, + [ATHOS_LUT_CHAN_660625_IDX] = { 26425, 0x1, 0x49, 0xCE38E, 0x89A }, + [ATHOS_LUT_CHAN_660750_IDX] = { 26430, 0x1, 0x49, 0xD5555, 0x89B }, + [ATHOS_LUT_CHAN_660875_IDX] = { 26435, 0x1, 0x49, 0xDC71C, 0x89B }, + [ATHOS_LUT_CHAN_661000_IDX] = { 26440, 0x1, 0x49, 0xE38E4, 0x89B }, + [ATHOS_LUT_CHAN_661125_IDX] = { 26445, 0x1, 0x49, 0xEAAAB, 0x89C }, + [ATHOS_LUT_CHAN_661250_IDX] = { 26450, 0x1, 0x49, 0xF1C72, 0x89C }, + [ATHOS_LUT_CHAN_661375_IDX] = { 26455, 0x1, 0x49, 0xF8E39, 0x89D }, + [ATHOS_LUT_CHAN_661500_IDX] = { 26460, 0x1, 0x49, 0x100000, 0x89D }, + [ATHOS_LUT_CHAN_661625_IDX] = { 26465, 0x1, 0x49, 0x1071C7, 0x89D }, + [ATHOS_LUT_CHAN_661750_IDX] = { 26470, 0x1, 0x49, 0x10E38E, 0x89E }, + [ATHOS_LUT_CHAN_661875_IDX] = { 26475, 0x1, 0x49, 0x115555, 0x89E }, + [ATHOS_LUT_CHAN_662000_IDX] = { 26480, 0x1, 0x49, 0x11C71C, 0x89F }, + [ATHOS_LUT_CHAN_662125_IDX] = { 26485, 0x1, 0x49, 0x1238E4, 0x89F }, + [ATHOS_LUT_CHAN_662250_IDX] = { 26490, 0x1, 0x49, 0x12AAAB, 0x8A0 }, + [ATHOS_LUT_CHAN_662375_IDX] = { 26495, 0x1, 0x49, 0x131C72, 0x8A0 }, + [ATHOS_LUT_CHAN_662500_IDX] = { 26500, 0x1, 0x49, 0x138E39, 0x8A0 }, + [ATHOS_LUT_CHAN_662625_IDX] = { 26505, 0x1, 0x49, 0x140000, 0x8A1 }, + [ATHOS_LUT_CHAN_662750_IDX] = { 26510, 0x1, 0x49, 0x1471C7, 0x8A1 }, + [ATHOS_LUT_CHAN_662875_IDX] = { 26515, 0x1, 0x49, 0x14E38E, 0x8A2 }, + [ATHOS_LUT_CHAN_663000_IDX] = { 26520, 0x1, 0x49, 0x155555, 0x8A2 }, + [ATHOS_LUT_CHAN_663125_IDX] = { 26525, 0x1, 0x49, 0x15C71C, 0x8A2 }, + [ATHOS_LUT_CHAN_663250_IDX] = { 26530, 0x1, 0x49, 0x1638E4, 0x8A3 }, + [ATHOS_LUT_CHAN_663375_IDX] = { 26535, 0x1, 0x49, 0x16AAAB, 0x8A3 }, + [ATHOS_LUT_CHAN_663500_IDX] = { 26540, 0x1, 0x49, 0x171C72, 0x8A4 }, + [ATHOS_LUT_CHAN_663625_IDX] = { 26545, 0x1, 0x49, 0x178E39, 0x8A4 }, + [ATHOS_LUT_CHAN_663750_IDX] = { 26550, 0x1, 0x49, 0x180000, 0x8A5 }, + [ATHOS_LUT_CHAN_663875_IDX] = { 26555, 0x1, 0x49, 0x1871C7, 0x8A5 }, + [ATHOS_LUT_CHAN_664000_IDX] = { 26560, 0x1, 0x49, 0x18E38E, 0x8A5 }, + [ATHOS_LUT_CHAN_664125_IDX] = { 26565, 0x1, 0x49, 0x195555, 0x8A6 }, + [ATHOS_LUT_CHAN_664250_IDX] = { 26570, 0x1, 0x49, 0x19C71C, 0x8A6 }, + [ATHOS_LUT_CHAN_664375_IDX] = { 26575, 0x1, 0x49, 0x1A38E4, 0x8A7 }, + [ATHOS_LUT_CHAN_664500_IDX] = { 26580, 0x1, 0x49, 0x1AAAAB, 0x8A7 }, + [ATHOS_LUT_CHAN_664625_IDX] = { 26585, 0x1, 0x49, 0x1B1C72, 0x8A7 }, + [ATHOS_LUT_CHAN_664750_IDX] = { 26590, 0x1, 0x49, 0x1B8E39, 0x8A8 }, + [ATHOS_LUT_CHAN_664875_IDX] = { 26595, 0x1, 0x49, 0x1C0000, 0x8A8 }, + [ATHOS_LUT_CHAN_665000_IDX] = { 26600, 0x1, 0x49, 0x1C71C7, 0x8A9 }, + [ATHOS_LUT_CHAN_665125_IDX] = { 26605, 0x1, 0x49, 0x1CE38E, 0x8A9 }, + [ATHOS_LUT_CHAN_665250_IDX] = { 26610, 0x1, 0x49, 0x1D5555, 0x8AA }, + [ATHOS_LUT_CHAN_665375_IDX] = { 26615, 0x1, 0x49, 0x1DC71C, 0x8AA }, + [ATHOS_LUT_CHAN_665500_IDX] = { 26620, 0x1, 0x49, 0x1E38E4, 0x8AA }, + [ATHOS_LUT_CHAN_665625_IDX] = { 26625, 0x1, 0x49, 0x1EAAAB, 0x8AB }, + [ATHOS_LUT_CHAN_665750_IDX] = { 26630, 0x1, 0x49, 0x1F1C72, 0x8AB }, + [ATHOS_LUT_CHAN_665875_IDX] = { 26635, 0x1, 0x49, 0x1F8E39, 0x8AC }, + [ATHOS_LUT_CHAN_666000_IDX] = { 26640, 0x1, 0x4A, 0x0, 0x8AC }, + [ATHOS_LUT_CHAN_666125_IDX] = { 26645, 0x1, 0x4A, 0x71C7, 0x8AC }, + [ATHOS_LUT_CHAN_666250_IDX] = { 26650, 0x1, 0x4A, 0xE38E, 0x8AD }, + [ATHOS_LUT_CHAN_666375_IDX] = { 26655, 0x1, 0x4A, 0x15555, 0x8AD }, + [ATHOS_LUT_CHAN_666500_IDX] = { 26660, 0x1, 0x4A, 0x1C71C, 0x8AE }, + [ATHOS_LUT_CHAN_666625_IDX] = { 26665, 0x1, 0x4A, 0x238E4, 0x8AE }, + [ATHOS_LUT_CHAN_666750_IDX] = { 26670, 0x1, 0x4A, 0x2AAAB, 0x8AF }, + [ATHOS_LUT_CHAN_666875_IDX] = { 26675, 0x1, 0x4A, 0x31C72, 0x8AF }, + [ATHOS_LUT_CHAN_667000_IDX] = { 26680, 0x1, 0x4A, 0x38E39, 0x8AF }, + [ATHOS_LUT_CHAN_667125_IDX] = { 26685, 0x1, 0x4A, 0x40000, 0x8B0 }, + [ATHOS_LUT_CHAN_667250_IDX] = { 26690, 0x1, 0x4A, 0x471C7, 0x8B0 }, + [ATHOS_LUT_CHAN_667375_IDX] = { 26695, 0x1, 0x4A, 0x4E38E, 0x8B1 }, + [ATHOS_LUT_CHAN_667500_IDX] = { 26700, 0x1, 0x4A, 0x55555, 0x8B1 }, + [ATHOS_LUT_CHAN_667625_IDX] = { 26705, 0x1, 0x4A, 0x5C71C, 0x8B1 }, + [ATHOS_LUT_CHAN_667750_IDX] = { 26710, 0x1, 0x4A, 0x638E4, 0x8B2 }, + [ATHOS_LUT_CHAN_667875_IDX] = { 26715, 0x1, 0x4A, 0x6AAAB, 0x8B2 }, + [ATHOS_LUT_CHAN_668000_IDX] = { 26720, 0x1, 0x4A, 0x71C72, 0x8B3 }, + [ATHOS_LUT_CHAN_668125_IDX] = { 26725, 0x1, 0x4A, 0x78E39, 0x8B3 }, + [ATHOS_LUT_CHAN_668250_IDX] = { 26730, 0x1, 0x4A, 0x80000, 0x8B4 }, + [ATHOS_LUT_CHAN_668375_IDX] = { 26735, 0x1, 0x4A, 0x871C7, 0x8B4 }, + [ATHOS_LUT_CHAN_668500_IDX] = { 26740, 0x1, 0x4A, 0x8E38E, 0x8B4 }, + [ATHOS_LUT_CHAN_668625_IDX] = { 26745, 0x1, 0x4A, 0x95555, 0x8B5 }, + [ATHOS_LUT_CHAN_668750_IDX] = { 26750, 0x1, 0x4A, 0x9C71C, 0x8B5 }, + [ATHOS_LUT_CHAN_668875_IDX] = { 26755, 0x1, 0x4A, 0xA38E4, 0x8B6 }, + [ATHOS_LUT_CHAN_669000_IDX] = { 26760, 0x1, 0x4A, 0xAAAAB, 0x8B6 }, + [ATHOS_LUT_CHAN_669125_IDX] = { 26765, 0x1, 0x4A, 0xB1C72, 0x8B6 }, + [ATHOS_LUT_CHAN_669250_IDX] = { 26770, 0x1, 0x4A, 0xB8E39, 0x8B7 }, + [ATHOS_LUT_CHAN_669375_IDX] = { 26775, 0x1, 0x4A, 0xC0000, 0x8B7 }, + [ATHOS_LUT_CHAN_669500_IDX] = { 26780, 0x1, 0x4A, 0xC71C7, 0x8B8 }, + [ATHOS_LUT_CHAN_669625_IDX] = { 26785, 0x1, 0x4A, 0xCE38E, 0x8B8 }, + [ATHOS_LUT_CHAN_669750_IDX] = { 26790, 0x1, 0x4A, 0xD5555, 0x8B9 }, + [ATHOS_LUT_CHAN_669875_IDX] = { 26795, 0x1, 0x4A, 0xDC71C, 0x8B9 }, + [ATHOS_LUT_CHAN_670000_IDX] = { 26800, 0x1, 0x4A, 0xE38E4, 0x8B9 }, + [ATHOS_LUT_CHAN_670125_IDX] = { 26805, 0x1, 0x4A, 0xEAAAB, 0x8BA }, + [ATHOS_LUT_CHAN_670250_IDX] = { 26810, 0x1, 0x4A, 0xF1C72, 0x8BA }, + [ATHOS_LUT_CHAN_670375_IDX] = { 26815, 0x1, 0x4A, 0xF8E39, 0x8BB }, + [ATHOS_LUT_CHAN_670500_IDX] = { 26820, 0x1, 0x4A, 0x100000, 0x8BB }, + [ATHOS_LUT_CHAN_670625_IDX] = { 26825, 0x1, 0x4A, 0x1071C7, 0x8BB }, + [ATHOS_LUT_CHAN_670750_IDX] = { 26830, 0x1, 0x4A, 0x10E38E, 0x8BC }, + [ATHOS_LUT_CHAN_670875_IDX] = { 26835, 0x1, 0x4A, 0x115555, 0x8BC }, + [ATHOS_LUT_CHAN_671000_IDX] = { 26840, 0x1, 0x4A, 0x11C71C, 0x8BD }, + [ATHOS_LUT_CHAN_671125_IDX] = { 26845, 0x1, 0x4A, 0x1238E4, 0x8BD }, + [ATHOS_LUT_CHAN_671250_IDX] = { 26850, 0x1, 0x4A, 0x12AAAB, 0x8BE }, + [ATHOS_LUT_CHAN_671375_IDX] = { 26855, 0x1, 0x4A, 0x131C72, 0x8BE }, + [ATHOS_LUT_CHAN_671500_IDX] = { 26860, 0x1, 0x4A, 0x138E39, 0x8BE }, + [ATHOS_LUT_CHAN_671625_IDX] = { 26865, 0x1, 0x4A, 0x140000, 0x8BF }, + [ATHOS_LUT_CHAN_671750_IDX] = { 26870, 0x1, 0x4A, 0x1471C7, 0x8BF }, + [ATHOS_LUT_CHAN_671875_IDX] = { 26875, 0x1, 0x4A, 0x14E38E, 0x8C0 }, + [ATHOS_LUT_CHAN_672000_IDX] = { 26880, 0x1, 0x4A, 0x155555, 0x8C0 }, + [ATHOS_LUT_CHAN_672125_IDX] = { 26885, 0x1, 0x4A, 0x15C71C, 0x8C0 }, + [ATHOS_LUT_CHAN_672250_IDX] = { 26890, 0x1, 0x4A, 0x1638E4, 0x8C1 }, + [ATHOS_LUT_CHAN_672375_IDX] = { 26895, 0x1, 0x4A, 0x16AAAB, 0x8C1 }, + [ATHOS_LUT_CHAN_672500_IDX] = { 26900, 0x1, 0x4A, 0x171C72, 0x8C2 }, + [ATHOS_LUT_CHAN_672625_IDX] = { 26905, 0x1, 0x4A, 0x178E39, 0x8C2 }, + [ATHOS_LUT_CHAN_672750_IDX] = { 26910, 0x1, 0x4A, 0x180000, 0x8C3 }, + [ATHOS_LUT_CHAN_672875_IDX] = { 26915, 0x1, 0x4A, 0x1871C7, 0x8C3 }, + [ATHOS_LUT_CHAN_673000_IDX] = { 26920, 0x1, 0x4A, 0x18E38E, 0x8C3 }, + [ATHOS_LUT_CHAN_673125_IDX] = { 26925, 0x1, 0x4A, 0x195555, 0x8C4 }, + [ATHOS_LUT_CHAN_673250_IDX] = { 26930, 0x1, 0x4A, 0x19C71C, 0x8C4 }, + [ATHOS_LUT_CHAN_673375_IDX] = { 26935, 0x1, 0x4A, 0x1A38E4, 0x8C5 }, + [ATHOS_LUT_CHAN_673500_IDX] = { 26940, 0x1, 0x4A, 0x1AAAAB, 0x8C5 }, + [ATHOS_LUT_CHAN_673625_IDX] = { 26945, 0x1, 0x4A, 0x1B1C72, 0x8C5 }, + [ATHOS_LUT_CHAN_673750_IDX] = { 26950, 0x1, 0x4A, 0x1B8E39, 0x8C6 }, + [ATHOS_LUT_CHAN_673875_IDX] = { 26955, 0x1, 0x4A, 0x1C0000, 0x8C6 }, + [ATHOS_LUT_CHAN_674000_IDX] = { 26960, 0x1, 0x4A, 0x1C71C7, 0x8C7 }, + [ATHOS_LUT_CHAN_674125_IDX] = { 26965, 0x1, 0x4A, 0x1CE38E, 0x8C7 }, + [ATHOS_LUT_CHAN_674250_IDX] = { 26970, 0x1, 0x4A, 0x1D5555, 0x8C8 }, + [ATHOS_LUT_CHAN_674375_IDX] = { 26975, 0x1, 0x4A, 0x1DC71C, 0x8C8 }, + [ATHOS_LUT_CHAN_674500_IDX] = { 26980, 0x1, 0x4A, 0x1E38E4, 0x8C8 }, + [ATHOS_LUT_CHAN_674625_IDX] = { 26985, 0x1, 0x4A, 0x1EAAAB, 0x8C9 }, + [ATHOS_LUT_CHAN_674750_IDX] = { 26990, 0x1, 0x4A, 0x1F1C72, 0x8C9 }, + [ATHOS_LUT_CHAN_674875_IDX] = { 26995, 0x1, 0x4A, 0x1F8E39, 0x8CA }, + [ATHOS_LUT_CHAN_675000_IDX] = { 27000, 0x1, 0x4B, 0x0, 0x8CA }, + [ATHOS_LUT_CHAN_675125_IDX] = { 27005, 0x1, 0x4B, 0x71C7, 0x8CA }, + [ATHOS_LUT_CHAN_675250_IDX] = { 27010, 0x1, 0x4B, 0xE38E, 0x8CB }, + [ATHOS_LUT_CHAN_675375_IDX] = { 27015, 0x1, 0x4B, 0x15555, 0x8CB }, + [ATHOS_LUT_CHAN_675500_IDX] = { 27020, 0x1, 0x4B, 0x1C71C, 0x8CC }, + [ATHOS_LUT_CHAN_675625_IDX] = { 27025, 0x1, 0x4B, 0x238E4, 0x8CC }, + [ATHOS_LUT_CHAN_675750_IDX] = { 27030, 0x1, 0x4B, 0x2AAAB, 0x8CD }, + [ATHOS_LUT_CHAN_675875_IDX] = { 27035, 0x1, 0x4B, 0x31C72, 0x8CD }, + [ATHOS_LUT_CHAN_676000_IDX] = { 27040, 0x1, 0x4B, 0x38E39, 0x8CD }, + [ATHOS_LUT_CHAN_676125_IDX] = { 27045, 0x1, 0x4B, 0x40000, 0x8CE }, + [ATHOS_LUT_CHAN_676250_IDX] = { 27050, 0x1, 0x4B, 0x471C7, 0x8CE }, + [ATHOS_LUT_CHAN_676375_IDX] = { 27055, 0x1, 0x4B, 0x4E38E, 0x8CF }, + [ATHOS_LUT_CHAN_676500_IDX] = { 27060, 0x1, 0x4B, 0x55555, 0x8CF }, + [ATHOS_LUT_CHAN_676625_IDX] = { 27065, 0x1, 0x4B, 0x5C71C, 0x8CF }, + [ATHOS_LUT_CHAN_676750_IDX] = { 27070, 0x1, 0x4B, 0x638E4, 0x8D0 }, + [ATHOS_LUT_CHAN_676875_IDX] = { 27075, 0x1, 0x4B, 0x6AAAB, 0x8D0 }, + [ATHOS_LUT_CHAN_677000_IDX] = { 27080, 0x1, 0x4B, 0x71C72, 0x8D1 }, + [ATHOS_LUT_CHAN_677125_IDX] = { 27085, 0x1, 0x4B, 0x78E39, 0x8D1 }, + [ATHOS_LUT_CHAN_677250_IDX] = { 27090, 0x1, 0x4B, 0x80000, 0x8D2 }, + [ATHOS_LUT_CHAN_677375_IDX] = { 27095, 0x1, 0x4B, 0x871C7, 0x8D2 }, + [ATHOS_LUT_CHAN_677500_IDX] = { 27100, 0x1, 0x4B, 0x8E38E, 0x8D2 }, + [ATHOS_LUT_CHAN_677625_IDX] = { 27105, 0x1, 0x4B, 0x95555, 0x8D3 }, + [ATHOS_LUT_CHAN_677750_IDX] = { 27110, 0x1, 0x4B, 0x9C71C, 0x8D3 }, + [ATHOS_LUT_CHAN_677875_IDX] = { 27115, 0x1, 0x4B, 0xA38E4, 0x8D4 }, + [ATHOS_LUT_CHAN_678000_IDX] = { 27120, 0x1, 0x4B, 0xAAAAB, 0x8D4 }, + [ATHOS_LUT_CHAN_678125_IDX] = { 27125, 0x1, 0x4B, 0xB1C72, 0x8D4 }, + [ATHOS_LUT_CHAN_678250_IDX] = { 27130, 0x1, 0x4B, 0xB8E39, 0x8D5 }, + [ATHOS_LUT_CHAN_678375_IDX] = { 27135, 0x1, 0x4B, 0xC0000, 0x8D5 }, + [ATHOS_LUT_CHAN_678500_IDX] = { 27140, 0x1, 0x4B, 0xC71C7, 0x8D6 }, + [ATHOS_LUT_CHAN_678625_IDX] = { 27145, 0x1, 0x4B, 0xCE38E, 0x8D6 }, + [ATHOS_LUT_CHAN_678750_IDX] = { 27150, 0x1, 0x4B, 0xD5555, 0x8D7 }, + [ATHOS_LUT_CHAN_678875_IDX] = { 27155, 0x1, 0x4B, 0xDC71C, 0x8D7 }, + [ATHOS_LUT_CHAN_679000_IDX] = { 27160, 0x1, 0x4B, 0xE38E4, 0x8D7 }, + [ATHOS_LUT_CHAN_679125_IDX] = { 27165, 0x1, 0x4B, 0xEAAAB, 0x8D8 }, + [ATHOS_LUT_CHAN_679250_IDX] = { 27170, 0x1, 0x4B, 0xF1C72, 0x8D8 }, + [ATHOS_LUT_CHAN_679375_IDX] = { 27175, 0x1, 0x4B, 0xF8E39, 0x8D9 }, + [ATHOS_LUT_CHAN_679500_IDX] = { 27180, 0x1, 0x4B, 0x100000, 0x8D9 }, + [ATHOS_LUT_CHAN_679625_IDX] = { 27185, 0x1, 0x4B, 0x1071C7, 0x8D9 }, + [ATHOS_LUT_CHAN_679750_IDX] = { 27190, 0x1, 0x4B, 0x10E38E, 0x8DA }, + [ATHOS_LUT_CHAN_679875_IDX] = { 27195, 0x1, 0x4B, 0x115555, 0x8DA }, + [ATHOS_LUT_CHAN_680000_IDX] = { 27200, 0x1, 0x4B, 0x11C71C, 0x8DB }, + [ATHOS_LUT_CHAN_680125_IDX] = { 27205, 0x1, 0x4B, 0x1238E4, 0x8DB }, + [ATHOS_LUT_CHAN_680250_IDX] = { 27210, 0x1, 0x4B, 0x12AAAB, 0x8DC }, + [ATHOS_LUT_CHAN_680375_IDX] = { 27215, 0x1, 0x4B, 0x131C72, 0x8DC }, + [ATHOS_LUT_CHAN_680500_IDX] = { 27220, 0x1, 0x4B, 0x138E39, 0x8DC }, + [ATHOS_LUT_CHAN_680625_IDX] = { 27225, 0x1, 0x4B, 0x140000, 0x8DD }, + [ATHOS_LUT_CHAN_680750_IDX] = { 27230, 0x1, 0x4B, 0x1471C7, 0x8DD }, + [ATHOS_LUT_CHAN_680875_IDX] = { 27235, 0x1, 0x4B, 0x14E38E, 0x8DE }, + [ATHOS_LUT_CHAN_681000_IDX] = { 27240, 0x1, 0x4B, 0x155555, 0x8DE }, + [ATHOS_LUT_CHAN_681125_IDX] = { 27245, 0x1, 0x4B, 0x15C71C, 0x8DE }, + [ATHOS_LUT_CHAN_681250_IDX] = { 27250, 0x1, 0x4B, 0x1638E4, 0x8DF }, + [ATHOS_LUT_CHAN_681375_IDX] = { 27255, 0x1, 0x4B, 0x16AAAB, 0x8DF }, + [ATHOS_LUT_CHAN_681500_IDX] = { 27260, 0x1, 0x4B, 0x171C72, 0x8E0 }, + [ATHOS_LUT_CHAN_681625_IDX] = { 27265, 0x1, 0x4B, 0x178E39, 0x8E0 }, + [ATHOS_LUT_CHAN_681750_IDX] = { 27270, 0x1, 0x4B, 0x180000, 0x8E1 }, + [ATHOS_LUT_CHAN_681875_IDX] = { 27275, 0x1, 0x4B, 0x1871C7, 0x8E1 }, + [ATHOS_LUT_CHAN_682000_IDX] = { 27280, 0x1, 0x4B, 0x18E38E, 0x8E1 }, + [ATHOS_LUT_CHAN_682125_IDX] = { 27285, 0x1, 0x4B, 0x195555, 0x8E2 }, + [ATHOS_LUT_CHAN_682250_IDX] = { 27290, 0x1, 0x4B, 0x19C71C, 0x8E2 }, + [ATHOS_LUT_CHAN_682375_IDX] = { 27295, 0x1, 0x4B, 0x1A38E4, 0x8E3 }, + [ATHOS_LUT_CHAN_682500_IDX] = { 27300, 0x1, 0x4B, 0x1AAAAB, 0x8E3 }, + [ATHOS_LUT_CHAN_682625_IDX] = { 27305, 0x1, 0x4B, 0x1B1C72, 0x8E3 }, + [ATHOS_LUT_CHAN_682750_IDX] = { 27310, 0x1, 0x4B, 0x1B8E39, 0x8E4 }, + [ATHOS_LUT_CHAN_682875_IDX] = { 27315, 0x1, 0x4B, 0x1C0000, 0x8E4 }, + [ATHOS_LUT_CHAN_683000_IDX] = { 27320, 0x1, 0x4B, 0x1C71C7, 0x8E5 }, + [ATHOS_LUT_CHAN_683125_IDX] = { 27325, 0x1, 0x4B, 0x1CE38E, 0x8E5 }, + [ATHOS_LUT_CHAN_683250_IDX] = { 27330, 0x1, 0x4B, 0x1D5555, 0x8E6 }, + [ATHOS_LUT_CHAN_683375_IDX] = { 27335, 0x1, 0x4B, 0x1DC71C, 0x8E6 }, + [ATHOS_LUT_CHAN_683500_IDX] = { 27340, 0x1, 0x4B, 0x1E38E4, 0x8E6 }, + [ATHOS_LUT_CHAN_683625_IDX] = { 27345, 0x1, 0x4B, 0x1EAAAB, 0x8E7 }, + [ATHOS_LUT_CHAN_683750_IDX] = { 27350, 0x1, 0x4B, 0x1F1C72, 0x8E7 }, + [ATHOS_LUT_CHAN_683875_IDX] = { 27355, 0x1, 0x4B, 0x1F8E39, 0x8E8 }, + [ATHOS_LUT_CHAN_684000_IDX] = { 27360, 0x1, 0x4C, 0x0, 0x8E8 }, + [ATHOS_LUT_CHAN_684125_IDX] = { 27365, 0x1, 0x4C, 0x71C7, 0x8E8 }, + [ATHOS_LUT_CHAN_684250_IDX] = { 27370, 0x1, 0x4C, 0xE38E, 0x8E9 }, + [ATHOS_LUT_CHAN_684375_IDX] = { 27375, 0x1, 0x4C, 0x15555, 0x8E9 }, + [ATHOS_LUT_CHAN_684500_IDX] = { 27380, 0x1, 0x4C, 0x1C71C, 0x8EA }, + [ATHOS_LUT_CHAN_684625_IDX] = { 27385, 0x1, 0x4C, 0x238E4, 0x8EA }, + [ATHOS_LUT_CHAN_684750_IDX] = { 27390, 0x1, 0x4C, 0x2AAAB, 0x8EB }, + [ATHOS_LUT_CHAN_684875_IDX] = { 27395, 0x1, 0x4C, 0x31C72, 0x8EB }, + [ATHOS_LUT_CHAN_685000_IDX] = { 27400, 0x1, 0x4C, 0x38E39, 0x8EB }, + [ATHOS_LUT_CHAN_685125_IDX] = { 27405, 0x1, 0x4C, 0x40000, 0x8EC }, + [ATHOS_LUT_CHAN_685250_IDX] = { 27410, 0x1, 0x4C, 0x471C7, 0x8EC }, + [ATHOS_LUT_CHAN_685375_IDX] = { 27415, 0x1, 0x4C, 0x4E38E, 0x8ED }, + [ATHOS_LUT_CHAN_685500_IDX] = { 27420, 0x1, 0x4C, 0x55555, 0x8ED }, + [ATHOS_LUT_CHAN_685625_IDX] = { 27425, 0x1, 0x4C, 0x5C71C, 0x8ED }, + [ATHOS_LUT_CHAN_685750_IDX] = { 27430, 0x1, 0x4C, 0x638E4, 0x8EE }, + [ATHOS_LUT_CHAN_685875_IDX] = { 27435, 0x1, 0x4C, 0x6AAAB, 0x8EE }, + [ATHOS_LUT_CHAN_686000_IDX] = { 27440, 0x1, 0x4C, 0x71C72, 0x8EF }, + [ATHOS_LUT_CHAN_686125_IDX] = { 27445, 0x1, 0x4C, 0x78E39, 0x8EF }, + [ATHOS_LUT_CHAN_686250_IDX] = { 27450, 0x1, 0x4C, 0x80000, 0x8F0 }, + [ATHOS_LUT_CHAN_686375_IDX] = { 27455, 0x1, 0x4C, 0x871C7, 0x8F0 }, + [ATHOS_LUT_CHAN_686500_IDX] = { 27460, 0x1, 0x4C, 0x8E38E, 0x8F0 }, + [ATHOS_LUT_CHAN_686625_IDX] = { 27465, 0x1, 0x4C, 0x95555, 0x8F1 }, + [ATHOS_LUT_CHAN_686750_IDX] = { 27470, 0x1, 0x4C, 0x9C71C, 0x8F1 }, + [ATHOS_LUT_CHAN_686875_IDX] = { 27475, 0x1, 0x4C, 0xA38E4, 0x8F2 }, + [ATHOS_LUT_CHAN_687000_IDX] = { 27480, 0x1, 0x4C, 0xAAAAB, 0x8F2 }, + [ATHOS_LUT_CHAN_687125_IDX] = { 27485, 0x1, 0x4C, 0xB1C72, 0x8F2 }, + [ATHOS_LUT_CHAN_687250_IDX] = { 27490, 0x1, 0x4C, 0xB8E39, 0x8F3 }, + [ATHOS_LUT_CHAN_687375_IDX] = { 27495, 0x1, 0x4C, 0xC0000, 0x8F3 }, + [ATHOS_LUT_CHAN_687500_IDX] = { 27500, 0x1, 0x4C, 0xC71C7, 0x8F4 }, + [ATHOS_LUT_CHAN_687625_IDX] = { 27505, 0x1, 0x4C, 0xCE38E, 0x8F4 }, + [ATHOS_LUT_CHAN_687750_IDX] = { 27510, 0x1, 0x4C, 0xD5555, 0x8F5 }, + [ATHOS_LUT_CHAN_687875_IDX] = { 27515, 0x1, 0x4C, 0xDC71C, 0x8F5 }, + [ATHOS_LUT_CHAN_688000_IDX] = { 27520, 0x1, 0x4C, 0xE38E4, 0x8F5 }, + [ATHOS_LUT_CHAN_688125_IDX] = { 27525, 0x1, 0x4C, 0xEAAAB, 0x8F6 }, + [ATHOS_LUT_CHAN_688250_IDX] = { 27530, 0x1, 0x4C, 0xF1C72, 0x8F6 }, + [ATHOS_LUT_CHAN_688375_IDX] = { 27535, 0x1, 0x4C, 0xF8E39, 0x8F7 }, + [ATHOS_LUT_CHAN_688500_IDX] = { 27540, 0x1, 0x4C, 0x100000, 0x8F7 }, + [ATHOS_LUT_CHAN_688625_IDX] = { 27545, 0x1, 0x4C, 0x1071C7, 0x8F7 }, + [ATHOS_LUT_CHAN_688750_IDX] = { 27550, 0x1, 0x4C, 0x10E38E, 0x8F8 }, + [ATHOS_LUT_CHAN_688875_IDX] = { 27555, 0x1, 0x4C, 0x115555, 0x8F8 }, + [ATHOS_LUT_CHAN_689000_IDX] = { 27560, 0x1, 0x4C, 0x11C71C, 0x8F9 }, + [ATHOS_LUT_CHAN_689125_IDX] = { 27565, 0x1, 0x4C, 0x1238E4, 0x8F9 }, + [ATHOS_LUT_CHAN_689250_IDX] = { 27570, 0x1, 0x4C, 0x12AAAB, 0x8FA }, + [ATHOS_LUT_CHAN_689375_IDX] = { 27575, 0x1, 0x4C, 0x131C72, 0x8FA }, + [ATHOS_LUT_CHAN_689500_IDX] = { 27580, 0x1, 0x4C, 0x138E39, 0x8FA }, + [ATHOS_LUT_CHAN_689625_IDX] = { 27585, 0x1, 0x4C, 0x140000, 0x8FB }, + [ATHOS_LUT_CHAN_689750_IDX] = { 27590, 0x1, 0x4C, 0x1471C7, 0x8FB }, + [ATHOS_LUT_CHAN_689875_IDX] = { 27595, 0x1, 0x4C, 0x14E38E, 0x8FC }, + [ATHOS_LUT_CHAN_690000_IDX] = { 27600, 0x1, 0x4C, 0x155555, 0x8FC }, + [ATHOS_LUT_CHAN_690125_IDX] = { 27605, 0x1, 0x4C, 0x15C71C, 0x8FC }, + [ATHOS_LUT_CHAN_690250_IDX] = { 27610, 0x1, 0x4C, 0x1638E4, 0x8FD }, + [ATHOS_LUT_CHAN_690375_IDX] = { 27615, 0x1, 0x4C, 0x16AAAB, 0x8FD }, + [ATHOS_LUT_CHAN_690500_IDX] = { 27620, 0x1, 0x4C, 0x171C72, 0x8FE }, + [ATHOS_LUT_CHAN_690625_IDX] = { 27625, 0x1, 0x4C, 0x178E39, 0x8FE }, + [ATHOS_LUT_CHAN_690750_IDX] = { 27630, 0x1, 0x4C, 0x180000, 0x8FF }, + [ATHOS_LUT_CHAN_690875_IDX] = { 27635, 0x1, 0x4C, 0x1871C7, 0x8FF }, + [ATHOS_LUT_CHAN_691000_IDX] = { 27640, 0x1, 0x4C, 0x18E38E, 0x8FF }, + [ATHOS_LUT_CHAN_691125_IDX] = { 27645, 0x1, 0x4C, 0x195555, 0x900 }, + [ATHOS_LUT_CHAN_691250_IDX] = { 27650, 0x1, 0x4C, 0x19C71C, 0x900 }, + [ATHOS_LUT_CHAN_691375_IDX] = { 27655, 0x1, 0x4C, 0x1A38E4, 0x901 }, + [ATHOS_LUT_CHAN_691500_IDX] = { 27660, 0x1, 0x4C, 0x1AAAAB, 0x901 }, + [ATHOS_LUT_CHAN_691625_IDX] = { 27665, 0x1, 0x4C, 0x1B1C72, 0x901 }, + [ATHOS_LUT_CHAN_691750_IDX] = { 27670, 0x1, 0x4C, 0x1B8E39, 0x902 }, + [ATHOS_LUT_CHAN_691875_IDX] = { 27675, 0x1, 0x4C, 0x1C0000, 0x902 }, + [ATHOS_LUT_CHAN_692000_IDX] = { 27680, 0x1, 0x4C, 0x1C71C7, 0x903 }, + [ATHOS_LUT_CHAN_692125_IDX] = { 27685, 0x1, 0x4C, 0x1CE38E, 0x903 }, + [ATHOS_LUT_CHAN_692250_IDX] = { 27690, 0x1, 0x4C, 0x1D5555, 0x904 }, + [ATHOS_LUT_CHAN_692375_IDX] = { 27695, 0x1, 0x4C, 0x1DC71C, 0x904 }, + [ATHOS_LUT_CHAN_692500_IDX] = { 27700, 0x1, 0x4C, 0x1E38E4, 0x904 }, + [ATHOS_LUT_CHAN_692625_IDX] = { 27705, 0x1, 0x4C, 0x1EAAAB, 0x905 }, + [ATHOS_LUT_CHAN_692750_IDX] = { 27710, 0x1, 0x4C, 0x1F1C72, 0x905 }, + [ATHOS_LUT_CHAN_692875_IDX] = { 27715, 0x1, 0x4C, 0x1F8E39, 0x906 }, + [ATHOS_LUT_CHAN_693000_IDX] = { 27720, 0x1, 0x4D, 0x0, 0x906 }, + [ATHOS_LUT_CHAN_693125_IDX] = { 27725, 0x1, 0x4D, 0x71C7, 0x906 }, + [ATHOS_LUT_CHAN_693250_IDX] = { 27730, 0x1, 0x4D, 0xE38E, 0x907 }, + [ATHOS_LUT_CHAN_693375_IDX] = { 27735, 0x1, 0x4D, 0x15555, 0x907 }, + [ATHOS_LUT_CHAN_693500_IDX] = { 27740, 0x1, 0x4D, 0x1C71C, 0x908 }, + [ATHOS_LUT_CHAN_693625_IDX] = { 27745, 0x1, 0x4D, 0x238E4, 0x908 }, + [ATHOS_LUT_CHAN_693750_IDX] = { 27750, 0x1, 0x4D, 0x2AAAB, 0x909 }, + [ATHOS_LUT_CHAN_693875_IDX] = { 27755, 0x1, 0x4D, 0x31C72, 0x909 }, + [ATHOS_LUT_CHAN_694000_IDX] = { 27760, 0x1, 0x4D, 0x38E39, 0x909 }, + [ATHOS_LUT_CHAN_694125_IDX] = { 27765, 0x1, 0x4D, 0x40000, 0x90A }, + [ATHOS_LUT_CHAN_694250_IDX] = { 27770, 0x1, 0x4D, 0x471C7, 0x90A }, + [ATHOS_LUT_CHAN_694375_IDX] = { 27775, 0x1, 0x4D, 0x4E38E, 0x90B }, + [ATHOS_LUT_CHAN_694500_IDX] = { 27780, 0x1, 0x4D, 0x55555, 0x90B }, + [ATHOS_LUT_CHAN_694625_IDX] = { 27785, 0x1, 0x4D, 0x5C71C, 0x90B }, + [ATHOS_LUT_CHAN_694750_IDX] = { 27790, 0x1, 0x4D, 0x638E4, 0x90C }, + [ATHOS_LUT_CHAN_694875_IDX] = { 27795, 0x1, 0x4D, 0x6AAAB, 0x90C }, + [ATHOS_LUT_CHAN_695000_IDX] = { 27800, 0x1, 0x4D, 0x71C72, 0x90D }, + [ATHOS_LUT_CHAN_695125_IDX] = { 27805, 0x1, 0x4D, 0x78E39, 0x90D }, + [ATHOS_LUT_CHAN_695250_IDX] = { 27810, 0x1, 0x4D, 0x80000, 0x90E }, + [ATHOS_LUT_CHAN_695375_IDX] = { 27815, 0x1, 0x4D, 0x871C7, 0x90E }, + [ATHOS_LUT_CHAN_695500_IDX] = { 27820, 0x1, 0x4D, 0x8E38E, 0x90E }, + [ATHOS_LUT_CHAN_695625_IDX] = { 27825, 0x1, 0x4D, 0x95555, 0x90F }, + [ATHOS_LUT_CHAN_695750_IDX] = { 27830, 0x1, 0x4D, 0x9C71C, 0x90F }, + [ATHOS_LUT_CHAN_695875_IDX] = { 27835, 0x1, 0x4D, 0xA38E4, 0x910 }, + [ATHOS_LUT_CHAN_696000_IDX] = { 27840, 0x1, 0x4D, 0xAAAAB, 0x910 }, + [ATHOS_LUT_CHAN_696125_IDX] = { 27845, 0x1, 0x4D, 0xB1C72, 0x910 }, + [ATHOS_LUT_CHAN_696250_IDX] = { 27850, 0x1, 0x4D, 0xB8E39, 0x911 }, + [ATHOS_LUT_CHAN_696375_IDX] = { 27855, 0x1, 0x4D, 0xC0000, 0x911 }, + [ATHOS_LUT_CHAN_696500_IDX] = { 27860, 0x1, 0x4D, 0xC71C7, 0x912 }, + [ATHOS_LUT_CHAN_696625_IDX] = { 27865, 0x1, 0x4D, 0xCE38E, 0x912 }, + [ATHOS_LUT_CHAN_696750_IDX] = { 27870, 0x1, 0x4D, 0xD5555, 0x913 }, + [ATHOS_LUT_CHAN_696875_IDX] = { 27875, 0x1, 0x4D, 0xDC71C, 0x913 }, + [ATHOS_LUT_CHAN_697000_IDX] = { 27880, 0x1, 0x4D, 0xE38E4, 0x913 }, + [ATHOS_LUT_CHAN_697125_IDX] = { 27885, 0x1, 0x4D, 0xEAAAB, 0x914 }, + [ATHOS_LUT_CHAN_697250_IDX] = { 27890, 0x1, 0x4D, 0xF1C72, 0x914 }, + [ATHOS_LUT_CHAN_697375_IDX] = { 27895, 0x1, 0x4D, 0xF8E39, 0x915 }, + [ATHOS_LUT_CHAN_697500_IDX] = { 27900, 0x1, 0x4D, 0x100000, 0x915 }, + [ATHOS_LUT_CHAN_697625_IDX] = { 27905, 0x1, 0x4D, 0x1071C7, 0x915 }, + [ATHOS_LUT_CHAN_697750_IDX] = { 27910, 0x1, 0x4D, 0x10E38E, 0x916 }, + [ATHOS_LUT_CHAN_697875_IDX] = { 27915, 0x1, 0x4D, 0x115555, 0x916 }, + [ATHOS_LUT_CHAN_698000_IDX] = { 27920, 0x1, 0x4D, 0x11C71C, 0x917 }, + [ATHOS_LUT_CHAN_698125_IDX] = { 27925, 0x1, 0x4D, 0x1238E4, 0x917 }, + [ATHOS_LUT_CHAN_698250_IDX] = { 27930, 0x1, 0x4D, 0x12AAAB, 0x918 }, + [ATHOS_LUT_CHAN_698375_IDX] = { 27935, 0x1, 0x4D, 0x131C72, 0x918 }, + [ATHOS_LUT_CHAN_698500_IDX] = { 27940, 0x1, 0x4D, 0x138E39, 0x918 }, + [ATHOS_LUT_CHAN_698625_IDX] = { 27945, 0x1, 0x4D, 0x140000, 0x919 }, + [ATHOS_LUT_CHAN_698750_IDX] = { 27950, 0x1, 0x4D, 0x1471C7, 0x919 }, + [ATHOS_LUT_CHAN_698875_IDX] = { 27955, 0x1, 0x4D, 0x14E38E, 0x91A }, + [ATHOS_LUT_CHAN_699000_IDX] = { 27960, 0x1, 0x4D, 0x155555, 0x91A }, + [ATHOS_LUT_CHAN_699125_IDX] = { 27965, 0x1, 0x4D, 0x15C71C, 0x91A }, + [ATHOS_LUT_CHAN_699250_IDX] = { 27970, 0x1, 0x4D, 0x1638E4, 0x91B }, + [ATHOS_LUT_CHAN_699375_IDX] = { 27975, 0x1, 0x4D, 0x16AAAB, 0x91B }, + [ATHOS_LUT_CHAN_699500_IDX] = { 27980, 0x1, 0x4D, 0x171C72, 0x91C }, + [ATHOS_LUT_CHAN_699625_IDX] = { 27985, 0x1, 0x4D, 0x178E39, 0x91C }, + [ATHOS_LUT_CHAN_699750_IDX] = { 27990, 0x1, 0x4D, 0x180000, 0x91D }, + [ATHOS_LUT_CHAN_699875_IDX] = { 27995, 0x1, 0x4D, 0x1871C7, 0x91D }, + [ATHOS_LUT_CHAN_700000_IDX] = { 28000, 0x1, 0x4D, 0x18E38E, 0x91D }, + [ATHOS_LUT_CHAN_700125_IDX] = { 28005, 0x1, 0x4D, 0x195555, 0x91E }, + [ATHOS_LUT_CHAN_700250_IDX] = { 28010, 0x1, 0x4D, 0x19C71C, 0x91E }, + [ATHOS_LUT_CHAN_700375_IDX] = { 28015, 0x1, 0x4D, 0x1A38E4, 0x91F }, + [ATHOS_LUT_CHAN_700500_IDX] = { 28020, 0x1, 0x4D, 0x1AAAAB, 0x91F }, + [ATHOS_LUT_CHAN_700625_IDX] = { 28025, 0x1, 0x4D, 0x1B1C72, 0x91F }, + [ATHOS_LUT_CHAN_700750_IDX] = { 28030, 0x1, 0x4D, 0x1B8E39, 0x920 }, + [ATHOS_LUT_CHAN_700875_IDX] = { 28035, 0x1, 0x4D, 0x1C0000, 0x920 }, + [ATHOS_LUT_CHAN_701000_IDX] = { 28040, 0x1, 0x4D, 0x1C71C7, 0x921 }, + [ATHOS_LUT_CHAN_701125_IDX] = { 28045, 0x1, 0x4D, 0x1CE38E, 0x921 }, + [ATHOS_LUT_CHAN_701250_IDX] = { 28050, 0x1, 0x4D, 0x1D5555, 0x922 }, + [ATHOS_LUT_CHAN_701375_IDX] = { 28055, 0x1, 0x4D, 0x1DC71C, 0x922 }, + [ATHOS_LUT_CHAN_701500_IDX] = { 28060, 0x1, 0x4D, 0x1E38E4, 0x922 }, + [ATHOS_LUT_CHAN_701625_IDX] = { 28065, 0x1, 0x4D, 0x1EAAAB, 0x923 }, + [ATHOS_LUT_CHAN_701750_IDX] = { 28070, 0x1, 0x4D, 0x1F1C72, 0x923 }, + [ATHOS_LUT_CHAN_701875_IDX] = { 28075, 0x1, 0x4D, 0x1F8E39, 0x924 }, + [ATHOS_LUT_CHAN_702000_IDX] = { 28080, 0x1, 0x4E, 0x0, 0x924 }, + [ATHOS_LUT_CHAN_702125_IDX] = { 28085, 0x1, 0x4E, 0x71C7, 0x924 }, + [ATHOS_LUT_CHAN_702250_IDX] = { 28090, 0x1, 0x4E, 0xE38E, 0x925 }, + [ATHOS_LUT_CHAN_702375_IDX] = { 28095, 0x1, 0x4E, 0x15555, 0x925 }, + [ATHOS_LUT_CHAN_702500_IDX] = { 28100, 0x1, 0x4E, 0x1C71C, 0x926 }, + [ATHOS_LUT_CHAN_702625_IDX] = { 28105, 0x1, 0x4E, 0x238E4, 0x926 }, + [ATHOS_LUT_CHAN_702750_IDX] = { 28110, 0x1, 0x4E, 0x2AAAB, 0x927 }, + [ATHOS_LUT_CHAN_702875_IDX] = { 28115, 0x1, 0x4E, 0x31C72, 0x927 }, + [ATHOS_LUT_CHAN_703000_IDX] = { 28120, 0x1, 0x4E, 0x38E39, 0x927 }, + [ATHOS_LUT_CHAN_703125_IDX] = { 28125, 0x1, 0x4E, 0x40000, 0x928 }, + [ATHOS_LUT_CHAN_703250_IDX] = { 28130, 0x1, 0x4E, 0x471C7, 0x928 }, + [ATHOS_LUT_CHAN_703375_IDX] = { 28135, 0x1, 0x4E, 0x4E38E, 0x929 }, + [ATHOS_LUT_CHAN_703500_IDX] = { 28140, 0x1, 0x4E, 0x55555, 0x929 }, + [ATHOS_LUT_CHAN_703625_IDX] = { 28145, 0x1, 0x4E, 0x5C71C, 0x929 }, + [ATHOS_LUT_CHAN_703750_IDX] = { 28150, 0x1, 0x4E, 0x638E4, 0x92A }, + [ATHOS_LUT_CHAN_703875_IDX] = { 28155, 0x1, 0x4E, 0x6AAAB, 0x92A }, + [ATHOS_LUT_CHAN_704000_IDX] = { 28160, 0x1, 0x4E, 0x71C72, 0x92B }, + [ATHOS_LUT_CHAN_704125_IDX] = { 28165, 0x1, 0x4E, 0x78E39, 0x92B }, + [ATHOS_LUT_CHAN_704250_IDX] = { 28170, 0x1, 0x4E, 0x80000, 0x92C }, + [ATHOS_LUT_CHAN_704375_IDX] = { 28175, 0x1, 0x4E, 0x871C7, 0x92C }, + [ATHOS_LUT_CHAN_704500_IDX] = { 28180, 0x1, 0x4E, 0x8E38E, 0x92C }, + [ATHOS_LUT_CHAN_704625_IDX] = { 28185, 0x1, 0x4E, 0x95555, 0x92D }, + [ATHOS_LUT_CHAN_704750_IDX] = { 28190, 0x1, 0x4E, 0x9C71C, 0x92D }, + [ATHOS_LUT_CHAN_704875_IDX] = { 28195, 0x1, 0x4E, 0xA38E4, 0x92E }, + [ATHOS_LUT_CHAN_705000_IDX] = { 28200, 0x1, 0x4E, 0xAAAAB, 0x92E }, + [ATHOS_LUT_CHAN_705125_IDX] = { 28205, 0x1, 0x4E, 0xB1C72, 0x92E }, + [ATHOS_LUT_CHAN_705250_IDX] = { 28210, 0x1, 0x4E, 0xB8E39, 0x92F }, + [ATHOS_LUT_CHAN_705375_IDX] = { 28215, 0x1, 0x4E, 0xC0000, 0x92F }, + [ATHOS_LUT_CHAN_705500_IDX] = { 28220, 0x1, 0x4E, 0xC71C7, 0x930 }, + [ATHOS_LUT_CHAN_705625_IDX] = { 28225, 0x1, 0x4E, 0xCE38E, 0x930 }, + [ATHOS_LUT_CHAN_705750_IDX] = { 28230, 0x1, 0x4E, 0xD5555, 0x931 }, + [ATHOS_LUT_CHAN_705875_IDX] = { 28235, 0x1, 0x4E, 0xDC71C, 0x931 }, + [ATHOS_LUT_CHAN_706000_IDX] = { 28240, 0x1, 0x4E, 0xE38E4, 0x931 }, + [ATHOS_LUT_CHAN_706125_IDX] = { 28245, 0x1, 0x4E, 0xEAAAB, 0x932 }, + [ATHOS_LUT_CHAN_706250_IDX] = { 28250, 0x1, 0x4E, 0xF1C72, 0x932 }, + [ATHOS_LUT_CHAN_706375_IDX] = { 28255, 0x1, 0x4E, 0xF8E39, 0x933 }, + [ATHOS_LUT_CHAN_706500_IDX] = { 28260, 0x1, 0x4E, 0x100000, 0x933 }, + [ATHOS_LUT_CHAN_706625_IDX] = { 28265, 0x1, 0x4E, 0x1071C7, 0x933 }, + [ATHOS_LUT_CHAN_706750_IDX] = { 28270, 0x1, 0x4E, 0x10E38E, 0x934 }, + [ATHOS_LUT_CHAN_706875_IDX] = { 28275, 0x1, 0x4E, 0x115555, 0x934 }, + [ATHOS_LUT_CHAN_707000_IDX] = { 28280, 0x1, 0x4E, 0x11C71C, 0x935 }, + [ATHOS_LUT_CHAN_707125_IDX] = { 28285, 0x1, 0x4E, 0x1238E4, 0x935 }, + [ATHOS_LUT_CHAN_707250_IDX] = { 28290, 0x1, 0x4E, 0x12AAAB, 0x936 }, + [ATHOS_LUT_CHAN_707375_IDX] = { 28295, 0x1, 0x4E, 0x131C72, 0x936 }, + [ATHOS_LUT_CHAN_707500_IDX] = { 28300, 0x1, 0x4E, 0x138E39, 0x936 }, + [ATHOS_LUT_CHAN_707625_IDX] = { 28305, 0x1, 0x4E, 0x140000, 0x937 }, + [ATHOS_LUT_CHAN_707750_IDX] = { 28310, 0x1, 0x4E, 0x1471C7, 0x937 }, + [ATHOS_LUT_CHAN_707875_IDX] = { 28315, 0x1, 0x4E, 0x14E38E, 0x938 }, + [ATHOS_LUT_CHAN_708000_IDX] = { 28320, 0x1, 0x4E, 0x155555, 0x938 }, + [ATHOS_LUT_CHAN_708125_IDX] = { 28325, 0x1, 0x4E, 0x15C71C, 0x938 }, + [ATHOS_LUT_CHAN_708250_IDX] = { 28330, 0x1, 0x4E, 0x1638E4, 0x939 }, + [ATHOS_LUT_CHAN_708375_IDX] = { 28335, 0x1, 0x4E, 0x16AAAB, 0x939 }, + [ATHOS_LUT_CHAN_708500_IDX] = { 28340, 0x1, 0x4E, 0x171C72, 0x93A }, + [ATHOS_LUT_CHAN_708625_IDX] = { 28345, 0x1, 0x4E, 0x178E39, 0x93A }, + [ATHOS_LUT_CHAN_708750_IDX] = { 28350, 0x1, 0x4E, 0x180000, 0x93B }, + [ATHOS_LUT_CHAN_708875_IDX] = { 28355, 0x1, 0x4E, 0x1871C7, 0x93B }, + [ATHOS_LUT_CHAN_709000_IDX] = { 28360, 0x1, 0x4E, 0x18E38E, 0x93B }, + [ATHOS_LUT_CHAN_709125_IDX] = { 28365, 0x1, 0x4E, 0x195555, 0x93C }, + [ATHOS_LUT_CHAN_709250_IDX] = { 28370, 0x1, 0x4E, 0x19C71C, 0x93C }, + [ATHOS_LUT_CHAN_709375_IDX] = { 28375, 0x1, 0x4E, 0x1A38E4, 0x93D }, + [ATHOS_LUT_CHAN_709500_IDX] = { 28380, 0x1, 0x4E, 0x1AAAAB, 0x93D }, + [ATHOS_LUT_CHAN_709625_IDX] = { 28385, 0x1, 0x4E, 0x1B1C72, 0x93D }, + [ATHOS_LUT_CHAN_709750_IDX] = { 28390, 0x1, 0x4E, 0x1B8E39, 0x93E }, + [ATHOS_LUT_CHAN_709875_IDX] = { 28395, 0x1, 0x4E, 0x1C0000, 0x93E }, + [ATHOS_LUT_CHAN_710000_IDX] = { 28400, 0x1, 0x4E, 0x1C71C7, 0x93F }, + [ATHOS_LUT_CHAN_710125_IDX] = { 28405, 0x1, 0x4E, 0x1CE38E, 0x93F }, + [ATHOS_LUT_CHAN_710250_IDX] = { 28410, 0x1, 0x4E, 0x1D5555, 0x940 }, + [ATHOS_LUT_CHAN_710375_IDX] = { 28415, 0x1, 0x4E, 0x1DC71C, 0x940 }, + [ATHOS_LUT_CHAN_710500_IDX] = { 28420, 0x1, 0x4E, 0x1E38E4, 0x940 }, + [ATHOS_LUT_CHAN_710625_IDX] = { 28425, 0x1, 0x4E, 0x1EAAAB, 0x941 }, + [ATHOS_LUT_CHAN_710750_IDX] = { 28430, 0x1, 0x4E, 0x1F1C72, 0x941 }, + [ATHOS_LUT_CHAN_710875_IDX] = { 28435, 0x1, 0x4E, 0x1F8E39, 0x942 }, + [ATHOS_LUT_CHAN_711000_IDX] = { 28440, 0x1, 0x4F, 0x0, 0x942 }, + [ATHOS_LUT_CHAN_711125_IDX] = { 28445, 0x1, 0x4F, 0x71C7, 0x942 }, + [ATHOS_LUT_CHAN_711250_IDX] = { 28450, 0x1, 0x4F, 0xE38E, 0x943 }, + [ATHOS_LUT_CHAN_711375_IDX] = { 28455, 0x1, 0x4F, 0x15555, 0x943 }, + [ATHOS_LUT_CHAN_711500_IDX] = { 28460, 0x1, 0x4F, 0x1C71C, 0x944 }, + [ATHOS_LUT_CHAN_711625_IDX] = { 28465, 0x1, 0x4F, 0x238E4, 0x944 }, + [ATHOS_LUT_CHAN_711750_IDX] = { 28470, 0x1, 0x4F, 0x2AAAB, 0x945 }, + [ATHOS_LUT_CHAN_711875_IDX] = { 28475, 0x1, 0x4F, 0x31C72, 0x945 }, + [ATHOS_LUT_CHAN_712000_IDX] = { 28480, 0x1, 0x4F, 0x38E39, 0x945 }, + [ATHOS_LUT_CHAN_712125_IDX] = { 28485, 0x1, 0x4F, 0x40000, 0x946 }, + [ATHOS_LUT_CHAN_712250_IDX] = { 28490, 0x1, 0x4F, 0x471C7, 0x946 }, + [ATHOS_LUT_CHAN_712375_IDX] = { 28495, 0x1, 0x4F, 0x4E38E, 0x947 }, + [ATHOS_LUT_CHAN_712500_IDX] = { 28500, 0x1, 0x4F, 0x55555, 0x947 }, + [ATHOS_LUT_CHAN_712625_IDX] = { 28505, 0x1, 0x4F, 0x5C71C, 0x947 }, + [ATHOS_LUT_CHAN_712750_IDX] = { 28510, 0x1, 0x4F, 0x638E4, 0x948 }, + [ATHOS_LUT_CHAN_712875_IDX] = { 28515, 0x1, 0x4F, 0x6AAAB, 0x948 }, + [ATHOS_LUT_CHAN_713000_IDX] = { 28520, 0x1, 0x4F, 0x71C72, 0x949 }, + [ATHOS_LUT_CHAN_713125_IDX] = { 28525, 0x1, 0x4F, 0x78E39, 0x949 }, + [ATHOS_LUT_CHAN_713250_IDX] = { 28530, 0x1, 0x4F, 0x80000, 0x94A }, + [ATHOS_LUT_CHAN_713375_IDX] = { 28535, 0x1, 0x4F, 0x871C7, 0x94A }, + [ATHOS_LUT_CHAN_713500_IDX] = { 28540, 0x1, 0x4F, 0x8E38E, 0x94A }, + [ATHOS_LUT_CHAN_713625_IDX] = { 28545, 0x1, 0x4F, 0x95555, 0x94B }, + [ATHOS_LUT_CHAN_713750_IDX] = { 28550, 0x1, 0x4F, 0x9C71C, 0x94B }, + [ATHOS_LUT_CHAN_713875_IDX] = { 28555, 0x1, 0x4F, 0xA38E4, 0x94C }, + [ATHOS_LUT_CHAN_714000_IDX] = { 28560, 0x1, 0x4F, 0xAAAAB, 0x94C }, + [ATHOS_LUT_CHAN_714125_IDX] = { 28565, 0x1, 0x4F, 0xB1C72, 0x94C }, + [ATHOS_LUT_CHAN_714250_IDX] = { 28570, 0x1, 0x4F, 0xB8E39, 0x94D }, + [ATHOS_LUT_CHAN_714375_IDX] = { 28575, 0x1, 0x4F, 0xC0000, 0x94D }, + [ATHOS_LUT_CHAN_714500_IDX] = { 28580, 0x1, 0x4F, 0xC71C7, 0x94E }, + [ATHOS_LUT_CHAN_714625_IDX] = { 28585, 0x1, 0x4F, 0xCE38E, 0x94E }, + [ATHOS_LUT_CHAN_714750_IDX] = { 28590, 0x1, 0x4F, 0xD5555, 0x94F }, + [ATHOS_LUT_CHAN_714875_IDX] = { 28595, 0x1, 0x4F, 0xDC71C, 0x94F }, + [ATHOS_LUT_CHAN_715000_IDX] = { 28600, 0x1, 0x4F, 0xE38E4, 0x94F }, + [ATHOS_LUT_CHAN_715125_IDX] = { 28605, 0x1, 0x4F, 0xEAAAB, 0x950 }, + [ATHOS_LUT_CHAN_715250_IDX] = { 28610, 0x1, 0x4F, 0xF1C72, 0x950 }, + [ATHOS_LUT_CHAN_715375_IDX] = { 28615, 0x1, 0x4F, 0xF8E39, 0x951 }, + [ATHOS_LUT_CHAN_715500_IDX] = { 28620, 0x1, 0x4F, 0x100000, 0x951 }, + [ATHOS_LUT_CHAN_715625_IDX] = { 28625, 0x1, 0x4F, 0x1071C7, 0x951 }, + [ATHOS_LUT_CHAN_715750_IDX] = { 28630, 0x1, 0x4F, 0x10E38E, 0x952 }, + [ATHOS_LUT_CHAN_715875_IDX] = { 28635, 0x1, 0x4F, 0x115555, 0x952 }, + [ATHOS_LUT_CHAN_716000_IDX] = { 28640, 0x1, 0x4F, 0x11C71C, 0x953 }, + [ATHOS_LUT_CHAN_716125_IDX] = { 28645, 0x1, 0x4F, 0x1238E4, 0x953 }, + [ATHOS_LUT_CHAN_716250_IDX] = { 28650, 0x1, 0x4F, 0x12AAAB, 0x954 }, + [ATHOS_LUT_CHAN_716375_IDX] = { 28655, 0x1, 0x4F, 0x131C72, 0x954 }, + [ATHOS_LUT_CHAN_716500_IDX] = { 28660, 0x1, 0x4F, 0x138E39, 0x954 }, + [ATHOS_LUT_CHAN_716625_IDX] = { 28665, 0x1, 0x4F, 0x140000, 0x955 }, + [ATHOS_LUT_CHAN_716750_IDX] = { 28670, 0x1, 0x4F, 0x1471C7, 0x955 }, + [ATHOS_LUT_CHAN_716875_IDX] = { 28675, 0x1, 0x4F, 0x14E38E, 0x956 }, + [ATHOS_LUT_CHAN_717000_IDX] = { 28680, 0x1, 0x4F, 0x155555, 0x956 }, + [ATHOS_LUT_CHAN_717125_IDX] = { 28685, 0x1, 0x4F, 0x15C71C, 0x956 }, + [ATHOS_LUT_CHAN_717250_IDX] = { 28690, 0x1, 0x4F, 0x1638E4, 0x957 }, + [ATHOS_LUT_CHAN_717375_IDX] = { 28695, 0x1, 0x4F, 0x16AAAB, 0x957 }, + [ATHOS_LUT_CHAN_717500_IDX] = { 28700, 0x1, 0x4F, 0x171C72, 0x958 }, + [ATHOS_LUT_CHAN_717625_IDX] = { 28705, 0x1, 0x4F, 0x178E39, 0x958 }, + [ATHOS_LUT_CHAN_717750_IDX] = { 28710, 0x1, 0x4F, 0x180000, 0x959 }, + [ATHOS_LUT_CHAN_717875_IDX] = { 28715, 0x1, 0x4F, 0x1871C7, 0x959 }, + [ATHOS_LUT_CHAN_718000_IDX] = { 28720, 0x1, 0x4F, 0x18E38E, 0x959 }, + [ATHOS_LUT_CHAN_718125_IDX] = { 28725, 0x1, 0x4F, 0x195555, 0x95A }, + [ATHOS_LUT_CHAN_718250_IDX] = { 28730, 0x1, 0x4F, 0x19C71C, 0x95A }, + [ATHOS_LUT_CHAN_718375_IDX] = { 28735, 0x1, 0x4F, 0x1A38E4, 0x95B }, + [ATHOS_LUT_CHAN_718500_IDX] = { 28740, 0x1, 0x4F, 0x1AAAAB, 0x95B }, + [ATHOS_LUT_CHAN_718625_IDX] = { 28745, 0x1, 0x4F, 0x1B1C72, 0x95B }, + [ATHOS_LUT_CHAN_718750_IDX] = { 28750, 0x1, 0x4F, 0x1B8E39, 0x95C }, + [ATHOS_LUT_CHAN_718875_IDX] = { 28755, 0x1, 0x4F, 0x1C0000, 0x95C }, + [ATHOS_LUT_CHAN_719000_IDX] = { 28760, 0x1, 0x4F, 0x1C71C7, 0x95D }, + [ATHOS_LUT_CHAN_719125_IDX] = { 28765, 0x1, 0x4F, 0x1CE38E, 0x95D }, + [ATHOS_LUT_CHAN_719250_IDX] = { 28770, 0x1, 0x4F, 0x1D5555, 0x95E }, + [ATHOS_LUT_CHAN_719375_IDX] = { 28775, 0x1, 0x4F, 0x1DC71C, 0x95E }, + [ATHOS_LUT_CHAN_719500_IDX] = { 28780, 0x1, 0x4F, 0x1E38E4, 0x95E }, + [ATHOS_LUT_CHAN_719625_IDX] = { 28785, 0x1, 0x4F, 0x1EAAAB, 0x95F }, + [ATHOS_LUT_CHAN_719750_IDX] = { 28790, 0x1, 0x4F, 0x1F1C72, 0x95F }, + [ATHOS_LUT_CHAN_719875_IDX] = { 28795, 0x1, 0x4F, 0x1F8E39, 0x960 }, + [ATHOS_LUT_CHAN_720000_IDX] = { 28800, 0x1, 0x50, 0x0, 0x960 }, + [ATHOS_LUT_CHAN_720125_IDX] = { 28805, 0x1, 0x50, 0x71C7, 0x960 }, + [ATHOS_LUT_CHAN_720250_IDX] = { 28810, 0x1, 0x50, 0xE38E, 0x961 }, + [ATHOS_LUT_CHAN_720375_IDX] = { 28815, 0x1, 0x50, 0x15555, 0x961 }, + [ATHOS_LUT_CHAN_720500_IDX] = { 28820, 0x1, 0x50, 0x1C71C, 0x962 }, + [ATHOS_LUT_CHAN_720625_IDX] = { 28825, 0x1, 0x50, 0x238E4, 0x962 }, + [ATHOS_LUT_CHAN_720750_IDX] = { 28830, 0x1, 0x50, 0x2AAAB, 0x963 }, + [ATHOS_LUT_CHAN_720875_IDX] = { 28835, 0x1, 0x50, 0x31C72, 0x963 }, + [ATHOS_LUT_CHAN_721000_IDX] = { 28840, 0x1, 0x50, 0x38E39, 0x963 }, + [ATHOS_LUT_CHAN_721125_IDX] = { 28845, 0x1, 0x50, 0x40000, 0x964 }, + [ATHOS_LUT_CHAN_721250_IDX] = { 28850, 0x1, 0x50, 0x471C7, 0x964 }, + [ATHOS_LUT_CHAN_721375_IDX] = { 28855, 0x1, 0x50, 0x4E38E, 0x965 }, + [ATHOS_LUT_CHAN_721500_IDX] = { 28860, 0x1, 0x50, 0x55555, 0x965 } +}; + From patchwork Thu Jun 17 16:00:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/phy/phy_common_lut.c | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/phy/phy_common_lut.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/phy/phy_common_lut.c b/drivers/net/wireless/celeno/cl8k/phy/phy_common_lut.c new file mode 100644 index 000000000000..73a79f297718 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/phy/phy_common_lut.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "phy_common_lut.h" +#include "phy_athos_lut.h" +#include "phy_olympus_lut.h" + +const struct common_lut_line *cl_phy_oly_get_lut_index(const struct common_lut_line *lut_table, + const u16 lut_table_size, u16 freq) +{ + u16 frequency_idx; + + /* Fine highest frequency in lut table that is lower or equal freq */ + for (frequency_idx = 0; + frequency_idx < lut_table_size && lut_table[frequency_idx].frequency_q2 <= freq; + ++frequency_idx) + ; + + if (frequency_idx) + frequency_idx--; + + return &lut_table[frequency_idx]; +} + +void cl_phy_lut_2_lines_update(u16 freq, + const struct common_lut_line *lut_table_60m, + const u16 lut_table_60m_size, + const struct common_lut_line *lut_table_40m, + const u16 lut_table_40m_size, + struct mm_mac_api_lut_line *api_lut_line) +{ + /* 1. configure the 40M xco lut table */ + const struct common_lut_line *data_line = + cl_phy_oly_get_lut_index(lut_table_40m, lut_table_40m_size, freq); + + api_lut_line->rfic_specific.olympus_2_lines.xco_40M.freqmeastarg = + cpu_to_le32(data_line->freqmeastarg); + api_lut_line->rfic_specific.olympus_2_lines.xco_40M.nfrac = + cpu_to_le32(data_line->nfrac); + api_lut_line->rfic_specific.olympus_2_lines.xco_40M.nint = + data_line->nint; + api_lut_line->rfic_specific.olympus_2_lines.xco_40M.vcocalsel = + data_line->vcocalsel; + + /* 2. configure the 60M xco lut table */ + data_line = cl_phy_oly_get_lut_index(lut_table_60m, lut_table_60m_size, freq); + api_lut_line->rfic_specific.olympus_2_lines.xco_60M.freqmeastarg = + cpu_to_le32(data_line->freqmeastarg); + api_lut_line->rfic_specific.olympus_2_lines.xco_60M.nfrac = + cpu_to_le32(data_line->nfrac); + api_lut_line->rfic_specific.olympus_2_lines.xco_60M.nint = + data_line->nint; + api_lut_line->rfic_specific.olympus_2_lines.xco_60M.vcocalsel = + data_line->vcocalsel; + + /* 3. set frequency */ + api_lut_line->frequency_q2 = cpu_to_le16(freq); +} + +void cl_phy_lut_3_lines_update(u16 freq, + const struct common_lut_line *lut_table_60m_s1, + const u16 lut_table_60m_s1_size, + const struct common_lut_line *lut_table_60m_s0, + const u16 lut_table_60m_s0_size, + const struct common_lut_line *lut_table_40m, + const u16 lut_table_40m_size, + struct mm_mac_api_lut_line *api_lut_line) +{ + /* 1. configure the 40M xco lut table */ + const struct common_lut_line *data_line = + cl_phy_oly_get_lut_index(lut_table_40m, lut_table_40m_size, freq); + + api_lut_line->rfic_specific.olympus_3_lines.xco_40M.freqmeastarg = + cpu_to_le32(data_line->freqmeastarg); + api_lut_line->rfic_specific.olympus_3_lines.xco_40M.nfrac = + cpu_to_le32(data_line->nfrac); + api_lut_line->rfic_specific.olympus_3_lines.xco_40M.nint = + data_line->nint; + api_lut_line->rfic_specific.olympus_3_lines.xco_40M.vcocalsel = + data_line->vcocalsel; + + /* 2. configure the 60M xco lut table , sxpfddesel=1*/ + data_line = cl_phy_oly_get_lut_index(lut_table_60m_s1, lut_table_60m_s1_size, freq); + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s1.freqmeastarg = + cpu_to_le32(data_line->freqmeastarg); + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s1.nfrac = + cpu_to_le32(data_line->nfrac); + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s1.nint = + data_line->nint; + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s1.vcocalsel = + data_line->vcocalsel; + + /* 3. configure the 60M xco lut table , sxpfddesel=0*/ + data_line = cl_phy_oly_get_lut_index(lut_table_60m_s0, lut_table_60m_s0_size, freq); + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s0.freqmeastarg = + cpu_to_le32(data_line->freqmeastarg); + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s0.nfrac = + cpu_to_le32(data_line->nfrac); + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s0.nint = + data_line->nint; + api_lut_line->rfic_specific.olympus_3_lines.xco_60M_s0.vcocalsel = + data_line->vcocalsel; + + /* 4. set frequency */ + api_lut_line->frequency_q2 = cpu_to_le16(freq); +} + +void cl_phy_oly_lut_update(u8 nl_band, u16 freq, + struct mm_mac_api_lut_line *api_lut_line) +{ + switch (nl_band) { + case NL80211_BAND_2GHZ: + cl_phy_lut_3_lines_update(freq, + olympus_lut_24g_60_mhz_s1, + OLYMPUS_LUT_CHAN_24G_MAX, + olympus_lut_24g_60_mhz_s0, + OLYMPUS_LUT_CHAN_24G_MAX, + olympus_lut_24g_40_mhz, + OLYMPUS_LUT_CHAN_24G_MAX, + api_lut_line); + break; + case NL80211_BAND_5GHZ: + cl_phy_lut_3_lines_update(freq, + olympus_lut_5g_60_mhz_s1, + OLYMPUS_LUT_CHAN_5G_MAX, + olympus_lut_5g_60_mhz_s0, + OLYMPUS_LUT_CHAN_5G_MAX, + olympus_lut_5g_40_mhz, + OLYMPUS_LUT_CHAN_5G_MAX, + api_lut_line); + break; + case NL80211_BAND_6GHZ: + cl_phy_lut_2_lines_update(freq, + athos_lut_6g_60_mhz, ATHOS_LUT_CHAN_6G_MAX, + athos_lut_6g_40_mhz, ATHOS_LUT_CHAN_6G_MAX, + api_lut_line); + break; + default: + /* If nl_band is not supported return zero's */ + memset(api_lut_line, 0, sizeof(struct mm_mac_api_lut_line)); + api_lut_line->frequency_q2 = cpu_to_le16(freq); + } +} From patchwork Thu Jun 17 16:00:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8D23C2B9F4 for ; Thu, 17 Jun 2021 16:09:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B00261407 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../celeno/cl8k/phy/phy_olympus_lut.c | 2189 +++++++++++++++++ 1 file changed, 2189 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/phy/phy_olympus_lut.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/phy/phy_olympus_lut.c b/drivers/net/wireless/celeno/cl8k/phy/phy_olympus_lut.c new file mode 100644 index 000000000000..c33f4460d6fa --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/phy/phy_olympus_lut.c @@ -0,0 +1,2189 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "phy_olympus_lut.h" + +const struct olympus_lut_line olympus_lut_5g_40_mhz[OLYMPUS_LUT_CHAN_5G_MAX] = { + [OLYMPUS_LUT_CHAN_516000_IDX] = { 20640, 0x0, 0x56, 0x0, 0x6B8 }, + [OLYMPUS_LUT_CHAN_516125_IDX] = { 20645, 0x0, 0x56, 0xAAAB, 0x6B8 }, + [OLYMPUS_LUT_CHAN_516250_IDX] = { 20650, 0x0, 0x56, 0x15555, 0x6B9 }, + [OLYMPUS_LUT_CHAN_516375_IDX] = { 20655, 0x0, 0x56, 0x20000, 0x6B9 }, + [OLYMPUS_LUT_CHAN_516500_IDX] = { 20660, 0x0, 0x56, 0x2AAAB, 0x6BA }, + [OLYMPUS_LUT_CHAN_516625_IDX] = { 20665, 0x0, 0x56, 0x35555, 0x6BA }, + [OLYMPUS_LUT_CHAN_516750_IDX] = { 20670, 0x0, 0x56, 0x40000, 0x6BB }, + [OLYMPUS_LUT_CHAN_516875_IDX] = { 20675, 0x0, 0x56, 0x4AAAB, 0x6BB }, + [OLYMPUS_LUT_CHAN_517000_IDX] = { 20680, 0x0, 0x56, 0x55555, 0x6BB }, + [OLYMPUS_LUT_CHAN_517125_IDX] = { 20685, 0x0, 0x56, 0x60000, 0x6BC }, + [OLYMPUS_LUT_CHAN_517250_IDX] = { 20690, 0x0, 0x56, 0x6AAAB, 0x6BC }, + [OLYMPUS_LUT_CHAN_517375_IDX] = { 20695, 0x0, 0x56, 0x75555, 0x6BD }, + [OLYMPUS_LUT_CHAN_517500_IDX] = { 20700, 0x0, 0x56, 0x80000, 0x6BD }, + [OLYMPUS_LUT_CHAN_517625_IDX] = { 20705, 0x0, 0x56, 0x8AAAB, 0x6BD }, + [OLYMPUS_LUT_CHAN_517750_IDX] = { 20710, 0x0, 0x56, 0x95555, 0x6BE }, + [OLYMPUS_LUT_CHAN_517875_IDX] = { 20715, 0x0, 0x56, 0xA0000, 0x6BE }, + [OLYMPUS_LUT_CHAN_518000_IDX] = { 20720, 0x1, 0x56, 0xAAAAB, 0x6BF }, + [OLYMPUS_LUT_CHAN_518125_IDX] = { 20725, 0x1, 0x56, 0xB5555, 0x6BF }, + [OLYMPUS_LUT_CHAN_518250_IDX] = { 20730, 0x1, 0x56, 0xC0000, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518375_IDX] = { 20735, 0x1, 0x56, 0xCAAAB, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518500_IDX] = { 20740, 0x1, 0x56, 0xD5555, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518625_IDX] = { 20745, 0x1, 0x56, 0xE0000, 0x6C1 }, + [OLYMPUS_LUT_CHAN_518750_IDX] = { 20750, 0x1, 0x56, 0xEAAAB, 0x6C1 }, + [OLYMPUS_LUT_CHAN_518875_IDX] = { 20755, 0x1, 0x56, 0xF5555, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519000_IDX] = { 20760, 0x1, 0x56, 0x100000, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519125_IDX] = { 20765, 0x1, 0x56, 0x10AAAB, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519250_IDX] = { 20770, 0x1, 0x56, 0x115555, 0x6C3 }, + [OLYMPUS_LUT_CHAN_519375_IDX] = { 20775, 0x1, 0x56, 0x120000, 0x6C3 }, + [OLYMPUS_LUT_CHAN_519500_IDX] = { 20780, 0x1, 0x56, 0x12AAAB, 0x6C4 }, + [OLYMPUS_LUT_CHAN_519625_IDX] = { 20785, 0x1, 0x56, 0x135555, 0x6C4 }, + [OLYMPUS_LUT_CHAN_519750_IDX] = { 20790, 0x1, 0x56, 0x140000, 0x6C5 }, + [OLYMPUS_LUT_CHAN_519875_IDX] = { 20795, 0x1, 0x56, 0x14AAAB, 0x6C5 }, + [OLYMPUS_LUT_CHAN_520000_IDX] = { 20800, 0x1, 0x56, 0x155555, 0x6C5 }, + [OLYMPUS_LUT_CHAN_520125_IDX] = { 20805, 0x1, 0x56, 0x160000, 0x6C6 }, + [OLYMPUS_LUT_CHAN_520250_IDX] = { 20810, 0x1, 0x56, 0x16AAAB, 0x6C6 }, + [OLYMPUS_LUT_CHAN_520375_IDX] = { 20815, 0x1, 0x56, 0x175555, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520500_IDX] = { 20820, 0x1, 0x56, 0x180000, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520625_IDX] = { 20825, 0x1, 0x56, 0x18AAAB, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520750_IDX] = { 20830, 0x1, 0x56, 0x195555, 0x6C8 }, + [OLYMPUS_LUT_CHAN_520875_IDX] = { 20835, 0x1, 0x56, 0x1A0000, 0x6C8 }, + [OLYMPUS_LUT_CHAN_521000_IDX] = { 20840, 0x1, 0x56, 0x1AAAAB, 0x6C9 }, + [OLYMPUS_LUT_CHAN_521125_IDX] = { 20845, 0x1, 0x56, 0x1B5555, 0x6C9 }, + [OLYMPUS_LUT_CHAN_521250_IDX] = { 20850, 0x1, 0x56, 0x1C0000, 0x6CA }, + [OLYMPUS_LUT_CHAN_521375_IDX] = { 20855, 0x1, 0x56, 0x1CAAAB, 0x6CA }, + [OLYMPUS_LUT_CHAN_521500_IDX] = { 20860, 0x1, 0x56, 0x1D5555, 0x6CA }, + [OLYMPUS_LUT_CHAN_521625_IDX] = { 20865, 0x1, 0x56, 0x1E0000, 0x6CB }, + [OLYMPUS_LUT_CHAN_521750_IDX] = { 20870, 0x1, 0x56, 0x1EAAAB, 0x6CB }, + [OLYMPUS_LUT_CHAN_521875_IDX] = { 20875, 0x1, 0x56, 0x1F5555, 0x6CC }, + [OLYMPUS_LUT_CHAN_522000_IDX] = { 20880, 0x1, 0x57, 0x0, 0x6CC }, + [OLYMPUS_LUT_CHAN_522125_IDX] = { 20885, 0x1, 0x57, 0xAAAB, 0x6CC }, + [OLYMPUS_LUT_CHAN_522250_IDX] = { 20890, 0x1, 0x57, 0x15555, 0x6CD }, + [OLYMPUS_LUT_CHAN_522375_IDX] = { 20895, 0x1, 0x57, 0x20000, 0x6CD }, + [OLYMPUS_LUT_CHAN_522500_IDX] = { 20900, 0x1, 0x57, 0x2AAAB, 0x6CE }, + [OLYMPUS_LUT_CHAN_522625_IDX] = { 20905, 0x1, 0x57, 0x35555, 0x6CE }, + [OLYMPUS_LUT_CHAN_522750_IDX] = { 20910, 0x1, 0x57, 0x40000, 0x6CF }, + [OLYMPUS_LUT_CHAN_522875_IDX] = { 20915, 0x1, 0x57, 0x4AAAB, 0x6CF }, + [OLYMPUS_LUT_CHAN_523000_IDX] = { 20920, 0x1, 0x57, 0x55555, 0x6CF }, + [OLYMPUS_LUT_CHAN_523125_IDX] = { 20925, 0x1, 0x57, 0x60000, 0x6D0 }, + [OLYMPUS_LUT_CHAN_523250_IDX] = { 20930, 0x1, 0x57, 0x6AAAB, 0x6D0 }, + [OLYMPUS_LUT_CHAN_523375_IDX] = { 20935, 0x1, 0x57, 0x75555, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523500_IDX] = { 20940, 0x1, 0x57, 0x80000, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523625_IDX] = { 20945, 0x1, 0x57, 0x8AAAB, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523750_IDX] = { 20950, 0x1, 0x57, 0x95555, 0x6D2 }, + [OLYMPUS_LUT_CHAN_523875_IDX] = { 20955, 0x1, 0x57, 0xA0000, 0x6D2 }, + [OLYMPUS_LUT_CHAN_524000_IDX] = { 20960, 0x1, 0x57, 0xAAAAB, 0x6D3 }, + [OLYMPUS_LUT_CHAN_524125_IDX] = { 20965, 0x1, 0x57, 0xB5555, 0x6D3 }, + [OLYMPUS_LUT_CHAN_524250_IDX] = { 20970, 0x1, 0x57, 0xC0000, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524375_IDX] = { 20975, 0x1, 0x57, 0xCAAAB, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524500_IDX] = { 20980, 0x1, 0x57, 0xD5555, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524625_IDX] = { 20985, 0x1, 0x57, 0xE0000, 0x6D5 }, + [OLYMPUS_LUT_CHAN_524750_IDX] = { 20990, 0x1, 0x57, 0xEAAAB, 0x6D5 }, + [OLYMPUS_LUT_CHAN_524875_IDX] = { 20995, 0x1, 0x57, 0xF5555, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525000_IDX] = { 21000, 0x1, 0x57, 0x100000, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525125_IDX] = { 21005, 0x1, 0x57, 0x10AAAB, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525250_IDX] = { 21010, 0x1, 0x57, 0x115555, 0x6D7 }, + [OLYMPUS_LUT_CHAN_525375_IDX] = { 21015, 0x1, 0x57, 0x120000, 0x6D7 }, + [OLYMPUS_LUT_CHAN_525500_IDX] = { 21020, 0x1, 0x57, 0x12AAAB, 0x6D8 }, + [OLYMPUS_LUT_CHAN_525625_IDX] = { 21025, 0x1, 0x57, 0x135555, 0x6D8 }, + [OLYMPUS_LUT_CHAN_525750_IDX] = { 21030, 0x1, 0x57, 0x140000, 0x6D9 }, + [OLYMPUS_LUT_CHAN_525875_IDX] = { 21035, 0x1, 0x57, 0x14AAAB, 0x6D9 }, + [OLYMPUS_LUT_CHAN_526000_IDX] = { 21040, 0x1, 0x57, 0x155555, 0x6D9 }, + [OLYMPUS_LUT_CHAN_526125_IDX] = { 21045, 0x1, 0x57, 0x160000, 0x6DA }, + [OLYMPUS_LUT_CHAN_526250_IDX] = { 21050, 0x1, 0x57, 0x16AAAB, 0x6DA }, + [OLYMPUS_LUT_CHAN_526375_IDX] = { 21055, 0x1, 0x57, 0x175555, 0x6DB }, + [OLYMPUS_LUT_CHAN_526500_IDX] = { 21060, 0x1, 0x57, 0x180000, 0x6DB }, + [OLYMPUS_LUT_CHAN_526625_IDX] = { 21065, 0x1, 0x57, 0x18AAAB, 0x6DB }, + [OLYMPUS_LUT_CHAN_526750_IDX] = { 21070, 0x1, 0x57, 0x195555, 0x6DC }, + [OLYMPUS_LUT_CHAN_526875_IDX] = { 21075, 0x1, 0x57, 0x1A0000, 0x6DC }, + [OLYMPUS_LUT_CHAN_527000_IDX] = { 21080, 0x1, 0x57, 0x1AAAAB, 0x6DD }, + [OLYMPUS_LUT_CHAN_527125_IDX] = { 21085, 0x1, 0x57, 0x1B5555, 0x6DD }, + [OLYMPUS_LUT_CHAN_527250_IDX] = { 21090, 0x1, 0x57, 0x1C0000, 0x6DE }, + [OLYMPUS_LUT_CHAN_527375_IDX] = { 21095, 0x1, 0x57, 0x1CAAAB, 0x6DE }, + [OLYMPUS_LUT_CHAN_527500_IDX] = { 21100, 0x1, 0x57, 0x1D5555, 0x6DE }, + [OLYMPUS_LUT_CHAN_527625_IDX] = { 21105, 0x1, 0x57, 0x1E0000, 0x6DF }, + [OLYMPUS_LUT_CHAN_527750_IDX] = { 21110, 0x1, 0x57, 0x1EAAAB, 0x6DF }, + [OLYMPUS_LUT_CHAN_527875_IDX] = { 21115, 0x1, 0x57, 0x1F5555, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528000_IDX] = { 21120, 0x1, 0x58, 0x0, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528125_IDX] = { 21125, 0x1, 0x58, 0xAAAB, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528250_IDX] = { 21130, 0x1, 0x58, 0x15555, 0x6E1 }, + [OLYMPUS_LUT_CHAN_528375_IDX] = { 21135, 0x1, 0x58, 0x20000, 0x6E1 }, + [OLYMPUS_LUT_CHAN_528500_IDX] = { 21140, 0x1, 0x58, 0x2AAAB, 0x6E2 }, + [OLYMPUS_LUT_CHAN_528625_IDX] = { 21145, 0x1, 0x58, 0x35555, 0x6E2 }, + [OLYMPUS_LUT_CHAN_528750_IDX] = { 21150, 0x1, 0x58, 0x40000, 0x6E3 }, + [OLYMPUS_LUT_CHAN_528875_IDX] = { 21155, 0x1, 0x58, 0x4AAAB, 0x6E3 }, + [OLYMPUS_LUT_CHAN_529000_IDX] = { 21160, 0x1, 0x58, 0x55555, 0x6E3 }, + [OLYMPUS_LUT_CHAN_529125_IDX] = { 21165, 0x1, 0x58, 0x60000, 0x6E4 }, + [OLYMPUS_LUT_CHAN_529250_IDX] = { 21170, 0x1, 0x58, 0x6AAAB, 0x6E4 }, + [OLYMPUS_LUT_CHAN_529375_IDX] = { 21175, 0x1, 0x58, 0x75555, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529500_IDX] = { 21180, 0x1, 0x58, 0x80000, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529625_IDX] = { 21185, 0x1, 0x58, 0x8AAAB, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529750_IDX] = { 21190, 0x1, 0x58, 0x95555, 0x6E6 }, + [OLYMPUS_LUT_CHAN_529875_IDX] = { 21195, 0x1, 0x58, 0xA0000, 0x6E6 }, + [OLYMPUS_LUT_CHAN_530000_IDX] = { 21200, 0x1, 0x58, 0xAAAAB, 0x6E7 }, + [OLYMPUS_LUT_CHAN_530125_IDX] = { 21205, 0x1, 0x58, 0xB5555, 0x6E7 }, + [OLYMPUS_LUT_CHAN_530250_IDX] = { 21210, 0x1, 0x58, 0xC0000, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530375_IDX] = { 21215, 0x1, 0x58, 0xCAAAB, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530500_IDX] = { 21220, 0x1, 0x58, 0xD5555, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530625_IDX] = { 21225, 0x1, 0x58, 0xE0000, 0x6E9 }, + [OLYMPUS_LUT_CHAN_530750_IDX] = { 21230, 0x1, 0x58, 0xEAAAB, 0x6E9 }, + [OLYMPUS_LUT_CHAN_530875_IDX] = { 21235, 0x1, 0x58, 0xF5555, 0x6EA }, + [OLYMPUS_LUT_CHAN_531000_IDX] = { 21240, 0x1, 0x58, 0x100000, 0x6EA }, + [OLYMPUS_LUT_CHAN_531125_IDX] = { 21245, 0x1, 0x58, 0x10AAAB, 0x6EA }, + [OLYMPUS_LUT_CHAN_531250_IDX] = { 21250, 0x1, 0x58, 0x115555, 0x6EB }, + [OLYMPUS_LUT_CHAN_531375_IDX] = { 21255, 0x1, 0x58, 0x120000, 0x6EB }, + [OLYMPUS_LUT_CHAN_531500_IDX] = { 21260, 0x1, 0x58, 0x12AAAB, 0x6EC }, + [OLYMPUS_LUT_CHAN_531625_IDX] = { 21265, 0x1, 0x58, 0x135555, 0x6EC }, + [OLYMPUS_LUT_CHAN_531750_IDX] = { 21270, 0x1, 0x58, 0x140000, 0x6ED }, + [OLYMPUS_LUT_CHAN_531875_IDX] = { 21275, 0x1, 0x58, 0x14AAAB, 0x6ED }, + [OLYMPUS_LUT_CHAN_532000_IDX] = { 21280, 0x1, 0x58, 0x155555, 0x6ED }, + [OLYMPUS_LUT_CHAN_532125_IDX] = { 21285, 0x1, 0x58, 0x160000, 0x6EE }, + [OLYMPUS_LUT_CHAN_532250_IDX] = { 21290, 0x1, 0x58, 0x16AAAB, 0x6EE }, + [OLYMPUS_LUT_CHAN_532375_IDX] = { 21295, 0x1, 0x58, 0x175555, 0x6EF }, + [OLYMPUS_LUT_CHAN_532500_IDX] = { 21300, 0x1, 0x58, 0x180000, 0x6EF }, + [OLYMPUS_LUT_CHAN_532625_IDX] = { 21305, 0x1, 0x58, 0x18AAAB, 0x6EF }, + [OLYMPUS_LUT_CHAN_532750_IDX] = { 21310, 0x1, 0x58, 0x195555, 0x6F0 }, + [OLYMPUS_LUT_CHAN_532875_IDX] = { 21315, 0x1, 0x58, 0x1A0000, 0x6F0 }, + [OLYMPUS_LUT_CHAN_533000_IDX] = { 21320, 0x1, 0x58, 0x1AAAAB, 0x6F1 }, + [OLYMPUS_LUT_CHAN_533125_IDX] = { 21325, 0x1, 0x58, 0x1B5555, 0x6F1 }, + [OLYMPUS_LUT_CHAN_533250_IDX] = { 21330, 0x1, 0x58, 0x1C0000, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533375_IDX] = { 21335, 0x1, 0x58, 0x1CAAAB, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533500_IDX] = { 21340, 0x1, 0x58, 0x1D5555, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533625_IDX] = { 21345, 0x1, 0x58, 0x1E0000, 0x6F3 }, + [OLYMPUS_LUT_CHAN_533750_IDX] = { 21350, 0x1, 0x58, 0x1EAAAB, 0x6F3 }, + [OLYMPUS_LUT_CHAN_533875_IDX] = { 21355, 0x1, 0x58, 0x1F5555, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534000_IDX] = { 21360, 0x1, 0x59, 0x0, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534125_IDX] = { 21365, 0x1, 0x59, 0xAAAB, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534250_IDX] = { 21370, 0x1, 0x59, 0x15555, 0x6F5 }, + [OLYMPUS_LUT_CHAN_534375_IDX] = { 21375, 0x1, 0x59, 0x20000, 0x6F5 }, + [OLYMPUS_LUT_CHAN_534500_IDX] = { 21380, 0x1, 0x59, 0x2AAAB, 0x6F6 }, + [OLYMPUS_LUT_CHAN_534625_IDX] = { 21385, 0x1, 0x59, 0x35555, 0x6F6 }, + [OLYMPUS_LUT_CHAN_534750_IDX] = { 21390, 0x1, 0x59, 0x40000, 0x6F7 }, + [OLYMPUS_LUT_CHAN_534875_IDX] = { 21395, 0x1, 0x59, 0x4AAAB, 0x6F7 }, + [OLYMPUS_LUT_CHAN_535000_IDX] = { 21400, 0x1, 0x59, 0x55555, 0x6F7 }, + [OLYMPUS_LUT_CHAN_535125_IDX] = { 21405, 0x1, 0x59, 0x60000, 0x6F8 }, + [OLYMPUS_LUT_CHAN_535250_IDX] = { 21410, 0x1, 0x59, 0x6AAAB, 0x6F8 }, + [OLYMPUS_LUT_CHAN_535375_IDX] = { 21415, 0x1, 0x59, 0x75555, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535500_IDX] = { 21420, 0x1, 0x59, 0x80000, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535625_IDX] = { 21425, 0x1, 0x59, 0x8AAAB, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535750_IDX] = { 21430, 0x1, 0x59, 0x95555, 0x6FA }, + [OLYMPUS_LUT_CHAN_535875_IDX] = { 21435, 0x1, 0x59, 0xA0000, 0x6FA }, + [OLYMPUS_LUT_CHAN_536000_IDX] = { 21440, 0x1, 0x59, 0xAAAAB, 0x6FB }, + [OLYMPUS_LUT_CHAN_536125_IDX] = { 21445, 0x1, 0x59, 0xB5555, 0x6FB }, + [OLYMPUS_LUT_CHAN_536250_IDX] = { 21450, 0x1, 0x59, 0xC0000, 0x6FC }, + [OLYMPUS_LUT_CHAN_536375_IDX] = { 21455, 0x1, 0x59, 0xCAAAB, 0x6FC }, + [OLYMPUS_LUT_CHAN_536500_IDX] = { 21460, 0x1, 0x59, 0xD5555, 0x6FC }, + [OLYMPUS_LUT_CHAN_536625_IDX] = { 21465, 0x1, 0x59, 0xE0000, 0x6FD }, + [OLYMPUS_LUT_CHAN_536750_IDX] = { 21470, 0x1, 0x59, 0xEAAAB, 0x6FD }, + [OLYMPUS_LUT_CHAN_536875_IDX] = { 21475, 0x1, 0x59, 0xF5555, 0x6FE }, + [OLYMPUS_LUT_CHAN_537000_IDX] = { 21480, 0x1, 0x59, 0x100000, 0x6FE }, + [OLYMPUS_LUT_CHAN_537125_IDX] = { 21485, 0x1, 0x59, 0x10AAAB, 0x6FE }, + [OLYMPUS_LUT_CHAN_537250_IDX] = { 21490, 0x1, 0x59, 0x115555, 0x6FF }, + [OLYMPUS_LUT_CHAN_537375_IDX] = { 21495, 0x1, 0x59, 0x120000, 0x6FF }, + [OLYMPUS_LUT_CHAN_537500_IDX] = { 21500, 0x1, 0x59, 0x12AAAB, 0x700 }, + [OLYMPUS_LUT_CHAN_537625_IDX] = { 21505, 0x1, 0x59, 0x135555, 0x700 }, + [OLYMPUS_LUT_CHAN_537750_IDX] = { 21510, 0x1, 0x59, 0x140000, 0x701 }, + [OLYMPUS_LUT_CHAN_537875_IDX] = { 21515, 0x1, 0x59, 0x14AAAB, 0x701 }, + [OLYMPUS_LUT_CHAN_538000_IDX] = { 21520, 0x1, 0x59, 0x155555, 0x701 }, + [OLYMPUS_LUT_CHAN_538125_IDX] = { 21525, 0x1, 0x59, 0x160000, 0x702 }, + [OLYMPUS_LUT_CHAN_538250_IDX] = { 21530, 0x1, 0x59, 0x16AAAB, 0x702 }, + [OLYMPUS_LUT_CHAN_538375_IDX] = { 21535, 0x1, 0x59, 0x175555, 0x703 }, + [OLYMPUS_LUT_CHAN_538500_IDX] = { 21540, 0x1, 0x59, 0x180000, 0x703 }, + [OLYMPUS_LUT_CHAN_538625_IDX] = { 21545, 0x1, 0x59, 0x18AAAB, 0x703 }, + [OLYMPUS_LUT_CHAN_538750_IDX] = { 21550, 0x1, 0x59, 0x195555, 0x704 }, + [OLYMPUS_LUT_CHAN_538875_IDX] = { 21555, 0x1, 0x59, 0x1A0000, 0x704 }, + [OLYMPUS_LUT_CHAN_539000_IDX] = { 21560, 0x1, 0x59, 0x1AAAAB, 0x705 }, + [OLYMPUS_LUT_CHAN_539125_IDX] = { 21565, 0x1, 0x59, 0x1B5555, 0x705 }, + [OLYMPUS_LUT_CHAN_539250_IDX] = { 21570, 0x1, 0x59, 0x1C0000, 0x706 }, + [OLYMPUS_LUT_CHAN_539375_IDX] = { 21575, 0x1, 0x59, 0x1CAAAB, 0x706 }, + [OLYMPUS_LUT_CHAN_539500_IDX] = { 21580, 0x1, 0x59, 0x1D5555, 0x706 }, + [OLYMPUS_LUT_CHAN_539625_IDX] = { 21585, 0x1, 0x59, 0x1E0000, 0x707 }, + [OLYMPUS_LUT_CHAN_539750_IDX] = { 21590, 0x1, 0x59, 0x1EAAAB, 0x707 }, + [OLYMPUS_LUT_CHAN_539875_IDX] = { 21595, 0x1, 0x59, 0x1F5555, 0x708 }, + [OLYMPUS_LUT_CHAN_540000_IDX] = { 21600, 0x1, 0x5A, 0x0, 0x708 }, + [OLYMPUS_LUT_CHAN_540125_IDX] = { 21605, 0x1, 0x5A, 0xAAAB, 0x708 }, + [OLYMPUS_LUT_CHAN_540250_IDX] = { 21610, 0x1, 0x5A, 0x15555, 0x709 }, + [OLYMPUS_LUT_CHAN_540375_IDX] = { 21615, 0x1, 0x5A, 0x20000, 0x709 }, + [OLYMPUS_LUT_CHAN_540500_IDX] = { 21620, 0x1, 0x5A, 0x2AAAB, 0x70A }, + [OLYMPUS_LUT_CHAN_540625_IDX] = { 21625, 0x1, 0x5A, 0x35555, 0x70A }, + [OLYMPUS_LUT_CHAN_540750_IDX] = { 21630, 0x1, 0x5A, 0x40000, 0x70B }, + [OLYMPUS_LUT_CHAN_540875_IDX] = { 21635, 0x1, 0x5A, 0x4AAAB, 0x70B }, + [OLYMPUS_LUT_CHAN_541000_IDX] = { 21640, 0x1, 0x5A, 0x55555, 0x70B }, + [OLYMPUS_LUT_CHAN_541125_IDX] = { 21645, 0x1, 0x5A, 0x60000, 0x70C }, + [OLYMPUS_LUT_CHAN_541250_IDX] = { 21650, 0x1, 0x5A, 0x6AAAB, 0x70C }, + [OLYMPUS_LUT_CHAN_541375_IDX] = { 21655, 0x1, 0x5A, 0x75555, 0x70D }, + [OLYMPUS_LUT_CHAN_541500_IDX] = { 21660, 0x1, 0x5A, 0x80000, 0x70D }, + [OLYMPUS_LUT_CHAN_541625_IDX] = { 21665, 0x1, 0x5A, 0x8AAAB, 0x70D }, + [OLYMPUS_LUT_CHAN_541750_IDX] = { 21670, 0x1, 0x5A, 0x95555, 0x70E }, + [OLYMPUS_LUT_CHAN_541875_IDX] = { 21675, 0x1, 0x5A, 0xA0000, 0x70E }, + [OLYMPUS_LUT_CHAN_542000_IDX] = { 21680, 0x1, 0x5A, 0xAAAAB, 0x70F }, + [OLYMPUS_LUT_CHAN_542125_IDX] = { 21685, 0x1, 0x5A, 0xB5555, 0x70F }, + [OLYMPUS_LUT_CHAN_542250_IDX] = { 21690, 0x1, 0x5A, 0xC0000, 0x710 }, + [OLYMPUS_LUT_CHAN_542375_IDX] = { 21695, 0x1, 0x5A, 0xCAAAB, 0x710 }, + [OLYMPUS_LUT_CHAN_542500_IDX] = { 21700, 0x1, 0x5A, 0xD5555, 0x710 }, + [OLYMPUS_LUT_CHAN_542625_IDX] = { 21705, 0x1, 0x5A, 0xE0000, 0x711 }, + [OLYMPUS_LUT_CHAN_542750_IDX] = { 21710, 0x1, 0x5A, 0xEAAAB, 0x711 }, + [OLYMPUS_LUT_CHAN_542875_IDX] = { 21715, 0x1, 0x5A, 0xF5555, 0x712 }, + [OLYMPUS_LUT_CHAN_543000_IDX] = { 21720, 0x1, 0x5A, 0x100000, 0x712 }, + [OLYMPUS_LUT_CHAN_543125_IDX] = { 21725, 0x1, 0x5A, 0x10AAAB, 0x712 }, + [OLYMPUS_LUT_CHAN_543250_IDX] = { 21730, 0x1, 0x5A, 0x115555, 0x713 }, + [OLYMPUS_LUT_CHAN_543375_IDX] = { 21735, 0x1, 0x5A, 0x120000, 0x713 }, + [OLYMPUS_LUT_CHAN_543500_IDX] = { 21740, 0x1, 0x5A, 0x12AAAB, 0x714 }, + [OLYMPUS_LUT_CHAN_543625_IDX] = { 21745, 0x1, 0x5A, 0x135555, 0x714 }, + [OLYMPUS_LUT_CHAN_543750_IDX] = { 21750, 0x1, 0x5A, 0x140000, 0x715 }, + [OLYMPUS_LUT_CHAN_543875_IDX] = { 21755, 0x1, 0x5A, 0x14AAAB, 0x715 }, + [OLYMPUS_LUT_CHAN_544000_IDX] = { 21760, 0x1, 0x5A, 0x155555, 0x715 }, + [OLYMPUS_LUT_CHAN_544125_IDX] = { 21765, 0x1, 0x5A, 0x160000, 0x716 }, + [OLYMPUS_LUT_CHAN_544250_IDX] = { 21770, 0x1, 0x5A, 0x16AAAB, 0x716 }, + [OLYMPUS_LUT_CHAN_544375_IDX] = { 21775, 0x1, 0x5A, 0x175555, 0x717 }, + [OLYMPUS_LUT_CHAN_544500_IDX] = { 21780, 0x1, 0x5A, 0x180000, 0x717 }, + [OLYMPUS_LUT_CHAN_544625_IDX] = { 21785, 0x1, 0x5A, 0x18AAAB, 0x717 }, + [OLYMPUS_LUT_CHAN_544750_IDX] = { 21790, 0x1, 0x5A, 0x195555, 0x718 }, + [OLYMPUS_LUT_CHAN_544875_IDX] = { 21795, 0x1, 0x5A, 0x1A0000, 0x718 }, + [OLYMPUS_LUT_CHAN_545000_IDX] = { 21800, 0x1, 0x5A, 0x1AAAAB, 0x719 }, + [OLYMPUS_LUT_CHAN_545125_IDX] = { 21805, 0x1, 0x5A, 0x1B5555, 0x719 }, + [OLYMPUS_LUT_CHAN_545250_IDX] = { 21810, 0x1, 0x5A, 0x1C0000, 0x71A }, + [OLYMPUS_LUT_CHAN_545375_IDX] = { 21815, 0x1, 0x5A, 0x1CAAAB, 0x71A }, + [OLYMPUS_LUT_CHAN_545500_IDX] = { 21820, 0x1, 0x5A, 0x1D5555, 0x71A }, + [OLYMPUS_LUT_CHAN_545625_IDX] = { 21825, 0x1, 0x5A, 0x1E0000, 0x71B }, + [OLYMPUS_LUT_CHAN_545750_IDX] = { 21830, 0x1, 0x5A, 0x1EAAAB, 0x71B }, + [OLYMPUS_LUT_CHAN_545875_IDX] = { 21835, 0x1, 0x5A, 0x1F5555, 0x71C }, + [OLYMPUS_LUT_CHAN_546000_IDX] = { 21840, 0x1, 0x5B, 0x0, 0x71C }, + [OLYMPUS_LUT_CHAN_546125_IDX] = { 21845, 0x1, 0x5B, 0xAAAB, 0x71C }, + [OLYMPUS_LUT_CHAN_546250_IDX] = { 21850, 0x1, 0x5B, 0x15555, 0x71D }, + [OLYMPUS_LUT_CHAN_546375_IDX] = { 21855, 0x1, 0x5B, 0x20000, 0x71D }, + [OLYMPUS_LUT_CHAN_546500_IDX] = { 21860, 0x1, 0x5B, 0x2AAAB, 0x71E }, + [OLYMPUS_LUT_CHAN_546625_IDX] = { 21865, 0x1, 0x5B, 0x35555, 0x71E }, + [OLYMPUS_LUT_CHAN_546750_IDX] = { 21870, 0x1, 0x5B, 0x40000, 0x71F }, + [OLYMPUS_LUT_CHAN_546875_IDX] = { 21875, 0x1, 0x5B, 0x4AAAB, 0x71F }, + [OLYMPUS_LUT_CHAN_547000_IDX] = { 21880, 0x1, 0x5B, 0x55555, 0x71F }, + [OLYMPUS_LUT_CHAN_547125_IDX] = { 21885, 0x1, 0x5B, 0x60000, 0x720 }, + [OLYMPUS_LUT_CHAN_547250_IDX] = { 21890, 0x1, 0x5B, 0x6AAAB, 0x720 }, + [OLYMPUS_LUT_CHAN_547375_IDX] = { 21895, 0x1, 0x5B, 0x75555, 0x721 }, + [OLYMPUS_LUT_CHAN_547500_IDX] = { 21900, 0x1, 0x5B, 0x80000, 0x721 }, + [OLYMPUS_LUT_CHAN_547625_IDX] = { 21905, 0x1, 0x5B, 0x8AAAB, 0x721 }, + [OLYMPUS_LUT_CHAN_547750_IDX] = { 21910, 0x1, 0x5B, 0x95555, 0x722 }, + [OLYMPUS_LUT_CHAN_547875_IDX] = { 21915, 0x1, 0x5B, 0xA0000, 0x722 }, + [OLYMPUS_LUT_CHAN_548000_IDX] = { 21920, 0x1, 0x5B, 0xAAAAB, 0x723 }, + [OLYMPUS_LUT_CHAN_548125_IDX] = { 21925, 0x1, 0x5B, 0xB5555, 0x723 }, + [OLYMPUS_LUT_CHAN_548250_IDX] = { 21930, 0x1, 0x5B, 0xC0000, 0x724 }, + [OLYMPUS_LUT_CHAN_548375_IDX] = { 21935, 0x1, 0x5B, 0xCAAAB, 0x724 }, + [OLYMPUS_LUT_CHAN_548500_IDX] = { 21940, 0x1, 0x5B, 0xD5555, 0x724 }, + [OLYMPUS_LUT_CHAN_548625_IDX] = { 21945, 0x1, 0x5B, 0xE0000, 0x725 }, + [OLYMPUS_LUT_CHAN_548750_IDX] = { 21950, 0x1, 0x5B, 0xEAAAB, 0x725 }, + [OLYMPUS_LUT_CHAN_548875_IDX] = { 21955, 0x1, 0x5B, 0xF5555, 0x726 }, + [OLYMPUS_LUT_CHAN_549000_IDX] = { 21960, 0x1, 0x5B, 0x100000, 0x726 }, + [OLYMPUS_LUT_CHAN_549125_IDX] = { 21965, 0x1, 0x5B, 0x10AAAB, 0x726 }, + [OLYMPUS_LUT_CHAN_549250_IDX] = { 21970, 0x1, 0x5B, 0x115555, 0x727 }, + [OLYMPUS_LUT_CHAN_549375_IDX] = { 21975, 0x1, 0x5B, 0x120000, 0x727 }, + [OLYMPUS_LUT_CHAN_549500_IDX] = { 21980, 0x1, 0x5B, 0x12AAAB, 0x728 }, + [OLYMPUS_LUT_CHAN_549625_IDX] = { 21985, 0x1, 0x5B, 0x135555, 0x728 }, + [OLYMPUS_LUT_CHAN_549750_IDX] = { 21990, 0x1, 0x5B, 0x140000, 0x729 }, + [OLYMPUS_LUT_CHAN_549875_IDX] = { 21995, 0x1, 0x5B, 0x14AAAB, 0x729 }, + [OLYMPUS_LUT_CHAN_550000_IDX] = { 22000, 0x1, 0x5B, 0x155555, 0x729 }, + [OLYMPUS_LUT_CHAN_550125_IDX] = { 22005, 0x1, 0x5B, 0x160000, 0x72A }, + [OLYMPUS_LUT_CHAN_550250_IDX] = { 22010, 0x1, 0x5B, 0x16AAAB, 0x72A }, + [OLYMPUS_LUT_CHAN_550375_IDX] = { 22015, 0x1, 0x5B, 0x175555, 0x72B }, + [OLYMPUS_LUT_CHAN_550500_IDX] = { 22020, 0x1, 0x5B, 0x180000, 0x72B }, + [OLYMPUS_LUT_CHAN_550625_IDX] = { 22025, 0x1, 0x5B, 0x18AAAB, 0x72B }, + [OLYMPUS_LUT_CHAN_550750_IDX] = { 22030, 0x1, 0x5B, 0x195555, 0x72C }, + [OLYMPUS_LUT_CHAN_550875_IDX] = { 22035, 0x1, 0x5B, 0x1A0000, 0x72C }, + [OLYMPUS_LUT_CHAN_551000_IDX] = { 22040, 0x1, 0x5B, 0x1AAAAB, 0x72D }, + [OLYMPUS_LUT_CHAN_551125_IDX] = { 22045, 0x1, 0x5B, 0x1B5555, 0x72D }, + [OLYMPUS_LUT_CHAN_551250_IDX] = { 22050, 0x1, 0x5B, 0x1C0000, 0x72E }, + [OLYMPUS_LUT_CHAN_551375_IDX] = { 22055, 0x1, 0x5B, 0x1CAAAB, 0x72E }, + [OLYMPUS_LUT_CHAN_551500_IDX] = { 22060, 0x1, 0x5B, 0x1D5555, 0x72E }, + [OLYMPUS_LUT_CHAN_551625_IDX] = { 22065, 0x1, 0x5B, 0x1E0000, 0x72F }, + [OLYMPUS_LUT_CHAN_551750_IDX] = { 22070, 0x1, 0x5B, 0x1EAAAB, 0x72F }, + [OLYMPUS_LUT_CHAN_551875_IDX] = { 22075, 0x1, 0x5B, 0x1F5555, 0x730 }, + [OLYMPUS_LUT_CHAN_552000_IDX] = { 22080, 0x1, 0x5C, 0x0, 0x730 }, + [OLYMPUS_LUT_CHAN_552125_IDX] = { 22085, 0x1, 0x5C, 0xAAAB, 0x730 }, + [OLYMPUS_LUT_CHAN_552250_IDX] = { 22090, 0x1, 0x5C, 0x15555, 0x731 }, + [OLYMPUS_LUT_CHAN_552375_IDX] = { 22095, 0x1, 0x5C, 0x20000, 0x731 }, + [OLYMPUS_LUT_CHAN_552500_IDX] = { 22100, 0x1, 0x5C, 0x2AAAB, 0x732 }, + [OLYMPUS_LUT_CHAN_552625_IDX] = { 22105, 0x1, 0x5C, 0x35555, 0x732 }, + [OLYMPUS_LUT_CHAN_552750_IDX] = { 22110, 0x1, 0x5C, 0x40000, 0x733 }, + [OLYMPUS_LUT_CHAN_552875_IDX] = { 22115, 0x1, 0x5C, 0x4AAAB, 0x733 }, + [OLYMPUS_LUT_CHAN_553000_IDX] = { 22120, 0x1, 0x5C, 0x55555, 0x733 }, + [OLYMPUS_LUT_CHAN_553125_IDX] = { 22125, 0x1, 0x5C, 0x60000, 0x734 }, + [OLYMPUS_LUT_CHAN_553250_IDX] = { 22130, 0x1, 0x5C, 0x6AAAB, 0x734 }, + [OLYMPUS_LUT_CHAN_553375_IDX] = { 22135, 0x1, 0x5C, 0x75555, 0x735 }, + [OLYMPUS_LUT_CHAN_553500_IDX] = { 22140, 0x1, 0x5C, 0x80000, 0x735 }, + [OLYMPUS_LUT_CHAN_553625_IDX] = { 22145, 0x1, 0x5C, 0x8AAAB, 0x735 }, + [OLYMPUS_LUT_CHAN_553750_IDX] = { 22150, 0x1, 0x5C, 0x95555, 0x736 }, + [OLYMPUS_LUT_CHAN_553875_IDX] = { 22155, 0x1, 0x5C, 0xA0000, 0x736 }, + [OLYMPUS_LUT_CHAN_554000_IDX] = { 22160, 0x1, 0x5C, 0xAAAAB, 0x737 }, + [OLYMPUS_LUT_CHAN_554125_IDX] = { 22165, 0x1, 0x5C, 0xB5555, 0x737 }, + [OLYMPUS_LUT_CHAN_554250_IDX] = { 22170, 0x1, 0x5C, 0xC0000, 0x738 }, + [OLYMPUS_LUT_CHAN_554375_IDX] = { 22175, 0x1, 0x5C, 0xCAAAB, 0x738 }, + [OLYMPUS_LUT_CHAN_554500_IDX] = { 22180, 0x1, 0x5C, 0xD5555, 0x738 }, + [OLYMPUS_LUT_CHAN_554625_IDX] = { 22185, 0x1, 0x5C, 0xE0000, 0x739 }, + [OLYMPUS_LUT_CHAN_554750_IDX] = { 22190, 0x1, 0x5C, 0xEAAAB, 0x739 }, + [OLYMPUS_LUT_CHAN_554875_IDX] = { 22195, 0x1, 0x5C, 0xF5555, 0x73A }, + [OLYMPUS_LUT_CHAN_555000_IDX] = { 22200, 0x1, 0x5C, 0x100000, 0x73A }, + [OLYMPUS_LUT_CHAN_555125_IDX] = { 22205, 0x1, 0x5C, 0x10AAAB, 0x73A }, + [OLYMPUS_LUT_CHAN_555250_IDX] = { 22210, 0x1, 0x5C, 0x115555, 0x73B }, + [OLYMPUS_LUT_CHAN_555375_IDX] = { 22215, 0x1, 0x5C, 0x120000, 0x73B }, + [OLYMPUS_LUT_CHAN_555500_IDX] = { 22220, 0x1, 0x5C, 0x12AAAB, 0x73C }, + [OLYMPUS_LUT_CHAN_555625_IDX] = { 22225, 0x1, 0x5C, 0x135555, 0x73C }, + [OLYMPUS_LUT_CHAN_555750_IDX] = { 22230, 0x1, 0x5C, 0x140000, 0x73D }, + [OLYMPUS_LUT_CHAN_555875_IDX] = { 22235, 0x1, 0x5C, 0x14AAAB, 0x73D }, + [OLYMPUS_LUT_CHAN_556000_IDX] = { 22240, 0x1, 0x5C, 0x155555, 0x73D }, + [OLYMPUS_LUT_CHAN_556125_IDX] = { 22245, 0x1, 0x5C, 0x160000, 0x73E }, + [OLYMPUS_LUT_CHAN_556250_IDX] = { 22250, 0x1, 0x5C, 0x16AAAB, 0x73E }, + [OLYMPUS_LUT_CHAN_556375_IDX] = { 22255, 0x1, 0x5C, 0x175555, 0x73F }, + [OLYMPUS_LUT_CHAN_556500_IDX] = { 22260, 0x1, 0x5C, 0x180000, 0x73F }, + [OLYMPUS_LUT_CHAN_556625_IDX] = { 22265, 0x1, 0x5C, 0x18AAAB, 0x73F }, + [OLYMPUS_LUT_CHAN_556750_IDX] = { 22270, 0x1, 0x5C, 0x195555, 0x740 }, + [OLYMPUS_LUT_CHAN_556875_IDX] = { 22275, 0x1, 0x5C, 0x1A0000, 0x740 }, + [OLYMPUS_LUT_CHAN_557000_IDX] = { 22280, 0x1, 0x5C, 0x1AAAAB, 0x741 }, + [OLYMPUS_LUT_CHAN_557125_IDX] = { 22285, 0x1, 0x5C, 0x1B5555, 0x741 }, + [OLYMPUS_LUT_CHAN_557250_IDX] = { 22290, 0x1, 0x5C, 0x1C0000, 0x742 }, + [OLYMPUS_LUT_CHAN_557375_IDX] = { 22295, 0x1, 0x5C, 0x1CAAAB, 0x742 }, + [OLYMPUS_LUT_CHAN_557500_IDX] = { 22300, 0x1, 0x5C, 0x1D5555, 0x742 }, + [OLYMPUS_LUT_CHAN_557625_IDX] = { 22305, 0x1, 0x5C, 0x1E0000, 0x743 }, + [OLYMPUS_LUT_CHAN_557750_IDX] = { 22310, 0x1, 0x5C, 0x1EAAAB, 0x743 }, + [OLYMPUS_LUT_CHAN_557875_IDX] = { 22315, 0x1, 0x5C, 0x1F5555, 0x744 }, + [OLYMPUS_LUT_CHAN_558000_IDX] = { 22320, 0x1, 0x5D, 0x0, 0x744 }, + [OLYMPUS_LUT_CHAN_558125_IDX] = { 22325, 0x1, 0x5D, 0xAAAB, 0x744 }, + [OLYMPUS_LUT_CHAN_558250_IDX] = { 22330, 0x1, 0x5D, 0x15555, 0x745 }, + [OLYMPUS_LUT_CHAN_558375_IDX] = { 22335, 0x1, 0x5D, 0x20000, 0x745 }, + [OLYMPUS_LUT_CHAN_558500_IDX] = { 22340, 0x1, 0x5D, 0x2AAAB, 0x746 }, + [OLYMPUS_LUT_CHAN_558625_IDX] = { 22345, 0x1, 0x5D, 0x35555, 0x746 }, + [OLYMPUS_LUT_CHAN_558750_IDX] = { 22350, 0x1, 0x5D, 0x40000, 0x747 }, + [OLYMPUS_LUT_CHAN_558875_IDX] = { 22355, 0x1, 0x5D, 0x4AAAB, 0x747 }, + [OLYMPUS_LUT_CHAN_559000_IDX] = { 22360, 0x1, 0x5D, 0x55555, 0x747 }, + [OLYMPUS_LUT_CHAN_559125_IDX] = { 22365, 0x1, 0x5D, 0x60000, 0x748 }, + [OLYMPUS_LUT_CHAN_559250_IDX] = { 22370, 0x1, 0x5D, 0x6AAAB, 0x748 }, + [OLYMPUS_LUT_CHAN_559375_IDX] = { 22375, 0x1, 0x5D, 0x75555, 0x749 }, + [OLYMPUS_LUT_CHAN_559500_IDX] = { 22380, 0x1, 0x5D, 0x80000, 0x749 }, + [OLYMPUS_LUT_CHAN_559625_IDX] = { 22385, 0x1, 0x5D, 0x8AAAB, 0x749 }, + [OLYMPUS_LUT_CHAN_559750_IDX] = { 22390, 0x1, 0x5D, 0x95555, 0x74A }, + [OLYMPUS_LUT_CHAN_559875_IDX] = { 22395, 0x1, 0x5D, 0xA0000, 0x74A }, + [OLYMPUS_LUT_CHAN_560000_IDX] = { 22400, 0x1, 0x5D, 0xAAAAB, 0x74B }, + [OLYMPUS_LUT_CHAN_560125_IDX] = { 22405, 0x1, 0x5D, 0xB5555, 0x74B }, + [OLYMPUS_LUT_CHAN_560250_IDX] = { 22410, 0x1, 0x5D, 0xC0000, 0x74C }, + [OLYMPUS_LUT_CHAN_560375_IDX] = { 22415, 0x1, 0x5D, 0xCAAAB, 0x74C }, + [OLYMPUS_LUT_CHAN_560500_IDX] = { 22420, 0x1, 0x5D, 0xD5555, 0x74C }, + [OLYMPUS_LUT_CHAN_560625_IDX] = { 22425, 0x1, 0x5D, 0xE0000, 0x74D }, + [OLYMPUS_LUT_CHAN_560750_IDX] = { 22430, 0x1, 0x5D, 0xEAAAB, 0x74D }, + [OLYMPUS_LUT_CHAN_560875_IDX] = { 22435, 0x1, 0x5D, 0xF5555, 0x74E }, + [OLYMPUS_LUT_CHAN_561000_IDX] = { 22440, 0x1, 0x5D, 0x100000, 0x74E }, + [OLYMPUS_LUT_CHAN_561125_IDX] = { 22445, 0x1, 0x5D, 0x10AAAB, 0x74E }, + [OLYMPUS_LUT_CHAN_561250_IDX] = { 22450, 0x1, 0x5D, 0x115555, 0x74F }, + [OLYMPUS_LUT_CHAN_561375_IDX] = { 22455, 0x1, 0x5D, 0x120000, 0x74F }, + [OLYMPUS_LUT_CHAN_561500_IDX] = { 22460, 0x1, 0x5D, 0x12AAAB, 0x750 }, + [OLYMPUS_LUT_CHAN_561625_IDX] = { 22465, 0x1, 0x5D, 0x135555, 0x750 }, + [OLYMPUS_LUT_CHAN_561750_IDX] = { 22470, 0x1, 0x5D, 0x140000, 0x751 }, + [OLYMPUS_LUT_CHAN_561875_IDX] = { 22475, 0x1, 0x5D, 0x14AAAB, 0x751 }, + [OLYMPUS_LUT_CHAN_562000_IDX] = { 22480, 0x1, 0x5D, 0x155555, 0x751 }, + [OLYMPUS_LUT_CHAN_562125_IDX] = { 22485, 0x1, 0x5D, 0x160000, 0x752 }, + [OLYMPUS_LUT_CHAN_562250_IDX] = { 22490, 0x1, 0x5D, 0x16AAAB, 0x752 }, + [OLYMPUS_LUT_CHAN_562375_IDX] = { 22495, 0x1, 0x5D, 0x175555, 0x753 }, + [OLYMPUS_LUT_CHAN_562500_IDX] = { 22500, 0x1, 0x5D, 0x180000, 0x753 }, + [OLYMPUS_LUT_CHAN_562625_IDX] = { 22505, 0x1, 0x5D, 0x18AAAB, 0x753 }, + [OLYMPUS_LUT_CHAN_562750_IDX] = { 22510, 0x1, 0x5D, 0x195555, 0x754 }, + [OLYMPUS_LUT_CHAN_562875_IDX] = { 22515, 0x1, 0x5D, 0x1A0000, 0x754 }, + [OLYMPUS_LUT_CHAN_563000_IDX] = { 22520, 0x1, 0x5D, 0x1AAAAB, 0x755 }, + [OLYMPUS_LUT_CHAN_563125_IDX] = { 22525, 0x1, 0x5D, 0x1B5555, 0x755 }, + [OLYMPUS_LUT_CHAN_563250_IDX] = { 22530, 0x1, 0x5D, 0x1C0000, 0x756 }, + [OLYMPUS_LUT_CHAN_563375_IDX] = { 22535, 0x1, 0x5D, 0x1CAAAB, 0x756 }, + [OLYMPUS_LUT_CHAN_563500_IDX] = { 22540, 0x1, 0x5D, 0x1D5555, 0x756 }, + [OLYMPUS_LUT_CHAN_563625_IDX] = { 22545, 0x1, 0x5D, 0x1E0000, 0x757 }, + [OLYMPUS_LUT_CHAN_563750_IDX] = { 22550, 0x1, 0x5D, 0x1EAAAB, 0x757 }, + [OLYMPUS_LUT_CHAN_563875_IDX] = { 22555, 0x1, 0x5D, 0x1F5555, 0x758 }, + [OLYMPUS_LUT_CHAN_564000_IDX] = { 22560, 0x1, 0x5E, 0x0, 0x758 }, + [OLYMPUS_LUT_CHAN_564125_IDX] = { 22565, 0x1, 0x5E, 0xAAAB, 0x758 }, + [OLYMPUS_LUT_CHAN_564250_IDX] = { 22570, 0x1, 0x5E, 0x15555, 0x759 }, + [OLYMPUS_LUT_CHAN_564375_IDX] = { 22575, 0x1, 0x5E, 0x20000, 0x759 }, + [OLYMPUS_LUT_CHAN_564500_IDX] = { 22580, 0x1, 0x5E, 0x2AAAB, 0x75A }, + [OLYMPUS_LUT_CHAN_564625_IDX] = { 22585, 0x1, 0x5E, 0x35555, 0x75A }, + [OLYMPUS_LUT_CHAN_564750_IDX] = { 22590, 0x1, 0x5E, 0x40000, 0x75B }, + [OLYMPUS_LUT_CHAN_564875_IDX] = { 22595, 0x1, 0x5E, 0x4AAAB, 0x75B }, + [OLYMPUS_LUT_CHAN_565000_IDX] = { 22600, 0x1, 0x5E, 0x55555, 0x75B }, + [OLYMPUS_LUT_CHAN_565125_IDX] = { 22605, 0x1, 0x5E, 0x60000, 0x75C }, + [OLYMPUS_LUT_CHAN_565250_IDX] = { 22610, 0x1, 0x5E, 0x6AAAB, 0x75C }, + [OLYMPUS_LUT_CHAN_565375_IDX] = { 22615, 0x1, 0x5E, 0x75555, 0x75D }, + [OLYMPUS_LUT_CHAN_565500_IDX] = { 22620, 0x1, 0x5E, 0x80000, 0x75D }, + [OLYMPUS_LUT_CHAN_565625_IDX] = { 22625, 0x1, 0x5E, 0x8AAAB, 0x75D }, + [OLYMPUS_LUT_CHAN_565750_IDX] = { 22630, 0x1, 0x5E, 0x95555, 0x75E }, + [OLYMPUS_LUT_CHAN_565875_IDX] = { 22635, 0x1, 0x5E, 0xA0000, 0x75E }, + [OLYMPUS_LUT_CHAN_566000_IDX] = { 22640, 0x1, 0x5E, 0xAAAAB, 0x75F }, + [OLYMPUS_LUT_CHAN_566125_IDX] = { 22645, 0x1, 0x5E, 0xB5555, 0x75F }, + [OLYMPUS_LUT_CHAN_566250_IDX] = { 22650, 0x1, 0x5E, 0xC0000, 0x760 }, + [OLYMPUS_LUT_CHAN_566375_IDX] = { 22655, 0x1, 0x5E, 0xCAAAB, 0x760 }, + [OLYMPUS_LUT_CHAN_566500_IDX] = { 22660, 0x1, 0x5E, 0xD5555, 0x760 }, + [OLYMPUS_LUT_CHAN_566625_IDX] = { 22665, 0x1, 0x5E, 0xE0000, 0x761 }, + [OLYMPUS_LUT_CHAN_566750_IDX] = { 22670, 0x1, 0x5E, 0xEAAAB, 0x761 }, + [OLYMPUS_LUT_CHAN_566875_IDX] = { 22675, 0x1, 0x5E, 0xF5555, 0x762 }, + [OLYMPUS_LUT_CHAN_567000_IDX] = { 22680, 0x1, 0x5E, 0x100000, 0x762 }, + [OLYMPUS_LUT_CHAN_567125_IDX] = { 22685, 0x1, 0x5E, 0x10AAAB, 0x762 }, + [OLYMPUS_LUT_CHAN_567250_IDX] = { 22690, 0x1, 0x5E, 0x115555, 0x763 }, + [OLYMPUS_LUT_CHAN_567375_IDX] = { 22695, 0x1, 0x5E, 0x120000, 0x763 }, + [OLYMPUS_LUT_CHAN_567500_IDX] = { 22700, 0x1, 0x5E, 0x12AAAB, 0x764 }, + [OLYMPUS_LUT_CHAN_567625_IDX] = { 22705, 0x1, 0x5E, 0x135555, 0x764 }, + [OLYMPUS_LUT_CHAN_567750_IDX] = { 22710, 0x1, 0x5E, 0x140000, 0x765 }, + [OLYMPUS_LUT_CHAN_567875_IDX] = { 22715, 0x1, 0x5E, 0x14AAAB, 0x765 }, + [OLYMPUS_LUT_CHAN_568000_IDX] = { 22720, 0x1, 0x5E, 0x155555, 0x765 }, + [OLYMPUS_LUT_CHAN_568125_IDX] = { 22725, 0x1, 0x5E, 0x160000, 0x766 }, + [OLYMPUS_LUT_CHAN_568250_IDX] = { 22730, 0x1, 0x5E, 0x16AAAB, 0x766 }, + [OLYMPUS_LUT_CHAN_568375_IDX] = { 22735, 0x1, 0x5E, 0x175555, 0x767 }, + [OLYMPUS_LUT_CHAN_568500_IDX] = { 22740, 0x1, 0x5E, 0x180000, 0x767 }, + [OLYMPUS_LUT_CHAN_568625_IDX] = { 22745, 0x1, 0x5E, 0x18AAAB, 0x767 }, + [OLYMPUS_LUT_CHAN_568750_IDX] = { 22750, 0x1, 0x5E, 0x195555, 0x768 }, + [OLYMPUS_LUT_CHAN_568875_IDX] = { 22755, 0x1, 0x5E, 0x1A0000, 0x768 }, + [OLYMPUS_LUT_CHAN_569000_IDX] = { 22760, 0x1, 0x5E, 0x1AAAAB, 0x769 }, + [OLYMPUS_LUT_CHAN_569125_IDX] = { 22765, 0x1, 0x5E, 0x1B5555, 0x769 }, + [OLYMPUS_LUT_CHAN_569250_IDX] = { 22770, 0x1, 0x5E, 0x1C0000, 0x76A }, + [OLYMPUS_LUT_CHAN_569375_IDX] = { 22775, 0x1, 0x5E, 0x1CAAAB, 0x76A }, + [OLYMPUS_LUT_CHAN_569500_IDX] = { 22780, 0x1, 0x5E, 0x1D5555, 0x76A }, + [OLYMPUS_LUT_CHAN_569625_IDX] = { 22785, 0x1, 0x5E, 0x1E0000, 0x76B }, + [OLYMPUS_LUT_CHAN_569750_IDX] = { 22790, 0x1, 0x5E, 0x1EAAAB, 0x76B }, + [OLYMPUS_LUT_CHAN_569875_IDX] = { 22795, 0x1, 0x5E, 0x1F5555, 0x76C }, + [OLYMPUS_LUT_CHAN_570000_IDX] = { 22800, 0x1, 0x5F, 0x0, 0x76C }, + [OLYMPUS_LUT_CHAN_570125_IDX] = { 22805, 0x1, 0x5F, 0xAAAB, 0x76C }, + [OLYMPUS_LUT_CHAN_570250_IDX] = { 22810, 0x1, 0x5F, 0x15555, 0x76D }, + [OLYMPUS_LUT_CHAN_570375_IDX] = { 22815, 0x1, 0x5F, 0x20000, 0x76D }, + [OLYMPUS_LUT_CHAN_570500_IDX] = { 22820, 0x1, 0x5F, 0x2AAAB, 0x76E }, + [OLYMPUS_LUT_CHAN_570625_IDX] = { 22825, 0x1, 0x5F, 0x35555, 0x76E }, + [OLYMPUS_LUT_CHAN_570750_IDX] = { 22830, 0x1, 0x5F, 0x40000, 0x76F }, + [OLYMPUS_LUT_CHAN_570875_IDX] = { 22835, 0x1, 0x5F, 0x4AAAB, 0x76F }, + [OLYMPUS_LUT_CHAN_571000_IDX] = { 22840, 0x1, 0x5F, 0x55555, 0x76F }, + [OLYMPUS_LUT_CHAN_571125_IDX] = { 22845, 0x1, 0x5F, 0x60000, 0x770 }, + [OLYMPUS_LUT_CHAN_571250_IDX] = { 22850, 0x1, 0x5F, 0x6AAAB, 0x770 }, + [OLYMPUS_LUT_CHAN_571375_IDX] = { 22855, 0x1, 0x5F, 0x75555, 0x771 }, + [OLYMPUS_LUT_CHAN_571500_IDX] = { 22860, 0x1, 0x5F, 0x80000, 0x771 }, + [OLYMPUS_LUT_CHAN_571625_IDX] = { 22865, 0x1, 0x5F, 0x8AAAB, 0x771 }, + [OLYMPUS_LUT_CHAN_571750_IDX] = { 22870, 0x1, 0x5F, 0x95555, 0x772 }, + [OLYMPUS_LUT_CHAN_571875_IDX] = { 22875, 0x1, 0x5F, 0xA0000, 0x772 }, + [OLYMPUS_LUT_CHAN_572000_IDX] = { 22880, 0x1, 0x5F, 0xAAAAB, 0x773 }, + [OLYMPUS_LUT_CHAN_572125_IDX] = { 22885, 0x1, 0x5F, 0xB5555, 0x773 }, + [OLYMPUS_LUT_CHAN_572250_IDX] = { 22890, 0x1, 0x5F, 0xC0000, 0x774 }, + [OLYMPUS_LUT_CHAN_572375_IDX] = { 22895, 0x1, 0x5F, 0xCAAAB, 0x774 }, + [OLYMPUS_LUT_CHAN_572500_IDX] = { 22900, 0x1, 0x5F, 0xD5555, 0x774 }, + [OLYMPUS_LUT_CHAN_572625_IDX] = { 22905, 0x1, 0x5F, 0xE0000, 0x775 }, + [OLYMPUS_LUT_CHAN_572750_IDX] = { 22910, 0x1, 0x5F, 0xEAAAB, 0x775 }, + [OLYMPUS_LUT_CHAN_572875_IDX] = { 22915, 0x1, 0x5F, 0xF5555, 0x776 }, + [OLYMPUS_LUT_CHAN_573000_IDX] = { 22920, 0x1, 0x5F, 0x100000, 0x776 }, + [OLYMPUS_LUT_CHAN_573125_IDX] = { 22925, 0x1, 0x5F, 0x10AAAB, 0x776 }, + [OLYMPUS_LUT_CHAN_573250_IDX] = { 22930, 0x1, 0x5F, 0x115555, 0x777 }, + [OLYMPUS_LUT_CHAN_573375_IDX] = { 22935, 0x1, 0x5F, 0x120000, 0x777 }, + [OLYMPUS_LUT_CHAN_573500_IDX] = { 22940, 0x1, 0x5F, 0x12AAAB, 0x778 }, + [OLYMPUS_LUT_CHAN_573625_IDX] = { 22945, 0x1, 0x5F, 0x135555, 0x778 }, + [OLYMPUS_LUT_CHAN_573750_IDX] = { 22950, 0x1, 0x5F, 0x140000, 0x779 }, + [OLYMPUS_LUT_CHAN_573875_IDX] = { 22955, 0x1, 0x5F, 0x14AAAB, 0x779 }, + [OLYMPUS_LUT_CHAN_574000_IDX] = { 22960, 0x1, 0x5F, 0x155555, 0x779 }, + [OLYMPUS_LUT_CHAN_574125_IDX] = { 22965, 0x1, 0x5F, 0x160000, 0x77A }, + [OLYMPUS_LUT_CHAN_574250_IDX] = { 22970, 0x1, 0x5F, 0x16AAAB, 0x77A }, + [OLYMPUS_LUT_CHAN_574375_IDX] = { 22975, 0x1, 0x5F, 0x175555, 0x77B }, + [OLYMPUS_LUT_CHAN_574500_IDX] = { 22980, 0x1, 0x5F, 0x180000, 0x77B }, + [OLYMPUS_LUT_CHAN_574625_IDX] = { 22985, 0x1, 0x5F, 0x18AAAB, 0x77B }, + [OLYMPUS_LUT_CHAN_574750_IDX] = { 22990, 0x1, 0x5F, 0x195555, 0x77C }, + [OLYMPUS_LUT_CHAN_574875_IDX] = { 22995, 0x1, 0x5F, 0x1A0000, 0x77C }, + [OLYMPUS_LUT_CHAN_575000_IDX] = { 23000, 0x1, 0x5F, 0x1AAAAB, 0x77D }, + [OLYMPUS_LUT_CHAN_575125_IDX] = { 23005, 0x1, 0x5F, 0x1B5555, 0x77D }, + [OLYMPUS_LUT_CHAN_575250_IDX] = { 23010, 0x1, 0x5F, 0x1C0000, 0x77E }, + [OLYMPUS_LUT_CHAN_575375_IDX] = { 23015, 0x1, 0x5F, 0x1CAAAB, 0x77E }, + [OLYMPUS_LUT_CHAN_575500_IDX] = { 23020, 0x1, 0x5F, 0x1D5555, 0x77E }, + [OLYMPUS_LUT_CHAN_575625_IDX] = { 23025, 0x1, 0x5F, 0x1E0000, 0x77F }, + [OLYMPUS_LUT_CHAN_575750_IDX] = { 23030, 0x1, 0x5F, 0x1EAAAB, 0x77F }, + [OLYMPUS_LUT_CHAN_575875_IDX] = { 23035, 0x1, 0x5F, 0x1F5555, 0x780 }, + [OLYMPUS_LUT_CHAN_576000_IDX] = { 23040, 0x1, 0x60, 0x0, 0x780 }, + [OLYMPUS_LUT_CHAN_576125_IDX] = { 23045, 0x1, 0x60, 0xAAAB, 0x780 }, + [OLYMPUS_LUT_CHAN_576250_IDX] = { 23050, 0x1, 0x60, 0x15555, 0x781 }, + [OLYMPUS_LUT_CHAN_576375_IDX] = { 23055, 0x1, 0x60, 0x20000, 0x781 }, + [OLYMPUS_LUT_CHAN_576500_IDX] = { 23060, 0x1, 0x60, 0x2AAAB, 0x782 }, + [OLYMPUS_LUT_CHAN_576625_IDX] = { 23065, 0x1, 0x60, 0x35555, 0x782 }, + [OLYMPUS_LUT_CHAN_576750_IDX] = { 23070, 0x1, 0x60, 0x40000, 0x783 }, + [OLYMPUS_LUT_CHAN_576875_IDX] = { 23075, 0x1, 0x60, 0x4AAAB, 0x783 }, + [OLYMPUS_LUT_CHAN_577000_IDX] = { 23080, 0x1, 0x60, 0x55555, 0x783 }, + [OLYMPUS_LUT_CHAN_577125_IDX] = { 23085, 0x1, 0x60, 0x60000, 0x784 }, + [OLYMPUS_LUT_CHAN_577250_IDX] = { 23090, 0x1, 0x60, 0x6AAAB, 0x784 }, + [OLYMPUS_LUT_CHAN_577375_IDX] = { 23095, 0x1, 0x60, 0x75555, 0x785 }, + [OLYMPUS_LUT_CHAN_577500_IDX] = { 23100, 0x1, 0x60, 0x80000, 0x785 }, + [OLYMPUS_LUT_CHAN_577625_IDX] = { 23105, 0x1, 0x60, 0x8AAAB, 0x785 }, + [OLYMPUS_LUT_CHAN_577750_IDX] = { 23110, 0x1, 0x60, 0x95555, 0x786 }, + [OLYMPUS_LUT_CHAN_577875_IDX] = { 23115, 0x1, 0x60, 0xA0000, 0x786 }, + [OLYMPUS_LUT_CHAN_578000_IDX] = { 23120, 0x1, 0x60, 0xAAAAB, 0x787 }, + [OLYMPUS_LUT_CHAN_578125_IDX] = { 23125, 0x1, 0x60, 0xB5555, 0x787 }, + [OLYMPUS_LUT_CHAN_578250_IDX] = { 23130, 0x1, 0x60, 0xC0000, 0x788 }, + [OLYMPUS_LUT_CHAN_578375_IDX] = { 23135, 0x1, 0x60, 0xCAAAB, 0x788 }, + [OLYMPUS_LUT_CHAN_578500_IDX] = { 23140, 0x1, 0x60, 0xD5555, 0x788 }, + [OLYMPUS_LUT_CHAN_578625_IDX] = { 23145, 0x1, 0x60, 0xE0000, 0x789 }, + [OLYMPUS_LUT_CHAN_578750_IDX] = { 23150, 0x1, 0x60, 0xEAAAB, 0x789 }, + [OLYMPUS_LUT_CHAN_578875_IDX] = { 23155, 0x1, 0x60, 0xF5555, 0x78A }, + [OLYMPUS_LUT_CHAN_579000_IDX] = { 23160, 0x1, 0x60, 0x100000, 0x78A }, + [OLYMPUS_LUT_CHAN_579125_IDX] = { 23165, 0x1, 0x60, 0x10AAAB, 0x78A }, + [OLYMPUS_LUT_CHAN_579250_IDX] = { 23170, 0x1, 0x60, 0x115555, 0x78B }, + [OLYMPUS_LUT_CHAN_579375_IDX] = { 23175, 0x1, 0x60, 0x120000, 0x78B }, + [OLYMPUS_LUT_CHAN_579500_IDX] = { 23180, 0x1, 0x60, 0x12AAAB, 0x78C }, + [OLYMPUS_LUT_CHAN_579625_IDX] = { 23185, 0x1, 0x60, 0x135555, 0x78C }, + [OLYMPUS_LUT_CHAN_579750_IDX] = { 23190, 0x1, 0x60, 0x140000, 0x78D }, + [OLYMPUS_LUT_CHAN_579875_IDX] = { 23195, 0x1, 0x60, 0x14AAAB, 0x78D }, + [OLYMPUS_LUT_CHAN_580000_IDX] = { 23200, 0x1, 0x60, 0x155555, 0x78D }, + [OLYMPUS_LUT_CHAN_580125_IDX] = { 23205, 0x1, 0x60, 0x160000, 0x78E }, + [OLYMPUS_LUT_CHAN_580250_IDX] = { 23210, 0x1, 0x60, 0x16AAAB, 0x78E }, + [OLYMPUS_LUT_CHAN_580375_IDX] = { 23215, 0x1, 0x60, 0x175555, 0x78F }, + [OLYMPUS_LUT_CHAN_580500_IDX] = { 23220, 0x1, 0x60, 0x180000, 0x78F }, + [OLYMPUS_LUT_CHAN_580625_IDX] = { 23225, 0x1, 0x60, 0x18AAAB, 0x78F }, + [OLYMPUS_LUT_CHAN_580750_IDX] = { 23230, 0x1, 0x60, 0x195555, 0x790 }, + [OLYMPUS_LUT_CHAN_580875_IDX] = { 23235, 0x1, 0x60, 0x1A0000, 0x790 }, + [OLYMPUS_LUT_CHAN_581000_IDX] = { 23240, 0x1, 0x60, 0x1AAAAB, 0x791 }, + [OLYMPUS_LUT_CHAN_581125_IDX] = { 23245, 0x1, 0x60, 0x1B5555, 0x791 }, + [OLYMPUS_LUT_CHAN_581250_IDX] = { 23250, 0x1, 0x60, 0x1C0000, 0x792 }, + [OLYMPUS_LUT_CHAN_581375_IDX] = { 23255, 0x1, 0x60, 0x1CAAAB, 0x792 }, + [OLYMPUS_LUT_CHAN_581500_IDX] = { 23260, 0x1, 0x60, 0x1D5555, 0x792 }, + [OLYMPUS_LUT_CHAN_581625_IDX] = { 23265, 0x1, 0x60, 0x1E0000, 0x793 }, + [OLYMPUS_LUT_CHAN_581750_IDX] = { 23270, 0x1, 0x60, 0x1EAAAB, 0x793 }, + [OLYMPUS_LUT_CHAN_581875_IDX] = { 23275, 0x1, 0x60, 0x1F5555, 0x794 }, + [OLYMPUS_LUT_CHAN_582000_IDX] = { 23280, 0x1, 0x61, 0x0, 0x794 }, + [OLYMPUS_LUT_CHAN_582125_IDX] = { 23285, 0x1, 0x61, 0xAAAB, 0x794 }, + [OLYMPUS_LUT_CHAN_582250_IDX] = { 23290, 0x1, 0x61, 0x15555, 0x795 }, + [OLYMPUS_LUT_CHAN_582375_IDX] = { 23295, 0x1, 0x61, 0x20000, 0x795 }, + [OLYMPUS_LUT_CHAN_582500_IDX] = { 23300, 0x1, 0x61, 0x2AAAB, 0x796 }, + [OLYMPUS_LUT_CHAN_582625_IDX] = { 23305, 0x1, 0x61, 0x35555, 0x796 }, + [OLYMPUS_LUT_CHAN_582750_IDX] = { 23310, 0x1, 0x61, 0x40000, 0x797 }, + [OLYMPUS_LUT_CHAN_582875_IDX] = { 23315, 0x1, 0x61, 0x4AAAB, 0x797 }, + [OLYMPUS_LUT_CHAN_583000_IDX] = { 23320, 0x1, 0x61, 0x55555, 0x797 }, + [OLYMPUS_LUT_CHAN_583125_IDX] = { 23325, 0x1, 0x61, 0x60000, 0x798 }, + [OLYMPUS_LUT_CHAN_583250_IDX] = { 23330, 0x1, 0x61, 0x6AAAB, 0x798 }, + [OLYMPUS_LUT_CHAN_583375_IDX] = { 23335, 0x1, 0x61, 0x75555, 0x799 }, + [OLYMPUS_LUT_CHAN_583500_IDX] = { 23340, 0x1, 0x61, 0x80000, 0x799 }, + [OLYMPUS_LUT_CHAN_583625_IDX] = { 23345, 0x1, 0x61, 0x8AAAB, 0x799 }, + [OLYMPUS_LUT_CHAN_583750_IDX] = { 23350, 0x1, 0x61, 0x95555, 0x79A }, + [OLYMPUS_LUT_CHAN_583875_IDX] = { 23355, 0x1, 0x61, 0xA0000, 0x79A }, + [OLYMPUS_LUT_CHAN_584000_IDX] = { 23360, 0x1, 0x61, 0xAAAAB, 0x79B }, + [OLYMPUS_LUT_CHAN_584125_IDX] = { 23365, 0x1, 0x61, 0xB5555, 0x79B }, + [OLYMPUS_LUT_CHAN_584250_IDX] = { 23370, 0x1, 0x61, 0xC0000, 0x79C }, + [OLYMPUS_LUT_CHAN_584375_IDX] = { 23375, 0x1, 0x61, 0xCAAAB, 0x79C }, + [OLYMPUS_LUT_CHAN_584500_IDX] = { 23380, 0x1, 0x61, 0xD5555, 0x79C }, + [OLYMPUS_LUT_CHAN_584625_IDX] = { 23385, 0x1, 0x61, 0xE0000, 0x79D }, + [OLYMPUS_LUT_CHAN_584750_IDX] = { 23390, 0x1, 0x61, 0xEAAAB, 0x79D }, + [OLYMPUS_LUT_CHAN_584875_IDX] = { 23395, 0x1, 0x61, 0xF5555, 0x79E }, + [OLYMPUS_LUT_CHAN_585000_IDX] = { 23400, 0x1, 0x61, 0x100000, 0x79E }, + [OLYMPUS_LUT_CHAN_585125_IDX] = { 23405, 0x1, 0x61, 0x10AAAB, 0x79E }, + [OLYMPUS_LUT_CHAN_585250_IDX] = { 23410, 0x1, 0x61, 0x115555, 0x79F }, + [OLYMPUS_LUT_CHAN_585375_IDX] = { 23415, 0x1, 0x61, 0x120000, 0x79F }, + [OLYMPUS_LUT_CHAN_585500_IDX] = { 23420, 0x1, 0x61, 0x12AAAB, 0x7A0 }, + [OLYMPUS_LUT_CHAN_585625_IDX] = { 23425, 0x1, 0x61, 0x135555, 0x7A0 }, + [OLYMPUS_LUT_CHAN_585750_IDX] = { 23430, 0x1, 0x61, 0x140000, 0x7A1 }, + [OLYMPUS_LUT_CHAN_585875_IDX] = { 23435, 0x1, 0x61, 0x14AAAB, 0x7A1 }, + [OLYMPUS_LUT_CHAN_586000_IDX] = { 23440, 0x1, 0x61, 0x155555, 0x7A1 }, + [OLYMPUS_LUT_CHAN_586125_IDX] = { 23445, 0x1, 0x61, 0x160000, 0x7A2 }, + [OLYMPUS_LUT_CHAN_586250_IDX] = { 23450, 0x1, 0x61, 0x16AAAB, 0x7A2 }, + [OLYMPUS_LUT_CHAN_586375_IDX] = { 23455, 0x1, 0x61, 0x175555, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586500_IDX] = { 23460, 0x1, 0x61, 0x180000, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586625_IDX] = { 23465, 0x1, 0x61, 0x18AAAB, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586750_IDX] = { 23470, 0x1, 0x61, 0x195555, 0x7A4 }, + [OLYMPUS_LUT_CHAN_586875_IDX] = { 23475, 0x1, 0x61, 0x1A0000, 0x7A4 }, + [OLYMPUS_LUT_CHAN_587000_IDX] = { 23480, 0x1, 0x61, 0x1AAAAB, 0x7A5 }, + [OLYMPUS_LUT_CHAN_587125_IDX] = { 23485, 0x1, 0x61, 0x1B5555, 0x7A5 }, + [OLYMPUS_LUT_CHAN_587250_IDX] = { 23490, 0x1, 0x61, 0x1C0000, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587375_IDX] = { 23495, 0x1, 0x61, 0x1CAAAB, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587500_IDX] = { 23500, 0x1, 0x61, 0x1D5555, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587625_IDX] = { 23505, 0x1, 0x61, 0x1E0000, 0x7A7 }, + [OLYMPUS_LUT_CHAN_587750_IDX] = { 23510, 0x1, 0x61, 0x1EAAAB, 0x7A7 }, + [OLYMPUS_LUT_CHAN_587875_IDX] = { 23515, 0x1, 0x61, 0x1F5555, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588000_IDX] = { 23520, 0x1, 0x62, 0x0, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588125_IDX] = { 23525, 0x1, 0x62, 0xAAAB, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588250_IDX] = { 23530, 0x1, 0x62, 0x15555, 0x7A9 }, + [OLYMPUS_LUT_CHAN_588375_IDX] = { 23535, 0x1, 0x62, 0x20000, 0x7A9 }, + [OLYMPUS_LUT_CHAN_588500_IDX] = { 23540, 0x1, 0x62, 0x2AAAB, 0x7AA }, + [OLYMPUS_LUT_CHAN_588625_IDX] = { 23545, 0x1, 0x62, 0x35555, 0x7AA }, + [OLYMPUS_LUT_CHAN_588750_IDX] = { 23550, 0x1, 0x62, 0x40000, 0x7AB }, + [OLYMPUS_LUT_CHAN_588875_IDX] = { 23555, 0x1, 0x62, 0x4AAAB, 0x7AB }, + [OLYMPUS_LUT_CHAN_589000_IDX] = { 23560, 0x1, 0x62, 0x55555, 0x7AB }, + [OLYMPUS_LUT_CHAN_589125_IDX] = { 23565, 0x1, 0x62, 0x60000, 0x7AC }, + [OLYMPUS_LUT_CHAN_589250_IDX] = { 23570, 0x1, 0x62, 0x6AAAB, 0x7AC }, + [OLYMPUS_LUT_CHAN_589375_IDX] = { 23575, 0x1, 0x62, 0x75555, 0x7AD }, + [OLYMPUS_LUT_CHAN_589500_IDX] = { 23580, 0x1, 0x62, 0x80000, 0x7AD }, + [OLYMPUS_LUT_CHAN_589625_IDX] = { 23585, 0x1, 0x62, 0x8AAAB, 0x7AD }, + [OLYMPUS_LUT_CHAN_589750_IDX] = { 23590, 0x1, 0x62, 0x95555, 0x7AE }, + [OLYMPUS_LUT_CHAN_589875_IDX] = { 23595, 0x1, 0x62, 0xA0000, 0x7AE }, + [OLYMPUS_LUT_CHAN_590000_IDX] = { 23600, 0x1, 0x62, 0xAAAAB, 0x7AF }, + [OLYMPUS_LUT_CHAN_590125_IDX] = { 23605, 0x1, 0x62, 0xB5555, 0x7AF }, + [OLYMPUS_LUT_CHAN_590250_IDX] = { 23610, 0x1, 0x62, 0xC0000, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590375_IDX] = { 23615, 0x1, 0x62, 0xCAAAB, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590500_IDX] = { 23620, 0x1, 0x62, 0xD5555, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590625_IDX] = { 23625, 0x1, 0x62, 0xE0000, 0x7B1 }, + [OLYMPUS_LUT_CHAN_590750_IDX] = { 23630, 0x1, 0x62, 0xEAAAB, 0x7B1 }, + [OLYMPUS_LUT_CHAN_590875_IDX] = { 23635, 0x1, 0x62, 0xF5555, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591000_IDX] = { 23640, 0x1, 0x62, 0x100000, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591125_IDX] = { 23645, 0x1, 0x62, 0x10AAAB, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591250_IDX] = { 23650, 0x1, 0x62, 0x115555, 0x7B3 }, + [OLYMPUS_LUT_CHAN_591375_IDX] = { 23655, 0x1, 0x62, 0x120000, 0x7B3 }, + [OLYMPUS_LUT_CHAN_591500_IDX] = { 23660, 0x1, 0x62, 0x12AAAB, 0x7B4 }, + [OLYMPUS_LUT_CHAN_591625_IDX] = { 23665, 0x1, 0x62, 0x135555, 0x7B4 }, + [OLYMPUS_LUT_CHAN_591750_IDX] = { 23670, 0x1, 0x62, 0x140000, 0x7B5 }, + [OLYMPUS_LUT_CHAN_591875_IDX] = { 23675, 0x1, 0x62, 0x14AAAB, 0x7B5 }, + [OLYMPUS_LUT_CHAN_592000_IDX] = { 23680, 0x1, 0x62, 0x155555, 0x7B5 }, + [OLYMPUS_LUT_CHAN_592125_IDX] = { 23685, 0x1, 0x62, 0x160000, 0x7B6 }, + [OLYMPUS_LUT_CHAN_592250_IDX] = { 23690, 0x1, 0x62, 0x16AAAB, 0x7B6 }, + [OLYMPUS_LUT_CHAN_592375_IDX] = { 23695, 0x1, 0x62, 0x175555, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592500_IDX] = { 23700, 0x1, 0x62, 0x180000, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592625_IDX] = { 23705, 0x1, 0x62, 0x18AAAB, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592750_IDX] = { 23710, 0x1, 0x62, 0x195555, 0x7B8 }, + [OLYMPUS_LUT_CHAN_592875_IDX] = { 23715, 0x1, 0x62, 0x1A0000, 0x7B8 }, + [OLYMPUS_LUT_CHAN_593000_IDX] = { 23720, 0x1, 0x62, 0x1AAAAB, 0x7B9 }, + [OLYMPUS_LUT_CHAN_593125_IDX] = { 23725, 0x1, 0x62, 0x1B5555, 0x7B9 }, + [OLYMPUS_LUT_CHAN_593250_IDX] = { 23730, 0x1, 0x62, 0x1C0000, 0x7BA }, + [OLYMPUS_LUT_CHAN_593375_IDX] = { 23735, 0x1, 0x62, 0x1CAAAB, 0x7BA }, + [OLYMPUS_LUT_CHAN_593500_IDX] = { 23740, 0x1, 0x62, 0x1D5555, 0x7BA }, + [OLYMPUS_LUT_CHAN_593625_IDX] = { 23745, 0x1, 0x62, 0x1E0000, 0x7BB }, + [OLYMPUS_LUT_CHAN_593750_IDX] = { 23750, 0x1, 0x62, 0x1EAAAB, 0x7BB }, + [OLYMPUS_LUT_CHAN_593875_IDX] = { 23755, 0x1, 0x62, 0x1F5555, 0x7BC }, + [OLYMPUS_LUT_CHAN_594000_IDX] = { 23760, 0x1, 0x63, 0x0, 0x7BC }, + [OLYMPUS_LUT_CHAN_594125_IDX] = { 23765, 0x1, 0x63, 0xAAAB, 0x7BC }, + [OLYMPUS_LUT_CHAN_594250_IDX] = { 23770, 0x1, 0x63, 0x15555, 0x7BD }, + [OLYMPUS_LUT_CHAN_594375_IDX] = { 23775, 0x1, 0x63, 0x20000, 0x7BD }, + [OLYMPUS_LUT_CHAN_594500_IDX] = { 23780, 0x1, 0x63, 0x2AAAB, 0x7BE }, + [OLYMPUS_LUT_CHAN_594625_IDX] = { 23785, 0x1, 0x63, 0x35555, 0x7BE }, + [OLYMPUS_LUT_CHAN_594750_IDX] = { 23790, 0x1, 0x63, 0x40000, 0x7BF }, + [OLYMPUS_LUT_CHAN_594875_IDX] = { 23795, 0x1, 0x63, 0x4AAAB, 0x7BF }, + [OLYMPUS_LUT_CHAN_595000_IDX] = { 23800, 0x1, 0x63, 0x55555, 0x7BF }, + [OLYMPUS_LUT_CHAN_595125_IDX] = { 23805, 0x1, 0x63, 0x60000, 0x7C0 }, + [OLYMPUS_LUT_CHAN_595250_IDX] = { 23810, 0x1, 0x63, 0x6AAAB, 0x7C0 }, + [OLYMPUS_LUT_CHAN_595375_IDX] = { 23815, 0x1, 0x63, 0x75555, 0x7C1 }, + [OLYMPUS_LUT_CHAN_595500_IDX] = { 23820, 0x1, 0x63, 0x80000, 0x7C1 }, + [OLYMPUS_LUT_CHAN_595625_IDX] = { 23825, 0x1, 0x63, 0x8AAAB, 0x7C1 }, + [OLYMPUS_LUT_CHAN_595750_IDX] = { 23830, 0x1, 0x63, 0x95555, 0x7C2 }, + [OLYMPUS_LUT_CHAN_595875_IDX] = { 23835, 0x1, 0x63, 0xA0000, 0x7C2 }, + [OLYMPUS_LUT_CHAN_596000_IDX] = { 23840, 0x1, 0x63, 0xAAAAB, 0x7C3 }, + [OLYMPUS_LUT_CHAN_596125_IDX] = { 23845, 0x1, 0x63, 0xB5555, 0x7C3 }, + [OLYMPUS_LUT_CHAN_596250_IDX] = { 23850, 0x1, 0x63, 0xC0000, 0x7C4 }, + [OLYMPUS_LUT_CHAN_596375_IDX] = { 23855, 0x1, 0x63, 0xCAAAB, 0x7C4 }, + [OLYMPUS_LUT_CHAN_596500_IDX] = { 23860, 0x1, 0x63, 0xD5555, 0x7C4 }, + [OLYMPUS_LUT_CHAN_596625_IDX] = { 23865, 0x1, 0x63, 0xE0000, 0x7C5 }, + [OLYMPUS_LUT_CHAN_596750_IDX] = { 23870, 0x1, 0x63, 0xEAAAB, 0x7C5 }, + [OLYMPUS_LUT_CHAN_596875_IDX] = { 23875, 0x1, 0x63, 0xF5555, 0x7C6 }, + [OLYMPUS_LUT_CHAN_597000_IDX] = { 23880, 0x1, 0x63, 0x100000, 0x7C6 }, + [OLYMPUS_LUT_CHAN_597125_IDX] = { 23885, 0x1, 0x63, 0x10AAAB, 0x7C6 }, + [OLYMPUS_LUT_CHAN_597250_IDX] = { 23890, 0x1, 0x63, 0x115555, 0x7C7 }, + [OLYMPUS_LUT_CHAN_597375_IDX] = { 23895, 0x1, 0x63, 0x120000, 0x7C7 }, + [OLYMPUS_LUT_CHAN_597500_IDX] = { 23900, 0x1, 0x63, 0x12AAAB, 0x7C8 }, + [OLYMPUS_LUT_CHAN_597625_IDX] = { 23905, 0x1, 0x63, 0x135555, 0x7C8 }, + [OLYMPUS_LUT_CHAN_597750_IDX] = { 23910, 0x1, 0x63, 0x140000, 0x7C9 }, + [OLYMPUS_LUT_CHAN_597875_IDX] = { 23915, 0x1, 0x63, 0x14AAAB, 0x7C9 }, + [OLYMPUS_LUT_CHAN_598000_IDX] = { 23920, 0x1, 0x63, 0x155555, 0x7C9 }, + [OLYMPUS_LUT_CHAN_598125_IDX] = { 23925, 0x1, 0x63, 0x160000, 0x7CA }, + [OLYMPUS_LUT_CHAN_598250_IDX] = { 23930, 0x1, 0x63, 0x16AAAB, 0x7CA }, + [OLYMPUS_LUT_CHAN_598375_IDX] = { 23935, 0x1, 0x63, 0x175555, 0x7CB }, + [OLYMPUS_LUT_CHAN_598500_IDX] = { 23940, 0x1, 0x63, 0x180000, 0x7CB }, + [OLYMPUS_LUT_CHAN_598625_IDX] = { 23945, 0x1, 0x63, 0x18AAAB, 0x7CB }, + [OLYMPUS_LUT_CHAN_598750_IDX] = { 23950, 0x1, 0x63, 0x195555, 0x7CC }, + [OLYMPUS_LUT_CHAN_598875_IDX] = { 23955, 0x1, 0x63, 0x1A0000, 0x7CC }, + [OLYMPUS_LUT_CHAN_599000_IDX] = { 23960, 0x1, 0x63, 0x1AAAAB, 0x7CD }, + [OLYMPUS_LUT_CHAN_599125_IDX] = { 23965, 0x1, 0x63, 0x1B5555, 0x7CD }, + [OLYMPUS_LUT_CHAN_599250_IDX] = { 23970, 0x1, 0x63, 0x1C0000, 0x7CE }, + [OLYMPUS_LUT_CHAN_599375_IDX] = { 23975, 0x1, 0x63, 0x1CAAAB, 0x7CE }, + [OLYMPUS_LUT_CHAN_599500_IDX] = { 23980, 0x1, 0x63, 0x1D5555, 0x7CE }, + [OLYMPUS_LUT_CHAN_599625_IDX] = { 23985, 0x1, 0x63, 0x1E0000, 0x7CF }, + [OLYMPUS_LUT_CHAN_599750_IDX] = { 23990, 0x1, 0x63, 0x1EAAAB, 0x7CF }, + [OLYMPUS_LUT_CHAN_599875_IDX] = { 23995, 0x1, 0x63, 0x1F5555, 0x7D0 }, + [OLYMPUS_LUT_CHAN_600000_IDX] = { 24000, 0x1, 0x64, 0x0, 0x7D0 } +}; + +const struct olympus_lut_line olympus_lut_5g_60_mhz_s1[OLYMPUS_LUT_CHAN_5G_MAX] = { + [OLYMPUS_LUT_CHAN_516000_IDX] = { 20640, 0x0, 0x39, 0x11C71C, 0x6BF }, + [OLYMPUS_LUT_CHAN_516125_IDX] = { 20645, 0x0, 0x39, 0xB1C72, 0x6B8 }, + [OLYMPUS_LUT_CHAN_516250_IDX] = { 20650, 0x0, 0x39, 0xB8E39, 0x6B9 }, + [OLYMPUS_LUT_CHAN_516375_IDX] = { 20655, 0x0, 0x39, 0xC0000, 0x6B9 }, + [OLYMPUS_LUT_CHAN_516500_IDX] = { 20660, 0x0, 0x39, 0xC71C7, 0x6BA }, + [OLYMPUS_LUT_CHAN_516625_IDX] = { 20665, 0x0, 0x39, 0xCE38E, 0x6BA }, + [OLYMPUS_LUT_CHAN_516750_IDX] = { 20670, 0x0, 0x39, 0xD5555, 0x6BB }, + [OLYMPUS_LUT_CHAN_516875_IDX] = { 20675, 0x0, 0x39, 0xDC71C, 0x6BB }, + [OLYMPUS_LUT_CHAN_517000_IDX] = { 20680, 0x0, 0x39, 0xE38E4, 0x6BB }, + [OLYMPUS_LUT_CHAN_517125_IDX] = { 20685, 0x0, 0x39, 0xEAAAB, 0x6BC }, + [OLYMPUS_LUT_CHAN_517250_IDX] = { 20690, 0x0, 0x39, 0xF1C72, 0x6BC }, + [OLYMPUS_LUT_CHAN_517375_IDX] = { 20695, 0x0, 0x39, 0xF8E39, 0x6BD }, + [OLYMPUS_LUT_CHAN_517500_IDX] = { 20700, 0x0, 0x39, 0x100000, 0x6BD }, + [OLYMPUS_LUT_CHAN_517625_IDX] = { 20705, 0x0, 0x39, 0x1071C7, 0x6BD }, + [OLYMPUS_LUT_CHAN_517750_IDX] = { 20710, 0x0, 0x39, 0x10E38E, 0x6BE }, + [OLYMPUS_LUT_CHAN_517875_IDX] = { 20715, 0x0, 0x39, 0x115555, 0x6BE }, + [OLYMPUS_LUT_CHAN_518000_IDX] = { 20720, 0x1, 0x39, 0x11C71C, 0x6BF }, + [OLYMPUS_LUT_CHAN_518125_IDX] = { 20725, 0x1, 0x39, 0x1238E4, 0x6BF }, + [OLYMPUS_LUT_CHAN_518250_IDX] = { 20730, 0x1, 0x39, 0x12AAAB, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518375_IDX] = { 20735, 0x1, 0x39, 0x131C72, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518500_IDX] = { 20740, 0x1, 0x39, 0x138E39, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518625_IDX] = { 20745, 0x1, 0x39, 0x140000, 0x6C1 }, + [OLYMPUS_LUT_CHAN_518750_IDX] = { 20750, 0x1, 0x39, 0x1471C7, 0x6C1 }, + [OLYMPUS_LUT_CHAN_518875_IDX] = { 20755, 0x1, 0x39, 0x14E38E, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519000_IDX] = { 20760, 0x1, 0x39, 0x155555, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519125_IDX] = { 20765, 0x1, 0x39, 0x15C71C, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519250_IDX] = { 20770, 0x1, 0x39, 0x1638E4, 0x6C3 }, + [OLYMPUS_LUT_CHAN_519375_IDX] = { 20775, 0x1, 0x39, 0x16AAAB, 0x6C3 }, + [OLYMPUS_LUT_CHAN_519500_IDX] = { 20780, 0x1, 0x39, 0x171C72, 0x6C4 }, + [OLYMPUS_LUT_CHAN_519625_IDX] = { 20785, 0x1, 0x39, 0x178E39, 0x6C4 }, + [OLYMPUS_LUT_CHAN_519750_IDX] = { 20790, 0x1, 0x39, 0x180000, 0x6C5 }, + [OLYMPUS_LUT_CHAN_519875_IDX] = { 20795, 0x1, 0x39, 0x1871C7, 0x6C5 }, + [OLYMPUS_LUT_CHAN_520000_IDX] = { 20800, 0x1, 0x39, 0x18E38E, 0x6C5 }, + [OLYMPUS_LUT_CHAN_520125_IDX] = { 20805, 0x1, 0x39, 0x195555, 0x6C6 }, + [OLYMPUS_LUT_CHAN_520250_IDX] = { 20810, 0x1, 0x39, 0x19C71C, 0x6C6 }, + [OLYMPUS_LUT_CHAN_520375_IDX] = { 20815, 0x1, 0x39, 0x1A38E4, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520500_IDX] = { 20820, 0x1, 0x39, 0x1AAAAB, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520625_IDX] = { 20825, 0x1, 0x39, 0x1B1C72, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520750_IDX] = { 20830, 0x1, 0x39, 0x1B8E39, 0x6C8 }, + [OLYMPUS_LUT_CHAN_520875_IDX] = { 20835, 0x1, 0x39, 0x1C0000, 0x6C8 }, + [OLYMPUS_LUT_CHAN_521000_IDX] = { 20840, 0x1, 0x39, 0x1C71C7, 0x6C9 }, + [OLYMPUS_LUT_CHAN_521125_IDX] = { 20845, 0x1, 0x39, 0x1CE38E, 0x6C9 }, + [OLYMPUS_LUT_CHAN_521250_IDX] = { 20850, 0x1, 0x39, 0x1D5555, 0x6CA }, + [OLYMPUS_LUT_CHAN_521375_IDX] = { 20855, 0x1, 0x39, 0x1DC71C, 0x6CA }, + [OLYMPUS_LUT_CHAN_521500_IDX] = { 20860, 0x1, 0x39, 0x1E38E4, 0x6CA }, + [OLYMPUS_LUT_CHAN_521625_IDX] = { 20865, 0x1, 0x39, 0x1EAAAB, 0x6CB }, + [OLYMPUS_LUT_CHAN_521750_IDX] = { 20870, 0x1, 0x39, 0x1F1C72, 0x6CB }, + [OLYMPUS_LUT_CHAN_521875_IDX] = { 20875, 0x1, 0x39, 0x1F8E39, 0x6CC }, + [OLYMPUS_LUT_CHAN_522000_IDX] = { 20880, 0x1, 0x3A, 0x0, 0x6CC }, + [OLYMPUS_LUT_CHAN_522125_IDX] = { 20885, 0x1, 0x3A, 0x71C7, 0x6CC }, + [OLYMPUS_LUT_CHAN_522250_IDX] = { 20890, 0x1, 0x3A, 0xE38E, 0x6CD }, + [OLYMPUS_LUT_CHAN_522375_IDX] = { 20895, 0x1, 0x3A, 0x15555, 0x6CD }, + [OLYMPUS_LUT_CHAN_522500_IDX] = { 20900, 0x1, 0x3A, 0x1C71C, 0x6CE }, + [OLYMPUS_LUT_CHAN_522625_IDX] = { 20905, 0x1, 0x3A, 0x238E4, 0x6CE }, + [OLYMPUS_LUT_CHAN_522750_IDX] = { 20910, 0x1, 0x3A, 0x2AAAB, 0x6CF }, + [OLYMPUS_LUT_CHAN_522875_IDX] = { 20915, 0x1, 0x3A, 0x31C72, 0x6CF }, + [OLYMPUS_LUT_CHAN_523000_IDX] = { 20920, 0x1, 0x3A, 0x38E39, 0x6CF }, + [OLYMPUS_LUT_CHAN_523125_IDX] = { 20925, 0x1, 0x3A, 0x40000, 0x6D0 }, + [OLYMPUS_LUT_CHAN_523250_IDX] = { 20930, 0x1, 0x3A, 0x471C7, 0x6D0 }, + [OLYMPUS_LUT_CHAN_523375_IDX] = { 20935, 0x1, 0x3A, 0x4E38E, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523500_IDX] = { 20940, 0x1, 0x3A, 0x55555, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523625_IDX] = { 20945, 0x1, 0x3A, 0x5C71C, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523750_IDX] = { 20950, 0x1, 0x3A, 0x638E4, 0x6D2 }, + [OLYMPUS_LUT_CHAN_523875_IDX] = { 20955, 0x1, 0x3A, 0x6AAAB, 0x6D2 }, + [OLYMPUS_LUT_CHAN_524000_IDX] = { 20960, 0x1, 0x3A, 0x71C72, 0x6D3 }, + [OLYMPUS_LUT_CHAN_524125_IDX] = { 20965, 0x1, 0x3A, 0x78E39, 0x6D3 }, + [OLYMPUS_LUT_CHAN_524250_IDX] = { 20970, 0x1, 0x3A, 0x80000, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524375_IDX] = { 20975, 0x1, 0x3A, 0x871C7, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524500_IDX] = { 20980, 0x1, 0x3A, 0x8E38E, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524625_IDX] = { 20985, 0x1, 0x3A, 0x95555, 0x6D5 }, + [OLYMPUS_LUT_CHAN_524750_IDX] = { 20990, 0x1, 0x3A, 0x9C71C, 0x6D5 }, + [OLYMPUS_LUT_CHAN_524875_IDX] = { 20995, 0x1, 0x3A, 0xA38E4, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525000_IDX] = { 21000, 0x1, 0x3A, 0xAAAAB, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525125_IDX] = { 21005, 0x1, 0x3A, 0xB1C72, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525250_IDX] = { 21010, 0x1, 0x3A, 0xB8E39, 0x6D7 }, + [OLYMPUS_LUT_CHAN_525375_IDX] = { 21015, 0x1, 0x3A, 0xC0000, 0x6D7 }, + [OLYMPUS_LUT_CHAN_525500_IDX] = { 21020, 0x1, 0x3A, 0xC71C7, 0x6D8 }, + [OLYMPUS_LUT_CHAN_525625_IDX] = { 21025, 0x1, 0x3A, 0xCE38E, 0x6D8 }, + [OLYMPUS_LUT_CHAN_525750_IDX] = { 21030, 0x1, 0x3A, 0xD5555, 0x6D9 }, + [OLYMPUS_LUT_CHAN_525875_IDX] = { 21035, 0x1, 0x3A, 0xDC71C, 0x6D9 }, + [OLYMPUS_LUT_CHAN_526000_IDX] = { 21040, 0x1, 0x3A, 0xE38E4, 0x6D9 }, + [OLYMPUS_LUT_CHAN_526125_IDX] = { 21045, 0x1, 0x3A, 0xEAAAB, 0x6DA }, + [OLYMPUS_LUT_CHAN_526250_IDX] = { 21050, 0x1, 0x3A, 0xF1C72, 0x6DA }, + [OLYMPUS_LUT_CHAN_526375_IDX] = { 21055, 0x1, 0x3A, 0xF8E39, 0x6DB }, + [OLYMPUS_LUT_CHAN_526500_IDX] = { 21060, 0x1, 0x3A, 0x100000, 0x6DB }, + [OLYMPUS_LUT_CHAN_526625_IDX] = { 21065, 0x1, 0x3A, 0x1071C7, 0x6DB }, + [OLYMPUS_LUT_CHAN_526750_IDX] = { 21070, 0x1, 0x3A, 0x10E38E, 0x6DC }, + [OLYMPUS_LUT_CHAN_526875_IDX] = { 21075, 0x1, 0x3A, 0x115555, 0x6DC }, + [OLYMPUS_LUT_CHAN_527000_IDX] = { 21080, 0x1, 0x3A, 0x11C71C, 0x6DD }, + [OLYMPUS_LUT_CHAN_527125_IDX] = { 21085, 0x1, 0x3A, 0x1238E4, 0x6DD }, + [OLYMPUS_LUT_CHAN_527250_IDX] = { 21090, 0x1, 0x3A, 0x12AAAB, 0x6DE }, + [OLYMPUS_LUT_CHAN_527375_IDX] = { 21095, 0x1, 0x3A, 0x131C72, 0x6DE }, + [OLYMPUS_LUT_CHAN_527500_IDX] = { 21100, 0x1, 0x3A, 0x138E39, 0x6DE }, + [OLYMPUS_LUT_CHAN_527625_IDX] = { 21105, 0x1, 0x3A, 0x140000, 0x6DF }, + [OLYMPUS_LUT_CHAN_527750_IDX] = { 21110, 0x1, 0x3A, 0x1471C7, 0x6DF }, + [OLYMPUS_LUT_CHAN_527875_IDX] = { 21115, 0x1, 0x3A, 0x14E38E, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528000_IDX] = { 21120, 0x1, 0x3A, 0x155555, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528125_IDX] = { 21125, 0x1, 0x3A, 0x15C71C, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528250_IDX] = { 21130, 0x1, 0x3A, 0x1638E4, 0x6E1 }, + [OLYMPUS_LUT_CHAN_528375_IDX] = { 21135, 0x1, 0x3A, 0x16AAAB, 0x6E1 }, + [OLYMPUS_LUT_CHAN_528500_IDX] = { 21140, 0x1, 0x3A, 0x171C72, 0x6E2 }, + [OLYMPUS_LUT_CHAN_528625_IDX] = { 21145, 0x1, 0x3A, 0x178E39, 0x6E2 }, + [OLYMPUS_LUT_CHAN_528750_IDX] = { 21150, 0x1, 0x3A, 0x180000, 0x6E3 }, + [OLYMPUS_LUT_CHAN_528875_IDX] = { 21155, 0x1, 0x3A, 0x1871C7, 0x6E3 }, + [OLYMPUS_LUT_CHAN_529000_IDX] = { 21160, 0x1, 0x3A, 0x18E38E, 0x6E3 }, + [OLYMPUS_LUT_CHAN_529125_IDX] = { 21165, 0x1, 0x3A, 0x195555, 0x6E4 }, + [OLYMPUS_LUT_CHAN_529250_IDX] = { 21170, 0x1, 0x3A, 0x19C71C, 0x6E4 }, + [OLYMPUS_LUT_CHAN_529375_IDX] = { 21175, 0x1, 0x3A, 0x1A38E4, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529500_IDX] = { 21180, 0x1, 0x3A, 0x1AAAAB, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529625_IDX] = { 21185, 0x1, 0x3A, 0x1B1C72, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529750_IDX] = { 21190, 0x1, 0x3A, 0x1B8E39, 0x6E6 }, + [OLYMPUS_LUT_CHAN_529875_IDX] = { 21195, 0x1, 0x3A, 0x1C0000, 0x6E6 }, + [OLYMPUS_LUT_CHAN_530000_IDX] = { 21200, 0x1, 0x3A, 0x1C71C7, 0x6E7 }, + [OLYMPUS_LUT_CHAN_530125_IDX] = { 21205, 0x1, 0x3A, 0x1CE38E, 0x6E7 }, + [OLYMPUS_LUT_CHAN_530250_IDX] = { 21210, 0x1, 0x3A, 0x1D5555, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530375_IDX] = { 21215, 0x1, 0x3A, 0x1DC71C, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530500_IDX] = { 21220, 0x1, 0x3A, 0x1E38E4, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530625_IDX] = { 21225, 0x1, 0x3A, 0x1EAAAB, 0x6E9 }, + [OLYMPUS_LUT_CHAN_530750_IDX] = { 21230, 0x1, 0x3A, 0x1F1C72, 0x6E9 }, + [OLYMPUS_LUT_CHAN_530875_IDX] = { 21235, 0x1, 0x3A, 0x1F8E39, 0x6EA }, + [OLYMPUS_LUT_CHAN_531000_IDX] = { 21240, 0x1, 0x3B, 0x0, 0x6EA }, + [OLYMPUS_LUT_CHAN_531125_IDX] = { 21245, 0x1, 0x3B, 0x71C7, 0x6EA }, + [OLYMPUS_LUT_CHAN_531250_IDX] = { 21250, 0x1, 0x3B, 0xE38E, 0x6EB }, + [OLYMPUS_LUT_CHAN_531375_IDX] = { 21255, 0x1, 0x3B, 0x15555, 0x6EB }, + [OLYMPUS_LUT_CHAN_531500_IDX] = { 21260, 0x1, 0x3B, 0x1C71C, 0x6EC }, + [OLYMPUS_LUT_CHAN_531625_IDX] = { 21265, 0x1, 0x3B, 0x238E4, 0x6EC }, + [OLYMPUS_LUT_CHAN_531750_IDX] = { 21270, 0x1, 0x3B, 0x2AAAB, 0x6ED }, + [OLYMPUS_LUT_CHAN_531875_IDX] = { 21275, 0x1, 0x3B, 0x31C72, 0x6ED }, + [OLYMPUS_LUT_CHAN_532000_IDX] = { 21280, 0x1, 0x3B, 0x38E39, 0x6ED }, + [OLYMPUS_LUT_CHAN_532125_IDX] = { 21285, 0x1, 0x3B, 0x40000, 0x6EE }, + [OLYMPUS_LUT_CHAN_532250_IDX] = { 21290, 0x1, 0x3B, 0x471C7, 0x6EE }, + [OLYMPUS_LUT_CHAN_532375_IDX] = { 21295, 0x1, 0x3B, 0x4E38E, 0x6EF }, + [OLYMPUS_LUT_CHAN_532500_IDX] = { 21300, 0x1, 0x3B, 0x55555, 0x6EF }, + [OLYMPUS_LUT_CHAN_532625_IDX] = { 21305, 0x1, 0x3B, 0x5C71C, 0x6EF }, + [OLYMPUS_LUT_CHAN_532750_IDX] = { 21310, 0x1, 0x3B, 0x638E4, 0x6F0 }, + [OLYMPUS_LUT_CHAN_532875_IDX] = { 21315, 0x1, 0x3B, 0x6AAAB, 0x6F0 }, + [OLYMPUS_LUT_CHAN_533000_IDX] = { 21320, 0x1, 0x3B, 0x71C72, 0x6F1 }, + [OLYMPUS_LUT_CHAN_533125_IDX] = { 21325, 0x1, 0x3B, 0x78E39, 0x6F1 }, + [OLYMPUS_LUT_CHAN_533250_IDX] = { 21330, 0x1, 0x3B, 0x80000, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533375_IDX] = { 21335, 0x1, 0x3B, 0x871C7, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533500_IDX] = { 21340, 0x1, 0x3B, 0x8E38E, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533625_IDX] = { 21345, 0x1, 0x3B, 0x95555, 0x6F3 }, + [OLYMPUS_LUT_CHAN_533750_IDX] = { 21350, 0x1, 0x3B, 0x9C71C, 0x6F3 }, + [OLYMPUS_LUT_CHAN_533875_IDX] = { 21355, 0x1, 0x3B, 0xA38E4, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534000_IDX] = { 21360, 0x1, 0x3B, 0xAAAAB, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534125_IDX] = { 21365, 0x1, 0x3B, 0xB1C72, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534250_IDX] = { 21370, 0x1, 0x3B, 0xB8E39, 0x6F5 }, + [OLYMPUS_LUT_CHAN_534375_IDX] = { 21375, 0x1, 0x3B, 0xC0000, 0x6F5 }, + [OLYMPUS_LUT_CHAN_534500_IDX] = { 21380, 0x1, 0x3B, 0xC71C7, 0x6F6 }, + [OLYMPUS_LUT_CHAN_534625_IDX] = { 21385, 0x1, 0x3B, 0xCE38E, 0x6F6 }, + [OLYMPUS_LUT_CHAN_534750_IDX] = { 21390, 0x1, 0x3B, 0xD5555, 0x6F7 }, + [OLYMPUS_LUT_CHAN_534875_IDX] = { 21395, 0x1, 0x3B, 0xDC71C, 0x6F7 }, + [OLYMPUS_LUT_CHAN_535000_IDX] = { 21400, 0x1, 0x3B, 0xE38E4, 0x6F7 }, + [OLYMPUS_LUT_CHAN_535125_IDX] = { 21405, 0x1, 0x3B, 0xEAAAB, 0x6F8 }, + [OLYMPUS_LUT_CHAN_535250_IDX] = { 21410, 0x1, 0x3B, 0xF1C72, 0x6F8 }, + [OLYMPUS_LUT_CHAN_535375_IDX] = { 21415, 0x1, 0x3B, 0xF8E39, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535500_IDX] = { 21420, 0x1, 0x3B, 0x100000, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535625_IDX] = { 21425, 0x1, 0x3B, 0x1071C7, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535750_IDX] = { 21430, 0x1, 0x3B, 0x10E38E, 0x6FA }, + [OLYMPUS_LUT_CHAN_535875_IDX] = { 21435, 0x1, 0x3B, 0x115555, 0x6FA }, + [OLYMPUS_LUT_CHAN_536000_IDX] = { 21440, 0x1, 0x3B, 0x11C71C, 0x6FB }, + [OLYMPUS_LUT_CHAN_536125_IDX] = { 21445, 0x1, 0x3B, 0x1238E4, 0x6FB }, + [OLYMPUS_LUT_CHAN_536250_IDX] = { 21450, 0x1, 0x3B, 0x12AAAB, 0x6FC }, + [OLYMPUS_LUT_CHAN_536375_IDX] = { 21455, 0x1, 0x3B, 0x131C72, 0x6FC }, + [OLYMPUS_LUT_CHAN_536500_IDX] = { 21460, 0x1, 0x3B, 0x138E39, 0x6FC }, + [OLYMPUS_LUT_CHAN_536625_IDX] = { 21465, 0x1, 0x3B, 0x140000, 0x6FD }, + [OLYMPUS_LUT_CHAN_536750_IDX] = { 21470, 0x1, 0x3B, 0x1471C7, 0x6FD }, + [OLYMPUS_LUT_CHAN_536875_IDX] = { 21475, 0x1, 0x3B, 0x14E38E, 0x6FE }, + [OLYMPUS_LUT_CHAN_537000_IDX] = { 21480, 0x1, 0x3B, 0x155555, 0x6FE }, + [OLYMPUS_LUT_CHAN_537125_IDX] = { 21485, 0x1, 0x3B, 0x15C71C, 0x6FE }, + [OLYMPUS_LUT_CHAN_537250_IDX] = { 21490, 0x1, 0x3B, 0x1638E4, 0x6FF }, + [OLYMPUS_LUT_CHAN_537375_IDX] = { 21495, 0x1, 0x3B, 0x16AAAB, 0x6FF }, + [OLYMPUS_LUT_CHAN_537500_IDX] = { 21500, 0x1, 0x3B, 0x171C72, 0x700 }, + [OLYMPUS_LUT_CHAN_537625_IDX] = { 21505, 0x1, 0x3B, 0x178E39, 0x700 }, + [OLYMPUS_LUT_CHAN_537750_IDX] = { 21510, 0x1, 0x3B, 0x180000, 0x701 }, + [OLYMPUS_LUT_CHAN_537875_IDX] = { 21515, 0x1, 0x3B, 0x1871C7, 0x701 }, + [OLYMPUS_LUT_CHAN_538000_IDX] = { 21520, 0x1, 0x3B, 0x18E38E, 0x701 }, + [OLYMPUS_LUT_CHAN_538125_IDX] = { 21525, 0x1, 0x3B, 0x195555, 0x702 }, + [OLYMPUS_LUT_CHAN_538250_IDX] = { 21530, 0x1, 0x3B, 0x19C71C, 0x702 }, + [OLYMPUS_LUT_CHAN_538375_IDX] = { 21535, 0x1, 0x3B, 0x1A38E4, 0x703 }, + [OLYMPUS_LUT_CHAN_538500_IDX] = { 21540, 0x1, 0x3B, 0x1AAAAB, 0x703 }, + [OLYMPUS_LUT_CHAN_538625_IDX] = { 21545, 0x1, 0x3B, 0x1B1C72, 0x703 }, + [OLYMPUS_LUT_CHAN_538750_IDX] = { 21550, 0x1, 0x3B, 0x1B8E39, 0x704 }, + [OLYMPUS_LUT_CHAN_538875_IDX] = { 21555, 0x1, 0x3B, 0x1C0000, 0x704 }, + [OLYMPUS_LUT_CHAN_539000_IDX] = { 21560, 0x1, 0x3B, 0x1C71C7, 0x705 }, + [OLYMPUS_LUT_CHAN_539125_IDX] = { 21565, 0x1, 0x3B, 0x1CE38E, 0x705 }, + [OLYMPUS_LUT_CHAN_539250_IDX] = { 21570, 0x1, 0x3B, 0x1D5555, 0x706 }, + [OLYMPUS_LUT_CHAN_539375_IDX] = { 21575, 0x1, 0x3B, 0x1DC71C, 0x706 }, + [OLYMPUS_LUT_CHAN_539500_IDX] = { 21580, 0x1, 0x3B, 0x1E38E4, 0x706 }, + [OLYMPUS_LUT_CHAN_539625_IDX] = { 21585, 0x1, 0x3B, 0x1EAAAB, 0x707 }, + [OLYMPUS_LUT_CHAN_539750_IDX] = { 21590, 0x1, 0x3B, 0x1F1C72, 0x707 }, + [OLYMPUS_LUT_CHAN_539875_IDX] = { 21595, 0x1, 0x3B, 0x1F8E39, 0x708 }, + [OLYMPUS_LUT_CHAN_540000_IDX] = { 21600, 0x1, 0x3C, 0x0, 0x708 }, + [OLYMPUS_LUT_CHAN_540125_IDX] = { 21605, 0x1, 0x3C, 0x71C7, 0x708 }, + [OLYMPUS_LUT_CHAN_540250_IDX] = { 21610, 0x1, 0x3C, 0xE38E, 0x709 }, + [OLYMPUS_LUT_CHAN_540375_IDX] = { 21615, 0x1, 0x3C, 0x15555, 0x709 }, + [OLYMPUS_LUT_CHAN_540500_IDX] = { 21620, 0x1, 0x3C, 0x1C71C, 0x70A }, + [OLYMPUS_LUT_CHAN_540625_IDX] = { 21625, 0x1, 0x3C, 0x238E4, 0x70A }, + [OLYMPUS_LUT_CHAN_540750_IDX] = { 21630, 0x1, 0x3C, 0x2AAAB, 0x70B }, + [OLYMPUS_LUT_CHAN_540875_IDX] = { 21635, 0x1, 0x3C, 0x31C72, 0x70B }, + [OLYMPUS_LUT_CHAN_541000_IDX] = { 21640, 0x1, 0x3C, 0x38E39, 0x70B }, + [OLYMPUS_LUT_CHAN_541125_IDX] = { 21645, 0x1, 0x3C, 0x40000, 0x70C }, + [OLYMPUS_LUT_CHAN_541250_IDX] = { 21650, 0x1, 0x3C, 0x471C7, 0x70C }, + [OLYMPUS_LUT_CHAN_541375_IDX] = { 21655, 0x1, 0x3C, 0x4E38E, 0x70D }, + [OLYMPUS_LUT_CHAN_541500_IDX] = { 21660, 0x1, 0x3C, 0x55555, 0x70D }, + [OLYMPUS_LUT_CHAN_541625_IDX] = { 21665, 0x1, 0x3C, 0x5C71C, 0x70D }, + [OLYMPUS_LUT_CHAN_541750_IDX] = { 21670, 0x1, 0x3C, 0x638E4, 0x70E }, + [OLYMPUS_LUT_CHAN_541875_IDX] = { 21675, 0x1, 0x3C, 0x6AAAB, 0x70E }, + [OLYMPUS_LUT_CHAN_542000_IDX] = { 21680, 0x1, 0x3C, 0x71C72, 0x70F }, + [OLYMPUS_LUT_CHAN_542125_IDX] = { 21685, 0x1, 0x3C, 0x78E39, 0x70F }, + [OLYMPUS_LUT_CHAN_542250_IDX] = { 21690, 0x1, 0x3C, 0x80000, 0x710 }, + [OLYMPUS_LUT_CHAN_542375_IDX] = { 21695, 0x1, 0x3C, 0x871C7, 0x710 }, + [OLYMPUS_LUT_CHAN_542500_IDX] = { 21700, 0x1, 0x3C, 0x8E38E, 0x710 }, + [OLYMPUS_LUT_CHAN_542625_IDX] = { 21705, 0x1, 0x3C, 0x95555, 0x711 }, + [OLYMPUS_LUT_CHAN_542750_IDX] = { 21710, 0x1, 0x3C, 0x9C71C, 0x711 }, + [OLYMPUS_LUT_CHAN_542875_IDX] = { 21715, 0x1, 0x3C, 0xA38E4, 0x712 }, + [OLYMPUS_LUT_CHAN_543000_IDX] = { 21720, 0x1, 0x3C, 0xAAAAB, 0x712 }, + [OLYMPUS_LUT_CHAN_543125_IDX] = { 21725, 0x1, 0x3C, 0xB1C72, 0x712 }, + [OLYMPUS_LUT_CHAN_543250_IDX] = { 21730, 0x1, 0x3C, 0xB8E39, 0x713 }, + [OLYMPUS_LUT_CHAN_543375_IDX] = { 21735, 0x1, 0x3C, 0xC0000, 0x713 }, + [OLYMPUS_LUT_CHAN_543500_IDX] = { 21740, 0x1, 0x3C, 0xC71C7, 0x714 }, + [OLYMPUS_LUT_CHAN_543625_IDX] = { 21745, 0x1, 0x3C, 0xCE38E, 0x714 }, + [OLYMPUS_LUT_CHAN_543750_IDX] = { 21750, 0x1, 0x3C, 0xD5555, 0x715 }, + [OLYMPUS_LUT_CHAN_543875_IDX] = { 21755, 0x1, 0x3C, 0xDC71C, 0x715 }, + [OLYMPUS_LUT_CHAN_544000_IDX] = { 21760, 0x1, 0x3C, 0xE38E4, 0x715 }, + [OLYMPUS_LUT_CHAN_544125_IDX] = { 21765, 0x1, 0x3C, 0xEAAAB, 0x716 }, + [OLYMPUS_LUT_CHAN_544250_IDX] = { 21770, 0x1, 0x3C, 0xF1C72, 0x716 }, + [OLYMPUS_LUT_CHAN_544375_IDX] = { 21775, 0x1, 0x3C, 0xF8E39, 0x717 }, + [OLYMPUS_LUT_CHAN_544500_IDX] = { 21780, 0x1, 0x3C, 0x100000, 0x717 }, + [OLYMPUS_LUT_CHAN_544625_IDX] = { 21785, 0x1, 0x3C, 0x1071C7, 0x717 }, + [OLYMPUS_LUT_CHAN_544750_IDX] = { 21790, 0x1, 0x3C, 0x10E38E, 0x718 }, + [OLYMPUS_LUT_CHAN_544875_IDX] = { 21795, 0x1, 0x3C, 0x115555, 0x718 }, + [OLYMPUS_LUT_CHAN_545000_IDX] = { 21800, 0x1, 0x3C, 0x11C71C, 0x719 }, + [OLYMPUS_LUT_CHAN_545125_IDX] = { 21805, 0x1, 0x3C, 0x1238E4, 0x719 }, + [OLYMPUS_LUT_CHAN_545250_IDX] = { 21810, 0x1, 0x3C, 0x12AAAB, 0x71A }, + [OLYMPUS_LUT_CHAN_545375_IDX] = { 21815, 0x1, 0x3C, 0x131C72, 0x71A }, + [OLYMPUS_LUT_CHAN_545500_IDX] = { 21820, 0x1, 0x3C, 0x138E39, 0x71A }, + [OLYMPUS_LUT_CHAN_545625_IDX] = { 21825, 0x1, 0x3C, 0x140000, 0x71B }, + [OLYMPUS_LUT_CHAN_545750_IDX] = { 21830, 0x1, 0x3C, 0x1471C7, 0x71B }, + [OLYMPUS_LUT_CHAN_545875_IDX] = { 21835, 0x1, 0x3C, 0x14E38E, 0x71C }, + [OLYMPUS_LUT_CHAN_546000_IDX] = { 21840, 0x1, 0x3C, 0x155555, 0x71C }, + [OLYMPUS_LUT_CHAN_546125_IDX] = { 21845, 0x1, 0x3C, 0x15C71C, 0x71C }, + [OLYMPUS_LUT_CHAN_546250_IDX] = { 21850, 0x1, 0x3C, 0x1638E4, 0x71D }, + [OLYMPUS_LUT_CHAN_546375_IDX] = { 21855, 0x1, 0x3C, 0x16AAAB, 0x71D }, + [OLYMPUS_LUT_CHAN_546500_IDX] = { 21860, 0x1, 0x3C, 0x171C72, 0x71E }, + [OLYMPUS_LUT_CHAN_546625_IDX] = { 21865, 0x1, 0x3C, 0x178E39, 0x71E }, + [OLYMPUS_LUT_CHAN_546750_IDX] = { 21870, 0x1, 0x3C, 0x180000, 0x71F }, + [OLYMPUS_LUT_CHAN_546875_IDX] = { 21875, 0x1, 0x3C, 0x1871C7, 0x71F }, + [OLYMPUS_LUT_CHAN_547000_IDX] = { 21880, 0x1, 0x3C, 0x18E38E, 0x71F }, + [OLYMPUS_LUT_CHAN_547125_IDX] = { 21885, 0x1, 0x3C, 0x195555, 0x720 }, + [OLYMPUS_LUT_CHAN_547250_IDX] = { 21890, 0x1, 0x3C, 0x19C71C, 0x720 }, + [OLYMPUS_LUT_CHAN_547375_IDX] = { 21895, 0x1, 0x3C, 0x1A38E4, 0x721 }, + [OLYMPUS_LUT_CHAN_547500_IDX] = { 21900, 0x1, 0x3C, 0x1AAAAB, 0x721 }, + [OLYMPUS_LUT_CHAN_547625_IDX] = { 21905, 0x1, 0x3C, 0x1B1C72, 0x721 }, + [OLYMPUS_LUT_CHAN_547750_IDX] = { 21910, 0x1, 0x3C, 0x1B8E39, 0x722 }, + [OLYMPUS_LUT_CHAN_547875_IDX] = { 21915, 0x1, 0x3C, 0x1C0000, 0x722 }, + [OLYMPUS_LUT_CHAN_548000_IDX] = { 21920, 0x1, 0x3C, 0x1C71C7, 0x723 }, + [OLYMPUS_LUT_CHAN_548125_IDX] = { 21925, 0x1, 0x3C, 0x1CE38E, 0x723 }, + [OLYMPUS_LUT_CHAN_548250_IDX] = { 21930, 0x1, 0x3C, 0x1D5555, 0x724 }, + [OLYMPUS_LUT_CHAN_548375_IDX] = { 21935, 0x1, 0x3C, 0x1DC71C, 0x724 }, + [OLYMPUS_LUT_CHAN_548500_IDX] = { 21940, 0x1, 0x3C, 0x1E38E4, 0x724 }, + [OLYMPUS_LUT_CHAN_548625_IDX] = { 21945, 0x1, 0x3C, 0x1EAAAB, 0x725 }, + [OLYMPUS_LUT_CHAN_548750_IDX] = { 21950, 0x1, 0x3C, 0x1F1C72, 0x725 }, + [OLYMPUS_LUT_CHAN_548875_IDX] = { 21955, 0x1, 0x3C, 0x1F8E39, 0x726 }, + [OLYMPUS_LUT_CHAN_549000_IDX] = { 21960, 0x1, 0x3D, 0x0, 0x726 }, + [OLYMPUS_LUT_CHAN_549125_IDX] = { 21965, 0x1, 0x3D, 0x71C7, 0x726 }, + [OLYMPUS_LUT_CHAN_549250_IDX] = { 21970, 0x1, 0x3D, 0xE38E, 0x727 }, + [OLYMPUS_LUT_CHAN_549375_IDX] = { 21975, 0x1, 0x3D, 0x15555, 0x727 }, + [OLYMPUS_LUT_CHAN_549500_IDX] = { 21980, 0x1, 0x3D, 0x1C71C, 0x728 }, + [OLYMPUS_LUT_CHAN_549625_IDX] = { 21985, 0x1, 0x3D, 0x238E4, 0x728 }, + [OLYMPUS_LUT_CHAN_549750_IDX] = { 21990, 0x1, 0x3D, 0x2AAAB, 0x729 }, + [OLYMPUS_LUT_CHAN_549875_IDX] = { 21995, 0x1, 0x3D, 0x31C72, 0x729 }, + [OLYMPUS_LUT_CHAN_550000_IDX] = { 22000, 0x1, 0x3D, 0x38E39, 0x729 }, + [OLYMPUS_LUT_CHAN_550125_IDX] = { 22005, 0x1, 0x3D, 0x40000, 0x72A }, + [OLYMPUS_LUT_CHAN_550250_IDX] = { 22010, 0x1, 0x3D, 0x471C7, 0x72A }, + [OLYMPUS_LUT_CHAN_550375_IDX] = { 22015, 0x1, 0x3D, 0x4E38E, 0x72B }, + [OLYMPUS_LUT_CHAN_550500_IDX] = { 22020, 0x1, 0x3D, 0x55555, 0x72B }, + [OLYMPUS_LUT_CHAN_550625_IDX] = { 22025, 0x1, 0x3D, 0x5C71C, 0x72B }, + [OLYMPUS_LUT_CHAN_550750_IDX] = { 22030, 0x1, 0x3D, 0x638E4, 0x72C }, + [OLYMPUS_LUT_CHAN_550875_IDX] = { 22035, 0x1, 0x3D, 0x6AAAB, 0x72C }, + [OLYMPUS_LUT_CHAN_551000_IDX] = { 22040, 0x1, 0x3D, 0x71C72, 0x72D }, + [OLYMPUS_LUT_CHAN_551125_IDX] = { 22045, 0x1, 0x3D, 0x78E39, 0x72D }, + [OLYMPUS_LUT_CHAN_551250_IDX] = { 22050, 0x1, 0x3D, 0x80000, 0x72E }, + [OLYMPUS_LUT_CHAN_551375_IDX] = { 22055, 0x1, 0x3D, 0x871C7, 0x72E }, + [OLYMPUS_LUT_CHAN_551500_IDX] = { 22060, 0x1, 0x3D, 0x8E38E, 0x72E }, + [OLYMPUS_LUT_CHAN_551625_IDX] = { 22065, 0x1, 0x3D, 0x95555, 0x72F }, + [OLYMPUS_LUT_CHAN_551750_IDX] = { 22070, 0x1, 0x3D, 0x9C71C, 0x72F }, + [OLYMPUS_LUT_CHAN_551875_IDX] = { 22075, 0x1, 0x3D, 0xA38E4, 0x730 }, + [OLYMPUS_LUT_CHAN_552000_IDX] = { 22080, 0x1, 0x3D, 0xAAAAB, 0x730 }, + [OLYMPUS_LUT_CHAN_552125_IDX] = { 22085, 0x1, 0x3D, 0xB1C72, 0x730 }, + [OLYMPUS_LUT_CHAN_552250_IDX] = { 22090, 0x1, 0x3D, 0xB8E39, 0x731 }, + [OLYMPUS_LUT_CHAN_552375_IDX] = { 22095, 0x1, 0x3D, 0xC0000, 0x731 }, + [OLYMPUS_LUT_CHAN_552500_IDX] = { 22100, 0x1, 0x3D, 0xC71C7, 0x732 }, + [OLYMPUS_LUT_CHAN_552625_IDX] = { 22105, 0x1, 0x3D, 0xCE38E, 0x732 }, + [OLYMPUS_LUT_CHAN_552750_IDX] = { 22110, 0x1, 0x3D, 0xD5555, 0x733 }, + [OLYMPUS_LUT_CHAN_552875_IDX] = { 22115, 0x1, 0x3D, 0xDC71C, 0x733 }, + [OLYMPUS_LUT_CHAN_553000_IDX] = { 22120, 0x1, 0x3D, 0xE38E4, 0x733 }, + [OLYMPUS_LUT_CHAN_553125_IDX] = { 22125, 0x1, 0x3D, 0xEAAAB, 0x734 }, + [OLYMPUS_LUT_CHAN_553250_IDX] = { 22130, 0x1, 0x3D, 0xF1C72, 0x734 }, + [OLYMPUS_LUT_CHAN_553375_IDX] = { 22135, 0x1, 0x3D, 0xF8E39, 0x735 }, + [OLYMPUS_LUT_CHAN_553500_IDX] = { 22140, 0x1, 0x3D, 0x100000, 0x735 }, + [OLYMPUS_LUT_CHAN_553625_IDX] = { 22145, 0x1, 0x3D, 0x1071C7, 0x735 }, + [OLYMPUS_LUT_CHAN_553750_IDX] = { 22150, 0x1, 0x3D, 0x10E38E, 0x736 }, + [OLYMPUS_LUT_CHAN_553875_IDX] = { 22155, 0x1, 0x3D, 0x115555, 0x736 }, + [OLYMPUS_LUT_CHAN_554000_IDX] = { 22160, 0x1, 0x3D, 0x11C71C, 0x737 }, + [OLYMPUS_LUT_CHAN_554125_IDX] = { 22165, 0x1, 0x3D, 0x1238E4, 0x737 }, + [OLYMPUS_LUT_CHAN_554250_IDX] = { 22170, 0x1, 0x3D, 0x12AAAB, 0x738 }, + [OLYMPUS_LUT_CHAN_554375_IDX] = { 22175, 0x1, 0x3D, 0x131C72, 0x738 }, + [OLYMPUS_LUT_CHAN_554500_IDX] = { 22180, 0x1, 0x3D, 0x138E39, 0x738 }, + [OLYMPUS_LUT_CHAN_554625_IDX] = { 22185, 0x1, 0x3D, 0x140000, 0x739 }, + [OLYMPUS_LUT_CHAN_554750_IDX] = { 22190, 0x1, 0x3D, 0x1471C7, 0x739 }, + [OLYMPUS_LUT_CHAN_554875_IDX] = { 22195, 0x1, 0x3D, 0x14E38E, 0x73A }, + [OLYMPUS_LUT_CHAN_555000_IDX] = { 22200, 0x1, 0x3D, 0x155555, 0x73A }, + [OLYMPUS_LUT_CHAN_555125_IDX] = { 22205, 0x1, 0x3D, 0x15C71C, 0x73A }, + [OLYMPUS_LUT_CHAN_555250_IDX] = { 22210, 0x1, 0x3D, 0x1638E4, 0x73B }, + [OLYMPUS_LUT_CHAN_555375_IDX] = { 22215, 0x1, 0x3D, 0x16AAAB, 0x73B }, + [OLYMPUS_LUT_CHAN_555500_IDX] = { 22220, 0x1, 0x3D, 0x171C72, 0x73C }, + [OLYMPUS_LUT_CHAN_555625_IDX] = { 22225, 0x1, 0x3D, 0x178E39, 0x73C }, + [OLYMPUS_LUT_CHAN_555750_IDX] = { 22230, 0x1, 0x3D, 0x180000, 0x73D }, + [OLYMPUS_LUT_CHAN_555875_IDX] = { 22235, 0x1, 0x3D, 0x1871C7, 0x73D }, + [OLYMPUS_LUT_CHAN_556000_IDX] = { 22240, 0x1, 0x3D, 0x18E38E, 0x73D }, + [OLYMPUS_LUT_CHAN_556125_IDX] = { 22245, 0x1, 0x3D, 0x195555, 0x73E }, + [OLYMPUS_LUT_CHAN_556250_IDX] = { 22250, 0x1, 0x3D, 0x19C71C, 0x73E }, + [OLYMPUS_LUT_CHAN_556375_IDX] = { 22255, 0x1, 0x3D, 0x1A38E4, 0x73F }, + [OLYMPUS_LUT_CHAN_556500_IDX] = { 22260, 0x1, 0x3D, 0x1AAAAB, 0x73F }, + [OLYMPUS_LUT_CHAN_556625_IDX] = { 22265, 0x1, 0x3D, 0x1B1C72, 0x73F }, + [OLYMPUS_LUT_CHAN_556750_IDX] = { 22270, 0x1, 0x3D, 0x1B8E39, 0x740 }, + [OLYMPUS_LUT_CHAN_556875_IDX] = { 22275, 0x1, 0x3D, 0x1C0000, 0x740 }, + [OLYMPUS_LUT_CHAN_557000_IDX] = { 22280, 0x1, 0x3D, 0x1C71C7, 0x741 }, + [OLYMPUS_LUT_CHAN_557125_IDX] = { 22285, 0x1, 0x3D, 0x1CE38E, 0x741 }, + [OLYMPUS_LUT_CHAN_557250_IDX] = { 22290, 0x1, 0x3D, 0x1D5555, 0x742 }, + [OLYMPUS_LUT_CHAN_557375_IDX] = { 22295, 0x1, 0x3D, 0x1DC71C, 0x742 }, + [OLYMPUS_LUT_CHAN_557500_IDX] = { 22300, 0x1, 0x3D, 0x1E38E4, 0x742 }, + [OLYMPUS_LUT_CHAN_557625_IDX] = { 22305, 0x1, 0x3D, 0x1EAAAB, 0x743 }, + [OLYMPUS_LUT_CHAN_557750_IDX] = { 22310, 0x1, 0x3D, 0x1F1C72, 0x743 }, + [OLYMPUS_LUT_CHAN_557875_IDX] = { 22315, 0x1, 0x3D, 0x1F8E39, 0x744 }, + [OLYMPUS_LUT_CHAN_558000_IDX] = { 22320, 0x1, 0x3E, 0x0, 0x744 }, + [OLYMPUS_LUT_CHAN_558125_IDX] = { 22325, 0x1, 0x3E, 0x71C7, 0x744 }, + [OLYMPUS_LUT_CHAN_558250_IDX] = { 22330, 0x1, 0x3E, 0xE38E, 0x745 }, + [OLYMPUS_LUT_CHAN_558375_IDX] = { 22335, 0x1, 0x3E, 0x15555, 0x745 }, + [OLYMPUS_LUT_CHAN_558500_IDX] = { 22340, 0x1, 0x3E, 0x1C71C, 0x746 }, + [OLYMPUS_LUT_CHAN_558625_IDX] = { 22345, 0x1, 0x3E, 0x238E4, 0x746 }, + [OLYMPUS_LUT_CHAN_558750_IDX] = { 22350, 0x1, 0x3E, 0x2AAAB, 0x747 }, + [OLYMPUS_LUT_CHAN_558875_IDX] = { 22355, 0x1, 0x3E, 0x31C72, 0x747 }, + [OLYMPUS_LUT_CHAN_559000_IDX] = { 22360, 0x1, 0x3E, 0x38E39, 0x747 }, + [OLYMPUS_LUT_CHAN_559125_IDX] = { 22365, 0x1, 0x3E, 0x40000, 0x748 }, + [OLYMPUS_LUT_CHAN_559250_IDX] = { 22370, 0x1, 0x3E, 0x471C7, 0x748 }, + [OLYMPUS_LUT_CHAN_559375_IDX] = { 22375, 0x1, 0x3E, 0x4E38E, 0x749 }, + [OLYMPUS_LUT_CHAN_559500_IDX] = { 22380, 0x1, 0x3E, 0x55555, 0x749 }, + [OLYMPUS_LUT_CHAN_559625_IDX] = { 22385, 0x1, 0x3E, 0x5C71C, 0x749 }, + [OLYMPUS_LUT_CHAN_559750_IDX] = { 22390, 0x1, 0x3E, 0x638E4, 0x74A }, + [OLYMPUS_LUT_CHAN_559875_IDX] = { 22395, 0x1, 0x3E, 0x6AAAB, 0x74A }, + [OLYMPUS_LUT_CHAN_560000_IDX] = { 22400, 0x1, 0x3E, 0x71C72, 0x74B }, + [OLYMPUS_LUT_CHAN_560125_IDX] = { 22405, 0x1, 0x3E, 0x78E39, 0x74B }, + [OLYMPUS_LUT_CHAN_560250_IDX] = { 22410, 0x1, 0x3E, 0x80000, 0x74C }, + [OLYMPUS_LUT_CHAN_560375_IDX] = { 22415, 0x1, 0x3E, 0x871C7, 0x74C }, + [OLYMPUS_LUT_CHAN_560500_IDX] = { 22420, 0x1, 0x3E, 0x8E38E, 0x74C }, + [OLYMPUS_LUT_CHAN_560625_IDX] = { 22425, 0x1, 0x3E, 0x95555, 0x74D }, + [OLYMPUS_LUT_CHAN_560750_IDX] = { 22430, 0x1, 0x3E, 0x9C71C, 0x74D }, + [OLYMPUS_LUT_CHAN_560875_IDX] = { 22435, 0x1, 0x3E, 0xA38E4, 0x74E }, + [OLYMPUS_LUT_CHAN_561000_IDX] = { 22440, 0x1, 0x3E, 0xAAAAB, 0x74E }, + [OLYMPUS_LUT_CHAN_561125_IDX] = { 22445, 0x1, 0x3E, 0xB1C72, 0x74E }, + [OLYMPUS_LUT_CHAN_561250_IDX] = { 22450, 0x1, 0x3E, 0xB8E39, 0x74F }, + [OLYMPUS_LUT_CHAN_561375_IDX] = { 22455, 0x1, 0x3E, 0xC0000, 0x74F }, + [OLYMPUS_LUT_CHAN_561500_IDX] = { 22460, 0x1, 0x3E, 0xC71C7, 0x750 }, + [OLYMPUS_LUT_CHAN_561625_IDX] = { 22465, 0x1, 0x3E, 0xCE38E, 0x750 }, + [OLYMPUS_LUT_CHAN_561750_IDX] = { 22470, 0x1, 0x3E, 0xD5555, 0x751 }, + [OLYMPUS_LUT_CHAN_561875_IDX] = { 22475, 0x1, 0x3E, 0xDC71C, 0x751 }, + [OLYMPUS_LUT_CHAN_562000_IDX] = { 22480, 0x1, 0x3E, 0xE38E4, 0x751 }, + [OLYMPUS_LUT_CHAN_562125_IDX] = { 22485, 0x1, 0x3E, 0xEAAAB, 0x752 }, + [OLYMPUS_LUT_CHAN_562250_IDX] = { 22490, 0x1, 0x3E, 0xF1C72, 0x752 }, + [OLYMPUS_LUT_CHAN_562375_IDX] = { 22495, 0x1, 0x3E, 0xF8E39, 0x753 }, + [OLYMPUS_LUT_CHAN_562500_IDX] = { 22500, 0x1, 0x3E, 0x100000, 0x753 }, + [OLYMPUS_LUT_CHAN_562625_IDX] = { 22505, 0x1, 0x3E, 0x1071C7, 0x753 }, + [OLYMPUS_LUT_CHAN_562750_IDX] = { 22510, 0x1, 0x3E, 0x10E38E, 0x754 }, + [OLYMPUS_LUT_CHAN_562875_IDX] = { 22515, 0x1, 0x3E, 0x115555, 0x754 }, + [OLYMPUS_LUT_CHAN_563000_IDX] = { 22520, 0x1, 0x3E, 0x11C71C, 0x755 }, + [OLYMPUS_LUT_CHAN_563125_IDX] = { 22525, 0x1, 0x3E, 0x1238E4, 0x755 }, + [OLYMPUS_LUT_CHAN_563250_IDX] = { 22530, 0x1, 0x3E, 0x12AAAB, 0x756 }, + [OLYMPUS_LUT_CHAN_563375_IDX] = { 22535, 0x1, 0x3E, 0x131C72, 0x756 }, + [OLYMPUS_LUT_CHAN_563500_IDX] = { 22540, 0x1, 0x3E, 0x138E39, 0x756 }, + [OLYMPUS_LUT_CHAN_563625_IDX] = { 22545, 0x1, 0x3E, 0x140000, 0x757 }, + [OLYMPUS_LUT_CHAN_563750_IDX] = { 22550, 0x1, 0x3E, 0x1471C7, 0x757 }, + [OLYMPUS_LUT_CHAN_563875_IDX] = { 22555, 0x1, 0x3E, 0x14E38E, 0x758 }, + [OLYMPUS_LUT_CHAN_564000_IDX] = { 22560, 0x1, 0x3E, 0x155555, 0x758 }, + [OLYMPUS_LUT_CHAN_564125_IDX] = { 22565, 0x1, 0x3E, 0x15C71C, 0x758 }, + [OLYMPUS_LUT_CHAN_564250_IDX] = { 22570, 0x1, 0x3E, 0x1638E4, 0x759 }, + [OLYMPUS_LUT_CHAN_564375_IDX] = { 22575, 0x1, 0x3E, 0x16AAAB, 0x759 }, + [OLYMPUS_LUT_CHAN_564500_IDX] = { 22580, 0x1, 0x3E, 0x171C72, 0x75A }, + [OLYMPUS_LUT_CHAN_564625_IDX] = { 22585, 0x1, 0x3E, 0x178E39, 0x75A }, + [OLYMPUS_LUT_CHAN_564750_IDX] = { 22590, 0x1, 0x3E, 0x180000, 0x75B }, + [OLYMPUS_LUT_CHAN_564875_IDX] = { 22595, 0x1, 0x3E, 0x1871C7, 0x75B }, + [OLYMPUS_LUT_CHAN_565000_IDX] = { 22600, 0x1, 0x3E, 0x18E38E, 0x75B }, + [OLYMPUS_LUT_CHAN_565125_IDX] = { 22605, 0x1, 0x3E, 0x195555, 0x75C }, + [OLYMPUS_LUT_CHAN_565250_IDX] = { 22610, 0x1, 0x3E, 0x19C71C, 0x75C }, + [OLYMPUS_LUT_CHAN_565375_IDX] = { 22615, 0x1, 0x3E, 0x1A38E4, 0x75D }, + [OLYMPUS_LUT_CHAN_565500_IDX] = { 22620, 0x1, 0x3E, 0x1AAAAB, 0x75D }, + [OLYMPUS_LUT_CHAN_565625_IDX] = { 22625, 0x1, 0x3E, 0x1B1C72, 0x75D }, + [OLYMPUS_LUT_CHAN_565750_IDX] = { 22630, 0x1, 0x3E, 0x1B8E39, 0x75E }, + [OLYMPUS_LUT_CHAN_565875_IDX] = { 22635, 0x1, 0x3E, 0x1C0000, 0x75E }, + [OLYMPUS_LUT_CHAN_566000_IDX] = { 22640, 0x1, 0x3E, 0x1C71C7, 0x75F }, + [OLYMPUS_LUT_CHAN_566125_IDX] = { 22645, 0x1, 0x3E, 0x1CE38E, 0x75F }, + [OLYMPUS_LUT_CHAN_566250_IDX] = { 22650, 0x1, 0x3E, 0x1D5555, 0x760 }, + [OLYMPUS_LUT_CHAN_566375_IDX] = { 22655, 0x1, 0x3E, 0x1DC71C, 0x760 }, + [OLYMPUS_LUT_CHAN_566500_IDX] = { 22660, 0x1, 0x3E, 0x1E38E4, 0x760 }, + [OLYMPUS_LUT_CHAN_566625_IDX] = { 22665, 0x1, 0x3E, 0x1EAAAB, 0x761 }, + [OLYMPUS_LUT_CHAN_566750_IDX] = { 22670, 0x1, 0x3E, 0x1F1C72, 0x761 }, + [OLYMPUS_LUT_CHAN_566875_IDX] = { 22675, 0x1, 0x3E, 0x1F8E39, 0x762 }, + [OLYMPUS_LUT_CHAN_567000_IDX] = { 22680, 0x1, 0x3F, 0x0, 0x762 }, + [OLYMPUS_LUT_CHAN_567125_IDX] = { 22685, 0x1, 0x3F, 0x71C7, 0x762 }, + [OLYMPUS_LUT_CHAN_567250_IDX] = { 22690, 0x1, 0x3F, 0xE38E, 0x763 }, + [OLYMPUS_LUT_CHAN_567375_IDX] = { 22695, 0x1, 0x3F, 0x15555, 0x763 }, + [OLYMPUS_LUT_CHAN_567500_IDX] = { 22700, 0x1, 0x3F, 0x1C71C, 0x764 }, + [OLYMPUS_LUT_CHAN_567625_IDX] = { 22705, 0x1, 0x3F, 0x238E4, 0x764 }, + [OLYMPUS_LUT_CHAN_567750_IDX] = { 22710, 0x1, 0x3F, 0x2AAAB, 0x765 }, + [OLYMPUS_LUT_CHAN_567875_IDX] = { 22715, 0x1, 0x3F, 0x31C72, 0x765 }, + [OLYMPUS_LUT_CHAN_568000_IDX] = { 22720, 0x1, 0x3F, 0x38E39, 0x765 }, + [OLYMPUS_LUT_CHAN_568125_IDX] = { 22725, 0x1, 0x3F, 0x40000, 0x766 }, + [OLYMPUS_LUT_CHAN_568250_IDX] = { 22730, 0x1, 0x3F, 0x471C7, 0x766 }, + [OLYMPUS_LUT_CHAN_568375_IDX] = { 22735, 0x1, 0x3F, 0x4E38E, 0x767 }, + [OLYMPUS_LUT_CHAN_568500_IDX] = { 22740, 0x1, 0x3F, 0x55555, 0x767 }, + [OLYMPUS_LUT_CHAN_568625_IDX] = { 22745, 0x1, 0x3F, 0x5C71C, 0x767 }, + [OLYMPUS_LUT_CHAN_568750_IDX] = { 22750, 0x1, 0x3F, 0x638E4, 0x768 }, + [OLYMPUS_LUT_CHAN_568875_IDX] = { 22755, 0x1, 0x3F, 0x6AAAB, 0x768 }, + [OLYMPUS_LUT_CHAN_569000_IDX] = { 22760, 0x1, 0x3F, 0x71C72, 0x769 }, + [OLYMPUS_LUT_CHAN_569125_IDX] = { 22765, 0x1, 0x3F, 0x78E39, 0x769 }, + [OLYMPUS_LUT_CHAN_569250_IDX] = { 22770, 0x1, 0x3F, 0x80000, 0x76A }, + [OLYMPUS_LUT_CHAN_569375_IDX] = { 22775, 0x1, 0x3F, 0x871C7, 0x76A }, + [OLYMPUS_LUT_CHAN_569500_IDX] = { 22780, 0x1, 0x3F, 0x8E38E, 0x76A }, + [OLYMPUS_LUT_CHAN_569625_IDX] = { 22785, 0x1, 0x3F, 0x95555, 0x76B }, + [OLYMPUS_LUT_CHAN_569750_IDX] = { 22790, 0x1, 0x3F, 0x9C71C, 0x76B }, + [OLYMPUS_LUT_CHAN_569875_IDX] = { 22795, 0x1, 0x3F, 0xA38E4, 0x76C }, + [OLYMPUS_LUT_CHAN_570000_IDX] = { 22800, 0x1, 0x3F, 0xAAAAB, 0x76C }, + [OLYMPUS_LUT_CHAN_570125_IDX] = { 22805, 0x1, 0x3F, 0xB1C72, 0x76C }, + [OLYMPUS_LUT_CHAN_570250_IDX] = { 22810, 0x1, 0x3F, 0xB8E39, 0x76D }, + [OLYMPUS_LUT_CHAN_570375_IDX] = { 22815, 0x1, 0x3F, 0xC0000, 0x76D }, + [OLYMPUS_LUT_CHAN_570500_IDX] = { 22820, 0x1, 0x3F, 0xC71C7, 0x76E }, + [OLYMPUS_LUT_CHAN_570625_IDX] = { 22825, 0x1, 0x3F, 0xCE38E, 0x76E }, + [OLYMPUS_LUT_CHAN_570750_IDX] = { 22830, 0x1, 0x3F, 0xD5555, 0x76F }, + [OLYMPUS_LUT_CHAN_570875_IDX] = { 22835, 0x1, 0x3F, 0xDC71C, 0x76F }, + [OLYMPUS_LUT_CHAN_571000_IDX] = { 22840, 0x1, 0x3F, 0xE38E4, 0x76F }, + [OLYMPUS_LUT_CHAN_571125_IDX] = { 22845, 0x1, 0x3F, 0xEAAAB, 0x770 }, + [OLYMPUS_LUT_CHAN_571250_IDX] = { 22850, 0x1, 0x3F, 0xF1C72, 0x770 }, + [OLYMPUS_LUT_CHAN_571375_IDX] = { 22855, 0x1, 0x3F, 0xF8E39, 0x771 }, + [OLYMPUS_LUT_CHAN_571500_IDX] = { 22860, 0x1, 0x3F, 0x100000, 0x771 }, + [OLYMPUS_LUT_CHAN_571625_IDX] = { 22865, 0x1, 0x3F, 0x1071C7, 0x771 }, + [OLYMPUS_LUT_CHAN_571750_IDX] = { 22870, 0x1, 0x3F, 0x10E38E, 0x772 }, + [OLYMPUS_LUT_CHAN_571875_IDX] = { 22875, 0x1, 0x3F, 0x115555, 0x772 }, + [OLYMPUS_LUT_CHAN_572000_IDX] = { 22880, 0x1, 0x3F, 0x11C71C, 0x773 }, + [OLYMPUS_LUT_CHAN_572125_IDX] = { 22885, 0x1, 0x3F, 0x1238E4, 0x773 }, + [OLYMPUS_LUT_CHAN_572250_IDX] = { 22890, 0x1, 0x3F, 0x12AAAB, 0x774 }, + [OLYMPUS_LUT_CHAN_572375_IDX] = { 22895, 0x1, 0x3F, 0x131C72, 0x774 }, + [OLYMPUS_LUT_CHAN_572500_IDX] = { 22900, 0x1, 0x3F, 0x138E39, 0x774 }, + [OLYMPUS_LUT_CHAN_572625_IDX] = { 22905, 0x1, 0x3F, 0x140000, 0x775 }, + [OLYMPUS_LUT_CHAN_572750_IDX] = { 22910, 0x1, 0x3F, 0x1471C7, 0x775 }, + [OLYMPUS_LUT_CHAN_572875_IDX] = { 22915, 0x1, 0x3F, 0x14E38E, 0x776 }, + [OLYMPUS_LUT_CHAN_573000_IDX] = { 22920, 0x1, 0x3F, 0x155555, 0x776 }, + [OLYMPUS_LUT_CHAN_573125_IDX] = { 22925, 0x1, 0x3F, 0x15C71C, 0x776 }, + [OLYMPUS_LUT_CHAN_573250_IDX] = { 22930, 0x1, 0x3F, 0x1638E4, 0x777 }, + [OLYMPUS_LUT_CHAN_573375_IDX] = { 22935, 0x1, 0x3F, 0x16AAAB, 0x777 }, + [OLYMPUS_LUT_CHAN_573500_IDX] = { 22940, 0x1, 0x3F, 0x171C72, 0x778 }, + [OLYMPUS_LUT_CHAN_573625_IDX] = { 22945, 0x1, 0x3F, 0x178E39, 0x778 }, + [OLYMPUS_LUT_CHAN_573750_IDX] = { 22950, 0x1, 0x3F, 0x180000, 0x779 }, + [OLYMPUS_LUT_CHAN_573875_IDX] = { 22955, 0x1, 0x3F, 0x1871C7, 0x779 }, + [OLYMPUS_LUT_CHAN_574000_IDX] = { 22960, 0x1, 0x3F, 0x18E38E, 0x779 }, + [OLYMPUS_LUT_CHAN_574125_IDX] = { 22965, 0x1, 0x3F, 0x195555, 0x77A }, + [OLYMPUS_LUT_CHAN_574250_IDX] = { 22970, 0x1, 0x3F, 0x19C71C, 0x77A }, + [OLYMPUS_LUT_CHAN_574375_IDX] = { 22975, 0x1, 0x3F, 0x1A38E4, 0x77B }, + [OLYMPUS_LUT_CHAN_574500_IDX] = { 22980, 0x1, 0x3F, 0x1AAAAB, 0x77B }, + [OLYMPUS_LUT_CHAN_574625_IDX] = { 22985, 0x1, 0x3F, 0x1B1C72, 0x77B }, + [OLYMPUS_LUT_CHAN_574750_IDX] = { 22990, 0x1, 0x3F, 0x1B8E39, 0x77C }, + [OLYMPUS_LUT_CHAN_574875_IDX] = { 22995, 0x1, 0x3F, 0x1C0000, 0x77C }, + [OLYMPUS_LUT_CHAN_575000_IDX] = { 23000, 0x1, 0x3F, 0x1C71C7, 0x77D }, + [OLYMPUS_LUT_CHAN_575125_IDX] = { 23005, 0x1, 0x3F, 0x1CE38E, 0x77D }, + [OLYMPUS_LUT_CHAN_575250_IDX] = { 23010, 0x1, 0x3F, 0x1D5555, 0x77E }, + [OLYMPUS_LUT_CHAN_575375_IDX] = { 23015, 0x1, 0x3F, 0x1DC71C, 0x77E }, + [OLYMPUS_LUT_CHAN_575500_IDX] = { 23020, 0x1, 0x3F, 0x1E38E4, 0x77E }, + [OLYMPUS_LUT_CHAN_575625_IDX] = { 23025, 0x1, 0x3F, 0x1EAAAB, 0x77F }, + [OLYMPUS_LUT_CHAN_575750_IDX] = { 23030, 0x1, 0x3F, 0x1F1C72, 0x77F }, + [OLYMPUS_LUT_CHAN_575875_IDX] = { 23035, 0x1, 0x3F, 0x1F8E39, 0x780 }, + [OLYMPUS_LUT_CHAN_576000_IDX] = { 23040, 0x1, 0x40, 0x0, 0x780 }, + [OLYMPUS_LUT_CHAN_576125_IDX] = { 23045, 0x1, 0x40, 0x71C7, 0x780 }, + [OLYMPUS_LUT_CHAN_576250_IDX] = { 23050, 0x1, 0x40, 0xE38E, 0x781 }, + [OLYMPUS_LUT_CHAN_576375_IDX] = { 23055, 0x1, 0x40, 0x15555, 0x781 }, + [OLYMPUS_LUT_CHAN_576500_IDX] = { 23060, 0x1, 0x40, 0x1C71C, 0x782 }, + [OLYMPUS_LUT_CHAN_576625_IDX] = { 23065, 0x1, 0x40, 0x238E4, 0x782 }, + [OLYMPUS_LUT_CHAN_576750_IDX] = { 23070, 0x1, 0x40, 0x2AAAB, 0x783 }, + [OLYMPUS_LUT_CHAN_576875_IDX] = { 23075, 0x1, 0x40, 0x31C72, 0x783 }, + [OLYMPUS_LUT_CHAN_577000_IDX] = { 23080, 0x1, 0x40, 0x38E39, 0x783 }, + [OLYMPUS_LUT_CHAN_577125_IDX] = { 23085, 0x1, 0x40, 0x40000, 0x784 }, + [OLYMPUS_LUT_CHAN_577250_IDX] = { 23090, 0x1, 0x40, 0x471C7, 0x784 }, + [OLYMPUS_LUT_CHAN_577375_IDX] = { 23095, 0x1, 0x40, 0x4E38E, 0x785 }, + [OLYMPUS_LUT_CHAN_577500_IDX] = { 23100, 0x1, 0x40, 0x55555, 0x785 }, + [OLYMPUS_LUT_CHAN_577625_IDX] = { 23105, 0x1, 0x40, 0x5C71C, 0x785 }, + [OLYMPUS_LUT_CHAN_577750_IDX] = { 23110, 0x1, 0x40, 0x638E4, 0x786 }, + [OLYMPUS_LUT_CHAN_577875_IDX] = { 23115, 0x1, 0x40, 0x6AAAB, 0x786 }, + [OLYMPUS_LUT_CHAN_578000_IDX] = { 23120, 0x1, 0x40, 0x71C72, 0x787 }, + [OLYMPUS_LUT_CHAN_578125_IDX] = { 23125, 0x1, 0x40, 0x78E39, 0x787 }, + [OLYMPUS_LUT_CHAN_578250_IDX] = { 23130, 0x1, 0x40, 0x80000, 0x788 }, + [OLYMPUS_LUT_CHAN_578375_IDX] = { 23135, 0x1, 0x40, 0x871C7, 0x788 }, + [OLYMPUS_LUT_CHAN_578500_IDX] = { 23140, 0x1, 0x40, 0x8E38E, 0x788 }, + [OLYMPUS_LUT_CHAN_578625_IDX] = { 23145, 0x1, 0x40, 0x95555, 0x789 }, + [OLYMPUS_LUT_CHAN_578750_IDX] = { 23150, 0x1, 0x40, 0x9C71C, 0x789 }, + [OLYMPUS_LUT_CHAN_578875_IDX] = { 23155, 0x1, 0x40, 0xA38E4, 0x78A }, + [OLYMPUS_LUT_CHAN_579000_IDX] = { 23160, 0x1, 0x40, 0xAAAAB, 0x78A }, + [OLYMPUS_LUT_CHAN_579125_IDX] = { 23165, 0x1, 0x40, 0xB1C72, 0x78A }, + [OLYMPUS_LUT_CHAN_579250_IDX] = { 23170, 0x1, 0x40, 0xB8E39, 0x78B }, + [OLYMPUS_LUT_CHAN_579375_IDX] = { 23175, 0x1, 0x40, 0xC0000, 0x78B }, + [OLYMPUS_LUT_CHAN_579500_IDX] = { 23180, 0x1, 0x40, 0xC71C7, 0x78C }, + [OLYMPUS_LUT_CHAN_579625_IDX] = { 23185, 0x1, 0x40, 0xCE38E, 0x78C }, + [OLYMPUS_LUT_CHAN_579750_IDX] = { 23190, 0x1, 0x40, 0xD5555, 0x78D }, + [OLYMPUS_LUT_CHAN_579875_IDX] = { 23195, 0x1, 0x40, 0xDC71C, 0x78D }, + [OLYMPUS_LUT_CHAN_580000_IDX] = { 23200, 0x1, 0x40, 0xE38E4, 0x78D }, + [OLYMPUS_LUT_CHAN_580125_IDX] = { 23205, 0x1, 0x40, 0xEAAAB, 0x78E }, + [OLYMPUS_LUT_CHAN_580250_IDX] = { 23210, 0x1, 0x40, 0xF1C72, 0x78E }, + [OLYMPUS_LUT_CHAN_580375_IDX] = { 23215, 0x1, 0x40, 0xF8E39, 0x78F }, + [OLYMPUS_LUT_CHAN_580500_IDX] = { 23220, 0x1, 0x40, 0x100000, 0x78F }, + [OLYMPUS_LUT_CHAN_580625_IDX] = { 23225, 0x1, 0x40, 0x1071C7, 0x78F }, + [OLYMPUS_LUT_CHAN_580750_IDX] = { 23230, 0x1, 0x40, 0x10E38E, 0x790 }, + [OLYMPUS_LUT_CHAN_580875_IDX] = { 23235, 0x1, 0x40, 0x115555, 0x790 }, + [OLYMPUS_LUT_CHAN_581000_IDX] = { 23240, 0x1, 0x40, 0x11C71C, 0x791 }, + [OLYMPUS_LUT_CHAN_581125_IDX] = { 23245, 0x1, 0x40, 0x1238E4, 0x791 }, + [OLYMPUS_LUT_CHAN_581250_IDX] = { 23250, 0x1, 0x40, 0x12AAAB, 0x792 }, + [OLYMPUS_LUT_CHAN_581375_IDX] = { 23255, 0x1, 0x40, 0x131C72, 0x792 }, + [OLYMPUS_LUT_CHAN_581500_IDX] = { 23260, 0x1, 0x40, 0x138E39, 0x792 }, + [OLYMPUS_LUT_CHAN_581625_IDX] = { 23265, 0x1, 0x40, 0x140000, 0x793 }, + [OLYMPUS_LUT_CHAN_581750_IDX] = { 23270, 0x1, 0x40, 0x1471C7, 0x793 }, + [OLYMPUS_LUT_CHAN_581875_IDX] = { 23275, 0x1, 0x40, 0x14E38E, 0x794 }, + [OLYMPUS_LUT_CHAN_582000_IDX] = { 23280, 0x1, 0x40, 0x155555, 0x794 }, + [OLYMPUS_LUT_CHAN_582125_IDX] = { 23285, 0x1, 0x40, 0x15C71C, 0x794 }, + [OLYMPUS_LUT_CHAN_582250_IDX] = { 23290, 0x1, 0x40, 0x1638E4, 0x795 }, + [OLYMPUS_LUT_CHAN_582375_IDX] = { 23295, 0x1, 0x40, 0x16AAAB, 0x795 }, + [OLYMPUS_LUT_CHAN_582500_IDX] = { 23300, 0x1, 0x40, 0x171C72, 0x796 }, + [OLYMPUS_LUT_CHAN_582625_IDX] = { 23305, 0x1, 0x40, 0x178E39, 0x796 }, + [OLYMPUS_LUT_CHAN_582750_IDX] = { 23310, 0x1, 0x40, 0x180000, 0x797 }, + [OLYMPUS_LUT_CHAN_582875_IDX] = { 23315, 0x1, 0x40, 0x1871C7, 0x797 }, + [OLYMPUS_LUT_CHAN_583000_IDX] = { 23320, 0x1, 0x40, 0x18E38E, 0x797 }, + [OLYMPUS_LUT_CHAN_583125_IDX] = { 23325, 0x1, 0x40, 0x195555, 0x798 }, + [OLYMPUS_LUT_CHAN_583250_IDX] = { 23330, 0x1, 0x40, 0x19C71C, 0x798 }, + [OLYMPUS_LUT_CHAN_583375_IDX] = { 23335, 0x1, 0x40, 0x1A38E4, 0x799 }, + [OLYMPUS_LUT_CHAN_583500_IDX] = { 23340, 0x1, 0x40, 0x1AAAAB, 0x799 }, + [OLYMPUS_LUT_CHAN_583625_IDX] = { 23345, 0x1, 0x40, 0x1B1C72, 0x799 }, + [OLYMPUS_LUT_CHAN_583750_IDX] = { 23350, 0x1, 0x40, 0x1B8E39, 0x79A }, + [OLYMPUS_LUT_CHAN_583875_IDX] = { 23355, 0x1, 0x40, 0x1C0000, 0x79A }, + [OLYMPUS_LUT_CHAN_584000_IDX] = { 23360, 0x1, 0x40, 0x1C71C7, 0x79B }, + [OLYMPUS_LUT_CHAN_584125_IDX] = { 23365, 0x1, 0x40, 0x1CE38E, 0x79B }, + [OLYMPUS_LUT_CHAN_584250_IDX] = { 23370, 0x1, 0x40, 0x1D5555, 0x79C }, + [OLYMPUS_LUT_CHAN_584375_IDX] = { 23375, 0x1, 0x40, 0x1DC71C, 0x79C }, + [OLYMPUS_LUT_CHAN_584500_IDX] = { 23380, 0x1, 0x40, 0x1E38E4, 0x79C }, + [OLYMPUS_LUT_CHAN_584625_IDX] = { 23385, 0x1, 0x40, 0x1EAAAB, 0x79D }, + [OLYMPUS_LUT_CHAN_584750_IDX] = { 23390, 0x1, 0x40, 0x1F1C72, 0x79D }, + [OLYMPUS_LUT_CHAN_584875_IDX] = { 23395, 0x1, 0x40, 0x1F8E39, 0x79E }, + [OLYMPUS_LUT_CHAN_585000_IDX] = { 23400, 0x1, 0x41, 0x0, 0x79E }, + [OLYMPUS_LUT_CHAN_585125_IDX] = { 23405, 0x1, 0x41, 0x71C7, 0x79E }, + [OLYMPUS_LUT_CHAN_585250_IDX] = { 23410, 0x1, 0x41, 0xE38E, 0x79F }, + [OLYMPUS_LUT_CHAN_585375_IDX] = { 23415, 0x1, 0x41, 0x15555, 0x79F }, + [OLYMPUS_LUT_CHAN_585500_IDX] = { 23420, 0x1, 0x41, 0x1C71C, 0x7A0 }, + [OLYMPUS_LUT_CHAN_585625_IDX] = { 23425, 0x1, 0x41, 0x238E4, 0x7A0 }, + [OLYMPUS_LUT_CHAN_585750_IDX] = { 23430, 0x1, 0x41, 0x2AAAB, 0x7A1 }, + [OLYMPUS_LUT_CHAN_585875_IDX] = { 23435, 0x1, 0x41, 0x31C72, 0x7A1 }, + [OLYMPUS_LUT_CHAN_586000_IDX] = { 23440, 0x1, 0x41, 0x38E39, 0x7A1 }, + [OLYMPUS_LUT_CHAN_586125_IDX] = { 23445, 0x1, 0x41, 0x40000, 0x7A2 }, + [OLYMPUS_LUT_CHAN_586250_IDX] = { 23450, 0x1, 0x41, 0x471C7, 0x7A2 }, + [OLYMPUS_LUT_CHAN_586375_IDX] = { 23455, 0x1, 0x41, 0x4E38E, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586500_IDX] = { 23460, 0x1, 0x41, 0x55555, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586625_IDX] = { 23465, 0x1, 0x41, 0x5C71C, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586750_IDX] = { 23470, 0x1, 0x41, 0x638E4, 0x7A4 }, + [OLYMPUS_LUT_CHAN_586875_IDX] = { 23475, 0x1, 0x41, 0x6AAAB, 0x7A4 }, + [OLYMPUS_LUT_CHAN_587000_IDX] = { 23480, 0x1, 0x41, 0x71C72, 0x7A5 }, + [OLYMPUS_LUT_CHAN_587125_IDX] = { 23485, 0x1, 0x41, 0x78E39, 0x7A5 }, + [OLYMPUS_LUT_CHAN_587250_IDX] = { 23490, 0x1, 0x41, 0x80000, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587375_IDX] = { 23495, 0x1, 0x41, 0x871C7, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587500_IDX] = { 23500, 0x1, 0x41, 0x8E38E, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587625_IDX] = { 23505, 0x1, 0x41, 0x95555, 0x7A7 }, + [OLYMPUS_LUT_CHAN_587750_IDX] = { 23510, 0x1, 0x41, 0x9C71C, 0x7A7 }, + [OLYMPUS_LUT_CHAN_587875_IDX] = { 23515, 0x1, 0x41, 0xA38E4, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588000_IDX] = { 23520, 0x1, 0x41, 0xAAAAB, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588125_IDX] = { 23525, 0x1, 0x41, 0xB1C72, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588250_IDX] = { 23530, 0x1, 0x41, 0xB8E39, 0x7A9 }, + [OLYMPUS_LUT_CHAN_588375_IDX] = { 23535, 0x1, 0x41, 0xC0000, 0x7A9 }, + [OLYMPUS_LUT_CHAN_588500_IDX] = { 23540, 0x1, 0x41, 0xC71C7, 0x7AA }, + [OLYMPUS_LUT_CHAN_588625_IDX] = { 23545, 0x1, 0x41, 0xCE38E, 0x7AA }, + [OLYMPUS_LUT_CHAN_588750_IDX] = { 23550, 0x1, 0x41, 0xD5555, 0x7AB }, + [OLYMPUS_LUT_CHAN_588875_IDX] = { 23555, 0x1, 0x41, 0xDC71C, 0x7AB }, + [OLYMPUS_LUT_CHAN_589000_IDX] = { 23560, 0x1, 0x41, 0xE38E4, 0x7AB }, + [OLYMPUS_LUT_CHAN_589125_IDX] = { 23565, 0x1, 0x41, 0xEAAAB, 0x7AC }, + [OLYMPUS_LUT_CHAN_589250_IDX] = { 23570, 0x1, 0x41, 0xF1C72, 0x7AC }, + [OLYMPUS_LUT_CHAN_589375_IDX] = { 23575, 0x1, 0x41, 0xF8E39, 0x7AD }, + [OLYMPUS_LUT_CHAN_589500_IDX] = { 23580, 0x1, 0x41, 0x100000, 0x7AD }, + [OLYMPUS_LUT_CHAN_589625_IDX] = { 23585, 0x1, 0x41, 0x1071C7, 0x7AD }, + [OLYMPUS_LUT_CHAN_589750_IDX] = { 23590, 0x1, 0x41, 0x10E38E, 0x7AE }, + [OLYMPUS_LUT_CHAN_589875_IDX] = { 23595, 0x1, 0x41, 0x115555, 0x7AE }, + [OLYMPUS_LUT_CHAN_590000_IDX] = { 23600, 0x1, 0x41, 0x11C71C, 0x7AF }, + [OLYMPUS_LUT_CHAN_590125_IDX] = { 23605, 0x1, 0x41, 0x1238E4, 0x7AF }, + [OLYMPUS_LUT_CHAN_590250_IDX] = { 23610, 0x1, 0x41, 0x12AAAB, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590375_IDX] = { 23615, 0x1, 0x41, 0x131C72, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590500_IDX] = { 23620, 0x1, 0x41, 0x138E39, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590625_IDX] = { 23625, 0x1, 0x41, 0x140000, 0x7B1 }, + [OLYMPUS_LUT_CHAN_590750_IDX] = { 23630, 0x1, 0x41, 0x1471C7, 0x7B1 }, + [OLYMPUS_LUT_CHAN_590875_IDX] = { 23635, 0x1, 0x41, 0x14E38E, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591000_IDX] = { 23640, 0x1, 0x41, 0x155555, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591125_IDX] = { 23645, 0x1, 0x41, 0x15C71C, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591250_IDX] = { 23650, 0x1, 0x41, 0x1638E4, 0x7B3 }, + [OLYMPUS_LUT_CHAN_591375_IDX] = { 23655, 0x1, 0x41, 0x16AAAB, 0x7B3 }, + [OLYMPUS_LUT_CHAN_591500_IDX] = { 23660, 0x1, 0x41, 0x171C72, 0x7B4 }, + [OLYMPUS_LUT_CHAN_591625_IDX] = { 23665, 0x1, 0x41, 0x178E39, 0x7B4 }, + [OLYMPUS_LUT_CHAN_591750_IDX] = { 23670, 0x1, 0x41, 0x180000, 0x7B5 }, + [OLYMPUS_LUT_CHAN_591875_IDX] = { 23675, 0x1, 0x41, 0x1871C7, 0x7B5 }, + [OLYMPUS_LUT_CHAN_592000_IDX] = { 23680, 0x1, 0x41, 0x18E38E, 0x7B5 }, + [OLYMPUS_LUT_CHAN_592125_IDX] = { 23685, 0x1, 0x41, 0x195555, 0x7B6 }, + [OLYMPUS_LUT_CHAN_592250_IDX] = { 23690, 0x1, 0x41, 0x19C71C, 0x7B6 }, + [OLYMPUS_LUT_CHAN_592375_IDX] = { 23695, 0x1, 0x41, 0x1A38E4, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592500_IDX] = { 23700, 0x1, 0x41, 0x1AAAAB, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592625_IDX] = { 23705, 0x1, 0x41, 0x1B1C72, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592750_IDX] = { 23710, 0x1, 0x41, 0x1B8E39, 0x7B8 }, + [OLYMPUS_LUT_CHAN_592875_IDX] = { 23715, 0x1, 0x41, 0x1C0000, 0x7B8 }, + [OLYMPUS_LUT_CHAN_593000_IDX] = { 23720, 0x1, 0x41, 0x1C71C7, 0x7B9 }, + [OLYMPUS_LUT_CHAN_593125_IDX] = { 23725, 0x1, 0x41, 0x1CE38E, 0x7B9 }, + [OLYMPUS_LUT_CHAN_593250_IDX] = { 23730, 0x1, 0x41, 0x1D5555, 0x7BA }, + [OLYMPUS_LUT_CHAN_593375_IDX] = { 23735, 0x1, 0x41, 0x1DC71C, 0x7BA }, + [OLYMPUS_LUT_CHAN_593500_IDX] = { 23740, 0x1, 0x41, 0x1E38E4, 0x7BA }, + [OLYMPUS_LUT_CHAN_593625_IDX] = { 23745, 0x1, 0x41, 0x1EAAAB, 0x7BB }, + [OLYMPUS_LUT_CHAN_593750_IDX] = { 23750, 0x1, 0x41, 0x1F1C72, 0x7BB }, + [OLYMPUS_LUT_CHAN_593875_IDX] = { 23755, 0x1, 0x41, 0x1F8E39, 0x7BC }, + [OLYMPUS_LUT_CHAN_594000_IDX] = { 23760, 0x1, 0x42, 0x0, 0x7BC }, + [OLYMPUS_LUT_CHAN_594125_IDX] = { 23765, 0x1, 0x42, 0x71C7, 0x7BC }, + [OLYMPUS_LUT_CHAN_594250_IDX] = { 23770, 0x1, 0x42, 0xE38E, 0x7BD }, + [OLYMPUS_LUT_CHAN_594375_IDX] = { 23775, 0x1, 0x42, 0x15555, 0x7BD }, + [OLYMPUS_LUT_CHAN_594500_IDX] = { 23780, 0x1, 0x42, 0x1C71C, 0x7BE }, + [OLYMPUS_LUT_CHAN_594625_IDX] = { 23785, 0x1, 0x42, 0x238E4, 0x7BE }, + [OLYMPUS_LUT_CHAN_594750_IDX] = { 23790, 0x1, 0x42, 0x2AAAB, 0x7BF }, + [OLYMPUS_LUT_CHAN_594875_IDX] = { 23795, 0x1, 0x42, 0x31C72, 0x7BF }, + [OLYMPUS_LUT_CHAN_595000_IDX] = { 23800, 0x1, 0x42, 0x38E39, 0x7BF } +}; + +const struct olympus_lut_line olympus_lut_24g_40_mhz[OLYMPUS_LUT_CHAN_24G_MAX] = { + [OLYMPUS_LUT_CHAN_240700_IDX] = { 9628, 0x0, 0x50, 0x77777, 0x645 }, + [OLYMPUS_LUT_CHAN_240825_IDX] = { 9633, 0x0, 0x50, 0x8CCCD, 0x646 }, + [OLYMPUS_LUT_CHAN_240950_IDX] = { 9638, 0x0, 0x50, 0xA2222, 0x646 }, + [OLYMPUS_LUT_CHAN_241075_IDX] = { 9643, 0x0, 0x50, 0xB7777, 0x647 }, + [OLYMPUS_LUT_CHAN_241200_IDX] = { 9648, 0x0, 0x50, 0xCCCCD, 0x648 }, + [OLYMPUS_LUT_CHAN_241325_IDX] = { 9653, 0x0, 0x50, 0xE2222, 0x649 }, + [OLYMPUS_LUT_CHAN_241450_IDX] = { 9658, 0x0, 0x50, 0xF7777, 0x64A }, + [OLYMPUS_LUT_CHAN_241575_IDX] = { 9663, 0x0, 0x50, 0x10CCCD, 0x64B }, + [OLYMPUS_LUT_CHAN_241700_IDX] = { 9668, 0x0, 0x50, 0x122222, 0x64B }, + [OLYMPUS_LUT_CHAN_241825_IDX] = { 9673, 0x0, 0x50, 0x137777, 0x64C }, + [OLYMPUS_LUT_CHAN_241950_IDX] = { 9678, 0x0, 0x50, 0x14CCCD, 0x64D }, + [OLYMPUS_LUT_CHAN_242075_IDX] = { 9683, 0x0, 0x50, 0x162222, 0x64E }, + [OLYMPUS_LUT_CHAN_242200_IDX] = { 9688, 0x0, 0x50, 0x177777, 0x64F }, + [OLYMPUS_LUT_CHAN_242325_IDX] = { 9693, 0x0, 0x50, 0x18CCCD, 0x650 }, + [OLYMPUS_LUT_CHAN_242450_IDX] = { 9698, 0x0, 0x50, 0x1A2222, 0x650 }, + [OLYMPUS_LUT_CHAN_242575_IDX] = { 9703, 0x0, 0x50, 0x1B7777, 0x651 }, + [OLYMPUS_LUT_CHAN_242700_IDX] = { 9708, 0x0, 0x50, 0x1CCCCD, 0x652 }, + [OLYMPUS_LUT_CHAN_242825_IDX] = { 9713, 0x0, 0x50, 0x1E2222, 0x653 }, + [OLYMPUS_LUT_CHAN_242950_IDX] = { 9718, 0x0, 0x50, 0x1F7777, 0x654 }, + [OLYMPUS_LUT_CHAN_243075_IDX] = { 9723, 0x0, 0x51, 0xCCCD, 0x655 }, + [OLYMPUS_LUT_CHAN_243200_IDX] = { 9728, 0x0, 0x51, 0x22222, 0x655 }, + [OLYMPUS_LUT_CHAN_243325_IDX] = { 9733, 0x0, 0x51, 0x37777, 0x656 }, + [OLYMPUS_LUT_CHAN_243450_IDX] = { 9738, 0x0, 0x51, 0x4CCCD, 0x657 }, + [OLYMPUS_LUT_CHAN_243575_IDX] = { 9743, 0x0, 0x51, 0x62222, 0x658 }, + [OLYMPUS_LUT_CHAN_243700_IDX] = { 9748, 0x0, 0x51, 0x77777, 0x659 }, + [OLYMPUS_LUT_CHAN_243825_IDX] = { 9753, 0x0, 0x51, 0x8CCCD, 0x65A }, + [OLYMPUS_LUT_CHAN_243950_IDX] = { 9758, 0x0, 0x51, 0xA2222, 0x65A }, + [OLYMPUS_LUT_CHAN_244075_IDX] = { 9763, 0x0, 0x51, 0xB7777, 0x65B }, + [OLYMPUS_LUT_CHAN_244200_IDX] = { 9768, 0x0, 0x51, 0xCCCCD, 0x65C }, + [OLYMPUS_LUT_CHAN_244325_IDX] = { 9773, 0x0, 0x51, 0xE2222, 0x65D }, + [OLYMPUS_LUT_CHAN_244450_IDX] = { 9778, 0x0, 0x51, 0xF7777, 0x65E }, + [OLYMPUS_LUT_CHAN_244575_IDX] = { 9783, 0x0, 0x51, 0x10CCCD, 0x65F }, + [OLYMPUS_LUT_CHAN_244700_IDX] = { 9788, 0x0, 0x51, 0x122222, 0x65F }, + [OLYMPUS_LUT_CHAN_244825_IDX] = { 9793, 0x0, 0x51, 0x137777, 0x660 }, + [OLYMPUS_LUT_CHAN_244950_IDX] = { 9798, 0x0, 0x51, 0x14CCCD, 0x661 }, + [OLYMPUS_LUT_CHAN_245075_IDX] = { 9803, 0x0, 0x51, 0x162222, 0x662 }, + [OLYMPUS_LUT_CHAN_245200_IDX] = { 9808, 0x0, 0x51, 0x177777, 0x663 }, + [OLYMPUS_LUT_CHAN_245325_IDX] = { 9813, 0x0, 0x51, 0x18CCCD, 0x664 }, + [OLYMPUS_LUT_CHAN_245450_IDX] = { 9818, 0x0, 0x51, 0x1A2222, 0x664 }, + [OLYMPUS_LUT_CHAN_245575_IDX] = { 9823, 0x0, 0x51, 0x1B7777, 0x665 }, + [OLYMPUS_LUT_CHAN_245700_IDX] = { 9828, 0x0, 0x51, 0x1CCCCD, 0x666 }, + [OLYMPUS_LUT_CHAN_245825_IDX] = { 9833, 0x0, 0x51, 0x1E2222, 0x667 }, + [OLYMPUS_LUT_CHAN_245950_IDX] = { 9838, 0x0, 0x51, 0x1F7777, 0x668 }, + [OLYMPUS_LUT_CHAN_246075_IDX] = { 9843, 0x0, 0x52, 0xCCCD, 0x669 }, + [OLYMPUS_LUT_CHAN_246200_IDX] = { 9848, 0x0, 0x52, 0x22222, 0x669 }, + [OLYMPUS_LUT_CHAN_246325_IDX] = { 9853, 0x0, 0x52, 0x37777, 0x66A }, + [OLYMPUS_LUT_CHAN_246450_IDX] = { 9858, 0x0, 0x52, 0x4CCCD, 0x66B }, + [OLYMPUS_LUT_CHAN_246575_IDX] = { 9863, 0x0, 0x52, 0x62222, 0x66C }, + [OLYMPUS_LUT_CHAN_246700_IDX] = { 9868, 0x0, 0x52, 0x77777, 0x66D }, + [OLYMPUS_LUT_CHAN_246825_IDX] = { 9873, 0x0, 0x52, 0x8CCCD, 0x66E }, + [OLYMPUS_LUT_CHAN_246950_IDX] = { 9878, 0x0, 0x52, 0xA2222, 0x66E }, + [OLYMPUS_LUT_CHAN_247075_IDX] = { 9883, 0x0, 0x52, 0xB7777, 0x66F }, + [OLYMPUS_LUT_CHAN_247200_IDX] = { 9888, 0x0, 0x52, 0xCCCCD, 0x670 }, + [OLYMPUS_LUT_CHAN_247325_IDX] = { 9893, 0x0, 0x52, 0xE2222, 0x671 }, + [OLYMPUS_LUT_CHAN_247450_IDX] = { 9898, 0x0, 0x52, 0xF7777, 0x672 }, + [OLYMPUS_LUT_CHAN_247575_IDX] = { 9903, 0x0, 0x52, 0x10CCCD, 0x673 }, + [OLYMPUS_LUT_CHAN_247700_IDX] = { 9908, 0x0, 0x52, 0x122222, 0x673 }, + [OLYMPUS_LUT_CHAN_247825_IDX] = { 9913, 0x0, 0x52, 0x137777, 0x674 }, + [OLYMPUS_LUT_CHAN_247950_IDX] = { 9918, 0x0, 0x52, 0x14CCCD, 0x675 }, + [OLYMPUS_LUT_CHAN_248075_IDX] = { 9923, 0x0, 0x52, 0x162222, 0x676 }, + [OLYMPUS_LUT_CHAN_248200_IDX] = { 9928, 0x0, 0x52, 0x177777, 0x677 }, + [OLYMPUS_LUT_CHAN_248325_IDX] = { 9933, 0x0, 0x52, 0x18CCCD, 0x678 }, + [OLYMPUS_LUT_CHAN_248450_IDX] = { 9938, 0x0, 0x52, 0x1A2222, 0x678 }, + [OLYMPUS_LUT_CHAN_248575_IDX] = { 9943, 0x0, 0x52, 0x1B7777, 0x679 }, + [OLYMPUS_LUT_CHAN_248700_IDX] = { 9948, 0x0, 0x52, 0x1CCCCD, 0x67A }, + [OLYMPUS_LUT_CHAN_248825_IDX] = { 9953, 0x0, 0x52, 0x1E2222, 0x67B }, + [OLYMPUS_LUT_CHAN_248950_IDX] = { 9958, 0x0, 0x52, 0x1F7777, 0x67C }, + [OLYMPUS_LUT_CHAN_249075_IDX] = { 9963, 0x0, 0x53, 0xCCCD, 0x67D }, + [OLYMPUS_LUT_CHAN_249200_IDX] = { 9968, 0x0, 0x53, 0x22222, 0x67D }, + [OLYMPUS_LUT_CHAN_249325_IDX] = { 9973, 0x0, 0x53, 0x37777, 0x67E }, + [OLYMPUS_LUT_CHAN_249450_IDX] = { 9978, 0x0, 0x53, 0x4CCCD, 0x67F }, + [OLYMPUS_LUT_CHAN_249575_IDX] = { 9983, 0x0, 0x53, 0x62222, 0x680 }, + [OLYMPUS_LUT_CHAN_249700_IDX] = { 9988, 0x0, 0x53, 0x77777, 0x681 }, + [OLYMPUS_LUT_CHAN_249825_IDX] = { 9993, 0x0, 0x53, 0x8CCCD, 0x682 }, + [OLYMPUS_LUT_CHAN_249950_IDX] = { 9998, 0x0, 0x53, 0xA2222, 0x682 }, + [OLYMPUS_LUT_CHAN_250075_IDX] = { 10003, 0x0, 0x53, 0xB7777, 0x683 } +}; + +const struct olympus_lut_line olympus_lut_24g_60_mhz_s0[OLYMPUS_LUT_CHAN_24G_MAX] = { + [OLYMPUS_LUT_CHAN_240700_IDX] = { 9628, 0x0, 0x6A, 0x1F49F5, 0x645 }, + [OLYMPUS_LUT_CHAN_240825_IDX] = { 9633, 0x0, 0x6B, 0x11111, 0x646 }, + [OLYMPUS_LUT_CHAN_240950_IDX] = { 9638, 0x0, 0x6B, 0x2D82E, 0x646 }, + [OLYMPUS_LUT_CHAN_241075_IDX] = { 9643, 0x0, 0x6B, 0x49F4A, 0x647 }, + [OLYMPUS_LUT_CHAN_241200_IDX] = { 9648, 0x0, 0x6B, 0x66666, 0x648 }, + [OLYMPUS_LUT_CHAN_241325_IDX] = { 9653, 0x0, 0x6B, 0x82D83, 0x649 }, + [OLYMPUS_LUT_CHAN_241450_IDX] = { 9658, 0x0, 0x6B, 0x9F49F, 0x64A }, + [OLYMPUS_LUT_CHAN_241575_IDX] = { 9663, 0x0, 0x6B, 0xBBBBC, 0x64B }, + [OLYMPUS_LUT_CHAN_241700_IDX] = { 9668, 0x0, 0x6B, 0xD82D8, 0x64B }, + [OLYMPUS_LUT_CHAN_241825_IDX] = { 9673, 0x0, 0x6B, 0xF49F5, 0x64C }, + [OLYMPUS_LUT_CHAN_241950_IDX] = { 9678, 0x0, 0x6B, 0x111111, 0x64D }, + [OLYMPUS_LUT_CHAN_242075_IDX] = { 9683, 0x0, 0x6B, 0x12D82E, 0x64E }, + [OLYMPUS_LUT_CHAN_242200_IDX] = { 9688, 0x0, 0x6B, 0x149F4A, 0x64F }, + [OLYMPUS_LUT_CHAN_242325_IDX] = { 9693, 0x0, 0x6B, 0x166666, 0x650 }, + [OLYMPUS_LUT_CHAN_242450_IDX] = { 9698, 0x0, 0x6B, 0x182D83, 0x650 }, + [OLYMPUS_LUT_CHAN_242575_IDX] = { 9703, 0x0, 0x6B, 0x19F49F, 0x651 }, + [OLYMPUS_LUT_CHAN_242700_IDX] = { 9708, 0x0, 0x6B, 0x1BBBBC, 0x652 }, + [OLYMPUS_LUT_CHAN_242825_IDX] = { 9713, 0x0, 0x6B, 0x1D82D8, 0x653 }, + [OLYMPUS_LUT_CHAN_242950_IDX] = { 9718, 0x0, 0x6B, 0x1F49F5, 0x654 }, + [OLYMPUS_LUT_CHAN_243075_IDX] = { 9723, 0x0, 0x6C, 0x11111, 0x655 }, + [OLYMPUS_LUT_CHAN_243200_IDX] = { 9728, 0x0, 0x6C, 0x2D82E, 0x655 }, + [OLYMPUS_LUT_CHAN_243325_IDX] = { 9733, 0x0, 0x6C, 0x49F4A, 0x656 }, + [OLYMPUS_LUT_CHAN_243450_IDX] = { 9738, 0x0, 0x6C, 0x66666, 0x657 }, + [OLYMPUS_LUT_CHAN_243575_IDX] = { 9743, 0x0, 0x6C, 0x82D83, 0x658 }, + [OLYMPUS_LUT_CHAN_243700_IDX] = { 9748, 0x0, 0x6C, 0x9F49F, 0x659 }, + [OLYMPUS_LUT_CHAN_243825_IDX] = { 9753, 0x0, 0x6C, 0xBBBBC, 0x65A }, + [OLYMPUS_LUT_CHAN_243950_IDX] = { 9758, 0x0, 0x6C, 0xD82D8, 0x65A }, + [OLYMPUS_LUT_CHAN_244075_IDX] = { 9763, 0x0, 0x6C, 0xF49F5, 0x65B }, + [OLYMPUS_LUT_CHAN_244200_IDX] = { 9768, 0x0, 0x6C, 0x111111, 0x65C }, + [OLYMPUS_LUT_CHAN_244325_IDX] = { 9773, 0x0, 0x6C, 0x12D82E, 0x65D }, + [OLYMPUS_LUT_CHAN_244450_IDX] = { 9778, 0x0, 0x6C, 0x149F4A, 0x65E }, + [OLYMPUS_LUT_CHAN_244575_IDX] = { 9783, 0x0, 0x6C, 0x166666, 0x65F }, + [OLYMPUS_LUT_CHAN_244700_IDX] = { 9788, 0x0, 0x6C, 0x182D83, 0x65F }, + [OLYMPUS_LUT_CHAN_244825_IDX] = { 9793, 0x0, 0x6C, 0x19F49F, 0x660 }, + [OLYMPUS_LUT_CHAN_244950_IDX] = { 9798, 0x0, 0x6C, 0x1BBBBC, 0x661 }, + [OLYMPUS_LUT_CHAN_245075_IDX] = { 9803, 0x0, 0x6C, 0x1D82D8, 0x662 }, + [OLYMPUS_LUT_CHAN_245200_IDX] = { 9808, 0x0, 0x6C, 0x1F49F5, 0x663 }, + [OLYMPUS_LUT_CHAN_245325_IDX] = { 9813, 0x0, 0x6D, 0x11111, 0x664 }, + [OLYMPUS_LUT_CHAN_245450_IDX] = { 9818, 0x0, 0x6D, 0x2D82E, 0x664 }, + [OLYMPUS_LUT_CHAN_245575_IDX] = { 9823, 0x0, 0x6D, 0x49F4A, 0x665 }, + [OLYMPUS_LUT_CHAN_245700_IDX] = { 9828, 0x0, 0x6D, 0x66666, 0x666 }, + [OLYMPUS_LUT_CHAN_245825_IDX] = { 9833, 0x0, 0x6D, 0x82D83, 0x667 }, + [OLYMPUS_LUT_CHAN_245950_IDX] = { 9838, 0x0, 0x6D, 0x9F49F, 0x668 }, + [OLYMPUS_LUT_CHAN_246075_IDX] = { 9843, 0x0, 0x6D, 0xBBBBC, 0x669 }, + [OLYMPUS_LUT_CHAN_246200_IDX] = { 9848, 0x0, 0x6D, 0xD82D8, 0x669 }, + [OLYMPUS_LUT_CHAN_246325_IDX] = { 9853, 0x0, 0x6D, 0xF49F5, 0x66A }, + [OLYMPUS_LUT_CHAN_246450_IDX] = { 9858, 0x0, 0x6D, 0x111111, 0x66B }, + [OLYMPUS_LUT_CHAN_246575_IDX] = { 9863, 0x0, 0x6D, 0x12D82E, 0x66C }, + [OLYMPUS_LUT_CHAN_246700_IDX] = { 9868, 0x0, 0x6D, 0x149F4A, 0x66D }, + [OLYMPUS_LUT_CHAN_246825_IDX] = { 9873, 0x0, 0x6D, 0x166666, 0x66E }, + [OLYMPUS_LUT_CHAN_246950_IDX] = { 9878, 0x0, 0x6D, 0x182D83, 0x66E }, + [OLYMPUS_LUT_CHAN_247075_IDX] = { 9883, 0x0, 0x6D, 0x19F49F, 0x66F }, + [OLYMPUS_LUT_CHAN_247200_IDX] = { 9888, 0x0, 0x6D, 0x1BBBBC, 0x670 }, + [OLYMPUS_LUT_CHAN_247325_IDX] = { 9893, 0x0, 0x6D, 0x1D82D8, 0x671 }, + [OLYMPUS_LUT_CHAN_247450_IDX] = { 9898, 0x0, 0x6D, 0x1F49F5, 0x672 }, + [OLYMPUS_LUT_CHAN_247575_IDX] = { 9903, 0x0, 0x6E, 0x11111, 0x673 }, + [OLYMPUS_LUT_CHAN_247700_IDX] = { 9908, 0x0, 0x6E, 0x2D82E, 0x673 }, + [OLYMPUS_LUT_CHAN_247825_IDX] = { 9913, 0x0, 0x6E, 0x49F4A, 0x674 }, + [OLYMPUS_LUT_CHAN_247950_IDX] = { 9918, 0x0, 0x6E, 0x66666, 0x675 }, + [OLYMPUS_LUT_CHAN_248075_IDX] = { 9923, 0x0, 0x6E, 0x82D83, 0x676 }, + [OLYMPUS_LUT_CHAN_248200_IDX] = { 9928, 0x0, 0x6E, 0x9F49F, 0x677 }, + [OLYMPUS_LUT_CHAN_248325_IDX] = { 9933, 0x0, 0x6E, 0xBBBBC, 0x678 }, + [OLYMPUS_LUT_CHAN_248450_IDX] = { 9938, 0x0, 0x6E, 0xD82D8, 0x678 }, + [OLYMPUS_LUT_CHAN_248575_IDX] = { 9943, 0x0, 0x6E, 0xF49F5, 0x679 }, + [OLYMPUS_LUT_CHAN_248700_IDX] = { 9948, 0x0, 0x6E, 0x111111, 0x67A }, + [OLYMPUS_LUT_CHAN_248825_IDX] = { 9953, 0x0, 0x6E, 0x12D82E, 0x67B }, + [OLYMPUS_LUT_CHAN_248950_IDX] = { 9958, 0x0, 0x6E, 0x149F4A, 0x67C }, + [OLYMPUS_LUT_CHAN_249075_IDX] = { 9963, 0x0, 0x6E, 0x166666, 0x67D }, + [OLYMPUS_LUT_CHAN_249200_IDX] = { 9968, 0x0, 0x6E, 0x182D83, 0x67D }, + [OLYMPUS_LUT_CHAN_249325_IDX] = { 9973, 0x0, 0x6E, 0x19F49F, 0x67E }, + [OLYMPUS_LUT_CHAN_249450_IDX] = { 9978, 0x0, 0x6E, 0x1BBBBC, 0x67F }, + [OLYMPUS_LUT_CHAN_249575_IDX] = { 9983, 0x0, 0x6E, 0x1D82D8, 0x680 }, + [OLYMPUS_LUT_CHAN_249700_IDX] = { 9988, 0x0, 0x6E, 0x1F49F5, 0x681 }, + [OLYMPUS_LUT_CHAN_249825_IDX] = { 9993, 0x0, 0x6F, 0x11111, 0x682 }, + [OLYMPUS_LUT_CHAN_249950_IDX] = { 9998, 0x0, 0x6F, 0x2D82E, 0x682 }, + [OLYMPUS_LUT_CHAN_250075_IDX] = { 10003, 0x0, 0x6F, 0x49F4A, 0x683 } +}; + +const struct olympus_lut_line olympus_lut_24g_60_mhz_s1[OLYMPUS_LUT_CHAN_24G_MAX] = { + [OLYMPUS_LUT_CHAN_240700_IDX] = { 9628, 0x0, 0x35, 0xFA4FA, 0x645 }, + [OLYMPUS_LUT_CHAN_240825_IDX] = { 9633, 0x0, 0x35, 0x108889, 0x646 }, + [OLYMPUS_LUT_CHAN_240950_IDX] = { 9638, 0x0, 0x35, 0x116C17, 0x646 }, + [OLYMPUS_LUT_CHAN_241075_IDX] = { 9643, 0x0, 0x35, 0x124FA5, 0x647 }, + [OLYMPUS_LUT_CHAN_241200_IDX] = { 9648, 0x0, 0x35, 0x133333, 0x648 }, + [OLYMPUS_LUT_CHAN_241325_IDX] = { 9653, 0x0, 0x35, 0x1416C1, 0x649 }, + [OLYMPUS_LUT_CHAN_241450_IDX] = { 9658, 0x0, 0x35, 0x14FA50, 0x64A }, + [OLYMPUS_LUT_CHAN_241575_IDX] = { 9663, 0x0, 0x35, 0x15DDDE, 0x64B }, + [OLYMPUS_LUT_CHAN_241700_IDX] = { 9668, 0x0, 0x35, 0x16C16C, 0x64B }, + [OLYMPUS_LUT_CHAN_241825_IDX] = { 9673, 0x0, 0x35, 0x17A4FA, 0x64C }, + [OLYMPUS_LUT_CHAN_241950_IDX] = { 9678, 0x0, 0x35, 0x188889, 0x64D }, + [OLYMPUS_LUT_CHAN_242075_IDX] = { 9683, 0x0, 0x35, 0x196C17, 0x64E }, + [OLYMPUS_LUT_CHAN_242200_IDX] = { 9688, 0x0, 0x35, 0x1A4FA5, 0x64F }, + [OLYMPUS_LUT_CHAN_242325_IDX] = { 9693, 0x0, 0x35, 0x1B3333, 0x650 }, + [OLYMPUS_LUT_CHAN_242450_IDX] = { 9698, 0x0, 0x35, 0x1C16C1, 0x650 }, + [OLYMPUS_LUT_CHAN_242575_IDX] = { 9703, 0x0, 0x35, 0x1CFA50, 0x651 }, + [OLYMPUS_LUT_CHAN_242700_IDX] = { 9708, 0x0, 0x35, 0x1DDDDE, 0x652 }, + [OLYMPUS_LUT_CHAN_242825_IDX] = { 9713, 0x0, 0x35, 0x1EC16C, 0x653 }, + [OLYMPUS_LUT_CHAN_242950_IDX] = { 9718, 0x0, 0x35, 0x1FA4FA, 0x654 }, + [OLYMPUS_LUT_CHAN_243075_IDX] = { 9723, 0x0, 0x36, 0x8889, 0x655 }, + [OLYMPUS_LUT_CHAN_243200_IDX] = { 9728, 0x0, 0x36, 0x16C17, 0x655 }, + [OLYMPUS_LUT_CHAN_243325_IDX] = { 9733, 0x0, 0x36, 0x24FA5, 0x656 }, + [OLYMPUS_LUT_CHAN_243450_IDX] = { 9738, 0x0, 0x36, 0x33333, 0x657 }, + [OLYMPUS_LUT_CHAN_243575_IDX] = { 9743, 0x0, 0x36, 0x416C1, 0x658 }, + [OLYMPUS_LUT_CHAN_243700_IDX] = { 9748, 0x0, 0x36, 0x4FA50, 0x659 }, + [OLYMPUS_LUT_CHAN_243825_IDX] = { 9753, 0x0, 0x36, 0x5DDDE, 0x65A }, + [OLYMPUS_LUT_CHAN_243950_IDX] = { 9758, 0x0, 0x36, 0x6C16C, 0x65A }, + [OLYMPUS_LUT_CHAN_244075_IDX] = { 9763, 0x0, 0x36, 0x7A4FA, 0x65B }, + [OLYMPUS_LUT_CHAN_244200_IDX] = { 9768, 0x0, 0x36, 0x88889, 0x65C }, + [OLYMPUS_LUT_CHAN_244325_IDX] = { 9773, 0x0, 0x36, 0x96C17, 0x65D }, + [OLYMPUS_LUT_CHAN_244450_IDX] = { 9778, 0x0, 0x36, 0xA4FA5, 0x65E }, + [OLYMPUS_LUT_CHAN_244575_IDX] = { 9783, 0x0, 0x36, 0xB3333, 0x65F }, + [OLYMPUS_LUT_CHAN_244700_IDX] = { 9788, 0x0, 0x36, 0xC16C1, 0x65F }, + [OLYMPUS_LUT_CHAN_244825_IDX] = { 9793, 0x0, 0x36, 0xCFA50, 0x660 }, + [OLYMPUS_LUT_CHAN_244950_IDX] = { 9798, 0x0, 0x36, 0xDDDDE, 0x661 }, + [OLYMPUS_LUT_CHAN_245075_IDX] = { 9803, 0x0, 0x36, 0xEC16C, 0x662 }, + [OLYMPUS_LUT_CHAN_245200_IDX] = { 9808, 0x0, 0x36, 0xFA4FA, 0x663 }, + [OLYMPUS_LUT_CHAN_245325_IDX] = { 9813, 0x0, 0x36, 0x108889, 0x664 }, + [OLYMPUS_LUT_CHAN_245450_IDX] = { 9818, 0x0, 0x36, 0x116C17, 0x664 }, + [OLYMPUS_LUT_CHAN_245575_IDX] = { 9823, 0x0, 0x36, 0x124FA5, 0x665 }, + [OLYMPUS_LUT_CHAN_245700_IDX] = { 9828, 0x0, 0x36, 0x133333, 0x666 }, + [OLYMPUS_LUT_CHAN_245825_IDX] = { 9833, 0x0, 0x36, 0x1416C1, 0x667 }, + [OLYMPUS_LUT_CHAN_245950_IDX] = { 9838, 0x0, 0x36, 0x14FA50, 0x668 }, + [OLYMPUS_LUT_CHAN_246075_IDX] = { 9843, 0x0, 0x36, 0x15DDDE, 0x669 }, + [OLYMPUS_LUT_CHAN_246200_IDX] = { 9848, 0x0, 0x36, 0x16C16C, 0x669 }, + [OLYMPUS_LUT_CHAN_246325_IDX] = { 9853, 0x0, 0x36, 0x17A4FA, 0x66A }, + [OLYMPUS_LUT_CHAN_246450_IDX] = { 9858, 0x0, 0x36, 0x188889, 0x66B }, + [OLYMPUS_LUT_CHAN_246575_IDX] = { 9863, 0x0, 0x36, 0x196C17, 0x66C }, + [OLYMPUS_LUT_CHAN_246700_IDX] = { 9868, 0x0, 0x36, 0x1A4FA5, 0x66D }, + [OLYMPUS_LUT_CHAN_246825_IDX] = { 9873, 0x0, 0x36, 0x1B3333, 0x66E }, + [OLYMPUS_LUT_CHAN_246950_IDX] = { 9878, 0x0, 0x36, 0x1C16C1, 0x66E }, + [OLYMPUS_LUT_CHAN_247075_IDX] = { 9883, 0x0, 0x36, 0x1CFA50, 0x66F }, + [OLYMPUS_LUT_CHAN_247200_IDX] = { 9888, 0x0, 0x36, 0x1DDDDE, 0x670 }, + [OLYMPUS_LUT_CHAN_247325_IDX] = { 9893, 0x0, 0x36, 0x1EC16C, 0x671 }, + [OLYMPUS_LUT_CHAN_247450_IDX] = { 9898, 0x0, 0x36, 0x1FA4FA, 0x672 }, + [OLYMPUS_LUT_CHAN_247575_IDX] = { 9903, 0x0, 0x37, 0x8889, 0x673 }, + [OLYMPUS_LUT_CHAN_247700_IDX] = { 9908, 0x0, 0x37, 0x16C17, 0x673 }, + [OLYMPUS_LUT_CHAN_247825_IDX] = { 9913, 0x0, 0x37, 0x24FA5, 0x674 }, + [OLYMPUS_LUT_CHAN_247950_IDX] = { 9918, 0x0, 0x37, 0x33333, 0x675 }, + [OLYMPUS_LUT_CHAN_248075_IDX] = { 9923, 0x0, 0x37, 0x416C1, 0x676 }, + [OLYMPUS_LUT_CHAN_248200_IDX] = { 9928, 0x0, 0x37, 0x4FA50, 0x677 }, + [OLYMPUS_LUT_CHAN_248325_IDX] = { 9933, 0x0, 0x37, 0x5DDDE, 0x678 }, + [OLYMPUS_LUT_CHAN_248450_IDX] = { 9938, 0x0, 0x37, 0x6C16C, 0x678 }, + [OLYMPUS_LUT_CHAN_248575_IDX] = { 9943, 0x0, 0x37, 0x7A4FA, 0x679 }, + [OLYMPUS_LUT_CHAN_248700_IDX] = { 9948, 0x0, 0x37, 0x88889, 0x67A }, + [OLYMPUS_LUT_CHAN_248825_IDX] = { 9953, 0x0, 0x37, 0x96C17, 0x67B }, + [OLYMPUS_LUT_CHAN_248950_IDX] = { 9958, 0x0, 0x37, 0xA4FA5, 0x67C }, + [OLYMPUS_LUT_CHAN_249075_IDX] = { 9963, 0x0, 0x37, 0xB3333, 0x67D }, + [OLYMPUS_LUT_CHAN_249200_IDX] = { 9968, 0x0, 0x37, 0xC16C1, 0x67D }, + [OLYMPUS_LUT_CHAN_249325_IDX] = { 9973, 0x0, 0x37, 0xCFA50, 0x67E }, + [OLYMPUS_LUT_CHAN_249450_IDX] = { 9978, 0x0, 0x37, 0xDDDDE, 0x67F }, + [OLYMPUS_LUT_CHAN_249575_IDX] = { 9983, 0x0, 0x37, 0xEC16C, 0x680 }, + [OLYMPUS_LUT_CHAN_249700_IDX] = { 9988, 0x0, 0x37, 0xFA4FA, 0x681 }, + [OLYMPUS_LUT_CHAN_249825_IDX] = { 9993, 0x0, 0x37, 0x108889, 0x682 }, + [OLYMPUS_LUT_CHAN_249950_IDX] = { 9998, 0x0, 0x37, 0x116C17, 0x682 }, + [OLYMPUS_LUT_CHAN_250075_IDX] = { 10003, 0x0, 0x37, 0x124FA5, 0x683 } +}; + +const struct olympus_lut_line olympus_lut_5g_60_mhz_s0[OLYMPUS_LUT_CHAN_5G_MAX] = { + [OLYMPUS_LUT_CHAN_516000_IDX] = { 20640, 0x0, 0x73, 0x38E39, 0x6BF }, + [OLYMPUS_LUT_CHAN_516125_IDX] = { 20645, 0x0, 0x72, 0x1638E4, 0x6B8 }, + [OLYMPUS_LUT_CHAN_516250_IDX] = { 20650, 0x0, 0x72, 0x171C72, 0x6B9 }, + [OLYMPUS_LUT_CHAN_516375_IDX] = { 20655, 0x0, 0x72, 0x180000, 0x6B9 }, + [OLYMPUS_LUT_CHAN_516500_IDX] = { 20660, 0x0, 0x72, 0x18E38E, 0x6BA }, + [OLYMPUS_LUT_CHAN_516625_IDX] = { 20665, 0x0, 0x72, 0x19C71C, 0x6BA }, + [OLYMPUS_LUT_CHAN_516750_IDX] = { 20670, 0x0, 0x72, 0x1AAAAB, 0x6BB }, + [OLYMPUS_LUT_CHAN_516875_IDX] = { 20675, 0x0, 0x72, 0x1B8E39, 0x6BB }, + [OLYMPUS_LUT_CHAN_517000_IDX] = { 20680, 0x0, 0x72, 0x1C71C7, 0x6BB }, + [OLYMPUS_LUT_CHAN_517125_IDX] = { 20685, 0x0, 0x72, 0x1D5555, 0x6BC }, + [OLYMPUS_LUT_CHAN_517250_IDX] = { 20690, 0x0, 0x72, 0x1E38E4, 0x6BC }, + [OLYMPUS_LUT_CHAN_517375_IDX] = { 20695, 0x0, 0x72, 0x1F1C72, 0x6BD }, + [OLYMPUS_LUT_CHAN_517500_IDX] = { 20700, 0x0, 0x73, 0x0, 0x6BD }, + [OLYMPUS_LUT_CHAN_517625_IDX] = { 20705, 0x0, 0x73, 0xE38E, 0x6BD }, + [OLYMPUS_LUT_CHAN_517750_IDX] = { 20710, 0x0, 0x73, 0x1C71C, 0x6BE }, + [OLYMPUS_LUT_CHAN_517875_IDX] = { 20715, 0x0, 0x73, 0x2AAAB, 0x6BE }, + [OLYMPUS_LUT_CHAN_518000_IDX] = { 20720, 0x0, 0x73, 0x38E39, 0x6BF }, + [OLYMPUS_LUT_CHAN_518125_IDX] = { 20725, 0x0, 0x73, 0x471C7, 0x6BF }, + [OLYMPUS_LUT_CHAN_518250_IDX] = { 20730, 0x0, 0x73, 0x55555, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518375_IDX] = { 20735, 0x0, 0x73, 0x638E4, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518500_IDX] = { 20740, 0x0, 0x73, 0x71C72, 0x6C0 }, + [OLYMPUS_LUT_CHAN_518625_IDX] = { 20745, 0x0, 0x73, 0x80000, 0x6C1 }, + [OLYMPUS_LUT_CHAN_518750_IDX] = { 20750, 0x0, 0x73, 0x8E38E, 0x6C1 }, + [OLYMPUS_LUT_CHAN_518875_IDX] = { 20755, 0x0, 0x73, 0x9C71C, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519000_IDX] = { 20760, 0x0, 0x73, 0xAAAAB, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519125_IDX] = { 20765, 0x0, 0x73, 0xB8E39, 0x6C2 }, + [OLYMPUS_LUT_CHAN_519250_IDX] = { 20770, 0x0, 0x73, 0xC71C7, 0x6C3 }, + [OLYMPUS_LUT_CHAN_519375_IDX] = { 20775, 0x0, 0x73, 0xD5555, 0x6C3 }, + [OLYMPUS_LUT_CHAN_519500_IDX] = { 20780, 0x0, 0x73, 0xE38E4, 0x6C4 }, + [OLYMPUS_LUT_CHAN_519625_IDX] = { 20785, 0x0, 0x73, 0xF1C72, 0x6C4 }, + [OLYMPUS_LUT_CHAN_519750_IDX] = { 20790, 0x0, 0x73, 0x100000, 0x6C5 }, + [OLYMPUS_LUT_CHAN_519875_IDX] = { 20795, 0x0, 0x73, 0x10E38E, 0x6C5 }, + [OLYMPUS_LUT_CHAN_520000_IDX] = { 20800, 0x1, 0x73, 0x11C71C, 0x6C5 }, + [OLYMPUS_LUT_CHAN_520125_IDX] = { 20805, 0x1, 0x73, 0x12AAAB, 0x6C6 }, + [OLYMPUS_LUT_CHAN_520250_IDX] = { 20810, 0x1, 0x73, 0x138E39, 0x6C6 }, + [OLYMPUS_LUT_CHAN_520375_IDX] = { 20815, 0x1, 0x73, 0x1471C7, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520500_IDX] = { 20820, 0x1, 0x73, 0x155555, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520625_IDX] = { 20825, 0x1, 0x73, 0x1638E4, 0x6C7 }, + [OLYMPUS_LUT_CHAN_520750_IDX] = { 20830, 0x1, 0x73, 0x171C72, 0x6C8 }, + [OLYMPUS_LUT_CHAN_520875_IDX] = { 20835, 0x1, 0x73, 0x180000, 0x6C8 }, + [OLYMPUS_LUT_CHAN_521000_IDX] = { 20840, 0x1, 0x73, 0x18E38E, 0x6C9 }, + [OLYMPUS_LUT_CHAN_521125_IDX] = { 20845, 0x1, 0x73, 0x19C71C, 0x6C9 }, + [OLYMPUS_LUT_CHAN_521250_IDX] = { 20850, 0x1, 0x73, 0x1AAAAB, 0x6CA }, + [OLYMPUS_LUT_CHAN_521375_IDX] = { 20855, 0x1, 0x73, 0x1B8E39, 0x6CA }, + [OLYMPUS_LUT_CHAN_521500_IDX] = { 20860, 0x1, 0x73, 0x1C71C7, 0x6CA }, + [OLYMPUS_LUT_CHAN_521625_IDX] = { 20865, 0x1, 0x73, 0x1D5555, 0x6CB }, + [OLYMPUS_LUT_CHAN_521750_IDX] = { 20870, 0x1, 0x73, 0x1E38E4, 0x6CB }, + [OLYMPUS_LUT_CHAN_521875_IDX] = { 20875, 0x1, 0x73, 0x1F1C72, 0x6CC }, + [OLYMPUS_LUT_CHAN_522000_IDX] = { 20880, 0x1, 0x74, 0x0, 0x6CC }, + [OLYMPUS_LUT_CHAN_522125_IDX] = { 20885, 0x1, 0x74, 0xE38E, 0x6CC }, + [OLYMPUS_LUT_CHAN_522250_IDX] = { 20890, 0x1, 0x74, 0x1C71C, 0x6CD }, + [OLYMPUS_LUT_CHAN_522375_IDX] = { 20895, 0x1, 0x74, 0x2AAAB, 0x6CD }, + [OLYMPUS_LUT_CHAN_522500_IDX] = { 20900, 0x1, 0x74, 0x38E39, 0x6CE }, + [OLYMPUS_LUT_CHAN_522625_IDX] = { 20905, 0x1, 0x74, 0x471C7, 0x6CE }, + [OLYMPUS_LUT_CHAN_522750_IDX] = { 20910, 0x1, 0x74, 0x55555, 0x6CF }, + [OLYMPUS_LUT_CHAN_522875_IDX] = { 20915, 0x1, 0x74, 0x638E4, 0x6CF }, + [OLYMPUS_LUT_CHAN_523000_IDX] = { 20920, 0x1, 0x74, 0x71C72, 0x6CF }, + [OLYMPUS_LUT_CHAN_523125_IDX] = { 20925, 0x1, 0x74, 0x80000, 0x6D0 }, + [OLYMPUS_LUT_CHAN_523250_IDX] = { 20930, 0x1, 0x74, 0x8E38E, 0x6D0 }, + [OLYMPUS_LUT_CHAN_523375_IDX] = { 20935, 0x1, 0x74, 0x9C71C, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523500_IDX] = { 20940, 0x1, 0x74, 0xAAAAB, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523625_IDX] = { 20945, 0x1, 0x74, 0xB8E39, 0x6D1 }, + [OLYMPUS_LUT_CHAN_523750_IDX] = { 20950, 0x1, 0x74, 0xC71C7, 0x6D2 }, + [OLYMPUS_LUT_CHAN_523875_IDX] = { 20955, 0x1, 0x74, 0xD5555, 0x6D2 }, + [OLYMPUS_LUT_CHAN_524000_IDX] = { 20960, 0x1, 0x74, 0xE38E4, 0x6D3 }, + [OLYMPUS_LUT_CHAN_524125_IDX] = { 20965, 0x1, 0x74, 0xF1C72, 0x6D3 }, + [OLYMPUS_LUT_CHAN_524250_IDX] = { 20970, 0x1, 0x74, 0x100000, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524375_IDX] = { 20975, 0x1, 0x74, 0x10E38E, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524500_IDX] = { 20980, 0x1, 0x74, 0x11C71C, 0x6D4 }, + [OLYMPUS_LUT_CHAN_524625_IDX] = { 20985, 0x1, 0x74, 0x12AAAB, 0x6D5 }, + [OLYMPUS_LUT_CHAN_524750_IDX] = { 20990, 0x1, 0x74, 0x138E39, 0x6D5 }, + [OLYMPUS_LUT_CHAN_524875_IDX] = { 20995, 0x1, 0x74, 0x1471C7, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525000_IDX] = { 21000, 0x1, 0x74, 0x155555, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525125_IDX] = { 21005, 0x1, 0x74, 0x1638E4, 0x6D6 }, + [OLYMPUS_LUT_CHAN_525250_IDX] = { 21010, 0x1, 0x74, 0x171C72, 0x6D7 }, + [OLYMPUS_LUT_CHAN_525375_IDX] = { 21015, 0x1, 0x74, 0x180000, 0x6D7 }, + [OLYMPUS_LUT_CHAN_525500_IDX] = { 21020, 0x1, 0x74, 0x18E38E, 0x6D8 }, + [OLYMPUS_LUT_CHAN_525625_IDX] = { 21025, 0x1, 0x74, 0x19C71C, 0x6D8 }, + [OLYMPUS_LUT_CHAN_525750_IDX] = { 21030, 0x1, 0x74, 0x1AAAAB, 0x6D9 }, + [OLYMPUS_LUT_CHAN_525875_IDX] = { 21035, 0x1, 0x74, 0x1B8E39, 0x6D9 }, + [OLYMPUS_LUT_CHAN_526000_IDX] = { 21040, 0x1, 0x74, 0x1C71C7, 0x6D9 }, + [OLYMPUS_LUT_CHAN_526125_IDX] = { 21045, 0x1, 0x74, 0x1D5555, 0x6DA }, + [OLYMPUS_LUT_CHAN_526250_IDX] = { 21050, 0x1, 0x74, 0x1E38E4, 0x6DA }, + [OLYMPUS_LUT_CHAN_526375_IDX] = { 21055, 0x1, 0x74, 0x1F1C72, 0x6DB }, + [OLYMPUS_LUT_CHAN_526500_IDX] = { 21060, 0x1, 0x75, 0x0, 0x6DB }, + [OLYMPUS_LUT_CHAN_526625_IDX] = { 21065, 0x1, 0x75, 0xE38E, 0x6DB }, + [OLYMPUS_LUT_CHAN_526750_IDX] = { 21070, 0x1, 0x75, 0x1C71C, 0x6DC }, + [OLYMPUS_LUT_CHAN_526875_IDX] = { 21075, 0x1, 0x75, 0x2AAAB, 0x6DC }, + [OLYMPUS_LUT_CHAN_527000_IDX] = { 21080, 0x1, 0x75, 0x38E39, 0x6DD }, + [OLYMPUS_LUT_CHAN_527125_IDX] = { 21085, 0x1, 0x75, 0x471C7, 0x6DD }, + [OLYMPUS_LUT_CHAN_527250_IDX] = { 21090, 0x1, 0x75, 0x55555, 0x6DE }, + [OLYMPUS_LUT_CHAN_527375_IDX] = { 21095, 0x1, 0x75, 0x638E4, 0x6DE }, + [OLYMPUS_LUT_CHAN_527500_IDX] = { 21100, 0x1, 0x75, 0x71C72, 0x6DE }, + [OLYMPUS_LUT_CHAN_527625_IDX] = { 21105, 0x1, 0x75, 0x80000, 0x6DF }, + [OLYMPUS_LUT_CHAN_527750_IDX] = { 21110, 0x1, 0x75, 0x8E38E, 0x6DF }, + [OLYMPUS_LUT_CHAN_527875_IDX] = { 21115, 0x1, 0x75, 0x9C71C, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528000_IDX] = { 21120, 0x1, 0x75, 0xAAAAB, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528125_IDX] = { 21125, 0x1, 0x75, 0xB8E39, 0x6E0 }, + [OLYMPUS_LUT_CHAN_528250_IDX] = { 21130, 0x1, 0x75, 0xC71C7, 0x6E1 }, + [OLYMPUS_LUT_CHAN_528375_IDX] = { 21135, 0x1, 0x75, 0xD5555, 0x6E1 }, + [OLYMPUS_LUT_CHAN_528500_IDX] = { 21140, 0x1, 0x75, 0xE38E4, 0x6E2 }, + [OLYMPUS_LUT_CHAN_528625_IDX] = { 21145, 0x1, 0x75, 0xF1C72, 0x6E2 }, + [OLYMPUS_LUT_CHAN_528750_IDX] = { 21150, 0x1, 0x75, 0x100000, 0x6E3 }, + [OLYMPUS_LUT_CHAN_528875_IDX] = { 21155, 0x1, 0x75, 0x10E38E, 0x6E3 }, + [OLYMPUS_LUT_CHAN_529000_IDX] = { 21160, 0x1, 0x75, 0x11C71C, 0x6E3 }, + [OLYMPUS_LUT_CHAN_529125_IDX] = { 21165, 0x1, 0x75, 0x12AAAB, 0x6E4 }, + [OLYMPUS_LUT_CHAN_529250_IDX] = { 21170, 0x1, 0x75, 0x138E39, 0x6E4 }, + [OLYMPUS_LUT_CHAN_529375_IDX] = { 21175, 0x1, 0x75, 0x1471C7, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529500_IDX] = { 21180, 0x1, 0x75, 0x155555, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529625_IDX] = { 21185, 0x1, 0x75, 0x1638E4, 0x6E5 }, + [OLYMPUS_LUT_CHAN_529750_IDX] = { 21190, 0x1, 0x75, 0x171C72, 0x6E6 }, + [OLYMPUS_LUT_CHAN_529875_IDX] = { 21195, 0x1, 0x75, 0x180000, 0x6E6 }, + [OLYMPUS_LUT_CHAN_530000_IDX] = { 21200, 0x1, 0x75, 0x18E38E, 0x6E7 }, + [OLYMPUS_LUT_CHAN_530125_IDX] = { 21205, 0x1, 0x75, 0x19C71C, 0x6E7 }, + [OLYMPUS_LUT_CHAN_530250_IDX] = { 21210, 0x1, 0x75, 0x1AAAAB, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530375_IDX] = { 21215, 0x1, 0x75, 0x1B8E39, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530500_IDX] = { 21220, 0x1, 0x75, 0x1C71C7, 0x6E8 }, + [OLYMPUS_LUT_CHAN_530625_IDX] = { 21225, 0x1, 0x75, 0x1D5555, 0x6E9 }, + [OLYMPUS_LUT_CHAN_530750_IDX] = { 21230, 0x1, 0x75, 0x1E38E4, 0x6E9 }, + [OLYMPUS_LUT_CHAN_530875_IDX] = { 21235, 0x1, 0x75, 0x1F1C72, 0x6EA }, + [OLYMPUS_LUT_CHAN_531000_IDX] = { 21240, 0x1, 0x76, 0x0, 0x6EA }, + [OLYMPUS_LUT_CHAN_531125_IDX] = { 21245, 0x1, 0x76, 0xE38E, 0x6EA }, + [OLYMPUS_LUT_CHAN_531250_IDX] = { 21250, 0x1, 0x76, 0x1C71C, 0x6EB }, + [OLYMPUS_LUT_CHAN_531375_IDX] = { 21255, 0x1, 0x76, 0x2AAAB, 0x6EB }, + [OLYMPUS_LUT_CHAN_531500_IDX] = { 21260, 0x1, 0x76, 0x38E39, 0x6EC }, + [OLYMPUS_LUT_CHAN_531625_IDX] = { 21265, 0x1, 0x76, 0x471C7, 0x6EC }, + [OLYMPUS_LUT_CHAN_531750_IDX] = { 21270, 0x1, 0x76, 0x55555, 0x6ED }, + [OLYMPUS_LUT_CHAN_531875_IDX] = { 21275, 0x1, 0x76, 0x638E4, 0x6ED }, + [OLYMPUS_LUT_CHAN_532000_IDX] = { 21280, 0x1, 0x76, 0x71C72, 0x6ED }, + [OLYMPUS_LUT_CHAN_532125_IDX] = { 21285, 0x1, 0x76, 0x80000, 0x6EE }, + [OLYMPUS_LUT_CHAN_532250_IDX] = { 21290, 0x1, 0x76, 0x8E38E, 0x6EE }, + [OLYMPUS_LUT_CHAN_532375_IDX] = { 21295, 0x1, 0x76, 0x9C71C, 0x6EF }, + [OLYMPUS_LUT_CHAN_532500_IDX] = { 21300, 0x1, 0x76, 0xAAAAB, 0x6EF }, + [OLYMPUS_LUT_CHAN_532625_IDX] = { 21305, 0x1, 0x76, 0xB8E39, 0x6EF }, + [OLYMPUS_LUT_CHAN_532750_IDX] = { 21310, 0x1, 0x76, 0xC71C7, 0x6F0 }, + [OLYMPUS_LUT_CHAN_532875_IDX] = { 21315, 0x1, 0x76, 0xD5555, 0x6F0 }, + [OLYMPUS_LUT_CHAN_533000_IDX] = { 21320, 0x1, 0x76, 0xE38E4, 0x6F1 }, + [OLYMPUS_LUT_CHAN_533125_IDX] = { 21325, 0x1, 0x76, 0xF1C72, 0x6F1 }, + [OLYMPUS_LUT_CHAN_533250_IDX] = { 21330, 0x1, 0x76, 0x100000, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533375_IDX] = { 21335, 0x1, 0x76, 0x10E38E, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533500_IDX] = { 21340, 0x1, 0x76, 0x11C71C, 0x6F2 }, + [OLYMPUS_LUT_CHAN_533625_IDX] = { 21345, 0x1, 0x76, 0x12AAAB, 0x6F3 }, + [OLYMPUS_LUT_CHAN_533750_IDX] = { 21350, 0x1, 0x76, 0x138E39, 0x6F3 }, + [OLYMPUS_LUT_CHAN_533875_IDX] = { 21355, 0x1, 0x76, 0x1471C7, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534000_IDX] = { 21360, 0x1, 0x76, 0x155555, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534125_IDX] = { 21365, 0x1, 0x76, 0x1638E4, 0x6F4 }, + [OLYMPUS_LUT_CHAN_534250_IDX] = { 21370, 0x1, 0x76, 0x171C72, 0x6F5 }, + [OLYMPUS_LUT_CHAN_534375_IDX] = { 21375, 0x1, 0x76, 0x180000, 0x6F5 }, + [OLYMPUS_LUT_CHAN_534500_IDX] = { 21380, 0x1, 0x76, 0x18E38E, 0x6F6 }, + [OLYMPUS_LUT_CHAN_534625_IDX] = { 21385, 0x1, 0x76, 0x19C71C, 0x6F6 }, + [OLYMPUS_LUT_CHAN_534750_IDX] = { 21390, 0x1, 0x76, 0x1AAAAB, 0x6F7 }, + [OLYMPUS_LUT_CHAN_534875_IDX] = { 21395, 0x1, 0x76, 0x1B8E39, 0x6F7 }, + [OLYMPUS_LUT_CHAN_535000_IDX] = { 21400, 0x1, 0x76, 0x1C71C7, 0x6F7 }, + [OLYMPUS_LUT_CHAN_535125_IDX] = { 21405, 0x1, 0x76, 0x1D5555, 0x6F8 }, + [OLYMPUS_LUT_CHAN_535250_IDX] = { 21410, 0x1, 0x76, 0x1E38E4, 0x6F8 }, + [OLYMPUS_LUT_CHAN_535375_IDX] = { 21415, 0x1, 0x76, 0x1F1C72, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535500_IDX] = { 21420, 0x1, 0x77, 0x0, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535625_IDX] = { 21425, 0x1, 0x77, 0xE38E, 0x6F9 }, + [OLYMPUS_LUT_CHAN_535750_IDX] = { 21430, 0x1, 0x77, 0x1C71C, 0x6FA }, + [OLYMPUS_LUT_CHAN_535875_IDX] = { 21435, 0x1, 0x77, 0x2AAAB, 0x6FA }, + [OLYMPUS_LUT_CHAN_536000_IDX] = { 21440, 0x1, 0x77, 0x38E39, 0x6FB }, + [OLYMPUS_LUT_CHAN_536125_IDX] = { 21445, 0x1, 0x77, 0x471C7, 0x6FB }, + [OLYMPUS_LUT_CHAN_536250_IDX] = { 21450, 0x1, 0x77, 0x55555, 0x6FC }, + [OLYMPUS_LUT_CHAN_536375_IDX] = { 21455, 0x1, 0x77, 0x638E4, 0x6FC }, + [OLYMPUS_LUT_CHAN_536500_IDX] = { 21460, 0x1, 0x77, 0x71C72, 0x6FC }, + [OLYMPUS_LUT_CHAN_536625_IDX] = { 21465, 0x1, 0x77, 0x80000, 0x6FD }, + [OLYMPUS_LUT_CHAN_536750_IDX] = { 21470, 0x1, 0x77, 0x8E38E, 0x6FD }, + [OLYMPUS_LUT_CHAN_536875_IDX] = { 21475, 0x1, 0x77, 0x9C71C, 0x6FE }, + [OLYMPUS_LUT_CHAN_537000_IDX] = { 21480, 0x1, 0x77, 0xAAAAB, 0x6FE }, + [OLYMPUS_LUT_CHAN_537125_IDX] = { 21485, 0x1, 0x77, 0xB8E39, 0x6FE }, + [OLYMPUS_LUT_CHAN_537250_IDX] = { 21490, 0x1, 0x77, 0xC71C7, 0x6FF }, + [OLYMPUS_LUT_CHAN_537375_IDX] = { 21495, 0x1, 0x77, 0xD5555, 0x6FF }, + [OLYMPUS_LUT_CHAN_537500_IDX] = { 21500, 0x1, 0x77, 0xE38E4, 0x700 }, + [OLYMPUS_LUT_CHAN_537625_IDX] = { 21505, 0x1, 0x77, 0xF1C72, 0x700 }, + [OLYMPUS_LUT_CHAN_537750_IDX] = { 21510, 0x1, 0x77, 0x100000, 0x701 }, + [OLYMPUS_LUT_CHAN_537875_IDX] = { 21515, 0x1, 0x77, 0x10E38E, 0x701 }, + [OLYMPUS_LUT_CHAN_538000_IDX] = { 21520, 0x1, 0x77, 0x11C71C, 0x701 }, + [OLYMPUS_LUT_CHAN_538125_IDX] = { 21525, 0x1, 0x77, 0x12AAAB, 0x702 }, + [OLYMPUS_LUT_CHAN_538250_IDX] = { 21530, 0x1, 0x77, 0x138E39, 0x702 }, + [OLYMPUS_LUT_CHAN_538375_IDX] = { 21535, 0x1, 0x77, 0x1471C7, 0x703 }, + [OLYMPUS_LUT_CHAN_538500_IDX] = { 21540, 0x1, 0x77, 0x155555, 0x703 }, + [OLYMPUS_LUT_CHAN_538625_IDX] = { 21545, 0x1, 0x77, 0x1638E4, 0x703 }, + [OLYMPUS_LUT_CHAN_538750_IDX] = { 21550, 0x1, 0x77, 0x171C72, 0x704 }, + [OLYMPUS_LUT_CHAN_538875_IDX] = { 21555, 0x1, 0x77, 0x180000, 0x704 }, + [OLYMPUS_LUT_CHAN_539000_IDX] = { 21560, 0x1, 0x77, 0x18E38E, 0x705 }, + [OLYMPUS_LUT_CHAN_539125_IDX] = { 21565, 0x1, 0x77, 0x19C71C, 0x705 }, + [OLYMPUS_LUT_CHAN_539250_IDX] = { 21570, 0x1, 0x77, 0x1AAAAB, 0x706 }, + [OLYMPUS_LUT_CHAN_539375_IDX] = { 21575, 0x1, 0x77, 0x1B8E39, 0x706 }, + [OLYMPUS_LUT_CHAN_539500_IDX] = { 21580, 0x1, 0x77, 0x1C71C7, 0x706 }, + [OLYMPUS_LUT_CHAN_539625_IDX] = { 21585, 0x1, 0x77, 0x1D5555, 0x707 }, + [OLYMPUS_LUT_CHAN_539750_IDX] = { 21590, 0x1, 0x77, 0x1E38E4, 0x707 }, + [OLYMPUS_LUT_CHAN_539875_IDX] = { 21595, 0x1, 0x77, 0x1F1C72, 0x708 }, + [OLYMPUS_LUT_CHAN_540000_IDX] = { 21600, 0x1, 0x78, 0x0, 0x708 }, + [OLYMPUS_LUT_CHAN_540125_IDX] = { 21605, 0x1, 0x78, 0xE38E, 0x708 }, + [OLYMPUS_LUT_CHAN_540250_IDX] = { 21610, 0x1, 0x78, 0x1C71C, 0x709 }, + [OLYMPUS_LUT_CHAN_540375_IDX] = { 21615, 0x1, 0x78, 0x2AAAB, 0x709 }, + [OLYMPUS_LUT_CHAN_540500_IDX] = { 21620, 0x1, 0x78, 0x38E39, 0x70A }, + [OLYMPUS_LUT_CHAN_540625_IDX] = { 21625, 0x1, 0x78, 0x471C7, 0x70A }, + [OLYMPUS_LUT_CHAN_540750_IDX] = { 21630, 0x1, 0x78, 0x55555, 0x70B }, + [OLYMPUS_LUT_CHAN_540875_IDX] = { 21635, 0x1, 0x78, 0x638E4, 0x70B }, + [OLYMPUS_LUT_CHAN_541000_IDX] = { 21640, 0x1, 0x78, 0x71C72, 0x70B }, + [OLYMPUS_LUT_CHAN_541125_IDX] = { 21645, 0x1, 0x78, 0x80000, 0x70C }, + [OLYMPUS_LUT_CHAN_541250_IDX] = { 21650, 0x1, 0x78, 0x8E38E, 0x70C }, + [OLYMPUS_LUT_CHAN_541375_IDX] = { 21655, 0x1, 0x78, 0x9C71C, 0x70D }, + [OLYMPUS_LUT_CHAN_541500_IDX] = { 21660, 0x1, 0x78, 0xAAAAB, 0x70D }, + [OLYMPUS_LUT_CHAN_541625_IDX] = { 21665, 0x1, 0x78, 0xB8E39, 0x70D }, + [OLYMPUS_LUT_CHAN_541750_IDX] = { 21670, 0x1, 0x78, 0xC71C7, 0x70E }, + [OLYMPUS_LUT_CHAN_541875_IDX] = { 21675, 0x1, 0x78, 0xD5555, 0x70E }, + [OLYMPUS_LUT_CHAN_542000_IDX] = { 21680, 0x1, 0x78, 0xE38E4, 0x70F }, + [OLYMPUS_LUT_CHAN_542125_IDX] = { 21685, 0x1, 0x78, 0xF1C72, 0x70F }, + [OLYMPUS_LUT_CHAN_542250_IDX] = { 21690, 0x1, 0x78, 0x100000, 0x710 }, + [OLYMPUS_LUT_CHAN_542375_IDX] = { 21695, 0x1, 0x78, 0x10E38E, 0x710 }, + [OLYMPUS_LUT_CHAN_542500_IDX] = { 21700, 0x1, 0x78, 0x11C71C, 0x710 }, + [OLYMPUS_LUT_CHAN_542625_IDX] = { 21705, 0x1, 0x78, 0x12AAAB, 0x711 }, + [OLYMPUS_LUT_CHAN_542750_IDX] = { 21710, 0x1, 0x78, 0x138E39, 0x711 }, + [OLYMPUS_LUT_CHAN_542875_IDX] = { 21715, 0x1, 0x78, 0x1471C7, 0x712 }, + [OLYMPUS_LUT_CHAN_543000_IDX] = { 21720, 0x1, 0x78, 0x155555, 0x712 }, + [OLYMPUS_LUT_CHAN_543125_IDX] = { 21725, 0x1, 0x78, 0x1638E4, 0x712 }, + [OLYMPUS_LUT_CHAN_543250_IDX] = { 21730, 0x1, 0x78, 0x171C72, 0x713 }, + [OLYMPUS_LUT_CHAN_543375_IDX] = { 21735, 0x1, 0x78, 0x180000, 0x713 }, + [OLYMPUS_LUT_CHAN_543500_IDX] = { 21740, 0x1, 0x78, 0x18E38E, 0x714 }, + [OLYMPUS_LUT_CHAN_543625_IDX] = { 21745, 0x1, 0x78, 0x19C71C, 0x714 }, + [OLYMPUS_LUT_CHAN_543750_IDX] = { 21750, 0x1, 0x78, 0x1AAAAB, 0x715 }, + [OLYMPUS_LUT_CHAN_543875_IDX] = { 21755, 0x1, 0x78, 0x1B8E39, 0x715 }, + [OLYMPUS_LUT_CHAN_544000_IDX] = { 21760, 0x1, 0x78, 0x1C71C7, 0x715 }, + [OLYMPUS_LUT_CHAN_544125_IDX] = { 21765, 0x1, 0x78, 0x1D5555, 0x716 }, + [OLYMPUS_LUT_CHAN_544250_IDX] = { 21770, 0x1, 0x78, 0x1E38E4, 0x716 }, + [OLYMPUS_LUT_CHAN_544375_IDX] = { 21775, 0x1, 0x78, 0x1F1C72, 0x717 }, + [OLYMPUS_LUT_CHAN_544500_IDX] = { 21780, 0x1, 0x79, 0x0, 0x717 }, + [OLYMPUS_LUT_CHAN_544625_IDX] = { 21785, 0x1, 0x79, 0xE38E, 0x717 }, + [OLYMPUS_LUT_CHAN_544750_IDX] = { 21790, 0x1, 0x79, 0x1C71C, 0x718 }, + [OLYMPUS_LUT_CHAN_544875_IDX] = { 21795, 0x1, 0x79, 0x2AAAB, 0x718 }, + [OLYMPUS_LUT_CHAN_545000_IDX] = { 21800, 0x1, 0x79, 0x38E39, 0x719 }, + [OLYMPUS_LUT_CHAN_545125_IDX] = { 21805, 0x1, 0x79, 0x471C7, 0x719 }, + [OLYMPUS_LUT_CHAN_545250_IDX] = { 21810, 0x1, 0x79, 0x55555, 0x71A }, + [OLYMPUS_LUT_CHAN_545375_IDX] = { 21815, 0x1, 0x79, 0x638E4, 0x71A }, + [OLYMPUS_LUT_CHAN_545500_IDX] = { 21820, 0x1, 0x79, 0x71C72, 0x71A }, + [OLYMPUS_LUT_CHAN_545625_IDX] = { 21825, 0x1, 0x79, 0x80000, 0x71B }, + [OLYMPUS_LUT_CHAN_545750_IDX] = { 21830, 0x1, 0x79, 0x8E38E, 0x71B }, + [OLYMPUS_LUT_CHAN_545875_IDX] = { 21835, 0x1, 0x79, 0x9C71C, 0x71C }, + [OLYMPUS_LUT_CHAN_546000_IDX] = { 21840, 0x1, 0x79, 0xAAAAB, 0x71C }, + [OLYMPUS_LUT_CHAN_546125_IDX] = { 21845, 0x1, 0x79, 0xB8E39, 0x71C }, + [OLYMPUS_LUT_CHAN_546250_IDX] = { 21850, 0x1, 0x79, 0xC71C7, 0x71D }, + [OLYMPUS_LUT_CHAN_546375_IDX] = { 21855, 0x1, 0x79, 0xD5555, 0x71D }, + [OLYMPUS_LUT_CHAN_546500_IDX] = { 21860, 0x1, 0x79, 0xE38E4, 0x71E }, + [OLYMPUS_LUT_CHAN_546625_IDX] = { 21865, 0x1, 0x79, 0xF1C72, 0x71E }, + [OLYMPUS_LUT_CHAN_546750_IDX] = { 21870, 0x1, 0x79, 0x100000, 0x71F }, + [OLYMPUS_LUT_CHAN_546875_IDX] = { 21875, 0x1, 0x79, 0x10E38E, 0x71F }, + [OLYMPUS_LUT_CHAN_547000_IDX] = { 21880, 0x1, 0x79, 0x11C71C, 0x71F }, + [OLYMPUS_LUT_CHAN_547125_IDX] = { 21885, 0x1, 0x79, 0x12AAAB, 0x720 }, + [OLYMPUS_LUT_CHAN_547250_IDX] = { 21890, 0x1, 0x79, 0x138E39, 0x720 }, + [OLYMPUS_LUT_CHAN_547375_IDX] = { 21895, 0x1, 0x79, 0x1471C7, 0x721 }, + [OLYMPUS_LUT_CHAN_547500_IDX] = { 21900, 0x1, 0x79, 0x155555, 0x721 }, + [OLYMPUS_LUT_CHAN_547625_IDX] = { 21905, 0x1, 0x79, 0x1638E4, 0x721 }, + [OLYMPUS_LUT_CHAN_547750_IDX] = { 21910, 0x1, 0x79, 0x171C72, 0x722 }, + [OLYMPUS_LUT_CHAN_547875_IDX] = { 21915, 0x1, 0x79, 0x180000, 0x722 }, + [OLYMPUS_LUT_CHAN_548000_IDX] = { 21920, 0x1, 0x79, 0x18E38E, 0x723 }, + [OLYMPUS_LUT_CHAN_548125_IDX] = { 21925, 0x1, 0x79, 0x19C71C, 0x723 }, + [OLYMPUS_LUT_CHAN_548250_IDX] = { 21930, 0x1, 0x79, 0x1AAAAB, 0x724 }, + [OLYMPUS_LUT_CHAN_548375_IDX] = { 21935, 0x1, 0x79, 0x1B8E39, 0x724 }, + [OLYMPUS_LUT_CHAN_548500_IDX] = { 21940, 0x1, 0x79, 0x1C71C7, 0x724 }, + [OLYMPUS_LUT_CHAN_548625_IDX] = { 21945, 0x1, 0x79, 0x1D5555, 0x725 }, + [OLYMPUS_LUT_CHAN_548750_IDX] = { 21950, 0x1, 0x79, 0x1E38E4, 0x725 }, + [OLYMPUS_LUT_CHAN_548875_IDX] = { 21955, 0x1, 0x79, 0x1F1C72, 0x726 }, + [OLYMPUS_LUT_CHAN_549000_IDX] = { 21960, 0x1, 0x7A, 0x0, 0x726 }, + [OLYMPUS_LUT_CHAN_549125_IDX] = { 21965, 0x1, 0x7A, 0xE38E, 0x726 }, + [OLYMPUS_LUT_CHAN_549250_IDX] = { 21970, 0x1, 0x7A, 0x1C71C, 0x727 }, + [OLYMPUS_LUT_CHAN_549375_IDX] = { 21975, 0x1, 0x7A, 0x2AAAB, 0x727 }, + [OLYMPUS_LUT_CHAN_549500_IDX] = { 21980, 0x1, 0x7A, 0x38E39, 0x728 }, + [OLYMPUS_LUT_CHAN_549625_IDX] = { 21985, 0x1, 0x7A, 0x471C7, 0x728 }, + [OLYMPUS_LUT_CHAN_549750_IDX] = { 21990, 0x1, 0x7A, 0x55555, 0x729 }, + [OLYMPUS_LUT_CHAN_549875_IDX] = { 21995, 0x1, 0x7A, 0x638E4, 0x729 }, + [OLYMPUS_LUT_CHAN_550000_IDX] = { 22000, 0x1, 0x7A, 0x71C72, 0x729 }, + [OLYMPUS_LUT_CHAN_550125_IDX] = { 22005, 0x1, 0x7A, 0x80000, 0x72A }, + [OLYMPUS_LUT_CHAN_550250_IDX] = { 22010, 0x1, 0x7A, 0x8E38E, 0x72A }, + [OLYMPUS_LUT_CHAN_550375_IDX] = { 22015, 0x1, 0x7A, 0x9C71C, 0x72B }, + [OLYMPUS_LUT_CHAN_550500_IDX] = { 22020, 0x1, 0x7A, 0xAAAAB, 0x72B }, + [OLYMPUS_LUT_CHAN_550625_IDX] = { 22025, 0x1, 0x7A, 0xB8E39, 0x72B }, + [OLYMPUS_LUT_CHAN_550750_IDX] = { 22030, 0x1, 0x7A, 0xC71C7, 0x72C }, + [OLYMPUS_LUT_CHAN_550875_IDX] = { 22035, 0x1, 0x7A, 0xD5555, 0x72C }, + [OLYMPUS_LUT_CHAN_551000_IDX] = { 22040, 0x1, 0x7A, 0xE38E4, 0x72D }, + [OLYMPUS_LUT_CHAN_551125_IDX] = { 22045, 0x1, 0x7A, 0xF1C72, 0x72D }, + [OLYMPUS_LUT_CHAN_551250_IDX] = { 22050, 0x1, 0x7A, 0x100000, 0x72E }, + [OLYMPUS_LUT_CHAN_551375_IDX] = { 22055, 0x1, 0x7A, 0x10E38E, 0x72E }, + [OLYMPUS_LUT_CHAN_551500_IDX] = { 22060, 0x1, 0x7A, 0x11C71C, 0x72E }, + [OLYMPUS_LUT_CHAN_551625_IDX] = { 22065, 0x1, 0x7A, 0x12AAAB, 0x72F }, + [OLYMPUS_LUT_CHAN_551750_IDX] = { 22070, 0x1, 0x7A, 0x138E39, 0x72F }, + [OLYMPUS_LUT_CHAN_551875_IDX] = { 22075, 0x1, 0x7A, 0x1471C7, 0x730 }, + [OLYMPUS_LUT_CHAN_552000_IDX] = { 22080, 0x1, 0x7A, 0x155555, 0x730 }, + [OLYMPUS_LUT_CHAN_552125_IDX] = { 22085, 0x1, 0x7A, 0x1638E4, 0x730 }, + [OLYMPUS_LUT_CHAN_552250_IDX] = { 22090, 0x1, 0x7A, 0x171C72, 0x731 }, + [OLYMPUS_LUT_CHAN_552375_IDX] = { 22095, 0x1, 0x7A, 0x180000, 0x731 }, + [OLYMPUS_LUT_CHAN_552500_IDX] = { 22100, 0x1, 0x7A, 0x18E38E, 0x732 }, + [OLYMPUS_LUT_CHAN_552625_IDX] = { 22105, 0x1, 0x7A, 0x19C71C, 0x732 }, + [OLYMPUS_LUT_CHAN_552750_IDX] = { 22110, 0x1, 0x7A, 0x1AAAAB, 0x733 }, + [OLYMPUS_LUT_CHAN_552875_IDX] = { 22115, 0x1, 0x7A, 0x1B8E39, 0x733 }, + [OLYMPUS_LUT_CHAN_553000_IDX] = { 22120, 0x1, 0x7A, 0x1C71C7, 0x733 }, + [OLYMPUS_LUT_CHAN_553125_IDX] = { 22125, 0x1, 0x7A, 0x1D5555, 0x734 }, + [OLYMPUS_LUT_CHAN_553250_IDX] = { 22130, 0x1, 0x7A, 0x1E38E4, 0x734 }, + [OLYMPUS_LUT_CHAN_553375_IDX] = { 22135, 0x1, 0x7A, 0x1F1C72, 0x735 }, + [OLYMPUS_LUT_CHAN_553500_IDX] = { 22140, 0x1, 0x7B, 0x0, 0x735 }, + [OLYMPUS_LUT_CHAN_553625_IDX] = { 22145, 0x1, 0x7B, 0xE38E, 0x735 }, + [OLYMPUS_LUT_CHAN_553750_IDX] = { 22150, 0x1, 0x7B, 0x1C71C, 0x736 }, + [OLYMPUS_LUT_CHAN_553875_IDX] = { 22155, 0x1, 0x7B, 0x2AAAB, 0x736 }, + [OLYMPUS_LUT_CHAN_554000_IDX] = { 22160, 0x1, 0x7B, 0x38E39, 0x737 }, + [OLYMPUS_LUT_CHAN_554125_IDX] = { 22165, 0x1, 0x7B, 0x471C7, 0x737 }, + [OLYMPUS_LUT_CHAN_554250_IDX] = { 22170, 0x1, 0x7B, 0x55555, 0x738 }, + [OLYMPUS_LUT_CHAN_554375_IDX] = { 22175, 0x1, 0x7B, 0x638E4, 0x738 }, + [OLYMPUS_LUT_CHAN_554500_IDX] = { 22180, 0x1, 0x7B, 0x71C72, 0x738 }, + [OLYMPUS_LUT_CHAN_554625_IDX] = { 22185, 0x1, 0x7B, 0x80000, 0x739 }, + [OLYMPUS_LUT_CHAN_554750_IDX] = { 22190, 0x1, 0x7B, 0x8E38E, 0x739 }, + [OLYMPUS_LUT_CHAN_554875_IDX] = { 22195, 0x1, 0x7B, 0x9C71C, 0x73A }, + [OLYMPUS_LUT_CHAN_555000_IDX] = { 22200, 0x1, 0x7B, 0xAAAAB, 0x73A }, + [OLYMPUS_LUT_CHAN_555125_IDX] = { 22205, 0x1, 0x7B, 0xB8E39, 0x73A }, + [OLYMPUS_LUT_CHAN_555250_IDX] = { 22210, 0x1, 0x7B, 0xC71C7, 0x73B }, + [OLYMPUS_LUT_CHAN_555375_IDX] = { 22215, 0x1, 0x7B, 0xD5555, 0x73B }, + [OLYMPUS_LUT_CHAN_555500_IDX] = { 22220, 0x1, 0x7B, 0xE38E4, 0x73C }, + [OLYMPUS_LUT_CHAN_555625_IDX] = { 22225, 0x1, 0x7B, 0xF1C72, 0x73C }, + [OLYMPUS_LUT_CHAN_555750_IDX] = { 22230, 0x1, 0x7B, 0x100000, 0x73D }, + [OLYMPUS_LUT_CHAN_555875_IDX] = { 22235, 0x1, 0x7B, 0x10E38E, 0x73D }, + [OLYMPUS_LUT_CHAN_556000_IDX] = { 22240, 0x1, 0x7B, 0x11C71C, 0x73D }, + [OLYMPUS_LUT_CHAN_556125_IDX] = { 22245, 0x1, 0x7B, 0x12AAAB, 0x73E }, + [OLYMPUS_LUT_CHAN_556250_IDX] = { 22250, 0x1, 0x7B, 0x138E39, 0x73E }, + [OLYMPUS_LUT_CHAN_556375_IDX] = { 22255, 0x1, 0x7B, 0x1471C7, 0x73F }, + [OLYMPUS_LUT_CHAN_556500_IDX] = { 22260, 0x1, 0x7B, 0x155555, 0x73F }, + [OLYMPUS_LUT_CHAN_556625_IDX] = { 22265, 0x1, 0x7B, 0x1638E4, 0x73F }, + [OLYMPUS_LUT_CHAN_556750_IDX] = { 22270, 0x1, 0x7B, 0x171C72, 0x740 }, + [OLYMPUS_LUT_CHAN_556875_IDX] = { 22275, 0x1, 0x7B, 0x180000, 0x740 }, + [OLYMPUS_LUT_CHAN_557000_IDX] = { 22280, 0x1, 0x7B, 0x18E38E, 0x741 }, + [OLYMPUS_LUT_CHAN_557125_IDX] = { 22285, 0x1, 0x7B, 0x19C71C, 0x741 }, + [OLYMPUS_LUT_CHAN_557250_IDX] = { 22290, 0x1, 0x7B, 0x1AAAAB, 0x742 }, + [OLYMPUS_LUT_CHAN_557375_IDX] = { 22295, 0x1, 0x7B, 0x1B8E39, 0x742 }, + [OLYMPUS_LUT_CHAN_557500_IDX] = { 22300, 0x1, 0x7B, 0x1C71C7, 0x742 }, + [OLYMPUS_LUT_CHAN_557625_IDX] = { 22305, 0x1, 0x7B, 0x1D5555, 0x743 }, + [OLYMPUS_LUT_CHAN_557750_IDX] = { 22310, 0x1, 0x7B, 0x1E38E4, 0x743 }, + [OLYMPUS_LUT_CHAN_557875_IDX] = { 22315, 0x1, 0x7B, 0x1F1C72, 0x744 }, + [OLYMPUS_LUT_CHAN_558000_IDX] = { 22320, 0x1, 0x7C, 0x0, 0x744 }, + [OLYMPUS_LUT_CHAN_558125_IDX] = { 22325, 0x1, 0x7C, 0xE38E, 0x744 }, + [OLYMPUS_LUT_CHAN_558250_IDX] = { 22330, 0x1, 0x7C, 0x1C71C, 0x745 }, + [OLYMPUS_LUT_CHAN_558375_IDX] = { 22335, 0x1, 0x7C, 0x2AAAB, 0x745 }, + [OLYMPUS_LUT_CHAN_558500_IDX] = { 22340, 0x1, 0x7C, 0x38E39, 0x746 }, + [OLYMPUS_LUT_CHAN_558625_IDX] = { 22345, 0x1, 0x7C, 0x471C7, 0x746 }, + [OLYMPUS_LUT_CHAN_558750_IDX] = { 22350, 0x1, 0x7C, 0x55555, 0x747 }, + [OLYMPUS_LUT_CHAN_558875_IDX] = { 22355, 0x1, 0x7C, 0x638E4, 0x747 }, + [OLYMPUS_LUT_CHAN_559000_IDX] = { 22360, 0x1, 0x7C, 0x71C72, 0x747 }, + [OLYMPUS_LUT_CHAN_559125_IDX] = { 22365, 0x1, 0x7C, 0x80000, 0x748 }, + [OLYMPUS_LUT_CHAN_559250_IDX] = { 22370, 0x1, 0x7C, 0x8E38E, 0x748 }, + [OLYMPUS_LUT_CHAN_559375_IDX] = { 22375, 0x1, 0x7C, 0x9C71C, 0x749 }, + [OLYMPUS_LUT_CHAN_559500_IDX] = { 22380, 0x1, 0x7C, 0xAAAAB, 0x749 }, + [OLYMPUS_LUT_CHAN_559625_IDX] = { 22385, 0x1, 0x7C, 0xB8E39, 0x749 }, + [OLYMPUS_LUT_CHAN_559750_IDX] = { 22390, 0x1, 0x7C, 0xC71C7, 0x74A }, + [OLYMPUS_LUT_CHAN_559875_IDX] = { 22395, 0x1, 0x7C, 0xD5555, 0x74A }, + [OLYMPUS_LUT_CHAN_560000_IDX] = { 22400, 0x1, 0x7C, 0xE38E4, 0x74B }, + [OLYMPUS_LUT_CHAN_560125_IDX] = { 22405, 0x1, 0x7C, 0xF1C72, 0x74B }, + [OLYMPUS_LUT_CHAN_560250_IDX] = { 22410, 0x1, 0x7C, 0x100000, 0x74C }, + [OLYMPUS_LUT_CHAN_560375_IDX] = { 22415, 0x1, 0x7C, 0x10E38E, 0x74C }, + [OLYMPUS_LUT_CHAN_560500_IDX] = { 22420, 0x1, 0x7C, 0x11C71C, 0x74C }, + [OLYMPUS_LUT_CHAN_560625_IDX] = { 22425, 0x1, 0x7C, 0x12AAAB, 0x74D }, + [OLYMPUS_LUT_CHAN_560750_IDX] = { 22430, 0x1, 0x7C, 0x138E39, 0x74D }, + [OLYMPUS_LUT_CHAN_560875_IDX] = { 22435, 0x1, 0x7C, 0x1471C7, 0x74E }, + [OLYMPUS_LUT_CHAN_561000_IDX] = { 22440, 0x1, 0x7C, 0x155555, 0x74E }, + [OLYMPUS_LUT_CHAN_561125_IDX] = { 22445, 0x1, 0x7C, 0x1638E4, 0x74E }, + [OLYMPUS_LUT_CHAN_561250_IDX] = { 22450, 0x1, 0x7C, 0x171C72, 0x74F }, + [OLYMPUS_LUT_CHAN_561375_IDX] = { 22455, 0x1, 0x7C, 0x180000, 0x74F }, + [OLYMPUS_LUT_CHAN_561500_IDX] = { 22460, 0x1, 0x7C, 0x18E38E, 0x750 }, + [OLYMPUS_LUT_CHAN_561625_IDX] = { 22465, 0x1, 0x7C, 0x19C71C, 0x750 }, + [OLYMPUS_LUT_CHAN_561750_IDX] = { 22470, 0x1, 0x7C, 0x1AAAAB, 0x751 }, + [OLYMPUS_LUT_CHAN_561875_IDX] = { 22475, 0x1, 0x7C, 0x1B8E39, 0x751 }, + [OLYMPUS_LUT_CHAN_562000_IDX] = { 22480, 0x1, 0x7C, 0x1C71C7, 0x751 }, + [OLYMPUS_LUT_CHAN_562125_IDX] = { 22485, 0x1, 0x7C, 0x1D5555, 0x752 }, + [OLYMPUS_LUT_CHAN_562250_IDX] = { 22490, 0x1, 0x7C, 0x1E38E4, 0x752 }, + [OLYMPUS_LUT_CHAN_562375_IDX] = { 22495, 0x1, 0x7C, 0x1F1C72, 0x753 }, + [OLYMPUS_LUT_CHAN_562500_IDX] = { 22500, 0x1, 0x7D, 0x0, 0x753 }, + [OLYMPUS_LUT_CHAN_562625_IDX] = { 22505, 0x1, 0x7D, 0xE38E, 0x753 }, + [OLYMPUS_LUT_CHAN_562750_IDX] = { 22510, 0x1, 0x7D, 0x1C71C, 0x754 }, + [OLYMPUS_LUT_CHAN_562875_IDX] = { 22515, 0x1, 0x7D, 0x2AAAB, 0x754 }, + [OLYMPUS_LUT_CHAN_563000_IDX] = { 22520, 0x1, 0x7D, 0x38E39, 0x755 }, + [OLYMPUS_LUT_CHAN_563125_IDX] = { 22525, 0x1, 0x7D, 0x471C7, 0x755 }, + [OLYMPUS_LUT_CHAN_563250_IDX] = { 22530, 0x1, 0x7D, 0x55555, 0x756 }, + [OLYMPUS_LUT_CHAN_563375_IDX] = { 22535, 0x1, 0x7D, 0x638E4, 0x756 }, + [OLYMPUS_LUT_CHAN_563500_IDX] = { 22540, 0x1, 0x7D, 0x71C72, 0x756 }, + [OLYMPUS_LUT_CHAN_563625_IDX] = { 22545, 0x1, 0x7D, 0x80000, 0x757 }, + [OLYMPUS_LUT_CHAN_563750_IDX] = { 22550, 0x1, 0x7D, 0x8E38E, 0x757 }, + [OLYMPUS_LUT_CHAN_563875_IDX] = { 22555, 0x1, 0x7D, 0x9C71C, 0x758 }, + [OLYMPUS_LUT_CHAN_564000_IDX] = { 22560, 0x1, 0x7D, 0xAAAAB, 0x758 }, + [OLYMPUS_LUT_CHAN_564125_IDX] = { 22565, 0x1, 0x7D, 0xB8E39, 0x758 }, + [OLYMPUS_LUT_CHAN_564250_IDX] = { 22570, 0x1, 0x7D, 0xC71C7, 0x759 }, + [OLYMPUS_LUT_CHAN_564375_IDX] = { 22575, 0x1, 0x7D, 0xD5555, 0x759 }, + [OLYMPUS_LUT_CHAN_564500_IDX] = { 22580, 0x1, 0x7D, 0xE38E4, 0x75A }, + [OLYMPUS_LUT_CHAN_564625_IDX] = { 22585, 0x1, 0x7D, 0xF1C72, 0x75A }, + [OLYMPUS_LUT_CHAN_564750_IDX] = { 22590, 0x1, 0x7D, 0x100000, 0x75B }, + [OLYMPUS_LUT_CHAN_564875_IDX] = { 22595, 0x1, 0x7D, 0x10E38E, 0x75B }, + [OLYMPUS_LUT_CHAN_565000_IDX] = { 22600, 0x1, 0x7D, 0x11C71C, 0x75B }, + [OLYMPUS_LUT_CHAN_565125_IDX] = { 22605, 0x1, 0x7D, 0x12AAAB, 0x75C }, + [OLYMPUS_LUT_CHAN_565250_IDX] = { 22610, 0x1, 0x7D, 0x138E39, 0x75C }, + [OLYMPUS_LUT_CHAN_565375_IDX] = { 22615, 0x1, 0x7D, 0x1471C7, 0x75D }, + [OLYMPUS_LUT_CHAN_565500_IDX] = { 22620, 0x1, 0x7D, 0x155555, 0x75D }, + [OLYMPUS_LUT_CHAN_565625_IDX] = { 22625, 0x1, 0x7D, 0x1638E4, 0x75D }, + [OLYMPUS_LUT_CHAN_565750_IDX] = { 22630, 0x1, 0x7D, 0x171C72, 0x75E }, + [OLYMPUS_LUT_CHAN_565875_IDX] = { 22635, 0x1, 0x7D, 0x180000, 0x75E }, + [OLYMPUS_LUT_CHAN_566000_IDX] = { 22640, 0x1, 0x7D, 0x18E38E, 0x75F }, + [OLYMPUS_LUT_CHAN_566125_IDX] = { 22645, 0x1, 0x7D, 0x19C71C, 0x75F }, + [OLYMPUS_LUT_CHAN_566250_IDX] = { 22650, 0x1, 0x7D, 0x1AAAAB, 0x760 }, + [OLYMPUS_LUT_CHAN_566375_IDX] = { 22655, 0x1, 0x7D, 0x1B8E39, 0x760 }, + [OLYMPUS_LUT_CHAN_566500_IDX] = { 22660, 0x1, 0x7D, 0x1C71C7, 0x760 }, + [OLYMPUS_LUT_CHAN_566625_IDX] = { 22665, 0x1, 0x7D, 0x1D5555, 0x761 }, + [OLYMPUS_LUT_CHAN_566750_IDX] = { 22670, 0x1, 0x7D, 0x1E38E4, 0x761 }, + [OLYMPUS_LUT_CHAN_566875_IDX] = { 22675, 0x1, 0x7D, 0x1F1C72, 0x762 }, + [OLYMPUS_LUT_CHAN_567000_IDX] = { 22680, 0x1, 0x7E, 0x0, 0x762 }, + [OLYMPUS_LUT_CHAN_567125_IDX] = { 22685, 0x1, 0x7E, 0xE38E, 0x762 }, + [OLYMPUS_LUT_CHAN_567250_IDX] = { 22690, 0x1, 0x7E, 0x1C71C, 0x763 }, + [OLYMPUS_LUT_CHAN_567375_IDX] = { 22695, 0x1, 0x7E, 0x2AAAB, 0x763 }, + [OLYMPUS_LUT_CHAN_567500_IDX] = { 22700, 0x1, 0x7E, 0x38E39, 0x764 }, + [OLYMPUS_LUT_CHAN_567625_IDX] = { 22705, 0x1, 0x7E, 0x471C7, 0x764 }, + [OLYMPUS_LUT_CHAN_567750_IDX] = { 22710, 0x1, 0x7E, 0x55555, 0x765 }, + [OLYMPUS_LUT_CHAN_567875_IDX] = { 22715, 0x1, 0x7E, 0x638E4, 0x765 }, + [OLYMPUS_LUT_CHAN_568000_IDX] = { 22720, 0x1, 0x7E, 0x71C72, 0x765 }, + [OLYMPUS_LUT_CHAN_568125_IDX] = { 22725, 0x1, 0x7E, 0x80000, 0x766 }, + [OLYMPUS_LUT_CHAN_568250_IDX] = { 22730, 0x1, 0x7E, 0x8E38E, 0x766 }, + [OLYMPUS_LUT_CHAN_568375_IDX] = { 22735, 0x1, 0x7E, 0x9C71C, 0x767 }, + [OLYMPUS_LUT_CHAN_568500_IDX] = { 22740, 0x1, 0x7E, 0xAAAAB, 0x767 }, + [OLYMPUS_LUT_CHAN_568625_IDX] = { 22745, 0x1, 0x7E, 0xB8E39, 0x767 }, + [OLYMPUS_LUT_CHAN_568750_IDX] = { 22750, 0x1, 0x7E, 0xC71C7, 0x768 }, + [OLYMPUS_LUT_CHAN_568875_IDX] = { 22755, 0x1, 0x7E, 0xD5555, 0x768 }, + [OLYMPUS_LUT_CHAN_569000_IDX] = { 22760, 0x1, 0x7E, 0xE38E4, 0x769 }, + [OLYMPUS_LUT_CHAN_569125_IDX] = { 22765, 0x1, 0x7E, 0xF1C72, 0x769 }, + [OLYMPUS_LUT_CHAN_569250_IDX] = { 22770, 0x1, 0x7E, 0x100000, 0x76A }, + [OLYMPUS_LUT_CHAN_569375_IDX] = { 22775, 0x1, 0x7E, 0x10E38E, 0x76A }, + [OLYMPUS_LUT_CHAN_569500_IDX] = { 22780, 0x1, 0x7E, 0x11C71C, 0x76A }, + [OLYMPUS_LUT_CHAN_569625_IDX] = { 22785, 0x1, 0x7E, 0x12AAAB, 0x76B }, + [OLYMPUS_LUT_CHAN_569750_IDX] = { 22790, 0x1, 0x7E, 0x138E39, 0x76B }, + [OLYMPUS_LUT_CHAN_569875_IDX] = { 22795, 0x1, 0x7E, 0x1471C7, 0x76C }, + [OLYMPUS_LUT_CHAN_570000_IDX] = { 22800, 0x1, 0x7E, 0x155555, 0x76C }, + [OLYMPUS_LUT_CHAN_570125_IDX] = { 22805, 0x1, 0x7E, 0x1638E4, 0x76C }, + [OLYMPUS_LUT_CHAN_570250_IDX] = { 22810, 0x1, 0x7E, 0x171C72, 0x76D }, + [OLYMPUS_LUT_CHAN_570375_IDX] = { 22815, 0x1, 0x7E, 0x180000, 0x76D }, + [OLYMPUS_LUT_CHAN_570500_IDX] = { 22820, 0x1, 0x7E, 0x18E38E, 0x76E }, + [OLYMPUS_LUT_CHAN_570625_IDX] = { 22825, 0x1, 0x7E, 0x19C71C, 0x76E }, + [OLYMPUS_LUT_CHAN_570750_IDX] = { 22830, 0x1, 0x7E, 0x1AAAAB, 0x76F }, + [OLYMPUS_LUT_CHAN_570875_IDX] = { 22835, 0x1, 0x7E, 0x1B8E39, 0x76F }, + [OLYMPUS_LUT_CHAN_571000_IDX] = { 22840, 0x1, 0x7E, 0x1C71C7, 0x76F }, + [OLYMPUS_LUT_CHAN_571125_IDX] = { 22845, 0x1, 0x7E, 0x1D5555, 0x770 }, + [OLYMPUS_LUT_CHAN_571250_IDX] = { 22850, 0x1, 0x7E, 0x1E38E4, 0x770 }, + [OLYMPUS_LUT_CHAN_571375_IDX] = { 22855, 0x1, 0x7E, 0x1F1C72, 0x771 }, + [OLYMPUS_LUT_CHAN_571500_IDX] = { 22860, 0x1, 0x7F, 0x0, 0x771 }, + [OLYMPUS_LUT_CHAN_571625_IDX] = { 22865, 0x1, 0x7F, 0xE38E, 0x771 }, + [OLYMPUS_LUT_CHAN_571750_IDX] = { 22870, 0x1, 0x7F, 0x1C71C, 0x772 }, + [OLYMPUS_LUT_CHAN_571875_IDX] = { 22875, 0x1, 0x7F, 0x2AAAB, 0x772 }, + [OLYMPUS_LUT_CHAN_572000_IDX] = { 22880, 0x1, 0x7F, 0x38E39, 0x773 }, + [OLYMPUS_LUT_CHAN_572125_IDX] = { 22885, 0x1, 0x7F, 0x471C7, 0x773 }, + [OLYMPUS_LUT_CHAN_572250_IDX] = { 22890, 0x1, 0x7F, 0x55555, 0x774 }, + [OLYMPUS_LUT_CHAN_572375_IDX] = { 22895, 0x1, 0x7F, 0x638E4, 0x774 }, + [OLYMPUS_LUT_CHAN_572500_IDX] = { 22900, 0x1, 0x7F, 0x71C72, 0x774 }, + [OLYMPUS_LUT_CHAN_572625_IDX] = { 22905, 0x1, 0x7F, 0x80000, 0x775 }, + [OLYMPUS_LUT_CHAN_572750_IDX] = { 22910, 0x1, 0x7F, 0x8E38E, 0x775 }, + [OLYMPUS_LUT_CHAN_572875_IDX] = { 22915, 0x1, 0x7F, 0x9C71C, 0x776 }, + [OLYMPUS_LUT_CHAN_573000_IDX] = { 22920, 0x1, 0x7F, 0xAAAAB, 0x776 }, + [OLYMPUS_LUT_CHAN_573125_IDX] = { 22925, 0x1, 0x7F, 0xB8E39, 0x776 }, + [OLYMPUS_LUT_CHAN_573250_IDX] = { 22930, 0x1, 0x7F, 0xC71C7, 0x777 }, + [OLYMPUS_LUT_CHAN_573375_IDX] = { 22935, 0x1, 0x7F, 0xD5555, 0x777 }, + [OLYMPUS_LUT_CHAN_573500_IDX] = { 22940, 0x1, 0x7F, 0xE38E4, 0x778 }, + [OLYMPUS_LUT_CHAN_573625_IDX] = { 22945, 0x1, 0x7F, 0xF1C72, 0x778 }, + [OLYMPUS_LUT_CHAN_573750_IDX] = { 22950, 0x1, 0x7F, 0x100000, 0x779 }, + [OLYMPUS_LUT_CHAN_573875_IDX] = { 22955, 0x1, 0x7F, 0x10E38E, 0x779 }, + [OLYMPUS_LUT_CHAN_574000_IDX] = { 22960, 0x1, 0x7F, 0x11C71C, 0x779 }, + [OLYMPUS_LUT_CHAN_574125_IDX] = { 22965, 0x1, 0x7F, 0x12AAAB, 0x77A }, + [OLYMPUS_LUT_CHAN_574250_IDX] = { 22970, 0x1, 0x7F, 0x138E39, 0x77A }, + [OLYMPUS_LUT_CHAN_574375_IDX] = { 22975, 0x1, 0x7F, 0x1471C7, 0x77B }, + [OLYMPUS_LUT_CHAN_574500_IDX] = { 22980, 0x1, 0x7F, 0x155555, 0x77B }, + [OLYMPUS_LUT_CHAN_574625_IDX] = { 22985, 0x1, 0x7F, 0x1638E4, 0x77B }, + [OLYMPUS_LUT_CHAN_574750_IDX] = { 22990, 0x1, 0x7F, 0x171C72, 0x77C }, + [OLYMPUS_LUT_CHAN_574875_IDX] = { 22995, 0x1, 0x7F, 0x180000, 0x77C }, + [OLYMPUS_LUT_CHAN_575000_IDX] = { 23000, 0x1, 0x7F, 0x18E38E, 0x77D }, + [OLYMPUS_LUT_CHAN_575125_IDX] = { 23005, 0x1, 0x7F, 0x19C71C, 0x77D }, + [OLYMPUS_LUT_CHAN_575250_IDX] = { 23010, 0x1, 0x7F, 0x1AAAAB, 0x77E }, + [OLYMPUS_LUT_CHAN_575375_IDX] = { 23015, 0x1, 0x7F, 0x1B8E39, 0x77E }, + [OLYMPUS_LUT_CHAN_575500_IDX] = { 23020, 0x1, 0x7F, 0x1C71C7, 0x77E }, + [OLYMPUS_LUT_CHAN_575625_IDX] = { 23025, 0x1, 0x7F, 0x1D5555, 0x77F }, + [OLYMPUS_LUT_CHAN_575750_IDX] = { 23030, 0x1, 0x7F, 0x1E38E4, 0x77F }, + [OLYMPUS_LUT_CHAN_575875_IDX] = { 23035, 0x1, 0x7F, 0x1F1C72, 0x780 }, + [OLYMPUS_LUT_CHAN_576000_IDX] = { 23040, 0x1, 0x80, 0x0, 0x780 }, + [OLYMPUS_LUT_CHAN_576125_IDX] = { 23045, 0x1, 0x80, 0xE38E, 0x780 }, + [OLYMPUS_LUT_CHAN_576250_IDX] = { 23050, 0x1, 0x80, 0x1C71C, 0x781 }, + [OLYMPUS_LUT_CHAN_576375_IDX] = { 23055, 0x1, 0x80, 0x2AAAB, 0x781 }, + [OLYMPUS_LUT_CHAN_576500_IDX] = { 23060, 0x1, 0x80, 0x38E39, 0x782 }, + [OLYMPUS_LUT_CHAN_576625_IDX] = { 23065, 0x1, 0x80, 0x471C7, 0x782 }, + [OLYMPUS_LUT_CHAN_576750_IDX] = { 23070, 0x1, 0x80, 0x55555, 0x783 }, + [OLYMPUS_LUT_CHAN_576875_IDX] = { 23075, 0x1, 0x80, 0x638E4, 0x783 }, + [OLYMPUS_LUT_CHAN_577000_IDX] = { 23080, 0x1, 0x80, 0x71C72, 0x783 }, + [OLYMPUS_LUT_CHAN_577125_IDX] = { 23085, 0x1, 0x80, 0x80000, 0x784 }, + [OLYMPUS_LUT_CHAN_577250_IDX] = { 23090, 0x1, 0x80, 0x8E38E, 0x784 }, + [OLYMPUS_LUT_CHAN_577375_IDX] = { 23095, 0x1, 0x80, 0x9C71C, 0x785 }, + [OLYMPUS_LUT_CHAN_577500_IDX] = { 23100, 0x1, 0x80, 0xAAAAB, 0x785 }, + [OLYMPUS_LUT_CHAN_577625_IDX] = { 23105, 0x1, 0x80, 0xB8E39, 0x785 }, + [OLYMPUS_LUT_CHAN_577750_IDX] = { 23110, 0x1, 0x80, 0xC71C7, 0x786 }, + [OLYMPUS_LUT_CHAN_577875_IDX] = { 23115, 0x1, 0x80, 0xD5555, 0x786 }, + [OLYMPUS_LUT_CHAN_578000_IDX] = { 23120, 0x1, 0x80, 0xE38E4, 0x787 }, + [OLYMPUS_LUT_CHAN_578125_IDX] = { 23125, 0x1, 0x80, 0xF1C72, 0x787 }, + [OLYMPUS_LUT_CHAN_578250_IDX] = { 23130, 0x1, 0x80, 0x100000, 0x788 }, + [OLYMPUS_LUT_CHAN_578375_IDX] = { 23135, 0x1, 0x80, 0x10E38E, 0x788 }, + [OLYMPUS_LUT_CHAN_578500_IDX] = { 23140, 0x1, 0x80, 0x11C71C, 0x788 }, + [OLYMPUS_LUT_CHAN_578625_IDX] = { 23145, 0x1, 0x80, 0x12AAAB, 0x789 }, + [OLYMPUS_LUT_CHAN_578750_IDX] = { 23150, 0x1, 0x80, 0x138E39, 0x789 }, + [OLYMPUS_LUT_CHAN_578875_IDX] = { 23155, 0x1, 0x80, 0x1471C7, 0x78A }, + [OLYMPUS_LUT_CHAN_579000_IDX] = { 23160, 0x1, 0x80, 0x155555, 0x78A }, + [OLYMPUS_LUT_CHAN_579125_IDX] = { 23165, 0x1, 0x80, 0x1638E4, 0x78A }, + [OLYMPUS_LUT_CHAN_579250_IDX] = { 23170, 0x1, 0x80, 0x171C72, 0x78B }, + [OLYMPUS_LUT_CHAN_579375_IDX] = { 23175, 0x1, 0x80, 0x180000, 0x78B }, + [OLYMPUS_LUT_CHAN_579500_IDX] = { 23180, 0x1, 0x80, 0x18E38E, 0x78C }, + [OLYMPUS_LUT_CHAN_579625_IDX] = { 23185, 0x1, 0x80, 0x19C71C, 0x78C }, + [OLYMPUS_LUT_CHAN_579750_IDX] = { 23190, 0x1, 0x80, 0x1AAAAB, 0x78D }, + [OLYMPUS_LUT_CHAN_579875_IDX] = { 23195, 0x1, 0x80, 0x1B8E39, 0x78D }, + [OLYMPUS_LUT_CHAN_580000_IDX] = { 23200, 0x1, 0x80, 0x1C71C7, 0x78D }, + [OLYMPUS_LUT_CHAN_580125_IDX] = { 23205, 0x1, 0x80, 0x1D5555, 0x78E }, + [OLYMPUS_LUT_CHAN_580250_IDX] = { 23210, 0x1, 0x80, 0x1E38E4, 0x78E }, + [OLYMPUS_LUT_CHAN_580375_IDX] = { 23215, 0x1, 0x80, 0x1F1C72, 0x78F }, + [OLYMPUS_LUT_CHAN_580500_IDX] = { 23220, 0x1, 0x81, 0x0, 0x78F }, + [OLYMPUS_LUT_CHAN_580625_IDX] = { 23225, 0x1, 0x81, 0xE38E, 0x78F }, + [OLYMPUS_LUT_CHAN_580750_IDX] = { 23230, 0x1, 0x81, 0x1C71C, 0x790 }, + [OLYMPUS_LUT_CHAN_580875_IDX] = { 23235, 0x1, 0x81, 0x2AAAB, 0x790 }, + [OLYMPUS_LUT_CHAN_581000_IDX] = { 23240, 0x1, 0x81, 0x38E39, 0x791 }, + [OLYMPUS_LUT_CHAN_581125_IDX] = { 23245, 0x1, 0x81, 0x471C7, 0x791 }, + [OLYMPUS_LUT_CHAN_581250_IDX] = { 23250, 0x1, 0x81, 0x55555, 0x792 }, + [OLYMPUS_LUT_CHAN_581375_IDX] = { 23255, 0x1, 0x81, 0x638E4, 0x792 }, + [OLYMPUS_LUT_CHAN_581500_IDX] = { 23260, 0x1, 0x81, 0x71C72, 0x792 }, + [OLYMPUS_LUT_CHAN_581625_IDX] = { 23265, 0x1, 0x81, 0x80000, 0x793 }, + [OLYMPUS_LUT_CHAN_581750_IDX] = { 23270, 0x1, 0x81, 0x8E38E, 0x793 }, + [OLYMPUS_LUT_CHAN_581875_IDX] = { 23275, 0x1, 0x81, 0x9C71C, 0x794 }, + [OLYMPUS_LUT_CHAN_582000_IDX] = { 23280, 0x1, 0x81, 0xAAAAB, 0x794 }, + [OLYMPUS_LUT_CHAN_582125_IDX] = { 23285, 0x1, 0x81, 0xB8E39, 0x794 }, + [OLYMPUS_LUT_CHAN_582250_IDX] = { 23290, 0x1, 0x81, 0xC71C7, 0x795 }, + [OLYMPUS_LUT_CHAN_582375_IDX] = { 23295, 0x1, 0x81, 0xD5555, 0x795 }, + [OLYMPUS_LUT_CHAN_582500_IDX] = { 23300, 0x1, 0x81, 0xE38E4, 0x796 }, + [OLYMPUS_LUT_CHAN_582625_IDX] = { 23305, 0x1, 0x81, 0xF1C72, 0x796 }, + [OLYMPUS_LUT_CHAN_582750_IDX] = { 23310, 0x1, 0x81, 0x100000, 0x797 }, + [OLYMPUS_LUT_CHAN_582875_IDX] = { 23315, 0x1, 0x81, 0x10E38E, 0x797 }, + [OLYMPUS_LUT_CHAN_583000_IDX] = { 23320, 0x1, 0x81, 0x11C71C, 0x797 }, + [OLYMPUS_LUT_CHAN_583125_IDX] = { 23325, 0x1, 0x81, 0x12AAAB, 0x798 }, + [OLYMPUS_LUT_CHAN_583250_IDX] = { 23330, 0x1, 0x81, 0x138E39, 0x798 }, + [OLYMPUS_LUT_CHAN_583375_IDX] = { 23335, 0x1, 0x81, 0x1471C7, 0x799 }, + [OLYMPUS_LUT_CHAN_583500_IDX] = { 23340, 0x1, 0x81, 0x155555, 0x799 }, + [OLYMPUS_LUT_CHAN_583625_IDX] = { 23345, 0x1, 0x81, 0x1638E4, 0x799 }, + [OLYMPUS_LUT_CHAN_583750_IDX] = { 23350, 0x1, 0x81, 0x171C72, 0x79A }, + [OLYMPUS_LUT_CHAN_583875_IDX] = { 23355, 0x1, 0x81, 0x180000, 0x79A }, + [OLYMPUS_LUT_CHAN_584000_IDX] = { 23360, 0x1, 0x81, 0x18E38E, 0x79B }, + [OLYMPUS_LUT_CHAN_584125_IDX] = { 23365, 0x1, 0x81, 0x19C71C, 0x79B }, + [OLYMPUS_LUT_CHAN_584250_IDX] = { 23370, 0x1, 0x81, 0x1AAAAB, 0x79C }, + [OLYMPUS_LUT_CHAN_584375_IDX] = { 23375, 0x1, 0x81, 0x1B8E39, 0x79C }, + [OLYMPUS_LUT_CHAN_584500_IDX] = { 23380, 0x1, 0x81, 0x1C71C7, 0x79C }, + [OLYMPUS_LUT_CHAN_584625_IDX] = { 23385, 0x1, 0x81, 0x1D5555, 0x79D }, + [OLYMPUS_LUT_CHAN_584750_IDX] = { 23390, 0x1, 0x81, 0x1E38E4, 0x79D }, + [OLYMPUS_LUT_CHAN_584875_IDX] = { 23395, 0x1, 0x81, 0x1F1C72, 0x79E }, + [OLYMPUS_LUT_CHAN_585000_IDX] = { 23400, 0x1, 0x82, 0x0, 0x79E }, + [OLYMPUS_LUT_CHAN_585125_IDX] = { 23405, 0x1, 0x82, 0xE38E, 0x79E }, + [OLYMPUS_LUT_CHAN_585250_IDX] = { 23410, 0x1, 0x82, 0x1C71C, 0x79F }, + [OLYMPUS_LUT_CHAN_585375_IDX] = { 23415, 0x1, 0x82, 0x2AAAB, 0x79F }, + [OLYMPUS_LUT_CHAN_585500_IDX] = { 23420, 0x1, 0x82, 0x38E39, 0x7A0 }, + [OLYMPUS_LUT_CHAN_585625_IDX] = { 23425, 0x1, 0x82, 0x471C7, 0x7A0 }, + [OLYMPUS_LUT_CHAN_585750_IDX] = { 23430, 0x1, 0x82, 0x55555, 0x7A1 }, + [OLYMPUS_LUT_CHAN_585875_IDX] = { 23435, 0x1, 0x82, 0x638E4, 0x7A1 }, + [OLYMPUS_LUT_CHAN_586000_IDX] = { 23440, 0x1, 0x82, 0x71C72, 0x7A1 }, + [OLYMPUS_LUT_CHAN_586125_IDX] = { 23445, 0x1, 0x82, 0x80000, 0x7A2 }, + [OLYMPUS_LUT_CHAN_586250_IDX] = { 23450, 0x1, 0x82, 0x8E38E, 0x7A2 }, + [OLYMPUS_LUT_CHAN_586375_IDX] = { 23455, 0x1, 0x82, 0x9C71C, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586500_IDX] = { 23460, 0x1, 0x82, 0xAAAAB, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586625_IDX] = { 23465, 0x1, 0x82, 0xB8E39, 0x7A3 }, + [OLYMPUS_LUT_CHAN_586750_IDX] = { 23470, 0x1, 0x82, 0xC71C7, 0x7A4 }, + [OLYMPUS_LUT_CHAN_586875_IDX] = { 23475, 0x1, 0x82, 0xD5555, 0x7A4 }, + [OLYMPUS_LUT_CHAN_587000_IDX] = { 23480, 0x1, 0x82, 0xE38E4, 0x7A5 }, + [OLYMPUS_LUT_CHAN_587125_IDX] = { 23485, 0x1, 0x82, 0xF1C72, 0x7A5 }, + [OLYMPUS_LUT_CHAN_587250_IDX] = { 23490, 0x1, 0x82, 0x100000, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587375_IDX] = { 23495, 0x1, 0x82, 0x10E38E, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587500_IDX] = { 23500, 0x1, 0x82, 0x11C71C, 0x7A6 }, + [OLYMPUS_LUT_CHAN_587625_IDX] = { 23505, 0x1, 0x82, 0x12AAAB, 0x7A7 }, + [OLYMPUS_LUT_CHAN_587750_IDX] = { 23510, 0x1, 0x82, 0x138E39, 0x7A7 }, + [OLYMPUS_LUT_CHAN_587875_IDX] = { 23515, 0x1, 0x82, 0x1471C7, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588000_IDX] = { 23520, 0x1, 0x82, 0x155555, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588125_IDX] = { 23525, 0x1, 0x82, 0x1638E4, 0x7A8 }, + [OLYMPUS_LUT_CHAN_588250_IDX] = { 23530, 0x1, 0x82, 0x171C72, 0x7A9 }, + [OLYMPUS_LUT_CHAN_588375_IDX] = { 23535, 0x1, 0x82, 0x180000, 0x7A9 }, + [OLYMPUS_LUT_CHAN_588500_IDX] = { 23540, 0x1, 0x82, 0x18E38E, 0x7AA }, + [OLYMPUS_LUT_CHAN_588625_IDX] = { 23545, 0x1, 0x82, 0x19C71C, 0x7AA }, + [OLYMPUS_LUT_CHAN_588750_IDX] = { 23550, 0x1, 0x82, 0x1AAAAB, 0x7AB }, + [OLYMPUS_LUT_CHAN_588875_IDX] = { 23555, 0x1, 0x82, 0x1B8E39, 0x7AB }, + [OLYMPUS_LUT_CHAN_589000_IDX] = { 23560, 0x1, 0x82, 0x1C71C7, 0x7AB }, + [OLYMPUS_LUT_CHAN_589125_IDX] = { 23565, 0x1, 0x82, 0x1D5555, 0x7AC }, + [OLYMPUS_LUT_CHAN_589250_IDX] = { 23570, 0x1, 0x82, 0x1E38E4, 0x7AC }, + [OLYMPUS_LUT_CHAN_589375_IDX] = { 23575, 0x1, 0x82, 0x1F1C72, 0x7AD }, + [OLYMPUS_LUT_CHAN_589500_IDX] = { 23580, 0x1, 0x83, 0x0, 0x7AD }, + [OLYMPUS_LUT_CHAN_589625_IDX] = { 23585, 0x1, 0x83, 0xE38E, 0x7AD }, + [OLYMPUS_LUT_CHAN_589750_IDX] = { 23590, 0x1, 0x83, 0x1C71C, 0x7AE }, + [OLYMPUS_LUT_CHAN_589875_IDX] = { 23595, 0x1, 0x83, 0x2AAAB, 0x7AE }, + [OLYMPUS_LUT_CHAN_590000_IDX] = { 23600, 0x1, 0x83, 0x38E39, 0x7AF }, + [OLYMPUS_LUT_CHAN_590125_IDX] = { 23605, 0x1, 0x83, 0x471C7, 0x7AF }, + [OLYMPUS_LUT_CHAN_590250_IDX] = { 23610, 0x1, 0x83, 0x55555, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590375_IDX] = { 23615, 0x1, 0x83, 0x638E4, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590500_IDX] = { 23620, 0x1, 0x83, 0x71C72, 0x7B0 }, + [OLYMPUS_LUT_CHAN_590625_IDX] = { 23625, 0x1, 0x83, 0x80000, 0x7B1 }, + [OLYMPUS_LUT_CHAN_590750_IDX] = { 23630, 0x1, 0x83, 0x8E38E, 0x7B1 }, + [OLYMPUS_LUT_CHAN_590875_IDX] = { 23635, 0x1, 0x83, 0x9C71C, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591000_IDX] = { 23640, 0x1, 0x83, 0xAAAAB, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591125_IDX] = { 23645, 0x1, 0x83, 0xB8E39, 0x7B2 }, + [OLYMPUS_LUT_CHAN_591250_IDX] = { 23650, 0x1, 0x83, 0xC71C7, 0x7B3 }, + [OLYMPUS_LUT_CHAN_591375_IDX] = { 23655, 0x1, 0x83, 0xD5555, 0x7B3 }, + [OLYMPUS_LUT_CHAN_591500_IDX] = { 23660, 0x1, 0x83, 0xE38E4, 0x7B4 }, + [OLYMPUS_LUT_CHAN_591625_IDX] = { 23665, 0x1, 0x83, 0xF1C72, 0x7B4 }, + [OLYMPUS_LUT_CHAN_591750_IDX] = { 23670, 0x1, 0x83, 0x100000, 0x7B5 }, + [OLYMPUS_LUT_CHAN_591875_IDX] = { 23675, 0x1, 0x83, 0x10E38E, 0x7B5 }, + [OLYMPUS_LUT_CHAN_592000_IDX] = { 23680, 0x1, 0x83, 0x11C71C, 0x7B5 }, + [OLYMPUS_LUT_CHAN_592125_IDX] = { 23685, 0x1, 0x83, 0x12AAAB, 0x7B6 }, + [OLYMPUS_LUT_CHAN_592250_IDX] = { 23690, 0x1, 0x83, 0x138E39, 0x7B6 }, + [OLYMPUS_LUT_CHAN_592375_IDX] = { 23695, 0x1, 0x83, 0x1471C7, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592500_IDX] = { 23700, 0x1, 0x83, 0x155555, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592625_IDX] = { 23705, 0x1, 0x83, 0x1638E4, 0x7B7 }, + [OLYMPUS_LUT_CHAN_592750_IDX] = { 23710, 0x1, 0x83, 0x171C72, 0x7B8 }, + [OLYMPUS_LUT_CHAN_592875_IDX] = { 23715, 0x1, 0x83, 0x180000, 0x7B8 }, + [OLYMPUS_LUT_CHAN_593000_IDX] = { 23720, 0x1, 0x83, 0x18E38E, 0x7B9 }, + [OLYMPUS_LUT_CHAN_593125_IDX] = { 23725, 0x1, 0x83, 0x19C71C, 0x7B9 }, + [OLYMPUS_LUT_CHAN_593250_IDX] = { 23730, 0x1, 0x83, 0x1AAAAB, 0x7BA }, + [OLYMPUS_LUT_CHAN_593375_IDX] = { 23735, 0x1, 0x83, 0x1B8E39, 0x7BA }, + [OLYMPUS_LUT_CHAN_593500_IDX] = { 23740, 0x1, 0x83, 0x1C71C7, 0x7BA }, + [OLYMPUS_LUT_CHAN_593625_IDX] = { 23745, 0x1, 0x83, 0x1D5555, 0x7BB }, + [OLYMPUS_LUT_CHAN_593750_IDX] = { 23750, 0x1, 0x83, 0x1E38E4, 0x7BB }, + [OLYMPUS_LUT_CHAN_593875_IDX] = { 23755, 0x1, 0x83, 0x1F1C72, 0x7BC }, + [OLYMPUS_LUT_CHAN_594000_IDX] = { 23760, 0x1, 0x84, 0x0, 0x7BC }, + [OLYMPUS_LUT_CHAN_594125_IDX] = { 23765, 0x1, 0x84, 0xE38E, 0x7BC }, + [OLYMPUS_LUT_CHAN_594250_IDX] = { 23770, 0x1, 0x84, 0x1C71C, 0x7BD }, + [OLYMPUS_LUT_CHAN_594375_IDX] = { 23775, 0x1, 0x84, 0x2AAAB, 0x7BD }, + [OLYMPUS_LUT_CHAN_594500_IDX] = { 23780, 0x1, 0x84, 0x38E39, 0x7BE }, + [OLYMPUS_LUT_CHAN_594625_IDX] = { 23785, 0x1, 0x84, 0x471C7, 0x7BE }, + [OLYMPUS_LUT_CHAN_594750_IDX] = { 23790, 0x1, 0x84, 0x55555, 0x7BF }, + [OLYMPUS_LUT_CHAN_594875_IDX] = { 23795, 0x1, 0x84, 0x638E4, 0x7BF }, + [OLYMPUS_LUT_CHAN_595000_IDX] = { 23800, 0x1, 0x84, 0x71C72, 0x7BF } +}; From patchwork Thu Jun 17 16:00:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/power_cli.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/power_cli.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/power_cli.h b/drivers/net/wireless/celeno/cl8k/power_cli.h new file mode 100644 index 000000000000..c88e34a249da --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/power_cli.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_POWER_CLI_H +#define CL_POWER_CLI_H + +#include "vendor_cmd.h" +#include "hw.h" + +int cl_power_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_POWER_CLI_H */ From patchwork Thu Jun 17 16:00:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADCA1C2B9F4 for ; Thu, 17 Jun 2021 16:07:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A24660FDB for ; Thu, 17 Jun 2021 16:07:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232614AbhFQQJp (ORCPT ); Thu, 17 Jun 2021 12:09:45 -0400 Received: from mail-eopbgr140087.outbound.protection.outlook.com ([40.107.14.87]:56046 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231597AbhFQQIa (ORCPT ); Thu, 17 Jun 2021 12:08:30 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jc9TPYgpl3U9ar8LbmmbfaB/FBB9q18DXlQBAYgKaa4x+6vFjoIxh+m3QOiiMtPZOOBcdpOITJsY6ZW1r0DGK5gqMmFLGw4N90RBv12DvYsFcoF/9kry5kyYorhux9+2kvyS4dbLPBJtpAQEeW+caFyRvbCHf6mHuM5jgCPFunO0ezgE9wzCy6aBDefC3Llh1t5fJWPdGDZnSq17U5hdzfvceOITg/S0E7hBuHZbVfwY0oHYfYGCIM7d34cSwFWHTUByLdEeW/MNGxyMIuyr77Iw8Mkm3NjYCGn5mlWzfa376cdDBJfk3H/O/eL7JgfmOXJ1n3gKs0ygvsOgvWiKwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H5rGKCTLV4IQb4W1VaMIuLYr3gioe+/21zdjrN8y1Uo=; b=PpwZt9qVGEYsWW0I0Z0+VwQJM/pbt+E+ozQaBqB3fSk9wasGAWyOj50wDiuO1HhEPfTbnzp64vVJJt0JZnlz+BjsxU/uP3wf71T7+IyOUMidZsHDzZuwAO+sA5MEZYsx6nGoFSXd4u3sZsaTWvM6qO11VOEArB5WBIixVKBFq3zUSUQIPZEk4eCRVdPo/TMpntnhdcWEEl7XENeYauqzJsQTWz4USmCLATearBaAwFpQjkcESqUDL2FcMMn9qQbj/uRRogNpcQcY+HmuLWtV+GilZTuXOrwqwmIUoH2o9DcDzy8pnDWVECbYhnDJSl1g+XcGhQcE753cF97N/183Yg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H5rGKCTLV4IQb4W1VaMIuLYr3gioe+/21zdjrN8y1Uo=; b=bEVkF/iXiOiXa3AmphO0dwlnYDxXVgkM/836LETIwNjfR0C0ezc00JhGjwnw18aJkXV1MEI9yvcq1PHVFjASShA5y+BKAjFMExpZlzVY4jFxBNSdg9/foYxZAm0ieuJgutetAH+YfyG6K7rq3fFRlbVteeiMf0dGj1xkwWWdbpI= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM8P192MB1059.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1e3::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18; Thu, 17 Jun 2021 16:05:49 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:05:48 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 137/256] cl8k: add power_table.c Date: Thu, 17 Jun 2021 16:00:24 +0000 Message-Id: <20210617160223.160998-138-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:04 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0fa7d554-ccc9-4d6f-6bf2-08d931a9abdf X-MS-TrafficTypeDiagnostic: AM8P192MB1059: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nqiGI2ENGOgqTCzZUJ3UHitQJdi4LspUUXDXtVSSWKHvokNkn57BO/4aFilKtlGzLpKOdfWlzwbZUSIOSnoC1+UBjTH1+A7HWLbZk6rO9wCq8Y1zkjle51pEKjCAbk800Lb3VewcU4ZLtOG2jfWfmenncEk6RbVg7AExVI9OXwNNWlJwmfoEX99j/r6BWs6pXL68eFNIMMZyX0M/wADbRmR6dd9Ba3mCjMmVbIcs+255sJvH2RcOxCpceVCyhJBgAriqlkFAdf/d/GRtOf6QcsZKo9x9tci49iA0maHCsLKmPX9PXGSEBUW8AS+O2IAr+4EtkcCtjTbpmWogXF1viRsdsclh35raLRw7pvr6UAS9purwQne47i0vobbB/55FsofzxBmLkuF2PBghvZmfrhJ1TCvk+FhVPB6pChjuUQ6WLUT8UiNPRJ/iUXTjTb6GGJvHlg2XglSIBJlSmukUj7DEpjrfKgEMu+XOQFXfe4GFQ1wEe9cbpmfILWUCoAamGxffl3Bxj0jLFpUHHlEzkIkFsQbk1icOn8POUJE6Jwq/bDzPl4Jn7zIxTuySJgEXjF/oHkxAjcZ7keZcGou6puzGRv+bR7G8HYp8CWbNP1Yx4q81ZhRpsNvlR5TwPimGBVc04I0RbkjR+eS55kqggeUJ1SDf7How8tvTg53GL4QsVxXHZ52v65QE3UZMSV6Bnkf/PQ5f0ZXP2XY+iMteaA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(26005)(956004)(498600001)(186003)(66556008)(16526019)(107886003)(66946007)(66476007)(8936002)(6916009)(2616005)(1076003)(2906002)(54906003)(6506007)(6666004)(4326008)(38100700002)(38350700002)(83380400001)(9686003)(6512007)(5660300002)(6486002)(86362001)(55236004)(36756003)(30864003)(52116002)(8676002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3LtRPNPUuTtzTWMBQ3eCs7PC1am8YtmZl72yQWLSIZQl4ZiiaO0wvds3a4rXgnlzsVF5H6TKr2ZKvXHWgAR8GGSnrUj1cWGyVgcUxy+q1tlw8iaPHn/7ZH6gO3c7sqHfLuMj4MuSvIvI/5mcKD42OcI297hscXMZhNETuZj/WyKqIQOralfCu1NQQ9ePT7iNbcmztia8hnvmBjxlum14zAHk08Uq/DtCeKoSnUH2OpdescfcbOeETvsmbZoYKkrziwsVAhWOCsXFzxm+wkP+jfTpVZCf5rXYLGRp37T2XzBI8W+2NV34rTEMTvHrEkicYl4X2W2lCtWZrLabNu6BaQD+oHKKPQSEF47sQed972Ry4TKbLXmGqxAvcqzdPiR8J0vM1cNNmn/40rCzwQDALAW3fDv1/nlXQSFntaIE6OAo7/Quec/qALzZ0PI+lXbKdaAfBChGQYHRTIvfGnU8iUMU276j/c3PVm1scqdo4fVYcCQhGMkzjzXRi+aayRLAz5FoywbKMcOghL4Cy9ezMAxnL2vgQX40OvrFpIlKLSGMQnVg/hf2rwzN4bZtlvZk9aAkh7BejPkFkfpyyVb9yD4Bf0Vl10IHHTNJH+0la5ZiePYwfCUflYeuP/mqyKRV+ofbzJ0demP7F4qWyC9Wki7A4CPeNKz0ObXFgFGNrp6z7ivIIqOfr32KH2uTjyntJH0Fs7z3VcAQ18dhdYr1HsJ1kPrqoucCkYA7r7U7TiqWq9HzwFrgke4HpHQSzA8bfK4R8pHv89iF0uT6I9t/UJyK91vej6B3jDm6dk3ZOSVwGRfPnab/JW9pzTiHK0rCU7BvFG4R4g9sXr3kcJcP4MPuAd2jVPWYLI8QEmMLPH+vKvs9D7LKCbnJkGvdSK0DZdti0WpA/rGm75WVujLSFXtuLKDBj6U6svhSlBUuJdrUFi6PUOShe1Wq7SvOccGyDoKODh67kOcyz+9A/Thap033aBlM8MKwsZoQETELAq66fW+c47tmhX6ppSdzNONXGO30UwLRrPxxv93X9tB184atGjcO4dO7feVHNJkedCiAE9a6NRYcQRMiqKj4X+2fDpUyuElqDK/ww6fF/PAV0qYCtamIqN49K8tyviuBhGKO1AyWd139EJUgtx0JC+YFqNuOucptWM5ydA/wYZNm0eTKYimoEYjkWqjcZTUqV9zJnOJ3MyBgtcqs3F4KzLJg9Dwg1msdU+ERw2pXk1odmL9xZznRBoAXGuvo5mc/o47lvwstIDhyaam4m1Apk2Y9Qx0a+dFdA2ptuDDzWJCsnFyaxgVEISVXDCloTd3QLUdvRSdgL9K8WNq7AJ2F+9VO X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0fa7d554-ccc9-4d6f-6bf2-08d931a9abdf X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:05.4168 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: F4Af5ttZNCBdWi+tAEhzsY615OzuAQiVMscElAdQitkJ/6okeV6brx4n0z3P9O4ADnpyL3fcO67gJzyl7X2r5g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1059 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/power_table.c | 218 ++++++++++++++++++ 1 file changed, 218 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/power_table.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/power_table.c b/drivers/net/wireless/celeno/cl8k/power_table.c new file mode 100644 index 000000000000..27cbe5596af0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/power_table.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "power_table.h" +#include "chip.h" +#include "e2p.h" +#include "debug.h" +#include "band.h" + +/* + * How to fill power table: + * Set 81 values in the range of 100 - 180 according to the Excel file. + * 100 corresponds to power of -10dBm (Pout Ant). + * 180 corresponds to power of +30dBm (Pout Ant). + * All values between 0 - 99 should be same as the value of 100. + * All values between 181 - 255 should be same as the value of 180. + */ + +static const u8 power_to_powerword_conv_table_id_0[NUM_POWER_WORDS] = { + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 0 - 7 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 8 - 15 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 16 - 23 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 24 - 31 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 32 - 39 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 40 - 47 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 48 - 55 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 56 - 63 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 64 - 71 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 72 - 79 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 80 - 87 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 88 - 95 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x10, 0x11, /* 96 - 103 */ + 0x12, 0x13, 0x14, 0x40, 0x41, 0x42, 0x43, 0x44, /* 104 - 111 */ + 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, /* 112 - 119 */ + 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, /* 120 - 127 */ + 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, /* 128 - 135 */ + 0x5D, 0x5E, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, /* 136 - 143 */ + 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, /* 144 - 151 */ + 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, /* 152 - 159 */ + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, /* 160 - 167 */ + 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xF9, 0xFA, 0xFB, /* 168 - 175 */ + 0xFC, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 176 - 183 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 184 - 191 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 192 - 199 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 200 - 207 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 208 - 215 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 216 - 223 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 224 - 231 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 232 - 239 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, /* 240 - 247 */ + 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD /* 248 - 255 */ +}; + +static const u8 power_to_powerword_conv_table_id_1[NUM_POWER_WORDS] = { + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 0 - 7 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 8 - 15 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 16 - 23 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 24 - 31 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 32 - 39 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 40 - 47 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 48 - 55 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 56 - 63 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 64 - 71 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 72 - 79 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 80 - 87 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, /* 88 - 95 */ + 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x05, 0x06, /* 96 - 103 */ + 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, /* 104 - 111 */ + 0x0F, 0x10, 0x11, 0x12, 0x40, 0x41, 0x42, 0x43, /* 112 - 119 */ + 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, /* 120 - 127 */ + 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, /* 128 - 135 */ + 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, /* 136 - 143 */ + 0x5C, 0x5D, 0x5E, 0x60, 0x61, 0x62, 0x63, 0x64, /* 144 - 151 */ + 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, /* 152 - 159 */ + 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, /* 160 - 167 */ + 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, /* 168 - 175 */ + 0x7D, 0xB9, 0xBA, 0xBB, 0xBC, 0xBC, 0xBC, 0xBC, /* 176 - 183 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 184 - 191 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 192 - 199 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 200 - 207 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 208 - 215 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 216 - 223 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 224 - 231 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 232 - 239 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, /* 240 - 247 */ + 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC /* 248 - 255 */ +}; + +static const u8 power_to_powerword_conv_table_id_2[NUM_POWER_WORDS] = { + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 0 - 7 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 8 - 15 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 16 - 23 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 24 - 31 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 32 - 39 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 40 - 47 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 48 - 55 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 56 - 63 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 64 - 71 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 72 - 79 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 80 - 87 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, /* 88 - 95 */ + 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x10, 0x11, /* 96 - 103 */ + 0x12, 0x13, 0x14, 0x40, 0x41, 0x42, 0x43, 0x44, /* 104 - 111 */ + 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, /* 112 - 119 */ + 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, /* 120 - 127 */ + 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, /* 128 - 135 */ + 0x5D, 0x5E, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, /* 136 - 143 */ + 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, /* 144 - 151 */ + 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, /* 152 - 159 */ + 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, /* 160 - 167 */ + 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBD, 0xBD, 0xBD, /* 168 - 175 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 176 - 183 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 184 - 191 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 192 - 199 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 200 - 207 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 208 - 215 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 216 - 223 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 224 - 231 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 232 - 239 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, /* 240 - 247 */ + 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD /* 248 - 255 */ +}; + +static u8 cl_power_table_read(struct cl_hw *cl_hw) +{ + u8 pwr_table_id = 0; + + if (cl_e2p_read(cl_hw->chip, &pwr_table_id, 1, ADDR_GEN_PWR_TABLE_ID + cl_hw->tcv_idx)) + return U8_MAX; + + return pwr_table_id; +} + +static int cl_power_table_fill(struct cl_hw *cl_hw) +{ + u8 pwr_table_id = cl_power_table_read(cl_hw); + + switch (pwr_table_id) { + case 0: + if (cl_band_is_5g(cl_hw)) { + memcpy(cl_hw->power_table_info.data->conv_table, + power_to_powerword_conv_table_id_0, NUM_POWER_WORDS); + cl_hw->tx_power_version = 5; + } else { + CL_DBG_ERROR(cl_hw, "Power table ID (%u) is valid for 5g only\n", + pwr_table_id); + + if (!cl_hw->chip->conf->ce_production_mode) + return -1; + } + break; + case 1: + if (cl_band_is_24g(cl_hw)) { + memcpy(cl_hw->power_table_info.data->conv_table, + power_to_powerword_conv_table_id_1, NUM_POWER_WORDS); + cl_hw->tx_power_version = 25; + } else { + CL_DBG_ERROR(cl_hw, "Power table ID (%u) is valid for 2.4g only\n", + pwr_table_id); + + if (!cl_hw->chip->conf->ce_production_mode) + return -1; + } + break; + case 2: + if (cl_band_is_6g(cl_hw)) { + memcpy(cl_hw->power_table_info.data->conv_table, + power_to_powerword_conv_table_id_2, NUM_POWER_WORDS); + cl_hw->tx_power_version = 1; + } else { + CL_DBG_ERROR(cl_hw, "Power table ID (%u) is valid for 6g only\n", + pwr_table_id); + + if (!cl_hw->chip->conf->ce_production_mode) + return -1; + } + break; + default: + CL_DBG_ERROR(cl_hw, "Power table ID is not configured in EEPROM\n"); + + if (!cl_hw->chip->conf->ce_production_mode) + return -1; + } + + cl_dbg_verbose(cl_hw, "Power table ID %u (V%u)\n", pwr_table_id, cl_hw->tx_power_version); + + return 0; +} + +int cl_power_table_alloc(struct cl_hw *cl_hw) +{ + struct cl_power_table_data *buf = NULL; + u32 len = sizeof(struct cl_power_table_data); + dma_addr_t phys_dma_addr; + + buf = dma_alloc_coherent(cl_hw->chip->dev, len, &phys_dma_addr, GFP_KERNEL); + + if (!buf) + return -1; + + cl_hw->power_table_info.data = buf; + cl_hw->power_table_info.dma_addr = cpu_to_le32(phys_dma_addr); + + return cl_power_table_fill(cl_hw); +} + +void cl_power_table_free(struct cl_hw *cl_hw) +{ + struct cl_power_table_info *power_table_info = &cl_hw->power_table_info; + u32 len = sizeof(struct cl_power_table_data); + dma_addr_t phys_dma_addr = le32_to_cpu(power_table_info->dma_addr); + + if (!power_table_info->data) + return; + + dma_free_coherent(cl_hw->chip->dev, len, (void *)power_table_info->data, phys_dma_addr); + power_table_info->data = NULL; +} From patchwork Thu Jun 17 16:00:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3857BC49EB7 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/rate_ctrl.h | 106 +++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/rate_ctrl.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/rate_ctrl.h b/drivers/net/wireless/celeno/cl8k/rate_ctrl.h new file mode 100644 index 000000000000..181f6e31ca00 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/rate_ctrl.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_RATE_CTRL_H +#define CL_RATE_CTRL_H + +#include +#include "ipc_shared.h" + +#define RATE_CTRL_OFFSET_OFDM 4 +#define RATE_CNTRL_HE_SPATIAL_CONF_DEF 0xF + +/* Op_mode field in mm_update_rate_dl_req structure */ +enum cl_op_mode { + RATE_OP_MODE_FIXED, + RATE_OP_MODE_DEFAULT_HE, + RATE_OP_MODE_DEFAULT_OFDM, + RATE_OP_MODE_DEFAULT_CCK, + RATE_OP_MODE_STA_SU, + RATE_OP_MODE_STA_MU, + RATE_OP_MODE_MCAST, + RATE_OP_MODE_BCAST +}; + +/* Value to be set in tx_host_info */ +enum cl_rate_ctrl_entry { + RATE_CTRL_ENTRY_NA = 0, + + RATE_CTRL_ENTRY_STA, + RATE_CTRL_ENTRY_FIXED_RATE, + RATE_CTRL_ENTRY_MIN_HE, + RATE_CTRL_ENTRY_MIN_OFDM, + RATE_CTRL_ENTRY_MIN_CCK, + RATE_CTRL_ENTRY_MCAST, + RATE_CTRL_ENTRY_BCAST, + + /* Entry size in firmware is represented by 3 bits */ + RATE_CTRL_ENTRY_MAX = 8 +}; + +/* + * sw_ctrl includes eights bits (16 - 23) to be used by software. + * Bit 16 is used by driver to indicate tx_bf. + * Bit 17 is used by driver to indicate fallback. + * Bit 18 - 23 are still free. + */ +struct cl_rate_ctrl_info_fields { + u32 mcs_index : 7; /* [6:0] */ + u32 bw : 2; /* [8:7] */ + u32 gi : 2; /* [10:9] */ + u32 pre_type_or_stbc : 1; /* [11] */ + u32 format_mod : 4; /* [15:12] */ + u32 tx_bf : 1; /* [16] */ + u32 fallback : 1; /* [17] */ + u32 sw_ctrl : 6; /* [23:18] */ + u32 tx_chains : 8; /* [31:24] */ +}; + +union cl_rate_ctrl_info { + struct cl_rate_ctrl_info_fields field; + u32 word; +}; + +struct cl_rate_ctrl_info_he_fields { + u32 spatial_conf : 4; /* [3:0] */ + u32 starting_sts : 3; /* [6:4] */ + u32 ru_index : 6; /* [12:7] */ + u32 ru_type : 3; /* [15:13] */ + u32 ru_band : 1; /* [16] */ + u32 mu_usr_pos : 2; /* [18:17] */ + u32 dcm_data : 1; /* [19] */ + u32 num_usrs_mu_dl : 4; /* [23:20] */ + u32 ru_alloc : 8; /* [31:24] */ +}; + +union cl_rate_ctrl_info_he { + struct cl_rate_ctrl_info_he_fields field; + u32 word; +}; + +struct cl_hw; +struct cl_sta; +struct cl_sw_txhdr; + +u32 cl_rate_ctrl_generate(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + u8 mode, u8 bw, u8 nss, u8 mcs, u8 gi, + bool fallback_en); +void cl_rate_ctrl_convert(union cl_rate_ctrl_info *rate_ctrl_info); +void cl_rate_ctrl_parse(union cl_rate_ctrl_info *rate_ctrl_info, u8 *nss, u8 *mcs); + +void cl_rate_ctrl_set_default(struct cl_hw *cl_hw); + +void cl_rate_ctrl_set_default_per_he_minrate(struct cl_hw *cl_hw, u8 bw, + u8 nss, u8 mcs, u8 gi); +bool cl_rate_ctrl_set_mcast(struct cl_hw *cl_hw, u8 mode, u8 mcs); +bool cl_rate_ctrl_set_fixed(struct cl_hw *cl_hw, u32 rate_ctrl_he, u8 mode, u8 mcs, u8 nss, + u8 bw, u8 gi, u8 ltf_field); +bool cl_rate_ctrl_set_dbgfs(struct cl_hw *cl_hw, u8 sta_idx, u32 rate_ctrl, u32 rate_ctrl_he, + u8 op_mode, u8 bw, u8 ltf_field); +void cl_rate_ctrl_set_ate_agg(struct cl_hw *cl_hw, struct cl_sta *cl_sta); + +void cl_rate_ctrl_update_desc_single(struct cl_hw *cl_hw, struct tx_host_info *info, + struct cl_sw_txhdr *sw_txhdr); +void cl_rate_ctrl_update_desc_agg(struct cl_hw *cl_hw, struct tx_host_info *info); + +#endif /* CL_RATE_CTRL_H */ From patchwork Thu Jun 17 16:00:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7189DC49EA2 for ; Thu, 17 Jun 2021 16:08:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B6DF61407 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 148/256] cl8k: add reg/reg_access.h Date: Thu, 17 Jun 2021 16:00:35 +0000 Message-Id: <20210617160223.160998-149-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:16 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aa166848-80fd-40d4-716c-08d931a9b2e8 X-MS-TrafficTypeDiagnostic: AM8P192MB1059: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q6glUc1iQPpmbQIObQsEpABgjdRkAHDx+S2rUn+ApvCt0yCyvd9yk878RvY2ti+SdkPvSi78o2i0Wt8h1loo/a8rpCBwsExYrCP3buIh3Xm3S75gOXaHdeDkGPaW+FtjKx4xA99JhjOwXY7eGOqBSzKr3yJG9mc7uSr4a5YiwQWDLufRbSo9ARZkFhMGyNoAOlx055d/A12iLljiREeycM9jIdMfX2amBOdoqiiXwn2hSGvcmGWJYK9mBPmWUYjJeD9S2gpIlbt3YwEi1dxiExTDRr2gqfHjyXBAMUgRbm3LLBH9vb+nmK6Zs7DGP06HukjoqUPpxWb5IsfZSJKeQHR80P6nz1zve+4AHnP+Os3HJqpbhl1l2+idKfjvrk+ScE6X4G17PsUsDhVLLqbL+lamkLr1UC78fVWdJJfMFPQ+PUTkzlnENx4B4BQAAconvk2lsqLypybro608N/HazO0jgLjn243VaMRZVSNKXBoGJJFRKewtfjzDfHarNdOFgjhIGcPxngOzlOLCcJkxjCDinbrk01YKdf141oGHzV8FH6uWh6LatJjEBQ+6DF0ySnyuwdUap131P31ilPkv+vwgJ8gxmThvoQnDSnfdz6PM7I+pimn8hDEv0vabmb7xhaPZpq3+sK39WnOP57bPRMVXCwQ1131H2GfJ9JSSwser2vTniiEltoWDIvS0gyhrCs7hH/wf/Hgop8bCp6aMVA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(346002)(136003)(376002)(396003)(366004)(26005)(956004)(478600001)(186003)(66556008)(16526019)(107886003)(66946007)(66476007)(8936002)(6916009)(2616005)(1076003)(2906002)(54906003)(6506007)(6666004)(4326008)(38100700002)(38350700002)(83380400001)(9686003)(6512007)(5660300002)(6486002)(86362001)(316002)(55236004)(36756003)(52116002)(8676002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mQTCz2HXJwMA0SjqBNHFVPJNi3UsYbSRW+3X2rTF4frFZyBZ3/I0UG9cxzTkEbt6UXfKmEIIGYSI5NI44Kvz8F7/z8hu9qBcDQeXcPrZBPDqfKWgVVeVRb91NL7hRu6NZZoQPiob+l1TDzDyP2jSMXwrLXAnZzASitLDfrtlKpcBnIvofZ+x84EdQnGMYn+SIGuQYZLgDaZiVNnHhH9Yw8X4vwWVDGu9tUGzayBh/PX31K3b6qSQX9kkPV9wLeDXiq1kMJ+fxxuNdmck9BuWAuPzxBMB7SUjUbuNMHDbbfD/cgyscaxVqcNvXJS3dudr4mpP4k4bD6CvNvqfCYSecQdtPLx6WeajR85BKCNmCVFxHuYnFCGhc4H1Hw7660u1IQPw2Lb6B8KoqnySj3WbV+WITU4d5UGJ+Fxk2mNnbQgp9dguuKx9wdff+5heI/lfIl7VbeDwlkKyffA+4wRmNrVoi98b6G7EXv14qtwU82YDCTYshpNMGl+SA2QWaqZH/Tah68xYX4rkboIfSWih3VDNpzNWNfPMtKvV6sHcFTstXdwECNPgx6QLDDBci2q3Htr7HG59li7OUyzbeTJaRGbYq9wRTRuJok7kbROG0LA0siVLtyvIzD0gYtI8bAh9mMx+0HCG2P5eIw/YOnTT/Yi7FqUDHfQzS7NeK6PZ1i7eEgl1F9NKjlJHCY77IdpjS7+Oe7pLGbF6f/AKm9IzDIs93LOre8cIEdFq4C6FtsD0qGFoDLIoDCtPg7sie2s0m+6VttnXltXJuqu21T70dVBEvqVRZ4n2qle+R4xh78g8BFTSAizNujA/zPT/YDoIj5Gwy+E7sVAR+HYoXv8+LXYml88AQZRDItieMpN711tFQZzNraTK5skYjmnyEPrqKqDkiu/rCvcxSRRUvhLU/oPmBA9NfbKUdMGpAqOfCISc+miy7VBN1p4hWNAxvObiz+04w6bcXRzegPhrhavMgYt5OCNnUNxxcBRSSjAMUMNprmHUEi7KQgwLJHR3rA8fH5dvRR/2PwSDvLiHq2ziV4BuhWYpWdbj+wEMLQPdHlGEnDFJLSOz6oqIERhH87rtGg0Y2QcK14vFgg2p+Ss0hNUxrCZ4ILH7S90ExnRUFvaT1gH7TwAZ2/UuQ3ZwaiV7hfM769j5YiIACUNMxzHuhFbiA105QP5zzIfUnH3etbuLOyQYOtJx+coSKV5BUQ83HnXLFqoFRNCOvvKjWrPTRoXZTz7kYg9zbkdmn6QwVSW9LO5cSy9I+itts2UGrywMl0RXzyKk+mZJ4KuAbE8AlQwjNieBru4j9aABPzfIzNmtfA4HABtZeaaLSnDUNxzJ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: aa166848-80fd-40d4-716c-08d931a9b2e8 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:17.1921 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZHPlwhRQ8dRTKRLgz41tzt9+jIc28U/lIuwSR5AwCi0hGY28NTgpKbdKYSkW9RwcMMKIrpffIEXThgaGVW2noA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1059 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/reg/reg_access.h | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_access.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_access.h b/drivers/net/wireless/celeno/cl8k/reg/reg_access.h new file mode 100644 index 000000000000..337f6f809d35 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_access.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_ACCESS_H +#define CL_REG_ACCESS_H + +#include "hw.h" +#include "chip.h" +#include "ceva.h" +#include "fw/msg_tx.h" + +#define CL_REG_DBG(...) \ + do { \ + if (cl_hw->reg_dbg) \ + cl_dbg_verbose(__VA_ARGS__); \ + } while (0) + +#define CL_REG_DBG_CHIP(...) \ + do { \ + if (chip->reg_dbg) \ + cl_dbg_chip_verbose(__VA_ARGS__); \ + } while (0) + +#define XTENSA_PIF_BASE_ADDR 0x60000000 + +/* + * SHARED_RAM Address. + * Actually the PCI BAR4 window will be configured such as SHARED RAM + * is accessed with offset 0 (within the AHB Bridge main window) + */ +#define SHARED_RAM_START_ADDR 0x00000000 + +#define REG_MAC_HW_SMAC_OFFSET 0x80000 +#define REG_PHY_SMAC_OFFSET 0x100000 + +#define REG_MACDSP_API_BASE_ADDR 0x00400000 +#define REG_MAC_HW_BASE_ADDR 0x00600000 +#define REG_RIU_BASE_ADDR 0x00486000 +#define REG_RICU_BASE_ADDR 0x004B4000 + +#define APB_REGS_BASE_ADDR 0x007C0000 +#define I2C_REG_BASE_ADDR (APB_REGS_BASE_ADDR + 0x3000) +#define IPC_REG_BASE_ADDR (APB_REGS_BASE_ADDR + 0x4000) + +/* MACSYS_GCU_XT_CONTROL fields */ +#define SMAC_DEBUG_ENABLE BIT(21) +#define SMAC_BREAKPOINT BIT(20) +#define SMAC_OCD_HALT_ON_RESET BIT(19) +#define SMAC_RUN_STALL BIT(18) +#define SMAC_DRESET BIT(17) +#define SMAC_BRESET BIT(16) +#define UMAC_DEBUG_ENABLE BIT(13) +#define UMAC_BREAKPOINT BIT(11) +#define UMAC_OCD_HALT_ON_RESET BIT(11) +#define UMAC_RUN_STALL BIT(10) +#define UMAC_DRESET BIT(9) +#define UMAC_BRESET BIT(8) +#define LMAC_DEBUG_ENABLE BIT(5) +#define LMAC_BREAKPOINT BIT(4) +#define LMAC_OCD_HALT_ON_RESET BIT(3) +#define LMAC_RUN_STALL BIT(2) +#define LMAC_DRESET BIT(1) +#define LMAC_BRESET BIT(0) + +#define XMAC_BRESET \ + (LMAC_BRESET | SMAC_BRESET | UMAC_BRESET) +#define XMAC_DRESET \ + (LMAC_DRESET | SMAC_DRESET | UMAC_DRESET) +#define XMAC_RUN_STALL \ + (LMAC_RUN_STALL | SMAC_RUN_STALL | UMAC_RUN_STALL) +#define XMAC_OCD_HALT_ON_RESET \ + (LMAC_OCD_HALT_ON_RESET | SMAC_OCD_HALT_ON_RESET | UMAC_OCD_HALT_ON_RESET) +#define XMAC_DEBUG_ENABLE \ + (LMAC_DEBUG_ENABLE | SMAC_DEBUG_ENABLE | UMAC_DEBUG_ENABLE) + +/* Macro to read a platform register */ +#define REG_PL_RD(addr) le32_to_cpu(*(volatile __le32 *)(addr)) + +/* Macro to write a platform register */ +#define REG_PL_WR(addr, value) ((*(volatile __le32 *)(addr)) = cpu_to_le32(value)) + +#define CL_BAR_REG_READ(chip, reg) \ + le32_to_cpu((__force __le32)readl((chip)->pci_bar0_virt_addr + (reg))) + +#define CL_BAR_REG_WRITE(chip, reg, val) \ + writel((__force u32)cpu_to_le32(val), (chip)->pci_bar0_virt_addr + (reg)) + +static inline u32 get_actual_reg(struct cl_hw *cl_hw, u32 reg) +{ + if ((reg & 0x00ff0000) == REG_MAC_HW_BASE_ADDR) + return cl_hw->mac_hw_regs_offset + reg; + + if ((reg & 0x00f00000) == REG_MACDSP_API_BASE_ADDR) + return cl_hw->phy_regs_offset + reg; + + return reg; +} + +static inline u32 cl_reg_read(struct cl_hw *cl_hw, u32 reg) +{ + u32 actual_reg = get_actual_reg(cl_hw, reg); + u32 val = 0; + + if (actual_reg == (u32)(-1)) + return 0xff; + + val = REG_PL_RD(cl_hw->chip->pci_bar0_virt_addr + actual_reg); + CL_REG_DBG(cl_hw, "reg=0x%x, val=0x%x\n", actual_reg, val); + return val; +} + +static inline void cl_reg_write_direct(struct cl_hw *cl_hw, u32 reg, u32 val) +{ + u32 actual_reg = get_actual_reg(cl_hw, reg); + + if (actual_reg == (u32)(-1)) + return; + + CL_REG_DBG(cl_hw, "reg=0x%x, val=0x%x\n", actual_reg, val); + REG_PL_WR(cl_hw->chip->pci_bar0_virt_addr + actual_reg, val); +} + +#define BASE_ADDR(reg) ((ptrdiff_t)(reg) & 0x00fff000) + +static inline bool should_send_msg(struct cl_hw *cl_hw, u32 reg) +{ + /* + * Check in what cases we should send a message to the firmware, + * and in what cases we should write directly. + */ + if (!cl_hw->fw_active) + return false; + + return ((BASE_ADDR(reg) == REG_RIU_BASE_ADDR) || + (BASE_ADDR(reg) == REG_MAC_HW_BASE_ADDR)); +} + +static inline int cl_reg_write(struct cl_hw *cl_hw, u32 reg, u32 val) +{ + u32 actual_reg = get_actual_reg(cl_hw, reg); + int ret = 0; + + if (actual_reg == (u32)(-1)) + return -1; + + if (should_send_msg(cl_hw, reg)) { + CL_REG_DBG(cl_hw, "calling cl_msg_tx_reg_write: reg=0x%x, val=0x%x\n", + actual_reg, val); + cl_msg_tx_reg_write(cl_hw, (XTENSA_PIF_BASE_ADDR + actual_reg), val, U32_MAX); + } else { + CL_REG_DBG(cl_hw, "reg=0x%x, val=0x%x\n", actual_reg, val); + REG_PL_WR((cl_hw->chip->pci_bar0_virt_addr + actual_reg), val); + } + + return ret; +} + +static inline int cl_reg_write_mask(struct cl_hw *cl_hw, u32 reg, u32 val, u32 mask) +{ + u32 actual_reg = get_actual_reg(cl_hw, reg); + int ret = 0; + + if (actual_reg == (u32)(-1)) + return -1; + + if (should_send_msg(cl_hw, reg)) { + CL_REG_DBG(cl_hw, "calling cl_msg_tx_reg_write: reg=0x%x, val=0x%x, mask=0x%x\n", + actual_reg, val, mask); + cl_msg_tx_reg_write(cl_hw, (XTENSA_PIF_BASE_ADDR + actual_reg), val, mask); + } else { + u32 reg_rd = REG_PL_RD(cl_hw->chip->pci_bar0_virt_addr + actual_reg); + u32 val_write = ((reg_rd & ~mask) | (val & mask)); + + CL_REG_DBG(cl_hw, "reg=0x%x, mask=0x%x, val=0x%x\n", actual_reg, mask, val_write); + REG_PL_WR(cl_hw->chip->pci_bar0_virt_addr + actual_reg, val_write); + } + + return ret; +} + +static inline void cl_reg_write_chip(struct cl_chip *chip, u32 reg, u32 val) +{ + CL_REG_DBG_CHIP(chip, "reg=0x%x, val=0x%x\n", reg, val); + REG_PL_WR(chip->pci_bar0_virt_addr + reg, val); +} + +static inline u32 cl_reg_read_chip(struct cl_chip *chip, u32 reg) +{ + u32 val = 0; + + val = REG_PL_RD(chip->pci_bar0_virt_addr + reg); + + CL_REG_DBG_CHIP(chip, "reg=0x%x, val=0x%x\n", reg, val); + return val; +} + +#endif /* CL_REG_ACCESS_H */ From patchwork Thu Jun 17 16:00:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42617C2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 150/256] cl8k: add reg/reg_cli.h Date: Thu, 17 Jun 2021 16:00:37 +0000 Message-Id: <20210617160223.160998-151-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:18 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f86ed40b-b57d-446a-0ec4-08d931a9b41e X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VmtmDtzi4V2i1z6KudjF3G4BuGs41Q43bq00YjfZuzPWaIta5ZZnQd05Be1v9fDEL3QD+xs3Y0B5AvaC+jE2XLljro5SqjianpPfk1Jo/bFyk+EoswAqqseR55FBzTRHkGzuJBkNoultY1vDiuSzr0Px2UPdiWh+5ua1yJZkTO9t9sG2fgakGSahmbpveEgM5AMp59uv6/s/mbGoV0D08JDxFsMyakHKxJR85B1j6EO81bas1f2D5ijlChQZ4Js4OT1pbXE+0As0DABl0wMa7NQQSXKL1XRY50VgNoinsfwxvrgEhv3LWJe/bSssgcNn2bdY58PQntp032jPIQJro2wYCEfd4pTlFwL1zcZKWvrD8it10SFHbNoK4zLrUkz3Er/wP3wXE4I42K8xJsJFTfpd1pw6mOfnEOS5IOsoZlrBenbs1oV4D/RTuOMhX0rlGeEzDzvBA4J2SlCqbTZ4/7FJ6XPwqmbvTniqPZHO92eAWM0CaXT6hXCSuQ7kwrVeAcmWrvLELJFdv2WPld/AoeclEuI8tnkmAyJlDDnCVhu8q7iS/DsK9k3KliQ1LYF1XM5tVj+tXZaMSDIsiASk/LVnAbcoRwDjOkJz5Dc2Rg5tR0nPX49xs0oqlNByOVxTOx5ppFMWeS8n9Bt0ZpCBx1KTO2wJPmCdsn6LQSu6AeTYLr5ZklCuExT9AdPZIJg784zrbTcBg2qyJLDF5wM7Mg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(498600001)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /5SYh3C9AExYmVtpYVkssXzEqbFkieTwL/Gl8YxaBxOWTuMLNOMHOWyd7CwvmwfXIHd3Gcsbsm0l98G+/TVJtsXH0H6A6832uHKgLOpI68DDqhBmAidgS906/yPWgMME+5epBTlJJ5uVqcAHlZNOrNOGkJNsrdNMqD96JXq9hDj6iuItkEzCe0J2qoWenBqhE38bK1CMeFxJjYKhqE/9/RzgEQZVxWRJhOOM/adtsME8Em6vCUL0ufA3bI8m3VsxziH+G41EAYxv9Tu4W7llymoFYyWW0zEuma9mqKZoR7bsNG6iQ6GNkdBXCZeqNjkr5lf15zd8PiuwvWNUSmZk9s8Ds5Ink2A5zhWYENkXrTvhjpWgJpw0DeeqX9Wcuii0xRVDdyx35dcR29s6uXjjBSH5TCcU2z+MvVY9hX13EwFan4FvSTdX+6YKpWgpfEk+WVozKamqAcT6ikIkV3BkIIAspzF7zA9PsSEAGPLEIxXmuMyRqsLZd60yei6FOoNxbuRunnpQfxGdu0oAVGvq7c4dxr+WN7fib0DbdAP+Lra2z+b2ZQaWirzGYbs9q+Ca5x6fxfoUu+yYWpY4Pz3FVZi6+Xi/8n84wiomf4xy8y5z8TPTw93wFHDQe08W88/grjuRr4vLc/WcxXqMJxSfaRTo2HmdptSMZjsD36tDyVsggJ9JRaoYO0F/pP2sqvFJWtuFvg2kDppegY6K8mdtrsgwjDQGhOVHIejB0dCuFfzh6nRcznMmSewM09C2fGu+5yhzaAe629XWBx4hHkGTaN3/ACrJLJZNsQNItQzuJNoLs60LqzhXxsmGxGNcLStrDquO/CwEhUBHbbQBC4tMRpU3iLo/15avmdKuOflawS137hDpLhMbdHkM4QTBIgOc0Qoj01ItXPaiCev+VJiUDZpecKi+qVl/+JaQZVyvkM1bSPscIkq8hI2WpbTtaYNdB40NjuOWMV2kMcrkPC/f8i6aeGq27nexCU+lFhPAAN9oOEGNPiqMkimPy8+SJvvwYGVLXIN/dNZsNbnuTR4k5g/qcGYyzEtlbXKj6IeJ9KGkFH/qwGKvz92kUsTpgOszhjX2hf+cQYRRT8qHC8P0tsfIuyUFupCPiRxRa5BS/AkIrcc+7zLazhdjo5ImsMZ4dsVOLRxYIWcFoWyifBsnD15IfpLcrmG7+3/seHndy6uHq3Ic+rz+kWF6anoBUFB8vgSqprxliP/VGfP3/7UIntVOIhBNuV8scMUCFJW+aKyov1iJpnQFtbmNnAUAzOQ5v2EZLiPqQgZuyNBRuznyrWhK+2+mGxq0b/zcwID9ahKuV/+zIAhT1H54jSpWCnMZ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: f86ed40b-b57d-446a-0ec4-08d931a9b41e X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:19.2132 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3O2M45S/BW+26MzlYFnuKledbO5kWX2xxV3rLKmA9l1m+pM1B8lr9+5DrV1KR3WWxb2xnW6ttGUOjNy1fTfU5Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/reg/reg_cli.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_cli.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_cli.h b/drivers/net/wireless/celeno/cl8k/reg/reg_cli.h new file mode 100644 index 000000000000..4a77dca136d7 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_cli.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_CLI_H +#define CL_REG_CLI_H + +#include "hw.h" + +int cl_reg_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_REG_CLI_H */ From patchwork Thu Jun 17 16:00:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF946C49EA3 for ; Thu, 17 Jun 2021 16:07:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AAF0B60FDB for ; Thu, 17 Jun 2021 16:07:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229686AbhFQQJv (ORCPT ); Thu, 17 Jun 2021 12:09:51 -0400 Received: from mail-eopbgr20072.outbound.protection.outlook.com ([40.107.2.72]:4749 "EHLO EUR02-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233726AbhFQQIh (ORCPT ); Thu, 17 Jun 2021 12:08:37 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=d5CHn0sUoq2K5+Joigr1zNMTRkHwVF7EuveHtQD+4o4bYFWYgy6gxwPoyM0e7RLOobM3qeo71pIWY9E5q5xpIsiOAri4+/mPUPW3usVB6w1AbidXsQ8GPSPVC2TMUCiUlS+fLBtaqG+56XZZo8AtwVZhtcD0pCktiLQe76eVuxc1qwYpM4veuQPEw5F4lonifGHvsPv4FIAmS83hYicD85ypJthQsaUczLbV32ARgc26pwuE9pS2dGkpjm3Np0EutxvY7mVGyu94Aj+sB+Izl8EH0wacSuD29EV7UA3B9Skl4Awvt63XnoyBqupL4qj6FCsqSRBvGdijkz/VBNSwjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XonmHg04xYKLMaSqJNeIztOEZjjycppqBbn4+RcC9HM=; b=nGI4giYGT4V/tB9/E+VpxER6t1RS5qpRhPvNQa+LeIKisKjLCX+Wgh3jdKu9G9KOyN16YJAbe9p2HLtlMOX26P+wVNS9pR9SPrsDD4fjfIOX1N1/dvQL9qED6PdV3dZ2Rc6W14JdvMhTnRLhezRHdBHCCkXLpAd3Z54FJJoC7YxGB5vHgAOWvFzN2+EaSBF+Dc7phv5Yg8jUUB72SA7+wB00cZahvsT/BuUT3biC67zecP6h7BK9LarP4pxwj4loc/KZVsrA0uKeZPHJo3VvoU5ra5zB9tIi2Qc1znXHfLeGNpifCrsGJUGU8SJZmzbW7T67p5dJHR1O+9iG75nw6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XonmHg04xYKLMaSqJNeIztOEZjjycppqBbn4+RcC9HM=; b=gE6KaCZ5Bez4C6YQdZnk3go4i2shSQbvNAQCQWIG3fsqgpXCTYs7nxwzO8zrtq0ILuouX4ZjZtP0wghyPDwSlmqrPyCewsDH9Tz95fEs+D6GLu6WSurYYGKD0g8C1ck8BUPkP1tKeGRSHiA89FLwp6SuL6V+8o9myfrR197W8z4= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:24 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:24 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 151/256] cl8k: add reg/reg_cmu.h Date: Thu, 17 Jun 2021 16:00:38 +0000 Message-Id: <20210617160223.160998-152-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:19 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 668c68bb-84b9-439d-4eb2-08d931a9b4b4 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sVoFBv/w2MxpUzicY2VJeV6ymgPGITapjEnDkL+NqWVQ80cNWqh3ycVyMgTCbRjRoqOzdm6A3QFe6T1RR/U/NFZFpWCryAU/zOwmdmhfa424NWWlwOce/jQvijlTFpB67JKP4yl+1SLvJBIUpFdbwzwPWk1V7tCNVEuQwvP/znPX5umZoFuv1L6oeM1qQBxOD8nfkbocDcNcn+vRPOadUY25vhNR9Lsb7tjiSaJGfG2SmxPmCEUesfuqbdcY4KIL5YTV4RLrpvkV2GjS7xy3c9Ufhcu8wOAWTeAcoSGMuWZUGUcEBOfxhU+2kYxd1S1xxt9mdMk9crD68Vr7LAikeAu2QSwBwe70vg+EMuk+Ywufu/Cqf5cMT1TC32t51ehdhknrAQ4C7J4G6GSfG3zYXoMpd2CrerfvAEuCKjcOV1HGFKLiScPvNcBed7+MxDnp7F8XW5JTLfpi83kEj5kxDMA7Sw6JGI629dGu/cpVVLQTvj1Pj7LT+ooU8jh/RZTkR/aHYD0jxUsMMcmMUGdJ4bFXL/UGUGwQzuFoaodFjYsaXxTD5TbQuQ0LO2n+UsJ6Ck5P60VZYAfUE3dzod6pMwH7KkS7pQbmncB050QfuddsM1qjlnm1Llp3W17dE7EyKq2oIhlf1cguF1EWgzPEw7SnbKrwslJTBKzUBg6wdCCmrEsNRTXKseN6JaMAddhXLdJ9djMP3E2j860/INlGP6eWA7pztst+H/uMcV2LxxqRZqf4r56qBq6+nFEWNcNqxn/CWK5aVnhEaYgXi73rjg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(30864003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(498600001)(107886003)(69590400013)(32563001)(473944003)(414714003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aZLcXDqSezS0bu3BllWawM9XLe9KbDNwSeAmryKJa/dpT0h83SkeTmZgb8b4nkc3lHdS5Jg1VvrhIn76TZcJ3pMw4B8SVCC8EtVkgoJcKvwJ5lVFSAr8p4/B9xq+l/rIkSTBh05EZh2JJOB7IjoeHYnqBtw3MmkY7B+dBMdgfZlnV98lezlxl/Wk0l/0iS9RQlQETrENFMALIMBaITs9/xyKywsQDENM4SPZUOEs3Bk2Gg7Qrx3q5CJGLhfF5O+jzsUH+s0iE3beQQb/0QUDj9GVSTzlc25qtvknKGvGIcoKKyQcmxjcWDfDS7rUXhZ65cinynPr1EQFkCSJGd8wXIi0w3pYx5NRtYVUKnLXmCokavLi+t/slnhJPeXd77P50lfX59syDMSTwxdKQHRt8Xeh/YpcYvpR5d0X/DTlwwYrODg5ple+wjl71PyzP3rr+iyvagbtLkN3D6fSRu6yPpQhNxh441s5DlN2iPuvEqcNahrDIr9mdfUDpGt45ESq+JAOtvFnLT8yDjX7ts3AIPI7E3JiaB0wt+NvGhTECRQcfXmhI4TngR/BvRFgsPmHADRUiV9lwy+DrEslh+zOaQU1h4LEWTtX2ELYYt9rOTC1ZYevMWH+l75Ulany+aJmRLVg8jr7Hk0vMzglUM7fZn392OjOMfPILqEGMk7x/SfFGfm+IpMOjR7XPtYaThwsBjIjCmPIkBzulQzcD9XCBHHANyM+F92POu6pnx4eZ4bp38cgyPfv+eq3/MFXQtdrZUj9ldNfYDW0pk7NoDY92AMEM40m794rbE3BPq3q2T0FYGarTqCrlJDAz2Bop+tKgv6LfnfQbnsF0txQCNhwrS7OG/VGcEdr0twTT5WhvorpZX2ciVIYzjcuYWjgOVFv4qWfhyVX2GjfQGuTt5ns6BnQX24qojy/i15+Q2IuW+iwEZyVygHohnBfgfXLtQfblB6wai8HYB6VG30Y/yn2qCiNfvg9JZCJSpA4rWStGjS55CX+fWApK4iiBzkrF6Ds1V9ZzeGyyjmWocapLkaTlRNqOhuWXO+5k/ojMfB8YbK+EtG2Jcnl4oipg62NbcvbWhk2D3B1A8YnxyBf0qmIg+QIwlz2mQUgsShC0qdNbrvaRI2ZIbqHcrUteGSDIE3L6WohbUwcuRVpRXJ/X+kqJozmy5VSvGnW/hykAWnThqxZa3lzfmkaDupq/vQ1R9KuQD6MRuxnF3an2BE2klDgITXahhPlF2veY/+U+GuDr6JdgSeJTu5EytBjr2mVSQwc63VSJXmT9pdPeOmLGfn9twPtW9XO9gy5V8AMDdl7XEeT6PHL4ixYZxSTPRqq2UMY X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 668c68bb-84b9-439d-4eb2-08d931a9b4b4 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:20.2347 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bU3NgrqMmCJiOG8U0dVvW/Emp+vfVrgPIP15Bxi5TA7vBmTj+PQe25UU4eHGw9E5jxJToSHbFvPpgq2eaHye9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/reg/reg_cmu.h | 379 ++++++++++++++++++ 1 file changed, 379 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h new file mode 100644 index 000000000000..59428bf81e20 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_CMU_H +#define CL_REG_CMU_H + +#include +#include "reg/reg_access.h" +#include "chip.h" + +#define REG_CMU_BASE_ADDR 0x007C6000 + +/* + * @brief CMU_CLK_EN register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    spare_afe_gnrl_en         0
+ *    30    spare_sys_gnrl_en         0
+ *    27    spare_riu44_clk_en        0
+ *    26    spare_riu_clk_en          0
+ *    25    spare_riu2x_clk_en        0
+ *    24    spare_riu4x_clk_en        0
+ *    23    spare_phy_clk_en          0
+ *    22    spare_phy2x_clk_en        0
+ *    21    spare_sysx_clk_en         0
+ *    20    spare_sys2x_clk_en        0
+ *    19    ricu_clk_en               0
+ *    05    smac_proc_clk_en          1
+ *    04    umac_proc_clk_en          1
+ *    03    lmac_proc_clk_en          1
+ *
+ */ +#define CMU_CLK_EN_ADDR (REG_CMU_BASE_ADDR + 0x00000000) +#define CMU_CLK_EN_OFFSET 0x00000000 +#define CMU_CLK_EN_INDEX 0x00000000 +#define CMU_CLK_EN_RESET 0x00000038 + +/* Field definitions */ +#define CMU_SPARE_AFE_GNRL_EN_BIT ((u32)0x80000000) +#define CMU_SPARE_AFE_GNRL_EN_POS 31 +#define CMU_SPARE_SYS_GNRL_EN_BIT ((u32)0x40000000) +#define CMU_SPARE_SYS_GNRL_EN_POS 30 +#define CMU_SPARE_RIU_44_CLK_EN_BIT ((u32)0x08000000) +#define CMU_SPARE_RIU_44_CLK_EN_POS 27 +#define CMU_SPARE_RIU_CLK_EN_BIT ((u32)0x04000000) +#define CMU_SPARE_RIU_CLK_EN_POS 26 +#define CMU_SPARE_RIU_2_X_CLK_EN_BIT ((u32)0x02000000) +#define CMU_SPARE_RIU_2_X_CLK_EN_POS 25 +#define CMU_SPARE_RIU_4_X_CLK_EN_BIT ((u32)0x01000000) +#define CMU_SPARE_RIU_4_X_CLK_EN_POS 24 +#define CMU_SPARE_PHY_CLK_EN_BIT ((u32)0x00800000) +#define CMU_SPARE_PHY_CLK_EN_POS 23 +#define CMU_SPARE_PHY_2_X_CLK_EN_BIT ((u32)0x00400000) +#define CMU_SPARE_PHY_2_X_CLK_EN_POS 22 +#define CMU_SPARE_SYSX_CLK_EN_BIT ((u32)0x00200000) +#define CMU_SPARE_SYSX_CLK_EN_POS 21 +#define CMU_SPARE_SYS_2_X_CLK_EN_BIT ((u32)0x00100000) +#define CMU_SPARE_SYS_2_X_CLK_EN_POS 20 +#define CMU_RICU_CLK_EN_BIT ((u32)0x00080000) +#define CMU_RICU_CLK_EN_POS 19 +#define CMU_SMAC_PROC_CLK_EN_BIT ((u32)0x00000020) +#define CMU_SMAC_PROC_CLK_EN_POS 5 +#define CMU_UMAC_PROC_CLK_EN_BIT ((u32)0x00000010) +#define CMU_UMAC_PROC_CLK_EN_POS 4 +#define CMU_LMAC_PROC_CLK_EN_BIT ((u32)0x00000008) +#define CMU_LMAC_PROC_CLK_EN_POS 3 + +#define CMU_MAC_ALL_CLK_EN \ + (CMU_RICU_CLK_EN_BIT | \ + CMU_SMAC_PROC_CLK_EN_BIT | \ + CMU_UMAC_PROC_CLK_EN_BIT | \ + CMU_LMAC_PROC_CLK_EN_BIT) + +static inline void cmu_clk_en_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, CMU_CLK_EN_ADDR, value); +} + +/* + * @brief CMU_PHY_0_CLK_EN register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    02    ceva0_clk_en              0
+ *    01    phy0_apb_clk_en           0
+ *    00    phy0_main_clk_en          0
+ *
+ */ +#define CMU_PHY_0_CLK_EN_ADDR (REG_CMU_BASE_ADDR + 0x00000004) +#define CMU_PHY_0_CLK_EN_OFFSET 0x00000004 +#define CMU_PHY_0_CLK_EN_INDEX 0x00000001 +#define CMU_PHY_0_CLK_EN_RESET 0x00000000 + +static inline void cmu_phy_0_clk_en_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR, value); +} + +/* Field definitions */ +#define CMU_CEVA_0_CLK_EN_BIT ((u32)0x00000004) +#define CMU_CEVA_0_CLK_EN_POS 2 +#define CMU_PHY_0_APB_CLK_EN_BIT ((u32)0x00000002) +#define CMU_PHY_0_APB_CLK_EN_POS 1 +#define CMU_PHY_0_MAIN_CLK_EN_BIT ((u32)0x00000001) +#define CMU_PHY_0_MAIN_CLK_EN_POS 0 + +#define CMU_PHY0_CLK_EN \ + (CMU_CEVA_0_CLK_EN_BIT | \ + CMU_PHY_0_APB_CLK_EN_BIT | \ + CMU_PHY_0_MAIN_CLK_EN_BIT) + +static inline void cmu_phy_0_clk_en_pack(struct cl_chip *chip, u8 ceva0clken, u8 phy0apbclken, + u8 phy0mainclken) +{ + ASSERT_ERR_CHIP((((u32)ceva0clken << 2) & ~((u32)0x00000004)) == 0); + ASSERT_ERR_CHIP((((u32)phy0apbclken << 1) & ~((u32)0x00000002)) == 0); + ASSERT_ERR_CHIP((((u32)phy0mainclken << 0) & ~((u32)0x00000001)) == 0); + cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR, ((u32)ceva0clken << 2) | + ((u32)phy0apbclken << 1) | ((u32)phy0mainclken << 0)); +} + +static inline void cmu_phy_0_clk_en_ceva_0_clk_en_setf(struct cl_chip *chip, u8 ceva0clken) +{ + ASSERT_ERR_CHIP((((u32)ceva0clken << 2) & ~((u32)0x00000004)) == 0); + cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR, + (cl_reg_read_chip(chip, CMU_PHY_0_CLK_EN_ADDR) & ~((u32)0x00000004)) | ((u32)ceva0clken << 2)); +} + +static inline void cmu_phy_0_clk_en_phy_0_apb_clk_en_setf(struct cl_chip *chip, u8 phy0apbclken) +{ + ASSERT_ERR_CHIP((((u32)phy0apbclken << 1) & ~((u32)0x00000002)) == 0); + cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR, + (cl_reg_read_chip(chip, CMU_PHY_0_CLK_EN_ADDR) & ~((u32)0x00000002)) | ((u32)phy0apbclken << 1)); +} + +/* + * @brief CMU_PHY_1_CLK_EN register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    02    ceva1_clk_en              0
+ *    01    phy1_apb_clk_en           0
+ *    00    phy1_main_clk_en          0
+ *
+ */ +#define CMU_PHY_1_CLK_EN_ADDR (REG_CMU_BASE_ADDR + 0x00000008) +#define CMU_PHY_1_CLK_EN_OFFSET 0x00000008 +#define CMU_PHY_1_CLK_EN_INDEX 0x00000002 +#define CMU_PHY_1_CLK_EN_RESET 0x00000000 + +static inline void cmu_phy_1_clk_en_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR, value); +} + +/* Field definitions */ +#define CMU_CEVA_1_CLK_EN_BIT ((u32)0x00000004) +#define CMU_CEVA_1_CLK_EN_POS 2 +#define CMU_PHY_1_APB_CLK_EN_BIT ((u32)0x00000002) +#define CMU_PHY_1_APB_CLK_EN_POS 1 +#define CMU_PHY_1_MAIN_CLK_EN_BIT ((u32)0x00000001) +#define CMU_PHY_1_MAIN_CLK_EN_POS 0 + +#define CMU_PHY1_CLK_EN \ + (CMU_CEVA_1_CLK_EN_BIT | \ + CMU_PHY_1_APB_CLK_EN_BIT | \ + CMU_PHY_1_MAIN_CLK_EN_BIT) + +static inline void cmu_phy_1_clk_en_pack(struct cl_chip *chip, u8 ceva1clken, u8 phy1apbclken, + u8 phy1mainclken) +{ + ASSERT_ERR_CHIP((((u32)ceva1clken << 2) & ~((u32)0x00000004)) == 0); + ASSERT_ERR_CHIP((((u32)phy1apbclken << 1) & ~((u32)0x00000002)) == 0); + ASSERT_ERR_CHIP((((u32)phy1mainclken << 0) & ~((u32)0x00000001)) == 0); + cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR, ((u32)ceva1clken << 2) | + ((u32)phy1apbclken << 1) | ((u32)phy1mainclken << 0)); +} + +static inline void cmu_phy_1_clk_en_ceva_1_clk_en_setf(struct cl_chip *chip, u8 ceva1clken) +{ + ASSERT_ERR_CHIP((((u32)ceva1clken << 2) & ~((u32)0x00000004)) == 0); + cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR, + (cl_reg_read_chip(chip, CMU_PHY_1_CLK_EN_ADDR) & ~((u32)0x00000004)) | ((u32)ceva1clken << 2)); +} + +static inline void cmu_phy_1_clk_en_phy_1_apb_clk_en_setf(struct cl_chip *chip, u8 phy1apbclken) +{ + ASSERT_ERR_CHIP((((u32)phy1apbclken << 1) & ~((u32)0x00000002)) == 0); + cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR, + (cl_reg_read_chip(chip, CMU_PHY_1_CLK_EN_ADDR) & ~((u32)0x00000002)) | ((u32)phy1apbclken << 1)); +} + +/* + * @brief CMU_CONTROL register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    00    gl_mux_sel                0
+ *
+ */ +#define CMU_CONTROL_ADDR (REG_CMU_BASE_ADDR + 0x0000000C) +#define CMU_CONTROL_OFFSET 0x0000000C +#define CMU_CONTROL_INDEX 0x00000003 +#define CMU_CONTROL_RESET 0x00000000 + +static inline void cmu_control_gl_mux_sel_setf(struct cl_chip *chip, u8 glmuxsel) +{ + ASSERT_ERR_CHIP((((u32)glmuxsel << 0) & ~((u32)0x00000001)) == 0); + cl_reg_write_chip(chip, CMU_CONTROL_ADDR, (u32)glmuxsel << 0); +} + +/* + * @brief CMU_RST register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    18    spare_riu44_reset_n       0
+ *    17    spare_modem_reset_n       0
+ *    16    spare_sys_reset_n         0
+ *    15    n_RICURst                 1
+ *
+ */ +#define CMU_RST_ADDR (REG_CMU_BASE_ADDR + 0x00000010) +#define CMU_RST_OFFSET 0x00000010 +#define CMU_RST_INDEX 0x00000004 +#define CMU_RST_RESET 0x0000FF80 + +static inline void cmu_rst_n_ricurst_setf(struct cl_chip *chip, u8 nricurst) +{ + ASSERT_ERR_CHIP((((u32)nricurst << 15) & ~((u32)0x00008000)) == 0); + cl_reg_write_chip(chip, CMU_RST_ADDR, + (cl_reg_read_chip(chip, CMU_RST_ADDR) & ~((u32)0x00008000)) | ((u32)nricurst << 15)); +} + +/* + * @brief CMU_PHY_0_RST register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    03    ceva0_global_rst_n        1
+ *    02    mpif0_rst_n               1
+ *    01    phy0_preset_n             1
+ *    00    phy0_rst_n                1
+ *
+ */ +#define CMU_PHY_0_RST_ADDR (REG_CMU_BASE_ADDR + 0x00000014) +#define CMU_PHY_0_RST_OFFSET 0x00000014 +#define CMU_PHY_0_RST_INDEX 0x00000005 +#define CMU_PHY_0_RST_RESET 0x0000000F + +static inline void cmu_phy_0_rst_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, CMU_PHY_0_RST_ADDR, value); +} + +/* Field definitions */ +#define CMU_CEVA_0_GLOBAL_RST_N_BIT ((u32)0x00000008) +#define CMU_CEVA_0_GLOBAL_RST_N_POS 3 +#define CMU_MPIF_0_RST_N_BIT ((u32)0x00000004) +#define CMU_MPIF_0_RST_N_POS 2 +#define CMU_PHY_0_PRESET_N_BIT ((u32)0x00000002) +#define CMU_PHY_0_PRESET_N_POS 1 +#define CMU_PHY_0_RST_N_BIT ((u32)0x00000001) +#define CMU_PHY_0_RST_N_POS 0 + +#define CMU_PHY0_RST_EN \ + (CMU_PHY_0_PRESET_N_BIT | \ + CMU_MPIF_0_RST_N_BIT | \ + CMU_PHY_0_RST_N_BIT | \ + CMU_CEVA_0_GLOBAL_RST_N_BIT) + +static inline void cmu_phy_0_rst_ceva_0_global_rst_n_setf(struct cl_chip *chip, u8 ceva0globalrstn) +{ + ASSERT_ERR_CHIP((((u32)ceva0globalrstn << 3) & ~((u32)0x00000008)) == 0); + cl_reg_write_chip(chip, CMU_PHY_0_RST_ADDR, + (cl_reg_read_chip(chip, CMU_PHY_0_RST_ADDR) & ~((u32)0x00000008)) | ((u32)ceva0globalrstn << 3)); +} + +/* + * @brief CMU_PHY_1_RST register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    03    ceva1_global_rst_n        1
+ *    02    mpif1_rst_n               1
+ *    01    phy1_preset_n             1
+ *    00    phy1_rst_n                1
+ *
+ */ +#define CMU_PHY_1_RST_ADDR (REG_CMU_BASE_ADDR + 0x00000018) +#define CMU_PHY_1_RST_OFFSET 0x00000018 +#define CMU_PHY_1_RST_INDEX 0x00000006 +#define CMU_PHY_1_RST_RESET 0x0000000F + +static inline void cmu_phy_1_rst_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, CMU_PHY_1_RST_ADDR, value); +} + +/* Field definitions */ +#define CMU_CEVA_1_GLOBAL_RST_N_BIT ((u32)0x00000008) +#define CMU_CEVA_1_GLOBAL_RST_N_POS 3 +#define CMU_MPIF_1_RST_N_BIT ((u32)0x00000004) +#define CMU_MPIF_1_RST_N_POS 2 +#define CMU_PHY_1_PRESET_N_BIT ((u32)0x00000002) +#define CMU_PHY_1_PRESET_N_POS 1 +#define CMU_PHY_1_RST_N_BIT ((u32)0x00000001) +#define CMU_PHY_1_RST_N_POS 0 + +#define CMU_PHY1_RST_EN \ + (CMU_PHY_1_PRESET_N_BIT | \ + CMU_MPIF_1_RST_N_BIT | \ + CMU_PHY_1_RST_N_BIT | \ + CMU_CEVA_1_GLOBAL_RST_N_BIT) + +static inline void cmu_phy_1_rst_ceva_1_global_rst_n_setf(struct cl_chip *chip, u8 ceva1globalrstn) +{ + ASSERT_ERR_CHIP((((u32)ceva1globalrstn << 3) & ~((u32)0x00000008)) == 0); + cl_reg_write_chip(chip, CMU_PHY_1_RST_ADDR, + (cl_reg_read_chip(chip, CMU_PHY_1_RST_ADDR) & ~((u32)0x00000008)) | ((u32)ceva1globalrstn << 3)); +} + +/* + * @brief CMU_PLL_1_STAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    pll_lock                  0
+ *
+ */ +#define CMU_PLL_1_STAT_ADDR (REG_CMU_BASE_ADDR + 0x00000050) +#define CMU_PLL_1_STAT_OFFSET 0x00000050 +#define CMU_PLL_1_STAT_INDEX 0x00000014 +#define CMU_PLL_1_STAT_RESET 0x00000000 + +static inline u8 cmu_pll_1_stat_pll_lock_getf(struct cl_chip *chip) +{ + u32 local_val = cl_reg_read_chip(chip, CMU_PLL_1_STAT_ADDR); + + ASSERT_ERR_CHIP((local_val & ~((u32)0x80000000)) == 0); + return (local_val >> 31); +} + +/* + * @brief CMU_PHASE_SEL register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    20    gp_clk_phase_sel          1
+ *    19    dac_cdb_clk_phase_sel     0
+ *    18    adc_cdb_clk_phase_sel     0
+ *    17    dac_clk_phase_sel         0
+ *    16    adc_clk_phase_sel         0
+ *
+ */ +#define CMU_PHASE_SEL_ADDR (REG_CMU_BASE_ADDR + 0x00000060) +#define CMU_PHASE_SEL_OFFSET 0x00000060 +#define CMU_PHASE_SEL_INDEX 0x00000018 +#define CMU_PHASE_SEL_RESET 0x00100000 + +static inline void cmu_phase_sel_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, CMU_PHASE_SEL_ADDR, value); +} + +/* Field definitions */ +#define CMU_GP_CLK_PHASE_SEL_BIT ((u32)0x00100000) +#define CMU_GP_CLK_PHASE_SEL_POS 20 +#define CMU_DAC_CDB_CLK_PHASE_SEL_BIT ((u32)0x00080000) +#define CMU_DAC_CDB_CLK_PHASE_SEL_POS 19 +#define CMU_ADC_CDB_CLK_PHASE_SEL_BIT ((u32)0x00040000) +#define CMU_ADC_CDB_CLK_PHASE_SEL_POS 18 +#define CMU_DAC_CLK_PHASE_SEL_BIT ((u32)0x00020000) +#define CMU_DAC_CLK_PHASE_SEL_POS 17 +#define CMU_ADC_CLK_PHASE_SEL_BIT ((u32)0x00010000) +#define CMU_ADC_CLK_PHASE_SEL_POS 16 + +#endif /* CL_REG_CMU_H */ From patchwork Thu Jun 17 16:00:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 706EAC49EA6 for ; Thu, 17 Jun 2021 16:07:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 555CE60FDB for ; Thu, 17 Jun 2021 16:07:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233841AbhFQQJz (ORCPT ); Thu, 17 Jun 2021 12:09:55 -0400 Received: from mail-eopbgr70045.outbound.protection.outlook.com ([40.107.7.45]:47334 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231680AbhFQQIn (ORCPT ); Thu, 17 Jun 2021 12:08:43 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FJLgkJLmW9dGhh0BelISJtmUkKngzwLDvkInVNizaQk3Bt03A4sjTplNrcLJLZAoZeMrFyTQm90Rk6NGKy968Bls61+jNrouKaEuwZBZzoXkfRsoElEeGBdt0coisPMDT6v4U4L7WkRNb4eTlhQuTOQcUU3s+PKjBOneNjCyg9K6PA42yUzreMggaQg+fOfY28s8c9C1KFX0j5Qjn9Ov9Q1/L5H5MOMUdHJhatNauTr5RmWVgIatcJ1No3KmAneavX+CFc4J1d2KeNCDTzLewkyUrA2yFv5NsYOMnmLc/M0sOkK/SB7keecOm/fOzih446utf/TqIQcbUgSVzwjLbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vLSPt3m06p/sjN8PHT1jUWE6Ub/8dxzjcRSpRilUfEo=; b=a56jddtu4edGtpOgZ5IrAypZP+nSB1VTF0acNyjU5q6SsyKltOHeAOfefOae+QJmq+CfO3UGK/sK358Jpt7cJC1FfQ5adSliNo34pG/YBYQBFY6+F4pqk6ps0Upw+26BW53xtTIoLcgmOF5uOYV/jBPEf4EiPh+m6C8PUh1y2aFGJUqj2/2Rpr8m7O8+ssCL02BWIipkwQonSApmn5t67psDui5B1PqOVEw3sTvLmmfylMFji5lntwZbP77sWVliv9S4llkb3Egpx8Q6sRkHPIvGLjjxCYFXT64AcBFb71fK1/LBio4XjQkaW95Y41MskNyWw9ESCUUFppmtKhlrhA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vLSPt3m06p/sjN8PHT1jUWE6Ub/8dxzjcRSpRilUfEo=; b=wqpzIyt2ur9fvWrnlerTEKgAy1EJ6/SaFlFsShZPn3xFmDxhm+KVB6Kf+GeR2QrjZ3d7nelpdhl68Wi3IXrZqUu0EXQpdiwUFBFSo2uZrJnBaOLCkHRlXyGJzJChTiOzx90GPw4uCfzJvCISMDcitWqKK7TOsKKdeQVLWoMbdfY= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:24 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:24 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 152/256] cl8k: add reg/reg_fem.h Date: Thu, 17 Jun 2021 16:00:39 +0000 Message-Id: <20210617160223.160998-153-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:20 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7cf14df8-3c60-495a-cc9b-08d931a9b555 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:660; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Gu0ZfOVZrVV5AjVzrRl8c/769W05vYJQmOBK9+EQLgfLD3sUrn3i+x1Pm73mDM3DC1YKl5z25iwGB1we/ztqpHdS/Pso7hnl5q1wprkK7J7tStuoex+j2l0NwMYpMbyo2H1XOMCle0JhNRIVnQ/vW8eknNdAocVd9V1nWndwxApkRI/+lDPBAB/XKDIhl6N5OT19dsJGmDMrtU6nTIGORhITcjFNKrIwcpkT0uO8o4dzETGKt4pa1pYeH1BP4egZ4G0PXMjKy4KT2LbmsbXBl0hOjzJs4qoV54rh96+swEr1lqyiO05G0TW25EHbNOJLW9x0rAtOCFaJwL6Nin+b1to2fId0cjk1FM22f+fZRdPbF5JT3MEyRDqQJjiUlX9xnB56IwE2+vyI5zbZnuKqse4WsZWaMhk5ytLIRO2G7eyItW4+rLFU9HrLPDYF4Vyu1VlJ19A3zmXLo9SoqB5I1Abo2+MAB7Ip90E4IpMtqkLi4dcG6iDhE97BJdtOy0VWakpwhnVydtAwvQ9ajSigIj6Q9rGrZJNPLlgPBW/3d7qLhF8vv8/twTO2B5MTGU1S/WYzRg57IgICK8cs2+aDourqZuzS0Yc7Us8piV4EF2nHrPV8fDwbSxYc141C5CmE4EWUQ87mukqkAVkfHCer9IEPMa20xYCrwKItZZQ99nNMqWegeDjVSYIlShCC9khiwd4GQJIegezshOn/JqOu8g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(498600001)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 85sHjb0/k+mCFYng0LsRDBkLfQqt0gX2gt7cM4UzVmu1S70ZhKXR5dtaYvGAh8lMHVRiWxSy7u7Jpaetn7QVw8Qei5wvDkFKCsp5AqADwq0MtNyDdVbY2AwCr5WvkhNFA8Ko4DDhM3qq1CIfdlMNmSWAKX7mv+MUMDfoRjylnqJHyflO/jCiNqrwrIHKQyVxSCmTpRqRxDPF7dMl6Tf/gWpCjLc3Yxpeb0V2zGHSIzJa1FV3VvJVjhYHpfq5kD7E+/zSnsOt+mK/FJtQeWiVLjJABD1CJNUTbLvpF6GsLOLKB9lFoLgUD/mjCaarQOkBHk2QAoLSfK20Oc/5Y4qnXwztZdb8II+P/RCx+Jv2JqumRjpDoUKwhnB3kR3voxxKR+Kpwj8TugcLAKdqgykZU81M+5myG9JZ6sSykBSb0bWdMnLD7fwfDKjEgd65cEjDu41ABDri+8sNVYlOFti8qOfysIZ62KTbadwS2wRMTJ/rBB9qRjE0bDclFSDWj/KCqK0+VLhQlQvQM4Qp5Bo7zrbppEKiFIshbpM438tXIMQqkKrTlKyjx1WECOD8Swn3kUCr5ZaR/QfhLLyfrwoCV5AoE1wFP3hQ+aGu13TjooeRrAB5rLtw0/ei9/NFqZyvXXVVuHFgp6VkSMGkZ5LB+QmSui8ZpiUoM05AKW+2+K+BCfYh6sUhydrshxGgjraRNz2VmueeLJQjeC8UFNZcYvrXL1/GpI4SHzaCYQvfntJVy6ruivOrcb1IGfS/l5gHqYRscqR5cdk7HT1OFRxSkWVod3NNdlPb6mjyang5FS59puOdf/ETMSOow+ApBjQJRDZ3PLf7HBX/nYlq1Ivl0Z2bdYYy/s9bnYBSa1FDnK0UaNp3MwgEOzlGX0WJDWvT9snKMbZldwkZ96CxRmZWDT6oxl0DiLT0ut2XlH9ZbR4v+aGuwGBVw6KMAXxZ5y03Q8WbW2mM3o14hwKHuxAbYnfaCnQUFTab3NyWUaF1Nw/zkuDOeuyq7I10b1GNaPXt/oi6FozUBg1LCwLYCKSIjt9nGUF1oboyl4tU9d7ocEi7PAETSmKfMA/Bblf1+N04kMwz7S6T2gFidvsb/2hEPme3eLSMn1OoGR/9Cn4FKOgiSmdO+qfk2acTMWWVxs43gbuWQwhXVLhza9S5btA1LuJcJV9V62gAN5z66AtqQV3/Q4p0PtgpUR9ZzbF//+uYK9k5JlguVbqFfxGKtc/fKCPURPni+cS4h+RJ4cWztBb18nS/dq71F8qRuCZ+kHCkO97R6nPldFZyqY9SQu9AaeCgkKLaBjWTS2VmrWjkHg/eprsSBjyQAt3Y2ElVcWC4 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7cf14df8-3c60-495a-cc9b-08d931a9b555 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:21.2552 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xaBd7JZ9/FT6t73BfG/OMu+FHxEm7mXWnZjxyoIMiOt6Fuu9AlGW1Vn1UwVNDq9mJc/Xwr1sjOTd+tuoNG4qRw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/reg/reg_fem.h | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_fem.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_fem.h b/drivers/net/wireless/celeno/cl8k/reg/reg_fem.h new file mode 100644 index 000000000000..ab1aaae23782 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_fem.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_FEM_H +#define CL_REG_FEM_H + +#include "reg/reg_io_ctrl.h" + +struct cl_fem_lna_enable_gpio { + union { + u16 b0 : 1, + b1 : 1, + b2 : 1, + b3 : 1, + b4 : 1, + b5 : 1, + b6 : 1, + b7 : 1, + b8 : 1, + b9 : 1, + b10 : 1, + b11 : 1, + rsv : 4; + u16 val; + }; +}; + +struct cl_fem_pa_enable_gpio { + union { + u16 b0 : 1, + b1 : 1, + b2 : 1, + b3 : 1, + b4 : 1, + b5 : 1, + b6 : 1, + b7 : 1, + b8 : 1, + b9 : 1, + b10 : 1, + b11 : 1, + rsv : 4; + u16 val; + }; +}; + +struct cl_fem_rx_active_gpio { + union { + u8 b0 : 1, + b1 : 1, + b2 : 1, + b3 : 1, + b4 : 1, + b5 : 1, + b6 : 1, + b7 : 1; + u8 val; + }; +}; + +#define EXTRACT_OFF_LUT(lut) (((lut) >> 12) & 0x7) +#define FEM_LUT_MASK 0x0777 + +#define PA_ENABLE_POS 0 +#define LNA_ENABLE_POS 1 +#define RX_ACTIVE_POS 2 +#define GET_BIT(reg, pos) (((reg) >> (pos)) & 0x1) + +/* + * LNA_ENABLE + * IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS is used for all ioctl APIs - + * io_ctrl_lna_enable_0_set() ... io_ctrl_lna_enable_11_set() + * because all have the same value + */ +#define LNA_ENABLE_GPIO_VAL(val) \ + (((u32)(val) << IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS) & \ + IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_BIT) + +/* PA_ENABLE */ +#define PA_ENABLE_GPIO_VAL(val) \ + (((u32)(val) << IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_POS) & \ + IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_BIT) + +/* RX_ACTIVE */ +#define RX_ACTIVE_GPIO_VAL(val) \ + (((u32)(val) << IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_POS) & \ + IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_BIT) + +#define LNA_ENABLE_GPIO_OUT_CFG(val) \ + (((1 << IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS) & IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_BIT) | \ + ((1 << IO_CTRL_LNA_ENABLE_0_GPIO_OE_POS) & IO_CTRL_LNA_ENABLE_0_GPIO_OE_BIT) | \ + (((u32)(val) << IO_CTRL_LNA_ENABLE_0_GPIO_OUT_POS) & IO_CTRL_LNA_ENABLE_0_GPIO_OUT_BIT)) +#define PA_ENABLE_GPIO_OUT_CFG(val) \ + (((1 << IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_POS) & IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_BIT) | \ + ((1 << IO_CTRL_PA_ENABLE_0_GPIO_OE_POS) & IO_CTRL_PA_ENABLE_0_GPIO_OE_BIT) | \ + (((u32)(val) << IO_CTRL_PA_ENABLE_0_GPIO_OUT_POS) & IO_CTRL_PA_ENABLE_0_GPIO_OUT_BIT)) +#define RX_ACTIVE_GPIO_OUT_CFG(val) \ + (((1 << IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_POS) & IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_BIT) | \ + ((1 << IO_CTRL_RX_ACTIVE_0_GPIO_OE_POS) & IO_CTRL_RX_ACTIVE_0_GPIO_OE_BIT) | \ + (((u32)(val) << IO_CTRL_RX_ACTIVE_0_GPIO_OUT_POS) & IO_CTRL_RX_ACTIVE_0_GPIO_OUT_BIT)) + +#endif /* CL_REG_FEM_H */ From patchwork Thu Jun 17 16:00:40 2021 Content-Type: text/plain; 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Thu, 17 Jun 2021 16:06:25 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 153/256] cl8k: add reg/reg_io_ctrl.h Date: Thu, 17 Jun 2021 16:00:40 +0000 Message-Id: <20210617160223.160998-154-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:21 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f8e2a7b5-caf2-4808-a1ac-08d931a9b5ee X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: syUN/sMJIk5a/dcBtHjY3nS1P41xtInn0IKPJqKNGI2eH3fvy8QRjARFmjPG+GKUQDcBcj7nw19QL4C6uusFlvcpOq3RGUxlofznwM4ruawLmfeZDQ2qNWacbESkZUUFchATN52v2jDUvtuJh1+x5CywfA2I5XHzwvPrFScNhgxu/4fSH7aflFqw2CWx7ec+xJM6A4Na9lSjvqN11GIeL8GaFDUvZT3VarF9g3lfbqoiWN1ulUTJp+AsXmjPM7f7JKwKnsnYIouIC9Nyq9OKfRwW5dE0x9u2IcGWHt9q0VaOTnGiDs2VpFg7hPFQ/FPlGp5rnGPhRs4H7+2lWNMjwPy7+XzbKlhE2/74cb8zPLC+pOIg6NvcipfBFdEgh2EZghKaDU03iUvqD6fuN9hz0ac24rUSaVjKUbUcEb/7OC7yPeqBCnY9zlCckASiHf3JCFGume/biAYJBC4ZwJ2HGnxF1vsc+1SnSEty1tu8kGtTwBY72ywZ4bz44bAw6oyz2QOdQX2MYQEmraPOpuhYpqR/73DiGP6NOc0UfUtry+7P1WN8Jrm+Ncum4FOkT6+dgeyjv1XQJCke8De84j14jDnFSW/ALibgehkVpGrymS/mABxZrp8gzo3F9Pnm34+i91j+wIkmaPXuS1uWP+bHB4ORwC2JNmirUaFTRlMOaUvJPZ88VjLgbTwF7ApYt/NyyGl4taZ8gK9/J8ztG1aCtw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(30864003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(498600001)(107886003)(69590400013)(32563001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fOce2VYE+rETWEeZpcy/XZxjpUcpe3hjjR5qZnTKDbRfr6kqg8jVMXMjWPjH5EPbYdVFiA/4KgrUfadwti76FNx1SnggDngfbZk0LEoQfTNm8P/9OZRe4LPYcwehkBJqHKaJ+GaxOGp9IUFI9/XPboCzcgS+gW+dtOVZJiYmA5Hs7i7mEdO16oxZjfgmrJ1/NnP7tkoXBIor47EhbR8wbQEEpjJffIbTtU602CO6vP57FYzCm6pSclEKi/ZSEGkBdi79bXtlzEbrOYaDvTOxWYSTFIQ+HBPgSTIgiYBVpLWMG/ET7XFaYWJtkEk3mbZhAidVVN9aQIs+5OjQ7XNowgfkT/mEigcBBagEo4gP1NakuR9EdqPMC/IxeocB3V1oHs39LF6A8nkjZFEBg//UWpXvecIvWxTeRud9gPbu53pBWPoEnX0i9+KaHqx+oUgS8YVy/gKTJp/zXfrQQHYvqlLkSo3HmxCc6dgx2qh6VkA2Dj2BSR+Ob9mQtBTW6vsylmg5Wly4xLaXC31xwHGx6z5jfXTy9ixq8uYHMFZvEiOxjYlbxCoOADFT8i+CHts6KLKBColk6fCOFtJ5djKdPZpRvqEJ9MFzdNQEWXxbfz4rNiBlFaWzAdqN36dAStgg+rKiUXwYus8BNeU88FPJcHXutD0BypjbWmze8vYF0OIdXa6IS3KTYpbsJq8h6C2xssvk30fJHaJutlrNVNsHoRcl4pkkVddswa+Nfi6YMkIkyYrCA1jw6C3oYWw4HqUKbdQ+khgQrpNSnOitGhq4J8LYMsoh4mouAjRTVgYYvkysThDFVoetEtCWFFD8yf9MiLtS9nWmVnrX61ygH7kbUDrmv6VFeLLgawkpDbg9dyNculxy+AB3EczNsr8NT7xyAjMB1R2IUL8hc3ZdYhebmZ6pQENbRR1AgwcZ3EBUVbym+mjF17udkg3hQu+knOIoIZNsbGaKqV0LlcK+fvS1WNk3CI53bLoOSe+RfDXuaeDxLsWdKSXBm2rw0owu4B6oKWAClH6Jv5oNmnnKCVVUBWGHlkRkT8DvxRv5UmcvkRyvyROZcR9q1T+JyRAcEsCRvRf03ONGFkWVzE4HnxPLmfMTr/aA4vF6fizt4qTGK1M3KludJd6SDEsWp91v7IJ7nUOoCfnLRWRaHy1Co47gvc+aOzh36ykzPCRZGsdpeRdixSL9dNpzqYBE0mDOlCYtW/z5p/B5/KM6UTXTTTuO+UWmn2rkCxfOHFCMIXHv68oU79RcvlnojxMgRGA61Tq3CPyy4MsyVbxhwBBjXl0bBppzhz48JaVVvTmK8vCTkii5LYTyV79bdBW7MpaEs8JJ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: f8e2a7b5-caf2-4808-a1ac-08d931a9b5ee X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:22.3683 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4QoRyIru0LsV03EloflpDhWJiJf0LACfqlqUIgPYe4iTQ7YN8qARRYe5BSdPmTqKt3p3rO6Wtcm+tL5UK+kevA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_io_ctrl.h | 1223 +++++++++++++++++ 1 file changed, 1223 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h b/drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h new file mode 100644 index 000000000000..190a7a98ebd3 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_io_ctrl.h @@ -0,0 +1,1223 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_IO_CTRL_H +#define CL_REG_IO_CTRL_H + +#include +#include "reg/reg_access.h" +#include "chip.h" + +#define REG_IO_CTRL_BASE_ADDR 0x007C7000 + +/* + * @brief RX_ACTIVE_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000005C) +#define IO_CTRL_RX_ACTIVE_0_OFFSET 0x0000005C +#define IO_CTRL_RX_ACTIVE_0_INDEX 0x00000017 +#define IO_CTRL_RX_ACTIVE_0_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_0_ADDR, value); +} + +/* Field definitions */ +#define IO_CTRL_RX_ACTIVE_0_GPIO_IN_BIT ((u32)0x00002000) +#define IO_CTRL_RX_ACTIVE_0_GPIO_IN_POS 13 +#define IO_CTRL_RX_ACTIVE_0_GPIO_OUT_BIT ((u32)0x00001000) +#define IO_CTRL_RX_ACTIVE_0_GPIO_OUT_POS 12 +#define IO_CTRL_RX_ACTIVE_0_GPIO_OE_BIT ((u32)0x00000800) +#define IO_CTRL_RX_ACTIVE_0_GPIO_OE_POS 11 +#define IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_BIT ((u32)0x00000400) +#define IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_POS 10 +#define IO_CTRL_RX_ACTIVE_0_INPUT_ENABLE_BIT ((u32)0x00000200) +#define IO_CTRL_RX_ACTIVE_0_INPUT_ENABLE_POS 9 +#define IO_CTRL_RX_ACTIVE_0_SLEW_RATE_BIT ((u32)0x00000100) +#define IO_CTRL_RX_ACTIVE_0_SLEW_RATE_POS 8 +#define IO_CTRL_RX_ACTIVE_0_DRIVER_PULL_STATE_MASK ((u32)0x000000C0) +#define IO_CTRL_RX_ACTIVE_0_DRIVER_PULL_STATE_LSB 6 +#define IO_CTRL_RX_ACTIVE_0_DRIVER_PULL_STATE_WIDTH ((u32)0x00000002) +#define IO_CTRL_RX_ACTIVE_0_OUTPUT_PAD_STRENGTH_MASK ((u32)0x00000030) +#define IO_CTRL_RX_ACTIVE_0_OUTPUT_PAD_STRENGTH_LSB 4 +#define IO_CTRL_RX_ACTIVE_0_OUTPUT_PAD_STRENGTH_WIDTH ((u32)0x00000002) +#define IO_CTRL_RX_ACTIVE_0_SCHMIT_TRIGER_BIT ((u32)0x00000008) +#define IO_CTRL_RX_ACTIVE_0_SCHMIT_TRIGER_POS 3 +#define IO_CTRL_RX_ACTIVE_0_MUX_SELECT_MASK ((u32)0x00000007) +#define IO_CTRL_RX_ACTIVE_0_MUX_SELECT_LSB 0 +#define IO_CTRL_RX_ACTIVE_0_MUX_SELECT_WIDTH ((u32)0x00000003) + +/* + * @brief RX_ACTIVE_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000060) +#define IO_CTRL_RX_ACTIVE_1_OFFSET 0x00000060 +#define IO_CTRL_RX_ACTIVE_1_INDEX 0x00000018 +#define IO_CTRL_RX_ACTIVE_1_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_1_ADDR, value); +} + +/* + * @brief RX_ACTIVE_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000064) +#define IO_CTRL_RX_ACTIVE_2_OFFSET 0x00000064 +#define IO_CTRL_RX_ACTIVE_2_INDEX 0x00000019 +#define IO_CTRL_RX_ACTIVE_2_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_2_ADDR, value); +} + +/* + * @brief RX_ACTIVE_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000068) +#define IO_CTRL_RX_ACTIVE_3_OFFSET 0x00000068 +#define IO_CTRL_RX_ACTIVE_3_INDEX 0x0000001A +#define IO_CTRL_RX_ACTIVE_3_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_3_ADDR, value); +} + +/* + * @brief RX_ACTIVE_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000006C) +#define IO_CTRL_RX_ACTIVE_4_OFFSET 0x0000006C +#define IO_CTRL_RX_ACTIVE_4_INDEX 0x0000001B +#define IO_CTRL_RX_ACTIVE_4_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_4_ADDR, value); +} + +/* + * @brief RX_ACTIVE_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000070) +#define IO_CTRL_RX_ACTIVE_5_OFFSET 0x00000070 +#define IO_CTRL_RX_ACTIVE_5_INDEX 0x0000001C +#define IO_CTRL_RX_ACTIVE_5_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_5_ADDR, value); +} + +/* + * @brief RX_ACTIVE_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000074) +#define IO_CTRL_RX_ACTIVE_6_OFFSET 0x00000074 +#define IO_CTRL_RX_ACTIVE_6_INDEX 0x0000001D +#define IO_CTRL_RX_ACTIVE_6_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_6_ADDR, value); +} + +/* + * @brief RX_ACTIVE_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   1
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x3
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_RX_ACTIVE_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000078) +#define IO_CTRL_RX_ACTIVE_7_OFFSET 0x00000078 +#define IO_CTRL_RX_ACTIVE_7_INDEX 0x0000001E +#define IO_CTRL_RX_ACTIVE_7_RESET 0x000026D8 + +static inline void io_ctrl_rx_active_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_RX_ACTIVE_7_ADDR, value); +} + +/* + * @brief LNA_ENABLE_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000007C) +#define IO_CTRL_LNA_ENABLE_0_OFFSET 0x0000007C +#define IO_CTRL_LNA_ENABLE_0_INDEX 0x0000001F +#define IO_CTRL_LNA_ENABLE_0_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_0_ADDR, value); +} + +/* Field definitions */ +#define IO_CTRL_LNA_ENABLE_0_GPIO_IN_BIT ((u32)0x00002000) +#define IO_CTRL_LNA_ENABLE_0_GPIO_IN_POS 13 +#define IO_CTRL_LNA_ENABLE_0_GPIO_OUT_BIT ((u32)0x00001000) +#define IO_CTRL_LNA_ENABLE_0_GPIO_OUT_POS 12 +#define IO_CTRL_LNA_ENABLE_0_GPIO_OE_BIT ((u32)0x00000800) +#define IO_CTRL_LNA_ENABLE_0_GPIO_OE_POS 11 +#define IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_BIT ((u32)0x00000400) +#define IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS 10 +#define IO_CTRL_LNA_ENABLE_0_INPUT_ENABLE_BIT ((u32)0x00000200) +#define IO_CTRL_LNA_ENABLE_0_INPUT_ENABLE_POS 9 +#define IO_CTRL_LNA_ENABLE_0_SLEW_RATE_BIT ((u32)0x00000100) +#define IO_CTRL_LNA_ENABLE_0_SLEW_RATE_POS 8 +#define IO_CTRL_LNA_ENABLE_0_DRIVER_PULL_STATE_MASK ((u32)0x000000C0) +#define IO_CTRL_LNA_ENABLE_0_DRIVER_PULL_STATE_LSB 6 +#define IO_CTRL_LNA_ENABLE_0_DRIVER_PULL_STATE_WIDTH ((u32)0x00000002) +#define IO_CTRL_LNA_ENABLE_0_OUTPUT_PAD_STRENGTH_MASK ((u32)0x00000030) +#define IO_CTRL_LNA_ENABLE_0_OUTPUT_PAD_STRENGTH_LSB 4 +#define IO_CTRL_LNA_ENABLE_0_OUTPUT_PAD_STRENGTH_WIDTH ((u32)0x00000002) +#define IO_CTRL_LNA_ENABLE_0_SCHMIT_TRIGER_BIT ((u32)0x00000008) +#define IO_CTRL_LNA_ENABLE_0_SCHMIT_TRIGER_POS 3 +#define IO_CTRL_LNA_ENABLE_0_MUX_SELECT_MASK ((u32)0x00000007) +#define IO_CTRL_LNA_ENABLE_0_MUX_SELECT_LSB 0 +#define IO_CTRL_LNA_ENABLE_0_MUX_SELECT_WIDTH ((u32)0x00000003) + +/* + * @brief LNA_ENABLE_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000080) +#define IO_CTRL_LNA_ENABLE_1_OFFSET 0x00000080 +#define IO_CTRL_LNA_ENABLE_1_INDEX 0x00000020 +#define IO_CTRL_LNA_ENABLE_1_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_1_ADDR, value); +} + +/* + * @brief LNA_ENABLE_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000084) +#define IO_CTRL_LNA_ENABLE_2_OFFSET 0x00000084 +#define IO_CTRL_LNA_ENABLE_2_INDEX 0x00000021 +#define IO_CTRL_LNA_ENABLE_2_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_2_ADDR, value); +} + +/* + * @brief LNA_ENABLE_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000088) +#define IO_CTRL_LNA_ENABLE_3_OFFSET 0x00000088 +#define IO_CTRL_LNA_ENABLE_3_INDEX 0x00000022 +#define IO_CTRL_LNA_ENABLE_3_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_3_ADDR, value); +} + +/* + * @brief LNA_ENABLE_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000008C) +#define IO_CTRL_LNA_ENABLE_4_OFFSET 0x0000008C +#define IO_CTRL_LNA_ENABLE_4_INDEX 0x00000023 +#define IO_CTRL_LNA_ENABLE_4_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_4_ADDR, value); +} + +/* + * @brief LNA_ENABLE_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000090) +#define IO_CTRL_LNA_ENABLE_5_OFFSET 0x00000090 +#define IO_CTRL_LNA_ENABLE_5_INDEX 0x00000024 +#define IO_CTRL_LNA_ENABLE_5_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_5_ADDR, value); +} + +/* + * @brief LNA_ENABLE_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000094) +#define IO_CTRL_LNA_ENABLE_6_OFFSET 0x00000094 +#define IO_CTRL_LNA_ENABLE_6_INDEX 0x00000025 +#define IO_CTRL_LNA_ENABLE_6_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_6_ADDR, value); +} + +/* + * @brief LNA_ENABLE_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000098) +#define IO_CTRL_LNA_ENABLE_7_OFFSET 0x00000098 +#define IO_CTRL_LNA_ENABLE_7_INDEX 0x00000026 +#define IO_CTRL_LNA_ENABLE_7_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_7_ADDR, value); +} + +/* + * @brief LNA_ENABLE_8 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_8_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000009C) +#define IO_CTRL_LNA_ENABLE_8_OFFSET 0x0000009C +#define IO_CTRL_LNA_ENABLE_8_INDEX 0x00000027 +#define IO_CTRL_LNA_ENABLE_8_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_8_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_8_ADDR, value); +} + +/* + * @brief LNA_ENABLE_9 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_9_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000A0) +#define IO_CTRL_LNA_ENABLE_9_OFFSET 0x000000A0 +#define IO_CTRL_LNA_ENABLE_9_INDEX 0x00000028 +#define IO_CTRL_LNA_ENABLE_9_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_9_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_9_ADDR, value); +} + +/* + * @brief LNA_ENABLE_10 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_10_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000A4) +#define IO_CTRL_LNA_ENABLE_10_OFFSET 0x000000A4 +#define IO_CTRL_LNA_ENABLE_10_INDEX 0x00000029 +#define IO_CTRL_LNA_ENABLE_10_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_10_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_10_ADDR, value); +} + +/* + * @brief LNA_ENABLE_11 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_LNA_ENABLE_11_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000A8) +#define IO_CTRL_LNA_ENABLE_11_OFFSET 0x000000A8 +#define IO_CTRL_LNA_ENABLE_11_INDEX 0x0000002A +#define IO_CTRL_LNA_ENABLE_11_RESET 0x00000698 + +static inline void io_ctrl_lna_enable_11_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_LNA_ENABLE_11_ADDR, value); +} + +/* + * @brief PA_ENABLE_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000AC) +#define IO_CTRL_PA_ENABLE_0_OFFSET 0x000000AC +#define IO_CTRL_PA_ENABLE_0_INDEX 0x0000002B +#define IO_CTRL_PA_ENABLE_0_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_0_ADDR, value); +} + +/* Field definitions */ +#define IO_CTRL_PA_ENABLE_0_GPIO_IN_BIT ((u32)0x00002000) +#define IO_CTRL_PA_ENABLE_0_GPIO_IN_POS 13 +#define IO_CTRL_PA_ENABLE_0_GPIO_OUT_BIT ((u32)0x00001000) +#define IO_CTRL_PA_ENABLE_0_GPIO_OUT_POS 12 +#define IO_CTRL_PA_ENABLE_0_GPIO_OE_BIT ((u32)0x00000800) +#define IO_CTRL_PA_ENABLE_0_GPIO_OE_POS 11 +#define IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_BIT ((u32)0x00000400) +#define IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_POS 10 +#define IO_CTRL_PA_ENABLE_0_INPUT_ENABLE_BIT ((u32)0x00000200) +#define IO_CTRL_PA_ENABLE_0_INPUT_ENABLE_POS 9 +#define IO_CTRL_PA_ENABLE_0_SLEW_RATE_BIT ((u32)0x00000100) +#define IO_CTRL_PA_ENABLE_0_SLEW_RATE_POS 8 +#define IO_CTRL_PA_ENABLE_0_DRIVER_PULL_STATE_MASK ((u32)0x000000C0) +#define IO_CTRL_PA_ENABLE_0_DRIVER_PULL_STATE_LSB 6 +#define IO_CTRL_PA_ENABLE_0_DRIVER_PULL_STATE_WIDTH ((u32)0x00000002) +#define IO_CTRL_PA_ENABLE_0_OUTPUT_PAD_STRENGTH_MASK ((u32)0x00000030) +#define IO_CTRL_PA_ENABLE_0_OUTPUT_PAD_STRENGTH_LSB 4 +#define IO_CTRL_PA_ENABLE_0_OUTPUT_PAD_STRENGTH_WIDTH ((u32)0x00000002) +#define IO_CTRL_PA_ENABLE_0_SCHMIT_TRIGER_BIT ((u32)0x00000008) +#define IO_CTRL_PA_ENABLE_0_SCHMIT_TRIGER_POS 3 +#define IO_CTRL_PA_ENABLE_0_MUX_SELECT_MASK ((u32)0x00000007) +#define IO_CTRL_PA_ENABLE_0_MUX_SELECT_LSB 0 +#define IO_CTRL_PA_ENABLE_0_MUX_SELECT_WIDTH ((u32)0x00000003) + +/* + * @brief PA_ENABLE_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000B0) +#define IO_CTRL_PA_ENABLE_1_OFFSET 0x000000B0 +#define IO_CTRL_PA_ENABLE_1_INDEX 0x0000002C +#define IO_CTRL_PA_ENABLE_1_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_1_ADDR, value); +} + +/* + * @brief PA_ENABLE_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000B4) +#define IO_CTRL_PA_ENABLE_2_OFFSET 0x000000B4 +#define IO_CTRL_PA_ENABLE_2_INDEX 0x0000002D +#define IO_CTRL_PA_ENABLE_2_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_2_ADDR, value); +} + +/* + * @brief PA_ENABLE_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000B8) +#define IO_CTRL_PA_ENABLE_3_OFFSET 0x000000B8 +#define IO_CTRL_PA_ENABLE_3_INDEX 0x0000002E +#define IO_CTRL_PA_ENABLE_3_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_3_ADDR, value); +} + +/* + * @brief PA_ENABLE_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000BC) +#define IO_CTRL_PA_ENABLE_4_OFFSET 0x000000BC +#define IO_CTRL_PA_ENABLE_4_INDEX 0x0000002F +#define IO_CTRL_PA_ENABLE_4_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_4_ADDR, value); +} + +/* + * @brief PA_ENABLE_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000C0) +#define IO_CTRL_PA_ENABLE_5_OFFSET 0x000000C0 +#define IO_CTRL_PA_ENABLE_5_INDEX 0x00000030 +#define IO_CTRL_PA_ENABLE_5_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_5_ADDR, value); +} + +/* + * @brief PA_ENABLE_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000C4) +#define IO_CTRL_PA_ENABLE_6_OFFSET 0x000000C4 +#define IO_CTRL_PA_ENABLE_6_INDEX 0x00000031 +#define IO_CTRL_PA_ENABLE_6_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_6_ADDR, value); +} + +/* + * @brief PA_ENABLE_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000C8) +#define IO_CTRL_PA_ENABLE_7_OFFSET 0x000000C8 +#define IO_CTRL_PA_ENABLE_7_INDEX 0x00000032 +#define IO_CTRL_PA_ENABLE_7_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_7_ADDR, value); +} + +/* + * @brief PA_ENABLE_8 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_8_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000CC) +#define IO_CTRL_PA_ENABLE_8_OFFSET 0x000000CC +#define IO_CTRL_PA_ENABLE_8_INDEX 0x00000033 +#define IO_CTRL_PA_ENABLE_8_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_8_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_8_ADDR, value); +} + +/* + * @brief PA_ENABLE_9 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_9_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000D0) +#define IO_CTRL_PA_ENABLE_9_OFFSET 0x000000D0 +#define IO_CTRL_PA_ENABLE_9_INDEX 0x00000034 +#define IO_CTRL_PA_ENABLE_9_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_9_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_9_ADDR, value); +} + +/* + * @brief PA_ENABLE_10 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_10_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000D4) +#define IO_CTRL_PA_ENABLE_10_OFFSET 0x000000D4 +#define IO_CTRL_PA_ENABLE_10_INDEX 0x00000035 +#define IO_CTRL_PA_ENABLE_10_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_10_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_10_ADDR, value); +} + +/* + * @brief PA_ENABLE_11 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               1
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 0
+ *   07:06 DRIVER_PULL_STATE         0x2
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_PA_ENABLE_11_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000D8) +#define IO_CTRL_PA_ENABLE_11_OFFSET 0x000000D8 +#define IO_CTRL_PA_ENABLE_11_INDEX 0x00000036 +#define IO_CTRL_PA_ENABLE_11_RESET 0x00000698 + +static inline void io_ctrl_pa_enable_11_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_PA_ENABLE_11_ADDR, value); +} + +/* + * @brief SPICLK register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_SPICLK_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000DC) +#define IO_CTRL_SPICLK_OFFSET 0x000000DC +#define IO_CTRL_SPICLK_INDEX 0x00000037 +#define IO_CTRL_SPICLK_RESET 0x00000318 + +static inline void io_ctrl_spiclk_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_SPICLK_ADDR, value); +} + +/* + * @brief FWR_EN_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FWR_EN_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000F0) +#define IO_CTRL_FWR_EN_1_OFFSET 0x000000F0 +#define IO_CTRL_FWR_EN_1_INDEX 0x0000003C +#define IO_CTRL_FWR_EN_1_RESET 0x00000318 + +static inline void io_ctrl_fwr_en_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FWR_EN_1_ADDR, value); +} + +/* + * @brief FASTWR_7 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_7_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000F8) +#define IO_CTRL_FASTWR_7_OFFSET 0x000000F8 +#define IO_CTRL_FASTWR_7_INDEX 0x0000003E +#define IO_CTRL_FASTWR_7_RESET 0x00000318 + +static inline void io_ctrl_fastwr_7_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_7_ADDR, value); +} + +/* + * @brief FASTWR_6 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_6_ADDR (REG_IO_CTRL_BASE_ADDR + 0x000000FC) +#define IO_CTRL_FASTWR_6_OFFSET 0x000000FC +#define IO_CTRL_FASTWR_6_INDEX 0x0000003F +#define IO_CTRL_FASTWR_6_RESET 0x00000318 + +static inline void io_ctrl_fastwr_6_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_6_ADDR, value); +} + +/* + * @brief FASTWR_5 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_5_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000100) +#define IO_CTRL_FASTWR_5_OFFSET 0x00000100 +#define IO_CTRL_FASTWR_5_INDEX 0x00000040 +#define IO_CTRL_FASTWR_5_RESET 0x00000318 + +static inline void io_ctrl_fastwr_5_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_5_ADDR, value); +} + +/* + * @brief FASTWR_4 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_4_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000104) +#define IO_CTRL_FASTWR_4_OFFSET 0x00000104 +#define IO_CTRL_FASTWR_4_INDEX 0x00000041 +#define IO_CTRL_FASTWR_4_RESET 0x00000318 + +static inline void io_ctrl_fastwr_4_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_4_ADDR, value); +} + +/* + * @brief FASTWR_3 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_3_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000108) +#define IO_CTRL_FASTWR_3_OFFSET 0x00000108 +#define IO_CTRL_FASTWR_3_INDEX 0x00000042 +#define IO_CTRL_FASTWR_3_RESET 0x00000318 + +static inline void io_ctrl_fastwr_3_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_3_ADDR, value); +} + +/* + * @brief FASTWR_2 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_2_ADDR (REG_IO_CTRL_BASE_ADDR + 0x0000010C) +#define IO_CTRL_FASTWR_2_OFFSET 0x0000010C +#define IO_CTRL_FASTWR_2_INDEX 0x00000043 +#define IO_CTRL_FASTWR_2_RESET 0x00000318 + +static inline void io_ctrl_fastwr_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_2_ADDR, value); +} + +/* + * @brief FASTWR_1 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_1_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000110) +#define IO_CTRL_FASTWR_1_OFFSET 0x00000110 +#define IO_CTRL_FASTWR_1_INDEX 0x00000044 +#define IO_CTRL_FASTWR_1_RESET 0x00000318 + +static inline void io_ctrl_fastwr_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_1_ADDR, value); +} + + +/* + * @brief FASTWR_0 register definition + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   13    GPIO_IN                   0
+ *   12    GPIO_OUT                  0
+ *   11    GPIO_OE                   0
+ *   10    GPIO_ENABLE               0
+ *   09    input_enable              1
+ *   08    SLEW_RATE                 1
+ *   07:06 DRIVER_PULL_STATE         0x0
+ *   05:04 OUTPUT_PAD_STRENGTH       0x1
+ *   03    SCHMIT_TRIGER             1
+ *   02:00 MUX_SELECT                0x0
+ *
+ */ +#define IO_CTRL_FASTWR_0_ADDR (REG_IO_CTRL_BASE_ADDR + 0x00000114) +#define IO_CTRL_FASTWR_0_OFFSET 0x00000114 +#define IO_CTRL_FASTWR_0_INDEX 0x00000045 +#define IO_CTRL_FASTWR_0_RESET 0x00000318 + +static inline void io_ctrl_fastwr_0_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, IO_CTRL_FASTWR_0_ADDR, value); +} + +#endif /* CL_REG_IO_CTRL_H */ From patchwork Thu Jun 17 16:00:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4DCAC2B9F4 for ; Thu, 17 Jun 2021 16:08:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 898DF61425 for ; Thu, 17 Jun 2021 16:08:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233868AbhFQQKQ (ORCPT ); Thu, 17 Jun 2021 12:10:16 -0400 Received: from mail-eopbgr20072.outbound.protection.outlook.com ([40.107.2.72]:4749 "EHLO EUR02-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233724AbhFQQJJ (ORCPT ); Thu, 17 Jun 2021 12:09:09 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TfbuPU1GYJdmLbq4sqb+GUVC3ambpqzj90LvddJFMG+zL+P7u4qTXHz9PK55Kq2cfL9KksHSHT3fJie2Sw0tVPa4JA7gQ24ydlzbnq7nBg/+psYkuWn8Ih+UHCclYSEqxg2FBKu0y/ov333oUDuCIFAIW0K3mKjj4g9vrasw9DH8uAc8WtE4lPHZpg+vNbJD6Zuo/zKIPICFPrzlsiuMX1FZjDMcT14D45SwXkHndkPontus6LdjFdoLlctlbRv40CiUuSO11xDDqMGRzd7Kv1jn886pTcqarqcG9SFAuVhpUv9CWKBVJTUVqdSwvu+ikoXevyFqaJ8Za3X/0Of/rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V6Jp2ZWDpmXuvhy2UC/IlOvFWHexJBSfLpvrJKhbvxI=; b=nfSdoh5N057jOow3jReB6NasyGsOZ47y2GZN0ZXn9QmJakl8XUm7dlIfpfUNWYBiKdjfv888N9eYY9d8NpnawkFkMp5cV12wrxB38UAn5gGV90fnTsX85hhKa5zmWGAG1HKkC7w/xj2mqeVIZnJmrZCzkMnCtEFex4hTqNo3zBIQI7m0Pf3b76+VD67shqYI2W0jCB7SyE7eFB2UNVBg54IyDB0+dX3PZYWNVkK2y1rU2YKbhLcG/Kl3ko7tUj+xPy+51ZMZVYEbIcFmf9HKKJIeaka+EOsp9xfpkiCN9UGa0JmLx1yPelHxQLTE6RWM7LHhm0OAKXT2XN0am36FGA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V6Jp2ZWDpmXuvhy2UC/IlOvFWHexJBSfLpvrJKhbvxI=; b=tSEoR/Iog/Z6GqV9wJWL0oa5PBIXoTyIA5Fjo9y5CAQo6jYQlf4gaCjmBDOSDxO4jpOy2YTXTNIr7cyM8rSEPmVA62ngSsdu5CCYbLwufzslpgTNB+rH7sTlRPuMC33b1DY09fzHHArzY3Psc99V7AFNijgg5B+yLdTHZKYEbvQ= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:25 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:25 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 155/256] cl8k: add reg/reg_lcu_common.h Date: Thu, 17 Jun 2021 16:00:42 +0000 Message-Id: <20210617160223.160998-156-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:23 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 40a4952f-88c8-4285-eeb6-08d931a9b736 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jHIhKjXDnnV3h6TENEfWMwfLVhiOwNznQ9+BHKvsQBVCt56LvVLiP9nDeOf6t01aCHWjeQuTkvONcpw4hQFWaz+skghp5k2r6xjygZ7q74UqugrXpF9hoSpPKicGlOrunLtl3FRW+cUOhKTIIss2ujznm6DPJ6UdwEoHa8NDoD0QVG7TJ45OY8Yckn3TQvoZVZsJ8xKa9lesSskoT7w/o9Z4pdM5oLb1rGAMmNIQW8cg7tmprAmCXl6en89DZOEGfuxyHzBpns3sjTKeqcDwEtGRt021wjTK1mFW/vQppDPm5R+VPl0sYEw0QOyoPOnN5shtuZspwhNMD6mvsoKakd6iHSfzrA62QIllHB9ZJ0vRRR0jAY3YmAFlIT1Uur6rOGA4ByWkZ6aj5d0f88eGoedaY+JuB16Hur2nw+2pdmwOBIubAgSsgwAFeWkpbP8Kxnzh1gaGVNaS2RibyNFVgP9gd4CaMfFy9yScyLUnmaadUawpYKdhDsOyAVK5YUET6OoYBCWyl/PBb7Lyc4AjahYNHJzPvaN/g7bhBiTZbGr2lh80d2OO82o/b8bLTEwanzRF1FiA4z09TGlUvkeuAXHiNwvWiUHeVPUgNGmlbrx0tI/Q6wm7apxlZHIE1swYAwojOM5CL4ey/iShq4av9+dJltQIwMXwtE4yaKHut0/dsG/10iYLiqzqz/HCQZn5bZlHEg8x3h9ZT0rnCjuwdQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(498600001)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ogyg171KiYXP3nKwYn24WOhZiBZ6tKLLK2GdqhJBGahy1pLsNl/Sdt0VrnKygPE0AIxPd2ZtPreUHJesoiLOE+tmzgkjiUG8r9yg3JqOgBuNtMLWKES5aOk1QhQsqFg42hymRz8ZTbNGUTh/4o1s/4Q+EZ2hWxykXn7YKs7JxochBOgnrhRhLMDfrdxt3ImClwD6SzpRUFYxCiyWyU73f8HBzQ324z/bZ9yxIE1TPThNvgKpGdLkvfL6n/eaQq/qI+nKaXJpTlYzNEgrp/LYUYn2PlBTvsxsNxOQ2oXBEyySk4IZaG8Z11zQfqUJ4fTbQg/OhkfWENxLMYpDMLPZSN7hOOzJhaB2UXQfasLqtrCfRaLE/UxqVlIzLewc2tBUFPgj7bue6YHrw3hK1zCVdh4A/fUW+bsxaeKOi86fqmOISkhlpa12p93lS8Yu1Mwu4tLieljZ3wFYs9npSSiWHMpDVDnVwcMsUb0gJhJRrijvhYAA7FHzffSabQWJ0Y4aa+hW7SJorxGZP2gMIvGHU8Bwz+m89jIcPOmGG83idW6TE6BySPpfWQx4o4jtIPO9pjRCxWmeLiV5tAoDcUnYwthI9E5GCB3IiVNYeYSp7OzkvqaivQipKjfzc+B+AwdSMhucr5O8quULiIA88TgUggJXMnwZ7aXLm13es0cktJPXH5R9McWKIwGkbapZmXHo4IveOoPVso1eBzo98FHRA3ShCASK57rdIqr1vK3pyPNExXppKExMcU8J3dbvJQhT59Ourw1aTk3xXyAIYSGs/eYa4TlMQUlOrjg4eu5eZZPvn2gcXjqv2D41HwlEwFk2mrjjxupZAghREBaLt1cRKlQ7gb31jvZaVhlXL1F0khcU49VGju0PMy5FGEExs8Rz7EWgq525dB3TZH3vxWRhc4i1YjjPp90BP4VuG6C6S6ohjEOCvlYx8LVxB4ef1636+vXHUa8AIMRj8tAERfa4A26aG1U73S8k9liJpnSk1KImBygsI9ZIRd9taGHGe7bb3TP6usvBYKEXElwaRH5EAaUba88BSq0QECq2OHzeEbsRhL0EXvzxfZiVqveWgZw5KaVYd0ihL6Ld5OE04qTp0phUe2IDtVPfUk0aJQ0cwa1qUUhH+KaM0Li4M50uX3hZX0+0JlOIi5WN+s6HtBc1KLQWmO/oOw96ns7dKE53utZe+LdB9g6/Rd0tPyJHVFRvl1AkPmKZmR6pgUS9OGDgNgM9eQmrHJLV3qjIYSBySXZnTCgxG4fNarxQALUn0QrnjAGahNpOLOpQuEAEYKkY/FgenZdwnn0oLcnYENHI5bqRlFM5x6j2M4+llAYn4rD/ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40a4952f-88c8-4285-eeb6-08d931a9b736 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:24.4034 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: apOPJCC8StTxjWbQLhy5dgHgFHJYDMNnVB4ciT1L4HRG48xTHhdSwBBPpRuBBPSpqImmAHvq5GnDnhVIWKJUpg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_lcu_common.h | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_lcu_common.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_lcu_common.h b/drivers/net/wireless/celeno/cl8k/reg/reg_lcu_common.h new file mode 100644 index 000000000000..0f4695b7f66f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_lcu_common.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef REG_LCU_COMMON_H +#define REG_LCU_COMMON_H + +#include +#include "reg/reg_access.h" +#include "chip.h" + +#define REG_LCU_COMMON_BASE_ADDR 0x007CF000 + +/* + * @brief LCU_COMMON_SW_RST register definition + * Software reset register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    00    SW_RST                    0
+ *
+ */ +#define LCU_COMMON_SW_RST_ADDR (REG_LCU_COMMON_BASE_ADDR + 0x00000048) +#define LCU_COMMON_SW_RST_OFFSET 0x00000048 +#define LCU_COMMON_SW_RST_INDEX 0x00000012 +#define LCU_COMMON_SW_RST_RESET 0x00000000 + +static inline void lcu_common_sw_rst_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, LCU_COMMON_SW_RST_ADDR, value); +} + +#endif /* REG_LCU_COMMON_H */ From patchwork Thu Jun 17 16:00:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81E37C49EA7 for ; Thu, 17 Jun 2021 16:08:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 61F996141F for ; Thu, 17 Jun 2021 16:08:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232095AbhFQQKX (ORCPT ); Thu, 17 Jun 2021 12:10:23 -0400 Received: from mail-eopbgr70043.outbound.protection.outlook.com ([40.107.7.43]:64066 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231148AbhFQQJS (ORCPT ); Thu, 17 Jun 2021 12:09:18 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iVt1ugnLhweY4OvRhP0eovv84fHt7RyB9mXgbg4otVSGliUl3qnZJ4cpiKgRNcz80yl/gG3oxUSVTco8/f6ILD9aldJkYD0BCcnOYK/d9MFh10SCfUFhxSSxlm1kos2vQ09Um/5RX6KynVlYmSEAxH6jpZCwNQtZHDLdDxUgoaHcusk6+FCuK0b1Du9ApsAKQwocMgHfpazaN/sNa14hSqBlCWK4TqCuhyfiRJSNGhJPrRBVG1OtPpHf26hq5wKWF2KXFyRGCK6oOobQkCshKbRZeN/WFdUDDZBr1sx0vh87GoRSgh048ss923KIVgQHuvjsRq/MIEGkeH40FGSHRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ciE2nHticaYgdU77Q37QQJQhA+HC0FstWCGUqK1pcHE=; b=Mto05UaojsyMRAQ1MY3J7qFWF+yrl7jbAt5pL3DAxdkIXvReOepfV0zG5jhhxRdx2GxhgMYhJDr4eIYciG1BKuFnIO3gKSn3lFU2Ze8QVkhdnNPwwV4cB5Dm7Opr5obQuto5NVDVnmb0Abwv/fBr76sqisJz10lLu86LZS4j72yWPEegbdJZ2Sku5Ig6lZQ2/uIHPksiaWD+8FnboRSkyHZ0l0dDO4TVUP/vRyK+0jf/gj0oNLgPYdPDhQoaduYfgnmJRsrbm2NAsNkKxz23YhbkTz+UBeDi3iHk9XdSybBUmo1E7ZZIdeADC794jWZjFsHmItnOfGB8z6N431I+Zg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ciE2nHticaYgdU77Q37QQJQhA+HC0FstWCGUqK1pcHE=; b=nQGZlNDbpMSxapTL1a/l4pHqUdZvqV7bHxC8a6iMazgPgR81Fi2rsbx3cdTPk1wSD0gzszw983rbOS4GABtFDlPY4HVj9LwsE+RN/+0iM0y/wIG4DikUC7Q/p43lkdRMWyFmG2LYwGfdpHLfvuIj4uJCEN4OMkkWvyxQpJM17tM= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:26 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:26 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 157/256] cl8k: add reg/reg_macdsp_api.h Date: Thu, 17 Jun 2021 16:00:44 +0000 Message-Id: <20210617160223.160998-158-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:25 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5fe4f209-b8bd-4546-4e83-08d931a9b86d X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ap4o8N0zVifg9AArJqqqOvRRngZuWSeMaQBUk/Gr3mqOYa+TLQL3SO5qlryNjPxR7YPI62b8OgfJknSBz0TK3J5X1wpy70baKN3b3sj7N3JOaH0b5Hr4flEXbXHcrkmDGdwab5zuwl8b+7M1aAfQeWsRgvEAtK8dlbaZN+MANYtA38iOam9Jg7ATUe004El6WE7ce36hlRuGIucvEXtkG1500h/G85yV/8iddrScIHjY8Vsj5lisftSIUfj4GY4KJ3BZnbS5FXn6M2yJpmovB7jBSqLCH4yozXRShCH+q/zCUGCuIGaXhBbMW6qCsxdObwe3lUbkxOV/KZlKGTUMH+CJuM46tvZZwxNG84qU8EDurVTsQQOu4iBtcxojaaEtYO3LcW7N9so2Gubpy5Ooc8D1kmUOtQj+51GyglbY6YTMyzZCc+Ir3S+hNMhDtZwYjsmXesonZGKGXoCMkWISEGOsAN8G36XikoaZ1UZOxFiiIGNxHfNHXRI6bMVc5FuQHiDwhUtLtDdEbq1Wk/KWJiy1MpCf0cCKsL+Mq6ccetOhI8oA2bDqyiaDhpa/lpE8YNHkjWkLKyZaPdQVcAyf3zWl53kzN8U/oh/mVE0rWNx5ks/1Kspzpm7e9FJQBK4HfnNZY46hcfoJDkSC/GWbQilYiPWAxw0i6gpRIwBAq0mTMABVGmcavePK+M/4ObrGgd/MDwrklt+mayM9DUOMwQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UVz9yDc3Vjk1x3XBhTXOmKeHF6AmOtwFh+Y8LcLDyeZ3yblGKD0tHDsybIfWsbvFzPmPRWFM0An/FQpxtu+VWVTXENnOKzXrhdggMpAalczGjEJjyYzy7SNtUIWWeI2zmGwWvornlX9t4p1il0DZAxa/dzQlABQ1wpwR8vniDCCTlu9USydUpBYF/QQvjz224S5ByGsDvvLZdAvHYsLNMQ9l6FaOmQtG2nkkXSRq6skNVOTN5Ajc6ePAAxVtY2/lvDNhj/6GSzwAoZffYpNpi6pwvpYR+KyBH0j+jWmulqtwUcexqnZAX+MF2Uq6teUkYVmmjYD31/AVHK1oE/afJ8k5QeKPUNfIRff1Wiac88zW3bEmMlMTGl84s1Ae3IP7LpS8F49zL/0D7ZTEMvZu75dhCJN2f8wV8CLRXgiuIzfs0yCO3Je63KhJJMYI6nWEMRffyCn+YBzx5iMQH9M7oAJo0bVbSwm3SoG1wo+/guumLqu14HERfuP7LcXY2Z8vwhpYvT18u7w/v10HwcxhOoUzEL00X0qIGI05tQoIDo72NTB4FvBJKzuW9LC0t2SFR0e0SmnPxMs5b2/xU3HbimXCv69I0uzrEkjPgYFhFxAH9vrSZwPEeJUZnA4Nr7q9iZ4RC0ZGSjZMGV1LPP6y+CXMa6MCYlPoM872emflgoen2BCe3JPCY1K7gmF2AdnImxvtp+YYBQsSthwu6YHtEIb8XBPP9BbHSOTCLs895S8clLz3AS0caYS+e/f3GXi4uXvGp1q9sOkNX7MRIQeElxTTWavWsEhqn51mudklS6qzSJfL7xXwI2eYnZuilOaKfaIVgNunnhev12ytEhBCADZBZpKYQmojiFgJ+Z6j7Mu6T77ubQ/MLuJw4UQPgOtR5POYRCEkG+6HNi1skZBJJn3hCRqFkK4JyWDBXt5JDc437S7ayUv1/ADJi5Btyd8jhN9cX0fxL0ByiqUTD+DTuJKmmE16I5LhU7wlhPKdlDSbNChrTdsxpQ1upFlxBVReb/BE1Zm/rSFnn85RNQnhvd/QYDq1JW5PpTg1SaLS9U27rzNHb9J0agaYTOZObAmUf2XtS7eGT0DZ2OQxYXsFgSrT4x3P8vqQBk4kKCwX/vh4OmFn5jMrMbFutfCYIFgtDPlfGwU4WdtL3xL+Rf1E1yCHJjyLcO9dLcq97d1HW/XT6Q9E+WH2guXBW0ins1g6aD9ma0mx7/BGiJ81BGBOubwUoAi6ywIBEamn7/ozSjxV1PmrVVKtYb6OrBsQzj1cbrJG1QEL2VBg11hyeZMWbDPxQYk+tQ8TQ88uDe7rLD7rFREfiM93ire6zJ3sNp6D X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5fe4f209-b8bd-4546-4e83-08d931a9b86d X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:26.4524 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ChSVmvvlC1KsMHRfeyjFb69Fl3j34DlC9XXhwlrpEHswSNle/g48G5spuROjKaeEVSFTkpM2LmUFF/jWH+fG0w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_macdsp_api.h | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h b/drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h new file mode 100644 index 000000000000..434f963650a2 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_MACDSP_API_H +#define CL_REG_MACDSP_API_H + +#include +#include "reg/reg_access.h" +#include "hw.h" + +/* + * @brief CONFIG_SPACE register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:26 ActiveAntennaSet          0x0
+ *    25:20 RxCckActiveChain          0x0
+ *    19:14 RxOfdmActiveChain         0x0
+ *    13:08 TxCckActiveChain          0x0
+ *    07:06 Band                      0x0
+ *    05:04 ChannelBandwidth          0x0
+ *    03    OfdmOnly                  0
+ *    02    RxSensingMode             0
+ *    01    UpdateSync                0
+ *    00    StartupSync               0
+ *
+ */ +#define MACDSP_API_CONFIG_SPACE_ADDR (REG_MACDSP_API_BASE_ADDR + 0x00000010) +#define MACDSP_API_CONFIG_SPACE_OFFSET 0x00000010 +#define MACDSP_API_CONFIG_SPACE_INDEX 0x00000004 +#define MACDSP_API_CONFIG_SPACE_RESET 0x00000000 + +static inline void macdsp_api_config_space_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, MACDSP_API_CONFIG_SPACE_ADDR, value); +} + +/* + * @brief INBDPOW_20 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 Inbdpow20Pdbm3            0x0
+ *    23:16 Inbdpow20Pdbm2            0x0
+ *    15:08 Inbdpow20Pdbm1            0x0
+ *    07:00 Inbdpow20Pdbm0            0x0
+ *
+ */ +#define MACDSP_API_INBDPOW_20_ADDR (REG_MACDSP_API_BASE_ADDR + 0x00000974) +#define MACDSP_API_INBDPOW_20_OFFSET 0x00000974 +#define MACDSP_API_INBDPOW_20_INDEX 0x0000025D +#define MACDSP_API_INBDPOW_20_RESET 0x00000000 + +static inline void macdsp_api_inbdpow_20_unpack(struct cl_hw *cl_hw, + u8 *inbdpow20pdbm3, u8 *inbdpow20pdbm2, + u8 *inbdpow20pdbm1, u8 *inbdpow20pdbm0) +{ + u32 local_val = cl_reg_read(cl_hw, MACDSP_API_INBDPOW_20_ADDR); + + *inbdpow20pdbm3 = (local_val & ((u32)0xFF000000)) >> 24; + *inbdpow20pdbm2 = (local_val & ((u32)0x00FF0000)) >> 16; + *inbdpow20pdbm1 = (local_val & ((u32)0x0000FF00)) >> 8; + *inbdpow20pdbm0 = (local_val & ((u32)0x000000FF)) >> 0; +} + +#endif /* CL_REG_MACDSP_API_H */ From patchwork Thu Jun 17 16:00:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C48CCC2B9F4 for ; Thu, 17 Jun 2021 16:08:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AFDF861426 for ; Thu, 17 Jun 2021 16:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231526AbhFQQKl (ORCPT ); Thu, 17 Jun 2021 12:10:41 -0400 Received: from mail-eopbgr30061.outbound.protection.outlook.com ([40.107.3.61]:14471 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233806AbhFQQJn (ORCPT ); Thu, 17 Jun 2021 12:09:43 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qqw2GBnKzNgLAIPU9EMoj2GsHVqhIjCk9Sn0NTPFFsMUZj0ZQy1NiOjKAkNCcJdiqRKZPYUSCXlSl7hdKOCRwvJzfDF0G+l++qrHeI8lHgy9INdY78tmKuEQcG5YDji4mFCpEq2EWV0Ol8Ubh3r3Ss/4OlTyYv1JObNjjxy3+RW+xhvl1wUKcA1Wa6zsnmaMCFBtDERxqnmP+5jB1d3ZDa5dN5rSFLJS4FAVIs8iruV55DPZyRymP4F4cKmhTV6ocS+Aly5XQIfYrFDEkf6RY7kF8ECQrg84diD6fc08ny3VDAbFQs3wJl5Bkb8OXsa6K3BrTI7kN0ciWYQZ/cQgbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OyKC5Neenhlm6pI75Yz87G8rumom7TZaTC46kjH8xrQ=; b=kAAPV9Kv5pRv/iPryu/MkLCHc9xOGgssFFBRwnDXtT1LPDtQfhyWaZv5BbqgMvAAugewSZaWxxY3+OaJZh/f+sr+Rj/VA5tb+gpfZn/SE9Z0/x1PT4WEMHq0xnIi8K/JK+Rsvr4sJum6CSFVHis3kP94zj/Vmv/Eg23ERVexOpKIULXvSidS5cs+q0vD4uor3jWADhQTJunhCZSULiXMBEbJB1QtkHwRl9pPJn22L6AzxnEzOSHzv+WXuN30RGb21X0yGlhVegWDz9t3fX18nOga3vktIMbvwA9tSi+XyQERC1lXX7juj98T5v/wD0LzC2y96WMYTtKfk1a27sCiEA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OyKC5Neenhlm6pI75Yz87G8rumom7TZaTC46kjH8xrQ=; b=PqEHa3ZRYi493A+jV5/yTEp/t9V+O7Jlz+JETVVZHuilzJdG7XdYNqNm1tERBCrYTYMMT85YdNoK02nn60RcJiHkKYn/qwKD1AShHENtwCt5mK8GbCyX/GxYVNJYKaKGJ1xBqDlZWkcEhyo3N7HTZe55IxcOWlphMApR1zjVp+s= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:27 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:26 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 158/256] cl8k: add reg/reg_macsys_gcu.h Date: Thu, 17 Jun 2021 16:00:45 +0000 Message-Id: <20210617160223.160998-159-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:26 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1ea0da61-9612-4ca7-5e2f-08d931a9b90c X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lQXPgoX4WeKk550iMRD70aph0aQ41YBY3ZKIabj8gRI/QVkPNdKHp+c3z+55guinteTa5G6ZuDylx45HfljFeehyOLxmYjoW57YfQmDLtTVIXmSCu3yrf1d88/UEScWNXH1MWtW9tzEVh8jm58It7CAklSunuofMeKiLQXiGfR6fHbsSOwN3yGG3zbfpYdcr2RGJEIHHm1lwkmWy+rttP/40ArQGrB1VNDPYfCxQ+d9yuouOuwcomXE19ZW4gll6Va9wTBQTQwRj+0bPGCtOZc8GNIQhyuD2FKn3IsUVrxHIp93cGrDvbvlAdSC4oBDc9U6GxJn8S3vxsHyxFG1GXZVHttsJCLYvWjzVOp4AvYic1oMobEuPVZ3RBxlgz2fh3sWaZB4+w4XifQfSn2Jzeo+HGoeSo3iRW7h1baq0EZnfWIbxzl+PGBZdnZbdKt3Wxl3/xEQHfBpmMG+s3jid2EfKA2sq31no2nX9UBIGr+F3UecrycZGqruQuMiyTEMomF8LiPpUPIIdpbz6PaV/dI8+NA/ZDLkL0vbRJKHSeYtrzpqggxdv02IkMhwiUqGNfaqg7s8bmBR0Y0lfIKCF25V69xJpZdcBCLWSJMTPRsjAwTE3y88sNXDVE58o+I6ZoIp+5hl+Wxkp5pvdf8im3HJWG4VRnbcMmn64TzICEJAZHSWRf6F1iJjDIgasEKu9tRTiIBhuyePoABkzYoG/Mw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OXqJnNkXlw6yGiQQcSYzA5TU8J11VfLBkFJD3jWUvuEevAWVzQAm9yinb8ZNYMREP651L7IJtcH1uBZ8sgsOZ9o652aThQ2/eH2CzLXKRbc/46mSckK78EfiyKr26X6JAaKQ9iqy3U4vHLPtPQO+y12KW+I73bzhpKyp4HZ2+iE+hWmjn4vvAz/OQNPmockYb2dkIml8bXCl2ne5BBdXs7GMb0McbgOj+hxr99MwY2EzfShYGALGUAbIWA2ufWfQlcB3qW18+pSy8aC0p6XAudYmnn4LxL0GbDGztcZ4VP63fpR17EEhvZW4qOwERVEMOmrwaTcJFbbLUPhFaimycdTIZ1DWdG/qALH6ga+sRpqJ34+v7m07AMAl7gHPHvtoPErC/ZIOcinX+UKe2wwDcvqc+6Cs3UWp14e1tn9CDNBDCYFco3lCZn0ran5/mzojBrEvmOGueLhFVLqKmVnUqt2/qgN8hWv9DgXuLRJ91PtgMxvvRLdWxtMU2WL41ufa/gPQLVRI+bN5A4pimohHVcfOGv6Zc3gQLE7mfYEqn3uH8i2LI+x1iCJ5uFxTKTotCIO9f5hlNXOYNzkliKDDJYPNhg7sfnrCml9aWovKDvSUtZnIo2Kd84AiWp+pXeJWnpXNAxNLBamHzt5Lvmm3nejB9VrgmlUYSDos5Be/AXa/cApA3TPkDSo1POQ3rPmt61ti9RTCanYQ/ZdUjPo4Y8w0MF1HoIirG4qxAKoA8LHkVTTCp682hU5Xx0uMTQH2BTVW52Vc3MiM8bxtY80MKaD4QUX0zBOoltFQuVjfASw78YTvi1/CZhKDHr8gbCfQbW1qL+TX4OYF3ym87cduPwDNTWcs59vph4cmW5XejGpBaIktztvkC6k2jfIvW8AWEHp5f5Vj+mQzHVXGxarxsywwsViTaFdXLgl54wu0j2/Hs2h4iuGhc++wht6J8ZtGioOVZIlzHJWnJ/B7qgEBwxgDsfj+x43C2pn4qwpVv4Y1h+Fw7gEXaSQYMwYL7s8lF0CF9mnc6k/qgNd0KjhJZeSGmn8vuJom43bLBesERNRJp706Dgn7M7IA5+AZTHvExyjIVKTcE4r1kVQLM11meQCh4PlJy9iYaUgGaHI9tCaWHyPXjtsCJr7b1IVP43yWGWil5nEC+5E4lTUwQPppFVUH6FZfbZXPB3Be3twp9nB/CbQHjmxxOvltIeKkRbIiJuawB6OK6Fw2x9vql97M3/RlyOVMjjUm9TH6EDbyQPlcR+Pw+h7S0jG3Homg/7NEVjVeyWPT2aUrrzs8qzjYF0mPh3bfulNlL+EmNej3vTZyyUy5J9ttynZ5XZxASbqd X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1ea0da61-9612-4ca7-5e2f-08d931a9b90c X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:27.4829 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2cv1PAcFKdOqkpE6vbcu7vTBWN2qEcf0fX9fAaJhiSlSGhMiD6VbcKcV0uTcbZhRnO0WGf1dBc9JHsa67VsnIA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_macsys_gcu.h | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h new file mode 100644 index 000000000000..41eb196f4b7c --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_MACSYS_GCU_H +#define CL_REG_MACSYS_GCU_H + +#include +#include "reg/reg_access.h" +#include "chip.h" + +#define REG_MACSYS_GCU_BASE_ADDR 0x007C5000 +#define REG_MACSYS_GCU_COUNT 63 + +/* + * @brief CHIP_VERSION register definition + * Chip Version 8000B0 register description + * 
+ * Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *  23:08 PRODUCT_ID                0x8000
+ *  07:04 STEP_ID                   0xB
+ *  03:00 REV_ID                    0x0
+ *
+ */ +#define MACSYS_GCU_CHIP_VERSION_ADDR (REG_MACSYS_GCU_BASE_ADDR + 0x00000050) +#define MACSYS_GCU_CHIP_VERSION_OFFSET 0x00000050 +#define MACSYS_GCU_CHIP_VERSION_INDEX 0x00000014 +#define MACSYS_GCU_CHIP_VERSION_RESET 0x008000B0 + +static inline u32 macsys_gcu_chip_version_get(struct cl_chip *chip) +{ + return cl_reg_read_chip(chip, MACSYS_GCU_CHIP_VERSION_ADDR); +} + +/* Field definitions */ +#define MACSYS_GCU_CHIP_VERSION_PRODUCT_ID_MASK ((u32)0x00FFFF00) +#define MACSYS_GCU_CHIP_VERSION_PRODUCT_ID_LSB 8 +#define MACSYS_GCU_CHIP_VERSION_PRODUCT_ID_WIDTH ((u32)0x00000010) +#define MACSYS_GCU_CHIP_VERSION_STEP_ID_MASK ((u32)0x000000F0) +#define MACSYS_GCU_CHIP_VERSION_STEP_ID_LSB 4 +#define MACSYS_GCU_CHIP_VERSION_STEP_ID_WIDTH ((u32)0x00000004) +#define MACSYS_GCU_CHIP_VERSION_REV_ID_MASK ((u32)0x0000000F) +#define MACSYS_GCU_CHIP_VERSION_REV_ID_LSB 0 +#define MACSYS_GCU_CHIP_VERSION_REV_ID_WIDTH ((u32)0x00000004) + +static inline u8 macsys_gcu_chip_version_step_id_getf(struct cl_chip *chip) +{ + u32 local_val = cl_reg_read_chip(chip, MACSYS_GCU_CHIP_VERSION_ADDR); + + return ((local_val & ((u32)0x000000F0)) >> 4); +} + +/* + * @brief XT_CONTROL register definition + * Tensilica control register description + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   21    smac_debug_en             0
+ *   20    smac_break_in             0
+ *   19    smac_ocd_halt_on_reset    1
+ *   18    smac_run_stall            0
+ *   17    smac_dreset_n             1
+ *   16    smac_breset_n             0
+ *   13    umac_debug_en             0
+ *   12    umac_break_in             0
+ *   11    umac_ocd_halt_on_reset    1
+ *   10    umac_run_stall            0
+ *   09    umac_dreset_n             1
+ *   08    umac_breset_n             0
+ *   05    lmac_debug_en             0
+ *   04    lmac_break_in             0
+ *   03    lmac_ocd_halt_on_reset    1
+ *   02    lmac_run_stall            0
+ *   01    lmac_dreset_n             1
+ *   00    lmac_breset_n             0
+ *
+ */ +#define MACSYS_GCU_XT_CONTROL_ADDR (REG_MACSYS_GCU_BASE_ADDR + 0x000000F0) +#define MACSYS_GCU_XT_CONTROL_OFFSET 0x000000F0 +#define MACSYS_GCU_XT_CONTROL_INDEX 0x0000003C +#define MACSYS_GCU_XT_CONTROL_RESET 0x000A0A0A + +static inline u32 macsys_gcu_xt_control_get(struct cl_chip *chip) +{ + return cl_reg_read_chip(chip, MACSYS_GCU_XT_CONTROL_ADDR); +} + +static inline void macsys_gcu_xt_control_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, MACSYS_GCU_XT_CONTROL_ADDR, value); +} + +#endif /* CL_REG_MACSYS_GCU_H */ From patchwork Thu Jun 17 16:00:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F161BC49EAF for ; Thu, 17 Jun 2021 16:08:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE1F561425 for ; Thu, 17 Jun 2021 16:08:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233842AbhFQQLB (ORCPT ); Thu, 17 Jun 2021 12:11:01 -0400 Received: from mail-eopbgr70045.outbound.protection.outlook.com ([40.107.7.45]:47334 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232530AbhFQQJx (ORCPT ); Thu, 17 Jun 2021 12:09:53 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=O5RVp74fuxAKTHJaqNx7tX74SXxss2K4URu/fIxkdj0KQHryEjQiMf940x2tPzBtpwqDl2b9vt9A6C2gF4cyLv74UVRUsR0guEYsdwOzK4flNBLp0qDC6EnZUC8hPJVVpTnHbJYJIBN2P0OfOZocRawId3AqhRcOBnvGp90fGrOaJj7yJbM9th4QU//L5nInkqv9oBP4CuQHMIfBB8Yu5987sLiAa9eWuVwgZaIJ5e8/18t+P3zYn5PaAIpYrzaIib/LI1r0rnwqqsg9Lx69zsxPCIIfHaYuRTe+W5yXO1owYoBZ+9wYL4i857dVoU04n8WRJ8pEmnaD4lNqIJ2Ftw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dTo6SbFv8Wp0G5khxnuSq5LelCyAqljcWREnXvbK0lo=; b=Xa5Q/OJku624argakzsPcipsLSvGryoxkEBWNdZEo8PyAaTjCqDFLsQwPqSekVnQifqQqBkEZvqVwau++VMr4yY0jstnkMiCTo4IjFFWBjl8buIw61Ut4GREdOSOY2Y+hGm8VR8wKwdL4DefX63adPPWUSI3Wv1TvqS12u8Lo6TiDdBCZOYixtzt/WelhHkZXDkf5iKGOYrx4m1kNH0GtdXfrLoGAR6Vas44OXRW5oibsNonax8mfUjKs8cF8xQldHKFB1D/WYEoZ5/LCO+ScaO1INtozA6Xzs7wXbWr9Jf/PQWZrjRm7xIpThuuOr0fsSJy0X0Z6a6ykiPJuHNEXQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dTo6SbFv8Wp0G5khxnuSq5LelCyAqljcWREnXvbK0lo=; b=EIDdYMy9tmleBbIvBMU+hDZgTPLzPFXpd078XQXhXzA2rbTNQamPoL/siSFp1KZvIk5WJhuF0uV7ddHaqn/yUEWw9NWh7CQxhxwnQENVD2MpxG1TONpC2BThzcMo4nC5MKsW2DU57ckKAa8cZZZmBfFM1cMXGfEfW3HMjVJ52QE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:27 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:27 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 159/256] cl8k: add reg/reg_mac_hw.h Date: Thu, 17 Jun 2021 16:00:46 +0000 Message-Id: <20210617160223.160998-160-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:27 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ed37ae2e-d6b3-4f4a-5d96-08d931a9b9aa X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:551; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gcwxiFa6l6SlBPK/KENEA+/VozlxA8W4BkSsLMzN3sn3JO6wit7jcniF2hrawYK4xZYltVRjwL0mPQ7gEUCFQcP046D8wFrwNqCZ9/KbnvA7jfCdkzxHSNbW40PW/ZOSf+zq5WvPItRj8BwL+IOjjOxQkZQulXil+hi/gqvznwF5EJSpyUBb/1rPQJcloak6g87LTC9Vxo+F6Rb7lQ0+d0WCxAX15Ru6XlQGZ5p66kBOjLcDV+JRa643ho/+VB8x+fZp+wY0uAgX8WQfWumdZB7idMSFOy0B205A3UlifE5kE9dUIqmyduXT3cmSHzpNonVYUq2k9HkQ6CYQ5+I76KmpZeUNqMM7FJJCEcv0qFNOWUtEbr2P7YhV5R8p5VjQ0aBtG6eMocruhrpZc0yWUfuRpwRNpw8DKCJMAxuXLN1YeskJTWDHfY329hXisE/uP+qsfNf+lz/vltlYP5wkQWT2yVXAwbiCuTYX/icYOP2hoHo9Kxm1eROsUG0yzyZdnVlc+NuXhPeY+Obf5G0IPKctiL8hKjXis+BsUrJ2vAF5B7ZOpWBOXSYZIKTIoDGj4BBpLOxDxsb58DrkpIs8fV5RciT/rREejyYVco50C0wemH1xvz7GnhIUcjJPh9mx8Z0iMSvM5Eilx8/T1h/U0UveB5sx3xz/eMzJTPfX97WRUM9Kll9G92EYZDYC9mZ3JLCs8bEo4/w+HMYEEOTD7g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(30864003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SMT7HLvYooZwA8O8kEHvCwO0+wgDszqyd1W/P8n/wqWDYA1RkPKwcv5cnuLSSAa27EObf9ePd964hK35x/obAg/LJiUVXzFW4jxarB3KUrIZZM9D0foDXCw+hgaWx1hUGaIyDm1jOpmu2glEZPoKy0N3IIh2WWIwtdwhyYAVUBpR2Wj2bnSMc9E7n2Re2TAcW4n6t5UDC7NNitojsWUqB8FJqpfyTvbhRHEGB/XBruWWyQ02N3BO/G7ot/17039RioZbEk8hMkvWPFYDtFnaOqRCPymNrMwbgSuo9nxNKD8+pobDnBI3M9Euc24C774NucT6eBCcxCFc81MtnHo1cE+JKIjZ86y31K33AKXa/v+CafnveYBmwuJym4279dInWyHR7ccrBdKjlutioF+u4tY5LnL4IQUaT5YlyOTwVfJK2XtVrHqkab+Q9bsTm1tmWmwL/8GH7c2FH2vf4eILhVtx1syNiDKccfK1FOCCEOKj2r6wmckOX3zjn0gi+U1qltK+U/NyGAMMGJnwoctdSsUPLrjN2TdHUu3BVcEwXVlodH3FeyCAV+LdPhYwFQJGdmpWpHkWwgfmwe5t7dgPIum5tc4JMetyXGTqGeuI+yWrkDzQatwdtKULy0Zbd5AMMOZWLDDKGheW4aT6GLHBc/7PguUDhDuyGKqn87Owvsz/CROINtu96i/JURZzJcGyOG9fbovuq9NjFMSg3vILTATRpncYstOJT5P9TEpvg8wLm+5IHgyh1achlQjtdGEF2eW0Locj+EPwstWazBjddUE4C22BnXQp5H4qkkrh0YfudTKZn2ZWVfkdI5KSwbpe90Lp3iE2vEimN0DJ2Dv394OyCi2thmqg1UnGVmxicwMyIXDmoH4o8TQxXq4UQ1fCjgnzxA81IhuZf6R+JV5zo1WXc0kJ6p/CpGysWwAoQnp4mZuAw8Qu4nK0tGkG2/Lw1fXyf4tgXpesC14vwFkcYTRqGozpbM8Id74II/wlMkPbfbpmY67egyrws5nG57LHp3zsboM+xxcBfjHV8cMxGnnmJDTqpMmRMXUw9e9N4Qb+x29l0oxSKCP2oN9kdu0gqBhF75tqr5POVfRFd7g+O+p3ChXkwvEoCLyEWh4tezELH1oJqdsx0hAuqI3PQ87+I2TxVAt94MMlsaYOec+06VpurhAswK7oizKPQ7rjZAIpVgTDV64vNTdsfIGkAUFzIt1tS0gfuoH+0vWdXpvD3YBqa37RI6YIMKk1vZ2XSAWk0hSCmssKJRF5pm9+L3fFiC97JylFdxteqlFnHS5xM/qtP2shUzUaA8vsT0mb+2Itv0YN3wVmhbkL2cK4T2q+ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ed37ae2e-d6b3-4f4a-5d96-08d931a9b9aa X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:28.5442 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Xdj3mPWA7aEviMN6CSySp6iH+uK9aKbBlEzSC3Va2EdAx+13twm+KkR9TC2GUnUhbt/j7yzytQiFB3V5dCZxmg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/reg/reg_mac_hw.h | 490 ++++++++++++++++++ 1 file changed, 490 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h new file mode 100644 index 000000000000..50ee26b2c5fa --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_MAC_HW_H +#define CL_REG_MAC_HW_H + +#include +#include "reg/reg_access.h" +#include "hw.h" + +/* + * @brief STATE_CNTRL register definition + * This register controls the core's state transitions. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   07:04 NEXT_STATE                0x0
+ *   03:00 CURRENT_STATE             0x0
+ *
+ */ +#define MAC_HW_STATE_CNTRL_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000038) +#define MAC_HW_STATE_CNTRL_OFFSET 0x00000038 +#define MAC_HW_STATE_CNTRL_INDEX 0x0000000E +#define MAC_HW_STATE_CNTRL_RESET 0x00000000 + +/* Field definitions */ +#define MAC_HW_STATE_CNTRL_NEXT_STATE_MASK ((u32)0x000000F0) +#define MAC_HW_STATE_CNTRL_NEXT_STATE_LSB 4 +#define MAC_HW_STATE_CNTRL_NEXT_STATE_WIDTH ((u32)0x00000004) +#define MAC_HW_STATE_CNTRL_CURRENT_STATE_MASK ((u32)0x0000000F) +#define MAC_HW_STATE_CNTRL_CURRENT_STATE_LSB 0 +#define MAC_HW_STATE_CNTRL_CURRENT_STATE_WIDTH ((u32)0x00000004) + +static inline void mac_hw_state_cntrl_next_state_setf(struct cl_hw *cl_hw, u8 nextstate) +{ + ASSERT_ERR((((u32)nextstate << 4) & ~((u32)0x000000F0)) == 0); + cl_reg_write(cl_hw, MAC_HW_STATE_CNTRL_ADDR, + (cl_reg_read(cl_hw, MAC_HW_STATE_CNTRL_ADDR) & ~((u32)0x000000F0)) | ((u32)nextstate << 4)); +} + +/* + * @brief MAC_CNTRL_1 register definition + * Contains various settings for controlling the operation of the core. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31    EOF_PAD_FOR_HE            1
+ *   30    EOF_PAD_FOR_VHT           0
+ *   29:28 IMPLICIT_BF_INT_CONF      0x0
+ *   27    DISABLE_BFR_RESP          0
+ *   26    RX_RIFS_EN                0
+ *   25    TSF_MGT_DISABLE           0
+ *   24    TSF_UPDATED_BY_SW         0
+ *   22    MAC_DETECT_UNDERRUN_EN    0
+ *   21    DISABLE_MU_CTS_RESP       0
+ *   20    BQRP_RESP_BY_FW           0
+ *   19    BSRP_RESP_BY_FW           0
+ *   18    ENABLE_NORMAL_ACK_RESP_IN_HE_MU_W_TRIG 0
+ *   17    DISABLE_NORMAL_ACK_RESP_IN_HE_MU_WO_TRIG 0
+ *   16:14 ABGN_MODE                 0x3
+ *   13    KEY_STO_RAM_RESET         0
+ *   12    MIB_TABLE_RESET           0
+ *   11    RATE_CONTROLLER_MPIF      1
+ *   10    DISABLE_BA_RESP           0
+ *   09    DISABLE_CTS_RESP          0
+ *   08    DISABLE_ACK_RESP          0
+ *   07    ACTIVE_CLK_GATING         1
+ *   06    ENABLE_LP_CLK_SWITCH      0
+ *   05    FORCE_MSTA_BA             0
+ *   04    DISABLE_FAST_COMPARE      0
+ *   03    CFP_AWARE                 0
+ *   02    PWR_MGT                   0
+ *   01    AP                        0
+ *   00    BSS_TYPE                  1
+ *
+ */ +#define MAC_HW_MAC_CNTRL_1_ADDR (REG_MAC_HW_BASE_ADDR + 0x0000004C) +#define MAC_HW_MAC_CNTRL_1_OFFSET 0x0000004C +#define MAC_HW_MAC_CNTRL_1_INDEX 0x00000013 +#define MAC_HW_MAC_CNTRL_1_RESET 0x8000C881 + +/* Field definitions */ +#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_HE_BIT ((u32)0x80000000) +#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_HE_POS 31 +#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_VHT_BIT ((u32)0x40000000) +#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_VHT_POS 30 +#define MAC_HW_MAC_CNTRL_1_IMPLICIT_BF_INT_CONF_MASK ((u32)0x30000000) +#define MAC_HW_MAC_CNTRL_1_IMPLICIT_BF_INT_CONF_LSB 28 +#define MAC_HW_MAC_CNTRL_1_IMPLICIT_BF_INT_CONF_WIDTH ((u32)0x00000002) +#define MAC_HW_MAC_CNTRL_1_DISABLE_BFR_RESP_BIT ((u32)0x08000000) +#define MAC_HW_MAC_CNTRL_1_DISABLE_BFR_RESP_POS 27 +#define MAC_HW_MAC_CNTRL_1_RX_RIFS_EN_BIT ((u32)0x04000000) +#define MAC_HW_MAC_CNTRL_1_RX_RIFS_EN_POS 26 +#define MAC_HW_MAC_CNTRL_1_TSF_MGT_DISABLE_BIT ((u32)0x02000000) +#define MAC_HW_MAC_CNTRL_1_TSF_MGT_DISABLE_POS 25 +#define MAC_HW_MAC_CNTRL_1_TSF_UPDATED_BY_SW_BIT ((u32)0x01000000) +#define MAC_HW_MAC_CNTRL_1_TSF_UPDATED_BY_SW_POS 24 +#define MAC_HW_MAC_CNTRL_1_MAC_DETECT_UNDERRUN_EN_BIT ((u32)0x00400000) +#define MAC_HW_MAC_CNTRL_1_MAC_DETECT_UNDERRUN_EN_POS 22 +#define MAC_HW_MAC_CNTRL_1_DISABLE_MU_CTS_RESP_BIT ((u32)0x00200000) +#define MAC_HW_MAC_CNTRL_1_DISABLE_MU_CTS_RESP_POS 21 +#define MAC_HW_MAC_CNTRL_1_BQRP_RESP_BY_FW_BIT ((u32)0x00100000) +#define MAC_HW_MAC_CNTRL_1_BQRP_RESP_BY_FW_POS 20 +#define MAC_HW_MAC_CNTRL_1_BSRP_RESP_BY_FW_BIT ((u32)0x00080000) +#define MAC_HW_MAC_CNTRL_1_BSRP_RESP_BY_FW_POS 19 +#define MAC_HW_MAC_CNTRL_1_ENABLE_NORMAL_ACK_RESP_IN_HE_MU_W_TRIG_BIT ((u32)0x00040000) +#define MAC_HW_MAC_CNTRL_1_ENABLE_NORMAL_ACK_RESP_IN_HE_MU_W_TRIG_POS 18 +#define MAC_HW_MAC_CNTRL_1_DISABLE_NORMAL_ACK_RESP_IN_HE_MU_WO_TRIG_BIT ((u32)0x00020000) +#define MAC_HW_MAC_CNTRL_1_DISABLE_NORMAL_ACK_RESP_IN_HE_MU_WO_TRIG_POS 17 +#define MAC_HW_MAC_CNTRL_1_ABGN_MODE_MASK ((u32)0x0001C000) +#define MAC_HW_MAC_CNTRL_1_ABGN_MODE_LSB 14 +#define MAC_HW_MAC_CNTRL_1_ABGN_MODE_WIDTH ((u32)0x00000003) +#define MAC_HW_MAC_CNTRL_1_KEY_STO_RAM_RESET_BIT ((u32)0x00002000) +#define MAC_HW_MAC_CNTRL_1_KEY_STO_RAM_RESET_POS 13 +#define MAC_HW_MAC_CNTRL_1_MIB_TABLE_RESET_BIT ((u32)0x00001000) +#define MAC_HW_MAC_CNTRL_1_MIB_TABLE_RESET_POS 12 +#define MAC_HW_MAC_CNTRL_1_RATE_CONTROLLER_MPIF_BIT ((u32)0x00000800) +#define MAC_HW_MAC_CNTRL_1_RATE_CONTROLLER_MPIF_POS 11 +#define MAC_HW_MAC_CNTRL_1_DISABLE_BA_RESP_BIT ((u32)0x00000400) +#define MAC_HW_MAC_CNTRL_1_DISABLE_BA_RESP_POS 10 +#define MAC_HW_MAC_CNTRL_1_DISABLE_CTS_RESP_BIT ((u32)0x00000200) +#define MAC_HW_MAC_CNTRL_1_DISABLE_CTS_RESP_POS 9 +#define MAC_HW_MAC_CNTRL_1_DISABLE_ACK_RESP_BIT ((u32)0x00000100) +#define MAC_HW_MAC_CNTRL_1_DISABLE_ACK_RESP_POS 8 +#define MAC_HW_MAC_CNTRL_1_ACTIVE_CLK_GATING_BIT ((u32)0x00000080) +#define MAC_HW_MAC_CNTRL_1_ACTIVE_CLK_GATING_POS 7 +#define MAC_HW_MAC_CNTRL_1_ENABLE_LP_CLK_SWITCH_BIT ((u32)0x00000040) +#define MAC_HW_MAC_CNTRL_1_ENABLE_LP_CLK_SWITCH_POS 6 +#define MAC_HW_MAC_CNTRL_1_FORCE_MSTA_BA_BIT ((u32)0x00000020) +#define MAC_HW_MAC_CNTRL_1_FORCE_MSTA_BA_POS 5 +#define MAC_HW_MAC_CNTRL_1_DISABLE_FAST_COMPARE_BIT ((u32)0x00000010) +#define MAC_HW_MAC_CNTRL_1_DISABLE_FAST_COMPARE_POS 4 +#define MAC_HW_MAC_CNTRL_1_CFP_AWARE_BIT ((u32)0x00000008) +#define MAC_HW_MAC_CNTRL_1_CFP_AWARE_POS 3 +#define MAC_HW_MAC_CNTRL_1_PWR_MGT_BIT ((u32)0x00000004) +#define MAC_HW_MAC_CNTRL_1_PWR_MGT_POS 2 +#define MAC_HW_MAC_CNTRL_1_AP_BIT ((u32)0x00000002) +#define MAC_HW_MAC_CNTRL_1_AP_POS 1 +#define MAC_HW_MAC_CNTRL_1_BSS_TYPE_BIT ((u32)0x00000001) +#define MAC_HW_MAC_CNTRL_1_BSS_TYPE_POS 0 + +static inline void mac_hw_mac_cntrl_1_active_clk_gating_setf(struct cl_hw *cl_hw, u8 activeclkgating) +{ + ASSERT_ERR((((u32)activeclkgating << 7) & ~((u32)0x00000080)) == 0); + cl_reg_write(cl_hw, MAC_HW_MAC_CNTRL_1_ADDR, + (cl_reg_read(cl_hw, MAC_HW_MAC_CNTRL_1_ADDR) & ~((u32)0x00000080)) | ((u32)activeclkgating << 7)); +} + +/* + * @brief EDCA_CCA_BUSY register definition + * Indicates the CCA busy time. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 CCA_BUSY_DUR              0x0
+ *
+ */ +#define MAC_HW_EDCA_CCA_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000220) +#define MAC_HW_EDCA_CCA_BUSY_OFFSET 0x00000220 +#define MAC_HW_EDCA_CCA_BUSY_INDEX 0x00000088 +#define MAC_HW_EDCA_CCA_BUSY_RESET 0x00000000 + +static inline u32 mac_hw_edca_cca_busy_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_EDCA_CCA_BUSY_ADDR); +} + +/* + * @brief RX_MINE_BUSY register definition + * RX Busy time by my frames counter register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 rx_mine_time              0x0
+ *
+ */ +#define MAC_HW_RX_MINE_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000234) +#define MAC_HW_RX_MINE_BUSY_OFFSET 0x00000234 +#define MAC_HW_RX_MINE_BUSY_INDEX 0x0000008D +#define MAC_HW_RX_MINE_BUSY_RESET 0x00000000 + +static inline u32 mac_hw_rx_mine_busy_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_RX_MINE_BUSY_ADDR); +} + +/* + * @brief TX_MINE_BUSY register definition + * TX BUSY time by my TX frames register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 TX_MINE_TIME              0x0
+ *
+ */ +#define MAC_HW_TX_MINE_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000238) +#define MAC_HW_TX_MINE_BUSY_OFFSET 0x00000238 +#define MAC_HW_TX_MINE_BUSY_INDEX 0x0000008E +#define MAC_HW_TX_MINE_BUSY_RESET 0x00000000 + +static inline u32 mac_hw_tx_mine_busy_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_TX_MINE_BUSY_ADDR); +} + +/* + * @brief EDCA_NAV_BUSY register definition + * Indicates the NAV busy time register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 NAV_BUSY_DUR              0x0
+ *
+ */ +#define MAC_HW_EDCA_NAV_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000248) +#define MAC_HW_EDCA_NAV_BUSY_OFFSET 0x00000248 +#define MAC_HW_EDCA_NAV_BUSY_INDEX 0x00000092 +#define MAC_HW_EDCA_NAV_BUSY_RESET 0x00000000 + +static inline u32 mac_hw_edca_nav_busy_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_EDCA_NAV_BUSY_ADDR); +} + +/* + * @brief ADD_CCA_BUSY_SEC_20 register definition + * Indicates the CCA on Secondary 20MHz busy time. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 CCA_BUSY_DUR_SEC_20       0x0
+ *
+ */ +#define MAC_HW_ADD_CCA_BUSY_SEC_20_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000290) +#define MAC_HW_ADD_CCA_BUSY_SEC_20_OFFSET 0x00000290 +#define MAC_HW_ADD_CCA_BUSY_SEC_20_INDEX 0x000000A4 +#define MAC_HW_ADD_CCA_BUSY_SEC_20_RESET 0x00000000 + +static inline u32 mac_hw_add_cca_busy_sec_20_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_ADD_CCA_BUSY_SEC_20_ADDR); +} + +/* + * @brief ADD_CCA_BUSY_SEC_40 register definition + * Indicates the CCA on Secondary 40MHz busy time. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 CCA_BUSY_DUR_SEC_40       0x0
+ *
+ */ +#define MAC_HW_ADD_CCA_BUSY_SEC_40_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000294) +#define MAC_HW_ADD_CCA_BUSY_SEC_40_OFFSET 0x00000294 +#define MAC_HW_ADD_CCA_BUSY_SEC_40_INDEX 0x000000A5 +#define MAC_HW_ADD_CCA_BUSY_SEC_40_RESET 0x00000000 + +static inline u32 mac_hw_add_cca_busy_sec_40_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_ADD_CCA_BUSY_SEC_40_ADDR); +} + +/* + * @brief ADD_CCA_BUSY_SEC_80 register definition + * Indicates the CCA on Secondary 80MHz busy time. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 CCA_BUSY_DUR_SEC_80       0x0
+ *
+ */ +#define MAC_HW_ADD_CCA_BUSY_SEC_80_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000298) +#define MAC_HW_ADD_CCA_BUSY_SEC_80_OFFSET 0x00000298 +#define MAC_HW_ADD_CCA_BUSY_SEC_80_INDEX 0x000000A6 +#define MAC_HW_ADD_CCA_BUSY_SEC_80_RESET 0x00000000 + +static inline u32 mac_hw_add_cca_busy_sec_80_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_ADD_CCA_BUSY_SEC_80_ADDR); +} + +/* + * @brief INTRA_BSS_NAV_BUSY register definition + * Count intra BSS NAV busy period register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 INTRA_BSS_NAV_BUSY_DUR    0x0
+ *
+ */ +#define MAC_HW_INTRA_BSS_NAV_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000408) +#define MAC_HW_INTRA_BSS_NAV_BUSY_OFFSET 0x00000408 +#define MAC_HW_INTRA_BSS_NAV_BUSY_INDEX 0x00000102 +#define MAC_HW_INTRA_BSS_NAV_BUSY_RESET 0x00000000 + +static inline u32 mac_hw_intra_bss_nav_busy_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_INTRA_BSS_NAV_BUSY_ADDR); +} + +/* + * @brief INTER_BSS_NAV_BUSY register definition + * Count inter BSS NAV busy period register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 INTER_BSS_NAV_BUSY_DUR    0x0
+ *
+ */ +#define MAC_HW_INTER_BSS_NAV_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x0000040C) +#define MAC_HW_INTER_BSS_NAV_BUSY_OFFSET 0x0000040C +#define MAC_HW_INTER_BSS_NAV_BUSY_INDEX 0x00000103 +#define MAC_HW_INTER_BSS_NAV_BUSY_RESET 0x00000000 + +static inline u32 mac_hw_inter_bss_nav_busy_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_INTER_BSS_NAV_BUSY_ADDR); +} + +/* + * @brief DEBUG_PORT_SEL_A register definition + * Used to multiplex different sets of signals on the debug pins. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   15:08 DEBUG_PORT_SEL_1          0x0
+ *   07:00 DEBUG_PORT_SEL_0          0x0
+ *
+ */ +#define MAC_HW_DEBUG_PORT_SEL_A_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000510) +#define MAC_HW_DEBUG_PORT_SEL_A_OFFSET 0x00000510 +#define MAC_HW_DEBUG_PORT_SEL_A_INDEX 0x00000144 +#define MAC_HW_DEBUG_PORT_SEL_A_RESET 0x00000000 + +static inline u32 mac_hw_debug_port_sel_a_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_SEL_A_ADDR); +} + +static inline void mac_hw_debug_port_sel_a_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_SEL_A_ADDR, value); +} + +/* + * @brief DEBUG_PORT_SEL_B register definition + * Used to multiplex different sets of signals on the register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   15:08 DEBUG_PORT_SEL_3          0x0
+ *   07:00 DEBUG_PORT_SEL_2          0x0
+ *
+ */ +#define MAC_HW_DEBUG_PORT_SEL_B_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000530) +#define MAC_HW_DEBUG_PORT_SEL_B_OFFSET 0x00000530 +#define MAC_HW_DEBUG_PORT_SEL_B_INDEX 0x0000014C +#define MAC_HW_DEBUG_PORT_SEL_B_RESET 0x00000000 + +static inline u32 mac_hw_debug_port_sel_b_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_SEL_B_ADDR); +} + +static inline void mac_hw_debug_port_sel_b_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_SEL_B_ADDR, value); +} + +/* + * @brief DEBUG_PORT_SEL_C register definition + * Used to multiplex different sets of signals on the register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   15:08 DEBUG_PORT_SEL_5          0x0
+ *   07:00 DEBUG_PORT_SEL_4          0x0
+ *
+ */ +#define MAC_HW_DEBUG_PORT_SEL_C_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000534) +#define MAC_HW_DEBUG_PORT_SEL_C_OFFSET 0x00000534 +#define MAC_HW_DEBUG_PORT_SEL_C_INDEX 0x0000014D +#define MAC_HW_DEBUG_PORT_SEL_C_RESET 0x00000000 + +static inline u32 mac_hw_debug_port_sel_c_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_SEL_C_ADDR); +} + +static inline void mac_hw_debug_port_sel_c_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_SEL_C_ADDR, value); +} + +/* + * @brief DEBUG_PORT_EN register definition + * Used to determine which debug ports are enabled register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   05    EN5                       0
+ *   04    EN4                       0
+ *   03    EN3                       0
+ *   02    EN2                       0
+ *   01    EN1                       0
+ *   00    EN0                       0
+ *
+ */ +#define MAC_HW_DEBUG_PORT_EN_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000538) +#define MAC_HW_DEBUG_PORT_EN_OFFSET 0x00000538 +#define MAC_HW_DEBUG_PORT_EN_INDEX 0x0000014E +#define MAC_HW_DEBUG_PORT_EN_RESET 0x00000000 + +static inline u32 mac_hw_debug_port_en_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_EN_ADDR); +} + +static inline void mac_hw_debug_port_en_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_EN_ADDR, value); +} + +/* + * @brief DOZE_CNTRL_2 register definition + * Contains settings for controlling DOZE state. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31    WAKE_UP_FROM_DOZE         0
+ *   00    WAKE_UP_SW                1
+ *
+ */ +#define MAC_HW_DOZE_CNTRL_2_ADDR (REG_MAC_HW_BASE_ADDR + 0x00008048) +#define MAC_HW_DOZE_CNTRL_2_OFFSET 0x00008048 +#define MAC_HW_DOZE_CNTRL_2_INDEX 0x00002012 +#define MAC_HW_DOZE_CNTRL_2_RESET 0x00000001 + +/* Field definitions */ +#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_FROM_DOZE_BIT ((u32)0x80000000) +#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_FROM_DOZE_POS 31 +#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_SW_BIT ((u32)0x00000001) +#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_SW_POS 0 + +static inline void mac_hw_doze_cntrl_2_wake_up_sw_setf(struct cl_hw *cl_hw, u8 wakeupsw) +{ + ASSERT_ERR((((u32)wakeupsw << 0) & ~((u32)0x00000001)) == 0); + cl_reg_write(cl_hw, MAC_HW_DOZE_CNTRL_2_ADDR, + (cl_reg_read(cl_hw, MAC_HW_DOZE_CNTRL_2_ADDR) & ~((u32)0x00000001)) | ((u32)wakeupsw << 0)); +} + +/* + * @brief TSF_LO register definition + * Contains the TSF bits. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 TSF_TIMER_LOW             0x0
+ *
+ */ +#define MAC_HW_TSF_LO_ADDR (REG_MAC_HW_BASE_ADDR + 0x000080A4) +#define MAC_HW_TSF_LO_OFFSET 0x000080A4 +#define MAC_HW_TSF_LO_INDEX 0x00002029 +#define MAC_HW_TSF_LO_RESET 0x00000000 + +static inline u32 mac_hw_tsf_lo_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_TSF_LO_ADDR); +} + +/* + * @brief TSF_HI register definition + * Contains the TSF bits. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 TSF_TIMER_HIGH            0x0
+ *
+ */ +#define MAC_HW_TSF_HI_ADDR (REG_MAC_HW_BASE_ADDR + 0x000080A8) +#define MAC_HW_TSF_HI_OFFSET 0x000080A8 +#define MAC_HW_TSF_HI_INDEX 0x0000202A +#define MAC_HW_TSF_HI_RESET 0x00000000 + +static inline u32 mac_hw_tsf_hi_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, MAC_HW_TSF_HI_ADDR); +} + +#endif /*CL_REG_MAC_HW_H */ From patchwork Thu Jun 17 16:00:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43F15C2B9F4 for ; Thu, 17 Jun 2021 16:08:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2AF0C61407 for ; Thu, 17 Jun 2021 16:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232883AbhFQQKr (ORCPT ); Thu, 17 Jun 2021 12:10:47 -0400 Received: from mail-eopbgr20072.outbound.protection.outlook.com ([40.107.2.72]:4749 "EHLO EUR02-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232598AbhFQQJu (ORCPT ); Thu, 17 Jun 2021 12:09:50 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z3ydCt97uywPWAG8yNkBDHw8V0XTxODXqgaIqw2tp9y876HKMYr23OlcYyioqxrZZxkBQxDbdmChixfqQGWiIycZ9/2UbSGLLXEnk7WFPB08sImqYJVB2WiV6KyQPZLY4cCS+aqjp149cbqVjTXuAgz+Gbd9LiMd9dtlXjUQK1eVm85+zdKmcX/ZdqTO9gQtBWsrJZuqnChOTbDag+Zg1T1lQnrIbbCPbAphymZU1NQY5fGNGD5FyfpaSgBp07e7lbPCij+imSioRXHM25sjZwbw87Q7jGOmaETDpdXxHz9run5I1dIAGkUs0PRqlccc1Mw0YSJtkgA8dKL8Cva0Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VnbiDJUrS0osfSRKsPpfFxKgFQHWSOksUpZOemyPrxc=; b=KlZfyI7E6YyGhh8DRh/BPhMeOouJXpg/Ut1pfF9HX9PKQvNycM8H10SS/k8JildkdF0W54GMUQz5TntTJ+NksmMStItMXYwTokITZ8StO6eI7G7oFkIBzh5NKYAfprkEm2csa/TCL/UNsMvIMwY8YQZDJFXD3+jzwKNr4JqeiANgj0gAzun3+OzH2dbq6EOTvN6O24kV/ZdG8T6it5pi4tsQLp4SWUvQNm7jYbCz0jteaSsAlyOQzu3IQ4NERj/T9OmhIogF2vTmz4YJU2XgX+nNrlTGcgwObiYPKSVix7JeOBS2yN2gXPzS9s+JQRIGRHA5+kT99rZwX4kcKjxmjg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VnbiDJUrS0osfSRKsPpfFxKgFQHWSOksUpZOemyPrxc=; b=uxtrQbcYQC4jfI/32fZ7l6RUEtCM1zj4ffah/fJdlmMSAURYZUKOV38TcTou/me28On8xhhkm/ylZMkkrCwjLlWOjKIIaNLLm3Mk1ZomMKKzUlnPcv426mDWgedw1bCoji1zEhWVRKhf85lr5MlcTC0Ar5V4mj/BPDbCzRdJbVg= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:27 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:27 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_mac_hw_mu.h | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h new file mode 100644 index 000000000000..45368cfc36d6 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_MAC_HW_MU_H +#define CL_REG_MAC_HW_MU_H + +#include +#include "reg/reg_access.h" +#include "hw.h" + +#define MU_ADDR_OFFSET(i) ((i) << 16) + +/* + * @brief MAC_CNTRL_2 register definition + * Contains various settings for controlling the operation of the core. register description + * 
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   00    SOFT_RESET                0
+ *
+ */ +#define MAC_HW_MU_MAC_CNTRL_2_ADDR (REG_MAC_HW_BASE_ADDR + 0x00008050) +#define MAC_HW_MU_MAC_CNTRL_2_OFFSET 0x00008050 +#define MAC_HW_MU_MAC_CNTRL_2_INDEX 0x00002014 +#define MAC_HW_MU_MAC_CNTRL_2_RESET 0x00000000 + +static inline void mac_hw_mu_mac_cntrl_2_set(struct cl_hw *cl_hw, u32 value, u8 mu_idx) +{ + ASSERT_ERR(mu_idx < cl_hw->max_mu_cnt); + cl_reg_write(cl_hw, (MAC_HW_MU_MAC_CNTRL_2_ADDR + MU_ADDR_OFFSET(mu_idx)), value); +} + +#endif /* CL_REG_MAC_HW_MU_H */ From patchwork Thu Jun 17 16:00:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA12C49EA3 for ; Thu, 17 Jun 2021 16:09:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F114B61407 for ; Thu, 17 Jun 2021 16:09:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233903AbhFQQLF (ORCPT ); Thu, 17 Jun 2021 12:11:05 -0400 Received: from mail-eopbgr70043.outbound.protection.outlook.com ([40.107.7.43]:64066 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233614AbhFQQJ5 (ORCPT ); Thu, 17 Jun 2021 12:09:57 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ou5+3vB6fNV71v6rCkyqvJWYgvcuiHQt66ubvaMgx70+pGxqSbPnRxcYwQJQd5xM40/c/X3hBE/a+p+YLCNgX/ajnLkDyP19u7vtiHYOD3JEM6DTb8gJEG1uZw3pWZG3jiVLXFwsy0aju8//MSG02TosYdqHqM/VPpekNiXcOb2fPgzYXn5h7ulsj1kRiicuh2L9b+7Zotly9SIHVASu3hx2VSjKjUuEmQzis4RiOdBqxccdR5humO//Ruqrc8ox2e4mxqfROEs+GM1Wo1lP9BugknWLoj4e/tFG0CnVobbiHDBaeNLHrr4GLkqsslVzop8ZD9+srSv4riiqo48Ofw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=10BMgkutdWr07lSYNJbOPiY7EwWERiqzztOipad4sP8=; b=Rs4g0y5id9wK1/EPNLG8OsltReoJUayBdXaSvLVFeczYEJkJxWsb1pcpWF4VQEq5Rg1U4n9rAs5cBsBUv9YfhL//kLAqHqL2fOhaAJkdKx4szVaYOOLvkgkAdKOe2L5FIyQaBRThjWLP24K+c43sn6lS5/bgsYJO+7O+lZoB3TWMZLVb1GD5NgL5U61PTZAG9UdJ/XqnsYqbWl/m88deLhTp2I6ehHbMdK3SwcKg+6d2XICFuDwfDxc+s9WLbgGxJPxnnVu4PYegpJOgi8WQg736Qbyfxa+W7yEQrU16OZKNRf7g6cdM20ir56zwxJOUChb/wls1b/2jHshhT58jMA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=10BMgkutdWr07lSYNJbOPiY7EwWERiqzztOipad4sP8=; b=SgbNcLOHOtkRFZ8Btp/U29SqCnGxYGLHySyeNwKLwxTg7TP6e/7z+dSGbtvUMT4t1UZoonde+imjg1cOdakZjgFn0d67xYPW0rhDO5vRL5QNnQRzJtXvZ6kNAcWkyYqY5XglAEvoMJY1cebxQxdc8od9AugrwyO0brOsUA3/XLU= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:28 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:28 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 162/256] cl8k: add reg/reg_otp_pvt.h Date: Thu, 17 Jun 2021 16:00:49 +0000 Message-Id: <20210617160223.160998-163-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:30 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bbd764e0-def6-441f-4b91-08d931a9bb83 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mg1fei2DAIyXr26sJSTTphVuL460HnUnULVsgKPuWODrHzDQDZZ71+uTpcKLKUVi5Y7JDUnGUh5KWgmq1YKb/di1aLZYkeQXt7ZedIdhyrHEuZxBAztRZ31/BCzPrGAtTc8E5IGJLBPBYO1ym3k5WgkKvt2YUvFzDQcB2UTctyr2g+QdJSXrIuTjGPqIKwzBRXgcPnaWlgxd7fav/+CvSGEhLtfl5XZd92FWILa/53Rywc1UVztpwt6xpAHK7LSDNHuym272cf4Sr0BptSEHvQVzG3EqLJLzPLpeBRyCoLShgtuV9Bo3OqWjZ45UB77AKV5RUFwLa5usEnklgKrsHh5oOyMH5XOlUYvmi9hzGp763ASYZPfKbd1VmOYEnd5xi8su98NpgBE7DFoo058mMXw0UsEPm5KPDUgIzZzHegqZAf/GovU4bAH1t2T2gdQ/3v9zgisO/PstlQeK27H3NczME6i+QLuvJ/T/E4ocKuS+kXY3sgS75za+44viNqJ1WdftY8x1fGFGdZXLYGCldx02U7HthM1oooD3m2BW/P0lMuo0Avf6t3TGxJWpnGhRhXzs/qEekyyrEQUIE24TSuIQ4sZv6OFjAyUl2lkuqjMX0HWp/OGYyvweeICnla3adtROo+vHmmQcQZScBo52ulvWzyWOBRMENZmgH+Mtv5XDsG3Ivgf4Ws8APVYhgmqUlZn7kX28fzLclA0nNVOLNA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ss4TCfvhd8AyDFP2CeNlRr4rwIDK1v+wTOBsPkaDCVDIx3qiac4TEANfI47YJl00XrSMKpkNc5Q5spBueQKEaBAhR0BHfGEQMTg0AV7jS+dV5EYhj5TcS7rqJkK1L/DqPQnbJT14zGftXTHnVnhwDlqz4EhWbOFbtU1H/S400RBkjnEQyuoSLfVQfIO+jU4WP8TZwEoL/BBAR/GD6qbYqk9jhzmfSdRpaT8AsZ2loU4veyuJXqBeXYFizgqaMuK71/555vUDRyS/5tNxHDgSgUEBHtFFxIGz1s0WtmxCTT4+1vHJL9x1+OoQkO4MYWfhgTxxqJDatz1ZeZCWGwt/1Wy8k4rIye8WoMA6CD3lm/DFJnRZ/wfyCod7IwKbBa/V0zCvJTOH7fZQUUWsCGwyhHIVBpfA3l2W5o9jxy+bhdoI+c8xBa5wpCqnU9M2cD46AYdVeAjEOnA4PbBbnlpVg7CyLm1mfiE/r1BfycP3aOnR9Q4x0nrGhfasIH9Q2MFJ4JXXgOjRcfZqY1yG8OCZ6Uwbz0KWSHTi7V9IqEza3H/FHM+I86Vi60cm8AVGZrx1czcaWuEZQwGgXfjyC3XfgqN9qgEEfQPMyX64tLXu2MGuAFoWk05ik3mWJsN7GAryDw3O51TYL2feqEvy0QNvjn58ElznLm7z7F6vPXe7AAO1ayoKYkzEyFWfCwoMqfs8fYvIHCsPUUQSo94NM4ZDpvcYXq9AIyOzyBPCuWiMthER1DFiKZ6LII9J6ggKbyRn7L9647w7h4rVQds5X/YSCw8+SrBgxuzSOzGdUmae7OD1LGF5f6vhSe3J9tv781z1MmWJx5ztkhUKm0x92CMV5DJpZZSzlW8t8VLzY8S07uvkhGygDtL//HW9A7pK3P7vaYysETyUb5+weBj4sUmzSlo2NgbvpvShMP2y/eW5nJ3OFQ+uh+1BPaciIklzQDD+89C4szwZdsFwcpOjz3NSWD6J4f7v6Jp3tVGZi1XiVHUz0Poj1vQm94mzqU+FnlRV3kGsn0Zt7kW339Lr+qT9bRqFQiEBRfbb/M8+3N54KLfdraBcQZxwQwIelPF8d1bsTFK7P72k18c7wciF61dYO1gmExpgFKCB340KNJKqvE0rHJYeaEumGdpl/w1hF0EkPgMRz2zIYotyaIFyyiIS5drME7lSlCuJYgYKtapRjOyidHzvwy54/OSWEPft5UflCZJfILK2ba3tolpcJOeTxHBYGEu1kPg2kQTPKVXgJS4G7nzY2afcXQE8DIncxurpX2743T6JE6sw8HKDHYkjY7Ntkebr6XnAi5nZ8vTG4RGCwcYZm60l1Xi90m9Gc0PP X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: bbd764e0-def6-441f-4b91-08d931a9bb83 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:31.6247 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: C84xIRO8DniN8PIzCqPAtnQbjo49raZLbmWZbky1geUXhCqQu0TiHvFmeWdbW1L+PiE4URrIzb7hiPPecbeHPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/reg/reg_otp_pvt.h | 219 ++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h b/drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h new file mode 100644 index 000000000000..18866c1c3710 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_OTP_PVT +#define CL_REG_OTP_PVT + +#include +#include "reg/reg_access.h" +#include "chip.h" + +#define REG_OTP_PVT_BASE_ADDR 0x007C9000 + +/* + * @brief OTP_CMD register definition + * OTP command register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    28    OTP_PR_ACC                0
+ *    24    OTP_ABORT_CLR             0
+ *    16    OTP_READY                 1
+ *    12    OTP_WRITE_FAILED          0
+ *    01:00 OTP_CMD                   0x0
+ *
+ */ +#define OTP_PVT_OTP_CMD_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000000) +#define OTP_PVT_OTP_CMD_OFFSET 0x00000000 +#define OTP_PVT_OTP_CMD_INDEX 0x00000000 +#define OTP_PVT_OTP_CMD_RESET 0x00010000 + +static inline u8 otp_pvt_otp_cmd_otp_pr_acc_getf(struct cl_chip *chip) +{ + u32 local_val = cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR); + + return ((local_val & ((u32)0x10000000)) >> 28); +} + +static inline u8 otp_pvt_otp_cmd_otp_ready_getf(struct cl_chip *chip) +{ + u32 local_val = cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR); + + return ((local_val & ((u32)0x00010000)) >> 16); +} + +static inline u8 otp_pvt_otp_cmd_otp_write_failed_getf(struct cl_chip *chip) +{ + u32 local_val = cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR); + + return ((local_val & ((u32)0x00001000)) >> 12); +} + +static inline void otp_pvt_otp_cmd_otp_cmd_setf(struct cl_chip *chip, u8 otpcmd) +{ + ASSERT_ERR_CHIP((((u32)otpcmd << 0) & ~((u32)0x00000003)) == 0); + cl_reg_write_chip(chip, OTP_PVT_OTP_CMD_ADDR, + (cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR) & ~((u32)0x00000003)) | ((u32)otpcmd << 0)); +} + +/* + * @brief OTP_READ_VAL register definition + * OTP read value register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 OTP_READ_VAL              0x0
+ *
+ */ +#define OTP_PVT_OTP_READ_VAL_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000004) +#define OTP_PVT_OTP_READ_VAL_OFFSET 0x00000004 +#define OTP_PVT_OTP_READ_VAL_INDEX 0x00000001 +#define OTP_PVT_OTP_READ_VAL_RESET 0x00000000 + +static inline u32 otp_pvt_otp_read_val_get(struct cl_chip *chip) +{ + return cl_reg_read_chip(chip, OTP_PVT_OTP_READ_VAL_ADDR); +} + +/* + * @brief OTP_ADDR register definition + * OTP address register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    12:00 OTP_ADDR                  0x0
+ *
+ */ +#define OTP_PVT_OTP_ADDR_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000008) +#define OTP_PVT_OTP_ADDR_OFFSET 0x00000008 +#define OTP_PVT_OTP_ADDR_INDEX 0x00000002 +#define OTP_PVT_OTP_ADDR_RESET 0x00000000 + +static inline void otp_pvt_otp_addr_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, OTP_PVT_OTP_ADDR_ADDR, value); +} + +/* + * @brief OTP_TIMINGS_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:25 otp_t_CPH                 0xa
+ *    24:18 t_PES                     0xa
+ *    17:16 t_UT                      0x0
+ *    15:08 t_RW                      0x15
+ *    07:00 t_CSRT                    0x29
+ *
+ */ +#define OTP_PVT_OTP_TIMINGS_1_ADDR (REG_OTP_PVT_BASE_ADDR + 0x0000000C) +#define OTP_PVT_OTP_TIMINGS_1_OFFSET 0x0000000C +#define OTP_PVT_OTP_TIMINGS_1_INDEX 0x00000003 +#define OTP_PVT_OTP_TIMINGS_1_RESET 0x14281529 + +static inline void otp_pvt_otp_timings_1_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, OTP_PVT_OTP_TIMINGS_1_ADDR, value); +} + +/* + * @brief OTP_TIMINGS_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    30:26 t_RD                      0x5
+ *    25:16 t_PW                      0x50
+ *    15:08 t_PEH                     0x20
+ *    07:00 t_CPS                     0x20
+ *
+ */ +#define OTP_PVT_OTP_TIMINGS_2_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000010) +#define OTP_PVT_OTP_TIMINGS_2_OFFSET 0x00000010 +#define OTP_PVT_OTP_TIMINGS_2_INDEX 0x00000004 +#define OTP_PVT_OTP_TIMINGS_2_RESET 0x14502020 + +static inline void otp_pvt_otp_timings_2_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, OTP_PVT_OTP_TIMINGS_2_ADDR, value); +} + +/* + * @brief OTP_WRITE_VAL register definition + * OTP write value register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    00    OTP_WRITE_VAL             0
+ *
+ */ +#define OTP_PVT_OTP_WRITE_VAL_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000014) +#define OTP_PVT_OTP_WRITE_VAL_OFFSET 0x00000014 +#define OTP_PVT_OTP_WRITE_VAL_INDEX 0x00000005 +#define OTP_PVT_OTP_WRITE_VAL_RESET 0x00000000 + +static inline void otp_pvt_otp_write_val_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, OTP_PVT_OTP_WRITE_VAL_ADDR, value); +} + +/* + * @brief OTP_KEY register definition + * OTP key register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 OTP_KEY                   0x0
+ *
+ */ +#define OTP_PVT_OTP_KEY_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000018) +#define OTP_PVT_OTP_KEY_OFFSET 0x00000018 +#define OTP_PVT_OTP_KEY_INDEX 0x00000006 +#define OTP_PVT_OTP_KEY_RESET 0x00000000 + +static inline void otp_pvt_otp_key_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, OTP_PVT_OTP_KEY_ADDR, value); +} + +/* + * @brief OTP_CLK_DIV register definition + * OTP clock divisor register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    08:00 OTP_CLK_DIV               0x1
+ *
+ */ +#define OTP_PVT_OTP_CLK_DIV_ADDR (REG_OTP_PVT_BASE_ADDR + 0x0000001C) +#define OTP_PVT_OTP_CLK_DIV_OFFSET 0x0000001C +#define OTP_PVT_OTP_CLK_DIV_INDEX 0x00000007 +#define OTP_PVT_OTP_CLK_DIV_RESET 0x00000001 + +static inline void otp_pvt_otp_clk_div_set(struct cl_chip *chip, u32 value) +{ + cl_reg_write_chip(chip, OTP_PVT_OTP_CLK_DIV_ADDR, value); +} + +/* + * @brief OTP_PROTECT register definition + * OTP address protection register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    01    OTP_PR_DIS                0
+ *    00    OTP_PR_SEL                0
+ *
+ */ +#define OTP_PVT_OTP_PROTECT_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000024) +#define OTP_PVT_OTP_PROTECT_OFFSET 0x00000024 +#define OTP_PVT_OTP_PROTECT_INDEX 0x00000009 +#define OTP_PVT_OTP_PROTECT_RESET 0x00000000 + +static inline void otp_pvt_otp_protect_otp_pr_dis_setf(struct cl_chip *chip, u8 otpprdis) +{ + ASSERT_ERR_CHIP((((u32)otpprdis << 1) & ~((u32)0x00000002)) == 0); + cl_reg_write_chip(chip, OTP_PVT_OTP_PROTECT_ADDR, + (cl_reg_read_chip(chip, OTP_PVT_OTP_PROTECT_ADDR) & ~((u32)0x00000002)) | ((u32)otpprdis << 1)); +} + +#endif /* CL_REG_OTP_PVT */ From patchwork Thu Jun 17 16:00:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA8B0C49EA3 for ; Thu, 17 Jun 2021 16:09:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 92A216141F for ; Thu, 17 Jun 2021 16:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233718AbhFQQLw (ORCPT ); Thu, 17 Jun 2021 12:11:52 -0400 Received: from mail-eopbgr70045.outbound.protection.outlook.com ([40.107.7.45]:47334 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232156AbhFQQKk (ORCPT ); Thu, 17 Jun 2021 12:10:40 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OMFqjQrQgqmOkjoR5zhzSfhGJUiKdmw0yF+pVsLfA5qCYrx4bLBzMHrTfjP04ubx9ppGGp07m929oI7bSf40qyrkZ+oYzwbybkY78vkbrPveBLSt2+veTMKdcsacMm2oCV7AO5F3kb7uDTSRYVJFTf3TT5MPLW3PofnkRSfHNvRunJj3bTiqEk7z59HeEMbLMWwLIkOjlrQcj9w9TFvuz04UNcqxkU3xV9s8nqDXB7e1JrBKZbsCX3ET4mUDJOxvS3nG58Lvohx8Ue2IPAjDWa+ODphv9ddGRW+pXlFoXrpraI0IYA2hdpHnzXu1WO4LaNwd70Yq0B6yhqEKoH0Yhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/3R/b9BD2zgvmo+lYDiiKspljq7TL0bd1wwrPt81JF0=; b=oEkgb3QWATAeTXE49Q8pwz6qiWzkpcjE/XWcazarv04Hglq9bLuQFWCyniFslFnj4ZwV+MiRK9iU9cJ8yC+wla5NGFmeL8687z2XMTD64b8c2DphfJmqkTMPJMatlMLu4Z3ltpRK5sXIAKnCsUcSs0SfhPhIG3v2sQyY8rVPS6x2VYK/T3F18XEWvfa+RP7xUoYke545yGIuq8kLZIBsakgggsjfRvZ97SAUOz6BZ7tfeWAuOjQVcJIRFuvasNK3CjbrHdIrO4piC1gSNhW3H3B5AmQDy8GRhzJejkDcvBenUTP/a5hvKdHNFpDsNCh8MsL+ZtC/yhBQwiHMGZvNQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/3R/b9BD2zgvmo+lYDiiKspljq7TL0bd1wwrPt81JF0=; b=aODT6Kor9VPzYwABVVfms4bwTUlb/PZVfdS2B6MMCL9YY5k1KFskEurw0DCLSlkNwkFA0iF8p5bGd5bNJVF0w4d/EB4UxJvssUMDvH3tepu+uGeuzdvwY74HYxJ6L/cTAUzNmTRQAlA40NyP9aY9fOUQR4F9Tsrd6hVmtQt2/JE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:29 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:29 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 164/256] cl8k: add reg/reg_riu.h Date: Thu, 17 Jun 2021 16:00:51 +0000 Message-Id: <20210617160223.160998-165-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:33 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e3cfb4a1-6fa7-4860-5139-08d931a9bcc9 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:608; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M6S6gRkbNLZnt/xI7Ymag09qonjHnQVrpNpc/RWCEX2S5jfTkA3/v9EqxSSym3HU0nZfXgTIkby91Iu4mjSgvo6vwuuMYAKVOFO1A34CkUrd3CLVvRFhiWZyXJ7fKJa8tp9K+cUeGC/EuJcT4NYmgdXHRv+y0BMh6pgGRvQS8FGpa6RpDxD6qRXU/u+BtVSGQYIHXM9dzi57puMcxJ2QagJib9SmaFVzmd8NAGQ8Uo5mA2frX6J4nUHnc0jHGXyOD5goYARvbwZsMWe0R4LyghdzFiZ/77I0+b6jqlFGf6g6/qR2kKGWrBthsYEJT5ODBtS76kxU0Elr5+OZ1SJWvlM/7VTXa+jPMgMN42JCbsU4i7RVEJhsbPHCs6zQ82iaQAqV35PKeRGyj8iKIni3jq/oHZDLdvEe/rQAqEUD10p3VHjahhufhO3UfQvV2ODqq90Ic/W6v5DvkTeu+HaKrSy1BSBwRbm9O5raTxveouID1zn29U+vqzhNNPG3Y2sZ5A/XdcB8dTq7VzwTeO70VlCljaO4EC5pMrXhOzZ9x0QezzpffjQ08IhtzBpwBMFWZYwJCQfUVU83fT0A4nMWufcLuPFMT0EmFlcFcomewQHYXX1GuoapgyDuhcVunVZpe7DP67VR7+MYgRFf3v4/AxfSDcDUT07ZNwCaptsXj0ChiHqHKzndlY2TH6K04qOsxg0dxg9w09HbXDgUci2G9Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(30864003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5sTjTJhkB97ZE9MP0kWeJCIHf6E4Y8fSC3VzbvPB6EiW4gVRcgLnC8opH7J9Hnqq/rfPQJyfdiBG+IwKF4yMYVhSrVQ4GFUJ9GxEClVT8BgIfX0zoKxkiVHSLqiRc6D1XrEiTcjPEjoG4vhncWGa0ub0RmwrQgv6wXa8SBwWoO3GDfj8I/r96HBI1k76k/gy/KdF0cZeT4xtWbnELahm05SH052MqG7LgW7ok/P6GdS5KxnF3KuHQe/UGDC691Bu/++k531vFPUv1o1BCQzZbQpbXjnLUZ8qu1E7KKvHLUijgfXwbGSyoqfSgmE7I3QJjOsmrvYNsCVgB3IVNhPUEidqQo0e6jRw3pWlPm8KsXozGRrmZ4p9JQG/x/aOn7SVmf11YqmQknKyVG8uZcN+kNzmHl4UJubLnf3SoftDqUlRZokFBn7f66gLbsQcMEnqq2mv9aTze9REmmYk35HFDu2xghVdig5kO4uBPuVdvgW1O5Sd67MzeSfZuB/HvjkG8DoaG5Q/Bb0mA9Vz512fFKTijunPTo5a4KO9kBQRERAK/nWBe3Oi87rAh+JJmWIrFrrVWsxyGzYbM42xTsRqEwg4WjGSHQ4nP98hGpxe81sA0pNxJzCWOKh6G3Z5zwzk3Z3NEfS03i0/Le2As7dJh/KoZ71FZxUd1GoBVYktjYsz+jDjEow5jI6AwJUSI1/l50lfdzdnoqM1wn/kLyQImE7VVuMd/PveO8vDzhzmXu0knaLlDJMTMpezujP/VsA/GfTdp7ve6Ri8u/Cw1RT3IpBRVC9lkoz6Efj5Xipd2YqvqzoNzuIM3wZMDF19XmdYifKicsr4O4rbYdHmeYuuiFyurCqVO8NIt+YCTrywlpTZkpK8Nhdxdfe4+sM1mZ3aBzGVLQGgxWqEKLTcgO11uGeM/zxnSoKP/r9htPH3p9rkbUjZMclaBr2U1gD8J/bRv6XnX7T2000DiVb6bHaxeurdpU3XCaIfIEjNn4LrhlL2cyvxuurqEHZgXqtP7ApFGnHzrsc+O7EigvOY5Aas8HAgPIZ+nzZrE7DrQyZojOhUiFT//Y1IJZp7ocrZvw26NLrlu3KbAZfuOmN2toMY7qvyoPttsluXeAISgdYB0gBQ/NUJYCypwgDFogp9blgcHd4GvhU5vHXVsIR3kA01BBkSedIa7R+1JiSPEGY+8arZxHaooBHvzb68iSOYMe3s/IN6rCZnlnAh106kx+Hm4ygcrjfOg5HsnKmrH4HZAtnTNjVkBfBx/0WZi7R1EvQmcZAmcJo4oHRfOHGWtuE8Fq3DVglgU1xewY7UxhifuiwBxDHCKY8Fowih3hzSC6T+ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: e3cfb4a1-6fa7-4860-5139-08d931a9bcc9 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:33.8131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CaQorMnUbaTkN8l0Ihfq8SBe18TjOxMPff5GmN8gYIx4DEXgpVMBRCMEvc7Ln0uqR/4qAaRDOqkSKJLbsN1LsQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/reg/reg_riu.h | 902 ++++++++++++++++++ 1 file changed, 902 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_riu.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_riu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_riu.h new file mode 100644 index 000000000000..15df2dcb13ee --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_riu.h @@ -0,0 +1,902 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_RIU_H +#define CL_REG_RIU_H + +#include +#include "reg/reg_access.h" +#include "hw.h" + +#define RIU_RSF_FILE_SIZE 0x60C + +/* + * @brief CCA_CNT_CS register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_CS                0x0
+ *
+ */ +#define RIU_CCA_CNT_CS_ADDR (REG_RIU_BASE_ADDR + 0x00000058) +#define RIU_CCA_CNT_CS_OFFSET 0x00000058 +#define RIU_CCA_CNT_CS_INDEX 0x00000016 +#define RIU_CCA_CNT_CS_RESET 0x00000000 + +static inline u32 riu_cca_cnt_cs_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_CS_ADDR); +} + +/* + * @brief RSF_CONTROL register definition + * resampling filter operation mode register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    rsf_init_en               1
+ *    07    rsf_tx_bypass_type        0
+ *    06    rsf_tx_bypass_mode        1
+ *    05    rsf_rx_bypass_type        0
+ *    04    rsf_rx_bypass_mode        1
+ *    01    rsf_rx_ctl_from_reg       1
+ *
+ */ +#define RIU_RSF_CONTROL_ADDR (REG_RIU_BASE_ADDR + 0x000001A8) +#define RIU_RSF_CONTROL_OFFSET 0x000001A8 +#define RIU_RSF_CONTROL_INDEX 0x0000006A +#define RIU_RSF_CONTROL_RESET 0x80000053 + +static inline void riu_rsf_control_rsf_init_en_setf(struct cl_hw *cl_hw, u8 rsfiniten) +{ + cl_reg_write(cl_hw, RIU_RSF_CONTROL_ADDR, + (cl_reg_read(cl_hw, RIU_RSF_CONTROL_ADDR) & ~((u32)0x80000000)) | ((u32)rsfiniten << 31)); +} + +/* + * @brief RSF_INIT register definition + * resampling filter initialization data register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 RSF_INIT_DATA             0x0
+ *
+ */ +#define RIU_RSF_INIT_ADDR (REG_RIU_BASE_ADDR + 0x000001AC) +#define RIU_RSF_INIT_OFFSET 0x000001AC +#define RIU_RSF_INIT_INDEX 0x0000006B +#define RIU_RSF_INIT_RESET 0x00000000 + +static inline void riu_rsf_init_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, RIU_RSF_INIT_ADDR, value); +} + +/* + * @brief AGCFSM_RAM_INIT_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    AGC_FSM_RAM_INIT_EN       0
+ *    29    AGC_FSM_RAM_INIT_AINC2    0
+ *    28    AGC_FSM_RAM_INIT_AINC1    0
+ *    12    AGC_FSM_RAM_INIT_WPTR_SET 0
+ *    10:00 AGC_FSM_RAM_INIT_WPTR     0x0
+ *
+ */ +#define RIU_AGCFSM_RAM_INIT_1_ADDR (REG_RIU_BASE_ADDR + 0x000001B0) +#define RIU_AGCFSM_RAM_INIT_1_OFFSET 0x000001B0 +#define RIU_AGCFSM_RAM_INIT_1_INDEX 0x0000006C +#define RIU_AGCFSM_RAM_INIT_1_RESET 0x00000000 + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_wptr_setf(struct cl_hw *cl_hw, + u16 agcfsmraminitwptr) +{ + ASSERT_ERR((((u32)agcfsmraminitwptr << 0) & ~((u32)0x000007FF)) == 0); + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x000007FF)) | ((u32)agcfsmraminitwptr << 0)); +} + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_wptr_set_setf(struct cl_hw *cl_hw, u8 agcfsmraminitwptrset) +{ + ASSERT_ERR((((u32)agcfsmraminitwptrset << 12) & ~((u32)0x00001000)) == 0); + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x00001000)) | ((u32)agcfsmraminitwptrset << 12)); +} + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_ainc_1_setf(struct cl_hw *cl_hw, + u8 agcfsmraminitainc1) +{ + ASSERT_ERR((((u32)agcfsmraminitainc1 << 28) & ~((u32)0x10000000)) == 0); + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x10000000)) | ((u32)agcfsmraminitainc1 << 28)); +} + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_en_setf(struct cl_hw *cl_hw, + u8 agcfsmraminiten) +{ + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x80000000)) | ((u32)agcfsmraminiten << 31)); +} + +/* + * @brief AGCFSM_RAM_INIT_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 AGC_FSM_RAM_INIT_WDATA    0x0
+ *
+ */ +#define RIU_AGCFSM_RAM_INIT_2_ADDR (REG_RIU_BASE_ADDR + 0x000001B4) +#define RIU_AGCFSM_RAM_INIT_2_OFFSET 0x000001B4 +#define RIU_AGCFSM_RAM_INIT_2_INDEX 0x0000006D +#define RIU_AGCFSM_RAM_INIT_2_RESET 0x00000000 + +static inline void riu_agcfsm_ram_init_2_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_2_ADDR, value); +} + +/* + * @brief AGCINBDPOW_20_STAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PDBM3           0x0
+ *    23:16 INBDPOW20_PDBM2           0x0
+ *    15:08 INBDPOW20_PDBM1           0x0
+ *    07:00 INBDPOW20_PDBM0           0x0
+ *
+ */ +#define RIU_AGCINBDPOW_20_STAT_ADDR (REG_RIU_BASE_ADDR + 0x0000020C) +#define RIU_AGCINBDPOW_20_STAT_OFFSET 0x0000020C +#define RIU_AGCINBDPOW_20_STAT_INDEX 0x00000083 +#define RIU_AGCINBDPOW_20_STAT_RESET 0x00000000 + +static inline void riu_agcinbdpow_20_stat_unpack(struct cl_hw *cl_hw, + u8 *inbdpow20pdbm3, u8 *inbdpow20pdbm2, + u8 *inbdpow20pdbm1, u8 *inbdpow20pdbm0) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_AGCINBDPOW_20_STAT_ADDR); + + *inbdpow20pdbm3 = (local_val & ((u32)0xFF000000)) >> 24; + *inbdpow20pdbm2 = (local_val & ((u32)0x00FF0000)) >> 16; + *inbdpow20pdbm1 = (local_val & ((u32)0x0000FF00)) >> 8; + *inbdpow20pdbm0 = (local_val & ((u32)0x000000FF)) >> 0; +} + +/* + * @brief AGCINBDPOW_20_PNOISESTAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PNOISEDBM3      0x0
+ *    23:16 INBDPOW20_PNOISEDBM2      0x0
+ *    15:08 INBDPOW20_PNOISEDBM1      0x0
+ *    07:00 INBDPOW20_PNOISEDBM0      0x0
+ *
+ */ +#define RIU_AGCINBDPOW_20_PNOISESTAT_ADDR (REG_RIU_BASE_ADDR + 0x00000228) +#define RIU_AGCINBDPOW_20_PNOISESTAT_OFFSET 0x00000228 +#define RIU_AGCINBDPOW_20_PNOISESTAT_INDEX 0x0000008A +#define RIU_AGCINBDPOW_20_PNOISESTAT_RESET 0x00000000 + +static inline u32 riu_agcinbdpow_20_pnoisestat_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOW_20_PNOISESTAT_ADDR); +} + +/* + * @brief AGCINBDPOWSECNOISESTAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    23:16 INBDPOW80_SNOISEDBM       0x0
+ *    15:08 INBDPOW40_SNOISEDBM       0x0
+ *    07:00 INBDPOW20_SNOISEDBM       0x0
+ *
+ */ +#define RIU_AGCINBDPOWSECNOISESTAT_ADDR (REG_RIU_BASE_ADDR + 0x00000230) +#define RIU_AGCINBDPOWSECNOISESTAT_OFFSET 0x00000230 +#define RIU_AGCINBDPOWSECNOISESTAT_INDEX 0x0000008C +#define RIU_AGCINBDPOWSECNOISESTAT_RESET 0x00000000 + +static inline u32 riu_agcinbdpowsecnoisestat_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOWSECNOISESTAT_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_P register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_P     0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_P_ADDR (REG_RIU_BASE_ADDR + 0x000002DC) +#define RIU_CCA_CNT_MODEM_STATE_P_OFFSET 0x000002DC +#define RIU_CCA_CNT_MODEM_STATE_P_INDEX 0x000000B7 +#define RIU_CCA_CNT_MODEM_STATE_P_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_p_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_P_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_20_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_20_S  0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_20_S_ADDR (REG_RIU_BASE_ADDR + 0x000002E0) +#define RIU_CCA_CNT_MODEM_STATE_20_S_OFFSET 0x000002E0 +#define RIU_CCA_CNT_MODEM_STATE_20_S_INDEX 0x000000B8 +#define RIU_CCA_CNT_MODEM_STATE_20_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_20_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_20_S_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_40_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_40_S  0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_40_S_ADDR (REG_RIU_BASE_ADDR + 0x000002E4) +#define RIU_CCA_CNT_MODEM_STATE_40_S_OFFSET 0x000002E4 +#define RIU_CCA_CNT_MODEM_STATE_40_S_INDEX 0x000000B9 +#define RIU_CCA_CNT_MODEM_STATE_40_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_40_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_40_S_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_80_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_80_S  0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_80_S_ADDR (REG_RIU_BASE_ADDR + 0x000002E8) +#define RIU_CCA_CNT_MODEM_STATE_80_S_OFFSET 0x000002E8 +#define RIU_CCA_CNT_MODEM_STATE_80_S_INDEX 0x000000BA +#define RIU_CCA_CNT_MODEM_STATE_80_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_80_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_80_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_P register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_P      0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_P_ADDR (REG_RIU_BASE_ADDR + 0x000002F4) +#define RIU_CCA_CNT_ENERGY_THR_P_OFFSET 0x000002F4 +#define RIU_CCA_CNT_ENERGY_THR_P_INDEX 0x000000BD +#define RIU_CCA_CNT_ENERGY_THR_P_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_p_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_P_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_S   0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_S_ADDR (REG_RIU_BASE_ADDR + 0x000002F8) +#define RIU_CCA_CNT_ENERGY_THR_20_S_OFFSET 0x000002F8 +#define RIU_CCA_CNT_ENERGY_THR_20_S_INDEX 0x000000BE +#define RIU_CCA_CNT_ENERGY_THR_20_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_S_ADDR); +} + +/* + * @brief CCA_CNT_GI_20_P register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_20_P           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_20_P_ADDR (REG_RIU_BASE_ADDR + 0x000002FC) +#define RIU_CCA_CNT_GI_20_P_OFFSET 0x000002FC +#define RIU_CCA_CNT_GI_20_P_INDEX 0x000000BF +#define RIU_CCA_CNT_GI_20_P_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_20_p_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_20_P_ADDR); +} + +/* + * @brief RWNXAGCRAMP register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    26:24 RAMPDNNDLINDEX            0x5
+ *    23:16 RAMPDNGAPQDB              0x20
+ *    10:08 RAMPUPNDLINDEX            0x7
+ *    07:00 RAMPUPGAPQDB              0x10
+ *
+ */ +#define RIU_RWNXAGCRAMP_ADDR (REG_RIU_BASE_ADDR + 0x0000036C) +#define RIU_RWNXAGCRAMP_OFFSET 0x0000036C +#define RIU_RWNXAGCRAMP_INDEX 0x000000DB +#define RIU_RWNXAGCRAMP_RESET 0x05200710 + +static inline u8 riu_rwnxagcramp_rampupgapqdb_getf(struct cl_hw *cl_hw) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_RWNXAGCRAMP_ADDR); + + return ((local_val & ((u32)0x000000FF)) >> 0); +} + +static inline void riu_rwnxagcramp_rampupgapqdb_setf(struct cl_hw *cl_hw, u8 rampupgapqdb) +{ + cl_reg_write(cl_hw, RIU_RWNXAGCRAMP_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCRAMP_ADDR) & ~((u32)0x000000FF)) | ((u32)rampupgapqdb << 0)); +} + +/* + * @brief RWNXAGCCNTL register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:26 COMBPATHSEL               0x3F
+ *    25:20 GAINKEEP                  0x0
+ *    16    HTSTFGAINEN               1
+ *    15    NOISE_CAPTURE_DELAY_MODE  0
+ *    14    EST_PATH_SEL_2            0
+ *    13    CCA_MDM_ST_CLEAR          0
+ *    12    AGCFSMRESET               0
+ *    11    RADARDETEN                0
+ *    10    RIFSDETEN                 1
+ *    09    DSSSONLY                  0
+ *    08    OFDMONLY                  0
+ *    07:04 GPSTATUS                  0x0
+ *    03    EST_PATH_SEL              0
+ *    01    ADC_SEL_RADAR_DETECTOR    0
+ *    00    ADC_SEL_COMP_MODULE       0
+ *
+ */ +#define RIU_RWNXAGCCNTL_ADDR (REG_RIU_BASE_ADDR + 0x00000390) +#define RIU_RWNXAGCCNTL_OFFSET 0x00000390 +#define RIU_RWNXAGCCNTL_INDEX 0x000000E4 +#define RIU_RWNXAGCCNTL_RESET 0xFC010400 + +static inline void riu_rwnxagccntl_agcfsmreset_setf(struct cl_hw *cl_hw, u8 agcfsmreset) +{ + ASSERT_ERR((((u32)agcfsmreset << 12) & ~((u32)0x00001000)) == 0); + cl_reg_write(cl_hw, RIU_RWNXAGCCNTL_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCNTL_ADDR) & ~((u32)0x00001000)) | ((u32)agcfsmreset << 12)); +} + +/* + * @brief RWNXAGCCCA_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    CCA_CNT_CLEAR             0
+ *    30:29 CCA_CNT_RATE              0x0
+ *    28:20 INBDCCAPOWMINDBM          0x1B5
+ *    19:12 CCAFALLTHRDBM             0xBF
+ *    10    CCAEnergy_Reset_Type      0
+ *    09    DISCCAEN                  1
+ *    08    SATCCAEN                  1
+ *    07:00 CCARISETHRDBM             0xC2
+ *
+ */ +#define RIU_RWNXAGCCCA_1_ADDR (REG_RIU_BASE_ADDR + 0x000003AC) +#define RIU_RWNXAGCCCA_1_OFFSET 0x000003AC +#define RIU_RWNXAGCCCA_1_INDEX 0x000000EB +#define RIU_RWNXAGCCCA_1_RESET 0x1B5BF3C2 + +static inline void riu_rwnxagccca_1_cca_cnt_clear_setf(struct cl_hw *cl_hw, u8 ccacntclear) +{ + cl_reg_write(cl_hw, RIU_RWNXAGCCCA_1_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCCA_1_ADDR) & ~((u32)0x80000000)) | ((u32)ccacntclear << 31)); +} + +/* + * @brief RWNXAGCCCACTRL register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:28 CCAFLAG3_CTRL             0xA
+ *    27:24 CCAFLAG2_CTRL             0x2
+ *    23:20 CCAFLAG1_CTRL             0x8
+ *    19:16 CCAFLAG0_CTRL             0x0
+ *    14:12 CCA_SECOND_ANT_SEL        0x1
+ *    10:08 CCA_MAIN_ANT_SEL          0x0
+ *    07:04 CCADEMOD                  0xF
+ *    00    CCACSEN                   1
+ *
+ */ +#define RIU_RWNXAGCCCACTRL_ADDR (REG_RIU_BASE_ADDR + 0x000003B0) +#define RIU_RWNXAGCCCACTRL_OFFSET 0x000003B0 +#define RIU_RWNXAGCCCACTRL_INDEX 0x000000EC +#define RIU_RWNXAGCCCACTRL_RESET 0xA28010F1 + +static inline void riu_rwnxagcccactrl_cca_main_ant_sel_setf(struct cl_hw *cl_hw, u8 ccamainantsel) +{ + ASSERT_ERR((((u32)ccamainantsel << 8) & ~((u32)0x00000700)) == 0); + cl_reg_write(cl_hw, RIU_RWNXAGCCCACTRL_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCCACTRL_ADDR) & ~((u32)0x00000700)) | ((u32)ccamainantsel << 8)); +} + +/* + * @brief RWNXAGCCCASTATE_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    28    CCAMDMSTFORCEEN           0
+ *    27:24 CCAMDMSTFORCE             0x0
+ *    23:12 RXSTATECCA20_SSEL         0x380
+ *    11:00 RXSTATECCA20_PSEL         0x3F8
+ *
+ */ +#define RIU_RWNXAGCCCASTATE_0_ADDR (REG_RIU_BASE_ADDR + 0x000003B4) +#define RIU_RWNXAGCCCASTATE_0_OFFSET 0x000003B4 +#define RIU_RWNXAGCCCASTATE_0_INDEX 0x000000ED +#define RIU_RWNXAGCCCASTATE_0_RESET 0x003803F8 + +static inline void riu_rwnxagcccastate_0_rxstatecca_20_psel_setf(struct cl_hw *cl_hw, + u16 rxstatecca20psel) +{ + ASSERT_ERR((((u32)rxstatecca20psel << 0) & ~((u32)0x00000FFF)) == 0); + cl_reg_write(cl_hw, RIU_RWNXAGCCCASTATE_0_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCCASTATE_0_ADDR) & ~((u32)0x00000FFF)) | ((u32)rxstatecca20psel << 0)); +} + +/* + * @brief AGCINBDPOWNOISEPER_20_STAT_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWNOISEDBMPER20_3    0x0
+ *    23:16 INBDPOWNOISEDBMPER20_2    0x0
+ *    15:08 INBDPOWNOISEDBMPER20_1    0x0
+ *    07:00 INBDPOWNOISEDBMPER20_0    0x0
+ *
+ */ +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_ADDR (REG_RIU_BASE_ADDR + 0x00000478) +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_OFFSET 0x00000478 +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_INDEX 0x0000011E +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_RESET 0x00000000 + +static inline u32 riu_agcinbdpownoiseper_20_stat_0_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOWNOISEPER_20_STAT_0_ADDR); +} + +/* + * @brief AGCINBDPOWNOISEPER_20_STAT_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWNOISEDBMPER20_7    0x0
+ *    23:16 INBDPOWNOISEDBMPER20_6    0x0
+ *    15:08 INBDPOWNOISEDBMPER20_5    0x0
+ *    07:00 INBDPOWNOISEDBMPER20_4    0x0
+ *
+ */ +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_ADDR (REG_RIU_BASE_ADDR + 0x0000047C) +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_OFFSET 0x0000047C +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_INDEX 0x0000011F +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_RESET 0x00000000 + +static inline u32 riu_agcinbdpownoiseper_20_stat_1_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOWNOISEPER_20_STAT_1_ADDR); +} + +/* + * @brief INBDPOWFORMAC_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PDBMA3_MAC      0x0
+ *    23:16 INBDPOW20_PDBMA2_MAC      0x0
+ *    15:08 INBDPOW20_PDBMA1_MAC      0x0
+ *    07:00 INBDPOW20_PDBMA0_MAC      0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_0_ADDR (REG_RIU_BASE_ADDR + 0x00000480) +#define RIU_INBDPOWFORMAC_0_OFFSET 0x00000480 +#define RIU_INBDPOWFORMAC_0_INDEX 0x00000120 +#define RIU_INBDPOWFORMAC_0_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_0_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_0_ADDR); +} + +/* + * @brief INBDPOWFORMAC_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    15:08 INBDPOW20_PDBMA5_MAC      0x0
+ *    07:00 INBDPOW20_PDBMA4_MAC      0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_1_ADDR (REG_RIU_BASE_ADDR + 0x00000484) +#define RIU_INBDPOWFORMAC_1_OFFSET 0x00000484 +#define RIU_INBDPOWFORMAC_1_INDEX 0x00000121 +#define RIU_INBDPOWFORMAC_1_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_1_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_1_ADDR); +} + +/* + * @brief INBDPOWFORMAC_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    23:16 INBDPOW80_SDBM_MAC        0x0
+ *    15:08 INBDPOW40_SDBM_MAC        0x0
+ *    07:00 INBDPOW20_SDBM_MAC        0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_2_ADDR (REG_RIU_BASE_ADDR + 0x00000488) +#define RIU_INBDPOWFORMAC_2_OFFSET 0x00000488 +#define RIU_INBDPOWFORMAC_2_INDEX 0x00000122 +#define RIU_INBDPOWFORMAC_2_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_2_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_2_ADDR); +} + +/* + * @brief INBDPOWFORMAC_3 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWPER20_PDBM_3_MAC   0x0
+ *    23:16 INBDPOWPER20_PDBM_2_MAC   0x0
+ *    15:08 INBDPOWPER20_PDBM_1_MAC   0x0
+ *    07:00 INBDPOWPER20_PDBM_0_MAC   0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_3_ADDR (REG_RIU_BASE_ADDR + 0x0000048C) +#define RIU_INBDPOWFORMAC_3_OFFSET 0x0000048C +#define RIU_INBDPOWFORMAC_3_INDEX 0x00000123 +#define RIU_INBDPOWFORMAC_3_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_3_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_3_ADDR); +} + +/* + * @brief INBDPOWFORMAC_4 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWPER20_PDBM_7_MAC   0x0
+ *    23:16 INBDPOWPER20_PDBM_6_MAC   0x0
+ *    15:08 INBDPOWPER20_PDBM_5_MAC   0x0
+ *    07:00 INBDPOWPER20_PDBM_4_MAC   0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_4_ADDR (REG_RIU_BASE_ADDR + 0x00000490) +#define RIU_INBDPOWFORMAC_4_OFFSET 0x00000490 +#define RIU_INBDPOWFORMAC_4_INDEX 0x00000124 +#define RIU_INBDPOWFORMAC_4_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_4_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_4_ADDR); +} + +/* + * @brief CCA_CNT_GI_20_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_20_S           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_20_S_ADDR (REG_RIU_BASE_ADDR + 0x00000494) +#define RIU_CCA_CNT_GI_20_S_OFFSET 0x00000494 +#define RIU_CCA_CNT_GI_20_S_INDEX 0x00000125 +#define RIU_CCA_CNT_GI_20_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_20_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_20_S_ADDR); +} + +/* + * @brief CCA_CNT_GI_40_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_40_S           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_40_S_ADDR (REG_RIU_BASE_ADDR + 0x00000498) +#define RIU_CCA_CNT_GI_40_S_OFFSET 0x00000498 +#define RIU_CCA_CNT_GI_40_S_INDEX 0x00000126 +#define RIU_CCA_CNT_GI_40_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_40_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_40_S_ADDR); +} + +/* + * @brief CCA_CNT_GI_80_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_80_S           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_80_S_ADDR (REG_RIU_BASE_ADDR + 0x0000049C) +#define RIU_CCA_CNT_GI_80_S_OFFSET 0x0000049C +#define RIU_CCA_CNT_GI_80_S_INDEX 0x00000127 +#define RIU_CCA_CNT_GI_80_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_80_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_80_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_40_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_40_S   0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_40_S_ADDR (REG_RIU_BASE_ADDR + 0x000004A0) +#define RIU_CCA_CNT_ENERGY_THR_40_S_OFFSET 0x000004A0 +#define RIU_CCA_CNT_ENERGY_THR_40_S_INDEX 0x00000128 +#define RIU_CCA_CNT_ENERGY_THR_40_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_40_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_40_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_80_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_80_S   0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_80_S_ADDR (REG_RIU_BASE_ADDR + 0x000004A4) +#define RIU_CCA_CNT_ENERGY_THR_80_S_OFFSET 0x000004A4 +#define RIU_CCA_CNT_ENERGY_THR_80_S_INDEX 0x00000129 +#define RIU_CCA_CNT_ENERGY_THR_80_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_80_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_80_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_0 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_ADDR (REG_RIU_BASE_ADDR + 0x000004A8) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_OFFSET 0x000004A8 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_INDEX 0x0000012A +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_0_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_0_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_1 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_ADDR (REG_RIU_BASE_ADDR + 0x000004AC) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_OFFSET 0x000004AC +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_INDEX 0x0000012B +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_1_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_1_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_2 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_ADDR (REG_RIU_BASE_ADDR + 0x000004B0) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_OFFSET 0x000004B0 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_INDEX 0x0000012C +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_2_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_2_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_3 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_3 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_ADDR (REG_RIU_BASE_ADDR + 0x000004B4) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_OFFSET 0x000004B4 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_INDEX 0x0000012D +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_3_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_3_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_4 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_4 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_ADDR (REG_RIU_BASE_ADDR + 0x000004B8) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_OFFSET 0x000004B8 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_INDEX 0x0000012E +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_4_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_4_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_5 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_5 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_ADDR (REG_RIU_BASE_ADDR + 0x000004BC) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_OFFSET 0x000004BC +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_INDEX 0x0000012F +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_5_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_5_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_6 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_6 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_ADDR (REG_RIU_BASE_ADDR + 0x000004C0) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_OFFSET 0x000004C0 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_INDEX 0x00000130 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_6_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_6_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_7 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_7 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_ADDR (REG_RIU_BASE_ADDR + 0x000004C4) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_OFFSET 0x000004C4 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_INDEX 0x00000131 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_7_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_7_ADDR); +} + +/* + * @brief AGCADCPOWSTAT_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PDBM5           0x0
+ *    23:16 INBDPOW20_PDBM4           0x0
+ *    14:08 ADCPOWDBV5                0x0
+ *    06:00 ADCPOWDBV4                0x0
+ *
+ */ +#define RIU_AGCADCPOWSTAT_2_ADDR (REG_RIU_BASE_ADDR + 0x00000670) +#define RIU_AGCADCPOWSTAT_2_OFFSET 0x00000670 +#define RIU_AGCADCPOWSTAT_2_INDEX 0x0000019C +#define RIU_AGCADCPOWSTAT_2_RESET 0x00000000 + +static inline void riu_agcadcpowstat_2_unpack(struct cl_hw *cl_hw, + u8 *inbdpow20pdbm5, u8 *inbdpow20pdbm4, + u8 *adcpowdbv5, u8 *adcpowdbv4) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_AGCADCPOWSTAT_2_ADDR); + + *inbdpow20pdbm5 = (local_val & ((u32)0xFF000000)) >> 24; + *inbdpow20pdbm4 = (local_val & ((u32)0x00FF0000)) >> 16; + *adcpowdbv5 = (local_val & ((u32)0x00007F00)) >> 8; + *adcpowdbv4 = (local_val & ((u32)0x0000007F)) >> 0; +} + +/* + * @brief AGCINBDPOW_20_PNOISESTAT_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PNOISEDBM5      0x0
+ *    23:16 INBDPOW20_PNOISEDBM4      0x0
+ *    15:08 ADCPOWDBM5                0x0
+ *    07:00 ADCPOWDBM4                0x0
+ *
+ */ +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_ADDR (REG_RIU_BASE_ADDR + 0x0000067C) +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_OFFSET 0x0000067C +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_INDEX 0x0000019F +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_RESET 0x00000000 + +static inline u32 riu_agcinbdpow_20_pnoisestat_2_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOW_20_PNOISESTAT_2_ADDR); +} + +#endif /*_REG_RIU_H_ */ From patchwork Thu Jun 17 16:00:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96ED7C2B9F4 for ; Thu, 17 Jun 2021 16:09:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 811F36141F for ; Thu, 17 Jun 2021 16:09:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231621AbhFQQLp (ORCPT ); Thu, 17 Jun 2021 12:11:45 -0400 Received: from mail-eopbgr30061.outbound.protection.outlook.com ([40.107.3.61]:14471 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231889AbhFQQK0 (ORCPT ); Thu, 17 Jun 2021 12:10:26 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CVbtzZrQQyO/fL7xOLHYayln83GSpxP8Fy/hHkFFPkF0xHD1NuxIyoNwdxajLeAi5h6ne7NKSwcEbC6S5OaAx8gfRZpdD3p+cSPCsAk0QeQYrc/1GdhKl3mW04IzpEiQnK2AEZM2e7pc5S65/yaUY4yqZU6gTG9a6L6hAi1KBm9buSXH5vM3tUS1GHWbqjL1RwpS/QrhX0i6pdBt0p+9MrgbXFyU6tqOTjTBCmBCTeEiBijAwUik9Ajkf3dfd3HH41O/mzFI1c4uUQfsIl91qoVKtUBvK/AndgAop0eOGSCnqVSfTKSSh7ldt7gBXSF6lTIaoF4D7z+LlWPA3+iOsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6n80FhqlvDQm8Df+kvJDZOnhYx03D33Ar85HQ2gZeSo=; b=fzWzxZXX2OJQ7ktmIK3s80g4uIpGbPUsTs13fYB+yWGV08LQe+5vpK3dwePhyI05LoJcjPKXdM4WNegA0DCWL078a9wWrol3BRQPobGcV093q/4DSuOva+SwIB6/EYoXUAhNjrlwCxhKM86xu7doWNJ76idx3pn4egKK2UI4CXdmD5BzvkHBhiRuuGBJF1CSpsKBt1qH+hHo3n6bThsJOsX73fIe5AKKWBZ9GH3P8kv90eBQ3leJnpFOwfNXzuD4p7BmJbECXWccAixYton9p9Vg0SwO3bfM3MBTGb1qdRcBaB68R2z0yO+22JhGKZ8m95Zq4OiVg488zB4mYW0eUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6n80FhqlvDQm8Df+kvJDZOnhYx03D33Ar85HQ2gZeSo=; b=F/vBQCByGDoyDo9COPOktcDuUJnvxsenyMSzE45lyfAST1IUUAmZ+V1yr/OpOyNLn90SdISaNnoH3Ae8zsLEDGanXDewQ3qSYd1B6mZpVcWT0foNDtYi3mT5x9YuME1JW6RcyB/LdmQcOMwcZ8C+CX9qNFtChPnQ8ZQldmzAFb8= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:29 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:29 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 165/256] cl8k: add reg/reg_riu_rc.h Date: Thu, 17 Jun 2021 16:00:52 +0000 Message-Id: <20210617160223.160998-166-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:34 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 705d5200-17ca-46b4-1b4c-08d931a9bd96 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JTvZCs1Pdh35MASEEkcOwcxuQCPlG9Zq//0zQ0XYQEwyKemhf78OAQBQUJJ/yYcV0NxX6cVehPCCZ3RQ9122UrF/bQxzKvHg9fricuZH/YSHw2yoIhN0CuYSzd21TuZSquopa4HMfuZeNwXJV5S+xZO0saHyaHNT0Mng/3U0azbyXTUt98XiqtEhPxbrpvxb/lFvVO+TyrKlduB/bt9iPv5HRL4k6PJ9Dxw4q3UgF23qJXzPT3j11h55wvBnzgd3SSyPbDvTqz6+wRPedrLxVglu7/1iudsChNlYNfc+HGvHVN9uBIWAF6eR41YtlJP01uPISF45dkhKceZKbBfRZP1yIYSU+v35h4m13Fn6DkyHW2HYPMYoSWaTaEDMBaXW9Dz4TK5jC73Pn9y9i197FEGwg5aA/rhw7dez/2vkbHBQItI9vunBcZg6HNx7T6Fe3FNWzvNxJRgNLB4PblxmV19/ag2KOZ6XwnOpVSLDGh5BhphHZvE9ZEuU0Iru2X+d8uqxZr9SD3NJY5uCQEsvzv67ouagnKkyGz8YO30m5OBciYLLrPRsjWBPyrAkLr2AjzFjB0oSkfOkoAVDwaYc9WzqgiRZBJZmDJwURJry9NNJSSGkGjCaN9zdx+0dMeEWEKuMkTi8u/MIzMzouAh/ZoW7DEWq5S2W9vqova5XRqsTaaQVGGNEUrEeKOz9vJtibTL5NcOEQjUdxtNpOry2mA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 673w7unRHcyp+PCAhGrPu58gfhYuY0agUdGrNp5wino0Mhc4mqhDE71hc8uItp6cq2/QCPkSTn0q6NU5BcwG/SB1w/LxwqmddXf7ZtP5cHWg/zeXe3JQVOrbe1dFkW0SlmmxtaL1xFGqEa2TG2jt6Ad9IUhMy7cLujH2XWohvZXcZXL+SHeQgJRQ2WMjbMfvK5onGI64WGjLdo+ah2jtYMdlhA7MhWA8ibW3mloNliSLcBbR78sXufjST6qEnJaifVc72VE7pmGP1uYeuJxD179J6l3NuqEIQwbQ1CUC7GRX+btlnTwDB1Skji8KN9riwmfhIA7hlA6CFl8xU/jEStOIiMKmtHQUv4mfmnXCExj8VryvxBcPGHB4W3b8N9yqFDB5R6LPcKC0AP8yXUkYPWp5NUefSD4IlTU3HlgCx1WbKV5GY20deEOcgFSzzv6qtMeDfl1lDGFnnYRR5yW6A8JrFpmE4qwHuCZLYu1AlPZI6uhfoDtJh4gP9SMOFWN3oZkHsHmeRwJuzapKlmaS9hvPJxDuTszD0TSoEOpZCEBdEkaEdEl+WYcMwe9NR10SWsqBmb72S9Sd/LUotXDMkUW87fa3k+7uslSNQ0sIg0iqvCT/onmuAKH9ApJvF60asmgloU92dX7GuIcSTOwpxHi0qTroNw8AD0LoAsmoY6tfpOyn6A4El+v06VizUU/wmz5ALcIH+uJ29s1SCmdbivf56Yf+3O77+yckJg65vXVlzjfDahUw8x9eyh9HDMNnrdrePORt0Md0g2T624J/GLkPdax1zj6ZIpDYVEvEDKKGkYK4ZdlpeeKNJrUYpJYzuNZgSLiY83A2JsZgvKqSOlYSibskISMr0uoTq1RYP1AlT/8hHgvMoEi6oHcZGLZYsSAcPNC5Om8xcgKSvDvMDBc/Lh+1vUBMlZWd4aAbN4Q8hhnVUJTtk0eL3JxaPaVZmT38iIzlPNsjVC80Gsg65tbzPS3LtmzprgpYSYdPl3MFbg2wZfMzJxysVQP15JhGJMX00isKi+hv78+H8ZK63eTRirEHDlQtMyzDUUn6Tbcm3qCW+asDp+JrA1qkPzZSVmU2umGnLYRrmnFsQ2y5jV1IeDsIqm4ldxMGk4y+uIjtNzUHojaDNnsSVJQbIVnFtPJBkpoJ+99QGCy2B0q0GZkjFSwrhs+XVjBTxbEbdRzBkohtEp6KN7xgLJ1MffgGjHlSpBNf1raaJ1xMcdWjFAPUWqaHtGn02eYtNCn+a0FzxwlpCohr1AdpIgemUrlhKvulNcPKriXZ7+d04fK6Fc1vu2DYn/5o6ho29LjkX3lOKzCAsjhS+ePqOgnP1Lt4 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 705d5200-17ca-46b4-1b4c-08d931a9bd96 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:35.0965 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: G2aJr/DrWwPxNEG4KkyBW2hninZgSP6UUpfMk3ubue4yj7A3DJ5mG5Byl+CKFaAnqxZp2zWk5eMLoJoJW1NGXQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/reg/reg_riu_rc.h | 115 ++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_riu_rc.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_riu_rc.h b/drivers/net/wireless/celeno/cl8k/reg/reg_riu_rc.h new file mode 100644 index 000000000000..320a460df4f1 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/reg/reg_riu_rc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_RC_H +#define CL_REG_RC_H + +#include +#include "reg/reg_access.h" +#include "hw.h" + +#define REG_RIU_RC_BASE_ADDR 0x00485000 + +/* + * @brief SW_CTRL register definition + * This register provides write access to the radio SPI interface register description + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   31    START_DONE                0
+ *   30    MORE                      0
+ *   29    FASTWR_SPD                0
+ *   28    FASTWR_FORCE              0
+ *   27    FWR_HW_ENABLE             1
+ *   26    FWR_SW_ENABLE             1
+ *   25    FWR_ENABLE                1
+ *   24    RF_RESET_B                0
+ *   23:19 PRESCALER                 0x1
+ *   16    READNOTWRITE              0
+ *   14:08 ADDRESS                   0x0
+ *   07:00 DATA                      0x0
+ *
+ */ +#define RIU_RC_SW_CTRL_ADDR (REG_RIU_RC_BASE_ADDR + 0x00000000) +#define RIU_RC_SW_CTRL_OFFSET 0x00000000 +#define RIU_RC_SW_CTRL_INDEX 0x00000000 +#define RIU_RC_SW_CTRL_RESET 0x0E080000 + +static inline void riu_rc_sw_ctrl_pack(struct cl_hw *cl_hw, u8 startdone, u8 more, u8 fastwrspd, + u8 fastwrforce, u8 fwrhwenable, u8 fwrswenable, u8 fwrenable, + u8 rfresetb, u8 prescaler, u8 readnotwrite, u8 address, + u8 data) +{ + ASSERT_ERR((((u32)more << 30) & ~((u32)0x40000000)) == 0); + ASSERT_ERR((((u32)fastwrspd << 29) & ~((u32)0x20000000)) == 0); + ASSERT_ERR((((u32)fastwrforce << 28) & ~((u32)0x10000000)) == 0); + ASSERT_ERR((((u32)fwrhwenable << 27) & ~((u32)0x08000000)) == 0); + ASSERT_ERR((((u32)fwrswenable << 26) & ~((u32)0x04000000)) == 0); + ASSERT_ERR((((u32)fwrenable << 25) & ~((u32)0x02000000)) == 0); + ASSERT_ERR((((u32)rfresetb << 24) & ~((u32)0x01000000)) == 0); + ASSERT_ERR((((u32)prescaler << 19) & ~((u32)0x00F80000)) == 0); + ASSERT_ERR((((u32)readnotwrite << 16) & ~((u32)0x00010000)) == 0); + ASSERT_ERR((((u32)address << 8) & ~((u32)0x00007F00)) == 0); + + cl_reg_write(cl_hw, RIU_RC_SW_CTRL_ADDR, ((u32)startdone << 31) | ((u32)more << 30) | + ((u32)fastwrspd << 29) | ((u32)fastwrforce << 28) | ((u32)fwrhwenable << 27) | + ((u32)fwrswenable << 26) | ((u32)fwrenable << 25) | ((u32)rfresetb << 24) | + ((u32)prescaler << 19) | ((u32)readnotwrite << 16) | ((u32)address << 8) | + ((u32)data << 0)); +} + +static inline u8 riu_rc_sw_ctrl_start_done_getf(struct cl_hw *cl_hw) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_RC_SW_CTRL_ADDR); + + return ((local_val & ((u32)0x80000000)) >> 31); +} + +static inline u8 riu_rc_sw_ctrl_data_getf(struct cl_hw *cl_hw) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_RC_SW_CTRL_ADDR); + + return ((local_val & ((u32)0x000000FF)) >> 0); +} + +/* + * @brief RF_LNA_LUT register definition + * These registers provide control of the RF LNA assertion by decoding each possible value the AGC + * LNA gain setting, from minimum LNA gain to maximum LNA gain. register description + * 
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   26:24 RFLNALUT6                 0x6
+ *   22:20 RFLNALUT5                 0x5
+ *   18:16 RFLNALUT4                 0x4
+ *   14:12 RFLNALUT3                 0x3
+ *   10:08 RFLNALUT2                 0x2
+ *   06:04 RFLNALUT1                 0x1
+ *   02:00 RFLNALUT0                 0x0
+ *
+ */ + +/* Field definitions */ +#define RIU_RC_RF_LNA_LUT_RFLNALUT_6_MASK ((u32)0x07000000) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_6_LSB 24 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_6_WIDTH ((u32)0x00000003) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_5_MASK ((u32)0x00700000) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_5_LSB 20 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_5_WIDTH ((u32)0x00000003) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_4_MASK ((u32)0x00070000) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_4_LSB 16 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_4_WIDTH ((u32)0x00000003) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_3_MASK ((u32)0x00007000) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_3_LSB 12 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_3_WIDTH ((u32)0x00000003) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_2_MASK ((u32)0x00000700) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_2_LSB 8 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_2_WIDTH ((u32)0x00000003) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_1_MASK ((u32)0x00000070) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_1_LSB 4 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_1_WIDTH ((u32)0x00000003) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_0_MASK ((u32)0x00000007) +#define RIU_RC_RF_LNA_LUT_RFLNALUT_0_LSB 0 +#define RIU_RC_RF_LNA_LUT_RFLNALUT_0_WIDTH ((u32)0x00000003) + +#endif /* CL_REG_RC_H */ From patchwork Thu Jun 17 16:00:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5A53C49361 for ; Thu, 17 Jun 2021 16:09:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C976F61425 for ; Thu, 17 Jun 2021 16:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232604AbhFQQMA (ORCPT ); Thu, 17 Jun 2021 12:12:00 -0400 Received: from mail-eopbgr70043.outbound.protection.outlook.com ([40.107.7.43]:64066 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231455AbhFQQKo (ORCPT ); Thu, 17 Jun 2021 12:10:44 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=azRdw3RMpzE58/dMHOmaGXwN/LraPbVXVRUi6w/Shphn6MEueuGi75nevjYiCPIcPI+SMcMXj7tn0LN+7/JoYcvXjoZwa7FP7r8VGD3rRly3QRaVE+oj77qTnQuxeDh7jBhJjzVl3VkUkUeJXeBFZftSpBRbBNBXZe40J5hshF07jPDeJumIZ6+PqfFAxliooBgJhIUNDjwQW56Z/c1Y+ne/y/bBvmqKJOFnwQOKtpx+m+yXACR5ra2GX6OImFs8lIn09eKnEjvXj8FS6AhyvIDdU+RMLReFjND5I3caAnxXpzPLqeZLHL54lGJBCw/+HQUxEm3UfIgWH2yt9l3lLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t+LFlL72JcIHEZRkNIRjT3aQzwUkQfeiHWGgMfpGTxA=; b=MnUTtgZUVJGsyhYSpu0/B85uPVxw6IaAlpRL7cov0nC3dGaKhHcvPrKTIlRCLKbHkLC4I2TQz8UNhhN+VBv2OUX9PkBZcV9ZfS46gjNANKgoqBcakO0cOIWnon0SNh6nT5ZGiaqSHss9CfnHtqdZHuquct0BtQVNLibrynXh2e9o4qhXmUjxrgxSLxfd8fnvTk9I4fzOAmFs739rkwTLCO/458BIzM6ML29hntG10PODBRXlPniX2hkp18agZtTLT6SYPbUT2d1L2E0rompS4SFVWZW7zoZ/jWK/LnFDM/dVJypBMhI3sFjxzNDWP4YoPYpGzkhL1ADCWfFaCjDfyA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t+LFlL72JcIHEZRkNIRjT3aQzwUkQfeiHWGgMfpGTxA=; b=qhVzsTsULf6E5gFwKTqyR6dTl7qC6ayD1OuBtqXanxWgm0aw9o29Q0sRiBsgMt/iuZMZgG+2AATXNRVareG3W9wXA2268Re0wKrPdGG9OBhzLu3Rt5JG8u4Qzh83t3AbJW/cERfD+Tk3bDB3jYDLgSyeTBY2r4KvxFW+UIY93+Q= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1187.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3af::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15; Thu, 17 Jun 2021 16:06:30 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:06:30 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 166/256] cl8k: add rf_boot.c Date: Thu, 17 Jun 2021 16:00:53 +0000 Message-Id: <20210617160223.160998-167-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:35 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7268f07c-aae8-4232-6be9-08d931a9be39 X-MS-TrafficTypeDiagnostic: AM9P192MB1187: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dqVFKQbLcOfT617yw/uW6LOF2N3eIoUYpxz3bx+VUkzMFNrJp+NSz5pwheBMaVkkWBC3RaG1Eq4f+8d6BdaDIzSEVExOEipGxKz7oNtYOOzhuse0Qtfx864UiRWODJ/3jmPH4mV1rny3U3boQ2xKigO6DKBe2WM/5EYflzeOHkTCvuFR1BZ4VB2Z0vb05fv22oVlEhvw+DGQiVw/B850SmNRczNuxtnyVccAoHSZmA9pb+QdkXlplkbBwJuB17V9yamWqD9lyynZMXaC3sfeBWwyiVK3wWfD6u2PeF8ER/7DbDLew8cCldrok/xls4mSp0IatnVrffihmIZhhP9vfC/RrbV0LClwJlZ4x+Q96cxhgAc+D/RS+qHbYPyakQFfUq/2apspC6nWVlddUc9RvygisiuQivIf2NeHhS8wSECDQI7hnUdtNusuRbaU661X2qwuEmYEFjcq5VJc0FIXnSWteNw4BURcQNOVO/xoscLLbkkCrzrv7L0cBpbO+yS6oVuu0RWr+n4YK80D5NwEIQbtQ5o/O/Rr/5UcjY65E7BUSKXeZtSZob6lru3Mjt3Zg7+x0KJc/1GhQ2JZ6K3rQgo/m2kRBSkAXBrqHx6UbKrvWoCnO7u9PmnKK3TO2ajxV2QZzzTOQutSRf7djg5mSMIv1ke+oo6TevJeJ39GddK8f6vBJezo9K2MWuYjd0ZZvkYMRyXfOXbjOpUbH1J1Rw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(39840400004)(376002)(396003)(136003)(366004)(346002)(6512007)(66946007)(55236004)(66556008)(6506007)(54906003)(8676002)(4326008)(186003)(316002)(66476007)(6486002)(26005)(6916009)(86362001)(36756003)(9686003)(30864003)(8936002)(6666004)(5660300002)(2616005)(956004)(2906002)(478600001)(52116002)(83380400001)(38350700002)(16526019)(1076003)(38100700002)(107886003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: p+hq8vmmeVXlH8sghDPRparkVdB8GZXcbnWOz3NPB0GbpzQtrvbuN3XQjHdEYc5OVmplVNa2uQ5oLDPADD3DBTA/nwSJKddFRRzMgt3bN6H7jsf08dOPaHi6KAPrVCQT91Z2DorNc5xJWoeKwSoCUvOiGK0hsIjPc198TIZlqG9oMN189OT4ZqpTpb7Z+mmXDQJWdqxKzlg1/mGhFI5WLtZFvSDLQDQc3RUdM6upeAnpWAJQsK5SwwkVx7tdMvEFAYCF9jDJ5v4dFdsoPB+IISImydq4VCpmAveH4ZqybqAGqC5oRZ04KIv8PpJ1FP7wKmX60C27EtAaG+qGYD40nZm1KOxcXJNgNyafdXaOzxt1pwAbyDkfNnP20mr5Z+zAJO9WmvLasUCOLVH1a9V5qbZ+VGsjOWtTgpsWr2n3EO1I7E6iZv0DHQsSl0Mc9WyLD/91ua9vn6jQi57Zip7Djs5QyCVYwUavbM6Ko/rfnbAhmf/wybS5t2GvNDw4ZuSMW/4RcKmIjAOG7+2h2AfbELsuai0hVvrrGnwfxbDcAr6fK/8/U6yWl0badPMIBqGWCezKsb+rwkNaDBgIjVt9gba6cQ9n5q+3aljGdEc5OeEvmdGr8cA9Tejy30x7Vo03UU0YJsl/YJeaCm37FJJm/PPx9domaTmzXk/O+qMd/NXj6PhciZxUHM/rlTjX0Ox9c/SWXdeUE19GRqkOqbBcvmMtCdSv5aXOvfvGo919mL87op+SLcQ+RKJ9lGjL765rZWNkROmU/XNspFD1qESykQGBCZ4du4HH9lnJxC4mERt33Zb/FAJ2sLfFwmKPA821NbHaTe22PQnCoE7JLqtEj/SCkUnBbPvT17ZCqRnA5cDObzJBr+3//hjY8YjniQRTpbe3r5fmdWbmC8KRzD4RmC6+68u/tWEMfqpc6ZX6oM/+YFFWYM7BSOBVU1tmzJdzOoskuiQh3ZwOPiP4/GBZALwd1Ml6IL1PHifOn/REsZ7sLB1vshXLq+iid/VYexq38AIGIftCkQ98lTsijGuu54hgD9+2QTALJT4Ja49YKcFPR0yOz1KG11utVvB5ujOlFXecocYnpv5Oxv4woE+e6HYtA3Fc3YUHxjoH5Qxm8Uu44WSx9Z9ANxppiA8/nfyCsIhw32a77uU2jbu4rk9Epb5hLC55CoI2MncBUPmXLDZaN64vHyq1pSBuQNL2EV1IGpOqAdo/4P8OM8RAssXA20ZgK94s66oi2mPE2h5jhy3RRA0L7SVS7Cp/z1BWh5xepE/T+PxH8pBVLgufKYel21Ptph5Sf7YZpQk+K4r2jOIHQ2NivwOdC9QxwmmPxci4 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7268f07c-aae8-4232-6be9-08d931a9be39 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:36.1658 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: K6E3nUFF1qxCMzNilP8xKO6XkZQ8RAtYvm5oW7+nSWNNpXF1LkXtmgC6ncyG7r3131eOmFXtiHUQlCz7joeHEw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/rf_boot.c | 354 +++++++++++++++++++++ 1 file changed, 354 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/rf_boot.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/rf_boot.c b/drivers/net/wireless/celeno/cl8k/rf_boot.c new file mode 100644 index 000000000000..4202c153661b --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/rf_boot.c @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "rf_boot.h" +#include "hw.h" +#include "afe.h" +#include "utils/file.h" +#include "phy/phy.h" +#include "reg/reg_access.h" +#include "reg/reg_cmu.h" +#include "reg/reg_modem_gcu.h" +#include "reg/reg_ricu.h" +#include "reg/reg_riu.h" +#include "reg/reg_mac_hw.h" +#include "reg/reg_lcu_phy.h" + +static void cl_clk_init(struct cl_chip *chip) +{ + cmu_clk_en_set(chip, CMU_MAC_ALL_CLK_EN); + + cmu_phy_0_clk_en_set(chip, CMU_PHY_0_APB_CLK_EN_BIT | CMU_PHY_0_MAIN_CLK_EN_BIT); + cmu_phy_1_clk_en_set(chip, CMU_PHY_1_APB_CLK_EN_BIT | CMU_PHY_1_MAIN_CLK_EN_BIT); + + cmu_phy_0_rst_ceva_0_global_rst_n_setf(chip, 0); + modem_gcu_ceva_ctrl_external_wait_setf(chip->cl_hw_tcv0, 1); + cmu_phy_0_rst_ceva_0_global_rst_n_setf(chip, 1); + + cmu_phy_1_rst_ceva_1_global_rst_n_setf(chip, 0); + modem_gcu_ceva_ctrl_external_wait_setf(chip->cl_hw_tcv1, 1); + cmu_phy_1_rst_ceva_1_global_rst_n_setf(chip, 1); + + cmu_phy_0_clk_en_ceva_0_clk_en_setf(chip, 1); + cmu_phy_1_clk_en_ceva_1_clk_en_setf(chip, 1); +} + +static int cl_pll1_init(struct cl_chip *chip) +{ + int retry = 0; + + /* Verify pll is locked */ + while (!cmu_pll_1_stat_pll_lock_getf(chip) && (++retry < 10)) { + cl_dbg_chip_verbose(chip, "retry=%d\n", retry); + usleep_range(100, 200); + } + + /* Pll is not locked - fatal error */ + if (retry == 10) { + cl_dbg_chip_err(chip, "retry limit reached - pll is not locked !!!\n"); + return -1; + } + + return 0; +} + +static int cl_cmu_init(struct cl_chip *chip) +{ + if (cl_pll1_init(chip)) + return -1; + + /* Set gl_mux_sel bit to work with pll1 instead of crystal */ + cmu_control_gl_mux_sel_setf(chip, 1); + + cmu_rst_n_ricurst_setf(chip, 1); + + cmu_phy_0_rst_set(chip, CMU_PHY0_RST_EN); + cmu_phy_1_rst_set(chip, CMU_PHY1_RST_EN); + cmu_phy_0_rst_set(chip, 0x0); + cmu_phy_1_rst_set(chip, 0x0); + cmu_rst_n_ricurst_setf(chip, 1); + cmu_phy_0_rst_set(chip, CMU_PHY0_RST_EN); + cmu_phy_1_rst_set(chip, CMU_PHY1_RST_EN); + + return 0; +} + +static void cl_riu_clk_bw_init(struct cl_hw *cl_hw) +{ + u32 regval; + + switch (cl_hw->conf->ce_channel_bandwidth) { + case CHNL_BW_20: + regval = 0x00000100; + break; + case CHNL_BW_40: + regval = 0x00000555; + break; + case CHNL_BW_160: + regval = 0x00000dff; + break; + case CHNL_BW_80: + default: + regval = 0x000009aa; + break; + } + + /* Set RIU modules clock BW */ + modem_gcu_riu_clk_bw_set(cl_hw, regval); +} + +static int cl_load_riu_rsf_memory(struct cl_chip *chip, const char *filename) +{ + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + char *buf = NULL; + loff_t size, i = 0; + int ret = 0; + + size = cl_file_open_and_read(chip, filename, &buf); + + if (!buf) + return -ENOMEM; + + if (size > RIU_RSF_FILE_SIZE) { + ret = -EFBIG; + goto out; + } + + /* Enable re-sampling filter init. */ + riu_rsf_control_rsf_init_en_setf(cl_hw_tcv0, 0x1); + if (cl_hw_tcv1) + riu_rsf_control_rsf_init_en_setf(cl_hw_tcv1, 0x1); + + while (i < size) { + riu_rsf_init_set(cl_hw_tcv0, *(u32 *)&buf[i]); + if (cl_hw_tcv1) + riu_rsf_init_set(cl_hw_tcv1, *(u32 *)&buf[i]); + i += 4; + } + +out: + kfree(buf); + return ret; +} + +static int cl_load_riu_rsf_memory_recovery(struct cl_hw *cl_hw, const char *filename) +{ + struct cl_chip *chip = cl_hw->chip; + char *buf = NULL; + loff_t size, i = 0; + int ret = 0; + + size = cl_file_open_and_read(chip, filename, &buf); + + if (!buf) + return -ENOMEM; + + if (size > RIU_RSF_FILE_SIZE) { + ret = -EFBIG; + goto out; + } + + /* Enable re-sampling filter init. */ + riu_rsf_control_rsf_init_en_setf(cl_hw, 0x1); + + while (i < size) { + riu_rsf_init_set(cl_hw, *(u32 *)&buf[i]); + i += 4; + } + +out: + kfree(buf); + return ret; +} + +static int cl_load_agc_data(struct cl_hw *cl_hw, const char *filename) +{ + struct cl_chip *chip = cl_hw->chip; + char *buf = NULL; + loff_t size, i = 0; + + size = cl_file_open_and_read(chip, filename, &buf); + + if (!buf) + return -ENOMEM; + + /* Enable AGC FSM ram init state */ + riu_agcfsm_ram_init_1_agc_fsm_ram_init_en_setf(cl_hw, 0x1); + /* Start writing the firmware from WPTR=0 */ + riu_agcfsm_ram_init_1_agc_fsm_ram_init_wptr_setf(cl_hw, 0x0); + /* Allow WPTR register to be writable */ + riu_agcfsm_ram_init_1_agc_fsm_ram_init_wptr_set_setf(cl_hw, 0x1); + /* Enable auto increment WPTR by 1 upon any write */ + riu_agcfsm_ram_init_1_agc_fsm_ram_init_ainc_1_setf(cl_hw, 0x1); + + while (i < size) { + riu_agcfsm_ram_init_2_set(cl_hw, *(u32 *)&buf[i]); + i += 4; + } + + /* Disable AGC FSM ram init state */ + riu_agcfsm_ram_init_1_agc_fsm_ram_init_en_setf(cl_hw, 0x0); + + kfree(buf); + + return 0; +} + +static int cl_load_agc_fw(struct cl_hw *cl_hw, const char *filename) +{ + int ret = 0; + + /* Switch AGC to programming mode */ + + /* Disable RIU Modules clocks (RC,LB,ModemB,FE,ADC,Regs,AGC,Radar) */ + modem_gcu_riu_clk_set(cl_hw, 0); + + /* Switch AGC MEM clock to 480MHz */ + modem_gcu_riu_clk_bw_agc_mem_clk_bw_setf(cl_hw, 3); + + /* Enable RIU Modules clocks (RC,LB,ModemB,FE,ADC,Regs,AGC,Radar) */ + modem_gcu_riu_clk_set(cl_hw, 0xFFFFFFFF); + + /* Assert AGC FSM reset */ + riu_rwnxagccntl_agcfsmreset_setf(cl_hw, 1); + + /* Load AGC RAM data */ + ret = cl_load_agc_data(cl_hw, filename); + if (ret) + goto out; + + /* Switch AGC back to operational mode */ + + /* Disable RIU Modules clocks (RC, LB, ModemB, FE, ADC, Regs, AGC, Radar) */ + modem_gcu_riu_clk_set(cl_hw, 0); + /* Switch AGC MEM clock back to 80M */ + modem_gcu_riu_clk_bw_agc_mem_clk_bw_setf(cl_hw, 1); + /* Enable RIU Modules clocks (RC, LB, ModemB, FE, ADC, Regs, AGC, Radar) */ + modem_gcu_riu_clk_set(cl_hw, 0xFFFFFFFF); + + /* Release AGC FSM reset */ + riu_rwnxagccntl_agcfsmreset_setf(cl_hw, 0); + +out: + return ret; +} + +int cl_rf_boot(struct cl_chip *chip) +{ + int ret = 0; + struct cl_hw *cl_hw_tcv0 = chip->cl_hw_tcv0; + struct cl_hw *cl_hw_tcv1 = chip->cl_hw_tcv1; + + /* Call only once per chip after ASIC reset - configure both phys */ + ret = cl_cmu_init(chip); + if (ret != 0) + goto out; + + cl_clk_init(chip); + cmu_phase_sel_set(chip, (CMU_GP_CLK_PHASE_SEL_BIT | + CMU_DAC_CDB_CLK_PHASE_SEL_BIT | + CMU_DAC_CLK_PHASE_SEL_BIT) & + ~(CMU_ADC_CDB_CLK_PHASE_SEL_BIT | + CMU_ADC_CLK_PHASE_SEL_BIT)); + + mac_hw_mac_cntrl_1_active_clk_gating_setf(cl_hw_tcv0, 1); /* Disable MPIF clock */ + mac_hw_state_cntrl_next_state_setf(cl_hw_tcv0, 2); /* Move to doze */ + + mac_hw_mac_cntrl_1_active_clk_gating_setf(cl_hw_tcv1, 1); /* Disable MPIF clock */ + mac_hw_state_cntrl_next_state_setf(cl_hw_tcv1, 2); /* Move to doze */ + + /* Enable all PHY modules */ + cl_phy_enable(cl_hw_tcv0); + cl_phy_enable(cl_hw_tcv1); + + mac_hw_doze_cntrl_2_wake_up_sw_setf(cl_hw_tcv0, 1); /* Exit from doze */ + mac_hw_state_cntrl_next_state_setf(cl_hw_tcv0, 0); /* Move to idle */ + + mac_hw_doze_cntrl_2_wake_up_sw_setf(cl_hw_tcv1, 1); /* Exit from doze */ + mac_hw_state_cntrl_next_state_setf(cl_hw_tcv1, 0); /* Move to idle */ + + cl_riu_clk_bw_init(cl_hw_tcv0); + cl_riu_clk_bw_init(cl_hw_tcv1); + + /* Load RIU re-sampling filter memory with coefficients */ + ret = cl_load_riu_rsf_memory(chip, "riu_rsf.bin"); + if (ret != 0) { + pr_err("cl_load_riu_rsf_memory failed with error code %d.\n", ret); + goto out; + } + + /* Load AGC FW */ + ret = cl_load_agc_fw(cl_hw_tcv0, "agcram.bin"); + if (ret) { + pr_err("cl_load_agc_fw failed for tcv0 with error code %d.\n", ret); + goto out; + } + + ret = cl_load_agc_fw(cl_hw_tcv1, "agcram.bin"); + if (ret) { + pr_err("cl_load_agc_fw failed for tcv1 with error code %d.\n", ret); + goto out; + } + + /* AFE Registers configuration */ + ret = cl_afe_cfg(chip); + +out: + return ret; +} + +static void restore_ela_state(struct cl_hw *cl_hw) +{ + struct cl_recovery_db *recovery_db = &cl_hw->recovery_db; + + /* Restore eLA state after MAC-HW reset */ + if (recovery_db->ela_en) { + mac_hw_debug_port_sel_a_set(cl_hw, recovery_db->ela_sel_a); + mac_hw_debug_port_sel_b_set(cl_hw, recovery_db->ela_sel_b); + mac_hw_debug_port_sel_c_set(cl_hw, recovery_db->ela_sel_c); + } + + mac_hw_debug_port_en_set(cl_hw, recovery_db->ela_en); +} + +int cl_rf_boot_recovery(struct cl_hw *cl_hw) +{ + int ret = 0; + + mac_hw_mac_cntrl_1_active_clk_gating_setf(cl_hw, 1); /* Disable MPIF clock */ + mac_hw_state_cntrl_next_state_setf(cl_hw, 2); /* Move to doze */ + + /* Enable all PHY modules */ + cl_phy_enable(cl_hw); + + /* Restart LCU recording */ + if (cl_hw_is_tcv0(cl_hw)) + lcu_phy_lcu_ch_0_stop_set(cl_hw, 0); + else + lcu_phy_lcu_ch_1_stop_set(cl_hw, 0); + + restore_ela_state(cl_hw); + + mac_hw_doze_cntrl_2_wake_up_sw_setf(cl_hw, 1); /* Exit from doze */ + mac_hw_state_cntrl_next_state_setf(cl_hw, 0); /* Move to idle */ + + cl_riu_clk_bw_init(cl_hw); + + /* Load RIU re-sampling filter memory with coefficients */ + ret = cl_load_riu_rsf_memory_recovery(cl_hw, "riu_rsf.bin"); + if (ret != 0) { + pr_err("cl_load_riu_rsf_memory failed with error code %d.\n", ret); + goto out; + } + + /* Load AGC FW */ + ret = cl_load_agc_fw(cl_hw, "agcram.bin"); + if (ret) { + pr_err("cl_load_agc_fw failed for with error code %d.\n", ret); + goto out; + } + +out: + return ret; +} From patchwork Thu Jun 17 16:00:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A87EC49EA5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 170/256] cl8k: add rssi.c Date: Thu, 17 Jun 2021 16:00:57 +0000 Message-Id: <20210617160223.160998-171-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:39 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a82241b6-83eb-4063-5b86-08d931a9c0ec X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FcMGIaZhBUw9Eo1KbZZ81IfhYlqnfoQqy3FBrkNhJsJy2R9aqyzdom1YDwd3v/yJW6dA6vGkololw20XeayC8rFJYqxCtmXDxMdkNBJf18lZi6sMrK96kmRIil8wArXAEVFCSgB4b8RIcPj6/RGtr52nbx1Of7MWuWfWkzgGRmXu+LaOIiAFqV/zgaPO5e3UseSqkHLGJkFmKUmH9PBssYmQZ7jwlDXjiJc9hwPaEfhGt2OnK+yasbt62RfEJt17VLi9ew/65XFpE7ySvFiSEgKwXik+0jd7qC+3Ugz+81AZftTbKJ3xUk83IUAchPwUDCzPhmZcEBry1liqLicT7HZi3FDDPsuYINJZ9laS6gZQgi/8DsPBhMgPLj4R82V4xCCqMtK6ijuiPTiArMcUDjkepTVlKpo+usftUB8TsfxeAo8WsqasYfTdLoOdvYCjxLqAmefEl/QeVOp1XJkjI270iT2s0GwWBjKCEqUGhGPbuqohM18cmt3g+gK+p/Akyl1fza0RJGylhREaI87TPts1+EBMkvKiZ2som7+TI8766kIYiiVsFYce0Riqmse8k+d84god2HBx+IDaw8+ApvRcpf6HogNQ7kqDbq5IEAVoL3XznYIm9iTFzjRvfnNSsK6SSBQZ2003DDvFBsGJ9TL4NVbBR+NUEyB8BMqhdVN6IYZs1U2wO/pWcYvtb6F25AFUii01zSWJ1NSDg2pkcA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(376002)(136003)(39850400004)(396003)(508600001)(8936002)(86362001)(107886003)(4326008)(316002)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(30864003)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: URNCl8a3l5XF3M51nI7Bt+ypsIBeUUX3jfpE7nVs9L+vq1ropj8nKiqN6M+w82mHfZj4WhSPkx6/xelQPdsMNTms42jCicbG0mTau+9QJGzIcgQbY1w5+mV5e6IjtbuMnwzfBe7yCQ0RzeoVBETVeIibJvvtknZybwjlha1yvZrNYvMwhDyr7doFfAIx8EzH+woRB0nvQeKPT96Me2HM+FRiriGJODdkKVjB1/2x27HqrNLi55kmnUblkSTiadoGI4CIEV7G+P1rvXq6hMZMcdFKrpqUTbtUKofcax3LdovqJCmpdXNLT0QwBb3MTtis8BipmhPmBX2COWcDORgf+rpmI6pH7NzWl9cry+7TQOu4TEHES7/fm/6OgbFYVRCEV0zZTLMpf0VLcTnGgaQfzeRUBYL+Jt3FdXMVtdMgHV05ZcNcsWDxMNpHZnr/zKVGPk5d+Anl3pOee3a0sI4L61eUYboTAFUGxO0gnjFvcWKb/2f+LeEbVf0X12PDyFr1bys+42N23opmsi8oDxQfJcx+io0BoFqIvy5xX02gqmb5gHKcF/aiQJLo8NOdCLA047mqgIDrOoKAJuAm51/21znAvFGinzijkpJExvNy4sKBOgw9lqDFRkZtDD9LfdrdmiixXq0FqvEGcbVSrNVq89qKkzQrSbKtPKC1jhaycMYIt2idlDiatuwWdtBKeIwCzZnbNE8QPt1rqbMwNOWOcYoVjrEDFgJC1yDNdk1XXVdyKt/kay7Gyo2muU1WB/VRgk5bIlsFJJqVmnP7edJzDZOLZBBUEpdmT2vikcNvYZfubWu5IQ/YU2jtupHOmA4A15EASdgfhUX4PWHovRZ75psgr8zZqiZsnQ7qYMMrghkaMRClrQSgOgACqLSexk2yOWqKdI7fAF6u+80ni3QC82Br6eOboVaT3fGs14+KdUI/6zTwCXYtDJLaXL79SwL5H2ICBUvz/er2X4jb24BEqI0b8W583h9hdgT66kTAQ2j9aYllI05B+iA1f0t7X3VBCWQRvMPSJ/hXCHsk5MbyNYcMGQKXQqlRmNKTiEWQXJ3M80FYrpNHqrxFIOMnC21VzvA1oFPEuMCAIgeUNZSsJmS8G7Bm3x0IbefJyTed6IqqydyogOyKQUHauI+ofNbL7e7V8PZRf6O6lcFb+nZnufA6VLonhGWSGjhFzybWGEJm9j5Cm0gDRsivM1DWHmOiVo7vPuWmRwfEsqw0chxMPK68aofYD4iSxGTxXBfGezxsqG4a0TWp5BHE91hGAyuttcxH7gK31bYxi84iHbh+AepiBU/T7PJ1zcTtzAykuz1Du22armf9ZgSt3AXY6vU5 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: a82241b6-83eb-4063-5b86-08d931a9c0ec X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:40.7307 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GzNK+v5hT1s5tefcWLeAwfD7QoO83WZJ5UXq+muspCoqLKDu362XuSuXpBT/LS3ho5hPeVFlQb/MrP0cEc6UHA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/rssi.c | 320 ++++++++++++++++++++++++ 1 file changed, 320 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/rssi.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/rssi.c b/drivers/net/wireless/celeno/cl8k/rssi.c new file mode 100644 index 000000000000..48221007f424 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/rssi.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "rssi.h" +#include "vns.h" +#include "stats.h" +#include "sta.h" +#include "motion_sense.h" +#include "mac_addr.h" +#include "chip.h" + +/* + * cl_rssi_assoc_###() + * ------------------- + * RSSI values of association packets (request in AP mode and respone in STA mode) + * are not added to rssi pool sample, because at this stage station is not added + * to driver database. + * RSSI of association is important for WRS in order to select its initial rate. + * The goal of this code is to save MAC address and RSSI values of all association + * packets, and after station fully connects, search for the correct RSSI and add + * it to the rssi pool sample. + */ +struct assoc_queue_elem { + struct list_head list; + u8 addr[ETH_ALEN]; + s8 rssi[MAX_ANTENNAS]; + unsigned long timestamp; +}; + +#define CL_RSSI_LIFETIME_MS 5000 + +static void cl_rssi_add_to_wrs(struct cl_hw *cl_hw, struct cl_sta *cl_sta, s8 rssi[MAX_ANTENNAS]) +{ + struct cl_wrs_rssi *wrs_rssi = &cl_sta->wrs_rssi; + int i = 0; + + for (i = 0; i < cl_hw->num_antennas; i++) + wrs_rssi->sum[i] += rssi[i]; + + wrs_rssi->cnt++; +} + +void cl_rssi_assoc_init(struct cl_hw *cl_hw) +{ + INIT_LIST_HEAD(&cl_hw->assoc_queue.list); + spin_lock_init(&cl_hw->assoc_queue.lock); +} + +void cl_rssi_assoc_exit(struct cl_hw *cl_hw) +{ + /* Delete all remaining elements in list */ + spin_lock(&cl_hw->assoc_queue.lock); + + if (!list_empty(&cl_hw->assoc_queue.list)) { + struct assoc_queue_elem *elem = NULL; + struct assoc_queue_elem *tmp = NULL; + + list_for_each_entry_safe(elem, tmp, &cl_hw->assoc_queue.list, list) { + list_del(&elem->list); + kfree(elem); + } + } + + spin_unlock(&cl_hw->assoc_queue.lock); +} + +void cl_rssi_assoc_handle(struct cl_hw *cl_hw, u8 *mac_addr, struct hw_rxhdr *rxhdr) +{ + /* Allocate new element and add to list */ + struct assoc_queue_elem *elem = kmalloc(sizeof(*elem), GFP_ATOMIC); + + if (elem) { + INIT_LIST_HEAD(&elem->list); + cl_mac_addr_copy(elem->addr, mac_addr); + + elem->rssi[0] = (s8)rxhdr->rssi1; + elem->rssi[1] = (s8)rxhdr->rssi2; + elem->rssi[2] = (s8)rxhdr->rssi3; + elem->rssi[3] = (s8)rxhdr->rssi4; + elem->rssi[4] = (s8)rxhdr->rssi5; + elem->rssi[5] = (s8)rxhdr->rssi6; + + elem->timestamp = jiffies; + + spin_lock(&cl_hw->assoc_queue.lock); + list_add(&elem->list, &cl_hw->assoc_queue.list); + spin_unlock(&cl_hw->assoc_queue.lock); + } +} + +void cl_rssi_assoc_find(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u8 num_sta) +{ + /* Search for rssi of association according to mac address */ + spin_lock(&cl_hw->assoc_queue.lock); + + if (!list_empty(&cl_hw->assoc_queue.list)) { + unsigned long lifetime = 0; + struct assoc_queue_elem *elem = NULL; + struct assoc_queue_elem *tmp = NULL; + + list_for_each_entry_safe(elem, tmp, &cl_hw->assoc_queue.list, list) { + lifetime = jiffies_to_msecs(CL_TIME_DIFF(jiffies, elem->timestamp)); + + /* Check lifetime of rssi before using it */ + if (lifetime > CL_RSSI_LIFETIME_MS) { + /* Delete element from list */ + list_del(&elem->list); + kfree(elem); + continue; + } + + if (ether_addr_equal(elem->addr, cl_sta->addr)) { + struct hw_rxhdr rxhdr; + s8 equivalent_rssi = cl_rssi_calc_equivalent(cl_hw, elem->rssi); + + rxhdr.rssi1 = elem->rssi[0]; + rxhdr.rssi2 = elem->rssi[1]; + rxhdr.rssi3 = elem->rssi[2]; + rxhdr.rssi4 = elem->rssi[3]; + rxhdr.rssi5 = elem->rssi[4]; + rxhdr.rssi6 = elem->rssi[5]; + + cl_rssi_rx_handler(cl_hw, cl_sta, &rxhdr, equivalent_rssi); + + /* Delete element from list */ + list_del(&elem->list); + kfree(elem); + } + } + } + + spin_unlock(&cl_hw->assoc_queue.lock); +} + +void cl_rssi_sort_descending(s8 rssi[MAX_ANTENNAS], u8 num_ant) +{ + int i, j; + + for (i = 0; i < num_ant - 1; i++) + for (j = 0; j < num_ant - i - 1; j++) + if (rssi[j] < rssi[j + 1]) + swap(rssi[j], rssi[j + 1]); +} + +static s8 cl_rssi_equivalent_2_phys(s8 rssi_max, s8 rssi_min) +{ + s8 rssi_diff = rssi_min - rssi_max; + + if (rssi_diff > (-2)) + return (rssi_max + 3); + else if (rssi_diff > (-5)) + return (rssi_max + 2); + else if (rssi_diff > (-9)) + return (rssi_max + 1); + else + return rssi_max; +} + +s8 cl_rssi_calc_equivalent(struct cl_hw *cl_hw, s8 rssi[MAX_ANTENNAS]) +{ + s8 rssi_tmp[MAX_ANTENNAS] = {0}; + u8 rx_ant = cl_hw->num_antennas; + int i, j; + + /* Copy to rssi_tmp */ + memcpy(rssi_tmp, rssi, rx_ant); + + /* Sort the rssi's in desceding order */ + cl_rssi_sort_descending(rssi_tmp, rx_ant); + + /* + * 1) Calc equivalent rssi between the two lowest values. + * 2) Sort again + * 3) Repeat steps 1 and 2 according to number of antennas. + */ + for (i = 0; i < rx_ant - 1; i++) { + rssi_tmp[rx_ant - i - 2] = cl_rssi_equivalent_2_phys(rssi_tmp[rx_ant - i - 2], + rssi_tmp[rx_ant - i - 1]); + + for (j = rx_ant - i - 2; j > 0; j--) { + if (rssi_tmp[j] > rssi_tmp[j - 1]) + swap(rssi_tmp[j], rssi_tmp[j - 1]); + else + break; + } + } + + return rssi_tmp[0]; +} + +s8 cl_rssi_get_strongest(struct cl_hw *cl_hw, s8 rssi[MAX_ANTENNAS]) +{ + int i; + s8 strongest_rssi = S8_MIN; + + for (i = 0; i < cl_hw->num_antennas; i++) { + if (rssi[i] > strongest_rssi) + strongest_rssi = rssi[i]; + } + + return strongest_rssi; +} + +static void cl_update_sta_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + s8 rssi[MAX_ANTENNAS], s8 equivalent_rssi) +{ + /* Last RSSI */ + memcpy(cl_sta->last_rssi, rssi, cl_hw->num_antennas); + + if (cl_sta->manual_alpha_rssi) + return; + + /* Alpha RSSI - use alpha filter (87.5% current + 12.5% new) */ + if (cl_sta->alpha_rssi) + cl_sta->alpha_rssi = + ((cl_sta->alpha_rssi << 3) - cl_sta->alpha_rssi + equivalent_rssi) >> 3; + else + cl_sta->alpha_rssi = equivalent_rssi; +} + +void cl_rssi_block_ack_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report) +{ + /* Handle RSSI of block-ack's */ + union cl_rate_ctrl_info *rate_ctrl_info = + (union cl_rate_ctrl_info *)&agg_report->rate_cntrl_info; + u8 bw = (u8)rate_ctrl_info->field.bw; + s8 rssi[MAX_ANTENNAS]; + s8 equivalent_rssi; + int i; + s8 bw_factor = 0; + + /* + * For TCV1 fill in the rxhdr rssi "holes" so that values will start from rssi1. + * The implementation below takes into account elastic mimo, and maximum number + * of antennas for each TCV. + */ + if (cl_chip_is_8ant(cl_hw->chip)) { + rssi[0] = (s8)agg_report->rssi1; + rssi[1] = (s8)agg_report->rssi2; + rssi[2] = (s8)agg_report->rssi3; + rssi[3] = (s8)agg_report->rssi4; + rssi[4] = (s8)agg_report->rssi5; + rssi[5] = (s8)agg_report->rssi6; + } else if (cl_chip_is_6ant(cl_hw->chip)) { + if (cl_hw_is_tcv0(cl_hw)) { + rssi[0] = (s8)agg_report->rssi1; + rssi[1] = (s8)agg_report->rssi2; + rssi[2] = (s8)agg_report->rssi3; + rssi[3] = (s8)agg_report->rssi4; + rssi[4] = (s8)agg_report->rssi5; + } else { + /* Chain 1 is not used */ + rssi[0] = (s8)agg_report->rssi2; + rssi[1] = (s8)agg_report->rssi3; + rssi[2] = (s8)agg_report->rssi4; + rssi[3] = (s8)agg_report->rssi5; + rssi[4] = (s8)agg_report->rssi6; + } + } else { + if (cl_hw_is_tcv0(cl_hw)) { + rssi[0] = (s8)agg_report->rssi1; + rssi[1] = (s8)agg_report->rssi2; + rssi[2] = (s8)agg_report->rssi3; + rssi[3] = (s8)agg_report->rssi4; + } else { + /* Chains 0 & 1 are not used */ + rssi[0] = (s8)agg_report->rssi3; + rssi[1] = (s8)agg_report->rssi4; + rssi[2] = (s8)agg_report->rssi5; + rssi[3] = (s8)agg_report->rssi6; + } + } + + /* + * RSSI adjustment according to BW + * The BA is transmitted in the BW of the aggregation it acknowledges + */ + if (bw == CHNL_BW_160) + bw_factor = 9; + else if (bw == CHNL_BW_80) + bw_factor = 6; + else if (bw == CHNL_BW_40) + bw_factor = 3; + + for (i = 0; i < cl_hw->num_antennas; i++) + rssi[i] += bw_factor; + + equivalent_rssi = cl_rssi_calc_equivalent(cl_hw, rssi); + + /* Handle RSSI after BW adjustment */ + cl_rssi_add_to_wrs(cl_hw, cl_sta, rssi); + cl_stats_update_rx_rssi(cl_hw, cl_sta, rssi); + cl_vns_handle_rssi(cl_hw, cl_sta, rssi); + cl_update_sta_rssi(cl_hw, cl_sta, rssi, equivalent_rssi); + cl_motion_sense_rssi_ba(cl_hw, cl_sta, rssi); +} + +void cl_rssi_rx_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct hw_rxhdr *rxhdr, s8 equivalent_rssi) +{ + /* Called after BW adjustment */ + s8 rssi[MAX_ANTENNAS] = RX_HDR_RSSI(rxhdr); + + cl_rssi_add_to_wrs(cl_hw, cl_sta, rssi); + cl_stats_update_rx_rssi(cl_hw, cl_sta, rssi); + cl_vns_handle_rssi(cl_hw, cl_sta, rssi); + cl_update_sta_rssi(cl_hw, cl_sta, rssi, equivalent_rssi); +} + +void cl_rssi_bw_adjust(struct cl_hw *cl_hw, struct hw_rxhdr *rxhdr, s8 bw_factor) +{ + rxhdr->rssi1 += bw_factor; + rxhdr->rssi2 += bw_factor; + rxhdr->rssi3 += bw_factor; + rxhdr->rssi4 += bw_factor; + rxhdr->rssi5 += bw_factor; + rxhdr->rssi6 += bw_factor; +} + From patchwork Thu Jun 17 16:00:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95EF6C49EA3 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 171/256] cl8k: add rssi.h Date: Thu, 17 Jun 2021 16:00:58 +0000 Message-Id: <20210617160223.160998-172-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:41 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ef7702e1-36be-4ce4-281e-08d931a9c1a6 X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lAO14KX6eSfiOh/dotnF8I/hJYgcUU9W4YWQB4swbGrIMrGEF4wzuaehg1I3YY7OSKyx+UHQ3a+abBiLMz8WPpHB1W+qnU/UotKmqcsLCXpIrv9brQmQCxqF+gNDJQaRywKpKgJlj0rsHpJ09BCbDfaNR83dSB5TKnPdR0/unfvDem+BwJH6YanBVahCYPRStScfIMWj+ZLsDgqV4C8AOQbj9ahM34qiILw5XRG9exXztaVOmBOi+AZu5kV34tTCIvmytLWWh/y5yRCOd8Vy45bMBFdMqvr2x/WvKo5oyyliI9N8/VColb7J7OIW/TuGS21AXk8HHsYkj7ZPvlL17jM4kl4fM2dlaTn3+wR4bgtLYlpcCGIQYzrWonR3p81O3QSgI6sIkjMcHuNKG/b7CFNz9AmyWcHMMA4OfipTfRqGwBOXlcVhLjbjm0lrGvYCAH0/TzrKujnOJFmR8GSFQp4jvy09W46DMXMAwL1vVFwLqIH96/rE/LQfRsL/PjIM1dedCxs/il8tJCJT76z/MVb123lPMr7mXySZs6bXmAHUMMA1ctjwCLNlROnZmEOil0xkzGujePYuAesWQTO8yzgirxAUxFrp7raIWFWTpyH+xD76+YOPuaObtfor14bMm9HUxg3ZXCxPGS+8NL2Db9lNO1j754WYHNDdKOZ5ZT2iH9dBUWXKyiESmBWlcXwU4ePblviZJMq01uMWMtSxfA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(366004)(376002)(136003)(39850400004)(396003)(508600001)(8936002)(86362001)(107886003)(4326008)(316002)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Wulog/QeO/n/QuPhk5BYsZq3Sk0K5nKD1580WXspS+abn1VotGSMAve1fOGzouIs5WNRvdWbYGQmHuFKfOzqiEelJfDGG9vTdlqmhYzreuN/Y8yQJZlU8GnBD7+vfEW+AIFGtNCB+iZS/MjeOJNkVz5fTLAiiktex5fAApb5lUvj7pTARREc/1ClY8K/JcoqOi/l05wXoq5QSrybYLwS1N9i5kb6E53mTyXqD+x/76vh5Db79gsMZaLIv+7JUTTuoVd+pfPPgIueSku4OinR84Ku1fXhzTr500eOAQHE6+7Wqv+N2bJN0JyIZrscf+KTOU26Qd8Be9FIw48UtitJU8jYY0grhHQQsh79b8DjBV+AGj9JcZKs7c2nt+t/Nq6m42Krus6Jp2AAtlFi1NE64+2IoLq+YLNR2v2Q+6eDrmKS/oVSRSCv/55m8yatVq/KNt6q9Oe0BjpkNhzJnYu1b5yBCL0XPPmJNXXCzBpXMLUWUlzQpU2Z0vor7qZuKIjsHL13f1MtAKLnGz2vEVuFFayCCsmiHFFp3o8l6mvaEB/zuiQQ9/J5dsOuI/ZSTUkuw1UDaxXgjupWWlzRz0yygfd/JC0FzQX5X+PYj3dCjWdHFKE7CVrbjfOnq2I0nFlfZRc5nHaP7NvDp7ftRYWvYPudulLnWwnoAGHokoVwyplNHh2Lmvv2muZXMo60PpwJ3PzGLo7a4JlUNFlahlZOe/2t/jnyn875KZs7q9Vuk2Kp0tstntZa+IPJT5443+XnJEQ93N9+NZ9oQ3hYS8QdjDn8lBONvXL6wrHf7hFwZDDbgzStGpRQ2M8Xxl5Gx/ES+XLl4V9YrBMaZP8xiaiZH4Kbq9Cm2srBo1HZ8yPNCYQPYmfkingy1Awh0gjX1Koh6v9oij1qck9C/vgrqkoXBJRFKZu7D1/GUCp+a/bvmZmNN/oSe///O4OamNIcwpyKRSsdNwmBdXvqeL24WkMZ0SgAp4taBXCbJqsYhMoML3GtgfVwGqsEosc2sjumkRpySEEKDG6PSoHMQrF0s9veU2o4GuU4lii9eJARkyGem1C3xmnK2JCZGJKtbJNEN6xjtn0jykpTWNQLtOK7NKUWnALirQXpMZ4ZXchM3JxH+4xnBGV6FEpBJn7e6L2kYS83ZLSflT5J+fAAQHTbMPb4YeTAlA3m0SsSMMbktWHuBwLMuJPYv75JhZVzE61brWCxdiSVGhLeB/kOlwtKeBfIk/VGUet5oAgvutqokaUijWcdY0OCv0eP1gtpovlQaYk40ZT51ONBNiYOg8BQrZBFn1UYhRbGAzpudJBmDFzAiS6o7qpaJT084qH9eIZAGjm7 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef7702e1-36be-4ce4-281e-08d931a9c1a6 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:41.9066 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AOj4D6lQTrYQvpoI5CzBNMleOlMvrIQL+WhHw3ZAFKYj5H5sfAFrLtjPp+2CXHZEZLTvU5eiljpaaFTnaDo9oA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/rssi.h | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/rssi.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/rssi.h b/drivers/net/wireless/celeno/cl8k/rssi.h new file mode 100644 index 000000000000..26ea2b0693a0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/rssi.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_RSSI_H +#define CL_RSSI_H + +#include "rx/rx.h" +#include "hw.h" +#include "tx/agg_tx_report.h" + +#define RX_HDR_RSSI(rxhdr) \ + {(rxhdr)->rssi1, (rxhdr)->rssi2, (rxhdr)->rssi3, \ + (rxhdr)->rssi4, (rxhdr)->rssi5, (rxhdr)->rssi6} + +void cl_rssi_assoc_init(struct cl_hw *cl_hw); +void cl_rssi_assoc_exit(struct cl_hw *cl_hw); +void cl_rssi_assoc_handle(struct cl_hw *cl_hw, u8 *mac_addr, struct hw_rxhdr *rxhdr); +void cl_rssi_assoc_find(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u8 num_sta); +void cl_rssi_sort_descending(s8 rssi[MAX_ANTENNAS], u8 num_ant); +s8 cl_rssi_calc_equivalent(struct cl_hw *cl_hw, s8 rssi[MAX_ANTENNAS]); +s8 cl_rssi_get_strongest(struct cl_hw *cl_hw, s8 rssi[MAX_ANTENNAS]); +void cl_rssi_block_ack_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report); +void cl_rssi_rx_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct hw_rxhdr *rxhdr, s8 equivalent_rssi); +void cl_rssi_bw_adjust(struct cl_hw *cl_hw, struct hw_rxhdr *rxhdr, s8 bw_factor); + +#endif /* CL_RSSI_H */ From patchwork Thu Jun 17 16:01:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C47BBC49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 176/256] cl8k: add rx/rx_filter.c Date: Thu, 17 Jun 2021 16:01:03 +0000 Message-Id: <20210617160223.160998-177-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:47 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1b4b6d36-2a22-4542-e706-08d931a9c55a X-MS-TrafficTypeDiagnostic: AM9P192MB0981: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uydw1jmwtdXRRZ8lgdiCkxq4gif+d/AAwir0IsEMS1AObTCp3tqBnb9FFV/c+u3NnIIQIdlBQZz3yLshCsbEzo2gTsaYnleGd0dH8+PhkDOmOkAZJbLAH4go7Rg8/5JA8Zkna2i1P28Ouk7jMth4jEu09Y2yPbCdpeMj9YmrJU/YMXuh2S3L6+eJrVmBOCEzNI/fUZH5j9PnkpCEDx6CLAhqBIBQuxaSVCz/S3iPq13EgdQe+MsaAkH0n7NonIEWQvKz2ijSajNHUEyniRH5pybBS+i9OH+f7wiEXlwEEz7BD/QunlSze82eFzP0LNLuyTVcc4mDgunA228Yl+vQ3LSEIw1R/x3f0OMu2c0Fb/fy1QuN+SoBXE4z7wUi0kvYi3g6I4bczDl29qquk7iHTZPEP0/0vVCE+mJ4s94oCil830hYXaBrg2KMjtmr/QD46u0J+NbnQFblmNNKpPxG6aQI5ctyrYmKIBV5srY4pFeOxrEHYVDWsWSdpz3+wdTZAqTvD6hd/u8sP9F8z3iZoCn4RJlL54qbuaoBsFAcAVcIz1ESUgP+EyKQeUUMKcT9BMOyKXHpkJKcAU3O+HxrVpOuKzR42nLnUwm2KPJnMUYuMJ3cYeWy2nu5aAWQ35Xq6I5YOHBviCyH8DnUvlOiYvGola2BxhRiRaEPFevG/Xm0k2dKQ4A67/hPnalBs/0dar5qD0Wseh0aKRQRD5AgXQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(376002)(396003)(136003)(366004)(39850400004)(86362001)(5660300002)(9686003)(54906003)(107886003)(6666004)(1076003)(2906002)(478600001)(6512007)(26005)(2616005)(38350700002)(16526019)(55236004)(38100700002)(6506007)(4326008)(8676002)(66946007)(186003)(66476007)(66556008)(956004)(83380400001)(6916009)(8936002)(36756003)(52116002)(6486002)(316002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LSkAwBvg4CfIUGFBJKbHakzllTisroaS8UAzod6obRivkhqtw77VJ9zuXlmLx5y8c1fXBlawGP1mAnorfxEUTb7DHMLKJ+bNVt8Y5FycvmSc1LAgnhI68AZFQdWitFojSvGw7GGsGteNHEqtSoTpblZqRuZNgvvmFm/oaA+vZWYOYJr4cdS+VLezSxeeKo/Asi0VdFfObHyoztJfVGBRDewDU7YKLAsF02xjBQJHwcC6zbMrAvkuHULFiNvRmXIyH03Uf3vdagbKmqAaKfpgNCJqF9dDD7jC1SCfWyoC9ibNBfwJiQ0jozrY3u71GT/I9CMoWPcXiGE5Amhul/9pQLu8G58OfA2kMuO0/hw7G/MMMSKzIsutYv8ptBuWYYMEmG3m+9ib+UAhEqbYPtxI9XvilNdSM4TSg7Qsp37e4GiA0xsRgnX48s3q/ovywpqIA5cdrCWfHuDQt5xw5mhsOHDZYyrLcIbkYlG5N14KpNcE17nY7tjRXKaY8uM4cm2wvPJzV/pdf621fdDh16Bl8ajyzdkYUFWpQROomvgnzVt2LWtrKkHjCyDalhNRLPcb9nD3cR8M3HfDyzXh/TJ8S/5NqG5s9MbtMHRlPtc4171rrxT6Ma7op4GTBmI+gMIFMkcMPFjKSEuLWhYzWg9IwkmfE7sMEM6cuy14fqchkwvnG8NRiJ7ZMae6YLI/GVBTvFV41XnnvmYTzUu2h2cX7+c5GDwxCx1mV17Y396HM9JjGj9TZvm8t3wbC9NAhO9gMYSCQQKLSbgUaVYqvHn5W/fBD8EzGWWWs/EUE2qHVKLgTKCJGYIur9Dyv9h2DCt9Thwx1pUbPOZMyCcYotvTTVrGX4eVY4rsCMUExh+C2kyzUzeOnl+n87nyJubbP8oiIfFq7PTlNYBye+ND8wA6ncnqvsTM5ZrjmNlvhAib9gkHt3lQAlCuu77NuiRV6hiFxnUmhvD3/oN5jhHVXVqO8BLIwFm4EQ7wiGOBvB27b0uo1zjuQaLfrVibYfTWN9NlJhbx6kKE0UMpfBy2JYhXdNYSl/ZOwy5jQ49XSkqKQ+usH6pqmLm6y/qMjZQlWLmy7Yxr1kks4kZhsSRnSbfYmvu2M9mhTmHu8EkuXsKgfMa7QIZjFKNZLUZbOv5jEUdUGL95qxOpImFSxw5nNBRtQFrkEhwxowhtyDKbiMyHMVsvP5lN84gIuYOyZgBTIbPUaR01XBGjHTVbKsOYCi6tYtATSzOfR4h/E2HkXOuAXkN3j2MLyYgQT3xKEQ0koevxXIx0IbSF7s4LygjX+3IXXomPy86PyBZe3cTLFv/l8YLde7qTSfCcWCuYKZOYxqgG X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1b4b6d36-2a22-4542-e706-08d931a9c55a X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:48.1561 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nd1sJ2gNun1oHFQFf4hDKagGPAp4F0DFcibjtvxVQbhzD6mePvTaJWGDKASaMb6xTwzBR1z1PYf+jLR2T6gijA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB0981 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/rx/rx_filter.c | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/rx/rx_filter.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/rx/rx_filter.c b/drivers/net/wireless/celeno/cl8k/rx/rx_filter.c new file mode 100644 index 000000000000..95415ec6aad0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/rx/rx_filter.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "rx/rx_filter.h" +#include "fw/msg_tx.h" +#include "ieee80211_i.h" + +u32 cl_rx_filter_update_flags(struct cl_hw *cl_hw, u32 filter) +{ + u32 rx_filter = 0; + + if (filter & FIF_ALLMULTI) + rx_filter |= RX_CNTRL_ACCEPT_MULTICAST_BIT; + + if (filter & (FIF_FCSFAIL | FIF_PLCPFAIL)) + rx_filter |= RX_CNTRL_ACCEPT_ERROR_FRAMES_BIT; + + if (filter & FIF_BCN_PRBRESP_PROMISC) + rx_filter |= RX_CNTRL_ACCEPT_OTHER_BSSID_BIT; + + if (filter & FIF_CONTROL) + rx_filter |= RX_CNTRL_ACCEPT_OTHER_CNTRL_FRAMES_BIT | + RX_CNTRL_ACCEPT_CF_END_BIT | + RX_CNTRL_ACCEPT_ACK_BIT | + RX_CNTRL_ACCEPT_CTS_BIT | + RX_CNTRL_ACCEPT_RTS_BIT | + RX_CNTRL_ACCEPT_BA_BIT | RX_CNTRL_ACCEPT_BAR_BIT; + + if (filter & FIF_OTHER_BSS) + rx_filter |= RX_CNTRL_ACCEPT_OTHER_BSSID_BIT; + + if (filter & FIF_PSPOLL) + rx_filter |= RX_CNTRL_ACCEPT_PS_POLL_BIT; + + if (filter & FIF_PROBE_REQ) + rx_filter |= RX_CNTRL_ACCEPT_PROBE_REQ_BIT; + + /* Add the filter flags that are set by default and cannot be changed here */ + rx_filter |= CL_MAC80211_NOT_CHANGEABLE; + + if (ieee80211_hw_check(cl_hw->hw, AMPDU_AGGREGATION)) + rx_filter |= RX_CNTRL_ACCEPT_BA_BIT; + + /* + * work around for HW bug (AD 14672) + * In order for the response frames to BAR and RTS be with correct + * power they should always be accepted and found in the KSR + */ + rx_filter |= RX_CNTRL_ACCEPT_BAR_BIT | RX_CNTRL_ACCEPT_RTS_BIT; + + return rx_filter; +} + +static u32 cl_filter_get_flags(struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + + return sdata->local->filter_flags; +} + +void cl_rx_filter_restore_flags(struct cl_hw *cl_hw) +{ + struct net_device *dev = cl_vif_get_first_net_device(cl_hw); + u32 filter = 0; + + if (!dev) + return; + + filter = cl_filter_get_flags(dev); + cl_dbg_verbose(cl_hw, "Restoring filter flags to 0x%x\n", filter); + cl_msg_tx_set_filter(cl_hw, filter, false); +} + +void cl_rx_filter_set_promiscuous_off(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + + cl_rx_filter_restore_flags(cl_hw); +} + +void cl_rx_filter_set_promiscuous(struct cl_hw *cl_hw) +{ + u32 filter = ~(FIF_FCSFAIL | FIF_PLCPFAIL | (1 << 31)); + + cl_dbg_verbose(cl_hw, "set promiscuous mode 0x%x\n", filter); + cl_msg_tx_set_filter(cl_hw, filter, false); +} + From patchwork Thu Jun 17 16:01:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9A72C49EA5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 181/256] cl8k: add sounding.h Date: Thu, 17 Jun 2021 16:01:08 +0000 Message-Id: <20210617160223.160998-182-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:53 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8c5049a6-5275-48e4-6bce-08d931a9c915 X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:238; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6xDdjy97kLgnIH7/RR/m8UFsY4b/ayBXR/6V8JmryO211Pg/1Fbdu+i7bTywx11/aVAIjcE7ONHV4csdjVPWbRm3B4p7DCXA8Q+94Bm1YkEVq06FOGiY6pN5HTZ5/A0aUc8nYyA/GTw5K9QZ1QntdhBSYNe/tLKoLJYZnLWlUQ3JDbuU2tM0KJ08EkVe7moutYVqF/b9ww/aipbvw8Vjj4Vew9aeGeH8P4gmisfiH9GUznySMW1S9sLxlDQNUwNC8LIkB92dYH18CXDla3J6AVWDpjCzbLM7fmQCp5rjocBQqTsR/tYepkxaPIHDLBu8K73FjZ69KIidqJGUB67fGJTF12jSRlnjbt5lWDUTmnlkAUgHZL6f1ZannkvTM1jQe0rIbE9D4yHvU1PonyuoxEy+g6Kxet1ituKEii1kkY7j48kYMuS5WKXKUiJokn7NZvKPYAxWpBTLA9EpqRxPBOy2+x2XuAoy0tR7Yeo+ukeON7hG1vg1Ij285uXgVWeFGFiqK9n9JKaAyzpRA7Deq7fJx++w9wOBlk7NamdXIIdhQR8OjB19R4YpgL7dQgQHEq2tp1fZI73Qe+a6MKVG0XkmpDutlW3HQFqMbxqRfwwjqe91ECsVXQ8HEMmBQcbo4EPzAPOqBzrMJpqGhGHo1K+mb7rzR17JhMY1Oy/5ezHETsx9jW5GcziID9xI96/npnD8xyO7ZH9HBTVpQxUJeA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(8936002)(86362001)(107886003)(4326008)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(498600001)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vfv23rfb8IGlNys2uMYkaN3s/waPe37sjuF8GEQ7h9CEXISLLOqMR26AsNH61s3Aj2OC+HsS2ALMUwnNnkkBaMD1ZRldlXSSpxQNl3+ZGiuR01mAbP+RQT1PSZYIKD7QSqTRksaExFIURTaYLl2DzUreDSd8XyTyqO9lXkwFhZ6C32G36bBbWGKtMESc0j+A7gK+0hSAQlJWdGZcyGXbOdZ55iYm6VdfxdcKG4XLspEQB38epUoCPLKMabswrcndMRC3rQ2HQD5k0o9Idsbvs8IhsHnWtonVnRullqoaq/5WCuloEOwVowwkGNa4vG6OH0Ns5xPFV8FZTLsXCQmEuegvPjpEoH+sONKVQsUm3RaL8mnm8oY2lA5/BEZb9TyLLwfsqMW42uWzaWbTEqe15lJV2ut5xgL5n/uXESIH+y+td2czlZasx2segqVFsRM5wT2k5TWz+oBFWtyWPSSV5xhcdsMPWQclLY9DRYtRxc8hPwg9aKnORq9HmB2YpRsGizLWGgd0DHEP/y1+7l5TJ1b7c9HY8w490NxIGZxQlu1O/865mWZUk3QJo0TSvWkGCvzRhykEFtE3bfN9Kli1slFhrQcjc/h9oRHtp2Prr1VdUmL65lgvfKPpyKuOW6MuWQ6vmk4zNA01Vvz6eVtCQ/xtS8L+T4VoY620BWhM2AnaQo8rDVPUzKIxYy0YPNYxId9LDijn603aSX/PbN2i+qItT5rTkcw3l44qy3R8RT73ZsOoO/vjW/fYLdHDrzSIUCATHjW70cLXAx/+WDNnu9RKtqNhBoWI0UCyWm6SSuD8fFaHiL5aijULWLWTG2sMhVvX8d6G6Bh2T1gjkgA2NqpSibfhzxaA10BK4/vPI/5Iy2XY7KrcEZloM83cDes0fkspfQcQgMJIWO3H9lhmmyk2U2GQT9nnkqwEerSeA4fIUlQxcRe6Ip9TEgpPSRrml7T6ftOZwx6rHZJ4105KJXsk6vZPkx12Og3PJr4w33cmFF7ynfSTCqFp7HkP/EvwQ71J+mjmgXsALSL7ZMP8ThSSzBghk+JNrnyi8w5Hqz9tpyUo6Et0kAt1wC9lIB4SG4OL36Vqaaai8z9EWgUy1EnoOSxfiM/dtUZj32dhuAXA6Dr1UwBjVDEMm/T4ffe4C6Oi8JFjQgChKcBGCpSIk4qCuHk3DCNyT0zyflc9yKB3qHDfy9rqjne5yO1mpGhbja4mn1Bc6+A/1ZvBdahVTrNe7eBxcJmh3nulim8gr5RKDPtCqEgPPeoEclO8OgVHZ53C3+R5M+ull6NdC410X2vt+6Gb5T2Ar9tdgGcVc5cBl3yhZA+1tCIjQVYceSXW X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8c5049a6-5275-48e4-6bce-08d931a9c915 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:54.3907 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /XwgOIz9lwMsiKCVv0Bhg0MTw2U+kJf9aZMpfhVS8OGwZKhs2Be4y7gArPcetyUuGbptktxaHT5eceF7q+6wLw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/sounding.h | 148 ++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/sounding.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/sounding.h b/drivers/net/wireless/celeno/cl8k/sounding.h new file mode 100644 index 000000000000..d5d9d4941b23 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/sounding.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_SOUNDING_H +#define CL_SOUNDING_H + +#include +#include "fw/fw_msg.h" + +#define SOUNDING_ENABLE true +#define SOUNDING_DISABLE false +#define INVALID_SID 0xff +#define XMEM_SIZE (0x180 << 10) /* 384KB */ +#define CL_SOUNDING_STABILITY_TIME 5 +#define CL_SOUNDING_FACTOR 10 + +#define SOUNDING_FEEDBACK_TYPE_SHIFT 2 +#define SOUNDING_FEEDBACK_TYPE_MASK (BIT(SOUNDING_FEEDBACK_TYPE_SHIFT)) +#define SOUNDING_NG_SHIFT 1 +#define SOUNDING_NG_MASK (BIT(SOUNDING_NG_SHIFT)) +#define SOUNDING_MU_CODEBOOK_SIZE_SHIFT 0 +#define SOUNDING_MU_CODEBOOK_SIZE_MASK (BIT(SOUNDING_MU_CODEBOOK_SIZE_SHIFT)) +#define SOUNDING_FEEDBACK_TYPE_VAL(fb_type_ng_cb_size) (((fb_type_ng_cb_size) & \ + SOUNDING_FEEDBACK_TYPE_MASK) >> \ + SOUNDING_FEEDBACK_TYPE_SHIFT) +#define SOUNDING_NG_VAL(fb_type_ng_cb_size) (((fb_type_ng_cb_size) & \ + SOUNDING_NG_MASK) >> SOUNDING_NG_SHIFT) +#define SOUNDING_CODEBOOK_SIZE_VAL(fb_type_ng_cb_size) (((fb_type_ng_cb_size) & \ + SOUNDING_MU_CODEBOOK_SIZE_MASK) >> \ + SOUNDING_MU_CODEBOOK_SIZE_SHIFT) + +#define SOUNDING_TYPE_IS_VHT(type) ((type) == SOUNDING_TYPE_VHT_SU || \ + (type) == SOUNDING_TYPE_VHT_MU) +#define SOUNDING_TYPE_IS_CQI(type) ((type) == SOUNDING_TYPE_HE_CQI || \ + (type) == SOUNDING_TYPE_HE_CQI_TB) + +enum fb_type_ng_cb_size { + FEEDBACK_TYPE_SU_NG_4_CODEBOOK_SIZE_4_2 = 0x0, + FEEDBACK_TYPE_SU_NG_4_CODEBOOK_SIZE_6_4, + FEEDBACK_TYPE_SU_NG_16_CODEBOOK_SIZE_4_2, + FEEDBACK_TYPE_SU_NG_16_CODEBOOK_SIZE_6_4, + FEEDBACK_TYPE_MU_NG_4_CODEBOOK_SIZE_7_5, + FEEDBACK_TYPE_MU_NG_4_CODEBOOK_SIZE_9_7, + FEEDBACK_TYPE_CQI_TB, + FEEDBACK_TYPE_MU_NG_16_CODEBOOK_SIZE_9_7, +}; + +enum cl_sounding_response { + CL_SOUNDING_RSP_OK = 0, + + CL_SOUNDING_RSP_ERR_RLIMIT, + CL_SOUNDING_RSP_ERR_BW, + CL_SOUNDING_RSP_ERR_NSS, + CL_SOUNDING_RSP_ERR_INTERVAL, + CL_SOUNDING_RSP_ERR_ALREADY, + CL_SOUNDING_RSP_ERR_STA, + CL_SOUNDING_RSP_ERR_TYPE, +}; + +enum sounding_type { + SOUNDING_TYPE_HE_SU = 0, + SOUNDING_TYPE_HE_SU_TB, + SOUNDING_TYPE_VHT_SU, + SOUNDING_TYPE_HE_CQI, + SOUNDING_TYPE_HE_CQI_TB, + SOUNDING_TYPE_HE_MU, + SOUNDING_TYPE_VHT_MU, + + SOUNDING_TYPE_MAX +}; + +enum sounding_interval_coef { + SOUNDING_INTERVAL_COEF_MIN_INTERVAL = 0, + SOUNDING_INTERVAL_COEF_STA_STEP, + SOUNDING_INTERVAL_COEF_INTERVAL_STEP, + SOUNDING_INTERVAL_COEF_MAX_INTERVAL, + SOUNDING_INTERVAL_COEF_MAX +}; + +struct cl_hw; + +struct v_matrix_header { + u32 format : 2, + rsv1 : 30; + u32 bw : 2, + nr_index : 3, + nc_index : 3, + rsv2 : 24; + u32 grouping : 4, + rsv3 : 28; + u32 feedback_type : 1, + codebook_info : 3, + rsv4 : 28; + u32 ru_start_idx : 7, + rsv5 : 25; + u32 ru_end_idx : 7, + rsv6 : 25; + u32 padding : 6, + rsv7 : 26; + u32 rsv8; +}; + +struct cl_sounding_info { + enum sounding_type type; + u8 sounding_id; + struct v_matrix_header *v_matrices_data; + u32 v_matrices_data_len; + u32 v_matrices_dma_addr; + u8 gid; + u8 bw; + u8 sta_num; + u8 q_matrix_bitmap; + struct cl_sta *su_cl_sta_arr[CL_MU_MAX_STA_PER_GROUP]; + u32 xmem_space; + bool sounding_restart_required; + struct list_head list; +}; + +struct cl_sounding_db { + struct workqueue_struct *sounding_wq; + u8 num_soundings; + u8 cqi_profiles; /* Num of STAs with CQI active sounding */ + u8 active_profiles; /* Num of STAs with non-CQI active sounding */ + u8 active_profiles_prev[CL_SOUNDING_STABILITY_TIME]; + u8 active_profiles_idx; + u8 dbg_level; + u8 current_interval; + u8 last_conf_active_profiles; + rwlock_t list_lock; + struct list_head head; +}; + +void cl_sounding_init(struct cl_hw *cl_hw); +void cl_sounding_close(struct cl_hw *cl_hw); +void cl_sounding_send_request(struct cl_hw *cl_hw, struct cl_sta **cl_sta_arr, + u8 sta_num, bool enable, u8 sounding_type, u8 bw, + u8 q_matrix_bitmap, struct cl_sounding_info *recovery_elem); +void cl_sounding_switch_profile(struct cl_hw *cl_hw, u8 sta_idx_en, u8 sta_idx_dis); +u8 cl_sounding_get_active_profiles(struct cl_hw *cl_hw); +void cl_sounding_stop_by_sid(struct cl_hw *cl_hw, u8 sid, bool sounding_restart_check); +void cl_sounding_maintenance(struct cl_hw *cl_hw); +u16 cl_sounding_get_interval(struct cl_hw *cl_hw); +void cl_sounding_recovery(struct cl_hw *cl_hw); +struct cl_sounding_info *cl_sounding_get_elem(struct cl_hw *cl_hw, u8 sounding_id); +void cl_sounding_indication(struct cl_hw *cl_hw, struct mm_sounding_ind *ind); +int cl_sounding_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_SOUNDING_H */ From patchwork Thu Jun 17 16:01:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D659EC49361 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 183/256] cl8k: add sta.h Date: Thu, 17 Jun 2021 16:01:10 +0000 Message-Id: <20210617160223.160998-184-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:56 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: da940bb8-7116-49bd-5fa1-08d931a9ca85 X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HJjNRbcdJ+hS8N89w9lV89+14d68hkQeKW/lnoQPXLOUL/Gdjs/T1Uji+tqRG97JemkantHtrtiv57fa3pRZNswZMApuYuZnP5o7HFUdUDFO+IGQjU5gBrMN8Hcmg+SLsM3BPTF4eRB4jhlQm5Lz6RQ/rsceI756epXzhnOZrEywsdpPcCOvNGvJ0M7kjjPsnrU4tYLYey1K5QjEMEuGf8AGe02++f3LyLauNbCl9CkYqSAV5lzK38IXPa8Z0zG/h2W9gKvz7sn2kDvQBGqAmb9o0SGLQCnKOErQGiWIkgyBOpMjlb55SFU+sSK0IfGOmMDNDHiI9mowI7QdY3AMM9ggQsJz5aoD82n/CtV0Pp0/KSJXwrY58pF424Smw4tdPi6yvWOUnORrF8qMhtD8+Aqg0Fj+jpRmfXfbVHX1oykGgaZCsvERz/42Rr1s4JSsi1Knv6RQjI9UrKDwrSWcTrraqp4ypJgrW8PyK79ZH0IUwh5EjOhWIercjJJ3/cJAKnKaVeF59VtMx26YuMfISpyukw6V6/B52PqHUaUOlUdxF2DO4/9V3DF8VlCuz6wmPmZpERhNR/UjL+1Af9YUcU62lfBYZL5Dd7r9+x3cWQQSMhe37LUjMD88e3AMT76+7Nvttio3Fs2qZD8ccZF5LJgdNLc4aEgICdwmY6LtYiZfvgE+3yaUmaSmpls8Z+zEd3Ou5TvYBHtcrfI9nfBhxA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(8936002)(86362001)(107886003)(4326008)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(498600001)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IQJfDEmCtrzJJrFYWaP6p/wKqVugak26SBzI61xaxs1iZs7wjFybHLE19Q9AK0kMynQ83UB4fvzjHF+7b9bc5/sI2d1YY71rsPxSQN92qh8ayDTTcQnsRX4gB+tRoJpOt4X0UnLQl9T8cyU3LM49LI0yzF0QDKUMeTWtdFKd3oBbpKtqF28aRJWP/icoEGKWPGIRJz55d5JTUteUbbYFH6j3+IoB9sbOofSRA+hqCwYUNgQC7Nprp0oZBTnIk9szAC94caHVpAYRTHkjmFFhal2RG1Lejfzh3XHOOiVfblY0hItdqRTrmPbeEaGeb2wtrmxShYhAIIi2wlxo++ywGPiopROra1ML3Psa4IvMXjtFr7K87CXUXtSHgLAQZklAFOf6m4CkVBO5N7sGXvTMlHFQ3b5e+b/ma9UjUuxyOP8FAabqJ31zguuCR6/hckQ6Sml3hWNVBmoP9M9bXB0hVO7Ks+7E5XGVUkOPQIACtHZ6NWIPF1WGPFHchELW/nJGhLRUIIbDPsUoKyTQZe7+mEHCJHawQfcE4EGsSERDM1yQRdqXMODIdpXwPU9d+onyiarc3RTuyfkhrDONkh7/D6/IAy3pfYXLuuzAiO7xIr7b/p/QDC73rVrbluAU+W4UBwSo7+15+a/hG1yINm02FQLrutF6qebgRJLTawufKs40wCXV7kENcsji5CHkuInY97Pva8owkJM6x7RWlTmasCwIaXx2jff9HXFQ/KSnZ4OTcxdd3JeOM54+vOBVqr22+dccX9ZYAhfKpKUdPemhI+NFcDSIjwrmAt19oVjYAuydsKqjfZ03vRLDWHkHg+tkTkxFrylLFafqCtuJkLnxU1oZoRUxPrD+cRRQ5/3zGBvUAPkjMiXjwKU2fzW5Fv3IZs/+b0d9PC6geBSZAU120DskmlBqWYaUwzcZ/BbkiKhjDh2d1F47vgPllanyGIWjNBC9J2IBTNjfC30DQQyWJcIeWItqi9FmpFjCs1OnQ3TVqipTklfTM+FdDI2ol+gioYFNlfdkle6uhNibnXzluGWldYPmwrJXFpqOhx43V3NqhXPC5Qwj1DJ3zEvg3ATgi7qhIsOjGQnkzQLEDI14hU6PpNZs0d/cwSErUHygcK/lwdNwy+K/E8lQwyXEvC1s4jWdFjQgdo0SgdPrdWZx+msXjGrtCTLFfW2f76x3JjTC/Ox+4YAPw4yOShXeCPHoPHtuIiyTOOJGBWbcLDAGLw2TeyCEY1wvH3aWT6HjM2K001SQTCGkF3Lf1Z33NRoQTdLOpykDyygt0JbX+tv7eo7fTCZ4EEBMfDcRYspzcL4nNCA372UOZL/NfrxhXADb X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: da940bb8-7116-49bd-5fa1-08d931a9ca85 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:56.8400 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LMDGXnQh3DSXDmFQG7reDfcLQpKD6Oclzu5JPI5iFle6NSW8+qbmuHwsXe7rXbjxc9YsmDzgXOhjYpZ8iWijdQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/sta.h | 241 +++++++++++++++++++++++++ 1 file changed, 241 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/sta.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/sta.h b/drivers/net/wireless/celeno/cl8k/sta.h new file mode 100644 index 000000000000..8e1e47316cf8 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/sta.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_STA_H +#define CL_STA_H + +#include "sta_info.h" +#include "utils/timer.h" +#include "rate_ctrl.h" +#include "motion_sense.h" + +#define IEEE80211_STA_TO_CL_STA(sta) ((struct cl_sta *)(sta)->drv_priv) +#define STA_INFO_TO_CL_STA(sta_info) ((struct cl_sta *)(sta_info)->sta.drv_priv) + +#define STA_IDX_INVALID U8_MAX + +struct cl_wrs_info { + u64 epr_acc; + u32 tx_success; + u32 tx_fail; + u32 tx_fail_prev; + u32 ba_not_rcv; + u8 ba_not_rcv_consecutive; + u8 ba_not_rcv_consecutive_max; + bool synced; + u32 sync_attempts; + u8 quick_rate_agg_cntr; + u16 quick_rate_pkt_cntr; + bool quick_rate_check; +}; + +struct cl_wrs_rssi { + s32 sum[MAX_ANTENNAS]; + s32 cnt; +}; + +struct cl_amsdu_ctrl { + struct cl_sw_txhdr *sw_txhdr; + u16 rem_len; + u16 max_len; + u16 hdrlen; + u8 packet_cnt; + bool is_sw_amsdu; +}; + +struct cl_bf_sta_db { + bool traffic_active; + bool sounding_start; + bool sounding_remove_required; + bool indication_timeout; + bool synced; + bool is_on; + bool is_on_fallback; + u8 num_ss; + u8 num_ss_fallback; + u8 beamformee_sts; + u8 nc; + u32 sounding_indications; + struct cl_timer timer; +}; + +#define RSSI_ARR_SIZE 128 +#define BF_IDX_MAX 2 + +struct cl_tx_cntrs { + u32 success; + u32 fail; +}; + +struct cl_tx_stats { + struct cl_tx_cntrs he[CHNL_BW_MAX][WRS_SS_MAX][WRS_MCS_MAX][WRS_GI_MAX][BF_IDX_MAX]; + struct cl_tx_cntrs + vht[CHNL_BW_MAX_VHT][WRS_SS_MAX][WRS_MCS_MAX_VHT][WRS_GI_MAX_VHT][BF_IDX_MAX]; + struct cl_tx_cntrs ht[CHNL_BW_MAX_HT][WRS_SS_MAX][WRS_MCS_MAX_HT][WRS_GI_MAX_HT]; + struct cl_tx_cntrs ofdm[WRS_MCS_MAX_OFDM]; + struct cl_tx_cntrs cck[WRS_MCS_MAX_CCK]; + u32 agg_cntr; + u32 fail_cntr; +}; + +enum cl_ps_period { + PS_PERIOD_50MS, + PS_PERIOD_100MS, + PS_PERIOD_250MS, + PS_PERIOD_500MS, + PS_PERIOD_750MS, + PS_PERIOD_1000MS, + PS_PERIOD_2000MS, + PS_PERIOD_5000MS, + PS_PERIOD_10000MS, + PS_PERIOD_ABOVE, + + PS_PERIOD_MAX +}; + +struct cl_ps_stats { + bool is_ps; + unsigned long timestamp_sleep; + u32 period[PS_PERIOD_MAX]; +}; + +enum cl_fec_coding { + CL_FEC_CODING_BCC, + CL_FEC_CODING_LDPC, + CL_FEC_CODING_MAX +}; + +struct cl_stats { + struct cl_tx_stats tx; + struct cl_rx_stats rx; + u32 rssi[RSSI_ARR_SIZE][MAX_ANTENNAS]; + u32 fec_coding[CL_FEC_CODING_MAX]; + struct cl_ps_stats ps; +}; + +/* Per RA/TID Data for AMPDU TX */ +struct cl_baw { + u8 fw_agg_idx; + bool amsdu; + bool action_start; + u16 ssn; + u16 tid_seq; + struct sk_buff_head pending; +}; + +struct cl_vns_sta_db { + bool is_very_near; + bool prev_decision; + s32 rssi_sum[MAX_ANTENNAS]; + s32 rssi_samples; +}; + +struct cl_agc_cd_rssi { + s32 samples; + s32 sum[MAX_ANTENNAS]; + s8 prev; +}; + +struct cl_tid_ampdu_rx { + spinlock_t reorder_lock; + u64 reorder_buf_filtered; + struct sk_buff_head *reorder_buf; + unsigned long *reorder_time; + struct ieee80211_sta *sta; + struct cl_timer reorder_timer; + struct cl_hw *cl_hw; + u16 head_seq_num; + u16 stored_mpdu_num; + u16 ssn; + u16 buf_size; + u16 timeout; + u8 tid; + u8 auto_seq:1, + removed:1, + started:1; +}; + +/* + * Structure used to save information relative to the managed stations. + * Will be used as the 'drv_priv' field of the "struct ieee80211_sta" structure. + */ +struct cl_sta { + struct list_head list; + struct list_head list_hash; + u8 sta_idx; + u8 su_sid; + bool key_disable; + u8 addr[ETH_ALEN]; + struct cl_baw baws[IEEE80211_NUM_TIDS]; + struct cl_amsdu_ctrl amsdu_anchor[IEEE80211_NUM_TIDS]; + struct cl_tx_queue *agg_tx_queues[IEEE80211_NUM_TIDS]; + struct cl_vif *cl_vif; + struct sta_info *stainfo; + struct ieee80211_key_conf *key_conf; + struct cl_bf_sta_db bf_db; + struct cl_stats *stats; + s32 alpha_rssi; + bool manual_alpha_rssi; + s8 last_rssi[MAX_ANTENNAS]; + u8 ampdu_min_spacing; + struct cl_traffic_sta traffic_db[TRAFFIC_DIRECTION_MAX]; + struct cl_vns_sta_db vns_db; + struct cl_agc_cd_rssi agc_cd_rssi; + u32 retry_count; + u32 data_pending[AC_MAX]; + struct cl_wrs_info wrs_info; + struct cl_wrs_rssi wrs_rssi; + bool add_complete; + struct cl_wrs_sta wrs_sta; + struct cl_motion_sense motion_sense; + union cl_rate_ctrl_info_he rate_ctrl_he; + struct cl_tid_ampdu_rx *tid_agg_rx[IEEE80211_NUM_TIDS]; +}; + +typedef void (*sta_callback)(struct cl_hw *, struct cl_sta *); + +void cl_sta_init(struct cl_hw *cl_hw); + +/* These functions take the lock inside */ +u32 cl_sta_num(struct cl_hw *cl_hw); +u32 cl_sta_num_bh(struct cl_hw *cl_hw); +bool cl_sta_is_assoc(struct cl_hw *cl_hw, u8 sta_idx); + +/* Must take lock before calling these functions */ +struct cl_sta *cl_sta_get(struct cl_hw *cl_hw, u8 sta_idx); +struct cl_sta *cl_sta_get_by_addr(struct cl_hw *cl_hw, u8 *addr); + +/* Loop over list of stations and run the callback for each station */ +void cl_sta_loop(struct cl_hw *cl_hw, sta_callback callback); +void cl_sta_loop_bh(struct cl_hw *cl_hw, sta_callback callback); +void cl_sta_loop_safe(struct cl_hw *cl_hw, sta_callback callback); + +void cl_sta_init_stainfo(struct cl_hw *cl_hw, struct sta_info *stainfo); +int cl_sta_add(struct cl_hw *cl_hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta); +void cl_sta_mgd_add(struct cl_hw *cl_hw, struct cl_vif *cl_vif, struct ieee80211_sta *sta); +void cl_sta_remove(struct cl_hw *cl_hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta); +void cl_sta_disassociate_all(struct cl_hw *cl_hw); +void cl_sta_disassociate_ap_iface(struct cl_hw *cl_hw); +void cl_sta_ps_notify(struct cl_hw *cl_hw, struct cl_sta *cl_sta, bool is_ps); + +static inline void cl_sta_lock_bh(struct cl_hw *cl_hw) +{ + read_lock_bh(&cl_hw->cl_sta_db.lock); +} + +static inline void cl_sta_unlock_bh(struct cl_hw *cl_hw) +{ + read_unlock_bh(&cl_hw->cl_sta_db.lock); +} + +static inline void cl_sta_lock(struct cl_hw *cl_hw) +{ + read_lock(&cl_hw->cl_sta_db.lock); +} + +static inline void cl_sta_unlock(struct cl_hw *cl_hw) +{ + read_unlock(&cl_hw->cl_sta_db.lock); +} + +#endif /* CL_STA_H */ From patchwork Thu Jun 17 16:01:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6633C2B9F4 for ; Thu, 17 Jun 2021 16:10:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF12F61426 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 184/256] cl8k: add stats.c Date: Thu, 17 Jun 2021 16:01:11 +0000 Message-Id: <20210617160223.160998-185-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:57 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b0d3d35c-6ed1-45c7-fe07-08d931a9cb28 X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FvH3CYKLen7bL6xhpwO99QOns/6stZvRleLapd6n+nGqxHjrwMaKTLfSOjpGDO4KmbYnebB2caBKMD6UnkHL3VM8xdseYWmTsSd39qIdz63EIwSmxVVR2rOBEeah3uYEn303tCVFkUVZ4GfPI46ee6dVKCWqyfdZW1reolW5Hsq6zuy7H18PyHG+pXgXi/g5kAd2Eglg3FKoyCj1RTiGrIbMHnIYgkekRgcO0uZeuag3c2eoXGoNxJiwau38dTro/3ZCiYWsQ9gWG8OnkdxDhqvoLZdm05/OATW/j4qs9I5IDt+JlIKSQD6CrqylfbxiqdyJEea0aCbJDsjLRy0XNQXL6j1pNtoswNOSiKdAEXIxbfpPpFm4h3loDzRhOQMpo11gGfCCpUkIrqTAKIIeSoqca1CpoWC8Cq9/MNMeqZUHm2kgCUm31uhfcaSFbI6aicL1S3AOX5bDzTIz/Gxb/8zPwFsuAFWTBqCwYhuyzMsVD5+qceLofztJnil2fpQgrGEB6FnNCNZLeN57W/BNyJvXxVokcAbO+J2Wbg2BR41e6KCvDc8vOXbfDl6Z0NkXFTeDrR8SgPh0SWOiINGRDNByhHAzSbFU6fgEOsaDJfwJpfUJJP/nC+gvow+js5MruT905VGR76UKSt4IT5XOUXPWYGJwl6YD4SopePz744PzYTZP7Lf4Gxtm+h0N2yy+yrpTaMwEYh7LF/DsgfxsPA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(8936002)(86362001)(107886003)(4326008)(26005)(8676002)(956004)(45080400002)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(498600001)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(30864003)(6506007)(36756003)(1076003)(69590400013)(32563001)(579004)(559001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GU0hAL4BjVMp2Zye58Y7Ind17oyEhVsRfPpPwFQfXO/8BjvxBFv8Aj4beZHDpAvzFbPM/8g9EsaBBxGh8BFMbttgzjNmOEi657ezvFvYJo+IYPtwEpNadv82W+xGkeEW42YC7eAG2Lgu4d+0v8R7blApjAXwmEfYer9xchJF+So2s0p4VTEaHRAEcBuWz1TwxE2ROQrV5bm1G9LCPlsueDhVfXIUtTbsdBhP3V+ePiqRfjA/QSDGu6P04d02fOUnby+yYXpxDhLHM92f/9bCR4Umz0fJZgBPm+FzpK+iRW4pB6ZZI8GkV/8+q01gajvf0w87GSBquuSPFmxB3P3iTrVTRtpRxXyZkKBIj/Wz/jwJ7aLXPSTnAA7pftW0WBN3M8fmuWu6l+pSJkf+D/PVzKYSU9S30Szj+wspG6IF9xJrNuk0osAa4Vfas8Vgx2+Bb88xx8pi4jPICz5+vk+7tPXHwZx4SnnxP7+wdOguibanw/CAia9IrND8IyTjJ0k8zkMo8HSU7rqpIpClvmzvqj46KZxRPXodkLY+R7T8juLoXe/RQOwFX7kDsfUGw7apsdGjHTp31heJZF395CwjVh3qxPJiZnxg5bHH20pfG7JsoUicojUBVq0tcwehOXfkl5njhLQ/9opg2at7DSIGv9XWl87nXnZDsJWC177RN76PBxAtYU2nqRjy9j5cfCHS0rdQjxehauRu3sY5H4ZskSqFY00saD3EKjWGZvzVVBSp7mdRktUztuNb9d/D82c+P2SLs+6oGw60/UNotiwVjfpekm0Xs1TX1W98wWZ5/Cmp/OEF42iYFK1/ZVkFIC8Jq+2X1d4HB2TjQJvo531U6xcmlJWqR3CkuryAuFaYQ+6y9A1E4X7zA8QOzAK3PKTCMFze1i2SVbSdx12GmfW97Mw6p6VCtS3PZFuDi6SRTzOElBIoFeGhB14XPgNwviADAypz31pTjs5O2mDvkZDPcPStw4SdL/Q6IftMipGQTyRFhviaLjrOQLQbBnplJN+nf0vK2i4wuf1M89gq06oi4X58RL4XBZIdFV/OD7qlO75LfgJjIrpsqAHJGBfxpOPZRpGPevpOqK+UjmcncnWafDiPnGmQi1mA6R8HmaTFWOAjM6e8gYfUe15p95QpIcT+8bIcz0Njz/uc160yGkN25qR+IEwifpO29lXwOXdmWhl4+xuzj+T/ec+XmQs1C2MEfC9D9f4pHqq9B6xhqCyT91DzpLCAjx55Jb9FrjV3xTVwL5EWzt46AoX4HGYf/cYYb/XZLkrF/rS9nNa9VcDXe8+Su9JKSP/5H3AqGn2jRHaHmIqgxid1qogEXpYTCTso X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: b0d3d35c-6ed1-45c7-fe07-08d931a9cb28 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:58.0666 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: p+dLlNyc7sxFriRht+g8CCHIb59wU7IULwkGtrMhAe7BrSk2Fr81EEtKjCyzxhq60HGA1pT8xljYq08S2LxKbA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/stats.c | 1402 ++++++++++++++++++++++ 1 file changed, 1402 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/stats.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/stats.c b/drivers/net/wireless/celeno/cl8k/stats.c new file mode 100644 index 000000000000..f340f60ebab9 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/stats.c @@ -0,0 +1,1402 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "stats.h" +#include "rx/rx.h" +#include "reg/reg_access.h" +#include "sta.h" +#include "band.h" +#include "mib.h" +#include "rate_ctrl.h" +#include "vif.h" +#include "data_rates.h" + +typedef void (*stats_callback)(struct cl_hw *, struct cl_sta *); + +static const char *bw_str[CHNL_BW_MAX_OFDMA] = { + [CHNL_BW_2_5] = "2.5", + [CHNL_BW_5] = "5", + [CHNL_BW_10] = "10", + [CHNL_BW_20] = "20", + [CHNL_BW_40] = "40", + [CHNL_BW_80] = "80", + [CHNL_BW_160] = "160" +}; + +static const char *gi_he_str[WRS_GI_MAX_HE] = { + [WRS_GI_LONG] = "3.2", + [WRS_GI_SHORT] = "1.6", + [WRS_GI_VSHORT] = "0.8" +}; + +static const char *gi_ht_vht_str[WRS_GI_MAX_HT] = { + [WRS_GI_LONG] = "0.8", + [WRS_GI_SHORT] = "0.4", +}; + +static void cl_stats_sta_reset(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + struct cl_ps_stats *ps = &cl_sta->stats->ps; + bool is_ps = ps->is_ps; + unsigned long timestamp_sleep = ps->timestamp_sleep; + + memset(cl_sta->stats, 0, sizeof(struct cl_stats)); + + /* Restore value of power-save state and timestamp */ + ps->is_ps = is_ps; + ps->timestamp_sleep = timestamp_sleep; +} + +static void cl_stats_print_per(struct cl_hw *cl_hw, u32 delay) +{ + u32 system_per = 0, air_per = 0, ampdu_all, + old_phy_error, old_fcs_error, old_overflow, old_complete, + old_ampdu_failed, old_real_fcs, old_ampdu_success, + new_phy_error, new_fcs_error, new_overflow, new_complete, + new_ampdu_failed, new_real_fcs, new_ampdu_success; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + + old_phy_error = cl_mib_cntr_read(cl_hw, MIB_DOT11_RX_PHY_ERROR_COUNT); + old_fcs_error = cl_mib_cntr_read(cl_hw, MIB_DOT11_FCS_ERROR_COUNT); + old_overflow = cl_mib_cntr_read(cl_hw, MIB_DOT11_RX_FIFO_OVERFLOW_COUNT); + old_complete = cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT0) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT1) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT2) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT3) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT4) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT5) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT6) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT7); + old_ampdu_failed = cl_mib_cntr_read(cl_hw, MIB_AMPDU_INCORRECT_RCVED_COUNT); + old_ampdu_success = cl_mib_cntr_read(cl_hw, MIB_RW_U_AMPDU_RECEIVED_COUNT); + old_real_fcs = old_fcs_error - old_overflow; + + mdelay(delay); + + new_phy_error = cl_mib_cntr_read(cl_hw, MIB_DOT11_RX_PHY_ERROR_COUNT); + new_fcs_error = cl_mib_cntr_read(cl_hw, MIB_DOT11_FCS_ERROR_COUNT); + new_overflow = cl_mib_cntr_read(cl_hw, MIB_DOT11_RX_FIFO_OVERFLOW_COUNT); + new_complete = cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT0) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT1) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT2) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT3) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT4) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT5) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT6) + + cl_mib_cntr_read(cl_hw, MIB_RW_QOS_U_RECEIVED_MPDU_COUNT7); + new_ampdu_failed = cl_mib_cntr_read(cl_hw, MIB_AMPDU_INCORRECT_RCVED_COUNT); + new_ampdu_success = cl_mib_cntr_read(cl_hw, MIB_RW_U_AMPDU_RECEIVED_COUNT); + new_real_fcs = new_fcs_error - new_overflow; + + /* Overflow handling */ + if (old_complete > new_complete || + old_overflow > new_overflow || + old_fcs_error > new_fcs_error || + old_phy_error > new_phy_error || + old_ampdu_failed > new_ampdu_failed) + return; + + ampdu_all = (new_ampdu_failed - old_ampdu_failed) + + (new_ampdu_success - old_ampdu_success); + + if (new_complete - old_complete) { + system_per = ((new_overflow - old_overflow) * 100 / + (new_complete - old_complete)); + } else { + cl_snprintf(&buf, &len, &buf_size, "No successfully received packets\n"); + goto out; + } + + if ((new_fcs_error + new_phy_error + new_complete) - + (old_fcs_error + old_phy_error + old_complete)) + air_per = (new_real_fcs - old_real_fcs) * 100 / + ((new_real_fcs + new_complete) - (old_real_fcs + old_complete)); + + cl_snprintf(&buf, &len, &buf_size, + "Air PER = [%u%%]\n" + "System PER = [%u%%]\n" + "Successfully received packets = [%u]\n" + "Number of phy errors received: [%u]\n" + "Aggregation failure ratio: [%u/%u]\n", + air_per, system_per, new_complete - old_complete, + new_phy_error - old_phy_error, + new_ampdu_failed - old_ampdu_failed, ampdu_all); + +out: + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void cl_stats_print_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + struct cl_stats *stats = cl_sta->stats; + u32 i = 0, j = 0; + u64 avg_rssi[MAX_ANTENNAS] = {0}; + u64 sum_rssi[MAX_ANTENNAS] = {0}; + u64 total_rssi = 0; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "STA #%u, MAC %pM\n", cl_sta->sta_idx, cl_sta->addr); + + cl_snprintf(&buf, &len, &buf_size, "|----"); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "-----------"); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + cl_snprintf(&buf, &len, &buf_size, "|RSSI"); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "| Ant%u ", j + 1); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + cl_snprintf(&buf, &len, &buf_size, "|----"); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "+----------"); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + for (i = 0; i < RSSI_ARR_SIZE; i++) { + total_rssi = 0; + + for (j = 0; j < cl_hw->num_antennas; j++) { + total_rssi += stats->rssi[i][j]; + sum_rssi[j] += stats->rssi[i][j]; + avg_rssi[j] += (i * stats->rssi[i][j]); + } + + /* Does not print rssi entries with 0 packets */ + if (total_rssi == 0) + continue; + + cl_snprintf(&buf, &len, &buf_size, "|%3d ", -i); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, + "|%10u", stats->rssi[i][j]); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + } + + total_rssi = 0; + + for (j = 0; j < cl_hw->num_antennas; j++) { + if (sum_rssi[j] == 0) + goto out; + + avg_rssi[j] = div64_u64(avg_rssi[j], sum_rssi[j]); + } + + cl_snprintf(&buf, &len, &buf_size, "|----"); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "+----------"); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + cl_snprintf(&buf, &len, &buf_size, "|AVG "); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "|%10lld", -avg_rssi[j]); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + + cl_snprintf(&buf, &len, &buf_size, "|----"); + for (j = 0; j < cl_hw->num_antennas; j++) + cl_snprintf(&buf, &len, &buf_size, "-----------"); + cl_snprintf(&buf, &len, &buf_size, "|\n"); + +out: + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void cl_stats_print_fec_coding(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + struct cl_stats *stats = cl_sta->stats; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "\nSTA #%u, MAC %pM\n", cl_sta->sta_idx, cl_sta->addr); + cl_snprintf(&buf, &len, &buf_size, + "BCC = %u\n", stats->fec_coding[CL_FEC_CODING_BCC]); + cl_snprintf(&buf, &len, &buf_size, + "LDPC = %u\n", stats->fec_coding[CL_FEC_CODING_LDPC]); + + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void cl_stats_print_power_save(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + struct cl_ps_stats *ps_stats = &cl_sta->stats->ps; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "\n"); + cl_snprintf(&buf, &len, &buf_size, + "STA #%u, MAC %pM\n", cl_sta->sta_idx, cl_sta->addr); + cl_snprintf(&buf, &len, &buf_size, + "Current state = %s\n", ps_stats->is_ps ? "SLEEP" : "AWAKE"); + cl_snprintf(&buf, &len, &buf_size, + "|-------------------------|\n"); + cl_snprintf(&buf, &len, &buf_size, + "| Period | Counter |\n"); + cl_snprintf(&buf, &len, &buf_size, + "|-------------------------|\n"); + cl_snprintf(&buf, &len, &buf_size, + "| <= 50ms | %10u |\n", ps_stats->period[PS_PERIOD_50MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 100ms | %10u |\n", ps_stats->period[PS_PERIOD_100MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 250ms | %10u |\n", ps_stats->period[PS_PERIOD_250MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 500ms | %10u |\n", ps_stats->period[PS_PERIOD_500MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 750ms | %10u |\n", ps_stats->period[PS_PERIOD_750MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 1000ms | %10u |\n", ps_stats->period[PS_PERIOD_1000MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 2000ms | %10u |\n", ps_stats->period[PS_PERIOD_2000MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 5000ms | %10u |\n", ps_stats->period[PS_PERIOD_5000MS]); + cl_snprintf(&buf, &len, &buf_size, + "| <= 10000ms | %10u |\n", ps_stats->period[PS_PERIOD_10000MS]); + cl_snprintf(&buf, &len, &buf_size, + "| > 10000ms | %10u |\n", ps_stats->period[PS_PERIOD_ABOVE]); + cl_snprintf(&buf, &len, &buf_size, + "|-------------------------|\n"); + + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void _cl_stats_print_tx(char **buf, int *len, ssize_t *buf_size, + struct cl_tx_cntrs *cntrs, + const char *mode_str, const char *bw_str, const char *gi_str, + u8 nss, u8 mcs, u8 bf, + u64 *total_success, u64 *total_fail) +{ + u8 per = 0; + + if (cntrs->fail == 0 && cntrs->success == 0) + return; + + per = (u8)div64_u64(100 * (u64)cntrs->fail, cntrs->fail + cntrs->success); + + cl_snprintf(buf, len, buf_size, + "|%-8s|%-3s|%2u|%3u|%3s|%2u|%10u|%10u|%3u|\n", + mode_str, bw_str, nss, mcs, gi_str, bf, cntrs->success, cntrs->fail, per); + + *total_success += cntrs->success; + *total_fail += cntrs->fail; +} + +static void cl_stats_print_tx_he(char **buf, int *len, ssize_t *buf_size, + struct cl_stats *stats, u64 *total_success, u64 *total_fail) +{ + struct cl_tx_cntrs *cntrs; + u8 bw = 0, nss = 0, mcs = 0, gi = 0, bf = 0; + + for (bw = 0; bw < CHNL_BW_MAX; bw++) + for (nss = 0; nss < WRS_SS_MAX; nss++) + for (mcs = 0; mcs < WRS_MCS_MAX; mcs++) + for (gi = 0; gi < WRS_GI_MAX; gi++) + for (bf = 0; bf < BF_IDX_MAX; bf++) { + cntrs = &stats->tx.he[bw][nss][mcs][gi][bf]; + _cl_stats_print_tx(buf, len, buf_size, + cntrs, + "HE", + bw_str[bw], gi_he_str[gi], + nss, mcs, bf, + total_success, total_fail); + } +} + +static void cl_stats_print_tx_vht(char **buf, int *len, ssize_t *buf_size, + struct cl_stats *stats, u64 *total_success, u64 *total_fail) +{ + struct cl_tx_cntrs *cntrs; + u8 bw = 0, nss = 0, mcs = 0, gi = 0, bf = 0; + + for (bw = 0; bw < CHNL_BW_MAX_VHT; bw++) + for (nss = 0; nss < WRS_SS_MAX; nss++) + for (mcs = 0; mcs < WRS_MCS_MAX_VHT; mcs++) + for (gi = 0; gi < WRS_GI_MAX_VHT; gi++) + for (bf = 0; bf < BF_IDX_MAX; bf++) { + cntrs = &stats->tx.vht[bw][nss][mcs][gi][bf]; + _cl_stats_print_tx(buf, len, buf_size, + cntrs, + "VHT", + bw_str[bw], gi_ht_vht_str[gi], + nss, mcs, bf, + total_success, total_fail); + } +} + +static void cl_stats_print_tx_ht(char **buf, int *len, ssize_t *buf_size, + struct cl_stats *stats, u64 *total_success, u64 *total_fail) +{ + struct cl_tx_cntrs *cntrs; + u8 bw = 0, nss = 0, mcs = 0, gi = 0; + + for (bw = 0; bw < CHNL_BW_MAX_HT; bw++) + for (nss = 0; nss < WRS_SS_MAX; nss++) + for (mcs = 0; mcs < WRS_MCS_MAX_HT; mcs++) + for (gi = 0; gi < WRS_GI_MAX_HT; gi++) { + cntrs = &stats->tx.ht[bw][nss][mcs][gi]; + _cl_stats_print_tx(buf, len, buf_size, + cntrs, + "HT", + bw_str[bw], gi_ht_vht_str[gi], + nss, mcs, 0, + total_success, total_fail); + } +} + +static void cl_stats_print_tx_ofdm(char **buf, int *len, ssize_t *buf_size, + struct cl_stats *stats, u64 *total_success, u64 *total_fail) +{ + struct cl_tx_cntrs *cntrs; + u8 mcs; + + for (mcs = 0; mcs < WRS_MCS_MAX_OFDM; mcs++) { + cntrs = &stats->tx.ofdm[mcs]; + _cl_stats_print_tx(buf, len, buf_size, + cntrs, + "OFDM", bw_str[0], "0", + 0, mcs, 0, + total_success, total_fail); + } +} + +static void cl_stats_print_tx_cck(char **buf, int *len, ssize_t *buf_size, + struct cl_stats *stats, u64 *total_success, u64 *total_fail) +{ + struct cl_tx_cntrs *cntrs; + u8 mcs; + + for (mcs = 0; mcs < WRS_MCS_MAX_CCK; mcs++) { + cntrs = &stats->tx.cck[mcs]; + _cl_stats_print_tx(buf, len, buf_size, + cntrs, + "CCK", bw_str[0], "0", + 0, mcs, 0, + total_success, total_fail); + } +} + +static void cl_stats_print_tx(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + struct cl_stats *stats = cl_sta->stats; + u64 total_success = 0, total_fail = 0; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "\nSTA #%u, MAC %pM\n", cl_sta->sta_idx, cl_sta->addr); + cl_snprintf(&buf, &len, &buf_size, + "------------------------------------------------------\n"); + cl_snprintf(&buf, &len, &buf_size, + "|MODE |BW |SS|MCS|GI |BF| Success | Fail |PER|\n"); + cl_snprintf(&buf, &len, &buf_size, + "|--------+---+--+---+---+--+----------+----------+---|\n"); + + cl_stats_print_tx_he(&buf, &len, &buf_size, stats, &total_success, &total_fail); + cl_stats_print_tx_vht(&buf, &len, &buf_size, stats, &total_success, &total_fail); + cl_stats_print_tx_ht(&buf, &len, &buf_size, stats, &total_success, &total_fail); + cl_stats_print_tx_ofdm(&buf, &len, &buf_size, stats, &total_success, &total_fail); + cl_stats_print_tx_cck(&buf, &len, &buf_size, stats, &total_success, &total_fail); + + cl_snprintf(&buf, &len, &buf_size, + "------------------------------------------------------\n"); + cl_snprintf(&buf, &len, &buf_size, + " |%10llu|%10llu|\n", total_success, total_fail); + cl_snprintf(&buf, &len, &buf_size, + " -----------------------\n"); + cl_snprintf(&buf, &len, &buf_size, + "\n"); + + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void _cl_stats_print_rx(struct cl_hw *cl_hw, struct cl_rx_stats *rx_stats, + struct cl_sta *cl_sta) +{ + u8 mode = 0, mcs = 0, nss = 0, bw = 0, gi = 0, flag = rx_stats->flag; + u16 data_rate = 0, data_rate_div_10 = 0, data_rate_mod_10 = 0; + u64 remainder = 0, packets = 0, total_packets[WRS_MODE_MAX] = {0}, + total_data_rate[WRS_MODE_MAX] = {0}, equivalent_data_rate = 0; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + + if (cl_sta) + cl_snprintf(&buf, &len, &buf_size, + "\nSTA #%u, MAC %pM\n", + cl_sta->sta_idx, cl_sta->addr); + + cl_snprintf(&buf, &len, &buf_size, + "-------------------------------------------------------\n"); + cl_snprintf(&buf, &len, &buf_size, + "| MODE | BW | SS | MCS | GI | Data-Rate | #Packets |\n"); + cl_snprintf(&buf, &len, &buf_size, + "|---------+----+----+-----+----+-----------+----------|\n"); + + if ((flag & RX_STATS_HE_TRIG) == 0) + goto stats_he_ext; + + for (bw = 0; bw < CHNL_BW_MAX_HE; bw++) { + for (nss = 0; nss < WRS_SS_MAX; nss++) { + for (mcs = 0; mcs < WRS_MCS_MAX_HE; mcs++) { + for (gi = 0; gi < WRS_GI_MAX_HE; gi++) { + packets = rx_stats->he_trig[bw][nss][mcs][gi]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_HE, bw, + nss, mcs, gi); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_HE] += packets; + total_data_rate[WRS_MODE_HE] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| HE_TRIG |%4u|%4u|%5u|%4s| %7u.%u |%10llu|\n", + BW_TO_MHZ(bw), nss, mcs, gi_he_str[gi], + data_rate_div_10, data_rate_mod_10, packets); + } + } + } + } + +stats_he_ext: + if ((flag & RX_STATS_HE_EXT) == 0) + goto stats_he_mu; + + for (bw = 0; bw < CHNL_BW_MAX_HE; bw++) { + for (nss = 0; nss < WRS_SS_MAX; nss++) { + for (mcs = 0; mcs < WRS_MCS_MAX_HE; mcs++) { + for (gi = 0; gi < WRS_GI_MAX_HE; gi++) { + packets = rx_stats->he_ext[bw][nss][mcs][gi]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_HE, bw, + nss, mcs, gi); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_HE] += packets; + total_data_rate[WRS_MODE_HE] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| HE_EXT |%4u|%4u|%5u|%4s| %7u.%u |%10llu|\n", + BW_TO_MHZ(bw), nss, mcs, gi_he_str[gi], + data_rate_div_10, data_rate_mod_10, packets); + } + } + } + } + +stats_he_mu: + if ((flag & RX_STATS_HE_MU) == 0) + goto stats_he_su; + + for (bw = 0; bw < CHNL_BW_MAX_HE; bw++) { + for (nss = 0; nss < WRS_SS_MAX; nss++) { + for (mcs = 0; mcs < WRS_MCS_MAX_HE; mcs++) { + for (gi = 0; gi < WRS_GI_MAX_HE; gi++) { + packets = rx_stats->he_mu[bw][nss][mcs][gi]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_HE, bw, + nss, mcs, gi); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_HE] += packets; + total_data_rate[WRS_MODE_HE] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| HE_MU |%4u|%4u|%5u|%4s| %7u.%u |%10llu|\n", + BW_TO_MHZ(bw), nss, mcs, gi_he_str[gi], + data_rate_div_10, data_rate_mod_10, packets); + } + } + } + } + +stats_he_su: + if ((flag & RX_STATS_HE_SU) == 0) + goto stats_vht; + + for (bw = 0; bw < CHNL_BW_MAX_HE; bw++) { + for (nss = 0; nss < WRS_SS_MAX; nss++) { + for (mcs = 0; mcs < WRS_MCS_MAX_HE; mcs++) { + for (gi = 0; gi < WRS_GI_MAX_HE; gi++) { + packets = rx_stats->he_su[bw][nss][mcs][gi]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_HE, bw, + nss, mcs, gi); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_HE] += packets; + total_data_rate[WRS_MODE_HE] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| HE_SU |%4u|%4u|%5u|%4s| %7u.%u |%10llu|\n", + BW_TO_MHZ(bw), nss, mcs, gi_he_str[gi], + data_rate_div_10, data_rate_mod_10, packets); + } + } + } + } + +stats_vht: + if ((flag & RX_STATS_VHT) == 0) + goto stats_ht; + + for (bw = 0; bw < CHNL_BW_MAX_VHT; bw++) { + for (nss = 0; nss < WRS_SS_MAX; nss++) { + for (mcs = 0; mcs < WRS_MCS_MAX_VHT; mcs++) { + for (gi = 0; gi < WRS_GI_MAX_VHT; gi++) { + packets = rx_stats->vht[bw][nss][mcs][gi]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_VHT, + bw, nss, mcs, gi); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_VHT] += packets; + total_data_rate[WRS_MODE_VHT] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| VHT |%4u|%4u|%5u|%4s| %7u.%u |%10llu|\n", + BW_TO_MHZ(bw), nss, mcs, gi_ht_vht_str[gi], + data_rate_div_10, data_rate_mod_10, packets); + } + } + } + } + +stats_ht: + if ((flag & RX_STATS_HT) == 0) + goto stats_ofdm; + + for (bw = 0; bw < CHNL_BW_MAX_HT; bw++) { + for (nss = 0; nss < WRS_SS_MAX; nss++) { + for (mcs = 0; mcs < WRS_MCS_MAX_HT; mcs++) { + for (gi = 0; gi < WRS_GI_MAX_HT; gi++) { + packets = rx_stats->ht[bw][nss][mcs][gi]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_HT, + bw, nss, mcs, gi); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_HT] += packets; + total_data_rate[WRS_MODE_HT] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| HT |%4u|%4u|%5u|%4s| %7u.%u |%10llu|\n", + BW_TO_MHZ(bw), nss, mcs, gi_ht_vht_str[gi], + data_rate_div_10, data_rate_mod_10, packets); + } + } + } + } + +stats_ofdm: + if ((flag & RX_STATS_OFDM) == 0) + goto stats_cck; + + for (mcs = 0; mcs < WRS_MCS_MAX_OFDM; mcs++) { + packets = rx_stats->ofdm[mcs]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_OFDM, 0, 0, mcs, 0); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_OFDM] += packets; + total_data_rate[WRS_MODE_OFDM] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| OFDM | 20| 0|%5u| 0| %7u.%u |%10llu|\n", + mcs, data_rate_div_10, data_rate_mod_10, packets); + } + +stats_cck: + if ((flag & RX_STATS_CCK) == 0) + goto stats_end; + + for (mcs = 0; mcs < WRS_MCS_MAX_CCK; mcs++) { + packets = rx_stats->cck[mcs]; + + if (packets == 0) + continue; + + data_rate = cl_data_rates_get_x10(WRS_MODE_CCK, 0, 0, mcs, 0); + data_rate_div_10 = data_rate / 10; + data_rate_mod_10 = data_rate % 10; + + total_packets[WRS_MODE_CCK] += packets; + total_data_rate[WRS_MODE_CCK] += (packets * data_rate); + + cl_snprintf(&buf, &len, &buf_size, + "| CCK | 20| 0|%5u| 0| %7u.%u |%10llu|\n", + mcs, data_rate_div_10, data_rate_mod_10, packets); + } + +stats_end: + cl_snprintf(&buf, &len, &buf_size, + "-------------------------------------------------------\n"); + + for (mode = 0; mode < WRS_MODE_MAX; mode++) { + if (total_packets[mode] == 0) + continue; + + equivalent_data_rate = div64_u64(total_data_rate[mode], total_packets[mode]); + data_rate_div_10 = (u16)div64_u64_rem(equivalent_data_rate, 10, &remainder); + + cl_snprintf(&buf, &len, &buf_size, + "%s: Equivalent data rate = %u.%u Mbps\n\n", + WRS_MODE_STR(mode), data_rate_div_10, (u16)remainder); + } + + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void cl_stats_print_rx(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + if (cl_hw->chip->conf->ce_production_mode) + _cl_stats_print_rx(cl_hw, cl_hw->rx_stats, NULL); + else + _cl_stats_print_rx(cl_hw, &cl_sta->stats->rx, cl_sta); +} + +static void cl_stats_print_cpu(struct cl_hw *cl_hw) +{ + u32 cpu = 0; + char *buf = NULL; + ssize_t buf_size; + int len = 0; + struct cl_cpu_cntr *cpu_cntr = &cl_hw->cpu_cntr; + + cl_snprintf(&buf, &len, &buf_size, "|-------------------------|\n"); + cl_snprintf(&buf, &len, &buf_size, "|CPU|Tx Agg |Tx Single |\n"); + cl_snprintf(&buf, &len, &buf_size, "|---+----------+----------|\n"); + + for (cpu = 0; cpu < CPU_MAX_NUM; cpu++) { + if (cpu_cntr->tx_agg[cpu] == 0 && cpu_cntr->tx_single[cpu] == 0) + continue; + + cl_snprintf(&buf, &len, &buf_size, "| %u |%10u|%10u|\n", + cpu, + cpu_cntr->tx_agg[cpu], + cpu_cntr->tx_single[cpu]); + } + + cl_snprintf(&buf, &len, &buf_size, "|-------------------------|\n"); + + cl_vendor_reply(cl_hw, buf, len); + kfree(buf); +} + +static void cl_sta_print_do(struct cl_hw *cl_hw, u8 sta_idx, stats_callback callback) +{ + struct cl_sta *cl_sta; + + cl_sta_lock(cl_hw); + + cl_sta = cl_sta_get(cl_hw, sta_idx); + if (cl_sta) + callback(cl_hw, cl_sta); + + cl_sta_unlock(cl_hw); +} + +static void cl_stats_cli_cpu(struct cl_hw *cl_hw, bool action) +{ + if (action) + cl_stats_print_cpu(cl_hw); + else + memset(&cl_hw->cpu_cntr, 0, sizeof(struct cl_cpu_cntr)); +} + +static void cl_stats_cli_rx_info(struct cl_hw *cl_hw, bool action) +{ + if (action) + cl_rx_info_print(cl_hw); + else + cl_rx_info_reset(cl_hw); +} + +static void cll_stats_config_ps(struct cl_sta *cl_sta) +{ + cl_sta->stats->ps.timestamp_sleep = jiffies; + cl_sta->stats->ps.is_ps = test_sta_flag(cl_sta->stainfo, WLAN_STA_PS_STA) ? true : false; +} + +static void cl_stats_free(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + kfree(cl_sta->stats); + cl_sta->stats = NULL; +} + +static void cl_stats_disable(struct cl_hw *cl_hw) +{ + pr_debug("Statistics disabled\n"); + cl_hw->conf->ci_stats_en = false; + cl_sta_loop(cl_hw, cl_stats_free); + + if (cl_hw->chip->conf->ce_production_mode) { + kfree(cl_hw->rx_stats); + cl_hw->rx_stats = NULL; + } +} + +static void cl_stats_enable(struct cl_hw *cl_hw) +{ + /* + * Allocate for all existing stations. + * If one of the allocations fails disable ci_stats_en (and free the + * stations that were already allocated). + * In production mode also allocate cl_hw->rx_stats + */ + struct cl_sta *cl_sta = NULL; + bool success = true; + + if (cl_hw->chip->conf->ce_production_mode) { + cl_hw->rx_stats = kzalloc(sizeof(*cl_hw->rx_stats), GFP_ATOMIC); + + if (!cl_hw->rx_stats) + goto out; + } + + read_lock(&cl_hw->cl_sta_db.lock); + + list_for_each_entry(cl_sta, &cl_hw->cl_sta_db.head, list) { + cl_sta->stats = kzalloc(sizeof(*cl_sta->stats), GFP_ATOMIC); + + if (cl_sta->stats) { + cll_stats_config_ps(cl_sta); + } else { + success = false; + break; + } + } + + if (success) { + pr_debug("Statistics enabled\n"); + cl_hw->conf->ci_stats_en = true; + } else { + list_for_each_entry(cl_sta, &cl_hw->cl_sta_db.head, list) + cl_stats_free(cl_hw, cl_sta); + } + +out: + read_unlock(&cl_hw->cl_sta_db.lock); +} + +static void cl_stats_cli_enable(struct cl_hw *cl_hw, bool enable) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (enable == cl_hw->conf->ci_stats_en) { + pr_debug("Statistics are already %s\n", enable ? "Enabled" : "Disabled"); + goto out; + } + + if (enable) + cl_stats_enable(cl_hw); + else + cl_stats_disable(cl_hw); + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static void cl_stats_cli_rx(struct cl_hw *cl_hw, u8 sta_idx) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + if (cl_hw->chip->conf->ce_production_mode) { + cl_stats_print_rx(cl_hw, NULL); + } else { + if (sta_idx == STA_IDX_INVALID) + cl_sta_loop(cl_hw, cl_stats_print_rx); + else + cl_sta_print_do(cl_hw, sta_idx, cl_stats_print_rx); + } + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static void cl_stats_cli_rssi(struct cl_hw *cl_hw, u8 sta_idx) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + if (sta_idx == STA_IDX_INVALID) + cl_sta_loop(cl_hw, cl_stats_print_rssi); + else + cl_sta_print_do(cl_hw, sta_idx, cl_stats_print_rssi); + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static void cl_stats_cli_fec_coding(struct cl_hw *cl_hw, u8 sta_idx) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + if (sta_idx == STA_IDX_INVALID) + cl_sta_loop(cl_hw, cl_stats_print_fec_coding); + else + cl_sta_print_do(cl_hw, sta_idx, cl_stats_print_fec_coding); + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static void cl_stats_cli_ps(struct cl_hw *cl_hw, u8 sta_idx) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + if (sta_idx == STA_IDX_INVALID) + cl_sta_loop(cl_hw, cl_stats_print_power_save); + else + cl_sta_print_do(cl_hw, sta_idx, cl_stats_print_power_save); + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static void cl_stats_cli_tx(struct cl_hw *cl_hw, u8 sta_idx) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + if (sta_idx == STA_IDX_INVALID) + cl_sta_loop(cl_hw, cl_stats_print_tx); + else + cl_sta_print_do(cl_hw, sta_idx, cl_stats_print_tx); + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static void cl_stats_cli_reset(struct cl_hw *cl_hw, u8 sta_idx) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + if (cl_hw->chip->conf->ce_production_mode) { + memset(cl_hw->rx_stats, 0, sizeof(struct cl_rx_stats)); + } else { + if (sta_idx == STA_IDX_INVALID) + cl_sta_loop(cl_hw, cl_stats_sta_reset); + else + cl_sta_print_do(cl_hw, sta_idx, cl_stats_sta_reset); + } + +out: + spin_unlock_bh(&cl_hw->lock_stats); +} + +static int cl_stats_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "stats usage:\n" + "-a : Print air PER and system PER [delay-ms)]\n" + "-b : CPU stats [0-reset, 1-print]\n" + "-e : Enable/Disable statistics [0-dis, 1-en]\n" + "-f : Print RX FEC coding counters [sta_idx]\n" + "-p : Print power-save statistics [sta_idx]\n" + "-r : Print RX stats table [sta_idx]\n" + "-s : Print RSSI stats tables [sta_idx]\n" + "-t : Print TX stats table [sta_idx]\n" + "-u : Uplink stats [0-reset, 1-print]\n" + "-z : Reset stats tables [sta_idx]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static void _cl_stats_update_tx(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report) +{ + struct cl_stats *stats = cl_sta->stats; + struct cl_tx_cntrs *cntrs; + union cl_rate_ctrl_info rate_ctrl_info = {.word = agg_report->rate_cntrl_info}; + u8 bw, nss, mcs, gi, bf; + + switch (rate_ctrl_info.field.format_mod) { + case WRS_MODE_HE: + nss = (rate_ctrl_info.field.mcs_index >> 4); + mcs = (rate_ctrl_info.field.mcs_index & 0xF); + gi = rate_ctrl_info.field.gi; + bw = rate_ctrl_info.field.bw; + bf = agg_report->bf; + cntrs = &stats->tx.he[bw][nss][mcs][gi][bf]; + break; + case WRS_MODE_VHT: + bw = rate_ctrl_info.field.bw; + nss = (rate_ctrl_info.field.mcs_index >> 4); + mcs = (rate_ctrl_info.field.mcs_index & 0xF); + gi = rate_ctrl_info.field.gi; + bf = agg_report->bf; + cntrs = &stats->tx.vht[bw][nss][mcs][gi][bf]; + break; + case WRS_MODE_HT: + bw = rate_ctrl_info.field.bw; + nss = (rate_ctrl_info.field.mcs_index >> 3); + mcs = (rate_ctrl_info.field.mcs_index & 0x7); + gi = rate_ctrl_info.field.gi; + cntrs = &stats->tx.ht[bw][nss][mcs][gi]; + break; + case WRS_MODE_OFDM: + mcs = rate_ctrl_info.field.mcs_index - RATE_CTRL_OFFSET_OFDM; + cntrs = &stats->tx.ofdm[mcs]; + break; + case WRS_MODE_CCK: + mcs = rate_ctrl_info.field.mcs_index; + cntrs = &stats->tx.cck[mcs]; + break; + default: + return; + } + + cntrs->success += agg_report->success; + cntrs->fail += agg_report->fail; +} + +void cl_stats_init(struct cl_hw *cl_hw) +{ + spin_lock_init(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en && cl_hw->chip->conf->ce_production_mode) { + cl_hw->rx_stats = kzalloc(sizeof(*cl_hw->rx_stats), GFP_ATOMIC); + + if (!cl_hw->rx_stats) + cl_hw->conf->ci_stats_en = false; + } +} + +void cl_stats_deinit(struct cl_hw *cl_hw) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en && cl_hw->chip->conf->ce_production_mode) { + cl_hw->conf->ci_stats_en = false; + + kfree(cl_hw->rx_stats); + cl_hw->rx_stats = NULL; + } + + spin_unlock_bh(&cl_hw->lock_stats); +} + +void cl_stats_sta_add(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + /* If allocation failed disable ci_stats_en, and free the memory of all other stations */ + bool disable = false; + + /* Take regular lock and not BH, because cl_sta_add_to_lut() already disables BH */ + spin_lock(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en) { + cl_sta->stats = kzalloc(sizeof(*cl_sta->stats), GFP_ATOMIC); + + if (cl_sta->stats) + cll_stats_config_ps(cl_sta); + else + disable = true; + } + + spin_unlock(&cl_hw->lock_stats); + + if (disable) + cl_stats_cli_enable(cl_hw, false); +} + +void cl_stats_sta_remove(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + spin_lock_bh(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en) + cl_stats_free(cl_hw, cl_sta); + + spin_unlock_bh(&cl_hw->lock_stats); +} + +void cl_stats_update_tx_agg(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report) +{ + spin_lock(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en) { + struct cl_stats *stats = cl_sta->stats; + + stats->tx.agg_cntr++; + stats->tx.fail_cntr += agg_report->fail; + _cl_stats_update_tx(cl_hw, cl_sta, agg_report); + } + + spin_unlock(&cl_hw->lock_stats); +} + +void cl_stats_update_tx_single(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report) +{ + spin_lock(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en) { + cl_sta->stats->tx.fail_cntr += agg_report->fail; + _cl_stats_update_tx(cl_hw, cl_sta, agg_report); + } + + spin_unlock(&cl_hw->lock_stats); +} + +void cl_stats_update_rx_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta, s8 rssi[MAX_ANTENNAS]) +{ + int i; + s8 rx_rssi; + + spin_lock(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + for (i = 0; i < cl_hw->num_antennas; i++) { + rx_rssi = rssi[i] * -1; + + if (rx_rssi >= 0 && rx_rssi < RSSI_ARR_SIZE) + cl_sta->stats->rssi[rx_rssi][i]++; + } + +out: + spin_unlock(&cl_hw->lock_stats); +} + +void _cl_stats_update_rx_rate(struct cl_hw *cl_hw, struct cl_rx_stats *rx_stats, + struct hw_rxhdr *rxhdr) +{ + u8 bw, nss, mcs, gi; + + switch (rxhdr->format_mod) { + case FORMATMOD_HE_TRIG: + nss = rxhdr->n_sts & 0x3; + mcs = min_t(u8, rxhdr->mcs, WRS_MCS_MAX_HE); + gi = min_t(u8, rxhdr->gi_type, WRS_GI_MAX_HE); + rx_stats->he_trig[rxhdr->ch_bw][nss][mcs][gi] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_HE_TRIG; + break; + case FORMATMOD_HE_EXT: + nss = rxhdr->n_sts & 0x3; + mcs = min_t(u8, rxhdr->mcs, WRS_MCS_MAX_HE); + gi = min_t(u8, rxhdr->gi_type, WRS_GI_MAX_HE); + rx_stats->he_ext[rxhdr->ch_bw][nss][mcs][gi] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_HE_EXT; + break; + case FORMATMOD_HE_MU: + nss = rxhdr->n_sts & 0x3; + mcs = min_t(u8, rxhdr->mcs, WRS_MCS_MAX_HE); + gi = min_t(u8, rxhdr->gi_type, WRS_GI_MAX_HE); + rx_stats->he_mu[rxhdr->ch_bw][nss][mcs][gi] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_HE_MU; + break; + case FORMATMOD_HE_SU: + nss = rxhdr->n_sts & 0x3; + mcs = min_t(u8, rxhdr->mcs, WRS_MCS_MAX_HE); + gi = min_t(u8, rxhdr->gi_type, WRS_GI_MAX_HE); + rx_stats->he_su[rxhdr->ch_bw][nss][mcs][gi] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_HE_SU; + break; + case FORMATMOD_VHT: + nss = rxhdr->n_sts & 0x3; + mcs = min_t(u8, rxhdr->mcs, WRS_MCS_MAX_VHT); + gi = rxhdr->gi_type & 0x1; + rx_stats->vht[rxhdr->ch_bw][nss][mcs][gi] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_VHT; + break; + case FORMATMOD_HT_MF: + case FORMATMOD_HT_GF: + bw = rxhdr->ch_bw & 0x1; + nss = (rxhdr->mcs >> 3) & 0x3; + mcs = rxhdr->mcs & 0x7; + gi = rxhdr->gi_type & 0x1; + rx_stats->ht[bw][nss][mcs][gi] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_HT; + break; + case FORMATMOD_NON_HT: + if (rxhdr->mcs >= RATE_CTRL_OFFSET_OFDM) { + mcs = (rxhdr->mcs - RATE_CTRL_OFFSET_OFDM) & 0x7; + rx_stats->ofdm[mcs] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_OFDM; + } else if (cl_band_is_24g(cl_hw)) { + mcs = rxhdr->mcs & 0x3; + rx_stats->cck[mcs] += rxhdr->frm_successful_rx; + rx_stats->flag |= RX_STATS_CCK; + } + break; + } +} + +void cl_stats_update_rx_rate(struct cl_hw *cl_hw, struct cl_sta *cl_sta, struct hw_rxhdr *rxhdr) +{ + spin_lock(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en) { + _cl_stats_update_rx_rate(cl_hw, &cl_sta->stats->rx, rxhdr); + cl_sta->stats->fec_coding[rxhdr->fec_coding]++; + } + + spin_unlock(&cl_hw->lock_stats); +} + +void cl_stats_update_rx_rate_production(struct cl_hw *cl_hw, struct hw_rxhdr *rxhdr) +{ + spin_lock(&cl_hw->lock_stats); + + if (cl_hw->conf->ci_stats_en) + _cl_stats_update_rx_rate(cl_hw, cl_hw->rx_stats, rxhdr); + + spin_unlock(&cl_hw->lock_stats); +} + +void cl_stats_update_ps(struct cl_hw *cl_hw, struct cl_sta *cl_sta, bool is_ps) +{ + struct cl_ps_stats *ps; + + spin_lock(&cl_hw->lock_stats); + + if (!cl_hw->conf->ci_stats_en) + goto out; + + ps = &cl_sta->stats->ps; + + if (ps->is_ps == is_ps) + goto out; + + ps->is_ps = is_ps; + + if (is_ps) { + ps->timestamp_sleep = jiffies; + } else { + unsigned long sleep_time = jiffies_to_msecs(jiffies - ps->timestamp_sleep); + + if (sleep_time <= 50) + ps->period[PS_PERIOD_50MS]++; + else if (sleep_time <= 100) + ps->period[PS_PERIOD_100MS]++; + else if (sleep_time <= 250) + ps->period[PS_PERIOD_250MS]++; + else if (sleep_time <= 500) + ps->period[PS_PERIOD_500MS]++; + else if (sleep_time <= 750) + ps->period[PS_PERIOD_750MS]++; + else if (sleep_time <= 1000) + ps->period[PS_PERIOD_1000MS]++; + else if (sleep_time <= 2000) + ps->period[PS_PERIOD_2000MS]++; + else if (sleep_time <= 5000) + ps->period[PS_PERIOD_5000MS]++; + else if (sleep_time <= 10000) + ps->period[PS_PERIOD_10000MS]++; + else + ps->period[PS_PERIOD_ABOVE]++; + } + +out: + spin_unlock(&cl_hw->lock_stats); +} + +int cl_stats_cli(struct cl_hw *cl_hw, struct cl_vif *cl_vif, struct cli_params *cli_params) +{ + bool print_per = false; + bool cpu_stats = false; + bool enable_tx_rx_rssi = false; + bool print_rx = false; + bool print_rssi = false; + bool print_fec_coding = false; + bool print_power_save = false; + bool print_tx = false; + bool uplink_stats = false; + bool reset_stats = false; + u32 expected_params = -1; + + switch (cli_params->option) { + case 'a': + print_per = true; + expected_params = 1; + break; + case 'b': + cpu_stats = true; + expected_params = 1; + break; + case 'e': + enable_tx_rx_rssi = true; + expected_params = 1; + break; + case 'f': + print_fec_coding = true; + expected_params = 1; + break; + case 'p': + print_power_save = true; + expected_params = 1; + break; + case 't': + print_tx = true; + expected_params = 1; + break; + case 'r': + print_rx = true; + expected_params = cl_hw->chip->conf->ce_production_mode ? 0 : 1; + break; + case 'z': + reset_stats = true; + expected_params = cl_hw->chip->conf->ce_production_mode ? 0 : 1; + break; + case 's': + print_rssi = true; + expected_params = 1; + break; + case 'u': + uplink_stats = true; + expected_params = 1; + break; + case '?': + return cl_stats_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (print_per) { + cl_stats_print_per(cl_hw, (u32)cli_params->params[0]); + return 0; + } + + if (cpu_stats) { + cl_stats_cli_cpu(cl_hw, (bool)cli_params->params[0]); + return 0; + } + + if (uplink_stats) { + cl_stats_cli_rx_info(cl_hw, (bool)cli_params->params[0]); + return 0; + } + + if (enable_tx_rx_rssi) { + cl_stats_cli_enable(cl_hw, (bool)cli_params->params[0]); + return 0; + } + + if (!cl_hw->conf->ci_stats_en) { + pr_debug("Statistics are disabled!\n" + "To enable them type: " + "'iwcl cecli stats -e.1'\n"); + return 0; + } + + if (print_rx) { + u8 sta_idx = (u8)cli_params->params[0]; + + cl_stats_cli_rx(cl_hw, sta_idx); + return 0; + } + + if (print_rssi) { + u8 sta_idx = (u8)cli_params->params[0]; + + cl_stats_cli_rssi(cl_hw, sta_idx); + return 0; + } + + if (print_fec_coding) { + u8 sta_idx = (u8)cli_params->params[0]; + + cl_stats_cli_fec_coding(cl_hw, sta_idx); + return 0; + } + + if (print_power_save) { + u8 sta_idx = (u8)cli_params->params[0]; + + cl_stats_cli_ps(cl_hw, sta_idx); + return 0; + } + + if (print_tx) { + u8 sta_idx = (u8)cli_params->params[0]; + + cl_stats_cli_tx(cl_hw, sta_idx); + return 0; + } + + if (reset_stats) { + u8 sta_idx = (u8)cli_params->params[0]; + + cl_stats_cli_reset(cl_hw, sta_idx); + return 0; + } + +out_err: + return -EIO; +} From patchwork Thu Jun 17 16:01:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D722C49361 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 185/256] cl8k: add stats.h Date: Thu, 17 Jun 2021 16:01:12 +0000 Message-Id: <20210617160223.160998-186-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:05:58 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3820dcd5-e286-42a6-662b-08d931a9cbe3 X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FWQtPBp3G8v1bXH7nvcNew4azXGLQa6v9/PUYn5yWsDbjac8HXq2yNUpYwHpkoMANiicnwl1bpef09P8pS8p+IzxqiGTNVhzPYbDxLkv0yHodqZz9HeMh2y+qdrFo5YIDXVbxpBwaVJKgUhdZM3vEPJ2yZ2eBR5//5Q1+sVUs4JsJ28bUHHf7cPQua7ee/k5RvYa3JBSfDL3FuTdfDsb3e0Myeerm8ikjMe64sPLocl/cg37YYOBFSFekMIvXvDmQZIJtOYO5hJLNR2zAsm9kkhrblQvl7swhypYV2G2XUXejrr7rN+FL1YRGDWBN7PChEF11x05em05SIwOPcGcZfZ/PMOoKv6Uqxnq1c1fnhb8tiQv6aoAWJFxP7QAMyqgxgD4J115jRmAXw6prUB93OV7qfFYihXTLXUkpd+NtQmKyxz9he7CbwssG1KqwMxm6DY9AHT5Yn6pBWLCGm/RbWPT6M2IolRXtoqmRUF8RpSVnHBFO4FfGGKR38LpFZy60btDrPiS1DTcTySHnp38Wgb3+uLKX8BL1pZD1+pvtuZRjH2T7MhZhhRrF8RKdkTYCUxeBAx4j8M5Rsgh3Uin1t7yVxJpDs7t1uHE/hw9mSyVC6UKuma7iHLw86O4cKCURLNIuNbXsmBYP4CPFfVbG1647eAGt2oRSJCTgsnGgWbOQU8CiSsSo/i0hCvsbLg0/pZ/5kriA+WBzcqv5eiCcg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(8936002)(86362001)(107886003)(4326008)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(498600001)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dei20I/EAo65zY8FAcFinyfyMQUqssXZpEPeB5sRcVNVoLoaWiftG4pJsxLLJsPEtw8GDLXvAHtUnYp/zcXpaDEjyFq0b8ZX3JKQqqQFHbnHE+hjlHlvEi+QZ/QIoLRz7auW49vTa6aBiNwwirvBer0HBex9l9qFo/1fBkbUXXzdrreTs8MHnO9BIjLez8/sY5lw2K7MqfoMkAcHLYoBnuIkyIjcaT0ZaDJrDkiPxopzsU0PBDpA9FiF5UZaNLnwG7pf1UMoWcl8YCeM+61QBwhJ8ffB1PHnpZgE0fMzmgtnI5ZApAH2CUyoT+VbgQa7JJcPbzC3EWM5J5n2Tc/ixhHk6M1RqswVTG1zu9NeQvnATvyvC92SL1ZWUseWo6Dhs7powX5LnEK+WCLpSwqIdGRPxYepacWRf3XQK0NHbG2UiTup1kR6QwEQxErwKEtZNRckxdUReuCNLu2fVef2rDLW9umY7ASRSJ+/M9SzztRTOKdDQ650GIX9AaKb3Llme6LmERjx+8LiIvCOXujGaVFBLV+8/ZiNIosUrC5KN6KJvc483QWdHp0yXWJnUTuHWUsQxf8SZEfa7oMy/96KSr6Qzjy5VERg666LANQnyzWcR8xsqgTVogjghH3UbJVP4vx21QDESnY8NUB5IHN+aXmDZufsMDkBKf4fzLjPCqw3IOHAWWFcn7hJCeJSLh44gsdVaWWCPXK9/1E78Me1KHnjec9MUKJlSW5hNqRvvADnIdyfZ2rOR4LpS3BUTQ4RhfvSFzj3+xdbJ7kSYioAZpSftPHqRDu05tLMUzc8N9Gd9HpyNJxnmPIWEE7QOH+q9BnuiYwZEmI94zFEHjIAGBZ2G6r1fVbpbs/Qhv63kmQYzT8L3ccmMrK+SFuslHFv3MJG4FAouC1ipr5UcG5np23JXgjbXTjt4ITIgDwOBw1ZMfAYt/dDQArIaULrn5j8w+l7QEdBZE00UZFgf3nYypWQpKxEtr+whS/hCD4VQzK7RplpNAXAKKF3ELynqEok737W0z4/a95tsQCx/8vYmSYie2+zLG5BV/7d+ehUG5+Tz2/1nzGjVQ8CLoT0ac1SKr4mqh5p7NhQCpulXStEMY6gNbxDbrYtanGTT/Vhhu9KueJuA71zI66VK4LrXFlrwQJ7NHMVyeOAJG3Uj3VzfijeCXrjbO4azmmZy+t1Y7S1uGJ1a851ArknWZ0DrwFySguUP9lj9ad21GNB0FyVAKO5edof1zCK6aJJhP7yi37OUqrOWsN25+f3KAzEQEOCmUW+8aZN7oDHmMxCOVJ8xM/UYXXfLwrN7qBnK4rXccKPyWf3fLKeAhzp4mLVcJOP X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3820dcd5-e286-42a6-662b-08d931a9cbe3 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:05:59.0911 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: optsRIMkKd1C7AZ1C3a3r5zee0PXWYfUKujHuQxdn1nBaXcUDJpgKlDBBMA3FPvFbr0x/qTgl/h4Nd6S56wvrQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/stats.h | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/stats.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/stats.h b/drivers/net/wireless/celeno/cl8k/stats.h new file mode 100644 index 000000000000..91a7bed25a2a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/stats.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_STATS_H +#define CL_STATS_H + +#include "hw.h" +#include "rx/rx.h" +#include "utils/timer.h" +#include "tx/agg_tx_report.h" +#include "vendor_cmd.h" + +void cl_stats_init(struct cl_hw *cl_hw); +void cl_stats_deinit(struct cl_hw *cl_hw); +void cl_stats_sta_add(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +void cl_stats_sta_remove(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +void cl_stats_update_tx_agg(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report); +void cl_stats_update_tx_single(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report); +void cl_stats_update_rx_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta, s8 rssi[MAX_ANTENNAS]); +void cl_stats_update_rx_rate(struct cl_hw *cl_hw, struct cl_sta *cl_sta, struct hw_rxhdr *rxhdr); +void cl_stats_update_rx_rate_production(struct cl_hw *cl_hw, struct hw_rxhdr *rxhdr); +void cl_stats_update_ps(struct cl_hw *cl_hw, struct cl_sta *cl_sta, bool is_ps); +int cl_stats_cli(struct cl_hw *cl_hw, struct cl_vif *cl_vif, struct cli_params *cli_params); + +#endif /* CL_STATS_H */ From patchwork Thu Jun 17 16:01:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8B4AC2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 187/256] cl8k: add tcv_config.h Date: Thu, 17 Jun 2021 16:01:14 +0000 Message-Id: <20210617160223.160998-188-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:00 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 57a69745-2b6d-44c8-a077-08d931a9cd3d X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pwau+vfkMiDyMWUhBwyJzhDB8iAmQhjEHvuQdCUOeSn1SwT/Sw0/vz2KWkSh8/78IQcuYsOpIFMjVV/DOctdJiuZZ4Qn/i9F0ALooREt7lPiWkHe06V5KZYDDN4s/S5IeNO66vDdL8h9eT5FRaPOw+Y5mwbgJQirLR6KKqM9G/xO6jIMQpr0MD0YPce5LJNsFkjbcOr9rhpWxkVhsVioCKzVKSP8e88RVPmVj1ojA/GOxBfSvImCuiCBoTVDNdbsxkwJUTnFCCpAxe8XUCqbkq4OY1H05sb817zPbZvHz2cU5At99u1Q4rAvxu5XXRz+pDE0zshVgi4Qg/0DE/o2zWx70ybECtBIFHxiL9cD8I7+Fw3D9rQG0hsLQJAZvMGOxOcl5AYW5++ncC3KBUnA2BqhTMNTNcnY0ewiGUwVf9r6WGzcQvhH6PuZ5HYQybhudDUgaghzyQxTVfa5wnNcLj7c2RIoM6+ird4YLnrlTbhX0UB/6FAl6cpVWaCTJo3t3vpxRm96qpu/qeL13dhYRffz6TfFOKZ6zvgX8LTr4fgF5drmXeYXK5Kv6fFGXdtJh6mUgSZhc9RUkGPixsiQO/zfsaoEU4XCvvUlUPYYMA4oRfTBJR8cB1KPT205jfQwKkh1Te+gBwTwtoIEx4hS64KKCnY6yW9sTxenuQyTqqi+Lnkjdr65O0PMNXJBeAajjarW509qo+71Y2P2mbSwYw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(8936002)(86362001)(107886003)(4326008)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(498600001)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(30864003)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DjE3rLeStlOyscyq0O3dQqIBdG+wM8UVLwbr3R8puYJYoak5sYwtQavIJGpIg7spYAJzfwKHVOzsAYVVDI3GpzQ/1uCAfXcqllPYtFzY7o0L2+SiIJd6UhOFFPVRrPuJltNIku2HSljUrcLPeZKkSY/I7YA3uxFMU+lWCKL1tA2u199rKgS75F8owJm3s7tOnq7cCb9FDcig5JnLhmMkNV9nM+n+SAoiblyPAGXeoQnJMq/IhJCN3v6ysAV/53w0YOaawBjLIq1nG7y5qJCl4KmgJhB12WqEIfYtFn8D/fIveLVIIQwHTjy0RWdpJRx6YNIjSuyDpy4LSqEZdw4pMGy6JwzstGah9eMzPm5LfFN97dThROd5AfM4r6jQp6qCLGmPKvF1mNe3Ghc+Ku47HAJR355dPoaYEpafP7z7MQzhhJ7M7HZQIm+JXo1KV4KePzm4mG6ArnGGdbI+tA4YRAuR/VNRHyHP9dWiEtC5tDTJGb5YnAE+RwQ1Fk2XPpRGnOt2NwOLpzNQGqZlL6TQHwnGeT4lKvWw5ONpDojbDcRsxJGNHPWs1Jqx1mLTg3S/oNRwCTIg7b9poSKekcPnD8adEHRUPO7HOtbOQmWJ1pAfJj5wQoTIPknVpg7Z6b07MZ7DW9BRaM+pMAU4Vf1xtctfSVXzlOuBCYW5lL5P5kT8gbsYUxo8VsFt6XtdZLQEuza6EnPPeIUzdh2JXHPtuaPn/VFEo1khUJVbTWVP7oMUZ51SO46/843u1NrWj99kmT0F7CA19sISBlh3z7ar33o0Hpj12bzd+p7iK0tzO53lpcksDfqN8bwpFKDzEDlfeDCz3LrHEfDhXhOk/e2g4c5cLj2VOxd4CBCNkUJXrUbLvu/rXZvVoE/qNlquwGGQEdvAwV0RCAvSffDA8g0mdnisZcdsAC01+BzD/4ZbZAHUKOJdmpcpk8mLscx8GenXBTgZ1uz97c6KiDQaA7hIpP+FM2ZrBtxMOoyhJbnd++KS1WExCDQQDWpZCICRyOq+hknd9p8pKLMI9i5QMUCnxTeFxbRgN1Blv5Pxg1w3CrFKUMEwFx/7z9XTQ1YnYoFLYU5tnNLzhRcIG40RKUFkP1ub5JnMHWSe6vrtuf6qMS6ZpPzxD5qWydl6BM0NSo3n8AS7S1qcRr0k31reGxbnOEJiX2/b0A+YLRQK9mJIrYgmXpuc+SGjQMaqBM4TfYTTba1GiOSwTrfj6lEi4xPUyOVDHmu3dL1WWNBf1Wf3gP1YhJFOOAcaCI4PsQTanNmGE68dOGLYwHBaouhSfQ3DlqEm6pIJ6hHFIb5hfmLwlETY7XmSLmK/2t/PRScimU/b X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 57a69745-2b6d-44c8-a077-08d931a9cd3d X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:01.4030 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ib3YXXY6KyEQq8OSaj5jo60pNIjjfxFuHeIJyW+mez3UxA3YAj8k6CypSR162CBrDC8SxU5CDEWS/f779FvkBg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/tcv_config.h | 333 ++++++++++++++++++ 1 file changed, 333 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tcv_config.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tcv_config.h b/drivers/net/wireless/celeno/cl8k/tcv_config.h new file mode 100644 index 000000000000..f849cecb5656 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tcv_config.h @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TCV_CONFIG_H +#define CL_TCV_CONFIG_H + +#include "def.h" +#include "ipc_shared.h" +#include "wrs/wrs_db.h" +#include "dfs/dfs_db.h" +#include "edca.h" +#include "utils/string.h" +#include "sounding.h" + +/** + * TCV (=Tranceiver) configuration, is related to the specific band on top + * of specific chipset. + */ + +#define CL_DEFAULT_HAL_IDLE_TIMEOUT 16000 /* Idle request - 16ms */ +#define CL_TX_DEFAULT_AC0_TIMEOUT 500000 /* Background - 500ms */ +#define CL_TX_DEFAULT_AC1_TIMEOUT 300000 /* Best effort - 300ms */ +#define CL_TX_DEFAULT_AC2_TIMEOUT 200000 /* Video - 200ms */ +#define CL_TX_DEFAULT_AC3_TIMEOUT 200000 /* Voice - 200ms */ +#define CL_TX_DEFAULT_BCN_TIMEOUT 150000 /* Beacon - 150ms */ + +/* Minimal MPDU spacing we support in TX - correspond to FW NX_TX_MPDU_SPACING */ +#define CL_TX_MPDU_SPACING_INVALID 0xFF + +/* Default Power Per MCS (PPMCS) offsets in Q1 format */ +#define PPMCS_DFLT_OFT_V1_MCS_0 8 /* 4.0 */ +#define PPMCS_DFLT_OFT_V1_MCS_1 8 +#define PPMCS_DFLT_OFT_V1_MCS_2 6 /* 3.0 */ +#define PPMCS_DFLT_OFT_V1_MCS_3 6 +#define PPMCS_DFLT_OFT_V1_MCS_4 6 +#define PPMCS_DFLT_OFT_V1_MCS_5 4 /* 2.0 */ +#define PPMCS_DFLT_OFT_V1_MCS_6 4 +#define PPMCS_DFLT_OFT_V1_MCS_7 0 +#define PPMCS_DFLT_OFT_V1_MCS_8 -2 /* -1.0 */ +#define PPMCS_DFLT_OFT_V1_MCS_9 -2 +#define PPMCS_DFLT_OFT_V1_MCS_10 -6 /* -3.0 */ +#define PPMCS_DFLT_OFT_V1_MCS_11 -10 /* -5.0 */ + +#define PPMCS_DFLT_OFT_V2_MCS_0 6 +#define PPMCS_DFLT_OFT_V2_MCS_1 6 +#define PPMCS_DFLT_OFT_V2_MCS_2 4 +#define PPMCS_DFLT_OFT_V2_MCS_3 4 +#define PPMCS_DFLT_OFT_V2_MCS_4 4 +#define PPMCS_DFLT_OFT_V2_MCS_5 2 +#define PPMCS_DFLT_OFT_V2_MCS_6 2 +#define PPMCS_DFLT_OFT_V2_MCS_7 0 +#define PPMCS_DFLT_OFT_V2_MCS_8 -2 +#define PPMCS_DFLT_OFT_V2_MCS_9 -2 +#define PPMCS_DFLT_OFT_V2_MCS_10 -6 +#define PPMCS_DFLT_OFT_V2_MCS_11 -10 + +#define PPMCS_DFLT_OFT_V3_MCS_0 6 /* 3.0 */ +#define PPMCS_DFLT_OFT_V3_MCS_1 6 +#define PPMCS_DFLT_OFT_V3_MCS_2 4 /* 2.0 */ +#define PPMCS_DFLT_OFT_V3_MCS_3 4 +#define PPMCS_DFLT_OFT_V3_MCS_4 4 +#define PPMCS_DFLT_OFT_V3_MCS_5 2 /* 1.0 */ +#define PPMCS_DFLT_OFT_V3_MCS_6 2 +#define PPMCS_DFLT_OFT_V3_MCS_7 0 +#define PPMCS_DFLT_OFT_V3_MCS_8 -2 /* -1.0 */ +#define PPMCS_DFLT_OFT_V3_MCS_9 -2 +#define PPMCS_DFLT_OFT_V3_MCS_10 -10 /* -5.0 */ +#define PPMCS_DFLT_OFT_V3_MCS_11 -10 + +/* Default Power Per Bandwidth (PPBW) offsets in Q1 format*/ +#define PPBW_DFLT_OFT_BW_20 0 +#define PPBW_DFLT_OFT_BW_40 0 +#define PPBW_DFLT_OFT_BW_80 -2 +#define PPBW_DFLT_OFT_BW_160 -2 + +enum { + CL_RATE_FALLBACK_COUNT_SU, + CL_RATE_FALLBACK_COUNT_MU, + CL_RATE_FALLBACK_RETRY_COUNT_THR, + CL_RATE_FALLBACK_BA_PER_THR, + CL_RATE_FALLBACK_BA_NOT_RECEIVED_THR, + CL_RATE_FALLBACK_DISABLE_MCS, + + CL_RATE_FALLBACK_MAX, +}; + +struct cl_tcv_conf { + u8 ce_bss_num; + s8 ce_debug_level; + bool ce_radio_on; + bool ce_ps_ctrl_enabled; + u8 ha_channel; + bool ci_ieee80211w; + bool ci_ieee80211h; + u8 ha_short_guard_interval; + u8 ha_max_mpdu_len; + u8 ha_vht_max_ampdu_len_exp; + u32 ha_beacon_int; + s8 ce_dsp_code[STR_LEN_32B]; + s8 ce_dsp_data[STR_LEN_32B]; + s8 ce_dsp_external_data[STR_LEN_32B]; + bool ce_uapsd_en; + bool ci_eirp_regulatory_en; + bool ci_agg_tx; + bool ci_agg_rx; + bool ce_txldpc_en; + bool ce_ht_rxldpc_en; + bool ce_vht_rxldpc_en; + bool ce_he_rxldpc_en; + bool ci_cs_required; + s8 ci_rx_sensitivity_prod[MAX_ANTENNAS]; + s8 ci_rx_sensitivity_op[MAX_ANTENNAS]; + bool ce_cck_bcn_en; + bool ci_min_he_en; + u8 ce_cck_tx_ant_mask; + u8 ce_cck_rx_ant_mask; + u8 ce_rx_nss; + u8 ce_tx_nss; + u8 ce_num_antennas; + u8 ce_wireless_mode; + bool ha_wmm_enabled[MAX_BSS_NUM]; + u16 ce_max_agg_size_tx; + u16 ce_max_agg_size_rx; + bool ce_rxamsdu_en; + u8 ce_txamsdu_en; + u16 ci_tx_amsdu_min_data_rate; + u8 ci_tx_sw_amsdu_max_packets; + u16 ci_tx_packet_limit; + u16 ci_tx_queue_size_agg; + u16 ci_tx_queue_size_single; + u16 ci_ipc_rxbuf_size[CL_RX_BUF_MAX]; + u16 ce_max_retry; + u8 ce_short_retry_limit; + u8 ce_long_retry_limit; + u8 ci_assoc_auth_retry_limit; + u8 ce_channel_bandwidth; + u8 ce_iface_type[MAX_BSS_NUM]; + u8 ha_hw_mode; + s8 ce_temp_comp_slope; + u32 ci_fw_dbg_severity; + u32 ci_fw_dbg_module; + u32 ci_hal_idle_to; + u32 ci_tx_ac0_to; + u32 ci_tx_ac1_to; + u32 ci_tx_ac2_to; + u32 ci_tx_ac3_to; + u32 ci_tx_bcn_to; + s8 ce_hardware_power_table[STR_LEN_256B]; + s8 ce_arr_gain[STR_LEN_32B]; + s8 ce_bf_gain_2_ant[STR_LEN_32B]; + s8 ce_bf_gain_3_ant[STR_LEN_32B]; + s8 ce_bf_gain_4_ant[STR_LEN_32B]; + s8 ce_bf_gain_5_ant[STR_LEN_32B]; + s8 ce_bf_gain_6_ant[STR_LEN_32B]; + s8 ce_ant_gain[STR_LEN_32B]; + s8 ce_ant_gain_36_64[STR_LEN_32B]; + s8 ce_ant_gain_100_140[STR_LEN_32B]; + s8 ce_ant_gain_149_165[STR_LEN_32B]; + s8 ci_min_ant_pwr[STR_LEN_32B]; + s8 ci_bw_factor[STR_LEN_32B]; + u8 ce_mcast_rate; + bool ce_dyn_mcast_rate_en; + bool ce_dyn_bcast_rate_en; + u8 ce_default_mcs_ofdm; + u8 ce_default_mcs_cck; + bool ce_prot_log_nav_en; + u8 ce_prot_mode; + u8 ce_prot_rate_format; + u8 ce_prot_rate_mcs; + u8 ce_prot_rate_pre_type; + u8 ce_bw_signaling_mode; + u8 ci_dyn_cts_sta_thr; + s8 ci_vns_pwr_limit; + u8 ci_vns_pwr_mode; + s8 ci_vns_rssi_auto_resp_thr; + s8 ci_vns_rssi_thr; + s8 ci_vns_rssi_hys; + u16 ci_vns_maintenance_time; + u16 ce_bcn_tx_path_min_time; + bool ci_backup_bcn_en; + bool ce_tx_txop_cut_en; + u8 ci_bcns_flushed_cnt_thr; + bool ci_phy_err_prevents_phy_dump; + u8 ci_tx_rx_delay; + u8 ci_fw_assert_time_diff_sec; + u8 ci_fw_assert_storm_detect_thd; + u32 ce_hw_assert_time_max; + u8 ce_fw_watchdog_mode; + u8 ce_fw_watchdog_limit_count; + u32 ce_fw_watchdog_limit_time; + s8 ci_rx_remote_cpu_drv; + s8 ci_rx_remote_cpu_mac; + s8 ci_tx_remote_cpu; + u16 ci_pending_queue_size; + u8 ce_tx_power_control; + bool ce_standby_mode_en; + bool ce_coex_en; + s8 ce_extension_channel; + u8 ci_dfs_initial_gain; + u8 ci_dfs_agc_cd_th; + u16 ci_dfs_long_pulse_min; + u16 ci_dfs_long_pulse_max; + s8 ce_dfs_tbl_overwrite[STR_LEN_64B]; + s8 ce_dfs_jump_channels[STR_LEN_32B]; + /* Power Per MCS values - 6g */ + s8 ce_ppmcs_offset_he_6g[WRS_MCS_MAX_HE]; + /* Power Per MCS values - 5g */ + s8 ce_ppmcs_offset_he_36_64[WRS_MCS_MAX_HE]; + s8 ce_ppmcs_offset_he_100_140[WRS_MCS_MAX_HE]; + s8 ce_ppmcs_offset_he_149_165[WRS_MCS_MAX_HE]; + s8 ce_ppmcs_offset_ht_vht_36_64[WRS_MCS_MAX_VHT]; + s8 ce_ppmcs_offset_ht_vht_100_140[WRS_MCS_MAX_VHT]; + s8 ce_ppmcs_offset_ht_vht_149_165[WRS_MCS_MAX_VHT]; + s8 ce_ppmcs_offset_ofdm_36_64[WRS_MCS_MAX_OFDM]; + s8 ce_ppmcs_offset_ofdm_100_140[WRS_MCS_MAX_OFDM]; + s8 ce_ppmcs_offset_ofdm_149_165[WRS_MCS_MAX_OFDM]; + /* Power Per MCS values - 24g */ + s8 ce_ppmcs_offset_he[WRS_MCS_MAX_HE]; + s8 ce_ppmcs_offset_ht[WRS_MCS_MAX_HT]; + s8 ce_ppmcs_offset_ofdm[WRS_MCS_MAX_OFDM]; + s8 ce_ppmcs_offset_cck[WRS_MCS_MAX_CCK]; + /* Power Per BW values - all bands */ + s8 ce_ppbw_offset[CHNL_BW_MAX]; + bool ce_power_offset_prod_en; + bool ce_bf_en; + u8 ci_bf_max_nss; + u16 ce_sounding_interval_coefs[SOUNDING_INTERVAL_COEF_MAX]; + u8 ci_rate_fallback[CL_RATE_FALLBACK_MAX]; + u16 ce_rx_pkts_budget; + u8 ci_band_num; + bool ci_mult_ampdu_in_txop_en; + u8 ce_wmm_aifsn[AC_MAX]; + u8 ce_wmm_cwmin[AC_MAX]; + u8 ce_wmm_cwmax[AC_MAX]; + u16 ce_wmm_txop[AC_MAX]; + u8 ci_su_force_min_spacing; + u8 ci_mu_force_min_spacing; + u8 ci_tf_mac_pad_dur; + u32 ci_cca_timeout; + u16 ce_tx_ba_session_timeout; + bool ci_motion_sense_en; + s8 ci_motion_sense_rssi_thr; + u8 ci_wrs_max_bw; + u8 ci_wrs_min_bw; + s8 ci_wrs_fixed_rate[WRS_FIXED_PARAM_MAX]; + u8 ce_he_mcs_nss_supp_tx[WRS_SS_MAX]; + u8 ce_he_mcs_nss_supp_rx[WRS_SS_MAX]; + u8 ce_vht_mcs_nss_supp_tx[WRS_SS_MAX]; + u8 ce_vht_mcs_nss_supp_rx[WRS_SS_MAX]; + u8 ci_pe_duration; + u8 ci_pe_duration_bcast; + u32 ci_coredump_diff_time_ms; + u8 ci_gain_update_enable; + u8 ci_mcs_sig_b; + u8 ci_spp_ksr_value; + bool ci_rx_padding_en; + bool ci_stats_en; + bool ci_bar_disable; + bool ci_ofdm_only; + bool ci_drop_to_lower_bw; + bool ce_twt_en; + u32 ce_twt_default_interval; + u32 ce_twt_default_min_wake_duration; + u8 ce_twt_max_sessions; + u8 ci_hr_factor[CHNL_BW_MAX]; + bool ci_csd_en; + bool ci_signal_extension_en; + bool ce_dscp_vlan_enable[MAX_BSS_NUM]; + u8 ce_up0_7_default_vlan_user_prio[MAX_BSS_NUM]; + u8 ce_up0_7_layer_based[MAX_BSS_NUM]; + s8 ce_dscp_to_up0_7dec0[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec1[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec2[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec3[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec4[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec5[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec6[STR_LEN_128B]; + s8 ce_dscp_to_up0_7dec7[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec0[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec1[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec2[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec3[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec4[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec5[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec6[STR_LEN_128B]; + s8 ce_vlan_to_up0_7dec7[STR_LEN_128B]; + bool ci_vht_cap_24g; + bool ce_omi_en; + u32 ci_tx_digital_gain; + u32 ci_tx_digital_gain_cck; + s8 ci_ofdm_cck_power_offset; + bool ci_mac_clk_gating_en; + bool ci_phy_clk_gating_en; + bool ci_imaging_blocker; + u8 ci_ndp_tx_chain_mask; + u8 ci_ndp_tx_bw; + u8 ci_ndp_tx_format; + u8 ci_ndp_tx_num_ltf; + u8 ci_calib_ant_tx[MAX_ANTENNAS]; + u8 ci_calib_ant_rx[MAX_ANTENNAS]; + s8 ci_cca_ed_rise_thr_dbm; + s8 ci_cca_ed_fall_thr_dbm; + u8 ci_cca_cs_en; + u8 ci_cca_modem_en; + u8 ci_cca_main_ant; + u8 ci_cca_second_ant; + u8 ci_cca_flag0_ctrl; + u8 ci_cca_flag1_ctrl; + u8 ci_cca_flag2_ctrl; + u8 ci_cca_flag3_ctrl; + s8 ci_cca_gi_rise_thr_dbm; + s8 ci_cca_gi_fall_thr_dbm; + s8 ci_cca_gi_pow_lim_dbm; + u16 ci_cca_ed_en; + u8 ci_cca_gi_en; + bool ci_rx_he_mu_ppdu; + bool ci_fast_rx_en; + u8 ci_distance_auto_resp_all; + u8 ci_distance_auto_resp_msta; + + /* New NVRAM parameters must be added to cl_tcv_config_print() */ +}; + +struct cl_hw; + +int cl_tcv_config_read(struct cl_hw *cl_hw); +int cl_tcv_config_set(struct cl_hw *cl_hw, char *buf, size_t size); +u8 cl_tcv_config_get_num_ap(struct cl_hw *cl_hw); +int cl_tcv_config_alloc(struct cl_hw *cl_hw); +void cl_tcv_config_free(struct cl_hw *cl_hw); +void cl_tcv_config_print(struct cl_hw *cl_hw); + +#endif /* CL_TCV_CONFIG_H */ From patchwork Thu Jun 17 16:01:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F1A8C48BE5 for ; Thu, 17 Jun 2021 16:11:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 823B261428 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 189/256] cl8k: add temperature.h Date: Thu, 17 Jun 2021 16:01:16 +0000 Message-Id: <20210617160223.160998-190-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:02 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5f91a49c-3b61-45fa-2e7b-08d931a9ce8a X-MS-TrafficTypeDiagnostic: AM0P192MB0260: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:655; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: f2Ul6NzbbWSaGTGZewYmmKWt4vr9m/l4EGL89XiNtKHao/LAfdU1DGhbtnIS1WyMJ3RfTu4PYDEVV02OaVqujegjEGsayf1JPu3+DE/+wBzM4Vmub4cKvMTThu6eBEr3i15fB42uvV2on/sEf0NVJKLX+HJcdh4wPGZu5QTCfqySUxuinAoNpd5d9CB3Do6riijoTs+zWh4edPBGW3d9r+jo/FroXNSytTtetrjioRpwUJXAEYCmnYxHJ4sIbryrxrCGv2LVgDbJX4oPvFHULOC2uFSQZXy8gWVHdXp7Bs+SIuV1GIy59l8gppwQeCj8PuycGwliHlnOsmBVIKqtX1dM6fEUPrTNKYc4R/uyP88069K9mvJq8vQkHdr1J3aBzRXgNXTA6tFHZV1QVp/ZKqJFeRz9aF2ikAinoLKXurUYhIWHIZzjC1V6XKsUNx/gKaMFtoyvVO0c18hdP5lfCx7DTvp1m5CIp3lc5v0SGa/8WLlSm5A5SpfhwxzbXA5Ac5o0gu3wrSDgi3HGsdhWIABcZ1papbaxxBEvWV3xO0VpJeuUmC8wodb3kYcYJVoLe6BjzegK5RRb7+WztGaUtZ5vPmtMuLb9NPLgRsostZKyqY39zEj4P4x0NfK8P/DZgjwmn79XHuD8VHijvS/plClaYKUX4EdTJOKmsth9m+X/EJQKYPjgWJJISREiib2NFzZ0he+zHE8e/h1sWo7e8g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(8936002)(86362001)(107886003)(4326008)(26005)(8676002)(956004)(186003)(6666004)(2906002)(6512007)(66556008)(2616005)(5660300002)(498600001)(38350700002)(54906003)(38100700002)(16526019)(66946007)(9686003)(83380400001)(55236004)(52116002)(66476007)(6486002)(6916009)(6506007)(36756003)(1076003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aYOSpJxRGeYPYUge5jnr3TOODZOufJ+FU6GrGhLQ7k6p0FsCyVlIDDJ0vsSUW4pRH8vAdSXW4GU/OgGuDDGTfZeFk9GmTQH0JEBS36PC+mT3DEPNIViSMq1SBXoJZ0PWlu8g5VPCw6yxbPBPnAbMzGHIVp6TOZ09/l98Gl3n8a8AKHVfzHgomkxXjB8Ia53xnVlQN/R+fqTM6IQFvb48szbF9tTsiIH9RXMiPXXG/7nKuApjwEKj4rkZQ3p8QSMCyijxiUm5ErVpEqWluNoX0b/+evH9ikjp4ChAdzClXCxlJwknKueUgGgRakHB3ymYD59S1BTyu/YGOhLLTWs/0B2k6KBqAejFgGK2L6mrE0zRWVze4ZcC8xKVVSLXwRWnd4I3uqnD5WBF2pLq2LUOW0tAxmNh1HCRMFQTkXBAFeWGfPabkdR0pPkM2NzZP5qHPBxQZLIlPB8ISkIBJp2jzpmazwEZwio2n4Im3c5OKmBlGzUvzOoFQ0sxkzxdNFifOKtoTMrkyRMgM+frC2Pk2LzBF+UtNL1H0Pynf74JBuJbzdT44GenS59E/9U/1RxknO3nngQeTYSH//61Mamps4OPNqAl5rt6yqPjUJAjBm0a4IHPygux01KexdFcDwwbBXKLKXuAiAWSyLDXaI5X/X5kk8IxiEJvRyvlumk/gSuahrR5NyE89g1Ve59keJTjAcutKWp+QcJ2GJ0h17jmGhmixM5+gsr90wjcE1FAxPs1ggNx2nXcGGJ9i7MOIyQAZi4xZ5ZcjsdM8cofdv2aQUZtt+bEnm4I2+6fjYdXglpdyV3Qt7JTtrOfRgx9TrbrVaDp0N/0v7wesuFUmQxypuTE9tbeyX2cQKjkEmTaBAZW8jH/N9HcU1nBMHFq8akfr9UR00SzFAzsMfy4PnCYyujegII8DfAv+iG2RnzhTu19/Q2mnSqiKVtjq80Gzn4u3XhIZie1UPWGBw9DUcgH3L4D/F80myjBmbH3er5dytNNf4ytKBYuNdeljy9a1cv3gZ/965ENjbkfLIuMMLzmNjIbFOyMQYvJOqtykM3IhaVvDEm8dSFn5TtbFW2AJK5YSZ/lME8NpKQEg7VHIt/B7P8aVfyAmf/C5hjrT91CWdmvvr53Wr9nUmr6FlKw3nGsNyjuQatWkn/XlBpzc4FFQTYEoDX7TjXf0Ru3iFr4yEyM0FXvGNfpcAx79888J2dYVrXVgfCsFJbIuok7V5tpdT3n944T79J6OPgUD14qb/KFaoYjCQdOCsn0STqWvJndOlBwkOh00b1hX7bg36oz+qOjVjfpf7A1kcFaTkw52kJJBdFCDCugUXDUPbgr2tkC X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5f91a49c-3b61-45fa-2e7b-08d931a9ce8a X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:03.5416 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QKSA0i7MpNUf8U7PtmKx9/4pe+/PE3M2+G80bfoP2AL4qhR5M6gzBbCTzywTGhqq9iVng0U6lKlZNt4xGfwumA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0260 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/temperature.h | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/temperature.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/temperature.h b/drivers/net/wireless/celeno/cl8k/temperature.h new file mode 100644 index 000000000000..9f34d06b64eb --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/temperature.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TEMPERATURE_H +#define CL_TEMPERATURE_H + +#include +#include "vendor_cmd.h" + +#define CL_TEMP_PROTECT_INTERVAL_MS 40000 +#define CL_TEMP_PROTECT_NUM_SAMPLES 4 +#define CL_TEMP_PROTECT_RADIO_OFF_HYST 10 + +#define CL_TEMP_COMP_ITERATIONS 4 + +#define CL_TEMPERATURE_TIMER_INTERVAL_MS 4000 +#define CL_TEMPERATURE_UPDATE_INTERVAL_MS (CL_TEMPERATURE_TIMER_INTERVAL_MS - 100) + +enum cl_temp_state { + TEMP_PROTECT_OFF, + TEMP_PROTECT_INTERNAL, + TEMP_PROTECT_EXTERNAL, + TEMP_PROTECT_DIFF +}; + +enum cl_temp_mode { + TEMP_MODE_INTERNAL, + TEMP_MODE_EXTERNAL +}; + +struct cl_temp_comp_db { + s8 calib_temperature; + s8 power_offset; + s32 acc_temp_delta; + s32 avg_temp_delta; +}; + +struct cl_temp_protect_db { + bool force_radio_off; + u8 duty_cycle; + u8 test_mode_duty_cycle; + u8 curr_idx; + s16 last_samples[CL_TEMP_PROTECT_NUM_SAMPLES]; + unsigned long last_timestamp; +}; + +struct cl_temperature { + s8 diff_internal_external; + u8 comp_iterations; + struct cl_temp_protect_db protect_db; + struct task_struct *kthread; + wait_queue_head_t wait_q; + s16 internal_last; + s16 external_last; + unsigned long internal_read_timestamp; + unsigned long external_read_timestamp; + struct mutex mutex; +}; + +struct cl_chip; +struct cl_hw; + +void cl_temperature_init(struct cl_chip *chip); +void cl_temperature_close(struct cl_chip *chip); +s16 cl_temperature_get_internal(struct cl_hw *cl_hw); +s8 cl_temperature_read(struct cl_hw *cl_hw, enum cl_temp_mode mode); +int cl_temperature_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); +void cl_temperature_recovery(struct cl_hw *cl_hw); +bool cl_temperature_protect_did_reduce_duty_cycle(struct cl_hw *cl_hw); +int cl_temperature_diff_e2p_read(struct cl_hw *cl_hw); +s16 cl_temperature_calib_calc(struct cl_hw *cl_hw, u16 raw_bits); +void cl_temperature_comp_update_calib(struct cl_hw *cl_hw); + +#endif /* CL_TEMPERATURE_H */ From patchwork Thu Jun 17 16:01:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C556AC48BE5 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 191/256] cl8k: add trace.h Date: Thu, 17 Jun 2021 16:01:18 +0000 Message-Id: <20210617160223.160998-192-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:04 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d0cef862-0861-40d6-0ba2-08d931a9cffb X-MS-TrafficTypeDiagnostic: AM8P192MB1075: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EYT6fHNwiiSwVN3QjlZYUqnMG4/xjPoiFmcKBqAsDuJIOLNBiIAK/ttJ8T5JTzG7MB7xrL3paeHnS1+UO+Lc4K9TsHOY6+uoDh4hLnygW7SzMUEKJj71q0K5Dr/CjyI6JmLCGMbLgiqG36xlYTKCPvIQP8p8U70M6mlh3EXee30kQTZDZ35xIN+uGsRlSCiIlZAKjWzJMIJAqk+cIKd24XM4FRhPJksUompJCIHMfgCs8csy3MWAJh3X8oNClVC1405XHbiAuXc973OFxwefk80mAJSrk79/2VxPan0whlDbQQRRRC7xYBakjO7PwOjqeMfIh4xzYdpaYVNrP//DK01A801PPI424iXXNs7bv5aRX++4TKVEwtAcAv4hp0cf3mfB/cIz/4q7oFxuyBGpH9ghjmYMnUpLset3sd0s03Wh2dxEqqxdlIS6sFxC/eCl6HjIBdLFMRGklVYqrNAkkptI1oN/zifQCUFSundrO6x/wi/+0I7G7iC024izRQU8ZrP5iwxFeRcmqbFnRPXHdGumW//hlK0TJijN85UPfbGddjHRixGW/7yWVrEcAXqJgQ8z7jk0dQBrbEBMAR2gCFrN1rU/hLgZPOSoV6v2rr7+OcvUU4WxgYfB4ImbCCN9pJS/TDNYuDRx80it67oZbsVOuDxvEYXIwnRU2OIb6lmBUfpWLfLr0dETEG2+zDWzUYQwmfKOBgMSraPDzMcSVg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(66476007)(6512007)(8936002)(66556008)(38350700002)(6916009)(9686003)(66946007)(956004)(86362001)(26005)(5660300002)(2616005)(38100700002)(8676002)(6506007)(6666004)(4326008)(1076003)(55236004)(186003)(2906002)(83380400001)(498600001)(16526019)(54906003)(52116002)(36756003)(107886003)(6486002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cbQ4LyJfw7F/kRtUgtsXaOE3C5boJD6g77FfTO5FuM6XqdnBXVzd+kfL5hL2SLOAcFIrljKw+UAfCmfleaiEvtZ0NA0VPUAZL5fdgO1Bi0z91H8+2Jey72lrBd+BeH6goAdtwNlYJLOc2XbE8j6wOLVjiepIPTiJEBXwJTwJd7Y6MglQ2bQgIp0LRmhve/I2xAC2jSxwz7drX46gFmU15Oyd32vWob77GTlLYWMnW/xr/gEOEJcZjuxYez/464L/f/9PMC8MSiK/A7A2BWQP9CzQAqVAcHvczN92IayxghveQsLc14G9NPouvk2mumyLexPqealVDkD/TVvE8zrIR9F24kq/rcSygk065JkSlLhZ6YNS50WBkonrx/3k2CV/y/RwgoHLCQtnNBkdWZMCfHm3XHGq7j70IkYN+UAOcmqjtQ98qLkE1MUx/Wu2/lW10JQCQe3Ay3JRBcPj1p0I3FA+jhkvigqiDNT6fbHm7wq4Upa5yZXRMCqoZH2q9kwfVk3f0kLRCh3TeSpEz+7jTtyRLyvckm2dhwzPdqVf5e6a7Ier0bANvGf5Nd7vvCoCARfDkzMFoBHejQGblZDMPK7LS8lll8+iQcRo/BJRl9HK8PNs/G4uewGbz+QVWlD4E2bPC7BlEOxUU6FBdZKB3tW8O+/Jmzj4V1DT4ikXHB5BITeZV2z5f4NrwF4gDj2MTwCcbBh5pP/o402TpmFYeWwj0P4N9ZouABQQLvPw8i25gkMktH75Npjmz3Kr6EfNttzCO+z7fTCoBAVNWPdIXagFR6Sgu3Zf1+WePuEXrHnIcFCcG8CClmBRq9R7NpGelcP4dqhIRHD3zGuZEwKc7TJici41/+4dfy7654iIuBPh6rOJY0DGho1u619fvyJ8SUuo3e5hRiTyWkOQXgnYJSuAQxotETu8AwvokgUnBL+oM4aFHqGEUavIxPpM/Z8YQ3vIanOQU1QUFXUXRJm7II4jUvtwZqyEXjymtMz1Sd/1mga78R4AoI0FUzGqVE61shAjUmaoXskwAXgNmt4ITMJsRSeV6wGsHe4X+HrtaSgfBUfcj5/v6pPzdiHpYphP5q8EN423AHH2S0C/JYLUIgxvE+mkPFrx/pzeL9TnG438adWoyNtZCn+NIV05iN0i85mzphfxMGGlnKb7ZeNGT2UPk4Oq2cg6xtPR4IERfRm0fNqlv3KmCt6H19Q3paM9Jj8zG+gESgouNy4mw8AUnRIbCWXHLXlOfA5EiA69Hi3HJn6uyj/6RHTffIwxK9fNswXk4r+f8AVl5ym6GN9MI4RHM8AG9cSoKJqh1Cyg0FxFE2X0++DBgKFQZDXwUYPn X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0cef862-0861-40d6-0ba2-08d931a9cffb X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:06.0038 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VNBvQDhBIe7i5vnN74YFZgkJRBJMzmNp5gWxm52olI01sHWjx+PoYHD7OUTI0M2Y/D9NVZp3HFZwUOlXE3dt1g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1075 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/trace.h | 203 +++++++++++++++++++++++ 1 file changed, 203 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/trace.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/trace.h b/drivers/net/wireless/celeno/cl8k/trace.h new file mode 100644 index 000000000000..21b9927c0f99 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/trace.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM cl_trace + +#if !defined(_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_H + +#include + +/* Here, we need to include headers for definitions used in TP_PROTO */ +#include +#include +#include +#include "rx/rx.h" + +/* Add your tracepoint definitions here. */ +TRACE_EVENT(cl_trace_tx_start, + TP_PROTO(unsigned char cl_hw_idx, + struct sk_buff *skb, + int buffer_cnt), + TP_ARGS(cl_hw_idx, skb, buffer_cnt), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_tx_push, + TP_PROTO(unsigned char cl_hw_idx, + struct sk_buff *skb, + unsigned char packet_cnt, + unsigned short seq_ctrl, + unsigned char tid), + TP_ARGS(cl_hw_idx, skb, packet_cnt, seq_ctrl, tid), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_tx_pci_single_cfm_tasklet_start, + TP_PROTO(unsigned char cl_hw_idx, + unsigned int cfm_used_idx), + TP_ARGS(cl_hw_idx, cfm_used_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_tx_pci_single_cfm_tasklet_end, + TP_PROTO(unsigned char cl_hw_idx, + unsigned int cfm_used_idx), + TP_ARGS(cl_hw_idx, cfm_used_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_msg_rx_handler_start, + TP_PROTO(unsigned char cl_hw_idx, + unsigned short msg_id, + unsigned long msg_pattern, + unsigned long *cfm_flags), + TP_ARGS(cl_hw_idx, msg_id, msg_pattern, cfm_flags), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +) + +TRACE_EVENT(cl_trace_msg_rx_handler_end, + TP_PROTO(unsigned char cl_hw_idx, + unsigned long *cfm_flags), + TP_ARGS(cl_hw_idx, cfm_flags), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_msg_rx_tasklet_start, + TP_PROTO(unsigned char cl_hw_idx), + TP_ARGS(cl_hw_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_msg_rx_tasklet_end, + TP_PROTO(unsigned char cl_hw_idx, + int msg_handled), + TP_ARGS(cl_hw_idx, msg_handled), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_dbgfile_tasklet_start, + TP_PROTO(unsigned char cl_hw_idx), + TP_ARGS(cl_hw_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_dbgfile_tasklet_end, + TP_PROTO(unsigned char cl_hw_idx, + int dbg_handled), + TP_ARGS(cl_hw_idx, dbg_handled), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_tx_agg_cfm_tasklet_start, + TP_PROTO(unsigned char cl_hw_idx), + TP_ARGS(cl_hw_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_tx_agg_cfm_tasklet_end, + TP_PROTO(unsigned char cl_hw_idx, + int cfm_handled), + TP_ARGS(cl_hw_idx, cfm_handled), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_rx_desc_tasklet_start, + TP_PROTO(unsigned char cl_hw_idx, + unsigned int write_idx_rxm, + unsigned int write_idx_fw), + TP_ARGS(cl_hw_idx, write_idx_rxm, write_idx_fw), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_rx_desc_tasklet_end, + TP_PROTO(unsigned char cl_hw_idx, + unsigned int write_idx_rxm, + unsigned int write_idx_fw), + TP_ARGS(cl_hw_idx, write_idx_rxm, write_idx_fw), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_rx_tasklet_start, + TP_PROTO(unsigned char cl_hw_idx), + TP_ARGS(cl_hw_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_rx_tasklet_end, + TP_PROTO(unsigned char cl_hw_idx, + int handled), + TP_ARGS(cl_hw_idx, handled), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_netif_rx_start, + TP_PROTO(unsigned char cl_hw_idx), + TP_ARGS(cl_hw_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_netif_rx_end, + TP_PROTO(unsigned char cl_hw_idx), + TP_ARGS(cl_hw_idx), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +TRACE_EVENT(cl_trace_cl_msg_fw_send, + TP_PROTO(unsigned char cl_hw_idx, + int msg_id), + TP_ARGS(cl_hw_idx, msg_id), + TP_STRUCT__entry(), + TP_fast_assign(), + TP_printk("%d", 0) +); + +#endif /* !defined(_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) */ + +/* + * Without these two lines, the tracepoint will be searched + * for in include/trace/events, which is not what we desire. + */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE cl_trace + +#include From patchwork Thu Jun 17 16:01:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9E4DC49EA6 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 192/256] cl8k: add traffic.c Date: Thu, 17 Jun 2021 16:01:19 +0000 Message-Id: <20210617160223.160998-193-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:06 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bcc26f54-0ff0-44c3-e795-08d931a9d09d X-MS-TrafficTypeDiagnostic: AM8P192MB1075: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:112; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PLhs0kIv13hEBpiyw6QKl6YiaKpXqDBtIUJpNhqj7/4WB5I6uq7ofESZmjh0nbkI8jpqwXaTunPb3WKBRTQ0XGdfqtjheHCzr1scbUomSwgiTPokZ2g7ODhSnUzaZ7F5HxzNiGgGl0XU5KXMXG10HyBaWNBByLYpsBwMYmsRbSNr6hASWfPKqPY+WyBUkRP1qnaVtfT2drl2x/D7flgrwiIPPmvBSjwHB4bfylc2MAwDx+eSJ5f1rIDbA0RndLnCItyQlC25XSZNjQqosQU03wAVG25CIWexyrmJ8WPH3R/NYg+wRiLcHvzX+LCsFi2vYMf4fCNMsCUxlsRLnqIPR1J34+SRDB1teMy0x+4MpGLqog8ej3w66zrCmVviAooUwYCbAMB1pKLzgDWDVNl4k7DG7u7MOKjqOWranWA1E38JpnVBxsQVaEkP9NlAFFvmartUTsDeUp6609tgwClekNlMVNLGjMWg2ZkHLFxVWzTOjPxZmzWRp1UlTqvXAo/n039X9WTj+/xka2c8Z4Ecr6+3xfsBUCS0cTiYiQ0dfJj6FKrXLVvsI0iQM+VwRW/gUTj9O0rb2qtz8SUnS+7ONf8zJad3FFF0o9yX+PebwMRiz74oUg44dxm2ekA0JZXDq6/lJ/aPRu4Tc+mqqtw8HrUnM24TUh6n6gBExtbt2MMS9buRJ2hXR6tn3DPSnq+dNpuv3eJ0lRYls0EFUrymgQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(66476007)(6512007)(8936002)(66556008)(38350700002)(6916009)(9686003)(66946007)(956004)(86362001)(26005)(5660300002)(2616005)(38100700002)(8676002)(6506007)(6666004)(4326008)(1076003)(55236004)(186003)(30864003)(2906002)(83380400001)(498600001)(16526019)(54906003)(52116002)(36756003)(107886003)(6486002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UuJyDugEADN+aAyQqlKhDd/ZFqYEM/jPE7QXzbawMKRBE63b1t+KK+aXYC2YSm/4dA7hU2XfUmcmYBXHDnC8Pozbxz5qF6/myEHW/gRQ0nQgqZ/LnihOVub+pbdphBrQ1sN/2A9x4femC200aRLLt4iG7xv2owRYyKy/IKDUIKHMk+g3bQ1/M8+53qsMWkX1zNqVYj1GtjJuGQNsH4HNTgF+37L9yxzPPJHjO2b7LIMafrOZlCV//Ej+Yj+rjPf5X15K9mLusMylPzYHNrRpUoS8IUjqM+C4RW80ajrc0KvTRsyG3kffpyJKyqqEU+ycpNS2+xQkEeMg8sHMaVd8yPE0PFCdDslL+lRyCPLpLlGAt6cN4lhk85BIHJ+7vkcioZ9u1pT5fFNNrDuR569MfDp8/cOfw5yPvd6MYP+P4u2hlBG5FZMzGvAnPH1hyIRJZBD04ka6ypSHjfiuezZoX2maweSLHe+i4DCcvz0qqgfLORDfIdTBBMOJC71n+iFwKDVi2X1iXjD0K4ILnQo7SoV77K+yAKhaZCRhVl5444hcklu1AeRkce3xAoUMisP77VoPTTGMtStingJCsj3yL/Ln6PGk92GtuDbAGdrb4IWUWi0FGT1kJCeU8PtjiXMINrAsjuJSyyyRpF2tWp9VCECmBr5/hz/HsWwh9iPkS6QtJZo0LrgXV+yESblyWhE2fnZkUeJDJ5l3XevYoIsjL5RjNFVwC+7eEz1KSit11UeEkCe2Oa9MtleeV/bYyP0vXppJL42rHe6zN1luSpPdgvd4z55z8i0HQmVQpejIzlpTRR/4hyVubGdjCE76DwwC4wPZ4GxDa1dQ3KP62fDioAmwdIbLfXngZZTgWktoUVPazcp3ieKOI8RbN8b9CxiqxGeiwiOxRQ4QnB8xVVkCPUAlrDp5vhUWwINrwuRJrp1arHQnS5SqO/zdJYMWFid4Uqk2h0DpbwTwr3re95ctr2RZHksokZtwsbYVs05xcu+4yCm6+gm4lNYjIYBGi12LVMRft/JPuG77a2TmjhEQNSyzuueh/i43/02J2QZRR+9jneStwo0WSYsgmBXTyZhYGnrSthGWdhlYWem7NvGT/MEH2yphjXGtY2NpaLFT0dHLYhdtz4pe6sUrq8DVmylWRceo2hwLN+7rm8+Av77h9Ejjt+T5UpJ3TQUXF8mddpOMJq3Wz3YmQS0L9bKRf2gk21WgIHdHGT8mMx0xUjLyR+SWhYvfhIjNZsM9SZtJuasRVrPZKCzAbpZC/928ozG7sVFXYhq3mXNyDN3sUas8W7GQw5Rn1RnabaWrSKgOfJdC1erCQGHC1tGcOKUa1Y/3 X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcc26f54-0ff0-44c3-e795-08d931a9d09d X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:07.1099 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jrdnj4sKYk6s3oaGeGovpLn8cGrc1L+8BDfYapl6ll5gg59yoRJh+G24vx4UxVk5gjwPoiZ7ZokcJ70DhqObzQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1075 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/traffic.c | 315 +++++++++++++++++++++ 1 file changed, 315 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/traffic.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/traffic.c b/drivers/net/wireless/celeno/cl8k/traffic.c new file mode 100644 index 000000000000..19d91eb3e999 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/traffic.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "traffic.h" +#include "env_det.h" +#include "edca.h" +#include "bf.h" +#include "prot_mode.h" +#include "band.h" +#include "utils/utils.h" +#include "rsrc_mgmt.h" + +#define TRAFFIC_CNTR_ACTIVE_THR 3 /* 3 * 100ms = 300ms */ +#define TRAFFIC_CNTR_IDLE_THR 20 /* 20 * 100ms = 2sec */ + +/* Threshold in bytes */ +#define TRAFFIC_ACTIVE_THR_DRV 1920 /* = 150Kbit/sec (150 * 1024 / 8 / 10) */ +#define TRAFFIC_ACTIVE_THR_BF 26214 /* = 2mbit/sec (2 * 1024 * 1024 / 8 / 10) */ +#define TRAFFIC_ACTIVE_THR_EDCA_6G 2621440 /* = 200mbit/sec (200 * 1024 * 1024 / 8 / 10) */ +#define TRAFFIC_ACTIVE_THR_EDCA_5G 2621440 /* = 200mbit/sec (200 * 1024 * 1024 / 8 / 10) */ +#define TRAFFIC_ACTIVE_THR_EDCA_24G 655360 /* = 50mbit/sec (50 * 1024 * 1024 / 8 / 10) */ +#define TRAFFIC_ACTIVE_THR_DFS 13107 /* = 1mbit/sec (1 * 1024 * 1024 / 8 / 10) */ + +static const char *level_str[TRAFFIC_LEVEL_MAX] = { + [TRAFFIC_LEVEL_DRV] = "DRV", + [TRAFFIC_LEVEL_BF] = "BF", + [TRAFFIC_LEVEL_EDCA] = "EDCA", + [TRAFFIC_LEVEL_DFS] = "DFS" +}; + +static void cl_traffic_sta_start(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + enum cl_traffic_level level, enum cl_traffic_direction direction) +{ + cl_hw->traffic_db.num_active_sta_dir[direction][level]++; + + /* If other direction is not active increase num_active_sta */ + if (!cl_sta->traffic_db[1 - direction].activity_db[level].is_active) + cl_hw->traffic_db.num_active_sta[level]++; + + if (level == TRAFFIC_LEVEL_DRV) { + /* + * Dynamic CTS: + * If protection mode is disabled, environment is clean + * and station threshold was reached switch to CTS. + */ + if (cl_hw->traffic_db.num_active_sta[TRAFFIC_LEVEL_DRV] == + cl_hw->conf->ci_dyn_cts_sta_thr) + if (cl_env_det_is_clean(cl_hw) && + (cl_prot_mode_get(cl_hw) == TXL_NO_PROT)) { + cl_hw->traffic_db.dynamic_cts = true; + cl_prot_mode_set(cl_hw, TXL_PROT_CTS); + } + } else if (level == TRAFFIC_LEVEL_BF) { + if (direction == TRAFFIC_DIRECTION_TX) + cl_bf_sta_active(cl_hw, cl_sta, true); + } else if (level == TRAFFIC_LEVEL_EDCA) { + /* No action */ + } + + cl_rsrc_mgmt_traffic_start(cl_hw, level, direction); +} + +static void cl_traffic_sta_stop(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + enum cl_traffic_level level, enum cl_traffic_direction direction) +{ + cl_hw->traffic_db.num_active_sta_dir[direction][level]--; + + /* If other direction is not active decrease num_active_sta */ + if (!cl_sta->traffic_db[1 - direction].activity_db[level].is_active) + cl_hw->traffic_db.num_active_sta[level]--; + + if (level == TRAFFIC_LEVEL_DRV) { + /* + * Dynamic CTS: + * If it was turned on and active station count became lower than + * threshold --> return to no protection + */ + if (cl_hw->traffic_db.dynamic_cts) { + if (cl_hw->traffic_db.num_active_sta[TRAFFIC_LEVEL_DRV] == + (cl_hw->conf->ci_dyn_cts_sta_thr - 1)) { + cl_hw->traffic_db.dynamic_cts = false; + cl_prot_mode_set(cl_hw, TXL_NO_PROT); + } + } + } else if (level == TRAFFIC_LEVEL_BF) { + if (direction == TRAFFIC_DIRECTION_TX) + cl_bf_sta_active(cl_hw, cl_sta, false); + } else if (level == TRAFFIC_LEVEL_EDCA) { + /* No action */ + } + + cl_rsrc_mgmt_traffic_stop(cl_hw, level, direction); +} + +static void cl_traffic_check_activity(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + enum cl_traffic_level level, + enum cl_traffic_direction direction) +{ + struct cl_traffic_activity *activity_db = + &cl_sta->traffic_db[direction].activity_db[level]; + u32 num_bytes = cl_sta->traffic_db[direction].num_bytes; + + if (num_bytes > cl_hw->traffic_db.active_bytes_thr[level]) { + activity_db->cntr_active++; + activity_db->cntr_idle = 0; + + /* If traffic is above threshold for X consecutive times change state to active */ + if (!activity_db->is_active && + activity_db->cntr_active >= TRAFFIC_CNTR_ACTIVE_THR) { + activity_db->is_active = true; + cl_traffic_sta_start(cl_hw, cl_sta, level, direction); + } + } else { + activity_db->cntr_active = 0; + activity_db->cntr_idle++; + + /* If traffic is below threshold for Y consecutive times change state to idle */ + if (activity_db->is_active && activity_db->cntr_idle >= TRAFFIC_CNTR_IDLE_THR) { + activity_db->is_active = false; + cl_traffic_sta_stop(cl_hw, cl_sta, level, direction); + } + } +} + +static void cl_traffic_maintenance_sta(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + enum cl_traffic_level level = 0; + + /* Check Tx & Rx activity in all levels */ + for (level = 0; level < TRAFFIC_LEVEL_MAX; level++) { + cl_traffic_check_activity(cl_hw, cl_sta, level, TRAFFIC_DIRECTION_TX); + cl_traffic_check_activity(cl_hw, cl_sta, level, TRAFFIC_DIRECTION_RX); + } + + /* Reset num_bytes */ + cl_sta->traffic_db[TRAFFIC_DIRECTION_TX].num_bytes = 0; + cl_sta->traffic_db[TRAFFIC_DIRECTION_RX].num_bytes = 0; +} + +static int cl_traffic_print_state(struct cl_hw *cl_hw, + enum cl_traffic_level level) +{ + struct cl_sta *cl_sta = NULL; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + struct cl_traffic_main *db = &cl_hw->traffic_db; + + if (level >= TRAFFIC_LEVEL_MAX) { + cl_snprintf(&buf, &len, &buf_size, + "invalid level %d\n", level); + goto out; + } + + cl_snprintf(&buf, &len, &buf_size, + "Level %s (%d)\n", level_str[level], level); + cl_snprintf(&buf, &len, &buf_size, + "Active stations - %u\n", + db->num_active_sta[level]); + cl_snprintf(&buf, &len, &buf_size, + "Active stations TX - %u\n", + db->num_active_sta_dir[TRAFFIC_DIRECTION_TX][level]); + cl_snprintf(&buf, &len, &buf_size, + "Active stations RX - %u\n", + db->num_active_sta_dir[TRAFFIC_DIRECTION_RX][level]); + + if (db->num_active_sta[level] == 0) + goto out; + + cl_snprintf(&buf, &len, &buf_size, + "|---------------------|\n" + "|Sta|ActiveTx|ActiveRx|\n" + "|---------------------|\n"); + + /* Go over all stations */ + cl_sta_lock_bh(cl_hw); + + list_for_each_entry(cl_sta, &cl_hw->cl_sta_db.head, list) + cl_snprintf(&buf, &len, &buf_size, + "|%3u|%-8s|%-8s|\n", + cl_sta->sta_idx, + cl_sta->traffic_db[TRAFFIC_DIRECTION_TX].activity_db[level].is_active ? + "True" : "False", + cl_sta->traffic_db[TRAFFIC_DIRECTION_RX].activity_db[level].is_active ? + "True" : "False"); + + cl_sta_unlock_bh(cl_hw); + + cl_snprintf(&buf, &len, &buf_size, + "|---------------------|\n"); +out: + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static int cl_traffic_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "traffic usage:\n" + "-s : Print traffic state [0-drv/1-bf/2-edca/3-dfs]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +void cl_traffic_init(struct cl_hw *cl_hw) +{ + struct cl_traffic_main *traffic_db = &cl_hw->traffic_db; + + traffic_db->active_bytes_thr[TRAFFIC_LEVEL_DRV] = TRAFFIC_ACTIVE_THR_DRV; + traffic_db->active_bytes_thr[TRAFFIC_LEVEL_BF] = TRAFFIC_ACTIVE_THR_BF; + + if (cl_band_is_6g(cl_hw)) + traffic_db->active_bytes_thr[TRAFFIC_LEVEL_EDCA] = TRAFFIC_ACTIVE_THR_EDCA_6G; + else if (cl_band_is_5g(cl_hw)) + traffic_db->active_bytes_thr[TRAFFIC_LEVEL_EDCA] = TRAFFIC_ACTIVE_THR_EDCA_5G; + else + traffic_db->active_bytes_thr[TRAFFIC_LEVEL_EDCA] = TRAFFIC_ACTIVE_THR_EDCA_24G; + + traffic_db->active_bytes_thr[TRAFFIC_LEVEL_DFS] = TRAFFIC_ACTIVE_THR_DFS; +} + +void cl_traffic_tx_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u32 num_bytes) +{ + cl_sta->traffic_db[TRAFFIC_DIRECTION_TX].num_bytes += num_bytes; +} + +void cl_traffic_rx_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u32 num_bytes) +{ + cl_sta->traffic_db[TRAFFIC_DIRECTION_RX].num_bytes += num_bytes; +} + +void cl_traffic_maintenance(struct cl_hw *cl_hw) +{ + cl_sta_loop(cl_hw, cl_traffic_maintenance_sta); +} + +void cl_traffic_sta_remove(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + /* Check if station disconnected during traffic */ + enum cl_traffic_level level = 0; + enum cl_traffic_direction direction = 0; + + for (direction = 0; direction < TRAFFIC_DIRECTION_MAX; direction++) { + for (level = 0; level < TRAFFIC_LEVEL_MAX; level++) { + if (cl_sta->traffic_db[direction].activity_db[level].is_active) + cl_traffic_sta_stop(cl_hw, cl_sta, level, direction); + } + + memset(&cl_sta->traffic_db, 0, sizeof(cl_sta->traffic_db)); + } +} + +bool cl_traffic_is_sta_active(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + return (cl_sta->traffic_db[TRAFFIC_DIRECTION_TX].activity_db[TRAFFIC_LEVEL_DRV].is_active || + cl_sta->traffic_db[TRAFFIC_DIRECTION_RX].activity_db[TRAFFIC_LEVEL_DRV].is_active); +} + +bool cl_traffic_is_sta_active_tx(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + return cl_sta->traffic_db[TRAFFIC_DIRECTION_TX].activity_db[TRAFFIC_LEVEL_DRV].is_active; +} + +u32 cl_traffic_num_active_sta(struct cl_hw *cl_hw) +{ + return cl_hw->traffic_db.num_active_sta[TRAFFIC_LEVEL_DRV]; +} + +u32 cl_traffic_num_active_dfs(struct cl_hw *cl_hw) +{ + return cl_hw->traffic_db.num_active_sta[TRAFFIC_LEVEL_DFS]; +} + +int cl_traffic_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + bool print_state = false; + int expected_params = -1; + + switch (cli_params->option) { + case 's': + print_state = true; + expected_params = 1; + break; + case '?': + return cl_traffic_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (print_state) + return cl_traffic_print_state(cl_hw, + (u8)(cli_params->params[0])); + +out_err: + return -EIO; +} From patchwork Thu Jun 17 16:01:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB69FC49361 for ; Thu, 17 Jun 2021 16:08:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B112661407 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 193/256] cl8k: add traffic.h Date: Thu, 17 Jun 2021 16:01:20 +0000 Message-Id: <20210617160223.160998-194-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:07 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d558f8b1-dffa-49b9-182d-08d931a9d14b X-MS-TrafficTypeDiagnostic: AM8P192MB1075: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Aey13Z4axxsJ2aFoEh5V6dSAl5hJWYEHX1lwX6VKLsKvz8g9TgjhODZokA3vtvt/54gIMKKcJD9dw3VTfHnjdH9+2QZCpa8bXJQZnWTvm6TQZu8a6G8lVSLJ8i+LQNwOL0Jx3dArlmEdDSCzsqdNnELUBnaBZ2n9NmSebYlYgaAtURjvzLy2oBLBXXhS+Z1LegyYt7IlHYh6B1LZQ6NqWN2YrYKSKrOEiT3xTWnR4+tWfgV81mtpMemk9wwCBzejPSRplHSXsLWasbZK2BBQ/X8f/HRo+Fs2N0zlTht6VsHLJkW/Y8rc2gn0GrEI0QvsRVA0KK2m1R2UedkkuQqGWAGQlbhgG3j6LaLqYrvWV+eHpXY8fnibBVmrbQQCE94DPuEtSWeY073VW3y2RowuQXb8PxHm/k2FcFeTbJAv4ZQn9rpbbTCh2BTCFnAEmbxsVH+NHHVPPOLcas8QtCmAHaztHzLCi3UMXiT5HbbmY58RVO9E01rTSp4L56AJ0xfumExWSCMBK2ZKN28LOnhRpdBHVVtIIH8iFBPpr5x8d/P8bvdURUKcnVFr0CWljMOVSWSQTCEzdIhcJCNmwT924lA0GvBuR4pnXD8cqrqbecv0grs2x6BoNYIYHrFG3BLA+t9SObAUtWTAfGMF8IBxuuCcoJ9ahBGhcrGKk40LXb7hTq17Bvv3v9v4W5PpwKX8UVhaRrzQKg+Ier8DpWKXVw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(66476007)(6512007)(8936002)(66556008)(38350700002)(6916009)(9686003)(66946007)(956004)(86362001)(26005)(5660300002)(2616005)(38100700002)(8676002)(6506007)(6666004)(4326008)(1076003)(55236004)(186003)(2906002)(83380400001)(498600001)(16526019)(54906003)(52116002)(36756003)(107886003)(6486002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j+1opkwrmBF+lGwWNrMLC66+qlcSbN3q6kjgK4ks//BAbY1lMnNY4qbgsLd8FwlGtogdImMjZLfpxk+MVgs/5jS3gPz+4c7GWV7OiBzCmKzRVq3hQ29dXAoMiJ8oFDoGm1kWOc7aEUyWDuCibRWDV+4mEh1wJtRP7+QIMWQcX2SfswLyBT4ldscCQvixSrx+6qE4Xro1VcEfRfxBN1MPnOzinEceFAQp5lTgtV50Wjy2OxKOaa/6wMXIO9cyclglePXbJDq3sBZxqZXe4nVGZgIq+8SrRSOwv7jiFY5r9lCQWgEydL32QwJEri5vISdAaK2mnkDmeQIMZ8YCVVacFwLUOKOfx4RjkZSg8FZBsfqW3pdLagwoMnmgb8qtX9r2HTZi66Tpx7/OHRDRTulQ2AMQUHaNGEj+Pj/h4WcfqFa7heejB4AAKtYO2v2btB/rzVhFaFWp23Z+MV1EdO5CLonZ0eCR6XPh4XnBNQ6UB94q4UCnkcF8kPzRQslzcUpTkwMwF1g482s+uy3LTGzqBuxcfyK2bkq2Fl6c/JB91+3KOJglXtFOSwofbhJLbNZmoXwNAL1DA/NtEzQqr8z6wCU6mGYlvgF8A8XOMxy+IJ+4d4BoKT/uTb1Bwy8uLLWBvalxcvnCxxVYIOknfwCGmvT6TAEd1aU4KIQKKgY83yLjWh6BZ1kz9Iett9GRpLugagzu9XSCxFEiPgpwMaDp71mefLsp1w7xSSd19TBWEBUjqn+Uiik0ZKUfSZwpQf+3vt7qLV+icbRSXTG6DwiqFymYrQxZin7wcdyc8+RKrzVYunkqsapGsAJh/c3ptAr1SqJ2fFEcmvqOM3Dv6cvrUo4b/o73YUI1MzrLSVJsS/rTRsOAdoQ+3o/a/6ncqEOTQ76m6otUpaXEj5totmosvUrIkg9LlFiv6vjLn55Zn9ONBs0cbsuS0toSeFSLqFWBbppO8/495b/ioT6d1INmU6ondQzBmCP+q5GxdpCjC1/Xv8mazbunbdQkuhfQX1WKOtouIJ+xa6Duy6pnUcTCrUNMdZ/55AJ2JoNdTU+SN2QApyjmR4DxsWAgYbK4UwPe30wO+7vkqiRytDJu7ufU0gG/IVa8Nwj+0jkMO8krbhDBVwjygIV86RDldedB5zgjVwb1t/4XOocNWSK8qIccJHz1zTElrZHT7wuQjHunFqAV5/HMmylaXvDcYrDIaa5jpN7PuMhG2RKE4LZwQP2TNK2Not0NLJqrGrVonnETI6c1iT7vDg6M62kQI/RfrNlWc5GK+Ow0kqEDIPEcFwcDxprkQXRt7xKK1ClBO7jFpTkjVIro447orZz94wgVkjVN X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: d558f8b1-dffa-49b9-182d-08d931a9d14b X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:08.1643 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: d1/StEQw361vqB0oE6OT+MGzs5X8iWb3hPMpeN7bYVfTz0DDZB38M3kFt15TH4C6gKiSfI1K1zawUjU1XUxbyg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1075 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/traffic.h | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/traffic.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/traffic.h b/drivers/net/wireless/celeno/cl8k/traffic.h new file mode 100644 index 000000000000..810bec60647d --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/traffic.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TRAFFIC_H +#define CL_TRAFFIC_H + +#include "vendor_cmd.h" + +enum cl_traffic_direction { + TRAFFIC_DIRECTION_TX, + TRAFFIC_DIRECTION_RX, + + TRAFFIC_DIRECTION_MAX +}; + +enum cl_traffic_level { + TRAFFIC_LEVEL_DRV, + TRAFFIC_LEVEL_BF, + TRAFFIC_LEVEL_EDCA, + TRAFFIC_LEVEL_DFS, + + TRAFFIC_LEVEL_MAX +}; + +struct cl_traffic_activity { + u8 cntr_active; + u8 cntr_idle; + bool is_active; +}; + +struct cl_traffic_sta { + struct cl_traffic_activity activity_db[TRAFFIC_LEVEL_MAX]; + u32 num_bytes; +}; + +struct cl_traffic_main { + u32 num_active_sta[TRAFFIC_LEVEL_MAX]; + u32 num_active_sta_dir[TRAFFIC_DIRECTION_MAX][TRAFFIC_LEVEL_MAX]; + u32 active_bytes_thr[TRAFFIC_LEVEL_MAX]; + bool dynamic_cts; +}; + +struct cl_hw; +struct cl_sta; + +void cl_traffic_init(struct cl_hw *cl_hw); +void cl_traffic_tx_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u32 num_bytes); +void cl_traffic_rx_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u32 num_bytes); +void cl_traffic_maintenance(struct cl_hw *cl_hw); +void cl_traffic_sta_remove(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +bool cl_traffic_is_sta_active(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +bool cl_traffic_is_sta_active_tx(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +u32 cl_traffic_num_active_sta(struct cl_hw *cl_hw); +u32 cl_traffic_num_active_dfs(struct cl_hw *cl_hw); +int cl_traffic_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_TRAFFIC_H */ From patchwork Thu Jun 17 16:01:23 2021 Content-Type: text/plain; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 196/256] cl8k: add twt_cli.c Date: Thu, 17 Jun 2021 16:01:23 +0000 Message-Id: <20210617160223.160998-197-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:10 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2cdf8d0b-3578-4184-36e3-08d931a9d327 X-MS-TrafficTypeDiagnostic: AM8P192MB1075: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:510; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: u+E5Qijf6MS+qZvHFIDL7uVBfzYcebi9tqQM/blaTjH2AsZz/XYi41gx/4JzeBImdNi4AXyU2t99FQghMP5u3EM44ZYODk7291UR/O8z/7bZP9xBIxpSSd4OCBn28Eb4f/ueFMY0Z9z2z1WTRmZLzSqGGoyLz5zLeEvyJFGystLtS27Hgd7yK2FeonxTrIUghDcLPAGkgo5BoJbEUFRED2VKwQznLKHdSGne+rgUeD1HwaU25hl1w/6XMUVbLWpz3QA2+0/I0xJMvNHe2YYogvFFxs/b0VkmKgCjmszLRx2dfAEqEH7xN/uu143tqcyrqWHzAWTN2jcQbnvr79GXwPCk3HkTxTp5YZrz7geEsZs9K8d304d/LHlhisfUqKvMzATx6UiDsLoFdx0qqdMKZRxMzwxThkM+UJ4q8PCD+CAvrWlwEhAxuD8n3+6vxneIGhZLQUgY0kp9jBJ/PoejK0KqeByWqaejJSg3+rX6BSuGJskBKgQHtue/1kbN1r0tMfQZODzqnSgocvK5IFHyo2qyKL8ClUEXtk/KjiH52/qv/qD68CujjvhMg6/QEFG4Ljse3noJk9ePq/XEEQx/z+jRSeKyXO75CSTT6iXzmjDjhPXapcMM0PLMRDvc2RPEAzYIyNPCtzUI+auFxXQYWIlDGR9/zAaq1/PwHqr9WaGjRQoYwNdNYrxkr9oGoT+VipPd26gir057X9QNRBX1zw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(66476007)(6512007)(8936002)(66556008)(38350700002)(6916009)(9686003)(66946007)(956004)(86362001)(26005)(5660300002)(2616005)(38100700002)(8676002)(6506007)(6666004)(4326008)(1076003)(55236004)(186003)(30864003)(2906002)(83380400001)(498600001)(16526019)(54906003)(52116002)(36756003)(107886003)(6486002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EVgcpVC8R8djx2PuVtb2gdtbBvAAIssT9yDZwE9wsT1kAuj/EEiGi6ulbqTKcITI6+v9P5eGv/Sk4VQfQD3srFvGTe7rbskJc/MGDuontd7hALx2Av93ghV/fijUfZkkm2+GiC5TFtjpzv2UNL6ih3F+E0QV7srOrolflmN3Yzpzq1T4bMzGtQNU0RGlBdv4zKWV04G8XZW/y4LlVRGs//APx0dQ6Xtlt6qGiywerUvRKSZe60iCffsYb4LfmLCtIgmo2CWAubWSw/8LDA63OGU+WyB/0v9fRlyfoQwdygtKm6+L+wK+ikCRDsNNtygQvfZ/pt5c5Pk/+6sE1HfzDZyrpAdEvypQ52YUIj22Q1IH8kFIPKlfZ53mj3rbFTaVxQL8htNXAcfxnBB+Ac8XlvPvPvg4PsSdmuBKeLkuwNM5GDU5H2JnqaZsan0aGcG9aJyV7gXM7G6ic9USk/M1N+DdFQltkbtoc1zWVom16Tkf9Lm5xVKt2G+2ktu1Yqp96QUBrcz3ks3fsPcvZUsvuhxnFmSVQH7XuaxQcxSgtKIWrS2Iml91MYf9DJBjsf/juSb4TyX7imdY2vQajHmq0QGMkMcpS7uFCcdWTv3Ni9zBX5271j1LyMK3w4ZVv9zWa7KckDwZbHfCU/ar1U7xIvFm43+5RIeRJUSDYiJ8744Ee96qLRr9xizSYC3xFNKBaDXxL9g7j2tVff9yGv4w8nJF2s80+fQTqv0PkVC9vCUEKsazD/9gnNZw4VvUnt+m5TRxOcdF70C42rbRmrP4vrgJQJe4rojAqf3NAVdhNSHuUvfQw6l78SPkPyqGJ61H/ML5v73tH/YqRE4ISS6QheZsVcLMty7V1lbPqB0gnGAmyzfNxFdYMZCTBKpZqYCatigW62l+LcvcKwJ2kLa3Nf7txrigg472musUOSEFH3fgYS3V5rEwxly8QJw3Es4a4Uel3mrSgUWIhpSDd3IssT7yKjJQQGgXzNyqwlFsB5HeZ1k1T6jsn0ofu9FyZXkg7xhyYMBZtrt/1rTWdMLWiQA5nnBOUunldN3Kd+os2UgtscQkSSLpj96OQOScAsAg6w7oDtt75C7ShFX7nxKLQW7gcwMiJ/8USYTOP4KqbQzCPc8mmeLWPInkjDVGCz9LsqbTMi4NrG8xiLEWXZLzxMm1zCGWymLc6sSsmpGbjVFzgI6KfdvDcDYxyQtMBuxVusQoVoa4OgryU/u9lFEEr6pUPqcn1uznoSzJUMpbPVbINKO/2F2gccnDd5zZiCaauznRHXdUPTct64XFsIGqJYYAlc9WrLVm0I5o9pYWB8GXc63sf/2sanfgDepc/rbj X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2cdf8d0b-3578-4184-36e3-08d931a9d327 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:11.3802 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1SNgtpKFH8GpnXzNFlYmAMwIX1VQNdm6ME/0sTWnu89nzYqdbc8t4kqyQxw28O/whh9t63iEn6doFfhjPqm9hg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1075 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/twt_cli.c | 359 +++++++++++++++++++++ 1 file changed, 359 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/twt_cli.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/twt_cli.c b/drivers/net/wireless/celeno/cl8k/twt_cli.c new file mode 100644 index 000000000000..258df0c83c48 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/twt_cli.c @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "twt_cli.h" +#include "twt.h" +#include "twt_frame.h" +#include "sta.h" +#include "utils/utils.h" + +#define CL_TWT_MIN_WAKE_DURATION_MAX_VAL_US (0xFFU << 10) + +static int cl_twt_cli_configuration_print(struct cl_hw *cl_hw) +{ + struct cl_tcv_conf *conf = cl_hw->conf; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "TWT configuration:\n"); + cl_snprintf(&buf, &len, &buf_size, + "TWT enabled: %u\n", + conf->ce_twt_en); + cl_snprintf(&buf, &len, &buf_size, + "TWT default interval: %u\n", + conf->ce_twt_default_interval); + cl_snprintf(&buf, &len, &buf_size, + "TWT default min wake duration: %u\n", + conf->ce_twt_default_min_wake_duration); + cl_snprintf(&buf, &len, &buf_size, + "TWT num of sessions: %u\n", + cl_hw->twt_db.num_sessions); + cl_snprintf(&buf, &len, &buf_size, + "TWT max sessions: %u\n", + conf->ce_twt_max_sessions); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_twt_cli_sessions_print(struct cl_hw *cl_hw) +{ + u8 i, handled_sessions = 0, num_sessions = cl_hw->twt_db.num_sessions; + u8 max_sessions = cl_hw->conf->ce_twt_max_sessions; + struct cl_twt_session_db *session; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "-----------------------------------------------------" + "---------------------------------\n" + "| STA idx | Flow id | Announced | Triggered | " + "Interval us | Min wake | Start time |\n" + "| | | | | " + " | duration us | |\n"); + for (i = 0, session = &cl_hw->twt_db.cl_twt_sessions[0]; + (i < max_sessions) && (handled_sessions < num_sessions); + i++, session++) { + if (!session->cl_sta) + continue; + + cl_snprintf(&buf, &len, &buf_size, + "+---------+---------+-----------+-----------+" + "-------------+-------------+------------+\n" + "| %3u | %1u | %1u | %1u" + " | %10llu | %6u | %10llu |\n", + session->cl_sta->sta_idx, + session->twt_setup.req_type.fields.flow_id, + !(session->twt_setup.req_type.fields.flow_type), + session->twt_setup.req_type.fields.trigger, + cl_twt_get_wake_interval_us(&session->twt_setup), + cl_twt_get_min_wake_time_us(&session->twt_setup), + session->twt_setup.target_wake_time); + handled_sessions++; + } + + cl_snprintf(&buf, &len, &buf_size, + "-----------------------------------------------------" + "---------------------------------\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_twt_cli_send_individual_setup_request(struct cl_hw *cl_hw, + struct cli_params *cli_params, + bool simulate) +{ + u8 sta_idx = (u8)cli_params->params[0]; + u8 setup_cmd = (u8)cli_params->params[1]; + u8 flow_id = (u8)cli_params->params[2]; + bool announced = (bool)cli_params->params[3]; + bool triggered = (bool)cli_params->params[4]; + u32 interval = (u32)cli_params->params[5]; + u32 min_wake_dur = (u32)cli_params->params[6]; + struct cl_sta *cl_sta; + int res = -1; + + if (!cl_twt_is_enabled(cl_hw)) { + cl_dbg_verbose(cl_hw, "Please enable TWT first\n"); + return -1; + } + + cl_sta_lock_bh(cl_hw); + cl_sta = cl_sta_get(cl_hw, sta_idx); + + if (!cl_sta) { + cl_dbg_err(cl_hw, "Invalid sta idx %u\n", sta_idx); + goto out; + } + + if (setup_cmd > IEEE80211_TWT_SETUP_COMMAND_DEMAND) { + cl_dbg_verbose(cl_hw, + "Invalid setup cmd %u. Must be lower than %u\n", + setup_cmd, IEEE80211_TWT_SETUP_COMMAND_DEMAND); + goto out; + } + + if (flow_id > CL_TWT_FLOW_ID_MAX) { + cl_dbg_verbose(cl_hw, + "Invalid flow id %u. Must be lower than %u\n", + flow_id, CL_TWT_FLOW_ID_MAX); + goto out; + } + + if (min_wake_dur > CL_TWT_MIN_WAKE_DURATION_MAX_VAL_US) { + cl_dbg_verbose(cl_hw, + "Invalid min wake duration (%u). Must be no greater than %u\n", + min_wake_dur, CL_TWT_MIN_WAKE_DURATION_MAX_VAL_US); + goto out; + } + + if (min_wake_dur > interval) { + cl_dbg_verbose(cl_hw, + "Min wake duration (%u) cannot be greater than interval (%u)\n", + min_wake_dur, interval); + goto out; + } + + cl_dbg_info(cl_hw, + "sta_idx %u, setup_cmd %u, flow_id %u, announced %u, " + "triggered %u, interval %u, min wake duration %u\n", + sta_idx, setup_cmd, flow_id, announced, triggered, interval, min_wake_dur); + + if (simulate) + res = cl_twt_frame_simulate_individual_setup_request(cl_hw, cl_sta, + setup_cmd, flow_id, + announced, triggered, + (u64)interval, min_wake_dur); + else + res = cl_twt_frame_send_individual_setup_request(cl_hw, cl_sta, setup_cmd, + flow_id, announced, triggered, + (u64)interval, min_wake_dur); + +out: + cl_sta_unlock_bh(cl_hw); + + return res; +} + +static int cl_twt_cli_send_individual_teardown_request(struct cl_hw *cl_hw, + struct cli_params *cli_params, + bool simulate) +{ + u8 sta_idx = (u8)cli_params->params[0]; + u8 flow_id = (u8)cli_params->params[1]; + struct cl_sta *cl_sta; + int res = 0; + + if (!cl_twt_is_enabled(cl_hw)) { + cl_dbg_verbose(cl_hw, "Please enable TWT first\n"); + return -1; + } + + cl_sta_lock_bh(cl_hw); + cl_sta = cl_sta_get(cl_hw, sta_idx); + + if (!cl_sta) { + cl_dbg_err(cl_hw, "Invalid sta idx %u\n", sta_idx); + res = -1; + goto out; + } + + if (flow_id > CL_TWT_FLOW_ID_MAX && flow_id != CL_TWT_FLOW_ID_ALL) { + cl_dbg_verbose(cl_hw, + "Invalid flow id %u. Must be lower than %u or %u\n", + flow_id, CL_TWT_FLOW_ID_MAX, CL_TWT_FLOW_ID_ALL); + res = -1; + goto out; + } + + if (simulate) { + res = cl_twt_frame_simulate_individual_teardown_request(cl_hw, cl_sta, flow_id); + } else { + /* + * If the session doesn't exist or couldn't be removed - + * send a teardown request anyway + */ + if (cl_twt_teardown_individual_sesseion(cl_hw, cl_sta, flow_id, true)) + cl_twt_frame_send_individual_teardown_request(cl_hw, cl_sta, flow_id); + } + +out: + cl_sta_unlock_bh(cl_hw); + + return res; +} + +static void cl_twt_cli_enable(struct cl_hw *cl_hw, bool enable) +{ + if (cl_hw->conf->ce_twt_en == enable) { + pr_debug("TWT is already %s\n", enable ? "enabled" : "disabled"); + return; + } + + cl_hw->conf->ce_twt_en = enable; + + if (enable) + cl_twt_init(cl_hw); + else + cl_twt_close(cl_hw); + + pr_debug("TWT has been %s\n", (enable ? "enabled" : "disabled")); +} + +static int cl_twt_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "twt usage\n" + "-c: Print configuration\n" + "-e: Enable/Disable TWT [0 - disable, 1 - enable]\n" + "-m: Simulate a reception of a TWT individual request:\n" + "\t[sta_idx].[setup_cmd (0:request, 1:suggest, " + "2:demand)].[flow_id (0-7))].[announced].[triggered]." + "[interval].[min_wake_duration]\n" + "-n: Simulate a reception of a TWT individual teardown " + "request:\n\t[sta_idx].[flow_id (0-7; 255 all_twt)]\n" + "-p: Print sessions\n" + "-s: Send a TWT individual setup request:\n" + "\t[sta_idx].[setup_cmd (0:request, 1:suggest, " + "2:demand)].[flow_id (0-7))].[announced].[triggered]." + "[interval].[min_wake_duration]\n" + "-t: Send a TWT individual teardown request:\n" + "\t[sta_idx].[flow_id (0-7; 255 for all_twt)]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +int cl_twt_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + u32 expected_params = 0; + bool print_conf = false; + bool enable = false; + bool simulate_req = false; + bool simulate_teardown = false; + bool print_sessions = false; + bool send_req = false; + bool send_teardown = false; + + switch (cli_params->option) { + case 'c': + print_conf = true; + expected_params = 0; + break; + case 'e': + enable = true; + expected_params = 1; + break; + case 'm': + simulate_req = true; + expected_params = 7; + break; + case 'n': + simulate_teardown = true; + expected_params = 2; + break; + case 'p': + print_sessions = true; + expected_params = 0; + break; + case 's': + send_req = true; + expected_params = 7; + break; + case 't': + send_teardown = true; + expected_params = 2; + break; + case '?': + return cl_twt_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (print_conf) + return cl_twt_cli_configuration_print(cl_hw); + + if (enable) { + cl_twt_cli_enable(cl_hw, (bool)cli_params->params[0]); + return 0; + } + + if (simulate_req) { + int res = cl_twt_cli_send_individual_setup_request(cl_hw, cli_params, true); + + if (res) + cl_dbg_verbose(cl_hw, "Error %d trying to simulate TWT request\n", res); + + return 0; + } + + if (simulate_teardown) { + cl_twt_cli_send_individual_teardown_request(cl_hw, cli_params, true); + return 0; + } + + if (print_sessions) + return cl_twt_cli_sessions_print(cl_hw); + + if (send_req) { + int res = cl_twt_cli_send_individual_setup_request(cl_hw, cli_params, false); + + if (res) + cl_dbg_verbose(cl_hw, "Error %d trying to send TWT request\n", res); + + return 0; + } + + if (send_teardown) { + cl_twt_cli_send_individual_teardown_request(cl_hw, cli_params, false); + return 0; + } + +out_err: + return -EIO; +} From patchwork Thu Jun 17 16:01:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5725C48BE5 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/twt_frame.h | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/twt_frame.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/twt_frame.h b/drivers/net/wireless/celeno/cl8k/twt_frame.h new file mode 100644 index 000000000000..92d462caba6f --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/twt_frame.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TWT_FRAME_H +#define CL_TWT_FRAME_H + +#include "hw.h" +#include "mac80211.h" + +bool cl_twt_frame_is_individual_setup_request_valid(struct cl_hw *cl_hw, + struct cl_ieee80211_mgmt *request); +int cl_twt_frame_send_individual_setup_response(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + struct cl_ieee80211_mgmt *request, + struct cl_twt_session_db **session); +int cl_twt_frame_send_individual_setup_request(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + enum ieee80211_twt_setup_command setup_cmd, + u8 flow_id, + bool announced, + bool triggered, + u64 interval_us, + u32 min_wake_duration_us); +int cl_twt_frame_simulate_individual_setup_request(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + enum ieee80211_twt_setup_command setup_cmd, + u8 flow_id, + bool announced, + bool triggered, + u64 interval_us, + u32 min_wake_duration_us); +int cl_twt_frame_send_individual_teardown_request(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + u8 flow_id); +int cl_twt_frame_simulate_individual_teardown_request(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + u8 flow_id); + +#endif /* CL_TWT_FRAME_H */ From patchwork Thu Jun 17 16:01:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72636C2B9F4 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../wireless/celeno/cl8k/tx/agg_tx_report.c | 196 ++++++++++++++++++ 1 file changed, 196 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/agg_tx_report.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/agg_tx_report.c b/drivers/net/wireless/celeno/cl8k/tx/agg_tx_report.c new file mode 100644 index 000000000000..478e5e734f08 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/agg_tx_report.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "tx/agg_tx_report.h" +#include "stats.h" +#include "rate_ctrl.h" +#include "wrs/wrs_api.h" +#include "data_rates.h" + +static bool is_same_rate(struct cl_agg_tx_report *agg_report, struct cl_wrs_tx_params *tx_params) +{ + union cl_rate_ctrl_info rate_ctrl_info = {.word = agg_report->rate_cntrl_info}; + u8 mcs = U8_MAX, nss = U8_MAX; + + if (agg_report->bw_requested != tx_params->bw || + rate_ctrl_info.field.gi != tx_params->gi) + return false; + + cl_rate_ctrl_parse(&rate_ctrl_info, &nss, &mcs); + + return ((mcs == tx_params->mcs) && (nss == tx_params->nss)); +} + +static void sync_tx_rate(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report, + struct cl_wrs_info *wrs_info, struct cl_wrs_params *wrs_params) +{ + if (!agg_report->is_fallback && is_same_rate(agg_report, &wrs_params->tx_params)) { + cl_wrs_api_rate_sync(cl_hw, cl_sta, wrs_params); + + wrs_info->synced = true; + wrs_info->quick_rate_check = true; + wrs_info->quick_rate_agg_cntr = 0; + wrs_info->quick_rate_pkt_cntr = 0; + } else { + wrs_info->sync_attempts++; + } +} + +static void ba_not_received_handler(struct cl_hw *cl_hw, struct cl_wrs_info *wrs_info, + struct cl_agg_tx_report *agg_report) +{ + /* Ignore 'BA not received' if station is in power-save or if RTS limit was reached */ + if (agg_report->is_sta_ps || agg_report->is_rts_retry_limit_reached) + return; + + /* Count number of consecutive 'BA not received' */ + wrs_info->ba_not_rcv_consecutive++; + + /* Save longest sequence of consecutive 'BA not received' */ + if (wrs_info->ba_not_rcv_consecutive > wrs_info->ba_not_rcv_consecutive_max) + wrs_info->ba_not_rcv_consecutive_max = wrs_info->ba_not_rcv_consecutive; + + if (cl_hw->wrs_db.ba_not_rcv_collision_filter) { + /* + * First 'BA not received' - might just be a collision. + * Don't add fail to ba_not_rcv but keep aside. + * Second consecutive 'BA not received' - not likely to be a collisions. + * Add fail to ba_not_rcv including previous fail that was kept aside. + * More than two consecutive 'BA not received' - very unlikely to be a collisions. + * Add fail to ba_not_rcv. + */ + if (wrs_info->ba_not_rcv_consecutive == 1) + wrs_info->tx_fail_prev = agg_report->fail; + else if (wrs_info->ba_not_rcv_consecutive == 2) + wrs_info->ba_not_rcv += (agg_report->fail + wrs_info->tx_fail_prev); + else + wrs_info->ba_not_rcv += agg_report->fail; + } else { + wrs_info->ba_not_rcv += agg_report->fail; + } +} + +void cl_agg_tx_report_handler(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_agg_tx_report *agg_report) +{ + struct cl_wrs_info *wrs_info = &cl_sta->wrs_info; + struct cl_wrs_params *wrs_params = &cl_sta->wrs_sta.su_params; + bool skip_epr_update = false; + union cl_rate_ctrl_info rate_ctrl_info = {.word = agg_report->rate_cntrl_info}; + + /* Retry_count for cl_wlan */ + cl_sta->retry_count += agg_report->success_after_retry; + + /* + * In case of big packets (4300 in VHT and 5400 in HE) and low + * rate (BW 20, NSS 1, MCS 0), firmware will increase rate to MCS 1, + * and give an indication to driver (set rate_fix_mcs1 in cl_agg_tx_report). + * WRS should also move to MCS 1, and give the maximum time + * penalty time from MCS 0 toMCS 1. + */ + if (agg_report->rate_fix_mcs1 && !agg_report->is_fallback) + if (cl_wrs_api_up_mcs1(cl_hw, cl_sta, wrs_params)) + return; + + /* WRS sync mechanism */ + if (!wrs_info->synced) + sync_tx_rate(cl_hw, cl_sta, agg_report, wrs_info, wrs_params); + + if (agg_report->bf && cl_sta->bf_db.is_on && !cl_sta->bf_db.synced) { + cl_sta->bf_db.synced = true; + /* Resetting the WRS UP weights */ + cl_wrs_api_beamforming_sync(cl_hw, cl_sta); + } + + if (agg_report->ba_not_received) { + ba_not_received_handler(cl_hw, wrs_info, agg_report); + } else { + if (!skip_epr_update) + wrs_info->tx_fail += agg_report->fail; + + wrs_info->ba_not_rcv_consecutive = 0; + } + + if (!skip_epr_update) { + u8 mcs = 0, nss = 0, bw = 0; + u16 data_rate = 0; + + switch (agg_report->bw_requested) { + case CHNL_BW_160: + bw = (cl_hw->wrs_db.adjacent_interference20 || + cl_hw->wrs_db.adjacent_interference40 || + cl_hw->wrs_db.adjacent_interference80) ? + rate_ctrl_info.field.bw : agg_report->bw_requested; + break; + case CHNL_BW_80: + bw = (cl_hw->wrs_db.adjacent_interference20 || + cl_hw->wrs_db.adjacent_interference40) ? + rate_ctrl_info.field.bw : agg_report->bw_requested; + break; + case CHNL_BW_40: + bw = cl_hw->wrs_db.adjacent_interference20 ? + rate_ctrl_info.field.bw : agg_report->bw_requested; + break; + case CHNL_BW_20: + bw = agg_report->bw_requested; + break; + } + + cl_rate_ctrl_parse(&rate_ctrl_info, &nss, &mcs); + + data_rate = cl_data_rates_get_x10(rate_ctrl_info.field.format_mod, + bw, + nss, + mcs, + rate_ctrl_info.field.gi); + + wrs_info->epr_acc += ((u64)agg_report->success * data_rate); + wrs_info->tx_success += agg_report->success; + } + + if (cl_hw->wrs_db.quick_down_en && wrs_info->quick_rate_check) { + if (is_same_rate(agg_report, &wrs_params->tx_params)) { + wrs_info->quick_rate_agg_cntr++; + wrs_info->quick_rate_pkt_cntr += (agg_report->success + agg_report->fail); + + if (wrs_info->quick_rate_agg_cntr >= cl_hw->wrs_db.quick_down_agg_thr && + wrs_info->quick_rate_pkt_cntr > cl_hw->wrs_db.quick_down_pkt_thr) { + wrs_info->quick_rate_check = false; + cl_wrs_api_quick_down_check(cl_hw, cl_sta, wrs_params); + } + } + } +} + +void cl_agg_tx_report_simulate_for_single(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_hw_tx_status *status) +{ + /* Assign statistics struct */ + struct cl_agg_tx_report agg_report; + union cl_rate_ctrl_info rate_ctrl_info; + + memset(&agg_report, 0, sizeof(struct cl_agg_tx_report)); + + agg_report.bf = status->bf; + agg_report.success = status->frm_successful; + agg_report.fail = status->num_mpdu_retries + (status->frm_successful ? 0 : 1); + agg_report.success_after_retry = + (status->frm_successful && status->num_mpdu_retries) ? 1 : 0; + agg_report.retry_limit_reached = !status->frm_successful ? 1 : 0; + agg_report.success_more_one_retry = + (status->frm_successful && (status->num_mpdu_retries > 1)) ? 1 : 0; + agg_report.sta_idx = cl_sta->sta_idx; + agg_report.bw_requested = status->bw_requested; + + rate_ctrl_info.field.bw = status->bw_transmitted; + rate_ctrl_info.field.gi = status->gi; + rate_ctrl_info.field.format_mod = status->format_mod; + rate_ctrl_info.field.mcs_index = status->mcs_index; + + cl_rate_ctrl_convert(&rate_ctrl_info); + + agg_report.rate_cntrl_info = rate_ctrl_info.word; + cl_agg_tx_report_handler(cl_hw, cl_sta, &agg_report); + cl_stats_update_tx_single(cl_hw, cl_sta, &agg_report); +} From patchwork Thu Jun 17 16:01:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 581EFC2B9F4 for ; Thu, 17 Jun 2021 16:11:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B533861428 for ; Thu, 17 Jun 2021 16:11:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232512AbhFQQNW (ORCPT ); Thu, 17 Jun 2021 12:13:22 -0400 Received: from mail-eopbgr00044.outbound.protection.outlook.com ([40.107.0.44]:21118 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233808AbhFQQMG (ORCPT ); Thu, 17 Jun 2021 12:12:06 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jQTs91xTLOZGRV53ZjXVBL/Cc3iYgScSoThBk6jpaFBLMDaeqJ4LImaxNw2RE1SwbFVncSONlohfUYt43hdOneXclw+MTzuBzUYpThe/zO0tFI7dw5Qr/0eo5Q7bhFgE00TCP4JdV1zqyjvn0kI6BRn93dnK2BdeCu9m4EWDa/1fXmxtFnq9635XjUCGQpZl5xkoOoH+Pq+sN+G7laIxLnOff6q4OoaKkxHcE5KO4y5t7csx2TmPIUp89fI8Oa/lFilH/p9tdKb1ne/XRxq2L2SyvQuwueCGMyyT+tZg7NHZHHKw/w3qDmCRmxTJ7Mlcaqs4MVBZSsPuzYuN1JqEBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9xxIRiwRYVg0/yxEseDVfslxWBjVO54Cq9ANtdsw88o=; b=FFwRaYAjkwXIWJ3faa7KvBpZMR3ek/B1E9p5UejxNmRqObnK8g1YHdn26nR1ShPU2rgkVgieA0W+JtiBIgbW6yt5XyAblqOiwTkbm36t8t6U01zBedwdqDbVY6cziw5CDbJdKRktLODtSSAmQK4vDAqXVcC2Ywybm8YJ9HvgFRw7dzDxzf1Jq4WkQKpOy8FmqsvOzSppoUsIX3CIOtikopOB04vjHZfHZzyWm9LsgKbxyG2L+CVAJLMVeqgvuaW6C54gkgtQJ/YL/pJYTEWCnotdoQQUBEwIm6aaNW/WIMhPodfUELkuOMK7kjBh3WY3RVN7wwPrxHkkrKpIIkBm2A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9xxIRiwRYVg0/yxEseDVfslxWBjVO54Cq9ANtdsw88o=; b=lXEH9LeQwivbsF7MPKYgsZqGR79hsjkyjYmZ3uVLA18nkNA1Vn/3zm68ZGDidc7ph9utOBwa7CyFP4TVItHbq++iBR7H4fZ8UPHCQJdxb75Q0Hv4UA1gNL8SpNrC/gJmIPgsdpePkROcrTQnKnjpXBh7/voSDlDE+0cVbF4P9ac= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM8P192MB1075.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1eb::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:07:18 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:18 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 205/256] cl8k: add tx/baw.h Date: Thu, 17 Jun 2021 16:01:32 +0000 Message-Id: <20210617160223.160998-206-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:20 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 09ce6556-8d9d-4d94-4c4d-08d931a9d920 X-MS-TrafficTypeDiagnostic: AM8P192MB1075: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1lgXdEZLv6CuwIG+JOkDQ290COZy1hwRnZFIFoVWivwxoSfmIGpEQAcZwOICAuC5RrDjSECIrhIFV2/R8oeckn4ovg5JCq4mbvnfM/rFowhxag/50BEEkVvP/Rt/UcZ70apI7SrVEHyJ7YVbrhwfhtcdz8gYCnMS+lWJ9CnM3+8i6DTCvkA6FohkrcPzI3I3xuFVjBqjL3eB2vDIvdrvCJ5YS3CEThFfny3Nc0bw96awXTkI4oRkssL1NmjNPJw5VxtkbiMVbQOzYfEWs3snpcRR4IX6N2gqhXsGT7nNSC0Lr7gTIkYp9irOzmWvE0L29qlQGz9uWd39Zjk420dh8gyv9MYVPNBLp255b12AJoQsI5eRWPexWkfUQ/6UvMTm+Qg7ZI5qiaEfGr1fK2wEXVPmxrwsUM5mqyb6xfvxEoUHqJ7ITLuTEPQ/JdjEo5L7Y9fhCSfeZqgPiKFmBN7DEYfpIggs/CjY/Y7QDhKd3Pb2Iar9UVrk2HCKpMh9MLthBJzjQrxz6dnkXURFkm4r2WquOr2oMNp0pv3fhGaNYDRGBrtPkAfmzhPhahWTjWAonIf4G8MzwoO6bRe3zy82+B9FKfsEgbwz/E06QyNb9p1kWhQDCfukUUOJaudAVCEp75DgJ3KPuC7RHQOWpTY9E/wwmc09yCnL11ZhmBPmPsKBCeZ3aL5lACLjDetDJvSnkGoG19IwtEztOtpzqkzjJQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(136003)(39850400004)(376002)(366004)(346002)(66476007)(6512007)(8936002)(66556008)(38350700002)(6916009)(9686003)(66946007)(956004)(86362001)(26005)(5660300002)(2616005)(38100700002)(478600001)(8676002)(6506007)(6666004)(4326008)(1076003)(55236004)(186003)(316002)(2906002)(83380400001)(16526019)(54906003)(52116002)(36756003)(107886003)(6486002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: H/OBHrticB9V5yJ5eP/RNkK02AP7oecKKjLyEUAuPX19hyiXrhYNOcG2VX9WufQVWyIv9X129EuGcB5O7iukTEaewlYEg7gVSZnJhEcDV8j7lLonCQwVtQ/B1U4d8qbTdO/DwwpEHvJ5dAG+yIRb+bFRo0bWw8l54kDBFUvi91IjR1ph6Q4VdJVO0A6sHbZayMfgX6Yc72MFDBB7MRecFYwfotcGU/OFA5/z+CJFIM0jPaJPr/QGDQuaPsFv+iZuzOOGaIearD0YfWf/+Ty2m87WMwj6tBlOWnNVciq3ZLW+x1NOrCLK/GJwiylAr6v1+I1J/GL/iYt4E+xLEOV2DFGOkdfNRlMNWJJx3KFsbJKj3nW9xcJNCboGuArGnWGOZycfVim7dStc+tfk4SzpFxPUTSupD1SJEhgqTjOT35F8L/A0E+2bWOEfTdqSWw8unIMJCmdTRQSCzbPqkdLcL/PmdLaD9kDr7897LZFgBIa2RFd54xieHfevpg+2u8AYLfDIbbf6Kf2aRcxaJGHnepuoMqMuQLBxQgo9uEEpGsQa+4En60fEb/ZIb0aBm/uAO+xPLWH47wB+HItgvg9EKOwVclmHqMTZq4ymeKQHhvqEc7KyVOKQKxUlBzbwLZYxiv/zNZO5F0iEaCAj1pFG+z/NtDEdmO4vZuz1618ofPkB0Sf5S52pO1aGEJR+ZyE4W5Gr6pKVm2zsn5oLyCh+sHF4m61nM7YxQuZkrYyTd1mesHgakoLvbaJbXAntUoJYlHWvQ8OSgxJE2z1Qn6+nSq31Nn25ZGGYIj4mruu/bfBuGOL1h/khuzrAQFL+IALAYtQq/yG5sHAuSmnI1+2umqBKPJKq2t4sk5QbQvvvUiCjDcQzWeDFiQQZYbBsX5KsH0mRWacPN0OrfXgvTkbL13IW47JrasTy9CuRsywVU4ADozAaTF3cb4iF48xGe0whmhqn7vp4MbtjlZ/NliODq6QC6X4PcNMblMNVIzhWr8szGtHMAHoXb8xg+zYTTgRy+zJxSez63N105yePGbdN97+Qx53ALX0aUA/Rq0fsT6CSUgVfLRHL0+8KuTQi7o7zEwEaHDNuWzalFLIGmN1/D13swOtKosmdKEN/6xhEtPlLznIdSQY/TSvOrTd17py2LfPPFviBh7wqyvMVtLtc+VrgyLNiIexX2blob2G+WwV5B1EBuJmbd19o7v0ukl7YDiMw6Q5ri5JwLpM5XGq9mL/bY06k5nwf0s8QFevJLby7eeLvaJDXjI6pcxyjp9nWv/AqdBSc4JyC98xOMBO8j7VFd1MUkvRYWGHNnjn7CUQm927o5kQCAhLiY3dNXaSU X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 09ce6556-8d9d-4d94-4c4d-08d931a9d920 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:21.3056 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xZjRM/uIWDL2xjrX3junraF9k2uGbSH04YJZhoPWtKCaiz5kcMkcvrhgMXg1uYKprZdQANBVyAnhHw2k2kV4Eg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1075 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/tx/baw.h | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/baw.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/baw.h b/drivers/net/wireless/celeno/cl8k/tx/baw.h new file mode 100644 index 000000000000..448fea76422a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/baw.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_BAW_H +#define CL_BAW_H + +#include "hw.h" +#include "sta.h" + +void cl_baw_init(struct cl_sta *cl_sta); +void cl_baw_start(struct cl_baw *baw, u16 ssn); +void cl_baw_operational(struct cl_hw *cl_hw, struct cl_baw *baw, + u8 fw_agg_idx, bool amsdu_supported); +void cl_baw_stop(struct cl_baw *baw); +void cl_baw_tx_inject(struct cl_hw *cl_hw, + struct cl_baw *baw, + u8 fw_agg_idx); +void cl_baw_pending_to_agg(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + u8 tid); +void cl_baw_pending_to_single(struct cl_hw *cl_hw, + struct cl_sta *cl_sta, + struct cl_baw *baw); +void cl_baw_pending_purge(struct cl_baw *baw); + +#endif /* CL_BAW_H */ From patchwork Thu Jun 17 16:01:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFCEFC2B9F4 for ; Thu, 17 Jun 2021 16:11:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96FC1610A5 for ; Thu, 17 Jun 2021 16:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232987AbhFQQNq (ORCPT ); Thu, 17 Jun 2021 12:13:46 -0400 Received: from mail-eopbgr60067.outbound.protection.outlook.com ([40.107.6.67]:35227 "EHLO EUR04-DB3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231379AbhFQQMs (ORCPT ); Thu, 17 Jun 2021 12:12:48 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VrgU1uuA42mb8CGdvU/Fk/6x+DKQzN2afO8GPvHJvZZhpN2NuTeZ3CVoGeBW3DwhN1mjrnJ54aPX2nBcUiPoA+lqe/+wQWO1vM4J8r5gb+eQoYXVy3HOnhJB2XgvmjIOWE6s94GWi0S8Mwolkcg/duY3Sn6q++cbN3niS+l8K7LyFmY7Du86Ry2Ot5Hj992ZALJZe+9B+fblZuljaTQyoyc2xjy9R5x08DqQN/umZwflKgkfXQRCxBv0qbzetO8bZTqhdILrWxMjMUyaMvPCl/wHGhuzobPtahWnluk2sjRO2LZ+fy6uN05zTTE3zVDjzBgpsDniIzwh3TXef5dmww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4x1TZIui1lHt+IAEkFjZfXChNYePgNOilKczZJ/Wtds=; b=ie6FP0oV5GxLSFgv+d2PstTYxBfl7pQATNChNI74qevJ4c3XOxHymy/S9I7M5eE2LB6ItE1VlZW0GMdJ2t4Aj86jLsEvj0NGl4CdJZUUqUeAQmoJWhLF7T0njfHvz/lEtFMzUoRMLpx9kTUcJhjxE8Qr9H9+vjXjueg3IUvYK7hQwMjOI3nquY4MZsFCpXvzdQdsKAynLrqjI+mYghwDpO/mQDsjf0T25CdhFCSNzjnwu0J4o1CSNCcKV7bSCg766J4yaID+Vu+yU46oVRnlhqBgM9A0vUuimGQec86qp9UEOTltoyCnKRofu0a1Y139zNfzt4CQAMKXStg4oHjgoA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4x1TZIui1lHt+IAEkFjZfXChNYePgNOilKczZJ/Wtds=; b=QmjXclpmI0voNO53jU+H+PAXftR7Y4IgzzjBKEyst0RuKDOsr3S29bhM2rQ7OG0nS6JuHNewyDUVxkKxgyXsQdcP60+ijLr+D3t9KRD68Eg0an5achAcIEC5REU+BBHGeK3hXLDIk8Va1oDEFD3lKaxSoqiKKcTPdiHV3Hq2Q3g= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM8P192MB1075.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1eb::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:07:20 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:19 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 209/256] cl8k: add tx/single_cfm.h Date: Thu, 17 Jun 2021 16:01:36 +0000 Message-Id: <20210617160223.160998-210-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:24 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8afe4e5e-ad6e-4c95-c508-08d931a9db96 X-MS-TrafficTypeDiagnostic: AM8P192MB1075: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IdQp8gdfV05KxuvpyUdcKqVgDo5uofst+IUrkf7XPiLgvifuoQ3n4wGokCHvI0fVNxXMnW4bd1RukUeh+gD7sJQXTE+QEyWIttjY111wMz8zts2tN3ReW+zMwjo3wln/r0gdccJZkPtiWM09W1W6Hmdi4Y6slZC2VVbs0ptdIDA0LL91+ekB7JZk4Qd3tvc5ptN3PsCWvGT8vD6Gz5wSEMYyTBwhcLJ5Cy+iMHExkw5TcTCAmDX0VJqKPfhWE+9M9Iqy6SFQImOK5qEp/AilNHDdfgL2hT6cWSgSfNVi4SYj5cst56dA6gSFa8lS9w/Hj5FhFvOAOdhMlubwXpEmnTscHIeQHBeLxmP6o5iOQmeEjPMjNG/+MdWk42tGMAWpGiyhze4priU5Rp8Y/aTMOMUmUfE6l/8kLCkRv7vCXYyNUoRGrw2WxIq84e0IWPDAY6+vaC1OStRN4B0h1b/Ca6iYRiU4v2Z/hB4CDvhsx9nqNSycokoxfql1uBHJA9QZ/D313JUNrRPeXqA+Y6Ob6x5Xavka97fvqdnHsQdV6/Unvqcw1FKuctcy1//kPFIauCIz8awrcjREzy4GlMVi5/e8apJzECvslKFOt9EH/EoSGQR3prFxDG7BiUSq9g45gSM+Yw8NvDJbFW294LTCOXFuE93bN1JPTCCRoFrWTi/1xKNQHICuxXP0rU91+mYklIHGYAdl05Snjk5mPu6brA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(136003)(39850400004)(376002)(366004)(346002)(66476007)(6512007)(8936002)(66556008)(38350700002)(6916009)(9686003)(66946007)(956004)(86362001)(26005)(5660300002)(2616005)(38100700002)(478600001)(8676002)(6506007)(6666004)(4326008)(1076003)(55236004)(186003)(316002)(2906002)(83380400001)(16526019)(54906003)(52116002)(36756003)(107886003)(6486002)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7aOx6j/pIu7pyiArz1E1IqJePTVShGMQ0xx7A4YEM/cPh/qwyi5Ye1m/lQN+/AulVEO0Y2+YRzYYXQp2ppYqhABwPCA/ExfLbyFGDDxzWlLHs0MLRIMA9K///rPe2zqwaXjEyVzP7vRuT+6LfsG9GW8VTpGOhiB9w97pTGPqK7y5ZoYma/Y2U+bCsrD3beBDNXClDS5/4FQudShjfQjjOBhinno2xnwISmbHLzzfBOUPtzjB8ui/TFAHHaecpLXVhEQVFzk7U3SQGg9wK6YBBd6LAD/QIgSvsoFDrlKKgy+nN1luutZSf2fCBhqlcHJATXHxLVWQkm9DRmJe+ae07X34tYzZkztOvWpPeV9yAqwdmSAnwt8LYOvPvCcL82hwzLVL0/cfo/cgU0FFTRufQtPygSTN876DzF0D8ey00onjbout+rUZ1mfZ7fnluTDQl7RyUbOTvqM1Z8z8ojoiQmf0AuXQyUPdmxJlstn6x3GqRYj3kla1v5B5o1m4b5JEl51tbMEflzgBrq9w8A7wmkbEzhoJPWDVMwXrsKxeAFDBJum/HYb8JhfoKmE913IMR//JICEY5PZiuXT1VV+GQJ/pk+JXcdbJnBwaifb4jFrJVlLedPYt6sCkYaE//+tyjQRg+iU/zLtxvApRsc56fYEYeEwgz8M1+6vTfg6tR06iaC3khubGEW1ysqnMLuI/rJKQxw8ek+74dKQIzZceVExsaPCpFvy/vtPBqqJ6nEWLurIVviaFzarnszen+RKRpfU8irASGTbR67dTYm9s+aK99oY3CeqR606HSQVzXDmkXzEaega0HxXwvBXvk6KfAulxuPwKoDnCVia5AwUHjM3pK84RRU8vhU+DHzqle7EE5gkngroZfMqID89BbQP12W/OSXLM7gPpYyp/2yWqy0cua1MSRE25gV/mhLAL7EyiL4aGKtv2+3NN3QAQ1PCjH3ZNBIN6dDDlMcVNrW8am9l2g6eTYtGuTkbjf2//Aw5ZGnGgeVMfZDelsWfwil9mrrqQgP3sssrtAZDI2kuHOF5HQaDTN5dRyJrSBXD7OeW+OIWLnDURo7Uir2RufqOCKM+HbDGWS3oUKJgmbpUDAy2aI5XwCkilxk02uDcGx/pBhhnTwfG1LS6a/eHDZy4iOmmZSDlgvyJGMKQje8YURU+jpz1A4wSFaWemO/746/Mtm3jhFuUQXVN5PK9l0oFjApa3+eECnuCKdxJvvD7ifqgG0i2uea0QvNZUkQfvXB0OdSOcj8XncFx5TIGA+48ZtD7ShwYW2Lt8nGJlKm3VKviesCd075Ga5+6T+XvWFcylPZEc4Fcj1U8v1PtYzrYt X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8afe4e5e-ad6e-4c95-c508-08d931a9db96 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:25.4494 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3Vr2Wm8AkGeKe5kZxDCmiyQZ5y5v52fugtxZZ4H6LCu5j2my8X7Gb7o3f6BwD1klYsa8iChqFk71SK2FVA2BDw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB1075 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/tx/single_cfm.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/single_cfm.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/single_cfm.h b/drivers/net/wireless/celeno/cl8k/tx/single_cfm.h new file mode 100644 index 000000000000..f04b93a51ba5 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/single_cfm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_SINGLE_CFM_H +#define CL_SINGLE_CFM_H + +#include "tx/tx.h" + +void cl_single_cfm_init(struct cl_hw *cl_hw); +void cl_single_cfm_add(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr, u32 queue_idx); +struct cl_sw_txhdr *cl_single_cfm_find(struct cl_hw *cl_hw, u32 queue_idx, + dma_addr_t dma_addr); +void cl_single_cfm_flush_all(struct cl_hw *cl_hw); +void cl_single_cfm_flush_sta(struct cl_hw *cl_hw, u8 sta_idx); +void cl_single_cfm_poll_empty(struct cl_hw *cl_hw, u32 queue_idx); +void cl_single_cfm_poll_empty_sta(struct cl_hw *cl_hw, u8 sta_idx); + +#endif /* CL_SINGLE_CFM_H */ From patchwork Thu Jun 17 16:01:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5685EC49EA3 for ; Thu, 17 Jun 2021 16:09:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B51661425 for ; Thu, 17 Jun 2021 16:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233809AbhFQQMG (ORCPT ); Thu, 17 Jun 2021 12:12:06 -0400 Received: from mail-eopbgr80045.outbound.protection.outlook.com ([40.107.8.45]:58683 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233805AbhFQQKt (ORCPT ); Thu, 17 Jun 2021 12:10:49 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mL3MWfkydnpHoAj3KG9BA+ptEsbUKnIFrrW8PV/rPWYcH0QyapXY6Blap0++EYH/LhdDkqxz+XsOIiZbhVgVjbHoBIxojDJj0po1oUXWvuq9THPc6qMZBMEjnH/xbpZPbEn5AdAFY0mWsWjR0l9fThcH5oWhiHfL63r5E81lgsHFa0I541EbNmMQlw9xIf/oq+AoG1oKgtXtNbbIGHj8TOGuPVmGu28julPkGORidj5lwzD4dgSWPqzRMP/XQnv2FXAzOR65EL4ec2yV7LGvEDNZiFWPDiyBAuCfb4pu7/NybwWhR+s2csxBaE8w3wNkN/A8PntMrWVbcdX6xdd9YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NZORK/eU497SVPt5EDkh3yY85FkarXgYaUUpscdrxTc=; b=hbYTwyGNSc/Bi+i6JtlcU8ZRDF77JtJ5WY7YO+8D/dHn6E65OKiuxIaCEgqd6Anvlrb7g7PidA+dU+HYmVXGU7cVHNutguCp1yEOkpIa7kXA/SOpYnbNfIOtx+9mkoGvX2QP7yFlIzP/UEvd/VvOgArY8meh7py/KcZlks5PBxwBBFpTAkmsO376Jr1is+a2486yHjXVc5AOy/biULzHogH0Hsc1uCKuFRC2owx9DsH6EJOMTuH0bKv3fFKKnhqLr1BOjJEDdY6YLayy6/VYHxK1eWyqMO9WZxv/4LzJ/bEv+dSJr0JoEA0aRxa02JtjsvBUl6ajVvVNM+D9YtX7yg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NZORK/eU497SVPt5EDkh3yY85FkarXgYaUUpscdrxTc=; b=o4hdPQT6jf4mAwmxNtfOGMafyuOXAzg5QnbqoLK0yeGdJ20OB/Dy0mpbf3iDEWuQyOYaRfTxwKFJ0mq5A7jpuN/jdkWW9qfQntxyiGyKbSXs3yv7zApDSG8kAJAPvBs1EV2myUvGwzNSSPsR/ExNmdLM0YNLVndVInBCEujkIXs= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1329.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:3ab::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16; Thu, 17 Jun 2021 16:07:51 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:51 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 212/256] cl8k: add tx/tx.c Date: Thu, 17 Jun 2021 16:01:39 +0000 Message-Id: <20210617160223.160998-213-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3525cabf-f1aa-486f-3bf8-08d931a9dddd X-MS-TrafficTypeDiagnostic: AM9P192MB1329: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FGY0p+d9aLCi223ktt5C400H9iFK+hX2XyJMUiTHY/MP3NxaJZtURq7Lzl8Ltzzo30I+dS2/xa9Djv1jiEDza2BqdxJ2Xa+fEi/dyyO+nJ67JBnbrYIwFLcJmNabRdbx3SSqS8ezSxgXDFzuLrAMXr0+Y7qJobYEFnQFFgk8WUNzmEf9dt+/IagZWeIemhCRGt3JY1mVPLkZ3Pv659czhwbn5iJ4G55rOCfsaebNbylHaFesvqegwtE197hKdBLxbVaVaWtUzmvFCaa+M0jKhAXthIMb/+IHQLFTiBRNdghiXxi8dJNhoNqc2p8Bwymq5/cyagwoPkel66Tbss19YXsWkbVa8NXMjF9X6C3Y4qrnCVANbwQPWN2lSvCATNpwwEcCIa9TqXTUfOHfF36T4+rlgsRaQAUXAfujMXCu88KoOyfNcy3JW0zbVNfI2sBN/F/6njFS3iiJ0g8WDsXztPH7IrYXEPGlxqH+rxwt7T5ey1rpeq+51Z0bpvyiD27Us2uvHFKLVmOt1A6UgFXLURvVauhY4lCvPRno4GwZ9i6HqoER5f15QIKGZNzx5tHJdYm8M8J1EWGmFYvPDisQKRS4x/GKNj0wGi82VaJMwv9yJSKkfIG0ppBv824hd88EKee6lJoqpfiaoKHjLZNK7SN/2e/549Atk5YSteyF6/f0EKCmotfdRkLCUHA8ooXP4Oi5Gltpk3b1qM+7Cb/xkQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(39850400004)(376002)(136003)(346002)(396003)(86362001)(38350700002)(8936002)(38100700002)(6916009)(52116002)(6486002)(55236004)(54906003)(36756003)(6506007)(956004)(4326008)(30864003)(186003)(2616005)(1076003)(478600001)(26005)(16526019)(107886003)(6666004)(66556008)(83380400001)(5660300002)(2906002)(6512007)(9686003)(8676002)(316002)(66476007)(66946007)(69590400013)(32563001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1dGLpxWvzFsU7ZBn0qcWR2kgUzyCAbKjlOKyeONbSjVE9snPvU4000gm0cq8RHEgRhfiOtirtICJXc3V5jT8rye8NztH17pbLdcNZBL+ttkMWeLuSb0NntxrVT2FZFrV9uGGKOEtb49aNSdN+9MkaD6zL7mfWYCTVEvC5gjzrk8ZvqhMCdWorf3PqZD4LLnSkftJu4+pkBPkIx8pEz5KSXEVaP5cv+YbVpu9oDj8cDX4CMAtWlFI/rlIq5tmKRNU+LtnwlO/ZW7hgtQRzEqNU5ETAWyXlrBiJfT1osBebIpzDrTfY7O7OJtEEncKaY4EU2ZsVfyy6VQ1oTm4L2wtUMa3wVq5Gn45dnuWH7+9vg+lYwEFvgs9/bk74Vg1MFo/QFLgRLeKBayfMGul82JSH6UBrlBdEPtsj9GE+lwKr1zoCAUyvPx1sVZHewj7PdVFTkbYM2SDKcTAbH/xTVM1bq9g08/eMSQvsCuHFw+9E1PTAIXsUr9z4zt22BVgxE/4iXRSNAxYMSrLgP1GaAjIjioB61qSNLhjKiVHru8lm0mTD3r17bJDElK56uYBeocDM6TA/l9vcOka9qlz0vezUeM4qQpqN4gaf1C7Zok81hCMHF8gP02oG+yuzvkp+ARyAT2TeFS+IkvgZxZjXgkEgPN6WPaSTsqMDP14Yq6P+yoYYKrnIzN9JBkJPeowMQ8jarBkhyv3Z5krpzYRK1C4o+FtnnPm1ZTSGcgMFF1l9mjBkTnp9SVy8dqWboFzXgowWReCu1xI5ayov99nONS9jDAP2UWrrniuzd2rLU5fmw3mSAtG1eqlMNfum0Dk2nGm2rAHDVU8/igU1SIELuZ9Kxo5nN9iMii5aXuYLQyxJiWJbfeNK+NJ1sg84occoCTWXPdAPimw6EJsMTRgYjpC4ECtwKbfiTJzDNSMEkSqFjFknSYI3eujEAY9LsIt4QSCNrv4mKof9ZSON/PMUfmgsd2oL+dV9Qv5kASD0OMaa/A2FuR8Ijxeo0dnNCwSwLqfzIsRccc2ZtBuSVsTVN7wkOOmjnpy3CuU0D3izaRzo+97iCLwtIRak+nkZiwMAxYw9wfmXLMMZD4XGTW6hXKnkpQHR6034Ax/VsuFlCHauJWCEYYyfOBmnIqcs8rkjrzEA3RFLp3nh2Kpiw5u8XP3PGSzkJQ5Fo2JpXlbEa4XALnbRwDMvgHcV++RUODVPGUSu5dT2hO3S4qvhnE9B9STcb5AgbqBaM+h2UFvdSUdQlxrqBHc9bCK2ShRukgsjj+MBZXkrKJMCOpax5qj0ZcStrZ0Ab8wyrJghJ6vW54EiR6BZ3CiginUd3V4AY/SQcOw X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3525cabf-f1aa-486f-3bf8-08d931a9dddd X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:29.7107 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 82CQesnTbD54GizGLzVXj7o79ZC+LP0h5vubqUrl4ibB0ZcZSkq+UZQm8gpMQWN97pmwLHLiOkaqvR/thbsGUg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1329 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/tx/tx.c | 1325 ++++++++++++++++++++++ 1 file changed, 1325 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/tx.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/tx.c b/drivers/net/wireless/celeno/cl8k/tx/tx.c new file mode 100644 index 000000000000..ccf81dbeb8ec --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/tx.c @@ -0,0 +1,1325 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "chip.h" +#include "tx/tx.h" +#include "tx/agg_cfm.h" +#include "tx/single_cfm.h" +#include "tx/bcmc_cfm.h" +#include "tx/tx_queue.h" +#include "stats.h" +#include "fw/msg_tx.h" +#include "rate_ctrl.h" +#include "tx/tx_amsdu.h" +#include "traffic.h" +#include "dfs/dfs.h" +#include "band.h" +#include "vns.h" +#include "utils/utils.h" +#include "enhanced_tim.h" +#include "mac_addr.h" +#include "key.h" +#include "utils/ip.h" +#include "radio.h" +#include "recovery.h" +#include "ext/vlan_dscp.h" +#include "wrs/wrs_api.h" +#include "drv_ops.h" +#ifdef TRACE_SUPPORT +#include "trace.h" +#endif + +/* Expected Acknowledgment */ +#define EXPECTED_NO_ACK 0 +#define EXPECTED_ACK 1 + +const u8 dscp_to_up[TID_MAX] = {0, 8, 16, 24, 32, 40, 48, 56}; + +static DEFINE_PER_CPU(struct tasklet_struct, tx_remote_tasklet[TCV_TOTAL]); + +static void cl_tx_remote_tasklet_sched(void *t) +{ + tasklet_schedule((struct tasklet_struct *)t); +} + +static void cl_tx_remote_cpu(struct cl_hw *cl_hw, struct sk_buff *skb, int cpu) +{ + /* Move driver TX path to a different CPU */ + struct tasklet_struct *t = &per_cpu(tx_remote_tasklet[cl_hw->idx], cpu); + + skb_queue_tail(&cl_hw->tx_remote_queue, skb); + + if (!test_bit(TASKLET_STATE_SCHED, &t->state)) + smp_call_function_single(cpu, cl_tx_remote_tasklet_sched, t, 0); +} + +static void cl_tx_remote_tasklet(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + struct sk_buff *skb = NULL; + + while ((skb = skb_dequeue(&cl_hw->tx_remote_queue))) + __cl_tx_start(cl_hw, skb, skb->dev); +} + +void cl_tx_init(struct cl_hw *cl_hw) +{ + int cpu = cl_hw->conf->ci_tx_remote_cpu; + + skb_queue_head_init(&cl_hw->tx_remote_queue); + + if (cpu >= 0) + tasklet_init(&per_cpu(tx_remote_tasklet[cl_hw->idx], cpu), + cl_tx_remote_tasklet, + (unsigned long)cl_hw); +} + +static void cl_tx_stop_remote_cpu(struct cl_hw *cl_hw) +{ + int cpu = cl_hw->conf->ci_tx_remote_cpu; + + if (cpu >= 0) { + tasklet_kill(&per_cpu(tx_remote_tasklet[cl_hw->idx], cpu)); + skb_queue_purge(&cl_hw->tx_remote_queue); + } +} + +static void cl_tx_cpu_single(struct cl_hw *cl_hw) +{ + u32 processor_id = smp_processor_id(); + + if (processor_id < CPU_MAX_NUM) + cl_hw->cpu_cntr.tx_single[processor_id]++; +} + +static void cl_tx_cpu_agg(struct cl_hw *cl_hw) +{ + u32 processor_id = smp_processor_id(); + + if (processor_id < CPU_MAX_NUM) + cl_hw->cpu_cntr.tx_agg[processor_id]++; +} + +static inline void cl_tx_update_stats(struct sk_buff *skb, struct cl_sta *cl_sta, u16 ac, u8 tid) +{ + struct sta_info *stainfo = cl_sta->stainfo; + struct net_device *dev = skb->dev; + struct pcpu_sw_netstats *tstats = this_cpu_ptr(dev->tstats); + + u64_stats_update_begin(&tstats->syncp); + tstats->tx_packets++; + tstats->tx_bytes += skb->len; + u64_stats_update_end(&tstats->syncp); + + stainfo->tx_stats.bytes[ac] += skb->len; + stainfo->tx_stats.packets[ac]++; + stainfo->tx_stats.msdu[tid]++; +} + +static char cl_tx_ctrl_single_frame_type(__le16 fc) +{ + if (ieee80211_is_data_qos(fc)) + return CL_TX_SINGLE_FRAME_TYPE_QOS_DATA; + else if (ieee80211_is_qos_nullfunc(fc)) + return CL_TX_SINGLE_FRAME_TYPE_QOS_NULL; + else if (ieee80211_is_mgmt(fc)) + return CL_TX_SINGLE_FRAME_TYPE_MANAGEMENT; + else + return CL_TX_SINGLE_FRAME_TYPE_OTHER; +} + +static void cl_tx_single_prep(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr, + u16 frame_len, u8 hdr_pads, bool is_vns) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(sw_txhdr->skb); + struct ieee80211_key_conf *key_conf = tx_info->control.hw_key; + struct txdesc *txdesc = &sw_txhdr->txdesc; + struct tx_host_info *host_info = &txdesc->host_info; + + /* Reset txdesc */ + memset(txdesc, 0, sizeof(struct txdesc)); + + /* Vif_index must be filled in even without header conversion */ + if (!cl_tx_ctrl_is_inject(tx_info)) { + struct cl_vif *cl_vif = (struct cl_vif *)tx_info->control.vif->drv_priv; + + host_info->vif_index = cl_vif->vif_index; + } + + if (hdr_pads) + host_info->host_padding |= BIT(0); + + host_info->is_bcn = sw_txhdr->is_bcn; + host_info->expected_ack = (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) ? + EXPECTED_NO_ACK : EXPECTED_ACK; + + /* Beware when prot and sta is unknown */ + if (key_conf) { + frame_len += key_conf->icv_len; + host_info->is_protected = true; + host_info->hw_key_idx = key_conf->hw_key_idx; + } + + host_info->packet_cnt = 1; + + txdesc->umacdesc.packet_len[0] = cpu_to_le16(frame_len); + txdesc->e2w_result.bcmc = (sw_txhdr->sta_idx == STA_IDX_INVALID); + txdesc->e2w_result.tid = sw_txhdr->tid; + txdesc->e2w_result.is_vns = is_vns; + txdesc->e2w_result.is_txinject = cl_tx_ctrl_is_inject(tx_info); + txdesc->e2w_result.single_type = cl_tx_ctrl_single_frame_type(sw_txhdr->fc); + txdesc->e2w_result.single_valid_sta__agg_e2w_tx_done = sw_txhdr->cl_sta ? 1 : 0; + txdesc->e2w_natt_param.sta_index = sw_txhdr->sta_idx; + + /* Set rate control */ + cl_rate_ctrl_update_desc_single(cl_hw, host_info, sw_txhdr); +} + +static void cl_tx_sub_frame_set(struct cl_sta *cl_sta, u8 tid) +{ + struct cl_tx_queue *tx_queue = cl_sta->agg_tx_queues[tid]; + + if (tx_queue) + tx_queue->total_packets++; +} + +static void cl_tx_send(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr, + struct cl_amsdu_ctrl *amsdu_anchor) +{ + struct cl_tx_queue *tx_queue = sw_txhdr->tx_queue; + + tx_queue->total_packets++; + + if (cl_txq_is_fw_full(tx_queue)) { + /* If firmware is full push the packet to the queue */ + cl_txq_push(cl_hw, sw_txhdr); + } else if (amsdu_anchor && amsdu_anchor->is_sw_amsdu) { + cl_txq_push(cl_hw, sw_txhdr); + tasklet_schedule(&cl_hw->tx_task); + } else if (!list_empty(&tx_queue->hdrs)) { + /* + * If queue in driver is not empty push the packet to the queue, + * and call cl_txq_sched() to transfer packets from the queue to firmware + */ + cl_txq_push(cl_hw, sw_txhdr); + cl_txq_sched(cl_hw, tx_queue); + } else { + /* Push the packet directly to firmware */ + cl_tx_push(cl_hw, sw_txhdr, tx_queue); + } +} + +void cl_tx_push(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr, struct cl_tx_queue *tx_queue) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(sw_txhdr->skb); + struct ieee80211_key_conf *keyconf = tx_info->control.hw_key; + struct cl_sta *cl_sta = sw_txhdr->cl_sta; + struct cl_vif *cl_vif = sw_txhdr->cl_vif; + u8 tid = sw_txhdr->tid; + struct txdesc *txdesc = &sw_txhdr->txdesc; + struct tx_host_info *host_info = &txdesc->host_info; + struct cl_e2w_txhdr_param *e2w_txhdr_param = &txdesc->e2w_txhdr_param; + struct ieee80211_hdr *hdr80211 = sw_txhdr->hdr80211; + u8 queue_type = tx_queue->type; + bool is_mgmt = ieee80211_is_mgmt(sw_txhdr->fc); + + if (cl_key_is_cipher_ccmp_gcmp(keyconf)) { + /* + * In case of CCMP or GCMP encryption we need to inc pn. + * In case of amsdu/header_conversion we need to pass it to firmware as well + */ + u64 pn = atomic64_inc_return(&keyconf->tx_pn); + + if (txdesc->e2w_natt_param.hdr_conv_enable) { + memcpy(&e2w_txhdr_param->encrypt_pn, &pn, CL_CCMP_GCMP_PN_SIZE); + } else { + u8 hdrlen = ieee80211_hdrlen(sw_txhdr->fc); + + cl_key_ccmp_gcmp_pn_to_hdr((u8 *)hdr80211 + hdrlen, pn, keyconf->keyidx); + } + } + + if (queue_type == QUEUE_TYPE_AGG) { + struct cl_baw *baw = &cl_sta->baws[tid]; + bool is_amsdu = cl_tx_ctrl_is_amsdu(tx_info); + + if (is_amsdu) { + struct cl_amsdu_ctrl *amsdu_anchor = &cl_sta->amsdu_anchor[tid]; + + if (sw_txhdr->is_sw_amsdu) { + u8 pkt_cnt = sw_txhdr->sw_amsdu_packet_cnt; + + if (pkt_cnt == 1) + cl_tx_amsdu_unset(sw_txhdr); /* Clear AMSDU bit. */ + + if (hdr80211) + hdr80211->seq_ctrl = cpu_to_le16(baw->tid_seq); + + tx_queue->stats_sw_amsdu_cnt[pkt_cnt - 1]++; + } else { + u8 pkt_cnt = host_info->packet_cnt; + + if (pkt_cnt == 1) + cl_tx_amsdu_unset(sw_txhdr); /* Clear AMSDU bit. */ + + tx_queue->stats_hw_amsdu_cnt[pkt_cnt - 1]++; + } + + /* Reset anchor if needed */ + if (amsdu_anchor->sw_txhdr == sw_txhdr) + cl_tx_amsdu_anchor_init(amsdu_anchor); + } + + /* Update sequence number and increase it */ + e2w_txhdr_param->seq_ctrl = cpu_to_le16(baw->tid_seq); + baw->tid_seq = INC_SN(baw->tid_seq); + } else { + /* + * Update sequence number and increase it + * Management sequence number is set by firmware. + */ + if (!is_mgmt) { + hdr80211->seq_ctrl |= cpu_to_le16(cl_vif->sequence_number); + cl_vif->sequence_number = INC_SN(cl_vif->sequence_number); + } + } + + cl_drv_ops_pkt_fw_send(cl_hw, sw_txhdr, tx_queue); +} + +void cl_tx_single_free_skb(struct cl_hw *cl_hw, struct sk_buff *skb) +{ + if (IEEE80211_SKB_CB(skb)->ack_frame_id) + ieee80211_tx_status(cl_hw->hw, skb); + else + dev_kfree_skb_any(skb); +} + +void cl_tx_single(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct sk_buff *skb, bool is_vns, bool lock) +{ + struct cl_tx_queue *tx_queue; + struct cl_sw_txhdr *sw_txhdr; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + struct cl_vif *cl_vif = (struct cl_vif *)tx_info->control.vif->drv_priv; + struct ieee80211_hdr *hdr80211 = (struct ieee80211_hdr *)skb->data; + u8 hdr_pads = CL_SKB_DATA_ALIGN_PADS(hdr80211); + __le16 fc = hdr80211->frame_control; + u16 frame_len = (u16)skb->len; + u8 tid = ieee80211_is_data_qos(fc) ? ieee80211_get_tid(hdr80211) : 0; + u8 ac = tid_to_ac[tid]; + bool is_beacon = ieee80211_is_beacon(fc); + + cl_tx_cpu_single(cl_hw); + + if (unlikely(!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) || + test_bit(CL_DEV_FW_ERROR, &cl_hw->drv_flags))) { + cl_tx_single_free_skb(cl_hw, skb); + cl_hw->tx_packet_cntr.drop.dev_flags++; + return; + } + + if (unlikely(!cl_vif->tx_en || cl_hw->tx_disable_flags)) { + cl_tx_single_free_skb(cl_hw, skb); + cl_hw->tx_packet_cntr.drop.tx_disable++; + return; + } + + /* Check if packet length exceeds max size */ + if (unlikely(frame_len > CL_TX_MAX_FRAME_LEN_SINGLE)) { + cl_tx_single_free_skb(cl_hw, skb); + cl_dbg_err(cl_hw, "frame_len (%u) exceeds max size\n", frame_len); + cl_hw->tx_packet_cntr.drop.length_limit++; + return; + } + + if (cl_sta && cl_sta->key_disable) { + cl_tx_single_free_skb(cl_hw, skb); + cl_hw->tx_packet_cntr.drop.key_disable++; + return; + } + + /* Allocate sw_txhdr */ + sw_txhdr = cl_sw_txhdr_alloc(cl_hw); + + if (unlikely(!sw_txhdr)) { + cl_tx_single_free_skb(cl_hw, skb); + cl_dbg_verbose(cl_hw, "sw_txhdr alloc failed\n"); + cl_hw->tx_packet_cntr.drop.txhdr_alloc_fail++; + return; + } + + /* Prepare sw_txhdr */ + sw_txhdr->hdr80211 = hdr80211; + sw_txhdr->hw_queue = tx_info->hw_queue; + sw_txhdr->is_bcn = is_beacon; + sw_txhdr->skb = skb; + sw_txhdr->map_len = frame_len + hdr_pads; + sw_txhdr->fc = fc; + sw_txhdr->cl_vif = cl_vif; + sw_txhdr->tid = tid; + sw_txhdr->ac = ac; + + if (cl_sta) { + sw_txhdr->cl_sta = cl_sta; + sw_txhdr->sta_idx = cl_sta->sta_idx; + } else { + sw_txhdr->cl_sta = NULL; + sw_txhdr->sta_idx = STA_IDX_INVALID; + } + + /* Prepare txdesc */ + cl_tx_single_prep(cl_hw, sw_txhdr, frame_len, hdr_pads, is_vns); + + /* + * Fetch the driver queue. + * IEEE80211_TX_CTL_AMPDU is not set in tx_info->flags, otherwise cl_tx_agg() + * would have been called and not cl_tx_single(). + * Therefore there is no need to check if tx_queue is NULL or if queue type + * is QUEUE_TYPE_AGG. + */ + tx_queue = cl_txq_get(cl_hw, sw_txhdr); + sw_txhdr->tx_queue = tx_queue; + + if (lock) { + if (tx_queue->type == QUEUE_TYPE_BCMC) { + /* + * There is no need to take spin_lock_irqsave() because bcmb queue + * will be called only from interrupt context - cl_irq_status_tbtt(). + * All other broadcast/multicast packets are buffered in + * ieee80211_tx_h_multicast_ps_buf() and will follow the beacon. + */ + spin_lock(&cl_hw->tx_lock_bcmc); + cl_tx_send(cl_hw, sw_txhdr, NULL); + spin_unlock(&cl_hw->tx_lock_bcmc); + } else { + spin_lock_bh(&cl_hw->tx_lock_single); + cl_tx_send(cl_hw, sw_txhdr, NULL); + spin_unlock_bh(&cl_hw->tx_lock_single); + } + } else { + cl_tx_send(cl_hw, sw_txhdr, NULL); + } +} + +void cl_tx_fast_single(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct sk_buff *skb, bool lock) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; + + /* hw_key must be set before calling cl_tx_8023_to_wlan() */ + tx_info->control.hw_key = cl_key_get(cl_sta); + + /* Convert 802.3 to 802.11 header */ + if (cl_tx_8023_to_wlan(cl_hw, skb, cl_sta, tid) == 0) { + bool is_vns = cl_vns_is_very_near(cl_hw, cl_sta, skb); + u8 ac = tid_to_ac[tid]; + + tx_info->hw_queue = ac; + tx_info->control.vif = cl_sta->cl_vif->vif; + + cl_tx_update_stats(skb, cl_sta, ac, tid); + + cl_hw->tx_packet_cntr.forward.drv_fast_single++; + + cl_tx_single(cl_hw, cl_sta, skb, is_vns, lock); + } +} + +void cl_tx_agg_prep(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr, + u16 frame_len, u8 hdr_pads, bool hdr_conv) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(sw_txhdr->skb); + struct ieee80211_key_conf *key_conf = tx_info->control.hw_key; + struct txdesc *txdesc = &sw_txhdr->txdesc; + struct lmacapi *umacdesc = &txdesc->umacdesc; + struct tx_host_info *host_info = &txdesc->host_info; + u16 qos_ctrl = sw_txhdr->tid; + + /* Reset txdesc */ + memset(txdesc, 0, sizeof(struct txdesc)); + + txdesc->e2w_result.tid = sw_txhdr->tid; + txdesc->e2w_result.is_txinject = cl_tx_ctrl_is_inject(tx_info); + txdesc->e2w_natt_param.sta_index = sw_txhdr->sta_idx; + txdesc->e2w_natt_param.ampdu = true; + txdesc->e2w_natt_param.hdr_conv_enable = hdr_conv; + + if (hdr_conv) { + if (cl_tx_ctrl_is_amsdu(tx_info)) + qos_ctrl |= IEEE80211_QOS_CTL_A_MSDU_PRESENT; + + txdesc->e2w_txhdr_param.frame_ctrl = cpu_to_le16(sw_txhdr->fc); + txdesc->e2w_txhdr_param.qos_ctrl = cpu_to_le16(qos_ctrl); + } + + if (hdr_pads) + host_info->host_padding |= BIT(0); + + /* Vif_index must be filled in even without header conversion */ + host_info->vif_index = sw_txhdr->cl_sta->cl_vif->vif_index; + + /* Set the expected_ack flag */ + host_info->expected_ack = (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) ? + EXPECTED_NO_ACK : EXPECTED_ACK; + + if (key_conf) { + host_info->is_protected = true; + host_info->hw_key_idx = key_conf->hw_key_idx; + + if (!hdr_conv) + frame_len += key_conf->icv_len; + } + + host_info->packet_cnt = 1; + umacdesc->packet_len[0] = cpu_to_le16(frame_len); + + /* Set rate control */ + cl_rate_ctrl_update_desc_agg(cl_hw, host_info); +} + +static __le16 cl_tx_agg_frame_control(struct cl_vif *cl_vif, + struct ieee80211_key_conf *key_conf, + u8 *hdrlen) +{ + struct ieee80211_vif *vif = cl_vif->vif; + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); + enum nl80211_iftype type = vif->type; + __le16 fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA); + + if (type == NL80211_IFTYPE_AP) { + fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS); + *hdrlen = 26; + } else if (type == NL80211_IFTYPE_STATION) { + fc |= cpu_to_le16(IEEE80211_FCTL_TODS); + + if (sdata->u.mgd.use_4addr) { + fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS); + *hdrlen = 32; + } else { + *hdrlen = 26; + } + } + + if (key_conf) + fc |= cpu_to_le16(IEEE80211_FCTL_PROTECTED); + + return fc; +} + +static void _cl_tx_agg(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct sk_buff *skb, bool hdr_conv) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + struct ieee80211_key_conf *key_conf = tx_info->control.hw_key; + struct cl_sw_txhdr *sw_txhdr = NULL; + struct cl_tx_queue *tx_queue = NULL; + struct cl_vif *cl_vif = cl_sta->cl_vif; + u16 frame_len = (u16)skb->len; + u16 total_frame_len = 0; + u8 hdr_pads = CL_SKB_DATA_ALIGN_PADS(skb->data); + u8 is_amsdu = cl_tx_ctrl_is_amsdu(tx_info); + u8 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; + u8 ac = tid_to_ac[tid]; + u8 hdrlen = 0; + + cl_tx_cpu_agg(cl_hw); + + if (unlikely(!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) || + test_bit(CL_DEV_FW_ERROR, &cl_hw->drv_flags))) { + kfree_skb(skb); + cl_hw->tx_packet_cntr.drop.dev_flags++; + return; + } + + if (unlikely(!cl_vif->tx_en || cl_hw->tx_disable_flags)) { + kfree_skb(skb); + cl_hw->tx_packet_cntr.drop.tx_disable++; + return; + } + + /* Check if packet length exceeds max size */ + if (unlikely(frame_len > CL_TX_MAX_FRAME_LEN_AGG)) { + kfree_skb(skb); + cl_dbg_err(cl_hw, "frame_len exceeds max size %d\n", frame_len); + cl_hw->tx_packet_cntr.drop.length_limit++; + return; + } + + if (cl_sta->key_disable) { + kfree_skb(skb); + cl_hw->tx_packet_cntr.drop.key_disable++; + return; + } + + /* Check if amsdu is enable for current skb */ + if (is_amsdu) { + enum cl_amsdu_result amsdu_res = cl_tx_amsdu_set(cl_hw, cl_sta, skb, tid); + + switch (amsdu_res) { + case CL_AMSDU_SKIP: + is_amsdu = false; + tx_info->control.flags &= ~IEEE80211_TX_CTRL_AMSDU; + case CL_AMSDU_ANCHOR_SET: + /* + * If new anchor was set, or AMSDU is + * skipped continue building sw_txhdr + */ + break; + case CL_AMSDU_SUB_FRAME_SET: + cl_tx_sub_frame_set(cl_sta, tid); + fallthrough; + case CL_AMSDU_FAILED: + default: + return; + } + } else { + /* + * If not amsdu & anchor exist. reset current anchor + * in order to avoid reordring packets. + */ + if (cl_sta->amsdu_anchor[tid].sw_txhdr) + cl_tx_amsdu_anchor_init(&cl_sta->amsdu_anchor[tid]); + } + + /* Allocate sw_txhdr */ + sw_txhdr = cl_sw_txhdr_alloc(cl_hw); + if (unlikely(!sw_txhdr)) { + kfree_skb(skb); + cl_dbg_err(cl_hw, "sw_txhdr alloc failed\n"); + cl_hw->tx_packet_cntr.drop.txhdr_alloc_fail++; + return; + } + + /* Fill sw_txhdr */ + sw_txhdr->tid = tid; + sw_txhdr->ac = ac; + sw_txhdr->hw_queue = tx_info->hw_queue; + sw_txhdr->cl_sta = cl_sta; + sw_txhdr->sta_idx = cl_sta->sta_idx; + sw_txhdr->is_bcn = 0; + sw_txhdr->skb = skb; + sw_txhdr->map_len = frame_len + hdr_pads; + sw_txhdr->cl_vif = cl_vif; + + if (cl_sta->amsdu_anchor[tid].is_sw_amsdu) { + sw_txhdr->is_sw_amsdu = true; + sw_txhdr->sw_amsdu_packet_cnt = 1; + } else { + sw_txhdr->is_sw_amsdu = false; + } + + if (hdr_conv) { + sw_txhdr->hdr80211 = NULL; + sw_txhdr->fc = cl_tx_agg_frame_control(cl_vif, key_conf, &hdrlen); + } else { + struct ieee80211_hdr *hdr80211 = (struct ieee80211_hdr *)skb->data; + __le16 fc = hdr80211->frame_control; + + sw_txhdr->hdr80211 = hdr80211; + sw_txhdr->fc = fc; + hdrlen = ieee80211_hdrlen(fc); + } + + /* Fetch the relevant agg queue */ + tx_queue = cl_sta->agg_tx_queues[tid]; + + if (unlikely(!tx_queue)) { + kfree_skb(skb); + cl_sw_txhdr_free(cl_hw, sw_txhdr); + cl_dbg_err(cl_hw, "tx_queue is NULL [sta_idx = %u] [tid = %u]\n", + cl_sta->sta_idx, tid); + cl_hw->tx_packet_cntr.drop.queue_null++; + return; + } + + sw_txhdr->tx_queue = tx_queue; + + total_frame_len = frame_len + hdrlen - sizeof(struct ethhdr); + + if (key_conf) + total_frame_len += key_conf->icv_len; + + /* Prepare txdesc */ + cl_tx_agg_prep(cl_hw, sw_txhdr, frame_len, hdr_pads, hdr_conv); + + /* + * AMSDU - first sub frame + * !!! Must be done after calling cl_tx_agg_prep() !!! + */ + if (is_amsdu) + cl_tx_amsdu_first_sub_frame(sw_txhdr, cl_sta, skb, tid); + + cl_tx_send(cl_hw, sw_txhdr, &cl_sta->amsdu_anchor[tid]); +} + +void cl_tx_agg(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct sk_buff *skb, bool hdr_conv, bool lock) +{ + if (lock) { + spin_lock_bh(&cl_hw->tx_lock_agg); + _cl_tx_agg(cl_hw, cl_sta, skb, hdr_conv); + spin_unlock_bh(&cl_hw->tx_lock_agg); + } else { + _cl_tx_agg(cl_hw, cl_sta, skb, hdr_conv); + } +} + +static bool cl_tx_check_agg(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb) +{ + u16 ethertype = (skb->data[12] << 8) | skb->data[13]; + + /* Control port protocol needs a lot of special handling */ + if (cpu_to_be16(ethertype) == sdata->control_port_protocol) + return false; + + /* Only RFC 1042 SNAP */ + if (ethertype < ETH_P_802_3_MIN) + return false; + + /* Don't handle TX status request here either */ + if (skb->sk && skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) + return false; + + return true; +} + +static void cl_tx_reset_session_timer(struct sta_info *stainfo, u8 tid) +{ + struct tid_ampdu_tx *tid_tx = NULL; + + tid_tx = rcu_dereference(stainfo->ampdu_mlme.tid_tx[tid]); + + if (tid_tx && tid_tx->timeout) + tid_tx->last_tx = jiffies; +} + +void cl_tx_fast_agg(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct sk_buff *skb, bool lock) +{ + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + struct ieee80211_vif *vif = cl_sta->cl_vif->vif; + u16 ac = skb_get_queue_mapping(skb); + u8 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; + + tx_info->control.vif = vif; + tx_info->control.hw_key = cl_key_get(cl_sta); + tx_info->hw_queue = vif->hw_queue[ac]; + tx_info->flags |= IEEE80211_TX_CTL_AMPDU; + + if (cl_sta->baws[tid].amsdu && + (cl_wrs_api_get_sta_data_rate(cl_sta) > cl_hw->conf->ci_tx_amsdu_min_data_rate)) + tx_info->control.flags |= IEEE80211_TX_CTRL_AMSDU; + + cl_tx_update_stats(skb, cl_sta, ac, tid); + cl_tx_agg(cl_hw, cl_sta, skb, true, lock); + cl_tx_reset_session_timer(cl_sta->stainfo, tid); + cl_hw->tx_packet_cntr.forward.drv_fast_agg++; +} + +void cl_tx_wlan_to_8023(struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + struct ethhdr tmp_eth; + struct ethhdr *ehdr; + struct { + u8 hdr[ETH_ALEN]__aligned(2); + __be16 proto; + } payload; + u16 hdrlen = ieee80211_hdrlen(hdr->frame_control); + u8 enc_len = cl_key_get_cipher_len(skb); + + cl_mac_addr_copy(tmp_eth.h_dest, ieee80211_get_DA(hdr)); + cl_mac_addr_copy(tmp_eth.h_source, ieee80211_get_SA(hdr)); + skb_copy_bits(skb, hdrlen, &payload, sizeof(payload)); + tmp_eth.h_proto = payload.proto; + + if (enc_len) { + memcpy(skb->data + hdrlen, + skb->data + hdrlen + enc_len, + skb->len - hdrlen - enc_len); + skb_trim(skb, skb->len - enc_len); + } + + if (likely((ether_addr_equal(payload.hdr, rfc1042_header) && + tmp_eth.h_proto != htons(ETH_P_AARP) && + tmp_eth.h_proto != htons(ETH_P_IPX)) || + ether_addr_equal(payload.hdr, bridge_tunnel_header))) + /* Remove RFC1042 or Bridge-Tunnel encapsulation and replace ether_type */ + hdrlen += ETH_ALEN + 2; + else + tmp_eth.h_proto = htons(skb->len - hdrlen); + + skb_pull(skb, hdrlen); + ehdr = skb_push(skb, sizeof(struct ethhdr)); + memcpy(ehdr, &tmp_eth, sizeof(tmp_eth)); +} + +u16 cl_tx_prepare_wlan_hdr(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct sk_buff *skb, struct ieee80211_hdr *hdr) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(skb->dev); + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + u16 hdrlen = 0; + __le16 fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA); + + if (tx_info->control.hw_key) + fc |= cpu_to_le16(IEEE80211_FCTL_PROTECTED); + + switch (sdata->vif.type) { + case NL80211_IFTYPE_AP: + fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS); + /* DA BSSID SA */ + memcpy(hdr->addr1, skb->data, ETH_ALEN); + memcpy(hdr->addr2, sdata->vif.addr, ETH_ALEN); + memcpy(hdr->addr3, skb->data + ETH_ALEN, ETH_ALEN); + hdrlen = 24; + break; + case NL80211_IFTYPE_STATION: + if (sdata->u.mgd.use_4addr) { + fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS | + IEEE80211_FCTL_TODS); + /* RA TA DA SA */ + memcpy(hdr->addr1, sdata->u.mgd.bssid, ETH_ALEN); + memcpy(hdr->addr2, sdata->vif.addr, ETH_ALEN); + memcpy(hdr->addr3, skb->data, ETH_ALEN); + memcpy(hdr->addr4, skb->data + ETH_ALEN, ETH_ALEN); + hdrlen = 30; + } else { + fc |= cpu_to_le16(IEEE80211_FCTL_TODS); + /* BSSID SA DA */ + memcpy(hdr->addr1, sdata->u.mgd.bssid, ETH_ALEN); + memcpy(hdr->addr2, skb->data + ETH_ALEN, ETH_ALEN); + memcpy(hdr->addr3, skb->data, ETH_ALEN); + hdrlen = 24; + } + break; + default: + cl_dbg_err(cl_hw, "Unknown vif type %d !!!\n", sdata->vif.type); + return 0; + } + + if (cl_sta->stainfo->sta.wme) { + fc |= cpu_to_le16(IEEE80211_STYPE_QOS_DATA); + hdrlen += 2; + } + + hdr->frame_control = fc; + hdr->duration_id = 0; + hdr->seq_ctrl = 0; + + return hdrlen; +} + +int cl_tx_8023_to_wlan(struct cl_hw *cl_hw, struct sk_buff *skb, struct cl_sta *cl_sta, u8 tid) +{ + struct ieee80211_hdr hdr; + int head_need, ret = 0; + u16 ethertype, hdrlen; + const u8 *encaps_data = NULL; + int encaps_len = 0, skip_header_bytes = ETH_HLEN; + u8 enc_len = cl_key_get_cipher_len(skb); + + /* Convert Ethernet header to proper 802.11 header */ + ethertype = (skb->data[12] << 8) | skb->data[13]; + + hdrlen = cl_tx_prepare_wlan_hdr(cl_hw, cl_sta, skb, &hdr); + if (!hdrlen) { + ret = -EINVAL; + goto free; + } + + if (ethertype >= ETH_P_802_3_MIN) { + encaps_data = rfc1042_header; + encaps_len = sizeof(rfc1042_header); + skip_header_bytes -= 2; + } + + skb_pull(skb, skip_header_bytes); + head_need = hdrlen + enc_len + encaps_len - skb_headroom(skb); + + if (head_need > 0) { + head_need = ((head_need + 3) & ~3); + if (pskb_expand_head(skb, head_need, 0, GFP_ATOMIC)) { + ret = -ENOMEM; + goto free; + } + } + + if (encaps_data) + memcpy(skb_push(skb, encaps_len), encaps_data, encaps_len); + + skb_push(skb, hdrlen + enc_len); + + if (cl_sta->stainfo->sta.wme) { + u16 qos_ctrl = tid; + + memcpy(skb->data, &hdr, hdrlen - 2); + memcpy(skb->data + hdrlen - 2, &qos_ctrl, 2); + } else { + memcpy(skb->data, &hdr, hdrlen); + } + + skb_reset_mac_header(skb); + + return ret; +free: + cl_hw->tx_packet_cntr.drop.build_hdr_fail++; + kfree_skb(skb); + skb = NULL; + + return ret; +} + +void cl_tx_check_start_ba_session(struct cl_hw *cl_hw, + struct sta_info *stainfo, + struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + struct ieee80211_sta *sta = &stainfo->sta; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + u8 tid; + + /* TODO: What about HE? */ + if (!sta->ht_cap.ht_supported && + !sta->vht_cap.vht_supported && + !cl_band_is_6g(cl_hw)) + return; + + if (test_sta_flag(stainfo, WLAN_STA_PS_STA)) + return; + + if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && + !(tx_info->flags & IEEE80211_TX_STAT_AMPDU)) + return; + + if (cl_tx_ctrl_is_eapol(tx_info)) + return; + + if (unlikely(!ieee80211_is_data_qos(hdr->frame_control))) + return; + + if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) + return; + + tid = ieee80211_get_tid(hdr); + + if (likely(stainfo->ampdu_mlme.tid_tx[tid])) + return; + + ieee80211_start_tx_ba_session(sta, tid, cl_hw->conf->ce_tx_ba_session_timeout); +} + +static struct sk_buff *cl_tx_beacon_get(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct ieee80211_local *local = hw_to_local(hw); + struct sk_buff *skb = NULL; + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); + struct ieee80211_if_ap *ap = &sdata->u.ap; + struct beacon_data *beacon = rcu_dereference(ap->beacon); + + local->tim_in_locked_section = true; + if (beacon) { + if (beacon->cntdwn_counter_offsets[0] && + beacon->cntdwn_current_counter == 1) { + ieee80211_csa_finish(vif); + goto out; + } + } + + skb = ieee80211_beacon_get(hw, vif); +out: + local->tim_in_locked_section = false; + + return skb; +} + +static void cl_tx_mc(struct cl_vif *cl_vif, int *mc_fw_free) +{ + struct cl_hw *cl_hw = cl_vif->cl_hw; + struct ieee80211_vif *vif = cl_vif->vif; + struct sk_buff *skb = NULL; + struct ieee80211_tx_info *tx_info; + + if (unlikely(!vif)) + return; + + while (((*mc_fw_free) > 0) && + (skb = ieee80211_get_buffered_bc(cl_hw->hw, vif))) { + /* Route this MCBC frame to the BCN ipc queue */ + tx_info = IEEE80211_SKB_CB(skb); + tx_info->hw_queue = CL_HWQ_BCN; + + (*mc_fw_free)--; + + /* Clear more data bit if this is the last frame in this SP */ + if (*mc_fw_free == 0) { + struct ieee80211_hdr *hdr = + (struct ieee80211_hdr *)skb->data; + hdr->frame_control &= + cpu_to_le16(~IEEE80211_FCTL_MOREDATA); + } + + cl_tx_single(cl_hw, NULL, skb, false, true); + } +} + +void cl_tx_bcn_mesh_task(unsigned long data) +{ + struct cl_vif *cl_vif = (struct cl_vif *)data; + struct cl_hw *cl_hw = cl_vif->cl_hw; + struct ieee80211_tx_info *tx_info; + struct sk_buff *skb; + int mc_fw_free; + + if (cl_radio_is_off(cl_hw) || + cl_recovery_in_progress(cl_hw) || + !test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) || + test_bit(CL_DEV_FW_ERROR, &cl_hw->drv_flags) || + cl_hw->tx_disable_flags) + return; + + skb = cl_tx_beacon_get(cl_hw->hw, cl_vif->vif); + if (!skb) + return; + + /* Route this BCN to the BCN ipc queue */ + tx_info = IEEE80211_SKB_CB(skb); + tx_info->hw_queue = CL_HWQ_BCN; + + cl_tx_single(cl_hw, NULL, skb, false, true); + + mc_fw_free = cl_hw->tx_queues.bcmc.fw_free_space; + cl_tx_mc(cl_vif, &mc_fw_free); +} + +static void cl_tx_bcn(struct cl_vif *cl_vif) +{ + struct cl_hw *cl_hw = cl_vif->cl_hw; + u8 vif_index = cl_vif->vif_index; + struct ieee80211_vif *vif = cl_vif->vif; + struct ieee80211_tx_info *tx_info; + struct sk_buff *skb; + struct ieee80211_sub_if_data *sdata = NULL; + + if (!vif || vif->type != NL80211_IFTYPE_AP) + return; + + sdata = vif_to_sdata(vif); + /* TODO: Check if this is really needed */ + sdata->u.ap.ps.dtim_count = + cl_hw->ipc_env->ring_indices_elem->indices->dtim_count[vif_index]; + + /* + * If we are in the middle of the CAC, we allow regular channel switch + * and retrigger the CAC (If needed). + */ + if (cl_dfs_is_in_cac(cl_hw) && vif->csa_active) { + /* + * TODO: if radar is detected, we wait for all CSAs to be transmitted, + * before allowing channel switch + */ + + ieee80211_csa_finish(vif); + return; + } + + skb = cl_tx_beacon_get(cl_hw->hw, vif); + if (!skb) + return; + + /* Route this BCN to the BCN ipc queue */ + tx_info = IEEE80211_SKB_CB(skb); + tx_info->hw_queue = CL_HWQ_BCN; + + cl_tx_single(cl_hw, NULL, skb, false, true); +} + +/* Cl_tx_bcns - generate BCNs and TX buffered MC frames each BCN DTIM interval + * + * Beacons are sent first followed by cyclic MC for fairness between VIF's + * the FW buffer is restricted to "IPC_TXDESC_CNT_BCMC" buffer size. + */ +void cl_tx_bcns(struct cl_hw *cl_hw) +{ + struct cl_vif *cl_vif = NULL; + int mc_fw_free = 0; + + /* Don't send beacons during scan */ + if (cl_channel_is_scan_active(cl_hw)) + return; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) + cl_tx_bcn(cl_vif); + + cl_vif = cl_hw->mc_vif; + mc_fw_free = cl_hw->tx_queues.bcmc.fw_free_space; + + do { + cl_tx_mc(cl_vif, &mc_fw_free); + /* Cl_vif_get_next() is cyclic */ + cl_vif = cl_vif_get_next(cl_hw, cl_vif); + } while ((cl_vif != cl_hw->mc_vif) && mc_fw_free); + + cl_hw->mc_vif = cl_vif_get_next(cl_hw, cl_hw->mc_vif); +} + +void cl_tx_en(struct cl_hw *cl_hw, u8 reason, bool enable) +{ + unsigned long tx_disable_flags_prev = cl_hw->tx_disable_flags; + + if (enable) { + clear_bit(reason, &cl_hw->tx_disable_flags); + + if (tx_disable_flags_prev != 0 && cl_hw->tx_disable_flags == 0) + if (cl_hw->conf->ci_backup_bcn_en) + cl_msg_tx_backup_bcn_en(cl_hw, true); + } else { + set_bit(reason, &cl_hw->tx_disable_flags); + + if (tx_disable_flags_prev == 0) + if (cl_hw->conf->ci_backup_bcn_en) + cl_msg_tx_backup_bcn_en(cl_hw, false); + } +} + +static void cl_tx_flush(struct cl_hw *cl_hw) +{ + unsigned long flags; + + /* Flush bcmc */ + spin_lock_irqsave(&cl_hw->tx_lock_bcmc, flags); + cl_bcmc_cfm_flush_queue(cl_hw); + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); + + /* Flush single */ + spin_lock_bh(&cl_hw->tx_lock_single); + cl_txq_flush_all_single(cl_hw); + cl_single_cfm_flush_all(cl_hw); + spin_unlock_bh(&cl_hw->tx_lock_single); + + /* Flush agg */ + spin_lock_bh(&cl_hw->tx_lock_agg); + cl_txq_flush_all_agg(cl_hw); + cl_agg_cfm_flush_all(cl_hw); + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +void cl_tx_off(struct cl_hw *cl_hw) +{ + cl_tx_stop_remote_cpu(cl_hw); + cl_txq_stop(cl_hw); + cl_tx_flush(cl_hw); +} + +static void cl_tx_set_mapping(struct cl_hw *cl_hw, struct sk_buff *skb, struct net_device *dev) +{ + struct cl_vif *cl_vif = NETDEV_TO_CL_VIF(dev); + u8 vif_index = cl_vif->vif_index; + + if (!cl_hw->conf->ha_wmm_enabled[vif_index]) { + skb->priority = 0; + goto set_queue_mapping; + } + + if (cl_vlan_dscp_is_enabled(cl_hw, cl_vif)) { + skb->priority = cl_vlan_dscp_check_ether_type(cl_hw, skb, vif_index); + } else { + /* + * TODO: IPv6 support + * TODO: VLAN user priority support + */ + + u8 i = 0, dcsp_val = 0, *src_buf = NULL; + u16 ether_type = get_ether_type(2 * ETH_ALEN, skb->data); + + /* Patch until IPv6 will be supported - set priority to 0 */ + if (ether_type != ETH_P_IP) { + skb->priority = 0; + goto set_queue_mapping; + } + + src_buf = skb->data; + src_buf += ETH_HLEN; + dcsp_val = (*(src_buf + 1) & 0xec) >> 2; + + for (i = 0; i < TID_MAX; i++) + if (dscp_to_up[i] == dcsp_val) { + skb->priority = i; + break; + } + } + +set_queue_mapping: + skb_set_queue_mapping(skb, ieee802_1d_to_ac[skb->priority]); +} + +static bool cl_tx_packet_limit(struct cl_hw *cl_hw, struct sk_buff *skb) +{ + if (cl_hw->conf->ci_tx_packet_limit > 0) + return (atomic_read(&cl_hw->tx_packet_count) >= cl_hw->conf->ci_tx_packet_limit); + + return false; +} + +static void cl_tx_destructor(struct sk_buff *skb) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(skb->dev); + struct cl_hw *cl_hw = sdata->local->hw.priv; + + atomic_dec(&cl_hw->tx_packet_count); +} + +void cl_tx_drop_dkb(struct sk_buff *skb) +{ + skb->dev->stats.rx_dropped++; + kfree_skb(skb); +} + +static netdev_tx_t _____cl_tx_start(struct cl_hw *cl_hw, struct sk_buff *skb, + struct net_device *dev, struct cl_sta *cl_sta) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_vif *vif = &sdata->vif; + struct cl_vif *cl_vif = (struct cl_vif *)vif->drv_priv; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + int buffer_cnt = 0; + u8 hw_queue = vif->hw_queue[skb_get_queue_mapping(skb)]; + + cl_hw->tx_packet_cntr.forward.tx_start++; + + if (cl_hw->wd_restart_drv) { + cl_hw->tx_packet_cntr.drop.wd_restart++; + cl_tx_drop_dkb(skb); + return NETDEV_TX_OK; + } + + if (cl_radio_is_off(cl_hw)) { + cl_hw->tx_packet_cntr.drop.radio_off++; + cl_tx_drop_dkb(skb); + return NETDEV_TX_OK; + } + + if (cl_recovery_in_progress(cl_hw)) { + cl_hw->tx_packet_cntr.drop.in_recovery++; + cl_tx_drop_dkb(skb); + return NETDEV_TX_OK; + } + + if (skb->len < ETH_HLEN) { + cl_hw->tx_packet_cntr.drop.short_length++; + cl_tx_drop_dkb(skb); + return NETDEV_TX_OK; + } + + if (skb_queue_len(&sdata->local->pending[hw_queue]) >= + cl_hw->conf->ci_pending_queue_size) { + cl_hw->tx_packet_cntr.drop.pending_full++; + cl_tx_drop_dkb(skb); + tasklet_schedule(&sdata->local->tx_pending_tasklet); + return NETDEV_TX_OK; + } + + /* Limit total packets for TX */ + if (cl_tx_packet_limit(cl_hw, skb)) { + cl_hw->tx_packet_cntr.drop.packet_limit++; + cl_tx_drop_dkb(skb); + return NETDEV_TX_OK; + } + + if (!skb->destructor) { + skb->destructor = cl_tx_destructor; + buffer_cnt = atomic_inc_return(&cl_hw->tx_packet_count); + } + + memset(tx_info, 0, sizeof(struct ieee80211_tx_info)); + +#ifdef TRACE_SUPPORT + trace_cl_trace_tx_start(cl_hw->idx, skb, buffer_cnt); +#endif + if (cl_sta && cl_sta->stainfo && + (test_sta_flag(cl_sta->stainfo, WLAN_STA_AUTHORIZED))) { + u8 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; + bool is_agg = cl_tx_check_agg(sdata, skb); + + cl_traffic_tx_handler(cl_hw, cl_sta, skb->len); + + if (!ieee80211_vif_is_mesh(&sdata->vif)) { + if (is_agg && cl_sta->agg_tx_queues[tid]) + cl_tx_fast_agg(cl_hw, cl_sta, skb, true); + else if (is_agg && cl_sta->baws[tid].action_start) + __skb_queue_tail(&cl_sta->baws[tid].pending, skb); + else + cl_tx_fast_single(cl_hw, cl_sta, skb, true); + + return NETDEV_TX_OK; + } + } + + cl_hw->tx_packet_cntr.forward.to_mac++; + cl_vif->orig_dev_ops->ndo_start_xmit(skb, dev); + + return NETDEV_TX_OK; +} + +netdev_tx_t ____cl_tx_start(struct cl_hw *cl_hw, struct sk_buff *skb, struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct cl_sta *cl_sta; + + cl_sta_lock(cl_hw); + + if (sdata->vif.type == NL80211_IFTYPE_STATION) + cl_sta = cl_sta_get_by_addr(cl_hw, sdata->u.mgd.bssid); + else + cl_sta = cl_sta_get_by_addr(cl_hw, skb->data); + + if (cl_sta) { + netdev_tx_t ret = _____cl_tx_start(cl_hw, skb, dev, cl_sta); + + cl_sta_unlock(cl_hw); + return ret; + } + + cl_sta_unlock(cl_hw); + return _____cl_tx_start(cl_hw, skb, dev, NULL); +} + +netdev_tx_t ___cl_tx_start(struct cl_hw *cl_hw, struct sk_buff *skb, struct net_device *dev) +{ + skb->dev = dev; + cl_tx_set_mapping(cl_hw, skb, dev); + + return ____cl_tx_start(cl_hw, skb, dev); +} + +netdev_tx_t __cl_tx_start(struct cl_hw *cl_hw, struct sk_buff *skb, struct net_device *dev) +{ + if (!skb_mac_header_was_set(skb)) + skb_reset_mac_header(skb); + + return ___cl_tx_start(cl_hw, skb, dev); +} + +netdev_tx_t _cl_tx_start(struct cl_hw *cl_hw, struct sk_buff *skb, struct net_device *dev) +{ + int cpu = cl_hw->conf->ci_tx_remote_cpu; + + if (cpu == -1) + return __cl_tx_start(cl_hw, skb, dev); + + skb->dev = dev; + cl_tx_remote_cpu(cl_hw, skb, cpu); + return NETDEV_TX_OK; +} + +netdev_tx_t cl_tx_start(struct sk_buff *skb, struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct cl_hw *cl_hw = sdata->local->hw.priv; + + return _cl_tx_start(cl_hw, skb, dev); +} + From patchwork Thu Jun 17 16:01:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0E06C48BE5 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/tx/tx_amsdu.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/tx_amsdu.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/tx_amsdu.h b/drivers/net/wireless/celeno/cl8k/tx/tx_amsdu.h new file mode 100644 index 000000000000..efabed0c561c --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/tx_amsdu.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TX_AMSDU_H +#define CL_TX_AMSDU_H + +#include "sta.h" + +enum cl_amsdu_result { + CL_AMSDU_ANCHOR_SET, + CL_AMSDU_SUB_FRAME_SET, + CL_AMSDU_SKIP, + CL_AMSDU_FAILED +}; + +/* Max size of 802.11 WLAN header */ +#define CL_WLAN_HEADER_MAX_SIZE 36 + +#define CL_AMSDU_MIN_AGG_SIZE 3 +#define CL_AMSDU_CONST_LEN 256 + +struct cl_amsdu_txhdr { + struct list_head list; + struct list_head list_pool; + struct sk_buff *skb; + dma_addr_t dma_addr; +}; + +void cl_tx_amsdu_anchor_init(struct cl_amsdu_ctrl *amsdu_anchor); +void cl_tx_amsdu_anchor_reset(struct cl_amsdu_ctrl *amsdu_anchor); +void cl_tx_amsdu_set_max_len(struct cl_hw *cl_hw, struct cl_sta *cl_sta, u8 tid); +void cl_tx_amsdu_first_sub_frame(struct cl_sw_txhdr *sw_txhdr, struct cl_sta *cl_sta, + struct sk_buff *skb, u8 tid); +void cl_tx_amsdu_flush_sub_frames(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr); +void cl_tx_amsdu_transfer_single(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr); +int cl_tx_amsdu_set(struct cl_hw *cl_hw, struct cl_sta *cl_sta, struct sk_buff *skb, u8 tid); +void cl_tx_amsdu_unset(struct cl_sw_txhdr *sw_txhdr); + +int cl_tx_amsdu_txhdr_init(struct cl_hw *cl_hw); +void cl_tx_amsdu_txhdr_deinit(struct cl_hw *cl_hw); +void cl_tx_amsdu_txhdr_free(struct cl_hw *cl_hw, struct cl_amsdu_txhdr *amsdu_txhdr); + +#endif /* CL_TX_AMSDU_H */ From patchwork Thu Jun 17 16:01:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14BE2C49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 218/256] cl8k: add tx/tx_queue.c Date: Thu, 17 Jun 2021 16:01:45 +0000 Message-Id: <20210617160223.160998-219-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:36 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 10547838-7774-48b5-7c02-08d931a9e287 X-MS-TrafficTypeDiagnostic: AM9P192MB1329: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DaS20mFmAFQTMI0gRY9qOzYMnn9CjSFvgsqQdFbRYTzQxpCzxp49GZBJXml1B8omrisp1VV5pbxHoPDEDeE4zEiovofekt8NYJ8pa5NK4TlxfCoyDj+m3Rugvq3VIOmcWUGxoVQxh1Q16HmNfufZ464ElP+K3pokqA18Rrm1jf4CHRWN1e+1eJwatewwW/xZ06kolnzpJUBsTSbDI/GxpMBKDpwjaAjoUHlImFHni0KxCtki6PylOXFybb2xEdZKIYCupxVOadQgDgMS8gVUfUzO9isQ+sJUQVgVHMAun0KKlpHsPDJ7EEgKF0HxZbcMxfdpbcJUaN9EWqsIyEWGEvCu1EyiQmxdLax8uZM1bVaoHpJQFHfI6Gw/RFYwmgodV/8S0s5Ec3qD9qvpGfoxzyBcoTQ/7QbUfjJoXtIGuJGEA6YuaCozzMvRLUcs7YGUB58aAbGE8ED8j34uOeuRdkhTF9gGOgxWjeR5qCEzFnq/egj/UPBJqu28GC1huIGsQ10f18T2qB+tXulaOt6VCxPiJGt7gJmN/Z5DHqQVdwu311XTZa7xxBJ0liGdNUlMzVSh5+o2BiuvAEuCUsr762+rybDxd+W8o9NGDY/TvzXqw4pHBcHCHoYqifkbLBLd/1AkM6MVPuJFwBxZXY+yVeAokOkxLz4uDhsE/xI9NJ7rdC3o4oKZIAIlCSbF/Mwnp2nWQSzQ+UTNHVIB+Twmhw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(39850400004)(376002)(136003)(346002)(396003)(86362001)(38350700002)(8936002)(38100700002)(6916009)(52116002)(6486002)(55236004)(54906003)(36756003)(6506007)(956004)(4326008)(30864003)(186003)(2616005)(1076003)(478600001)(26005)(16526019)(107886003)(6666004)(66556008)(83380400001)(5660300002)(2906002)(6512007)(9686003)(8676002)(316002)(66476007)(66946007)(69590400013)(32563001)(559001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5cVPC7L9oe3+WYB+vpmuOhiZTZX+IUXr4tbCarpNrcLrGPzJ5sCvBPgk1aTJ7uA2+y3o5c60pjQd6zpFk3YeNhTHGlndasOJpHn391spd19Kikhtj58NSwSQePx8jqo0ahYxaQH5tXDPNnxvLTUg321dnOH1OSPk79zZAmleOrTVMrbWgFTaqU9vj7ROrA/PMfCuvg9b50jbI1kAD4VrqNKITJW8ET5IyQEBwXtHO1/onXecwknOtkYkE6OX6Sli0Ik5pyylCYGqQOw2LM9YEqKhdhOJbJGRxV+GVcmWXi5TT/pUa/ldfmwJmYXEdi7XOYXkQuXBo7W8/W1muj8vSNLt9pfQ6Hbt/12+v6cMtKrJ6G/VNppthcB7sazowagGBzAkDC5dVwqDNpObLth59hyPXz5rtlf3VSOkGDZiWOn29apDe9IsLdRJFycT52wHaXtJF8CfGJ382NhFegIFBBJwGDse8FRsZTpgk3HDkbe/8bT56x7KgJrtLH2UWGqFXVCDYbj5cC/JFASzluBBAm0ZWCDUEiaLlpmHhohIxlmUtLEWAJo4P1YjC1/jBmc+F8OimqiA39GKrAZ8QMQqlEASwB8j2U5frQLvokE2CvsMxsyEHUXKf1My+ZZQ4cpMcR6QvGsbvhvLpn9uMb79YYbwGUqBthOF8I3SvylyL3COdnXJkzDJVbVgxvpgciE75oTxhYmW/evKI4TRCT2tWzjbPGRe/x5MsxvPSXlFRN09oCHcsQbqkrULl2U4cXBKf8KhnxkK/zNNnyzYxbYCL8LRHG2IYqhS1bmNGRNdSzeB2rnhI1g8aN0sC/NR0Hyd03702w3dE4bl+dy4ITtD0AZPsTjRsQQppKxmsU9j16hwdrtFPL7CaJ/j1N156XN7A9Xpf/9Rm69w2nmHCn0CG0NaWvHx6BSobw5jt33Jk53kyklqGFXnwJLY0T+ski7vYDgpBpoNbmBHqZox2fM/PDVgh+ZyTUwC04sy9kontfV0qnA2RUyFXPiOKJ3snPWJ63kKcfmJEBe8qciKC4k9s42QrNmqG2WJbxYhyBVpf3hvI9PesK/7GuLaT1HOuqL4knue65QK3Uq7h5UfX4fzyMsvYIIiaUHQGCsUB11FsqNoDuFHN0ERRIpqppOfgKVlvXHS5soj05pbVg6mo/NARvyJlF4DY+du8MhqT+uKbcZSqQZ3h/uuoNgo8fAP0U5k0pobvf3jGCin2ivmy6+Ry2nPgeWzhopXJSgImxOYMtC7vvs+eQNioQUMW74036OLjb6u0Agp64u4BVCX9RykNc6nWBJu84cAlu7xFECXXYZ6dNl/X0eXX0CO8gWnt5jp X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 10547838-7774-48b5-7c02-08d931a9e287 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:37.6418 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xBEkYn8pakiTrGEA/zLDOt+COwgw4s1fdS5mTPOiHRr5t2EKnN4g5puvYV029xdNQpL8cANlKYJ21wD2MHlsCA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1329 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/tx/tx_queue.c | 1620 +++++++++++++++++ 1 file changed, 1620 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/tx_queue.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/tx_queue.c b/drivers/net/wireless/celeno/cl8k/tx/tx_queue.c new file mode 100644 index 000000000000..18c5bd2b81f7 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/tx_queue.c @@ -0,0 +1,1620 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include +#include +#include + +#include "tx/tx_queue.h" +#include "tx/tx.h" +#include "tx/sw_txhdr.h" +#include "tx/tx_amsdu.h" +#include "tx/baw.h" +#ifdef CONFIG_CL_PCIE +#include "bus/pci/ipc.h" +#endif +#include "tx/agg_cfm.h" + +const u8 cl_tid2hwq[IEEE80211_NUM_TIDS] = { + CL_HWQ_BE, + CL_HWQ_BK, + CL_HWQ_BK, + CL_HWQ_BE, + CL_HWQ_VI, + CL_HWQ_VI, + CL_HWQ_VO, + CL_HWQ_VO, + /* At the moment, all others TID are mapped to BE */ + CL_HWQ_BE, + CL_HWQ_BE, + CL_HWQ_BE, + CL_HWQ_BE, + CL_HWQ_BE, + CL_HWQ_BE, + CL_HWQ_BE, + CL_HWQ_BE, +}; + +static u32 cl_txq_total_dump_drv(struct cl_tx_queue *tx_queue) +{ + return tx_queue->dump_queue_full + tx_queue->dump_dma_map_fail; +} + +static void cl_txq_sched_list_add(struct cl_tx_queue *tx_queue, struct cl_hw *cl_hw) +{ + /* Add to schedule queue */ + if (tx_queue->sched) + return; + + tx_queue->sched = true; + if (tx_queue->type == QUEUE_TYPE_AGG) + list_add_tail(&tx_queue->sched_list, &cl_hw->list_sched_q_agg); + else + list_add_tail(&tx_queue->sched_list, &cl_hw->list_sched_q_single); +} + +static void cl_txq_sched_list_remove(struct cl_tx_queue *tx_queue) +{ + /* Remove from schedule queue */ + if (tx_queue->sched) { + tx_queue->sched = false; + list_del(&tx_queue->sched_list); + } +} + +static void cl_txq_sched_list_remove_if_empty(struct cl_tx_queue *tx_queue) +{ + /* If queue is empty remove it from schedule list */ + if (list_empty(&tx_queue->hdrs)) + cl_txq_sched_list_remove(tx_queue); +} + +static void cl_txq_transfer_single_to_agg(struct cl_hw *cl_hw, + struct cl_tx_queue *single_queue, + struct cl_tx_queue *agg_queue, u8 tid) +{ + struct cl_sw_txhdr *sw_txhdr, *sw_txhdr_tmp; + struct ieee80211_tx_info *tx_info; + struct sk_buff *skb; + u8 hdr_pads; + + spin_lock_bh(&cl_hw->tx_lock_single); + + if (single_queue->num_packets == 0) + goto out; + + list_for_each_entry_safe(sw_txhdr, sw_txhdr_tmp, &single_queue->hdrs, tx_queue_list) { + if (sw_txhdr->tid != tid) + continue; + + if (!ieee80211_is_data_qos(sw_txhdr->fc)) + continue; + + cl_hw->tx_packet_cntr.transfer.single_to_agg++; + + /* Remove from single queue */ + list_del(&sw_txhdr->tx_queue_list); + + /* Update single queue counters */ + single_queue->num_packets--; + single_queue->total_packets--; + + /* Turn on AMPDU flag */ + skb = sw_txhdr->skb; + tx_info = IEEE80211_SKB_CB(skb); + tx_info->flags |= IEEE80211_TX_CTL_AMPDU; + + /* Push skb to agg queue */ + hdr_pads = CL_SKB_DATA_ALIGN_PADS(skb->data); + cl_tx_agg_prep(cl_hw, sw_txhdr, skb->len, hdr_pads, false); + agg_queue->total_packets++; + sw_txhdr->tx_queue = agg_queue; + cl_txq_push(cl_hw, sw_txhdr); + } + + /* If single queue is empty remove it from schedule list */ + cl_txq_sched_list_remove_if_empty(single_queue); + +out: + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +static void cl_txq_delete_packets(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue, u8 sta_idx) +{ + struct cl_sw_txhdr *sw_txhdr, *sw_txhdr_tmp; + + list_for_each_entry_safe(sw_txhdr, sw_txhdr_tmp, &tx_queue->hdrs, tx_queue_list) { + /* + * Brodcast frames do not have cl_sta and should not be + * deleted at station remove sequence. + */ + if (!sw_txhdr->cl_sta) + continue; + + if (sw_txhdr->sta_idx != sta_idx) + continue; + + list_del(&sw_txhdr->tx_queue_list); + tx_queue->num_packets--; + + cl_tx_single_free_skb(cl_hw, sw_txhdr->skb); + cl_sw_txhdr_free(cl_hw, sw_txhdr); + } + + /* If queue is empty remove it from schedule list */ + cl_txq_sched_list_remove_if_empty(tx_queue); +} + +static void cl_txq_reset_counters(struct cl_tx_queue *tx_queue) +{ + tx_queue->total_fw_push_desc = 0; + tx_queue->total_fw_push_skb = 0; + tx_queue->total_fw_cfm = 0; + tx_queue->total_packets = 0; + tx_queue->dump_queue_full = 0; + tx_queue->dump_dma_map_fail = 0; + + memset(tx_queue->stats_hw_amsdu_cnt, 0, + sizeof(tx_queue->stats_hw_amsdu_cnt)); + + memset(tx_queue->stats_sw_amsdu_cnt, 0, + sizeof(tx_queue->stats_sw_amsdu_cnt)); +} + +static u16 cl_txq_desc_in_fw(struct cl_tx_queue *tx_queue) +{ + return (tx_queue->fw_max_size - tx_queue->fw_free_space); +} + +static void cl_txq_reset_counters_during_traffic(struct cl_tx_queue *tx_queue) +{ + /* + * This function can be called during traffic, while descriptors + * are waiting in firmware. We set total_fw_cfm to minus the number + * of descriptors in firmware so that after confirmation arrives + * total_fw_cfm will be equal to total_fw_push_desc. + */ + u32 desc_in_fw = cl_txq_desc_in_fw(tx_queue); + + cl_txq_reset_counters(tx_queue); + tx_queue->total_fw_cfm = -desc_in_fw; +} + +static void cl_txq_agg_size_set(struct cl_hw *cl_hw) +{ + struct cl_tx_queue *tx_queue = NULL; + u16 new_size = 0; + u16 drv_max_size = 0; + int i = 0; + int j = 0; + + if (!cl_hw->used_agg_queues || !cl_hw->conf->ci_tx_packet_limit) + return; + + new_size = cl_hw->conf->ci_tx_packet_limit / cl_hw->used_agg_queues; + drv_max_size = max(new_size, cl_hw->conf->ci_tx_queue_size_agg); + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + tx_queue = &cl_hw->tx_queues.agg[i]; + + if (!tx_queue->cl_sta) + continue; + + tx_queue->max_packets = drv_max_size; + + j++; + if (j == cl_hw->used_agg_queues) + break; + } + + cl_dbg_trace(cl_hw, "drv_max_size = %u\n", drv_max_size); +} + +static int cl_txq_request_find(struct cl_hw *cl_hw, u8 sta_idx, u8 tid) +{ + int i = 0; + struct cl_req_agg_db *req_agg_db = NULL; + u8 req_agg_queues = 0; + + for (i = 0; (i < IPC_MAX_BA_SESSIONS) && (req_agg_queues < cl_hw->req_agg_queues); i++) { + req_agg_db = &cl_hw->req_agg_db[i]; + + if (!req_agg_db->is_used) + continue; + + req_agg_queues++; + + if (sta_idx == req_agg_db->sta_idx && tid == req_agg_db->tid) + return i; + } + + return -1; +} + +static void cl_txq_traffic_counters_print_bcmc(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + struct cl_tx_queue *tx_queue = &cl_hw->tx_queues.bcmc; + unsigned long flags; + u8 hw_index; + u32 total_packets; + u16 fw_curr; + u32 total_push; + u32 total_cfm; + u32 dump; + + spin_lock_irqsave(&cl_hw->tx_lock_bcmc, flags); + + hw_index = tx_queue->hw_index; + total_packets = tx_queue->total_packets; + fw_curr = cl_txq_desc_in_fw(tx_queue); + total_push = tx_queue->total_fw_push_skb; + total_cfm = tx_queue->total_fw_cfm; + dump = cl_txq_total_dump_drv(tx_queue); + + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); + + if (total_packets == 0) + return; + + cl_snprintf(buf, len, buf_size, + "\nTX MULTICAST AND BOROADCAST QUEUE (MAX 1):\n" + "|-----------------------------------------------------------|\n" + "| hw | driver | fw | fw total | fw total | dump |\n" + "| idx | total | current | push | cfm | |\n" + "|-----+----------+---------+----------+----------+----------|\n" + "| %3u |%10u|%9u|%10u|%10u|%10u|\n", + hw_index, total_packets, fw_curr, total_push, total_cfm, dump); + cl_snprintf(buf, len, buf_size, + "|-----------------------------------------------------------|\n"); +} + +static void cl_txq_traffic_counters_print_single(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u16 queue_idx = 0; + u32 sta_idx = 0, ac = 0; + struct cl_tx_queue *tx_queue; + + cl_snprintf(buf, len, buf_size, + "\nTX SINGLE QUEUES (MAX %d):\n", MAX_SINGLE_QUEUES); + cl_snprintf(buf, len, buf_size, + "|----------------------------------------------------------------------" + "----------|\n" + "| idx | sta | ac | driver | driver | fw | fw total | fw total |" + " dump |\n" + "| | | | total | current | current | push | cfm |" + " |\n" + "|-----+-----+----+----------+---------+---------+----------+----------+" + "----------|\n"); + + spin_lock_bh(&cl_hw->tx_lock_single); + + for (sta_idx = 0; sta_idx < FW_MAX_NUM_STA; sta_idx++) { + for (ac = 0; ac < AC_MAX; ac++) { + queue_idx = QUEUE_IDX(sta_idx, ac); + tx_queue = &cl_hw->tx_queues.single[queue_idx]; + + if (tx_queue->total_packets == 0) + continue; + + if (tx_queue->index == HIGH_PRIORITY_QUEUE) + cl_snprintf(buf, len, buf_size, + "|-----+-----+----+----------+---------+---------+" + "----------+----------+----------|\n"); + + cl_snprintf(buf, len, buf_size, + "| %3u | %3u | %2u |%10u|%9u|%9u|%10u|%10u|%10u|\n", + tx_queue->index, + sta_idx, + tx_queue->hw_index, + tx_queue->total_packets, + tx_queue->num_packets, + cl_txq_desc_in_fw(tx_queue), + tx_queue->total_fw_push_skb, + tx_queue->total_fw_cfm, + cl_txq_total_dump_drv(tx_queue)); + } + } + + cl_snprintf(buf, len, buf_size, + "|------------------------------------------------------------------------" + "--------|\n"); + + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +static void cl_txq_traffic_counters_print_agg(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u32 ba_idx = 0; + struct cl_tx_queue *tx_queue; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + if (cl_hw->used_agg_queues == 0) + goto out; + + cl_snprintf(buf, len, buf_size, + "\nTX AGGREGATION QUEUES (MAX %d):\n", IPC_MAX_BA_SESSIONS); + cl_snprintf(buf, len, buf_size, + "|-----------------------------------------------------------------------" + "---------------------|\n" + "| idx | sta | tid | driver | driver | fw | fw total | fw total |" + " fw total | dump |\n" + "| | idx | | total | current | current | push skb | push desc|" + " cfm | |\n" + "|-----+-----+-----+----------+---------+---------+----------+----------+" + "----------+----------|\n"); + + for (ba_idx = 0; ba_idx < IPC_MAX_BA_SESSIONS; ba_idx++) { + tx_queue = &cl_hw->tx_queues.agg[ba_idx]; + + if (!cl_hw->tx_queues.agg[ba_idx].cl_sta) + continue; + + if (tx_queue->total_packets == 0) + continue; + + cl_snprintf(buf, len, buf_size, + "| %3u | %3u | %3u |%10u|%9u|%9u|%10u|%10u|%10u|%10u|\n", + tx_queue->index, + tx_queue->cl_sta->sta_idx, + tx_queue->tid, + tx_queue->total_packets, + tx_queue->num_packets, + cl_txq_desc_in_fw(tx_queue), + tx_queue->total_fw_push_skb, + tx_queue->total_fw_push_desc, + tx_queue->total_fw_cfm, + cl_txq_total_dump_drv(tx_queue)); + } + + cl_snprintf(buf, len, buf_size, + "|------------------------------------------------------------------------" + "--------------------|\n"); + +out: + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +static void cl_txq_traffic_counters_print_mac(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + struct ieee80211_local *local = hw_to_local(cl_hw->hw); + u32 i = 0, total_len = 0, q_len[IEEE80211_MAX_QUEUES] = {0}; + unsigned long flags; + + spin_lock_irqsave(&local->queue_stop_reason_lock, flags); + + for (i = 0; i < IEEE80211_MAX_QUEUES; i++) { + q_len[i] = skb_queue_len(&local->pending[i]); + total_len += q_len[i]; + } + + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); + + if (total_len == 0) + return; + + cl_snprintf(buf, len, buf_size, + "\nMAC80211 PENDING QUEUES (MAX %d):\n", IEEE80211_MAX_QUEUES); + cl_snprintf(buf, len, buf_size, + "|--------------------|\n" + "| queue | current |\n" + "|-------+------------|\n"); + + for (i = 0; i < IEEE80211_MAX_QUEUES; i++) + if (q_len[i] > 0) + cl_snprintf(buf, len, buf_size, "| %5u | %10u |\n", i, q_len[i]); + + cl_snprintf(buf, len, buf_size, "|--------------------|\n"); +} + +static int cl_txq_traffic_counters_print(struct cl_hw *cl_hw) +{ + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_txq_traffic_counters_print_bcmc(cl_hw, &buf, &len, &buf_size); + cl_txq_traffic_counters_print_single(cl_hw, &buf, &len, &buf_size); + cl_txq_traffic_counters_print_agg(cl_hw, &buf, &len, &buf_size); + cl_txq_traffic_counters_print_mac(cl_hw, &buf, &len, &buf_size); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static void cl_txq_drop_reasons_print_bcmc(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u32 total = 0; + u32 dump_queue_full = 0; + u32 dump_dma_map_fail = 0; + struct cl_tx_queue *tx_queue = &cl_hw->tx_queues.bcmc; + unsigned long flags; + + spin_lock_irqsave(&cl_hw->tx_lock_bcmc, flags); + + total = cl_txq_total_dump_drv(tx_queue); + dump_queue_full = tx_queue->dump_queue_full; + dump_dma_map_fail = tx_queue->dump_dma_map_fail; + + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); + + if (total > 0) + cl_snprintf(buf, len, buf_size, + "|bcmc | |%10u|%10u|%10u|\n", + dump_queue_full, dump_dma_map_fail, total); +} + +static void cl_txq_drop_reasons_print_single(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u32 i = 0, total = 0; + struct cl_tx_queue *tx_queue; + + spin_lock_bh(&cl_hw->tx_lock_single); + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) { + tx_queue = &cl_hw->tx_queues.single[i]; + total = cl_txq_total_dump_drv(tx_queue); + + if (total == 0) + continue; + + cl_snprintf(buf, len, buf_size, + "|single|%5u|%10u|%10u|%10u|\n", + tx_queue->index, + tx_queue->dump_queue_full, + tx_queue->dump_dma_map_fail, + total); + } + + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +static void cl_txq_drop_reasons_print_agg(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u32 i = 0, total = 0; + struct cl_tx_queue *tx_queue; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + tx_queue = &cl_hw->tx_queues.agg[i]; + total = cl_txq_total_dump_drv(tx_queue); + + if (total == 0) + continue; + + cl_snprintf(buf, len, buf_size, + "|agg |%5u|%10u|%10u|%10u|\n", + tx_queue->index, + tx_queue->dump_queue_full, + tx_queue->dump_dma_map_fail, + total); + } + + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +static int cl_txq_drop_reasons_print(struct cl_hw *cl_hw) +{ + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "-----------------------------------------------\n" + "| type | idx | queue | dma map | total |\n" + "| | | full | fail | dump |\n" + "|------+-----+----------+----------+----------|\n"); + + cl_txq_drop_reasons_print_bcmc(cl_hw, &buf, &len, &buf_size); + cl_txq_drop_reasons_print_single(cl_hw, &buf, &len, &buf_size); + cl_txq_drop_reasons_print_agg(cl_hw, &buf, &len, &buf_size); + + cl_snprintf(&buf, &len, &buf_size, + "-----------------------------------------------\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_txq_global_counters_print(struct cl_hw *cl_hw) +{ + struct cl_tx_forward_cntr *forward = &cl_hw->tx_packet_cntr.forward; + struct cl_tx_drop_cntr *drop = &cl_hw->tx_packet_cntr.drop; + struct cl_tx_transfer_cntr *transfer = &cl_hw->tx_packet_cntr.transfer; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "FORWARD\n" + "----------------------------\n" + "tx_start = %u\n", forward->tx_start); + cl_snprintf(&buf, &len, &buf_size, + "drv_fast_agg = %u\n", forward->drv_fast_agg); + cl_snprintf(&buf, &len, &buf_size, + "drv_fast_single = %u\n", forward->drv_fast_single); + cl_snprintf(&buf, &len, &buf_size, + "to_mac = %u\n", forward->to_mac); + cl_snprintf(&buf, &len, &buf_size, + "from_mac_single = %u\n", forward->from_mac_single); + cl_snprintf(&buf, &len, &buf_size, + "from_mac_agg = %u\n", forward->from_mac_agg); + cl_snprintf(&buf, &len, &buf_size, + "DROP\n" + "----------------------------\n" + "wd_restart = %u\n", drop->wd_restart); + cl_snprintf(&buf, &len, &buf_size, + "radio_off = %u\n", drop->radio_off); + cl_snprintf(&buf, &len, &buf_size, + "in_recovery = %u\n", drop->in_recovery); + cl_snprintf(&buf, &len, &buf_size, + "short_length = %u\n", drop->short_length); + cl_snprintf(&buf, &len, &buf_size, + "pending_full = %u\n", drop->pending_full); + cl_snprintf(&buf, &len, &buf_size, + "packet_limit = %u\n", drop->packet_limit); + cl_snprintf(&buf, &len, &buf_size, + "dev_flags = %u\n", drop->dev_flags); + cl_snprintf(&buf, &len, &buf_size, + "length_limit = %u\n", drop->length_limit); + cl_snprintf(&buf, &len, &buf_size, + "txhdr_alloc_fail = %u\n", drop->txhdr_alloc_fail); + cl_snprintf(&buf, &len, &buf_size, + "queue_null = %u\n", drop->queue_null); + cl_snprintf(&buf, &len, &buf_size, + "amsdu_alloc_fail = %u\n", drop->amsdu_alloc_fail); + cl_snprintf(&buf, &len, &buf_size, + "amsdu_dma_map_err = %u\n", drop->amsdu_dma_map_err); + cl_snprintf(&buf, &len, &buf_size, + "build_hdr_fail = %u\n", drop->build_hdr_fail); + cl_snprintf(&buf, &len, &buf_size, + "key_disable = %u\n", drop->key_disable); + cl_snprintf(&buf, &len, &buf_size, + "queue_flush = %u\n", drop->queue_flush); + cl_snprintf(&buf, &len, &buf_size, + "sta_null_in_agg = %u\n", drop->sta_null_in_agg); + cl_snprintf(&buf, &len, &buf_size, + "TRANSFER\n" + "----------------------------\n" + "single_to_agg = %u\n", transfer->single_to_agg); + cl_snprintf(&buf, &len, &buf_size, + "agg_to_single = %u\n", transfer->agg_to_single); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_txq_stop_reasons_print(struct cl_hw *cl_hw) +{ + struct ieee80211_local *local = hw_to_local(cl_hw->hw); + unsigned long queue_stop_reasons; + unsigned long flags; + u8 i = 0; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_snprintf(&buf, &len, &buf_size, + "|------------------------|\n" + "|queue|queue_stop_reasons|\n" + "|-----+------------------|\n"); + + for (i = 0; i < IEEE80211_MAX_QUEUES; i++) { + spin_lock_irqsave(&local->queue_stop_reason_lock, flags); + queue_stop_reasons = local->queue_stop_reasons[i]; + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); + + if (queue_stop_reasons) + cl_snprintf(&buf, &len, &buf_size, "|%5u|0x%-16lx|\n", + i, queue_stop_reasons); + } + + cl_snprintf(&buf, &len, &buf_size, "|------------------------|\n"); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_txq_requested_agg_print(struct cl_hw *cl_hw) +{ + u8 i = 0; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + cl_snprintf(&buf, &len, &buf_size, + "## used_agg_queues = %u\n", cl_hw->used_agg_queues); + + if (cl_hw->used_agg_queues) { + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + if (!cl_hw->tx_queues.agg[i].cl_sta) + continue; + + cl_snprintf(&buf, &len, &buf_size, + "%u) sta_idx = %u, tid = %u\n", i + 1, + cl_hw->tx_queues.agg[i].cl_sta->sta_idx, + cl_hw->tx_queues.agg[i].tid); + } + } + + cl_snprintf(&buf, &len, &buf_size, "## req_agg_queues = %u\n", cl_hw->req_agg_queues); + + if (cl_hw->req_agg_queues) { + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + if (!cl_hw->req_agg_db[i].is_used) + continue; + + cl_snprintf(&buf, &len, &buf_size, "%u) sta_idx = %u, tid = %u\n", + i + 1, cl_hw->req_agg_db[i].sta_idx, + cl_hw->req_agg_db[i].tid); + } + } + + spin_unlock_bh(&cl_hw->tx_lock_agg); + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static void cl_txq_hw_amsdu_stats_print(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u32 i, j; + struct cl_tx_queue *tx_queue; + + cl_snprintf(buf, len, buf_size, "HW TX-AMSDU STATS:\n"); + + cl_snprintf(buf, len, buf_size, "|-----------"); + for (i = 0; i < CL_AMSDU_TX_PAYLOAD_MAX; i++) + cl_snprintf(buf, len, buf_size, "-----------"); + + cl_snprintf(buf, len, buf_size, "|\n|agg|sta|tid"); + for (i = 0; i < CL_AMSDU_TX_PAYLOAD_MAX; i++) + cl_snprintf(buf, len, buf_size, "| amsdu #%u ", i + 1); + + cl_snprintf(buf, len, buf_size, "|\n|---+---+---"); + for (i = 0; i < CL_AMSDU_TX_PAYLOAD_MAX; i++) + cl_snprintf(buf, len, buf_size, "+----------"); + + cl_snprintf(buf, len, buf_size, "|\n"); + + for (j = 0; j < IPC_MAX_BA_SESSIONS; j++) { + tx_queue = &cl_hw->tx_queues.agg[j]; + + if (!tx_queue->cl_sta) + continue; + + if (tx_queue->total_packets == 0) + continue; + + cl_snprintf(buf, len, buf_size, "|%3u|%3u|%3u", + tx_queue->index, + tx_queue->cl_sta->sta_idx, + tx_queue->tid); + + for (i = 0; i < CL_AMSDU_TX_PAYLOAD_MAX; i++) + cl_snprintf(buf, len, buf_size, "|%10u", tx_queue->stats_hw_amsdu_cnt[i]); + + cl_snprintf(buf, len, buf_size, "|\n"); + } + + cl_snprintf(buf, len, buf_size, "|-----------"); + for (i = 0; i < CL_AMSDU_TX_PAYLOAD_MAX; i++) + cl_snprintf(buf, len, buf_size, "-----------"); + + cl_snprintf(buf, len, buf_size, "|\n"); +} + +static void cl_txq_sw_amsdu_stats_print(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u32 i, j; + struct cl_tx_queue *tx_queue; + + if (cl_hw->conf->ci_tx_sw_amsdu_max_packets < 2) + return; + + cl_snprintf(buf, len, buf_size, "SW TX-AMSDU STATS:\n"); + + for (j = 0; j < IPC_MAX_BA_SESSIONS; j++) { + tx_queue = &cl_hw->tx_queues.agg[j]; + + if (!tx_queue->cl_sta) + continue; + + if (tx_queue->total_packets == 0) + continue; + + cl_snprintf(buf, len, buf_size, + "\nagg idx %u, sta %u, tid %u :\n", + tx_queue->index, + tx_queue->cl_sta->sta_idx, + tx_queue->tid); + cl_snprintf(buf, len, buf_size, "----------------------------\n"); + + for (i = 0; i < cl_hw->conf->ci_tx_sw_amsdu_max_packets; i++) + if (tx_queue->stats_sw_amsdu_cnt[i] > 0) + cl_snprintf(buf, len, buf_size, + "amsdu #%u = %u\n", i + 1, + tx_queue->stats_sw_amsdu_cnt[i]); + } +} + +static int cl_txq_amsdu_stats_print(struct cl_hw *cl_hw) +{ + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + if (cl_hw->used_agg_queues == 0) + goto out; + + cl_txq_hw_amsdu_stats_print(cl_hw, &buf, &len, &buf_size); + cl_txq_sw_amsdu_stats_print(cl_hw, &buf, &len, &buf_size); +out: + spin_unlock_bh(&cl_hw->tx_lock_agg); + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static void cl_txq_max_size_print_single(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u8 ac = 0; + u8 sta_idx = 0; + u16 queue_idx = 0; + struct cl_tx_queue *tx_queue; + + cl_snprintf(buf, len, buf_size, + "MAX SIZE SINGLE QUEUES:\n" + "|----------------------|\n" + "|idx|sta|ac| drv | fw |\n" + "|---+---+--+-----+-----|\n"); + + spin_lock_bh(&cl_hw->tx_lock_single); + + for (sta_idx = 0; sta_idx < FW_MAX_NUM_STA; sta_idx++) { + for (ac = 0; ac < AC_MAX; ac++) { + queue_idx = QUEUE_IDX(sta_idx, ac); + tx_queue = &cl_hw->tx_queues.single[queue_idx]; + + if (tx_queue->total_fw_push_skb == 0) + continue; + + cl_snprintf(buf, len, buf_size, + "|%3u|%3u|%2u|%5u|%5u|\n", + tx_queue->index, + sta_idx, + tx_queue->hw_index, + tx_queue->max_packets, + tx_queue->fw_max_size); + } + } + + spin_unlock_bh(&cl_hw->tx_lock_single); + + cl_snprintf(buf, len, buf_size, "|----------------------|\n"); +} + +static void cl_txq_max_size_print_agg(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + u8 agg_idx = 0; + struct cl_tx_queue *tx_queue; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + if (cl_hw->used_agg_queues == 0) + goto out; + + cl_snprintf(buf, len, buf_size, + "MAX SIZE AGGREGATION QUEUES:\n" + "|-----------------------|\n" + "|idx|sta|tid| drv | fw |\n" + "|---+---+---+-----+-----|\n"); + + for (agg_idx = 0; agg_idx < IPC_MAX_BA_SESSIONS; agg_idx++) { + tx_queue = &cl_hw->tx_queues.agg[agg_idx]; + + if (!tx_queue->cl_sta) + continue; + + cl_snprintf(buf, len, buf_size, + "|%3u|%3u|%3u|%5u|%5u|\n", + tx_queue->index, + tx_queue->cl_sta->sta_idx, + tx_queue->tid, + tx_queue->max_packets, + tx_queue->fw_max_size); + } + + cl_snprintf(buf, len, buf_size, "|----------------------|\n"); + +out: + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +static int cl_txq_max_size_print(struct cl_hw *cl_hw) +{ + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_txq_max_size_print_single(cl_hw, &buf, &len, &buf_size); + cl_txq_max_size_print_agg(cl_hw, &buf, &len, &buf_size); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static void cl_txq_stats_reset_bcmc(struct cl_hw *cl_hw) +{ + unsigned long flags; + + spin_lock_irqsave(&cl_hw->tx_lock_bcmc, flags); + cl_txq_reset_counters_during_traffic(&cl_hw->tx_queues.bcmc); + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); +} + +static void cl_txq_stats_reset_single(struct cl_hw *cl_hw) +{ + u16 i = 0; + + spin_lock_bh(&cl_hw->tx_lock_single); + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) + cl_txq_reset_counters_during_traffic(&cl_hw->tx_queues.single[i]); + + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +static void cl_txq_stats_reset_agg(struct cl_hw *cl_hw) +{ + u16 i = 0; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) + cl_txq_reset_counters_during_traffic(&cl_hw->tx_queues.agg[i]); + + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +static void cl_txq_stats_reset(struct cl_hw *cl_hw) +{ + cl_txq_stats_reset_bcmc(cl_hw); + cl_txq_stats_reset_single(cl_hw); + cl_txq_stats_reset_agg(cl_hw); + + memset(&cl_hw->tx_packet_cntr, 0, sizeof(struct cl_tx_packet_cntr)); + + pr_debug("Reset queue stats\n"); +} + +static void cl_txq_sched_list_print_single(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + struct cl_tx_queue *tx_queue; + u32 num_queues = 0; + + cl_snprintf(buf, len, buf_size, "TX single sched list:\n"); + + spin_lock_bh(&cl_hw->tx_lock_single); + + list_for_each_entry(tx_queue, &cl_hw->list_sched_q_single, sched_list) { + num_queues++; + cl_snprintf(buf, len, buf_size, "%u) Index = %u\n", num_queues, tx_queue->index); + } + + spin_unlock_bh(&cl_hw->tx_lock_single); + + if (num_queues == 0) + cl_snprintf(buf, len, buf_size, "empty\n"); +} + +static void cl_txq_sched_list_print_agg(struct cl_hw *cl_hw, + char **buf, int *len, ssize_t *buf_size) +{ + struct cl_tx_queue *tx_queue; + u32 num_queues = 0; + + cl_snprintf(buf, len, buf_size, "\nTX agg sched list:\n"); + + spin_lock_bh(&cl_hw->tx_lock_agg); + + list_for_each_entry(tx_queue, &cl_hw->list_sched_q_agg, sched_list) { + num_queues++; + cl_snprintf(buf, len, buf_size, "%u) Index = %u\n", num_queues, tx_queue->index); + } + + spin_unlock_bh(&cl_hw->tx_lock_agg); + + if (num_queues == 0) + cl_snprintf(buf, len, buf_size, "empty\n"); +} + +static int cl_txq_sched_list_print(struct cl_hw *cl_hw) +{ + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + cl_txq_sched_list_print_single(cl_hw, &buf, &len, &buf_size); + cl_txq_sched_list_print_agg(cl_hw, &buf, &len, &buf_size); + + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_txq_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "txq usage:\n" + "-a : Print traffic counters\n" + "-b : Print drop counters\n" + "-c : Print global counters\n" + "-d : Print stop reasons\n" + "-e : Print requested aggregations\n" + "-f : Print AMSDU statistics\n" + "-m : Print maximum queues size\n" + "-r : Reset queue stats\n" + "-s : Print schedule list\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +static void cl_txq_task_single(struct cl_hw *cl_hw) +{ + /* Schedule single queues */ + struct cl_tx_queue *tx_queue, *tx_queue_tmp; + + spin_lock(&cl_hw->tx_lock_single); + + list_for_each_entry_safe(tx_queue, tx_queue_tmp, &cl_hw->list_sched_q_single, sched_list) + cl_txq_sched(cl_hw, tx_queue); + + /* Rotate the queue so next schedule will start with a different queue */ + list_rotate_left(&cl_hw->list_sched_q_single); + + spin_unlock(&cl_hw->tx_lock_single); +} + +static void cl_txq_task_agg(struct cl_hw *cl_hw) +{ + /* Schedule agg queueus */ + struct cl_tx_queue *tx_queue, *tx_queue_tmp; + + spin_lock(&cl_hw->tx_lock_agg); + + list_for_each_entry_safe(tx_queue, tx_queue_tmp, &cl_hw->list_sched_q_agg, sched_list) + cl_txq_sched(cl_hw, tx_queue); + + /* Rotate the queue so next schedule will start with a different queue */ + list_rotate_left(&cl_hw->list_sched_q_agg); + + spin_unlock(&cl_hw->tx_lock_agg); +} + +static void cl_txq_task(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + + cl_txq_task_single(cl_hw); + cl_txq_task_agg(cl_hw); +} + +static void cl_txq_agg_inc_usage_cntr(struct cl_hw *cl_hw) +{ + /* Should be called in cl_hw->tx_lock_agg context */ + cl_hw->used_agg_queues++; + cl_txq_agg_size_set(cl_hw); +} + +static void cl_txq_agg_dec_usage_cntr(struct cl_hw *cl_hw) +{ + /* Should be called in cl_hw->tx_lock_agg context */ + WARN_ON_ONCE(cl_hw->used_agg_queues == 0); + + cl_hw->used_agg_queues--; + cl_txq_agg_size_set(cl_hw); +} + +static void cl_txq_init_single(struct cl_hw *cl_hw) +{ + struct cl_tx_queue *tx_queue; + u32 i; + + spin_lock_bh(&cl_hw->tx_lock_single); + + INIT_LIST_HEAD(&cl_hw->list_sched_q_single); + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) { + tx_queue = &cl_hw->tx_queues.single[i]; + memset(tx_queue, 0, sizeof(struct cl_tx_queue)); + INIT_LIST_HEAD(&tx_queue->hdrs); + tx_queue->hw_index = i / FW_MAX_NUM_STA; + tx_queue->fw_max_size = IPC_TXDESC_CNT_SINGLE; + tx_queue->fw_free_space = IPC_TXDESC_CNT_SINGLE; + tx_queue->index = i; + tx_queue->max_packets = cl_hw->conf->ci_tx_queue_size_single; + tx_queue->type = QUEUE_TYPE_SINGLE; + } + + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +static void cl_txq_init_bcmc(struct cl_hw *cl_hw) +{ + unsigned long flags; + struct cl_tx_queue *tx_queue; + + spin_lock_irqsave(&cl_hw->tx_lock_bcmc, flags); + + tx_queue = &cl_hw->tx_queues.bcmc; + memset(tx_queue, 0, sizeof(struct cl_tx_queue)); + INIT_LIST_HEAD(&tx_queue->hdrs); + tx_queue->hw_index = CL_HWQ_BCN; + tx_queue->fw_max_size = IPC_TXDESC_CNT_BCMC; + tx_queue->fw_free_space = IPC_TXDESC_CNT_BCMC; + tx_queue->index = 0; + tx_queue->max_packets = 0; + tx_queue->type = QUEUE_TYPE_BCMC; + + spin_unlock_irqrestore(&cl_hw->tx_lock_bcmc, flags); +} + +static void cl_txq_init_agg(struct cl_hw *cl_hw) +{ + spin_lock_bh(&cl_hw->tx_lock_agg); + INIT_LIST_HEAD(&cl_hw->list_sched_q_agg); + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +static void cl_txq_agg_request_reset(struct cl_hw *cl_hw) +{ + cl_hw->req_agg_queues = 0; + memset(cl_hw->req_agg_db, 0, sizeof(cl_hw->req_agg_db)); +} + +void cl_txq_init(struct cl_hw *cl_hw) +{ + tasklet_init(&cl_hw->tx_task, cl_txq_task, (unsigned long)cl_hw); + + cl_txq_agg_request_reset(cl_hw); + cl_txq_init_single(cl_hw); + cl_txq_init_bcmc(cl_hw); + cl_txq_init_agg(cl_hw); +} + +void cl_txq_stop(struct cl_hw *cl_hw) +{ + tasklet_kill(&cl_hw->tx_task); +} + +struct cl_tx_queue *cl_txq_get(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr) +{ + struct cl_sta *cl_sta = sw_txhdr->cl_sta; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(sw_txhdr->skb); + u8 hw_queue = sw_txhdr->hw_queue; + + if (!cl_sta && + hw_queue == CL_HWQ_VO && + is_multicast_ether_addr(sw_txhdr->hdr80211->addr1)) { + /* + * If HW queue is VO and packet is multicast, it was not buffered + * by mac80211, and it should be pushed to the high-priority queue + * and not to the bcmc queue. + */ + return &cl_hw->tx_queues.single[HIGH_PRIORITY_QUEUE]; + } else if (!cl_sta && + (hw_queue != CL_HWQ_BCN) && + !(tx_info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) { + /* + * If station is NULL, but HW queue is not BCN, + * it most go to the high-priority queue. + */ + tx_info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER; + sw_txhdr->hw_queue = CL_HWQ_VO; + return &cl_hw->tx_queues.single[HIGH_PRIORITY_QUEUE]; + } else if (cl_sta && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { + /* Agg packet */ + return cl_sta->agg_tx_queues[sw_txhdr->tid]; + } else if (hw_queue == CL_HWQ_BCN) { + return &cl_hw->tx_queues.bcmc; + } else if (tx_info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER) { + /* + * Only frames that are power save response or non-bufferable MMPDU + * will have this flag set our driver will push those frame to the + * highiest priority queue. + */ + return &cl_hw->tx_queues.single[HIGH_PRIORITY_QUEUE]; + } + + return &cl_hw->tx_queues.single[QUEUE_IDX(sw_txhdr->sta_idx, hw_queue)]; +} + +void cl_txq_push(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr) +{ + struct cl_tx_queue *tx_queue = sw_txhdr->tx_queue; + + if (tx_queue->num_packets < tx_queue->max_packets) { + tx_queue->num_packets++; + + /* + * This prioritization of action frames helps Samsung Galaxy Note 8 to + * open BA session more easily, when phy dev is PHY_DEV_OLYMPUS + */ + if (ieee80211_is_action(sw_txhdr->fc)) + list_add(&sw_txhdr->tx_queue_list, &tx_queue->hdrs); + else + list_add_tail(&sw_txhdr->tx_queue_list, &tx_queue->hdrs); + + /* If it is the first packet in the queue, add the queue to the sched list */ + cl_txq_sched_list_add(tx_queue, cl_hw); + } else { + struct cl_sta *cl_sta = sw_txhdr->cl_sta; + u8 tid = sw_txhdr->tid; + + /* If the SW queue full, release the packet */ + tx_queue->dump_queue_full++; + + if (cl_sta && cl_sta->amsdu_anchor[tid].sw_txhdr) { + if (cl_sta->amsdu_anchor[tid].sw_txhdr == sw_txhdr) { + cl_sta->amsdu_anchor[tid].sw_txhdr = NULL; + cl_sta->amsdu_anchor[tid].packet_cnt = 0; + } + } + + dev_kfree_skb_any(sw_txhdr->skb); + cl_sw_txhdr_free(cl_hw, sw_txhdr); + + /* Schedule tasklet to try and empty the queue */ + tasklet_schedule(&cl_hw->tx_task); + } +} + +void cl_txq_sched(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue) +{ + struct cl_sw_txhdr *sw_txhdr, *sw_txhdr_tmp; + + if (!test_bit(CL_DEV_STARTED, &cl_hw->drv_flags) || + cl_hw->tx_disable_flags || + cl_txq_is_fw_full(tx_queue)) + return; + + /* Go over all descriptors in queue */ + list_for_each_entry_safe(sw_txhdr, sw_txhdr_tmp, &tx_queue->hdrs, tx_queue_list) { + list_del(&sw_txhdr->tx_queue_list); + tx_queue->num_packets--; + + cl_tx_push(cl_hw, sw_txhdr, tx_queue); + + if (cl_txq_is_fw_full(tx_queue)) + break; + } + + /* If queue is empty remove it from schedule list */ + cl_txq_sched_list_remove_if_empty(tx_queue); +} + +void cl_txq_agg_alloc(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct mm_ba_add_cfm *ba_add_cfm, u16 buf_size) +{ + u8 tid = ba_add_cfm->tid; + u8 fw_agg_idx = ba_add_cfm->agg_idx; + u8 sta_idx = cl_sta->sta_idx; + u8 ac = cl_tid2hwq[tid]; + u16 single_queue_idx = QUEUE_IDX(sta_idx, ac); + struct cl_tx_queue *tx_queue = &cl_hw->tx_queues.agg[fw_agg_idx]; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + /* Init aggregated queue struct */ + memset(tx_queue, 0, sizeof(struct cl_tx_queue)); + INIT_LIST_HEAD(&tx_queue->hdrs); + + /* + * Firmware agg queues size is static and set to 512, so that for the worst + * case of HE stations,that support AMPDU of 256, it has room for two full + * aggregation. + * To keep this logic, of room for two aggregations, for non-HE stations, or + * for HE stations that do not support AMPDU of 256, we initialize fw_max_size + to twice the buffer size supported by the station. + */ + tx_queue->fw_max_size = min_t(u16, cl_hw->max_agg_tx_q_size, buf_size * 2); + tx_queue->fw_free_space = tx_queue->fw_max_size; + + tx_queue->max_packets = cl_hw->conf->ci_tx_queue_size_agg; + tx_queue->hw_index = ac; + tx_queue->cl_sta = cl_sta; + tx_queue->type = QUEUE_TYPE_AGG; + tx_queue->tid = tid; + tx_queue->index = fw_agg_idx; + +#ifdef CONFIG_CL_PCIE + /* Reset the synchronization counters between the fw and the IPC layer */ + cl_hw->ipc_env->ring_indices_elem->indices->txdesc_write_idx.agg[fw_agg_idx] = 0; +#endif + + /* Attach the cl_hw chosen queue to the station and agg queues DB */ + cl_sta->agg_tx_queues[tid] = tx_queue; + cl_agg_cfm_set_tx_queue(cl_hw, tx_queue, fw_agg_idx); + + /* Notify upper mac80211 layer of queues resources status */ + cl_txq_agg_inc_usage_cntr(cl_hw); + cl_txq_agg_request_del(cl_hw, sta_idx, tid); + + /* + * Move the qos descriptors to the new allocated aggregated queues, + * otherwise we might reorder packets) + */ + cl_txq_transfer_single_to_agg(cl_hw, &cl_hw->tx_queues.single[single_queue_idx], + tx_queue, tid); + /* Move the BA window pending packets to agg path */ + cl_baw_pending_to_agg(cl_hw, cl_sta, tid); + + spin_unlock_bh(&cl_hw->tx_lock_agg); + + cl_dbg_trace(cl_hw, "Allocate queue [%u] to station [%u] tid [%u]\n", + fw_agg_idx, sta_idx, tid); +} + +void cl_txq_agg_free(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue, + struct cl_sta *cl_sta, u8 tid) +{ + spin_lock_bh(&cl_hw->tx_lock_agg); + + cl_dbg_trace(cl_hw, "Free queue [%u] of station [%u] tid [%u]\n", + tx_queue->index, cl_sta->sta_idx, tid); + + memset(tx_queue, 0, sizeof(struct cl_tx_queue)); + + cl_txq_agg_dec_usage_cntr(cl_hw); + + spin_unlock_bh(&cl_hw->tx_lock_agg); +} + +void cl_txq_agg_stop(struct cl_sta *cl_sta, u8 tid) +{ + cl_sta->agg_tx_queues[tid] = NULL; +} + +void cl_txq_sta_add(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + /* Set cl_sta field for all single queues of this station */ + u8 ac; + u16 queue_idx; + + for (ac = 0; ac < AC_MAX; ac++) { + queue_idx = QUEUE_IDX(cl_sta->sta_idx, ac); + cl_hw->tx_queues.single[queue_idx].cl_sta = cl_sta; + } + + /* Reset pointers to TX agg queues */ + memset(cl_sta->agg_tx_queues, 0, sizeof(cl_sta->agg_tx_queues)); +} + +void cl_txq_sta_remove(struct cl_hw *cl_hw, u8 sta_idx) +{ + /* Clear cl_sta field for all single queues of this station */ + u8 ac; + u16 queue_idx; + + for (ac = 0; ac < AC_MAX; ac++) { + queue_idx = QUEUE_IDX(sta_idx, ac); + cl_hw->tx_queues.single[queue_idx].cl_sta = NULL; + } +} + +void cl_txq_transfer_agg_to_single(struct cl_hw *cl_hw, struct cl_tx_queue *agg_queue) +{ + /* + * 1) Remove from aggregation queue + * 2) Free sw_txhdr + * 3) Push to single queue + */ + struct cl_sw_txhdr *sw_txhdr, *sw_txhdr_tmp; + struct sk_buff *skb; + struct ieee80211_tx_info *tx_info; + struct cl_tx_queue *single_queue; + struct cl_sta *cl_sta = agg_queue->cl_sta; + u16 single_queue_idx = 0; + + if (agg_queue->num_packets == 0) + return; + + single_queue_idx = QUEUE_IDX(cl_sta->sta_idx, agg_queue->hw_index); + single_queue = &cl_hw->tx_queues.single[single_queue_idx]; + + list_for_each_entry_safe(sw_txhdr, sw_txhdr_tmp, &agg_queue->hdrs, tx_queue_list) { + list_del(&sw_txhdr->tx_queue_list); + agg_queue->num_packets--; + + skb = sw_txhdr->skb; + tx_info = IEEE80211_SKB_CB(skb); + + if (cl_tx_ctrl_is_amsdu(tx_info)) { + cl_tx_amsdu_transfer_single(cl_hw, sw_txhdr); + } else { + tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; + + if (cl_tx_8023_to_wlan(cl_hw, skb, cl_sta, sw_txhdr->tid) == 0) { + cl_hw->tx_packet_cntr.transfer.agg_to_single++; + cl_tx_single(cl_hw, cl_sta, skb, false, false); + } + } + + cl_sw_txhdr_free(cl_hw, sw_txhdr); + } + + /* If queue is empty remove it from schedule list */ + cl_txq_sched_list_remove_if_empty(agg_queue); +} + +void cl_txq_flush(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue) +{ + struct cl_sw_txhdr *sw_txhdr, *sw_txhdr_tmp; + struct ieee80211_tx_info *tx_info; + + if (tx_queue->num_packets == 0) + return; + + list_for_each_entry_safe(sw_txhdr, sw_txhdr_tmp, &tx_queue->hdrs, tx_queue_list) { + list_del(&sw_txhdr->tx_queue_list); + tx_queue->num_packets--; + + /* Can not send AMSDU frames as singles */ + tx_info = IEEE80211_SKB_CB(sw_txhdr->skb); + + /* Free mid & last AMSDU sub frames */ + if (cl_tx_ctrl_is_amsdu(tx_info)) { + cl_tx_amsdu_flush_sub_frames(cl_hw, sw_txhdr); + } else { + if (tx_queue->type == QUEUE_TYPE_SINGLE) + cl_tx_single_free_skb(cl_hw, sw_txhdr->skb); + else + kfree_skb(sw_txhdr->skb); + + cl_sw_txhdr_free(cl_hw, sw_txhdr); + cl_hw->tx_packet_cntr.drop.queue_flush++; + } + } + + /* Remove from schedule queue */ + cl_txq_sched_list_remove(tx_queue); + + /* Sanity check that queue is empty */ + WARN_ON(tx_queue->num_packets > 0); +} + +void cl_txq_flush_single(struct cl_hw *cl_hw, u16 idx) +{ + spin_lock_bh(&cl_hw->tx_lock_single); + cl_txq_flush(cl_hw, &cl_hw->tx_queues.single[idx]); + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +void cl_txq_flush_all_agg(struct cl_hw *cl_hw) +{ + int i = 0; + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) + cl_txq_flush(cl_hw, &cl_hw->tx_queues.agg[i]); +} + +void cl_txq_flush_all_single(struct cl_hw *cl_hw) +{ + int i = 0; + + for (i = 0; i < MAX_SINGLE_QUEUES; i++) + cl_txq_flush(cl_hw, &cl_hw->tx_queues.single[i]); +} + +void cl_txq_flush_sta(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + int i = 0; + u8 sta_idx = cl_sta->sta_idx; + u32 queue_idx = 0; + struct cl_tx_queue *tx_queue = NULL; + + spin_lock_bh(&cl_hw->tx_lock_agg); + + /* Flush all aggregation queues for this station */ + for (i = 0; i < IEEE80211_NUM_TIDS; i++) + if (cl_sta->agg_tx_queues[i]) + cl_txq_flush(cl_hw, cl_sta->agg_tx_queues[i]); + + spin_unlock_bh(&cl_hw->tx_lock_agg); + + spin_lock_bh(&cl_hw->tx_lock_single); + + /* Flush all single queues for this station */ + for (i = 0; i < AC_MAX; i++) { + queue_idx = QUEUE_IDX(sta_idx, i); + tx_queue = &cl_hw->tx_queues.single[queue_idx]; + cl_txq_flush(cl_hw, tx_queue); + cl_txq_reset_counters(tx_queue); + } + + /* Go over high prioirty queue and delete packets belonging to this station */ + cl_txq_delete_packets(cl_hw, &cl_hw->tx_queues.single[HIGH_PRIORITY_QUEUE], sta_idx); + + spin_unlock_bh(&cl_hw->tx_lock_single); +} + +void cl_txq_agg_request_add(struct cl_hw *cl_hw, u8 sta_idx, u8 tid) +{ + int i = cl_txq_request_find(cl_hw, sta_idx, tid); + struct cl_req_agg_db *req_agg_db = NULL; + + if (i != -1) { + cl_dbg_trace(cl_hw, "ALREADY_ADDED - entry = %d, sta_idx = %u, tid = %u\n", + i, sta_idx, tid); + return; + } + + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) { + req_agg_db = &cl_hw->req_agg_db[i]; + + if (!req_agg_db->is_used) { + cl_dbg_trace(cl_hw, "ADD - entry = %d, sta_idx = %u, tid = %u\n", + i, sta_idx, tid); + req_agg_db->is_used = true; + req_agg_db->sta_idx = sta_idx; + req_agg_db->tid = tid; + cl_hw->req_agg_queues++; + return; + } + } +} + +void cl_txq_agg_request_del(struct cl_hw *cl_hw, u8 sta_idx, u8 tid) +{ + int i = cl_txq_request_find(cl_hw, sta_idx, tid); + + if (i != -1) { + cl_dbg_trace(cl_hw, "DEL - entry = %d, sta_idx = %u, tid = %u\n", + i, sta_idx, tid); + cl_hw->req_agg_db[i].is_used = false; + cl_hw->req_agg_queues--; + } +} + +bool cl_txq_is_agg_available(struct cl_hw *cl_hw) +{ + u8 total_agg_queues = cl_hw->used_agg_queues + cl_hw->req_agg_queues; + + return (total_agg_queues < IPC_MAX_BA_SESSIONS); +} + +bool cl_txq_single_is_full(struct cl_hw *cl_hw, u16 idx) +{ + struct cl_tx_queue *tx_queue = &cl_hw->tx_queues.single[idx]; + bool is_full = 0; + + spin_lock_bh(&cl_hw->tx_lock_single); + is_full = (tx_queue->max_packets == tx_queue->num_packets); + spin_unlock_bh(&cl_hw->tx_lock_single); + + return is_full; +} + +void cl_txq_single_sched(struct cl_hw *cl_hw, u16 idx) +{ + /* + * Don't take lock because it is already taken by + * all functions that call cl_txq_single_sched(). + */ + struct cl_tx_queue *tx_queue = &cl_hw->tx_queues.single[idx]; + + if (tx_queue->num_packets) + cl_txq_sched(cl_hw, tx_queue); +} + +bool cl_txq_is_fw_empty(struct cl_tx_queue *tx_queue) +{ + return (tx_queue->fw_free_space == tx_queue->fw_max_size); +} + +bool cl_txq_is_fw_full(struct cl_tx_queue *tx_queue) +{ + return (tx_queue->fw_free_space == 0); +} + +bool cl_txq_frames_pending(struct cl_hw *cl_hw) +{ + int i = 0; + + /* Check if we have multicast/bradcast frame in FW queues */ + if (!cl_txq_is_fw_empty(&cl_hw->tx_queues.bcmc)) + return true; + + /* Check if we have singles frame in FW queues */ + for (i = 0; i < MAX_SINGLE_QUEUES; i++) + if (!cl_txq_is_fw_empty(&cl_hw->tx_queues.single[i])) + return true; + + /* Check if we have aggregation frame in FW queues */ + for (i = 0; i < IPC_MAX_BA_SESSIONS; i++) + if (!cl_txq_is_fw_empty(&cl_hw->tx_queues.agg[i])) + return true; + + return false; +} + +int cl_txq_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + switch (cli_params->option) { + case 'a': + return cl_txq_traffic_counters_print(cl_hw); + case 'b': + return cl_txq_drop_reasons_print(cl_hw); + case 'c': + return cl_txq_global_counters_print(cl_hw); + case 'd': + return cl_txq_stop_reasons_print(cl_hw); + case 'e': + return cl_txq_requested_agg_print(cl_hw); + case 'f': + return cl_txq_amsdu_stats_print(cl_hw); + case 'm': + return cl_txq_max_size_print(cl_hw); + case 'r': + cl_txq_stats_reset(cl_hw); + break; + case 's': + return cl_txq_sched_list_print(cl_hw); + case '?': + return cl_txq_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + break; + } + + return 0; +} From patchwork Thu Jun 17 16:01:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8617C2B9F4 for ; Thu, 17 Jun 2021 16:11:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADF466141F for ; Thu, 17 Jun 2021 16:11:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231723AbhFQQNS (ORCPT ); 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 219/256] cl8k: add tx/tx_queue.h Date: Thu, 17 Jun 2021 16:01:46 +0000 Message-Id: <20210617160223.160998-220-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:38 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac54fc37-61da-4a98-9d6a-08d931a9e3a6 X-MS-TrafficTypeDiagnostic: AM9P192MB1329: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RymBl9DCY8Fb2y9wK58UjZWHXIfvpWTf71kHv4CqDzLWxsTxZQtrxDM4elzW8om0eDyCYsXg2nIKQksPKjDeNcSyKV6Ium7+aRaEcMEQfg8Z8X7gHA2FIWaAIdVmv9x17F0D5uqGlneDRwG7ZeBDJDpw5HJiqb8Mo/hxwT4pI+4QDGhJwT0MRqwC2tY1queLXofypBAKAGwc08AEgfC9catJjvuJl3cSxYXpA0RVFPz9GUIhQt6G+jN0j+ezzWJ+XeC/Xdh4eap+xJaCFwZYcVBiCWrabX9AObH4oQGvcPZWcNPobA2kbQg9aGWRrYGshhFkFwwi9bcuSG/o+XHet4H1JB2dKY1liianOPLvSQNiY/0xZird76mP17PhKWt7BhOqca5OcZ20FeNTKIzuDL2y/2Vfu590k9nAjXtVA75Eh6uwXpTe/LboOaAwrYfz/5hUnpLcp3sLzbxTNxbFCg1jRHFLMo6XnpnD0/V2NppDS1Yp6/vJ+nAjUJfscfmTtx4CgQcnlDZ6YbRvcRvS4+ioGNUftjOVCETgZ9MKHWlc2YP4tyVh7Nf5TukMxDHhDpzl6pexfDIJiWyh6Ts0pSNw89ENU1O1jIYke1IOzmvIBNzhcDPi4Ca5WXUQtMhSe9iLEZL+641udwzYG74OgU4mpviH9O27A95z8z9E4HSefh25Ohn7rOwX+914uE5VjijIr9BQ238STodjCnEb4A== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(39850400004)(376002)(136003)(346002)(396003)(86362001)(38350700002)(8936002)(38100700002)(6916009)(52116002)(6486002)(55236004)(54906003)(36756003)(6506007)(956004)(4326008)(186003)(2616005)(1076003)(478600001)(26005)(16526019)(107886003)(6666004)(66556008)(83380400001)(5660300002)(2906002)(6512007)(9686003)(8676002)(316002)(66476007)(66946007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0cKqqSIyjvSScmF6MSibEShcbvcpzWYlOliv+Hd0udTd23iTJH/C5teZmjlNTMrCIhXavEDVRHnFKMy84rCi0mV7XlmXki41Dn4egA4JDAaPRRkuNvfJuY57WIkrZgWxxB7PC30YhbXB3txWnMthr6I9vfgx7p0/z1ij1cZbFFmIhMVZ6+69IX5ZVWX0wLAEgvyp/k6NlEqYDziR/uQtrUhxmpd3T1u4fxh0nV+UtnCXhPe91YG1Gezv7EnizHsUe+Cppujbn4a2yxX6uBTa4d2KignCZEIFQzLEFiE4udd33B64u1nsWa1hy9eWdihxDEEc1sbQ/7RmlW2ZlLLx703fR6eICjAJpE+mcy43KZkySD93ssmkFGHz719+xcsoms3z/h2gT++AMFV/y43Be09oru5In54aC9J2/AB6peMGcIGx7nGCG8X0/869Acg69YMwG2JVKlKO3Y4PYLp/rMOMzAwvYH8dGyyCSOO7ecs3NTU9DOXHzwT0iXlpKdJnhQQUeObrRuXX29F7W4soXSRzpDN2AAi12U7/xqAeGYjk4meDsJoWJKfJ2t0MOEWhzfUPgtEi3XI29zAducB5yIaOnSqYkO9yx0LBmDL7YFdBMV2DPqx3TXrhvJMWJuOgYp1DcQCMYQiTUgSiiBJIXnvBJrBY5uKQ2wLoWkSY1ye70V1UTYZPvCdOS62gBjoDlrQvqzVxjp69GPVUUNkuHWTUWwVnoMdotPsGKjuqLzz399aKL1NegjY9HoYQ8HiA40Ge/LFgM+4rvMuVVZYCWBOajZd/L0rkYh57wM2E6a72Os2qa9JEQ0wOt4Y45JKHk70Ju/X2m3NNDnZEaSfJm266mQ11j3VHLo7VgwFkgEL3/rSYhSjCXG2WQXhMp8UOM5RrNSkPwSGRUnVouizNQuSU/y4V+93DpRuewdtYlKQZGcjWISJqO4RKGgi43S4bPQ4UbI5tt8fAeA6lTL8gMDLrgQmXgCk2tsDmRW0DJJMIezHTUCFd+60wKhCcVhwhnTLu8PCGB+wdCv89Qn+/3wLfzdzTVQ2ulzATg4buQhS/yaR9AJRUwEmCuj9Wvu3YltA3XugBbr0G4bPkGjQ7iKg6+8Q+vfKqP4Vf5BSnibqplXta9dycENNbrCKEie+wOXsuTw7sqY290nMMdXVQvvOgqpBWFWXf1dtkXbF2ZQhWtED2o1wQk6sFoYWcuZWGuvorURIwgFhYYF8MFubIJ7FHTnXnrizBoWdcC6gcVeQsxNVc/Z2MXz7cwVTHNB1Cmd9WKrUtOj8xT+V8yvCnqG/v449gqeO0Fr9kvjcMrV9LoyuTVnZjtD04TSi9m5B/ X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ac54fc37-61da-4a98-9d6a-08d931a9e3a6 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:39.1253 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DidSvgkA8mRrf1YtoeXd928vhwWxySm8E4fm+JhUIb11d+9JHOWBwp130KYqnGw0yMpkCQNwIapoXSEh/V5EqA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1329 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/tx/tx_queue.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/tx/tx_queue.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/tx/tx_queue.h b/drivers/net/wireless/celeno/cl8k/tx/tx_queue.h new file mode 100644 index 000000000000..e8232b605b2b --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/tx/tx_queue.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TX_QUEUE_H +#define CL_TX_QUEUE_H + +#include "hw.h" +#include "tx/tx.h" + +enum cl_queue_type { + QUEUE_TYPE_SINGLE, + QUEUE_TYPE_AGG, + QUEUE_TYPE_BCMC, + + QUEUE_TYPE_MAX +}; + +#define QUEUE_IDX(sta, ac) ((sta) + (ac) * FW_MAX_NUM_STA) + +void cl_txq_init(struct cl_hw *cl_hw); +void cl_txq_stop(struct cl_hw *cl_hw); +struct cl_tx_queue *cl_txq_get(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr); +void cl_txq_push(struct cl_hw *cl_hw, struct cl_sw_txhdr *sw_txhdr); +void cl_txq_sched(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue); +void cl_txq_agg_alloc(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct mm_ba_add_cfm *ba_add_cfm, u16 buf_size); +void cl_txq_agg_free(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue, + struct cl_sta *cl_sta, u8 tid); +void cl_txq_agg_stop(struct cl_sta *cl_sta, u8 tid); +void cl_txq_sta_add(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +void cl_txq_sta_remove(struct cl_hw *cl_hw, u8 sta_idx); +void cl_txq_transfer_agg_to_single(struct cl_hw *cl_hw, struct cl_tx_queue *agg_queue); +void cl_txq_flush(struct cl_hw *cl_hw, struct cl_tx_queue *tx_queue); +void cl_txq_flush_single(struct cl_hw *cl_hw, u16 idx); +void cl_txq_flush_all_agg(struct cl_hw *cl_hw); +void cl_txq_flush_all_single(struct cl_hw *cl_hw); +void cl_txq_flush_sta(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +void cl_txq_agg_request_add(struct cl_hw *cl_hw, u8 sta_idx, u8 tid); +void cl_txq_agg_request_del(struct cl_hw *cl_hw, u8 sta_idx, u8 tid); +bool cl_txq_is_agg_available(struct cl_hw *cl_hw); +bool cl_txq_single_is_full(struct cl_hw *cl_hw, u16 idx); +void cl_txq_single_sched(struct cl_hw *cl_hw, u16 idx); +bool cl_txq_is_fw_empty(struct cl_tx_queue *tx_queue); +bool cl_txq_is_fw_full(struct cl_tx_queue *tx_queue); +bool cl_txq_frames_pending(struct cl_hw *cl_hw); +int cl_txq_cli(struct cl_hw *cl_hw, struct cli_params *cli_params); + +#endif /* CL_TX_QUEUE_H */ From patchwork Thu Jun 17 16:01:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFA5DC2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 220/256] cl8k: add utils/file.c Date: Thu, 17 Jun 2021 16:01:47 +0000 Message-Id: <20210617160223.160998-221-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:39 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b7ef0805-626f-45fc-dbb9-08d931a9e467 X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:826; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FwJZe8JLc5lxf4ef0Opi2XreZfcKRopyH5628D70Ay5zQm9FHPUFrD07bKmRwpaxPG8h7w7awKYOaMPrBbTpmNEbUjuUiIqCNiGi5+oaxX+czhST3qxrX8M99y1KHEbnWsUKFmkMP+5SfgzAcM6YpU9Po5O+CH77CZaNcmTmS5pyWs4KbhbeN0bEJ9BF+WtgFasrPXX1t0+amX5SHKEWu73hkX47mvyZRaE3+fXy6NPQL6NQNInJ40sUSUit6E2DDioECzfmNU8IvNnR2JSFfzzg7ApxHxT6Dv/wE4LvaEOwqC53JWj9nlOvGYSbUVyMcfdP5qaKVJmz763DaVHlt72aTWVxbbIB7fhgiLfFsfrwGCyaMZBQAgJuveGse70xJ0U4nYg7Y+b470/rVTsn9dN0ZXqH9clBH9sWN7bMYlYacRKw6lNMyIhEz1zaAA3ejSoqKVZ6YwVFTE3QIo4pUg9eSzn0lRGdi+3CLDtCWfE7RXlBxuakLq7COIbg17XQdm4a8ae+20OphOi/nkFzkf/3MN/9QgoPv30jVYQ+6KyphteTpMLl5ucDJlp1jskZSg/5chQRvYkYOjaY3ObMdXBNmcSVAQO0n/3piPdyrXlTlWI+ShfRfv5dUXzlsGJsAUnKy4BIQ/8xDzwJ0ISH0gIUsqEl88oHXmBbrgr4NOTAPz6+cyNfAATB0pzvKTuEStdGwXsV+82JzXCaannxnQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(6666004)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aV9Sw7PI8n7mQ/saSYUroyP/Nv+zP8r/Iql3jOEV12XvzHAXk3YzaAtpkVDEsYN0yF2XNxq0Z8i1+v9ndWm9iMvmSLVuc/vQFfsnSvxJUHls3geQUfT/GPmb5CSMkjWj5PHCUS6kLVUVLVpwKzY71LxVHtzQAhwW9EKcEhbqK7OCL52J66viVep2rCwvalyZu4C1cbaw4dcg3+OrWU2aSpbcaEpoUxAZ6Qh86T6Msuj4VugEp+LjK0Lk9XGPnDUqOpdEtISHucOyoG2U6isB6POOXuwSkkO5tk14a+hBpUame1Sffmk+C6WzfONe7gi+8z/9pYx4m7EYL/71YZNWufYjAYhBWy9jp2p3022Aqra5nsejFTYt3A7NZxCq2zCGaAz66MAH9pgnZt9IH4WS6RRELK0oWTL01OFCAYXp9Infay4SXUAtazLzXCrsyLQYsHQPbQ/PBrhegsDmpgMsiNKgu7htK+oKnRdyxeyad2EcQ8Ep/r7BvFlB3w7xQ6xSAToTBEu6eWpODzwVAcI/0S0vatUsPp0wkoZfD52hLF13UyW9KeW9Sc1nq44zswMtR8eSo7Y1IoGjw/awbmMmvuMYY3b4Ugi153d+4cTCnEB8CTegAxSz9CO7I6U0Hvyhw5fPaRXFTJnbVeULfuzj1/Zj1XgU9tGGejOfGonjkTLkFB8HwMeBoT8MKcgvHa9vJh2xYtrleupEA7c9EQahHe/jiRI1LX7eVj4p4mLMgKb6NZnlmSavEuYGbPMhfSm4EejZw+N2od0BYqiogPKXvLTIr7TusTBCYus7CqaiFvRyS30I90QXIE8TRQCQjSFqVzUjW3oSeJ6IPRwkHJ09VMKjhkKD3/RZW+ircZyecT1141hOdUooC0ODh5FQM/llThzo8qgHkXofHbgoygOXM1BlqZHLiH8aw+vZx70anh9HlC+PTOJY/UYbPtZDfUVdVCSOkkfF0qLvMWA8qHYDJ+IotmxeBsnQBJdW8BksLUPFW+DNaCFyRh1ZepiSI1glImZBLyiBAF0Y+2+E0qfMDBbmzJuPraHsLFllGjWzYtzDJi0VntdER5KM3v8B48Qa5rweTwFJ8E2CnR8BWAoNNQrKCPW9SRXwfZ3O11Gsfpk3X8J3c7osBCM05HC30uM40YFLeGaGZiYo2aTAZxz+VzvdxIrFn6PhkSLFPPYyqklJFo0xIxBE+5miMxHaU3l5y5B2kRq1GNp1jD7ZmXYYU/iW7U8K5jXsqea+NcPcpsc8yuz+DLDOvLkO7k8A8amgkvEDas8PqSKXqdbg9+Mg/KMMat7f3ElEIJuJGoVOSqlwDLochTdXz3eWqJeMqCeY X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: b7ef0805-626f-45fc-dbb9-08d931a9e467 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:40.2823 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xtXVNZbBWdoEKdTgKofR21vc0Y7Q3FrEzvZYSynMReMMI+AK95MxXiaHerx5AsHcnulMRgZsHYUCinNHjV3Mxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/utils/file.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/file.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/file.c b/drivers/net/wireless/celeno/cl8k/utils/file.c new file mode 100644 index 000000000000..b42d78f386e4 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/file.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "utils/file.h" +#include "reg/reg_access.h" +#include +#include +#include + +size_t cl_file_open_and_read(struct cl_chip *chip, const char *filename, + char **buf) +{ + const struct firmware *fw; + size_t size = 0; + int ret = 0; + char path_name[CL_PATH_MAX] = {0}; + + snprintf(path_name, sizeof(path_name), "cl8k/%s", filename); + ret = request_firmware(&fw, path_name, chip->dev); + + if (ret) { + cl_dbg_chip_err(chip, "request_firmware %s failed\n", + path_name); + return 0; + } + + if (!fw || !fw->data) { + cl_dbg_chip_err(chip, "Invalid firmware %s\n", path_name); + goto out; + } + + size = fw->size; + + /* + * Add one byte with a '\0' so that string manipulation functions + * used for parsing these files can find the string '\0' terminator. + * Make sure size is aligned to 4. + */ + *buf = kzalloc(ALIGN(size + 1, 4), GFP_KERNEL); + if (!(*buf)) { + size = 0; + goto out; + } + + memcpy(*buf, fw->data, size); + +out: + release_firmware(fw); + + return size; +} + From patchwork Thu Jun 17 16:01:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BBCDC49EA2 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 221/256] cl8k: add utils/file.h Date: Thu, 17 Jun 2021 16:01:48 +0000 Message-Id: <20210617160223.160998-222-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:40 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 198256ab-fec2-40d2-08e2-08d931a9e510 X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3EnfpAKgNaTdtufOIR6qWcElSdYMNNzUB3KgO1Jpi//IDdUoVjZVISRQ1rqWTnlEsYeySvthdBpERQjKAGpMx/msUwtdQ9AniCG5I4KbeAN5hNnx3jW75AbBQlQBhLiAy8QuDkCXUWJ4DL5obP492kd3Ji9g+6sDOWSjvOG5ICZqZMCMPgeApoyAMxsRUgJrvbKNS2bcNOLBGUEFKuXJJO7Tjrelfmna5QHAzHPp+HBwaEI/WCR2TOvOxLcwMofUB1+eVbPWziSfQdEkmMrgpC0MPSRif9PkmcVlAuB5L6vObVkDcoMuiTfWZIKHJ7VQYgkq1RGJs0b5qRPucsLAyio9Oou1ilg5PNz7bPa9W4qTYBXphhqAUsPcrjHpvD1h85YDXbObrmz7jizwNVxDCHVwQmGh/tB53okOL5oo8AHYLF3KgqK8ZOdUjd/bl6FPYQQFCUcKW+AjI1ju4ZFAirLKqhp6Hi1G8kvvZkCQWKyMVtNyJT0JR7sfJ6+6VahCzbIvMzZv8Y6pEXsakluTmB3LWuAxM1mdt22EjNoat5zcPMLCXoDZwrnE7Cf1clMikHuLQWyrohpCOoVgrqh5ZVmIc/Ws0xioPDFPykfON4e+zHujpOc/VaC7d+jLPEjv5iozLAHEz8JNVdBZtwk+KfcUoFAqr9dy2qe0bVWpJnbAWercyrDh/8OPCXai2X9zvQJWbjpcNKQfDBeush06TA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RCpaZUeQtSflhfGvEOOnfJc9F1Yqc2u+4cIjL1NjqBStHnKJPvpc3/m96uhmUO/dfILE29w6c42twpGX4nRCHXZLna5Bq+N+BgbirNZs1XM/OXA2AISB5QxdEaIWWXG9FhJVNiyrWdj5DVvCuob6oGK5o6a7HduiJcpPiaGK7GR83htyQy/VKBPDOuG1V3SPcrpCzSCBc3YQBPeSxTaw2XdeaRdackov0PUg+ezOGlR57aEvp2XCYROc/WdLpiOekAaTr600Z5+jpFvAsn6EzZzmbY1MStouR+HvODRpor49R8krEHkOSv+IBmI730yRk6U3DHQ9T9/z5YKnvdJluWo52HsdPkNOntYCGWKhr16X/Luxgn8clz0tcsdG4cspp0n3/79UMPTUZJOIN2eiXkBr5e414X+RMoaqORqLnWHpbMqhsUhCWuz6faCA16mtQ+WfhSRmGQCWtCeDLROFQTwXM1qj5lKpq5ZjoGUA7sdZ2QZ1aI42Oqyd7l2gzDEE7RPgryiawlMbCkHwN91MyJfbPY67407FyXK+JA9rmxH81WuPyMLjbFcSseXzeVnRvKparyf8IrVtI6Gq2IFD0H1QpCarnl4K7hyuPx49pbAlZg6D8q6gJNdFpG1p/W98HCdyEscy/8n4Dequjg1uOOKk7fIC4/KCz9I7AwIdouNTkftXDmdVgF+hIUnXuUTsbpBVDKDLRge7GlhbWA7GmaeyDDzbIXU5djEX5AzJirR8nS8HyKiNlKQ76Tq5ALRgoB7UBRqF2TswXOvlIX4urbzRORfTj5VSZvlespFtUcZcEcpbjsz4di2jI6torA2vXQ97UvRTnkLJuAYwJIHNU0oLpxPc0T0FIT+6giGew6gpMyn+klZxbEteaiBSnp9QW5DLZ70Qk3i48SR9YVXTnfs6y3XcHS/4ffF0hbCsb9110up8N5Sifd+66nD2JEYxxsLO7oHWpXenEDWDJLHl+34FILJntmJKhvxyIRPw8qrxFyta0FbX5iyZi2ZbNsrUnPSrdnQr7pAMIIgVAbayWz/vYcorJKHcaofuznH61uKunxLTZdU2MeCiuO5jUDhlQhC0cmfP2TV35ki6897VCEQU2XCfAuSWdSZsIy2D+WqDAyAAJhyVNBY2NJUF1WwCwICQD6bXBkwqsogkEhcbAikTotcMt23LB9tIzTqdc6G/wdOJTsiNP7277gXgORVFL7Rbyjccbhqyksd5x2l0ScraUR3UZ1wKZs1K1LBLiJZ3+XrDOFAYjgwA+l13G126Ra5kpN/Az31NPcgj4zRSOhWi1ys7bcxYQWx8qxHtWXaDumgNTqvnsZ6+Z8kRx5rG X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 198256ab-fec2-40d2-08e2-08d931a9e510 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:41.3336 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0O+EE2BYvKpNHIQe4jWkfTcM6i5vlpCaSWBYpKDYHzcRqadz/Z83c73C0fbVkz7XhHCGGe1a60EPCUtCf279PQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/utils/file.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/file.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/file.h b/drivers/net/wireless/celeno/cl8k/utils/file.h new file mode 100644 index 000000000000..331666524ef5 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/file.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_FILE_H +#define CL_FILE_H + +#include "hw.h" + +/* + * cl_file_open_and_read - Read the whole file into an allocated buffer. + * + * Allocates a buffer large enough to hold the contents of file at @filename and reads the + * contents of that file into that buffer. Upon success, the address of the allocated buffer + * is returned (which needs to be free later). Upon failure, returns NULL. + */ +size_t cl_file_open_and_read(struct cl_chip *chip, const char *filename, + char **buf); +#endif /* CL_FILE_H */ From patchwork Thu Jun 17 16:01:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E32E3C2B9F4 for ; Thu, 17 Jun 2021 16:10:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D200F61407 for ; Thu, 17 Jun 2021 16:10:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232867AbhFQQMK (ORCPT ); Thu, 17 Jun 2021 12:12:10 -0400 Received: from mail-eopbgr130071.outbound.protection.outlook.com ([40.107.13.71]:59907 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233875AbhFQQLD (ORCPT ); Thu, 17 Jun 2021 12:11:03 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Y3v7iEDBvRGnQPLPUg89htZI0pOh2valymihUkM5Xc3yorcTjlal+FKc5BL6vxBMG7WQ3Mxxr1MvZlGQ27W394f7hVDXyN/dDDkL6Qa545ZsCN3qR/MXFn8MxfjT5D+dEsUNyEbKhaZbCsmY9gbG5bVs6Cw63jo2JTn3EYC5H0PYm+ZCKLhcuFzgTPq9nfnjU3zMSHGm3/H5u9Ao434pvqGmvEjZMt+Jmds8tCHG1EDXA4VsRd4mNFtHfHydhGgFztAMiuY6dMDUU5/lIrckGU+8v1lhv5ErcuO43GeD9cRuQE0ZDeeZVY8SxQ8VB18wVm6HmSZe1RU2TNuBMe6Ngw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zRRGHQPn+ZXACgtNvmBMs49eCMFpnZpu+Dq7i9JatSc=; b=fsNEH9g8MPq3FZhzLM0yqHZwoPCKFXorISBf6nMzCof39ee18CwzoBuj79MAGPusjZTRfEG7lnPqBW0w83lWxCM75a0/PnBMLh1QKkGJYDaM2qD31h/Z2SbHia5sopQyq1NwF+rtdrNWBHZ/3J79eUEUy7sQHwsKY/zKTsUz0eTejiK2V2YelSCWwPQVenLFQOTQJ3B01RhTWSQZ5Ki5MfgHjmh2rh1h5vhYJHRIDIoWeP7RiFjgIdMzesFq5cIAJIZqD+0IuzLZezYUNk7Fl/8gYVQJjrApmQI0jXm+OUNFNUKpmwGDj0FYHyW+C3uHKvDu/S/yuRAON8xbGydd5A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zRRGHQPn+ZXACgtNvmBMs49eCMFpnZpu+Dq7i9JatSc=; b=2339EG6PGlDzZYxnKBRWDchgcIJJmugbbcLD8g1YTkS/n1zIdyrUJV7XqvALGZ1PzSDKIV4vtxgTS/p/9vOLZPUQ+skWHU2FMQSP1JoYhWhQmEfeVIw+0mWqffYgAiefsILp3YShBOuZX/Xju/M7AcHHklL/k4GulJKEvDs0+20= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0452.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.23; Thu, 17 Jun 2021 16:07:55 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:55 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/utils/math.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/math.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/math.h b/drivers/net/wireless/celeno/cl8k/utils/math.h new file mode 100644 index 000000000000..f03bef46f3eb --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/math.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_MATH_H +#define CL_MATH_H + +#include +#include + +static inline void cl_div64_decimal(u64 dividend, u64 divisor, u32 *a, u32 *b) +{ + u64 remainder = 0; + + *a = (u32)div64_u64_rem(dividend, divisor, &remainder); + *b = (u32)div64_u64(100 * remainder, divisor); +} + +#endif /* CL_MATH_H */ From patchwork Thu Jun 17 16:01:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6810DC2B9F4 for ; Thu, 17 Jun 2021 16:10:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BBA56141F for ; Thu, 17 Jun 2021 16:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230411AbhFQQMO (ORCPT ); Thu, 17 Jun 2021 12:12:14 -0400 Received: from mail-eopbgr30082.outbound.protection.outlook.com ([40.107.3.82]:58153 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233901AbhFQQLG (ORCPT ); Thu, 17 Jun 2021 12:11:06 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ngRKHYytTH8qQ9Nsx87kEGkQdv3SVGM6RwJTtE5WB3zTvFdQ4Wwx9Uhs0mir1qh0Ypv/BbU/hpBxJAWtAkBXyy8koaayl+2VdKDwg3lJ+ZXOWhYg9WQr0Xs3IZmJr2es1zcCanNBCxU7lYsZDzcXyRiGGyOMSmKdt00rP6BFiaPNOUeOWw+duO6yxD8Wuk2lm+VXsdFfbK8eKk3zhB+P+7yEWo/+OWcxYJgffWQ+xoKdQ9W2/pzzIMqyq7WS5z80MfjyqpzlCqwkjmBYSoTmVT33YaPt+56an8G/XHvbjyxs8r0vksIwm102gmYyYmJN4kEQ314Uo1ouKEPXiRZnrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pqBCiGiNkEMI7C+1H4LMo7RnmDW5KH+Ea1KhexpGGOA=; b=JlcxU83/vUgeNVTfQ59hANz2CjpPTdjsO4pSJYIYNCur69sXa5BN7oVI3bYW3apuXayvJsFlck20o5wmaYO3d4E700Tb9nwvlWJwD/bbAm+6aRxAwqhK+DQtl5y8uK9LXGom0HvNBCJfjKdfndu4MrbHFYIsBOOrQbATq7FdZqsTIFsW2w4DHStE7ouCQTWyWo044H6ZzejYq1RsiEHcfZKQRRQFO5Mt7oGqgbXIgKn8CumvsgLvEomuchrCK1KsRiXk+jRSSBQPUZ5zw6UMzCVIWccHIgH0Rz07ftQPrf57/SxaAxSN8wAeLHrqkMKZVKufu71xuj3Bne61lZqncA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pqBCiGiNkEMI7C+1H4LMo7RnmDW5KH+Ea1KhexpGGOA=; b=1Hp8mA4+ujxahtf7aOi7sM2DaGpnSl8G8DUlJjwAqUTqov5pXSwlkZF7Mjfuo5yDuV58C+k4FwpE2lIXEEMa7771cuCY5e2i2m1dlakpsnZqXfmdfV1C1iIMCAvjCnR7rudXWijdRgpSdAl3ijngmRuidtX95Ohw6oMmElW871I= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0452.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.23; Thu, 17 Jun 2021 16:07:55 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:55 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 225/256] cl8k: add utils/string.c Date: Thu, 17 Jun 2021 16:01:52 +0000 Message-Id: <20210617160223.160998-226-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4baeea58-73f4-4162-6801-08d931a9e78e X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:270; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iJokDDTAKToEb0mgpUBviqOuIh68uvzYZLN9QhjoZt+IznD6fOncdT65rKy9+Q15doqVvw3/jjJ48fT+b5Ebt2QJofUVjTZKmMkordjd1VtTvAnuqBCikpUVXM1NTPfcEJwDmDDx1sJ2dsSLK03t/9UZOuaLrP9ezwyOPVqL4mTuH2+AS08ULUmdE0vNFqjUwzLrf+HM28ZndBVAzKA19Vmnc239qETLzz3KPnQdStkYK7uAIDthdfQbbKD57BpWuFI62k0yfEAaH7eelKmux7sSoR6UZw7ghaRWRBVVKDOFGImOgFn1ut3pEcPEqjEkFUN6g8M93ZZRBF8fneVJcWCO9RC8PEZ7GSHadtCGp3xe5K4kJPY3oRprXrXmeF1tfBt9txuYIs/Qqn3Sgvard/dvgEgFjVzQAmX8EglJ34kVjHagsKTe25qlu3sDZrsqybp65rJ7D5R2DK5w4qc0wEoH++tpyRrQF4IcdPK9e5BWGOwJQpDmQ4B7AzvAeJxu/mxP4jrmduCZhWMiHp3OlberVuZWtd1FSqlsQPXtLr84D2PCPnV4iFFTge76eiC5C/TUjQgu5qhyzpfVRSUg9vtG0iLz8fOoqTvHMc/H/TsHz4XKjter1sJsmous5v8AKudw44g/1qEaoSej3Fgj3FrTvqXASAppxnZ2JtH+J+VUvNh6mPnYRR9MYDl+uXLg1IXeQWxNkWCsP3SHP5T5Vg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(6666004)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wZ9X5iG4TwqsvtgWlOQEAlu4oT1OX5BqkVH2d1hey6qCrZSvq425aHgGXcXVI1jkf2DO8bYbS4E8eGqXlu0aXAZMBuWcYsWufyMTbf5myxu+kMM0CyMwDhcOmzCp4TheTcV3HHimzcRTqEwXs2VPdUn6ZxRGzqyZKwa+u58bGbcWtU/4Y3EiOaTZA07L9NX5bzJFjS3QluXjxmwmA3Xg7vMVw7zvWax+SQvVQL9zWIq85Qc/Q2r1oQ7ZNQbmrOqPIi6c7QIJeeS2uVIfGdxpIpVBLzP/vrgBZDAAxj9Ho1UGRqG/sZOPVEqsSYxP/IDHC9JcrA1DQXSvwZYHo3DGNSsWEE90BlRUNR/+4Qs7I9w0IBFFMM3FuJsj1bTtaHgzoAM34m2yqMbS5CMnPONtVWDGAlOlM97Hl7xdlwR52dswG0EQ4N8tup/YtQzKahIku9laojvyRf8hxLMzbYo2HZsFcLX9ybZlwJvTbyjF+tDr0hzyq1q7pVSOzZ3yj2h6eSok4o4b087znomnvj+WrO+RrF2BJftE+OgobsClQfvGLNMiJA3wgvXlCwcWE8a8YoMH3IBys6lTMIPpWAT8t8oPu1Asp40KuWSyKI1ptQwsSUIMxLTee+dQmjeBJ+WDC5D13nRYnI51M54Wt1sDhQbBb3rWpDXxsu6qO50mTEF31k329yyIH2J1AHA6A9WWiVtQCI4Bxk6XrDrCajOt+ENhzLp3QJLTERKJLMo9yoOb40az7JY2vAIlPXlFOOeqxnkIgqatRuCiHXkhopOCocswkyP8MotCUBoCwnhjkg2IXwSjZWQQG4z8ZHEdvQ/OqCZhNYLqt64mhRhU5JUFaQE5pQYHepXTL4RgqAziumCJFfESOf8tm2v9evdbzwQoBikZheDw1ZSbIyYV/EeTfRvSWHe/OW7aXB8KlthrC9O4sSyk7HM6lWP7UzWpCaUo+J9qlIhVFdfZoju34p5Q3Jx0Fhze0AF0lDzc7cMujDMNe+rmBuNH/rGjeod85r/8HS+/b1zNqSdneZPEAV3Wdxz2/5keWsNNBjuph5g+EftX+DCl/qbvTzJ1vDNx8cCEZEab8L15JtptJE93J+u1s/MYouHMTgZSjAgtCvp3AJYANy+Gp0fJfaJlJAYEBkljkcWoBC6TUD83Y9MMJWbeGZh7VvkBsKZOkvoEnhtrS57vzERsj/+ZoztSeS3vrKg5M0sl4X4+EOId2KQNPPUUV9llkLKndNdhdRtdjB6BJWglAUF+o/Wzd+v6vzpebshsmjIDJNqR0ChnSsVd5BxIs3wrwG1UGSWk3CHgKqwK90UWN7TSqu9ekdPAF8JysNGq X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4baeea58-73f4-4162-6801-08d931a9e78e X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:45.5153 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FRUkqRw9vHAaHPW0zzvuiJz8tra0w5uy/ex8iqCo79SIkd/YkKs1tWGKoBWjK5lPY99wJYC4Gytb8yYUfhiovg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/utils/string.c | 235 ++++++++++++++++++ 1 file changed, 235 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/string.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/string.c b/drivers/net/wireless/celeno/cl8k/utils/string.c new file mode 100644 index 000000000000..1300563e86a6 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/string.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "utils/string.h" +#include "utils/utils.h" + +int cl_strtobool_vector(char *src, bool *dest, u8 elem_cnt, char *delim) +{ + u8 i = 0; + char *buf = NULL; + char vector[STR_LEN_256B] = {0}; + + if (strlen(src) >= sizeof(vector)) + return -E2BIG; + + strcpy(vector, src); + buf = cl_strtok(vector, delim); + + if (!buf) + return -EIO; + if (kstrtobool(buf, &dest[0]) != 0) + return -EINVAL; + + for (i = 1; i < elem_cnt; i++) { + buf = cl_strtok(NULL, delim); + if (!buf) + break; + if (kstrtobool(buf, &dest[i]) != 0) + return -EINVAL; + } + + if (i < elem_cnt) { + pr_err("src %s doesn't have %u elements\n", src, elem_cnt); + return -1; + } + + return 0; +} + +int cl_strtou8_vector(char *src, u8 *dest, u8 elem_cnt, char *delim) +{ + u8 i = 0; + char *buf = NULL; + char vector[STR_LEN_256B] = {0}; + + if (strlen(src) >= sizeof(vector)) + return -E2BIG; + + strcpy(vector, src); + buf = cl_strtok(vector, delim); + + if (!buf) + return -EIO; + if (kstrtou8(buf, 0, &dest[0]) != 0) + return -EINVAL; + + for (i = 1; i < elem_cnt; i++) { + buf = cl_strtok(NULL, delim); + if (!buf) + break; + if (kstrtou8(buf, 0, &dest[i]) != 0) + return -EINVAL; + } + + if (i < elem_cnt) { + pr_err("src %s doesn't have %u elements\n", src, elem_cnt); + return -1; + } + + return 0; +} + +int cl_strtou8_hex_vector(char *src, u8 *dest, u8 elem_cnt, char *delim) +{ + u8 i = 0; + char *buf = NULL; + char vector[STR_LEN_32B] = {0}; + + if (strlen(src) >= sizeof(vector)) + return -E2BIG; + + strcpy(vector, src); + buf = cl_strtok(vector, delim); + + if (!buf) + return -EIO; + if (kstrtou8(buf, 16, &dest[0]) != 0) + return -EINVAL; + + for (i = 1; i < elem_cnt; i++) { + buf = cl_strtok(NULL, delim); + if (!buf) + break; + if (kstrtou8(buf, 16, &dest[i]) != 0) + return -1; + } + + if (i < elem_cnt) { + pr_err("src %s doesn't have %u elements\n", src, elem_cnt); + return -1; + } + + return 0; +} + +int cl_strtou16_vector(char *src, u16 *dest, u8 elem_cnt, char *delim) +{ + u8 i = 0; + char *buf = NULL; + char vector[STR_LEN_256B] = {0}; + + if (strlen(src) >= sizeof(vector)) + return -E2BIG; + + strcpy(vector, src); + buf = cl_strtok(vector, delim); + + if (!buf) + return -EIO; + if (kstrtou16(buf, 0, &dest[0]) != 0) + return -EINVAL; + + for (i = 1; i < elem_cnt; i++) { + buf = cl_strtok(NULL, delim); + if (!buf) + break; + if (kstrtou16(buf, 0, &dest[i]) != 0) + return -EINVAL; + } + + if (i < elem_cnt) { + pr_err("src %s doesn't have %u elements\n", src, elem_cnt); + return -1; + } + + return 0; +} + +int cl_strtou32_vector(char *src, u32 *dest, u8 elem_cnt, char *delim) +{ + u8 i = 0; + char *buf = NULL; + char vector[STR_LEN_256B] = {0}; + + if (strlen(src) >= sizeof(vector)) + return -E2BIG; + + strcpy(vector, src); + buf = cl_strtok(vector, delim); + + if (!buf) + return -EIO; + if (kstrtou32(buf, 0, &dest[0]) != 0) + return -EINVAL; + + for (i = 1; i < elem_cnt; i++) { + buf = cl_strtok(NULL, delim); + if (!buf) + break; + if (kstrtou32(buf, 0, &dest[i]) != 0) + return -EINVAL; + } + + if (i < elem_cnt) { + pr_err("src %s doesn't have %u elements\n", src, elem_cnt); + return -1; + } + + return 0; +} + +int cl_strtos8_vector(char *src, s8 *dest, u8 elem_cnt, char *delim) +{ + u8 i = 0; + char *buf = NULL; + char vector[STR_LEN_256B] = {0}; + + if (strlen(src) >= sizeof(vector)) + return -E2BIG; + + strcpy(vector, src); + buf = cl_strtok(vector, delim); + + if (!buf) + return -EIO; + if (kstrtos8(buf, 0, &dest[0]) != 0) + return -EINVAL; + + for (i = 1; i < elem_cnt; i++) { + buf = cl_strtok(NULL, delim); + if (!buf) + break; + if (kstrtos8(buf, 0, &dest[i]) != 0) + return -EINVAL; + } + + if (i < elem_cnt) { + pr_err("src %s doesn't have %u elements\n", src, elem_cnt); + return -1; + } + + return 0; +} + +static s8 *_strtok; + +s8 *cl_strtok(s8 *s, const s8 *ct) +{ + return cl_strtok_r(s, ct, &_strtok); +} + +/* cl_strtok_r() is a reentrant version of cl_strtok() */ +s8 *cl_strtok_r(s8 *s, const s8 *ct, s8 **saveptr) +{ + s8 *sbegin, *send; + + sbegin = s ? s : *saveptr; + if (!sbegin) + return NULL; + + sbegin += strspn(sbegin, ct); + if (*sbegin == '\0') { + *saveptr = NULL; + return NULL; + } + + send = strpbrk(sbegin, ct); + if (send && *send != '\0') + *send++ = '\0'; + + *saveptr = send; + + return sbegin; +} + From patchwork Thu Jun 17 16:01:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1ED4C2B9F4 for ; Thu, 17 Jun 2021 16:10:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D79956141F for ; Thu, 17 Jun 2021 16:10:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233953AbhFQQNC (ORCPT ); Thu, 17 Jun 2021 12:13:02 -0400 Received: from mail-eopbgr130077.outbound.protection.outlook.com ([40.107.13.77]:23879 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233709AbhFQQLw (ORCPT ); Thu, 17 Jun 2021 12:11:52 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HytxgubL/AuzBxLaiqYj75yAM5qy81WGRx8EsEVLTyWNCCMLVE/19eDXn9CVjSMI4pMaDmLITDGZdVTcSYz+TyH7aXeyUx19MUj/jyn2XLKjtISSeIkzkxT2aHJAwOHnUKZiAFX4nZ8oLrhV0OobFCVIab4eosV7V3v1QOOOZHQouJmZjZ9gEp3Cuz53tBfW/MNYjw9XL4yir+uUhavml5hKB4leHCdpxU8/RZbDoIplyTMNFOm0Q/QRD+gkS8R7hw049F5LOTVXrf978EVJu4HglXIonXJQSfMGSuBbf5ubo8VvS70b/eVm5UGt0PjcIiPykNAgLfidDSJYsDcABQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lrAhmlWjzAmRFbllSeMdMSdDYRmifAX7wegtulbU8Sk=; b=YbkHqc5VeG+wlll1hEZwJw1ta0V1NnwCNLU7SdyVcoJ/IEZfJr5JYOMiN2TvzD5T4+qfEijTuAatvuEgCTqFDMLMlyAQc8WdcQomBBLc/vDeAbHO9ZCCgE41If8ToW4tSr6qtf9BDrw5cVExBJ7QdiFO7aGREAtAEXy4qFFuCi1kMi5ZibU6SzhgfIW1AnsCQzEg4XpWfsVClB5sSzesbVgQ1TgoFk0ms7U3PBOxU0w46aMRrtqIc73Z/fVALvqIqlosO75aIEY1YrA+h+MOkXrZj9JpiPLnXaB/MZB+ohrwXtgRr8i9HL1RwH8GhmkZlhfotC+X/15v13omBUKBVQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lrAhmlWjzAmRFbllSeMdMSdDYRmifAX7wegtulbU8Sk=; b=ixJItP1Mzw4zneURvdLByPSvquTQTHbeu6LEdNp4KfMXWaAwETBbvwAEy/gal+Xitfa9sGuhh3wbV93hkjP9g/xCj3eO/dPWXF6seDWnmztYyjkil8MWmQiRQiJkJwJ8dpVSa8mtqW8mZPcgoTgyqpuW/DnBAWMA5jLYgszZP7k= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0452.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.23; Thu, 17 Jun 2021 16:07:56 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:56 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 228/256] cl8k: add utils/timer.h Date: Thu, 17 Jun 2021 16:01:55 +0000 Message-Id: <20210617160223.160998-229-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:48 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 47cf599d-f4e6-4724-1748-08d931a9e99f X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5PkGNxWUPMtMAOLQT1cbvVl3fyC3ztabu8qJIV/+RWObDPHZ98a0WWIgTp5kDhLC6hMByvb/PGBSmYDhLRv1KgOVEYJt9J5LCa80yZqWzbhQf5soCcHo+wMvZkiSutfe2kPL3fB55yoqRaqoK5ED6WBAEMidC5eqTy4DtZkNpzNy6bWMXAngMtZlE/3T9tErold7ULmlcQdUTezIQQ2EGKk5nSQHb2jbBqPu/EqX4YmnCk2FJcCO5ihLU99ZOxzvVo+r0+HFnVCSoCh1+SBQRbq2fO9B/fdke/P1cWx64430QOJx7BrAI5zbRDkTGBg1t2PHxaZtS67vu9GXJxgxF2fecW08ck4gHQEwDKmkPQ4ZdwlQtymKyMLxZPxX3JdPXOsHa0w9hMFaayz7HK/xo1+9hFKKW70Zy2lswPGV7VHyydR7es/x3/c/7bSXHJ9nSrPn4JcJgF6BNcFFcUcpYdrCypYja5iWLPVfTOSjn3ilxRDvRUXE1lz8DXBkXIwqL3FQn9Ao83LKO0/v+15AsRP0nP2tR5W0CZeAJQB2e+yypV8ftMwJZQjRlMlannSakia7iZSPvsYSk+0ZKiOskZ4pZxyc6szkbIqiDPnFz/2p+pKs28Jof/K8tV2tFA3EyX5V91jTSrsHItlAaAgMA7CIlNo9KVN1OdMD7p5fOxW4l8pNcZNwzMl4jaRD63Po3XzLiqh1PkgVRFcivQbeDw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(6666004)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: grWlBfcwdGazvPW1ykgGkR2+H8alBFqhhIbY2DcTeKUgVKkmUZ45lQe/RnOAAjWLDokGvfoMz1qUF9EjP5gwoMkd3Zo+H6/bo74uxOYv2PEdWUmnbkhNGKSFIQxALR5r2z8as68sF+Cgb/srDf20/hH9Roo+OZxYaJ/l0WtwhAWFVD9DJEJbaSPIKUiakYTHMrvRWHEhEzGCapSMxlff/WpanxWikbfRqi3daNawz6pTx3X//mwkkLQ++DRR5Ks0YB4Pf1BuSBRIDiHhPVzM7QjEWDbmiq+EzsI6RbuPURTKWGoKZ9gdjovenDghwXwkOY4aLWcsgl7a6XRtL9N6n+kSx1OE0ki1zCKYua0XPWA5HdwL7AOr7c5LYjktqNIfKTnPllx/IgB/uRyHj2Q08cAyVGkvaDUAbxoRM9S7ILTI5g7enreSOgPBxUVVUZ1OLIBhW0+0Rzdgm2pGvexOBai7A1IKKA+MKOB0Udxrn2bvtzbn7y2pNWZKSI+dHaxB1/rj+JTpMAMovK8i1F3qscdiNvG6y/rQPXoFIgua0LUOQOg5UsOAtA1Fwr20ILkKIgsP+4WfPinpzVQ3KpBI0xE+u0m06ExsCOhPK03cAyd8TnRp1pCd83OrkpLL0qJ86AYQ3lCmAjSZYKzIiFZ80JSGDRzXTcOXGG6UNcqg5kuZwaubG0dHNa6BlNIBU27neTf81Ndzm5R37Lx+wn6jFzPiK4YNPqL98OAQYZS1IOHrki2eAqMfLKCNXTVfxgp7x8FDrehWqMrBZbZnCjcdczqF3IA1629+p7ImXhpV+81p/Jm/DD0jq993Of2h40hkZxdLBwoW8fIsbv0ryPPnki4wQzxJm6VlcKJcS3FyuV5PILqbXlyHcyDM5XRIDI0hgdo4Cp0xKblcEGMBVXIpEhJ1QFtKhDx0jOJ8BSlZyxtrIvcg3YHpx1tnNQFWrpu+qUe5CALFg3pGVVL70nNBmdO1yhRu7L9bi3987x/Mm0N6YcF1W+bhb/WsU2NnJI8dkPzLVBk514fBlQQakmbm9bCyNjO2rS0nkI+xZG7zp3g5CBFrYIbqg6xIpkqze6mfgAe+8fArpMVrN/FSRLW8jAfL1YPz1K1t3nWO9D67KeW1PtTUlXae10Pyh94X0/NWRSlJkk06G9L5qO+AxEnbMDPutrgdR+SED6Dn1WVlcVogkh4Ti2+OdYAZuproaGW9Ii7mFh6PVdcCHCkPcWQHs6FvJ1Ymgo1Fl5eEIaur0KmrrxxH3tpnzaWtFRer2Vv3uX7k+7sCCtZl3Aj9n9X4ij8fcpaKZGxEUCAjWcJFGcixaJodHd75qtgVEe9IQW/L X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 47cf599d-f4e6-4724-1748-08d931a9e99f X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:48.9771 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TsjI/mSB0fQjFMWXTkoekG93xQQ2d+wVgQHbMpx1B+3pz/TVhaz8yTDKccQ7uTXTMqTgjJ4EGBK4rbF0jhFwEg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/utils/timer.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/timer.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/timer.h b/drivers/net/wireless/celeno/cl8k/utils/timer.h new file mode 100644 index 000000000000..1481d8d78db4 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/timer.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_TIMER_H +#define CL_TIMER_H + +#include + +struct cl_timer { + struct timer_list obj; + void (*f)(unsigned long data); + unsigned long data; + atomic_t period; + bool periodic; + bool enable; +}; + +void cl_timer_init(struct cl_timer *timer, + void (*f)(unsigned long data), + unsigned long data, + unsigned long period, + bool periodic); +void cl_timer_period_set(struct cl_timer *timer, unsigned long period); +void cl_timer_enable(struct cl_timer *timer); +void cl_timer_disable(struct cl_timer *timer); +void cl_timer_disable_sync(struct cl_timer *timer); +void cl_timer_rearm(struct cl_timer *timer); +int cl_timer_rearm_offset(struct cl_timer *timer, unsigned long time_offset); + +#endif /* CL_TIMER_H */ From patchwork Thu Jun 17 16:01:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C312C49361 for ; Thu, 17 Jun 2021 16:09:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27DBF6141F for ; Thu, 17 Jun 2021 16:09:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233731AbhFQQLS (ORCPT ); Thu, 17 Jun 2021 12:11:18 -0400 Received: from mail-eopbgr10086.outbound.protection.outlook.com ([40.107.1.86]:64640 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233594AbhFQQKH (ORCPT ); Thu, 17 Jun 2021 12:10:07 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KfWJCn01JTNlGChaXZo/aB4LmBtEf9hBfOTPjZ32XBnzqUexfzvllHzrJOy2QIEtp0YYTDRjOjLrFhrHb/hkd9vTX1365fWFbUUV9k2SQhTmQ0mHHLRfbkFoBRLssbfvZgagROquFXzKohixtSxzj8wcN+PV3oCSldkd2Iq8sQqNOBGKys5SFdWODjPjpXSIKLacZfUq1flifZi2f7YevWTQSYr983/Cd7mTp3xDQEcK0OEPkhcP0X8tIKUM4kcRPqUzKwllVLeToRIJqYHQByJTYGhg2Ftk+jrj1pyS4AkRQ8QvoRBFl0tRX/KKW5dAHVmD+docAL1rJiPtmjnY7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MlFUXudKfigqF8NuTl7BLqfJKPJVdnATWkgl+sW9umA=; b=dMPpBSlyNnAUJqKFtOlNF6BLx6jr2btc/O1HcDS61mbdd5YQC/IIEgiMIykeJR8YJpAsK/hrUDsjin7TI4XHAr1Q5DTaOvfVjz3JDXD+kKILcWPgMkZLMW+Pis6VQl4gRKpBjxzYVQ4ygDR14XxsEZ4gaIoXIMKxmsUWEJNt0+cp9u/sqGG1T1/G/65ujTdtTpX5S0m9LQkOGaU5YF3JwutB0n2iOC5LGRKY56WCRuSbysxpDgfQ7xexxAE7F0Jx26a4k8YAXDeBlmhYRkdT2jgHrsPUUdjUUWDDyGja+D17MyuAJspInniEjuCGRQLkgDS3yKeL7FVV/aVbrNj/4g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MlFUXudKfigqF8NuTl7BLqfJKPJVdnATWkgl+sW9umA=; b=2W9KalOfVVbWZMXlbZzZmnqWO4QEQNQEX0ZfOUw2gWKYkh7rvc70KstdGOv4k2BFTzDl+x2eYNb2LvMaygtflzTfQaJ9UQuXuoYXEBz6chF4yxuFT7O0oczg/wBBANp5qsRPVKJpJo2BZuksdlwIHQaVcO/ytcF+K1OpSXqEjvE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0515.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:45::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:07:57 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:57 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 229/256] cl8k: add utils/utils.c Date: Thu, 17 Jun 2021 16:01:56 +0000 Message-Id: <20210617160223.160998-230-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:49 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6fa6f399-a8e3-42a7-57aa-08d931a9ea41 X-MS-TrafficTypeDiagnostic: AM0P192MB0515: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:101; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qMy0ja2FNmKCUBsWXlMKLm9FNsV0ep+OoFa43NsY+mrIiK5dboBmLaVSl7goZbYrDvn09y6qbfIzAxClmlws+SfR4OCWdbXcdrcXRzjpt4HLXm7mJopqiNBmT3avIHLjfu6pSVA+UC9OnHwFDxho5ZoxLs5B5N8jpoEaV19qk4i3XE8Jq1sfPRw+oy2sXzUzvbDshQQNkYGm45tdie4ljqF7z+J/dn7dyIsmeFlYgV5d+OPETBB9CV0k6zV14qxbrPxZTb3H+1GlgTohYs/4beljPL9Ti8coCnwr371nmlfVT2PfOFTI60ZBEUM5BoOBcjxu8JX8dRjq34nbe7r6vMzn/oSR1pp9WDR41yYZdhK6Gk5IgSCQqPeHqIeEBhJHCXpXQg8ql2vLiUZUZPJOm3Mj0es95pu0IjRk0xLRjMFqWHA+6G1g/vt32IKvKXehyjx8L4r51KsAjVIog9GuuLHcNmjc5ucQi/BYIzEJFlpGY3t2KKWMN6zcnT/g0fkaVWhEQ++qiI3fHfcGRGg6MkA1DfBEOdeIdF+iX1XhMmbqH27B3vGi8qWiQLrmpleTUGFPwPUMnOPErcmdHArRSnBP2eodngLjTx67FPNOtAv0b8WlENm1QNTF4I1yh1PAToBRYK2JnPUIN85stDqZQsx2i0xImts/tEJF2h3hqhPFHl0agWKbKYQOkTazfNxN2LX38Xl3lFav1qO2UH/xeg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(376002)(39850400004)(136003)(366004)(346002)(4326008)(16526019)(83380400001)(1076003)(8676002)(9686003)(55236004)(6666004)(36756003)(478600001)(8936002)(956004)(186003)(6486002)(38350700002)(6512007)(6916009)(52116002)(86362001)(5660300002)(2906002)(38100700002)(66946007)(2616005)(316002)(6506007)(30864003)(26005)(54906003)(66476007)(107886003)(66556008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uC/jkwiEUrSxl0dhJdBcEqwWwlRfUvB9c6U8eYbSCqCUdZCw03r1yi8MeladaXXUSyIFzGZp3enwzN2PCUr7s9X67PPyDFyBXdgeMl9O5X+dSdhbDmBaE06Jb/Qob8o9p5kMjVOtCRSDdFjQjfENwRek4ZxCNenjRqbpMx2Q2mjqC3S6AFumhW/tNMb1CpsGthURammCl7vM/d2VJ535rsNZGd3GcmRtM+pM+MMh8qeTdtsxlXvF83CG+sMw4JS+HLxDpe1SvnQeWPvo/KTtbhOGr+sfC9KM2tKlBAZOaR26NdwFFK8Q1vObJfNUAWn53BxYixQVOWVwdpae8h8P+bpTpjeKG0kpSVjvsEa1RufdAAZ0KL/qlk1HFkhKFS0Ap1snSay3Q+5A1cqmWUHA6wJVcHFwuMpCTBOUV4ZyEYYg27D5Qc2nXCYB9iJexwEI/7jkHSJ/PWjdfhYkf3MgxDiTiz3XOL9ZiG7sUssY1rwN11gYX/4jLd/KH+FEjxCpBom2LNAMMOBjGMTjw4OrRW8pXxFKX8wYJWJmkNFTzx5bzlgdc8/0SWWNmDBuOjAZOCAJDJZLM4Ib/vVp4Yw60G5f4UB1ZzfKb1Bd0j5Gd/jaggiuRqCb4onOJxyj7ZQxWjGfpHEeBBR2eR4xOHm9nHb/+ZVjH2VJsT8Oh3q1GuDSZ5IZrqYAsa+jExFZoH0aG7M8FhWaLr82m9WLiONnNXEacDk7twFNQnTh8OfygoTpbtAESR7VHaoWBMJ6SZ2gg8wouX9odtiZwSOzkbODN6QhLnc9OYAEthQrabtR7TGLQcZ4LySOgkcXrLyH1XRreRncPWvc8Pew7ZhHiHa1D5WAOlsr7pO4yWknNa8tmQ27h9KCc7h3gSt7PFTIPKsOn0umFe85MEE14w4sSISW2NRk7aChaz6aesFGQHlBPeYfiIpz+B6yBNEIsOfT+G7DX5v+nIiqI5S1zy8KLrvUBfOpRvy/vhWbTLhMMHllaxUWiYrM/a3VMbUE+20Sqo5j6ROH7r7Qc7laPiIwGpF6+8wpfTj+xfnzbaxaBWwoqB7J939vNaiufpM55jmfMVYPWVlgK1SVh50fiiu20Hz4WSoi9z5Vd4YOnuTSkFTN1lVfD/wjv8vPgsKdoPs7hs8OZgm2r3/zinwh8R+GZcZVJvy5gFKMBGmEC40GtitovpccGQJM8AUCIr9+CmADIeNqoH+TCf/uVG+6r1DJwHKsFujz+1JjYWHZVC1lZlviWutEJ9tG3eAwLYiVmb3XKrgu5lrcB+IEE7W9385VHI1Xox95JmsJck+PdL/LOapW5TquF9zx1yMT3pegMegcatRr X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6fa6f399-a8e3-42a7-57aa-08d931a9ea41 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:50.1002 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SwnHE6WZwpLvN94MakPTRbIhq8Az8Kazy06QM5LZck0r4tVjDQYbJr7zfiD0EhhxUwtxZjYnDdt4ZQoM4ziKdA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0515 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/utils/utils.c | 388 ++++++++++++++++++ 1 file changed, 388 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/utils.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/utils.c b/drivers/net/wireless/celeno/cl8k/utils/utils.c new file mode 100644 index 000000000000..6d6f913ae95a --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/utils.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include +#include +#include +#include +#include + +#include "utils/utils.h" +#include "rx/rx.h" +#include "tx/tx.h" +#include "fw/msg_tx.h" +#include "debugfs.h" +#include "ipc_shared.h" +#include "rssi.h" +#include "traffic.h" +#include "reg/reg_riu.h" +#include "reg/reg_mac_hw.h" +#include "utils/ip.h" + +#define GI_08 0 +#define GI_16 1 +#define GI_32 2 +#define GI_04 3 + +#define GI_MAX_FW 4 +#define GI_MAX_HE 3 +#define GI_MAX_HT_VHT 2 + +#define CL_TSF_LOW_MIGHT_OVERFLOW_TH 0xFFFFF000 + +static u8 conv_wrs_gi_ht_vht[GI_MAX_HT_VHT] = { + [WRS_GI_LONG] = GI_08, + [WRS_GI_SHORT] = GI_04 +}; + +static u8 conv_wrs_gi_he[GI_MAX_HE] = { + [WRS_GI_LONG] = GI_32, + [WRS_GI_SHORT] = GI_16, + [WRS_GI_VSHORT] = GI_08 +}; + +static u8 conv_fw_gi_ht_vht[GI_MAX_FW] = { + [GI_08] = WRS_GI_LONG, + [GI_16] = 0, + [GI_32] = 0, + [GI_04] = WRS_GI_SHORT, +}; + +static u8 conv_fw_gi_he[GI_MAX_FW] = { + [GI_08] = WRS_GI_VSHORT, + [GI_16] = WRS_GI_SHORT, + [GI_32] = WRS_GI_LONG, + [GI_04] = 0, +}; + +void cl_hex_dump(char *caption, u8 *buffer, u32 length, u32 offset, bool is_byte) +{ + u8 *pt = buffer; + u32 i; + bool end_nl = false; + char buf[STR_LEN_256B] = {0}; + int len = 0; + + if (caption) + pr_debug("%s: %p, len = %u\n", caption, buffer, length); + + if (is_byte) { + for (i = 0; i < length; i++) { + if (i % 16 == 0) + len += snprintf(buf + len, sizeof(buf) - len, + "0x%04x : ", i + offset); + len += snprintf(buf + len, sizeof(buf) - len, + "%02x ", ((u8)pt[i])); + end_nl = true; + if (i % 16 == 15) { + pr_debug("%s", buf); + len = 0; + end_nl = false; + } + } + } else { + for (i = 0; i < (length / sizeof(u32)); i++) { + if (i % 4 == 0) + len += snprintf(buf + len, sizeof(buf) - len, + "0x%04x : ", + (u32)(i * sizeof(u32) + offset)); + len += snprintf(buf + len, sizeof(buf) - len, + "%08x ", *((u32 *)(pt + i * sizeof(u32)))); + end_nl = true; + if (i % 4 == 3) { + pr_debug("%s", buf); + len = 0; + end_nl = false; + } + } + } + + if (end_nl) + pr_debug("%s", buf); +} + +u8 convert_gi_format_wrs_to_fw(u8 wrs_mode, u8 gi) +{ + if (wrs_mode == WRS_MODE_HE && gi < GI_MAX_HE) + return conv_wrs_gi_he[gi]; + else if (wrs_mode > WRS_MODE_OFDM && gi < GI_MAX_HT_VHT) + return conv_wrs_gi_ht_vht[gi]; + else + return 0; +} + +u8 convert_gi_format_fw_to_wrs(u8 format_mode, u8 gi) +{ + if (gi < GI_MAX_FW) { + if (format_mode >= FORMATMOD_HE_SU) + return conv_fw_gi_he[gi]; + else if (format_mode >= FORMATMOD_HT_MF) + return conv_fw_gi_ht_vht[gi]; + } + + return 0; +} + +static u8 map_gi_to_ltf[WRS_GI_MAX] = { + [WRS_GI_LONG] = LTF_X4, + [WRS_GI_SHORT] = LTF_X2, + [WRS_GI_VSHORT] = LTF_X2, +}; + +u8 cl_map_gi_to_ltf(u8 mode, u8 gi) +{ + if (mode == WRS_MODE_HE && gi < WRS_GI_MAX) + return map_gi_to_ltf[gi]; + + return 0; +} + +/* This table holds 10^(-110 -> 0) Q39 values for rx RSSI and noise floor calculations */ +#define CL_EXP_TBL_SIZE 111 /* 10^x table size (-110 -> 0dBm) */ + +static u64 CL_EXP_10[CL_EXP_TBL_SIZE] = { + 0x7FFFFFFFFF, 0x65AC8C2F36, 0x50C335D3DB, 0x4026E73CCD, 0x32F52CFEEA, 0x287A26C490, + 0x2026F30FBB, 0x198A13577C, 0x144960C577, 0x101D3F2D96, 0x0CCCCCCCCD, 0x0A2ADAD185, + 0x08138561FC, 0x066A4A52E1, 0x0518847FE4, 0x040C3713A8, 0x0337184E5F, 0x028DCEBBF3, + 0x0207567A25, 0x019C86515C, 0x0147AE147B, 0x01044914F4, 0x00CEC089CC, 0x00A43AA1E3, + 0x008273A664, 0x00679F1B91, 0x00524F3B0A, 0x0041617932, 0x0033EF0C37, 0x002940A1BC, + 0x0020C49BA6, 0x001A074EE5, 0x0014ACDA94, 0x00106C4364, 0x000D0B90A4, 0x000A5CB5F5, + 0x00083B1F81, 0x000689BF52, 0x0005318139, 0x000420102C, 0x000346DC5D, 0x00029A54B1, + 0x000211490F, 0x0001A46D24, 0x00014DF4DD, 0x0001094565, 0x0000D2B65A, 0x0000A75FEF, + 0x000084F352, 0x0000699B38, 0x000053E2D6, 0x000042A212, 0x000034EDB5, 0x00002A0AEA, + 0x0000216549, 0x00001A86F1, 0x000015123C, 0x000010BCCB, 0x00000D4B88, 0x00000A8F86, + 0x000008637C, 0x000006A9CF, 0x0000054AF8, 0x000004344B, 0x00000356EE, 0x000002A718, + 0x0000021B6C, 0x000001AC7B, 0x000001545A, 0x0000010E5A, 0x000000D6C0, 0x000000AA95, + 0x000000877F, 0x0000006BA1, 0x000000557E, 0x00000043E9, 0x00000035F1, 0x0000002AD9, + 0x0000002209, 0x0000001B09, 0x000000157A, 0x000000110F, 0x0000000D8D, 0x0000000AC3, + 0x000000088D, 0x00000006CA, 0x0000000565, 0x0000000449, 0x0000000367, 0x00000002B4, + 0x0000000226, 0x00000001B5, 0x000000015B, 0x0000000114, 0x00000000DB, 0x00000000AE, + 0x000000008A, 0x000000006E, 0x0000000057, 0x0000000045, 0x0000000037, 0x000000002C, + 0x0000000023, 0x000000001C, 0x0000000016, 0x0000000011, 0x000000000E, 0x000000000B, + 0x0000000009, 0x0000000007, 0x0000000005 +}; + +static s8 cl_eng_to_noise_floor(u64 eng) +{ + s8 i = 0; + s8 noise = 0; + s64 min_delta = S64_MAX; + + for (i = ARRAY_SIZE(CL_EXP_10) - 1; i >= 0; i--) { + if (abs((s64)(((s64)eng) - ((s64)CL_EXP_10[i]))) < min_delta) { + min_delta = abs((s64)(((s64)eng) - ((s64)CL_EXP_10[i]))); + noise = i; + } + } + + return (-noise); +} + +static void cl_read_reg_noise(struct cl_hw *cl_hw, s8 res[4]) +{ + u32 reg_val = riu_agcinbdpow_20_pnoisestat_get(cl_hw); + u8 i = 0; + + for (i = 0; i < 4; i++) { + u8 curr_val = (reg_val >> (i * 8)) & 0xFF; + /* Convert reg value to real value */ + res[i] = curr_val - 0xFF; + } +} + +s8 cl_calc_noise_floor(struct cl_hw *cl_hw, const s8 *reg_noise_floor) +{ + s8 noise_floor[4] = {0}; + u64 noise_floor_eng = 0; + + if (reg_noise_floor) + memcpy(noise_floor, reg_noise_floor, sizeof(noise_floor)); + else + cl_read_reg_noise(cl_hw, noise_floor); + + noise_floor[0] = abs(noise_floor[0]); + noise_floor[1] = abs(noise_floor[1]); + noise_floor[2] = abs(noise_floor[2]); + noise_floor[3] = abs(noise_floor[3]); + + BUILD_BUG_ON(CL_EXP_TBL_SIZE > S8_MAX); + noise_floor_eng = (CL_EXP_10[min_t(s8, noise_floor[0], CL_EXP_TBL_SIZE - 1)] + + CL_EXP_10[min_t(s8, noise_floor[1], CL_EXP_TBL_SIZE - 1)] + + CL_EXP_10[min_t(s8, noise_floor[2], CL_EXP_TBL_SIZE - 1)] + + CL_EXP_10[min_t(s8, noise_floor[3], CL_EXP_TBL_SIZE - 1)]); + + noise_floor_eng = div64_u64(noise_floor_eng, 4); + + return cl_eng_to_noise_floor(noise_floor_eng); +} + +u8 cl_convert_signed_to_reg_value(s8 val) +{ + bool sign = (val < 0 ? true : false); + u8 res = abs(val); + + if (sign) + res |= (1 << 7); + + return res; +} + +static const int nl_width_to_phy_bw[] = { + [NL80211_CHAN_WIDTH_20_NOHT] = CHNL_BW_20, + [NL80211_CHAN_WIDTH_20] = CHNL_BW_20, + [NL80211_CHAN_WIDTH_40] = CHNL_BW_40, + [NL80211_CHAN_WIDTH_80] = CHNL_BW_80, + [NL80211_CHAN_WIDTH_80P80] = CHNL_BW_20, + [NL80211_CHAN_WIDTH_160] = CHNL_BW_160, + [NL80211_CHAN_WIDTH_5] = CHNL_BW_20, + [NL80211_CHAN_WIDTH_10] = CHNL_BW_20, +}; + +u8 width_to_bw(enum nl80211_chan_width width) +{ + if (width <= NL80211_CHAN_WIDTH_10) + return nl_width_to_phy_bw[width]; + + return NL80211_CHAN_WIDTH_20; +} + +static const int phy_bw_to_nl_width[] = { + [CHNL_BW_20] = NL80211_CHAN_WIDTH_20, + [CHNL_BW_40] = NL80211_CHAN_WIDTH_40, + [CHNL_BW_80] = NL80211_CHAN_WIDTH_80, + [CHNL_BW_160] = NL80211_CHAN_WIDTH_160, +}; + +enum nl80211_chan_width bw_to_width(u8 bw) +{ + if (bw < CHNL_BW_MAX) + return phy_bw_to_nl_width[bw]; + + return CHNL_BW_20; +} + +bool cl_is_valid_auth_mode(bool is_wpa, u8 auth_mode) +{ + return is_wpa ? (auth_mode <= CL_AKM_SUITE_PSK) : + (auth_mode <= CL_AKM_SUITE_FT_FILS_SHA384); +} + +bool cl_is_open_auth_mode(u8 auth_mode) +{ + return auth_mode == CL_AKM_SUITE_OPEN; +} + +u64 cl_get_tsf_u64(struct cl_hw *cl_hw) +{ + u32 tsf_low = mac_hw_tsf_lo_get(cl_hw); + u32 tsf_high = mac_hw_tsf_hi_get(cl_hw); + u64 tsf; + + if (tsf_low > CL_TSF_LOW_MIGHT_OVERFLOW_TH) { + u32 tmp_tsf_low = mac_hw_tsf_lo_get(cl_hw); + + /* Overflow of tsf_low occurred */ + if (tmp_tsf_low < 0xFFFFF000) + tsf_high++; + } + + tsf = ((u64)tsf_high << 32) | (u64)tsf_low; + + return tsf; +} + +u8 cl_center_freq_offset(u8 bw) +{ + if (bw == CHNL_BW_160) + return 70; + + if (bw == CHNL_BW_80) + return 30; + + if (bw == CHNL_BW_40) + return 10; + + return 0; +} + +u8 max_bw_idx(u8 wrs_mode, bool is_24g) +{ + if (wrs_mode < WRS_MODE_HT) + return CHNL_BW_20 + 1; + + if (wrs_mode == WRS_MODE_HT || is_24g) + return CHNL_BW_40 + 1; + + return CHNL_BW_MAX; +} + +bool cl_hw_mode_is_b_or_bg(struct cl_hw *cl_hw) +{ + return (cl_hw->conf->ha_hw_mode == HW_MODE_B || + cl_hw->conf->ha_hw_mode == HW_MODE_BG); +} + +void cl_snprintf(char **buf, int *offset, size_t *size, const char *fmt, ...) +{ + void *new_buf = NULL; + va_list args; + u16 str_len = strlen(fmt); + u16 new_size; + + if (!*buf) { + *size = PAGE_SIZE; + *buf = kzalloc(*size, GFP_KERNEL); + if (!*buf) { + pr_err("Buffer allocation failed (%u)\n", (u32)*size); + return; + } + } + + /* Additional space is required */ + if (str_len > *size - *offset) { + new_size = *size * 2; + new_buf = kvzalloc(new_size, GFP_KERNEL); + if (new_buf) { + *size = new_size; + memcpy(new_buf, *buf, strlen(*buf)); + kvfree(*buf); + *buf = new_buf; + } else { + pr_err("Buffer allocation failed (%u)\n", (u32)*size); + return; + } + } + + va_start(args, fmt); + *offset += vsnprintf(*buf + *offset, *size, fmt, args); + va_end(args); +} + +bool cl_is_eapol(struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + __le16 fc = hdr->frame_control; + unsigned int hdrlen = 0; + unsigned short ethertype = 0; + u8 *temp = NULL; + + /* Find the wireless header size */ + hdrlen = ieee80211_has_a4(fc) ? 30 : 24; + + if (ieee80211_is_data_qos(fc)) { + hdrlen += IEEE80211_QOS_CTL_LEN; + + if (ieee80211_has_order(fc)) + hdrlen += IEEE80211_HT_CTL_LEN; + } + + /* Skip wireless header */ + temp = (u8 *)(skb->data + hdrlen); + + /* Skip LLC and SNAP header */ + if (PKT_HAS_LLC_HDR(temp)) + ethertype = get_ether_type(LENGTH_LLC + LENGTH_SSNAP - 2, temp); + + return (ethertype == ETH_P_PAE) ? true : false; +} From patchwork Thu Jun 17 16:01:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74638C48BE5 for ; Thu, 17 Jun 2021 16:09:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D1A161407 for ; Thu, 17 Jun 2021 16:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233747AbhFQQLh (ORCPT ); Thu, 17 Jun 2021 12:11:37 -0400 Received: from mail-eopbgr10042.outbound.protection.outlook.com ([40.107.1.42]:19479 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233773AbhFQQKQ (ORCPT ); Thu, 17 Jun 2021 12:10:16 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RDEwCnJ2askiq7rKC6mTrnhxXsQxKCXT+wsuD8fyfULx0IwaAr4XWdYLWvSdMb3tkUKj4sjFyqnasYLSuS6c2XOp/8NqNKAd164inVl6mO+LoFZ95A+nIrJOhv1bjbWbFxogRIZj49dLFYUKsL9faWrKIBw43Yd/xk/XsYq9/IzJt3KvS2Awj3/x5BNBV/pgwTTN4sdkCRKrQbwofsc9a5CeXd7fOs77cIA8Ylj4sZ/xW0LURA4Qv6qZHULtuAZdYNI3KiFiUBDFndCxpwVZ1+zuT+a+7xQcKCwYEJsdIW6d9wnQqDptAydL4R/jLJAjwnUJVLu5MOoa19qbkjDnVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YLhnEA4L5RlebqXIgs2oB4ZkahhKHLgyzP0HPMg3FKM=; b=l2R5ddwQ+tD+HMVXoxI3PfY8N3WW2WHDIFtMQm5TWYNhNnHQQz3Htvo4GlPHvOpjjlfAlF4vAU2aUAvIiQCE9hLu88YE7yDPAiiOuqLkmXhE3oYDpzdro0YKAcDwRWcECV1cU1F21L7YvHPevhAWCVCWfOZBvyvafNUfial1t7T/kFIeECHWcCpFgGtfbPJovQbEtGXAxNYjVFY6HJYezXl8BYvZx3wJro8wKCh/EFesTPJdMaz7inw6hu3f443meTNEW8L78FnnxKF2hrV0UZRcQQ570tKCNgUK+vaqrEfeAXRSv2Oxys/YTYBin/NsAgNdmlFJBsg5tvVrD+3TeA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YLhnEA4L5RlebqXIgs2oB4ZkahhKHLgyzP0HPMg3FKM=; b=O4MwLOIrQ2D2AOiuuUfEpHasRY2JcrE8w66c0VD3wecQfwwA/B2K+CQGwd+rHNomkWW1aY6imJLGwxhLi2knaqA5HGM9Zj6dmLqJZOYanEe4OaPmlQqQA8yunKvYenkJYK4atBfgqvSs2rOLPnvAJm8qlVKEiW5lfR1GcLkdDAE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0515.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:45::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:07:57 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:07:57 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 230/256] cl8k: add utils/utils.h Date: Thu, 17 Jun 2021 16:01:57 +0000 Message-Id: <20210617160223.160998-231-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:50 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 25058e7f-a25f-45c4-712b-08d931a9eae3 X-MS-TrafficTypeDiagnostic: AM0P192MB0515: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:494; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AXyv/Pb3G7QKXuilVTpjoxgMzeLJHCuhG8BbrtajN42k5iKJcvHMx4xYjaz9ELhKDCL663W7T1TCNwMvREc7KSbg7OCYZ6oATVL854TnmdJlVPXSF8Fe4pneiRBt166sRlYF58PvXWb4gv7j61GKe8stwDQBqVmV+T8fxC2Pe6MQ9p+S3qYg0O/n01tusn4JxHFBm4U3vosgfDWW03ObzI0zdb2fHmDcMY3fLGCfVH8WIPyTTpvBTMBCpYWsV5l9FrE9quJtxXwj4ZpHLS7htegVRc3ZINaBTn4JwoJalngOWQDzZNBlY/K7GCzHuptBaninlZ+bS2tv/GNdO5Tl6nFws1AkJ9xKBAtayXIWbuzSZeJ12XcdXit1epwET0HKRhgnRTp2ODmbctw/kZvJ1KuCZNVgZBNqQ9q1wjwd7Wl/MWJ8+udjUsHcCkjVt7c/WGJP9PP0o2fjNZLwsT9IoYq84Q96yotXufmI1Dux8QtnzOIXznc9QSbE9L6n74vzJLNbaNq118QqPWrfpl4F+GwaR5uoy+QBwJRz0MwqvUaQe3rFUZzH95r7cwdEnR6MX8BCRlFxq+/DsM+kHH9aYCi6/HAvCtJAHLdTqFrzg1w35Tu6DSasZMlAHNswsvE2Eav3owpiYyAQ+k5Gg6Z1t/q/Zo6CqdsqhMTbtmHzCNNzrihdCLF+23rnZToZtmiy7mTxDs9IL6SNdJUKsOUhKA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(396003)(376002)(39850400004)(136003)(366004)(346002)(4326008)(16526019)(83380400001)(1076003)(8676002)(9686003)(55236004)(36756003)(478600001)(8936002)(956004)(186003)(6486002)(38350700002)(6512007)(6916009)(52116002)(86362001)(5660300002)(2906002)(38100700002)(66946007)(2616005)(316002)(6506007)(26005)(54906003)(66476007)(107886003)(66556008)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bxjZGJl1sdNH0ZecczDb9NmQPBwNM3zO02RBTgTvLcVy3PyAWvANQPgt4Rrt+Qsy5Y905hgksBZl16ezhgeWXeOHNXThE+CZkpnnlXZEGMziaKpcLUwsuo27Ln0JAstGMNZm0SHgqMZ77GAHmmjEW2+Oklf+jRDwAeT2G42m07TwJgmUaYJ3vW4dwFgpExUmmWPNjKR6p9BVX3jHBEJ6yMyox99MFZij07oK+P2Pq4UXFFlGvdUJa+QZuQD8Ie4aBF/bJ/1wSAM52up96LQJ61OmfVT8vcZXleld1937s1MbliWgtOMJ11BusVJ+nPV9Zo2J95PlfRoMlirNCB9TIElCbok34dbJyxkhbnB6Y5ABoF0NP3Uipi/cwBvWuuFcNo+WTLZbT84bgzDfqGxV92E3Zq2RbNzauwJ0UU2j4dWKfjwN8BQ086E8/IjRMC6LLBGrfT6r8nAjDqfkxJbff7N9bw6FlLdSixzc1xkRaqf/6lCwacXLtB3CI4PolJgcDJgIR5ZHj9dw5Cy8zfocUllvFop3R8QQ7/bWa0FlOInUawK1iiYk405qd2LyIx9hHC3Lt2APyIrLuI9QTvIfG7zW1QMf9KRh5Kf89fK1/6gEI0/Uvy88OblSbW9jhmzdpnPrMQXmv49U8W8tMdZs1O7RceKNlv3V0IyRM/S3JE1IAiVYzEdUtrpC01XEr3GpcpaX07XAozfCbiBICCyolovQb5FJDN6mlLQl1tl9cLQuqzzaRkbX67NTXVHoKosaKv50CoDi7eK9wZf/O1TheIOx0ovNePl+MmcHKSlHDiwTvP0s56Um6SYqs90OT5w461LCWOrjUMDxaWFIUUuMK+vk/YqrnmuPquHn3zqUPHPRC83GBdsQpRBG2Ig0j/S/s3VVLiOAFRtzgWy73Sq5cYedYAO9TxBL72ny7EaQPsPQWSpOXHSBWyhWP8xYi6uWa3swSkoBQBEbtmpG7KlH9i3/aqNozD6ex+X3JilIMzhdS2SY1rCRr/3gtPS+jYtSC2EBccBbjhqfDx3OvnwqoU+VBBAx55MXNNaFvQy86wIYLUUIy2L8Kdm7HfwyAJJWLqwQaJhAGKrGPZF11e47RaRaj+ic2uSFXjRRBeIyVyaT7iHTPcb1dDxxXJp84HyTtrAOxfnceSy0jOUKtahXPG5T7NHll2gFljDrxbICdAWFcQ6eWtiAbvVfBtBnrOG0xGTU3u1yoiQwmyGZWmgMPiC5d5HrM+vNpsKpC0vg86JY67GdTbsQuDpK6PGOOOQcAusz2SFWMFla0ZruoMSMlo5zHaNakVdeyIPnnwS/HsHMQ0t/4wARoyq/nbPx5o+n X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 25058e7f-a25f-45c4-712b-08d931a9eae3 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:51.0898 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CW8ZOaSiGSvnG5ts4c9+lBcMR2adl/N8Md+BcU1c2hhVUls/RvTda5OB7i7eHXS0q95rRC4AruhDnSq9bi+sFg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0515 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/utils/utils.h | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/utils/utils.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/utils/utils.h b/drivers/net/wireless/celeno/cl8k/utils/utils.h new file mode 100644 index 000000000000..d08cb23513ef --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/utils/utils.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_UTILS_H +#define CL_UTILS_H + +#include "hw.h" +#include "vendor_cmd.h" +#include "vif.h" +#include "ipc_shared.h" +#include "ieee80211_i.h" + +static const u8 tid_to_ac[] = { + AC_BE, AC_BK, AC_BK, AC_BE, AC_VI, AC_VI, AC_VO, AC_VO +}; + +static inline struct cl_vif *NETDEV_TO_CL_VIF(struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = netdev_priv(dev); + + return (struct cl_vif *)(sdata->vif.drv_priv); +} + +static inline struct cl_hw *NETDEV_TO_CL_HW(struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = netdev_priv(dev); + + return sdata->local->hw.priv; +} + +static inline struct cl_hw *WIPHY_TO_CL_HW(struct wiphy *wiphy) +{ + struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); + + return (struct cl_hw *)hw->priv; +} + +void cl_hex_dump(char *caption, u8 *buffer, u32 length, u32 offset, bool is_byte); + +bool cl_is_valid_auth_mode(bool wpa_ie, u8 auth_mode); +bool cl_is_open_auth_mode(u8 auth_mode); +u8 convert_gi_format_wrs_to_fw(u8 wrs_mode, u8 gi); +u8 convert_gi_format_fw_to_wrs(u8 format_mode, u8 gi); +u8 cl_map_gi_to_ltf(u8 mode, u8 gi); + +s8 cl_calc_noise_floor(struct cl_hw *cl_hw, const s8 *reg_noise_floor); + +u8 cl_convert_signed_to_reg_value(s8 val); + +u8 width_to_bw(enum nl80211_chan_width width); +enum nl80211_chan_width bw_to_width(u8 bw); +u64 cl_get_tsf_u64(struct cl_hw *cl_hw); + +u8 cl_center_freq_offset(u8 bw); + +u8 max_bw_idx(u8 wrs_mode, bool is_24g); + +bool cl_hw_mode_is_b_or_bg(struct cl_hw *cl_hw); + +void cl_snprintf(char **buf, int *offset, size_t *size, const char *fmt, ...); + +bool cl_is_eapol(struct sk_buff *skb); + +static inline bool cl_are_host_bytes_le(void) +{ +#ifdef __LITTLE_ENDIAN + return true; +#else + return false; +#endif /* __LITTLE_ENDIAN */ +} + +/* Most likely, bit endianess is the same as the byte endianess, but turn on + * paranoid mode and check separately */ +static inline bool cl_are_host_bits_le(void) +{ +#ifdef __LITTLE_ENDIAN_BITFIELD + return true; +#else + return false; +#endif /* __LITTLE_ENDIAN_BITFIELD */ +} + +/* We could inverse *_le checks here, but the motivation is the, as per bits + * endianess - anyway, it is better to check */ +static inline bool cl_are_host_bytes_be(void) +{ +#ifdef __BIG_ENDIAN + return true; +#else + return false; +#endif /* __BIG_ENDIAN */ +} + +static inline bool cl_are_host_bits_be(void) +{ +#ifdef __BIG_ENDIAN_BITFIELD + return true; +#else + return false; +#endif /* __BIG_ENDIAN_BITFIELD */ +} + +#endif /* CL_UTILS_H */ From patchwork Thu Jun 17 16:02:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB4EFC2B9F4 for ; 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 235/256] cl8k: add vif.c Date: Thu, 17 Jun 2021 16:02:02 +0000 Message-Id: <20210617160223.160998-236-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:55 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 730b7526-ba72-447e-283b-08d931a9ee1b X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0N3JSRxdBcXmTilku1jO4d+50ik1oKDyfxGDmobYhPIEN9fuuVWcmd/9Xi5AuElz2XwblJBvv2GuJxmMWR6dsc6uSfs3cf5skluxtTvLTkWST/5z7ZmzfjcqDB7ZtTHbnn732CQZJe83G2ae+YL27poNIFCd/61b0o+tvwXhdpncqhrz2Px1UNfT/6dvfyvgesAvLftQ3xwTca87SNcDBtNaO3lwNQxf1sHPZJTHiFhLGOC4BL/jG45/nDAE7aWdgY1jMA3dMJ0wJfmtFnAVrYzlXeIXhiTmc3WKxWQ40LrZm4913AOrc52w6IoO2a29ErOBXy4fIj86fpYOadIjzxG36ggjPzMDpGuf4sir/EMuGmhEx3wEiNX6Bc8fZnt8eyMz/xB5fV3PXB2kptyPjl+OM3yYrPbYFOdzSmiyJkPO0sjbG8Htk2+cjy3xxwCMm1grqN5Xzn6rO1uS242kU5mNXzjbGQH0u0BDTeo6YxdGwLt9fvmIjM0hLqkjJ55MRQWJ2Okxfn1kWP2bbV2wOqag8f8/fl0aF6f8zxQFKc+g9EixCh0BuxD+5XjHdVyGiHzaE1buF9SOMkaFHSMzKx8kc4O3GopkZhb+qtGws8Iyi54o3ZL4fhVYFqdjEDobGo2CcDBGWSO2ymvfCuOQgMgCIjgM+wrSRdBDt72MkJr+6ppHkyhWhKhSSKgrswD6R+jcx4nN3WLeYRJvkqBkiw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(6666004)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: W4tfwZxnaB+Pjn812DJltwkopNpDXBZJpSUzSQPC7H/QfeUAa2jh2LPXYox3nHQKkOLXckxZuugq91vaf0nFAG6N0HMrmfiAn98tuBok8K/TrS/GMLFN3eFpt5MHcFMhBFRQNLluiNw1u9T2sODUraWGpWCiAbR6LbrGnJpXfFlXd5kozBtbOasyXlLAFeEbMAGmgOJpBu/R3WnS9mWAfEajciU2bH19VFsmwFymI7gdo184YBx/uExIBUP4tJIOAjNZhdZFfdp5Jy2nb1VNZFveBoGEnfCy/VTnAbcu0M+TVDDf0R6DTIYW4xwqeHkBfrwIBsWSS5E+MPGOIXJ9EKKNxUHXQ1dkyEsEBtnnB+4wso4M/jMXWUnsFpwgs15X4wVRchi/hSwxC6oYSRWL0h249clFQtQ1opCiyL1dTB+bEnR7udpWp8b9ZRHp5Rg9Ruon4hEHB/+rq8jwIZP9SMx+az0BhJi6ftAG9DB9TAHKtKwnxdJwJfqFva2ur/tk6oLFbDv6dRyv32yhiuCo2WWr454/b00dWL+TA2KaFZdEp2CcRhk0S1PJ//57NpKK4/gopSfEbcH5eE3voiqMLqzLlRIF4K7khU1ye0P+aOl1k6UD5Zo9gmxNBeuz8IVtJZraQDNLu/83dja6djwSf+C5MzVrLwYI9kVWHXayiC7NZ1QTDcHHqp9hJANFqvDIZ1Yeyg2rRaHqaNpMIg7MLIl181jKiPu8v60Q+FrnMjeQ+66XG01TpTxtUG4jLNwm4PrNd0+dxZ+Ez0mSchLB4lLcbXVJ63woTVgbJeAaAHMiUwxVDMzlVt/YVdDRsUztsUoFtTYiIWgnFMt5JxO8DyQvLBRcGrNHeyEW+xUxJ0F6G5kfVXtVucUebniPFWj9msKlwqIqJB/uFaI6bZ3w5WruLANg5o0gzFIEZTBfhUwhGKWvgo7uRtrW5QxrwEya48Vwzx4CBCvv7yVcqCP/K/W4u9V/QgW13POyooGN4enrThZhZaP1sphQtGaE2n2jj8pPnk4eCso313HFE+C6yY4AWfxBP7ZSUyySGt+M2IVzLFce2k9dutnEWesl3umSqOGTtnfm/hXh9EE1q1utfkYXSrQXUvg+5VB2Zy/Vyh7syJKV/AmVe3a/qaaiFbIlKcjusWOTGqiKssAsG9VYTl95PXSbGLLsY7Y99uXTDS8r5BXsI046pTXh1Ptk0tewqjcABnmwNj/47vp2d884PNvG+foxGEWf+0aqQal46jxMw5SRlRcQm5IjB33vm/UQlIGAiuT16ix2YcILZ1scg5huTU/pifwHJseUaXPsmLbnkz3+hClI8RNT76LwRBwc X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 730b7526-ba72-447e-283b-08d931a9ee1b X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:56.5050 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ApHLDOmt2yAqelHdaRh2MWBYkENJ019QMS63NxCqKX4wCyIMovBAJUpcVahRab8gAMZFoaLcox4JR6l4RbNd6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/vif.c | 143 +++++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/vif.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/vif.c b/drivers/net/wireless/celeno/cl8k/vif.c new file mode 100644 index 000000000000..80234de0bb7c --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/vif.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "vif.h" +#include "hw.h" +#include "mac_addr.h" +#include "utils/utils.h" +#include + +void cl_vif_init(struct cl_hw *cl_hw) +{ + INIT_LIST_HEAD(&cl_hw->vif_db.head); +} + +void cl_vif_add(struct cl_hw *cl_hw, struct cl_vif *cl_vif) +{ + list_add_tail(&cl_vif->list, &cl_hw->vif_db.head); + + if (cl_vif->vif->type != NL80211_IFTYPE_STATION) + cl_hw->vif_db.num_iface_bcn++; + + /* Multicast vif set */ + cl_hw->mc_vif = cl_vif; +} + +void cl_vif_remove(struct cl_hw *cl_hw, struct cl_vif *cl_vif) +{ + /* Multicast vif unset */ + if (cl_hw->mc_vif == cl_vif) + cl_hw->mc_vif = cl_vif_get_next(cl_hw, cl_hw->mc_vif); + + list_del(&cl_vif->list); + + if (cl_vif->vif->type != NL80211_IFTYPE_STATION) + cl_hw->vif_db.num_iface_bcn--; +} + +struct cl_vif *cl_vif_get_next(struct cl_hw *cl_hw, struct cl_vif *cl_vif) +{ + if (list_is_last(&cl_vif->list, &cl_hw->vif_db.head)) + return list_first_entry_or_null(&cl_hw->vif_db.head, + struct cl_vif, list); + else + return list_next_entry(cl_vif, list); +} + +struct cl_vif *cl_vif_get_by_dev(struct cl_hw *cl_hw, struct net_device *dev) +{ + struct cl_vif *cl_vif = NULL; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) + if (cl_vif->dev == dev) + return cl_vif; + + return NULL; +} + +struct cl_vif *cl_vif_get_by_mac(struct cl_hw *cl_hw, u8 *mac_addr) +{ + struct cl_vif *cl_vif; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) + if (cl_mac_addr_compare(cl_vif->vif->addr, mac_addr)) + return cl_vif; + + return NULL; +} + +struct cl_vif *cl_vif_get_first(struct cl_hw *cl_hw) +{ + return list_first_entry_or_null(&cl_hw->vif_db.head, struct cl_vif, list); +} + +struct cl_vif *cl_vif_get_first_ap(struct cl_hw *cl_hw) +{ + struct cl_vif *cl_vif; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) + if (cl_vif->vif->type == NL80211_IFTYPE_AP || + cl_vif->vif->type == NL80211_IFTYPE_MESH_POINT) + return cl_vif; + + return NULL; +} + +struct net_device *cl_vif_get_first_net_device(struct cl_hw *cl_hw) +{ + struct cl_vif *cl_vif = list_first_entry_or_null(&cl_hw->vif_db.head, struct cl_vif, list); + + return cl_vif ? cl_vif->dev : NULL; +} + +struct net_device *cl_vif_get_dev_by_index(struct cl_hw *cl_hw, u8 index) +{ + struct cl_vif *cl_vif = NULL; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) + if (cl_vif->vif_index == index) + return cl_vif->dev; + + return NULL; +} + +bool cl_vif_find_mac(struct cl_hw *cl_hw, u8 *mac_addr) +{ + struct cl_vif *cl_vif; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) + if (cl_mac_addr_compare(cl_vif->vif->addr, mac_addr)) + return true; + + return false; +} + +void cl_vif_ap_tx_enable(struct cl_hw *cl_hw, bool enable) +{ + struct cl_vif *cl_vif; + struct ieee80211_vif *vif; + + list_for_each_entry(cl_vif, &cl_hw->vif_db.head, list) { + vif = cl_vif->vif; + + if (vif->type != NL80211_IFTYPE_AP) + continue; + + cl_vif->tx_en = enable; + cl_dbg_verbose(cl_hw, "Set tx_en=%u for vif_index=%u\n", + enable, cl_vif->vif_index); + } +} + +void cl_vif_bring_all_interfaces_down(struct cl_hw *cl_hw) +{ + struct cl_vif *cl_vif = NULL, *cl_vif_tmp = NULL; + + /* Remove all interfaces gracefully to avoid of memleaks and kernel panics */ + list_for_each_entry_safe(cl_vif, cl_vif_tmp, &cl_hw->vif_db.head, list) { + rtnl_lock(); + dev_close(cl_vif->dev); + rtnl_unlock(); + } +} + From patchwork Thu Jun 17 16:02:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 105D1C2B9F4 for ; Thu, 17 Jun 2021 16:11:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED8B3610A5 for ; Thu, 17 Jun 2021 16:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231667AbhFQQNl (ORCPT ); Thu, 17 Jun 2021 12:13:41 -0400 Received: from mail-eopbgr130083.outbound.protection.outlook.com ([40.107.13.83]:60643 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233916AbhFQQMU (ORCPT ); Thu, 17 Jun 2021 12:12:20 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XvzfpPeFpOhl8GRmhCEQaGTZ0TME6f70CaDlXwaWTZ8Wx1jcLlbsg/NoKlK9+evnxskbT99aS9HKyOk1XzKVgL0O/VEyId4p+JYopA1keK1d3MoGEvp/gfpqxTKlaSFIJViPlVBLm0EvtTupEywWp9ghP/4hGWc9SK3Q2jLLbX2kSUZRJX42JUs8VaX3Hv842bXPgnDbjhNbwNZHoNSOxZbYHb9tOcON6gHJxZX1KqVa2EucB2g3tcJ3kZD5LEtFuOl9hTc/Sy+k6iryPzdXje+EKcxtvdzstDbkC7gBVTym+hcnRJBUUqReJj2kpFu2MxVLjGpJDPZ4D2RwzbQ12g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=au4N+5Vj79W/vonL8EpSOAjxfdX39Nqx84GVaL5dLWI=; b=TkeTHvQPiskWN9JqPWaISJk9RawfuBCBrlnxxi+8piAWZTF0v+1oOpRiVCPVsdvq+RXJcjYRe/9SAJhgWzUS2oPoSNonHy4z4obXeW9BP1tYTv8dFoGo0CYSgtfONQ0ozaCRy8Wn30xQdrX6l5UHJQWOtVlPd4nr3UKjTgzP1A/QEVlScUlTRFHSFir1nZ3+N1AJE0Ye56aCETD3As9GfucZmuNv5bCnD+hqXDRLe4M+ntkyLcDMOP1y9C/N4ryHcwdcsQegoOcupaiDTsvCiieKFnZI8RVQKoCTBEXuSPo9DNFbLRygiQJMDPc15qd9c5licAC2WDgE7kR/aho7Og== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=au4N+5Vj79W/vonL8EpSOAjxfdX39Nqx84GVaL5dLWI=; b=lbZl9c6s7SqYDa4FrevEkGkcZk/VKsJtl4foAR4xl8QM6Eid9nt+8+yyt2/4ON5akEEzTAiJA/KLe7HPfnWM3bl3M/an8XA/ivsRWVtYX1klbMIkUaAV+/hu83JLcyuA0A11uLpfy006pQg1cLqFbXIDloWVp4FMgZAO2SykmqE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0452.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:4e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.23; Thu, 17 Jun 2021 16:08:00 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:00 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 236/256] cl8k: add vif.h Date: Thu, 17 Jun 2021 16:02:03 +0000 Message-Id: <20210617160223.160998-237-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:56 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ddc6968a-0193-4463-4826-08d931a9eebb X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /HnqETqNuz7E0x+Yc6ZGEKHokIl9WcGfRp8Sec5aLlUSmVaVkjryTBrp5EU6NCoFFXpxs9CX7dzBmIlqcWtE6JWG8JLvHPfvKa/J209fcWrqG8ghbBmx/RXJdHA5OeAZ1Nzzc7plJHfwrbcqe7t5y2avYqiHxcbMVn6OpBummZItAMlrRtmsvt3+1+Vn5adcUBXlz4PQAh65b8cC6/H+lsDhvEt+J1q8TTAhgEZrRcd6GUz96uScKIhXheDXv2kvM3wuBt/U0wGSfvODN8RQ2IUtlq7HeboMdSbAtjXnYx5a2XoK2ut3zzGJS7fGfs0byy1eYLjp8c60kgUZEMJRFyC4VXJ7rVuM7MV+lghBwizM0NuEdhb3DrvHZREXuxaA41qw2SCFXJ7INr15ox0WwY+uR9rJqk9G3FtrK7Ih69SMTYXV5ZfNT+rbZMW8eLMK9UluapG7Wlr1ZStTFeVOnZDhmN2m+ZpQjo9mfoFfe95Dr7yBsMS/ECzlB0qdh4qBlX9rbdK8k2MLl5kifo5672BXg4MPl5F2RCqlMGqAty9wnLS+SKcaAvS2cNYpCko6hOoru6bCj4TexDVyOGPKio7RKWSZaCq+Vgc6ayUfaWg5HT5iWAYElHmhyQ/U1fwK8X90JCsW3V1uQfD5tRsdX732HpEACvdIbF4eRhjyQ2bMRGF1t+ptCmwUPb1brzG4Govw/SLdiGihx2Z5bwAcvg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(6666004)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Io/szmltfvoW2BNH+xBt06TK5TbS6Hgsc7bdZ7r2wkHZ92cFdXfTPxRm1O6J9HN5WBfZ8TeAFoFeLtgA8qUvSRTqu+NK3WaFaPGvjwQym6Jmk/71ZrU//Je2q0ZogMNkS9XaJyarkNecgiU9nQxa6sSSlEVIuDOSomr+Yx7I8E/SYfGvMy5Qx9/PIv8eXN7CoLb4GBrsiWi+dmgfV8HlfBPXiqHtT5UH5uE3yGndljEEE4izjhr0v2CjldLQQX4kdprrPtMhE6sYtYxFFVcbX6SLKkOG+ykaFaZXz2msA+7zTSxyuPF+qUrvYzQjKRuSjMxsVIPjrnLsywZ+xk5FYgI3432idZn3eeCvrU8D2dwmHlsYVcVU/2j47QpDD3AR+53KgDmZvRauJBRsMmKsATX3J6hL9lwFAnVMI7Z1D91yiB2Ir55F4soG+BDk7SR7X5NaV3CJZu4L8eQtp9TliK0LN0KIQaha+lWgPGp2FkKYHs6qSFQXpjEUNa/L36CN+CdlKNWNRQ8R0tSR5u5udVOrThb+JDAKVEcDZwJNjFY1X3A7sgd9JAlhqA4owA59dDuFExFMzYsGgH7Z9DpP23DIRAB4dY/n0Pmbzp9bf1PadSjxKCREAtK7N3s/4wWNb/MSdUikRY/PkXxmpMWM0TtC0NqXjio9/UTs1ioAM0JdQl67Y1QG0U3yHAhs40yBJXqKkaPdAr3XIOYoIqa5vzRYRVVeUmfD5uQy9Vl+8kRdT51Kn04z1UT55gKJCht5Kdcy0lE/OFhIvDuXQ3SD8QtPInWO+fUQL6pjtnw1GA4RaU9aBQgDrNxP1cR18eAItzwfQRuLWhynGaKK1/JF51nCIolkfMCL95bO+H6Hv+pf3L/mT9x1LlLbMDxSx0UIMaO9h8OcBdrv+PrdWpjilZB6nkJAicWUlGN2UuQiGfqGOQ1/GJKDnWlLa5k31ieHwc6PSdJz8hHlDAcsFzwgqyuppaAyuo/agxhc+dAgr1HrbXZkudXW2tpAqvzXfXAcIAJkKTKUb9RN6zeVYYKQwQBbxT3U9zUKpwRly4Vc2LAxu8nGA7VyVUYQGNMLbZsQAsXqWmDoxaVitiiWBHjefyEnwCXuZSWx2VY9NX32if2MuztS72feWLePE5+D91ArlBaqe2v4ge3v3cR30euEbFcslQDJUxbA1SKgp5cOWmzhMFvk348gXAEJG2zxNf3AuS1Ghust/Y3wwFcpEy7J4FJBQeOdad7W4sjBPvzbP4r/suV3H3hQpJo0Giobe/Aifl0cqpv3Fhm96z5xl1PxCRWm1iA/Lpn14ope0vaGBkd5pFufq7c0vwHSrgQ/st8o X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: ddc6968a-0193-4463-4826-08d931a9eebb X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:57.5883 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pLIe9d3+9gN6p57wfggeNknAQmbmNHTQBnchg40ghhEcI1kCqh8XvdV0tw81XnCxHuhzppovBSVbFt93KrHF4w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/vif.h | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/vif.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/vif.h b/drivers/net/wireless/celeno/cl8k/vif.h new file mode 100644 index 000000000000..2cfd027ee88c --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/vif.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_VIF_H +#define CL_VIF_H + +#include "wrs/wrs_db.h" +#include + +/* + * Structure used to save information relative to the managed interfaces. + * Will be used as the 'drv_priv' field of the "struct ieee80211_vif" structure. + * This is also linked within the cl_hw vifs list. + */ +struct cl_vif { + struct list_head list; + struct cl_hw *cl_hw; + struct ieee80211_vif *vif; + struct net_device *dev; + struct net_device_ops dev_ops; + struct ieee80211_key_conf *key_conf; + const struct net_device_ops *orig_dev_ops; + u16 sequence_number; + u8 num_sta; /* Number of station connected per SSID */ + u8 vif_index; + bool tx_en; + struct mcast_table *mcast_table; +}; + +void cl_vif_init(struct cl_hw *cl_hw); +void cl_vif_add(struct cl_hw *cl_hw, struct cl_vif *cl_vif); +void cl_vif_remove(struct cl_hw *cl_hw, struct cl_vif *cl_vif); +struct cl_vif *cl_vif_get_next(struct cl_hw *cl_hw, struct cl_vif *cl_vif); +struct cl_vif *cl_vif_get_by_dev(struct cl_hw *cl_hw, struct net_device *dev); +struct cl_vif *cl_vif_get_by_mac(struct cl_hw *cl_hw, u8 *mac_addr); +struct cl_vif *cl_vif_get_first(struct cl_hw *cl_hw); +struct cl_vif *cl_vif_get_first_ap(struct cl_hw *cl_hw); +struct net_device *cl_vif_get_first_net_device(struct cl_hw *cl_hw); +struct net_device *cl_vif_get_dev_by_index(struct cl_hw *cl_hw, u8 index); +bool cl_vif_find_mac(struct cl_hw *cl_hw, u8 *mac_addr); +void cl_vif_ap_tx_enable(struct cl_hw *cl_hw, bool enable); +void cl_vif_bring_all_interfaces_down(struct cl_hw *cl_hw); + +#endif /* CL_VIF_H */ From patchwork Thu Jun 17 16:02:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20BDBC2B9F4 for ; Thu, 17 Jun 2021 16:11:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0512361059 for ; Thu, 17 Jun 2021 16:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232033AbhFQQNu (ORCPT ); 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Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 237/256] cl8k: add vns.c Date: Thu, 17 Jun 2021 16:02:04 +0000 Message-Id: <20210617160223.160998-238-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:06:57 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 01dac17c-40c9-4345-a29b-08d931a9ef61 X-MS-TrafficTypeDiagnostic: AM0P192MB0452: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:102; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rimp8nQU91oaufSXvmhcIaxSXUq7PvRpf7YRxz2nLSWpHQIcT+bdvObotFl/VKMYLFl3Ho4CAFPJJAAKW81FiLTFOvNgnIGlSNF39FycV5YxudHj0bRKwHr/Q0wk3qv9Lgwb7T6+8rME+OcoQd/xzHRwvAxpoPp4hFMZNFyxs1vqwAfpW1pZM0L6WuOINbEzLq6EXbknSoXOSesXtvFL479SNV/QS2093NaNf3wCt73o4ZbpK+/aUOfMflJDpG8eAaDdd+2TjlIwcUuImKmQHVUfJc7/67TtVvRJwUpxjsyBmz/EYBKkLz6pVPyfLNGHLk5QE1df8wrzIbEw4YkuSrzHdKpyq+Xu9T1cT+BpFUuxdTCABEzQ1yHYOlLX347n8XOy83QepyCw5sbYQ83E8a1wc6fDivnApUqVRhqISOOB7r17oPEfkw4CSbERM5II+BVKlVNiI8HQH/VeJkxDb2+S6dYGLhcXT+lHWX9fgsqwh3B44yjVPjWAJjlv6yIAHRSrS7erTdFMlaiM4geWvfMBBtys3Zw7+//iiiMAS08m338leD+F7xY73i1n3vDiapgbNdBMOXP5Olu5PNCjuwMwFYtOgwqvGyOhAJFQJRI+tYhKM3wyhoc78ERPTP9UJlZD+UCfE6nE21jsju599ryeROv8fcoOn/9P5Fr+n763BAuhibyfakwMsvlCkRK+Q4aa2DslGhcLIUA2WaZOuQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(376002)(366004)(346002)(136003)(396003)(39850400004)(66946007)(30864003)(66556008)(54906003)(9686003)(6512007)(16526019)(36756003)(107886003)(8676002)(66476007)(4326008)(26005)(316002)(6486002)(6666004)(8936002)(86362001)(186003)(1076003)(2906002)(2616005)(38100700002)(38350700002)(6916009)(956004)(55236004)(52116002)(508600001)(6506007)(5660300002)(83380400001)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gYXaldK9kiZ2mkLcPCi/Syajnc77PJm7r/MVeJrzqum2M8eBm3q1hbgnDsjdAm67cdOUxJ7u36QjR5q+4baYCv9NW3LAcawvpLAgL/hacB4rGJzMDS/ABX2rcKEtqAR9ODM+API0lsyJF7KyxWYKqunt9XNCIDcmldTjkIQ33IG7HeWUkBf5Wzri3GayAw8PebrsvVfaM2JEz6Wg4FHgCxTv4CtT93qeEByj8Gs66SgJZIh8kCbrMoxBZv30hU+j5ZS9ZyO8iHLlR77iyioxJYNQhTEeKFsYl8S6Wz/p4oaojdF81tqpzm2MFddMn6KSaZ7oIqzURoYX4B9X5O2p5uQPC97ZHUYQcGg2KQuaR6IKdY8WZmkNOV9CP1KDO7k0APaEKxoHY3qknEBA2EkTdcKBMLQiGvRipQGjEPSWxClv9thKUfi3cxJc12FGbq63c6UZN5BU/0GekLlpc0elgtfA48HTjTWqh+DplTjsN2Xv7V4Q1Ga7iWbXrJsFVd6m9cqTXHpfOT1gyCF8+sZkQEg84efALeHIKGd0Do/WJjTbpAZhTiC1mMB+bXfY9R/K1f9P4kweJuH3UlBcbkABtqeL3DZf85XMzx9qr2FXgENhEUdjgLv2DD07BYa5nogoZMvpNOUiqdR3Bg2TXcvYHm9UqZMx54Eoxlo2I3uwqChsFN1MOq0FEVv5/qirUU9Mv7z1C3OgaDmlah5Ktu4wlY9nWBbccmRqHjXTsIbR9kn2JgbPhEQaPQmxxmzRgV02hJxLxXCMaXSoETjqmhSYwsV0n7zdzGEhcxf1ITduRxITP2Y3dDNIANN9pPDTdgD4KoeO3lsoj+K5JYMhthM9VHfFuQgoLfD2BYMIa7bYA8uXmzfGzmphYplhC6HMdqT7ARHmHsotOLg+bGvnwMPb9vQASE1P4HOB9W6xH4hVHUiyVfN3gbIeqsSO1zi5uPfTxVMssUQgMkUCaygzP35bxVqfRvssZhJ2NR9Gx7SmOoSo+2fS7ZYKldmdpqjnzYQ8tiEeZmwlsYUda751oaCGTkC9zYGtT6b+qrhA2XEAco9AqCyx04681VrV3yS93Lg+rtMXxNaqQsUBMfFPVqz8ibd2E8D6nIuEhfex+ypGiNAD351yKj7iwvPZKXe5oy5gRMZtAqwI/QXIxwbTy7KAbwfPIRbHK4xd0U5ccoE3yPTaa+uwGU14EJtp/RerbyDSsPgnI3LmJUAM11XVVqRThO4YgDQIc6x1W13TufTzthbU6sV4jQkttle/ovoX18lhbFEb+qUN42X+JdDh1R2ZkVBbRLjzLag6WeqIwTXJDv4ISt/Qp08Ywc9tqDxRla2C X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01dac17c-40c9-4345-a29b-08d931a9ef61 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:06:58.6835 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1rYYZHeMGjT8f3fDve9JE0Qu0FhV3z0kokVAcYbHqG6W2AWNzx20NU8Uq2fqyTArcx7LEFtnmXcZE76vyica6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P192MB0452 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/vns.c | 505 +++++++++++++++++++++++++ 1 file changed, 505 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/vns.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/vns.c b/drivers/net/wireless/celeno/cl8k/vns.c new file mode 100644 index 000000000000..75c3c0374793 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/vns.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "vns.h" +#include "rssi.h" +#include "fw/msg_tx.h" +#include "maintenance.h" +#include "mac_addr.h" + +#define CL_VNS_HASH_IDX (ETH_ALEN - 2) +#define CL_VNS_MGMT_AGEOUT 200 + +#define CL_VNS_DBG(...) \ + do { \ + if (unlikely(cl_hw->vns_db.dbg)) \ + pr_debug(__VA_ARGS__); \ + } while (0) + +#define CL_VNS_DBG_PER_PACKET(...) \ + do { \ + if (unlikely(cl_hw->vns_db.dbg_per_packet)) \ + pr_debug(__VA_ARGS__); \ + } while (0) + +static void cl_vns_mgmt_list_add(struct cl_hw *cl_hw, u8 *addr, s8 strongset_rssi) +{ + /* Add entry to mgmt list */ + struct cl_vns_rssi_entry *entry = kzalloc(sizeof(*entry), GFP_ATOMIC); + + if (!entry) + return; + + /* Fill entry parameters */ + INIT_LIST_HEAD(&entry->list_all); + INIT_LIST_HEAD(&entry->list_addr); + cl_mac_addr_copy(entry->addr, addr); + entry->strongset_rssi = strongset_rssi; + entry->timestamp = jiffies; + + /* Add to list */ + cl_hw->vns_db.mgmt_db.num_entries++; + list_add(&entry->list_all, &cl_hw->vns_db.mgmt_db.list_all); + list_add(&entry->list_addr, &cl_hw->vns_db.mgmt_db.list_addr[addr[CL_VNS_HASH_IDX]]); +} + +static void cl_vns_mgmt_list_remove(struct cl_hw *cl_hw, struct cl_vns_rssi_entry *entry) +{ + /* Remove entry from mgmt list */ + cl_hw->vns_db.mgmt_db.num_entries--; + list_del(&entry->list_all); + list_del(&entry->list_addr); + kfree(entry); +} + +static void cl_vns_mgmt_list_flush(struct cl_hw *cl_hw) +{ + /* Flush all mgmt list */ + if (cl_hw->vns_db.mgmt_db.num_entries > 0) { + struct cl_vns_rssi_entry *entry = NULL, *tmp = NULL; + + list_for_each_entry_safe(entry, tmp, &cl_hw->vns_db.mgmt_db.list_all, list_all) + cl_vns_mgmt_list_remove(cl_hw, entry); + } +} + +static struct cl_vns_rssi_entry *cl_vns_mgmt_list_find(struct cl_hw *cl_hw, u8 *addr) +{ + /* Search for entry in mgmt list */ + struct cl_vns_mgmt_db *mgmt_db = &cl_hw->vns_db.mgmt_db; + + if (mgmt_db->num_entries > 0) { + struct cl_vns_rssi_entry *entry = NULL; + + list_for_each_entry(entry, &mgmt_db->list_addr[addr[CL_VNS_HASH_IDX]], list_addr) + if (ether_addr_equal(entry->addr, addr)) + return entry; + } + + return NULL; +} + +static bool cl_vns_mgmt_list_find_and_remove(struct cl_hw *cl_hw, u8 *addr) +{ + /* + * Search for entry in mgmt list + * If entry found remove it and return true + */ + struct cl_vns_rssi_entry *entry = cl_vns_mgmt_list_find(cl_hw, addr); + + if (entry) { + cl_vns_mgmt_list_remove(cl_hw, entry); + return true; + } + + return false; +} + +static void cl_vns_mgmt_list_ageout(struct cl_hw *cl_hw) +{ + /* Remove old entries from mgmt list */ + struct cl_vns_mgmt_db *mgmt_db = &cl_hw->vns_db.mgmt_db; + + if (mgmt_db->num_entries > 0) { + struct cl_vns_rssi_entry *entry = NULL, *tmp = NULL; + unsigned long delta_time; + + list_for_each_entry_safe(entry, tmp, &mgmt_db->list_all, list_all) { + delta_time = jiffies_to_msecs(jiffies - entry->timestamp); + + if (delta_time > CL_VNS_MGMT_AGEOUT) { + CL_VNS_DBG("[VNS] sta %pM removed from list because of ageout\n", + entry->addr); + cl_vns_mgmt_list_remove(cl_hw, entry); + } + } + } +} + +static s8 cl_vns_get_strongest_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + struct cl_vns_sta_db *vns_db = &cl_sta->vns_db; + s32 rssi_samples = vns_db->rssi_samples; + + if (rssi_samples > 0) { + u8 i; + s32 strongest_rssi = S32_MIN; + + for (i = 0; i < cl_hw->num_antennas; i++) + if (vns_db->rssi_sum[i] > strongest_rssi) + strongest_rssi = vns_db->rssi_sum[i]; + + /* Reset rssi for next time that cl_vns_get_strongest_rssi() will be called */ + memset(vns_db->rssi_sum, 0, sizeof(vns_db->rssi_sum)); + vns_db->rssi_samples = 0; + + return (s8)(strongest_rssi / rssi_samples); + } + + return 0; +} + +static void cl_vns_monitor_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + /* Monitor RSSI of associated stations and update state if necessary */ + struct cl_vns_sta_db *vns_db = &cl_sta->vns_db; + s8 strongset_rssi = cl_vns_get_strongest_rssi(cl_hw, cl_sta); + s8 rssi_thr = 0; + bool is_vns = false; + + if (strongset_rssi == 0) + return; + + /* + * Calculate RSSI threshold (take hystersis into + * consideration according to current state) + */ + if (vns_db->is_very_near) + rssi_thr = cl_hw->conf->ci_vns_rssi_thr - cl_hw->conf->ci_vns_rssi_hys; + else + rssi_thr = cl_hw->conf->ci_vns_rssi_thr + cl_hw->conf->ci_vns_rssi_hys; + + is_vns = (strongset_rssi > rssi_thr) ? true : false; + + /* Avoid toggling of VNS state - require two consecutive same decisions */ + if (is_vns != vns_db->prev_decision) { + vns_db->prev_decision = is_vns; + return; + } + + if (is_vns != vns_db->is_very_near) { + CL_VNS_DBG("[VNS] sta %pM changed state, strongset_rssi = %d, is_vns = %s\n", + cl_sta->addr, strongset_rssi, is_vns ? "TRUE" : "FALSE"); + vns_db->is_very_near = is_vns; + cl_msg_tx_set_vns(cl_hw, cl_sta->sta_idx, is_vns); + } +} + +static void cl_vns_recovery_sta(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + if (cl_sta->vns_db.is_very_near) + cl_msg_tx_set_vns(cl_hw, cl_sta->sta_idx, true); +} + +static int cl_vns_print_sta_state(struct cl_hw *cl_hw) +{ + struct cl_sta *cl_sta = NULL; + char *buf = NULL; + ssize_t buf_size; + int err = 0; + int len = 0; + + /* Go over all stations - use bottom-half lock */ + read_lock_bh(&cl_hw->cl_sta_db.lock); + + list_for_each_entry(cl_sta, &cl_hw->cl_sta_db.head, list) + cl_snprintf(&buf, &len, &buf_size, + "sta_idx = %u, mac = %pM, is_very_near = %s\n", + cl_sta->sta_idx, cl_sta->addr, + cl_sta->vns_db.is_very_near ? + "true" : "false"); + + read_unlock_bh(&cl_hw->cl_sta_db.lock); + err = cl_vendor_reply(cl_hw, buf, len); + kfree(buf); + + return err; +} + +static int cl_vns_cli_help(struct cl_hw *cl_hw) +{ + char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + int err = 0; + + if (!buf) + return -ENOMEM; + + snprintf(buf, PAGE_SIZE, + "vns usage\n" + "-a: Set rssi auto response threshold [thr]\n" + "-d: Set debug [0/1]\n" + "-h: Set rssi hystersis [hyst]\n" + "-l: Set power limit [limit]\n" + "-m: Set power mode [mode]\n" + "-p: Set debug per packet [0/1]\n" + "-s: Print all stations state\n" + "-t: Set rssi threshold [thr]\n"); + + err = cl_vendor_reply(cl_hw, buf, strlen(buf)); + kfree(buf); + + return err; +} + +void cl_vns_init(struct cl_hw *cl_hw) +{ + int i = 0; + u8 vns_pwr_mode = cl_hw->conf->ci_vns_pwr_mode; + + if (vns_pwr_mode == VNS_MODE_DATA || vns_pwr_mode == VNS_MODE_ALL) + cl_hw->vns_db.enable = true; + + spin_lock_init(&cl_hw->vns_db.lock); + + INIT_LIST_HEAD(&cl_hw->vns_db.mgmt_db.list_all); + + for (i = 0; i < STA_HASH_SIZE; i++) + INIT_LIST_HEAD(&cl_hw->vns_db.mgmt_db.list_addr[i]); +} + +void cl_vns_close(struct cl_hw *cl_hw) +{ + if (cl_hw->vns_db.enable) { + spin_lock_bh(&cl_hw->vns_db.lock); + cl_vns_mgmt_list_flush(cl_hw); + spin_unlock_bh(&cl_hw->vns_db.lock); + + cl_hw->vns_db.enable = false; + } +} + +void cl_vns_maintenance(struct cl_hw *cl_hw) +{ + /* + * Maintenance: + * 1) Remove old entries from mgmt list + * 2) Update state for associated clients + */ + if (!cl_hw->vns_db.enable) + return; + + cl_hw->vns_db.interval_period += CL_MAINTENANCE_PERIOD_SLOW_MS; + + if (cl_hw->vns_db.interval_period < cl_hw->conf->ci_vns_maintenance_time) + return; + + cl_hw->vns_db.interval_period = 0; + + spin_lock_bh(&cl_hw->vns_db.lock); + cl_vns_mgmt_list_ageout(cl_hw); + spin_unlock_bh(&cl_hw->vns_db.lock); + + /* Check RSSI of associated stations */ + cl_sta_loop(cl_hw, cl_vns_monitor_rssi); +} + +void cl_vns_mgmt_handler(struct cl_hw *cl_hw, u8 *addr, s8 rssi[MAX_ANTENNAS]) +{ + /* + * Handle management frames of non-associated stations, + * and save the very-near ones in the mgmt list + */ + s8 strongset_rssi = 0; + struct cl_vns_rssi_entry *entry = NULL; + + if (!cl_hw->vns_db.enable) + return; + + strongset_rssi = cl_rssi_get_strongest(cl_hw, rssi); + + spin_lock_bh(&cl_hw->vns_db.lock); + + entry = cl_vns_mgmt_list_find(cl_hw, addr); + + if (entry) { + if (strongset_rssi > cl_hw->conf->ci_vns_rssi_thr) { + /* Update existing entry */ + entry->strongset_rssi = strongset_rssi; + entry->timestamp = jiffies; + CL_VNS_DBG("[VNS] sta %pM updated in list (rssi=%d)\n", + addr, strongset_rssi); + } else { + /* Remove existing entry */ + cl_vns_mgmt_list_remove(cl_hw, entry); + CL_VNS_DBG("[VNS] sta %pM removed from list (rssi=%d)\n", + addr, strongset_rssi); + } + } else { + if (strongset_rssi > cl_hw->conf->ci_vns_rssi_thr) { + /* Add new entry */ + cl_vns_mgmt_list_add(cl_hw, addr, strongset_rssi); + CL_VNS_DBG("[VNS] sta %pM added to list (rssi=%d)\n", + addr, strongset_rssi); + } + } + + spin_unlock_bh(&cl_hw->vns_db.lock); +} + +bool cl_vns_is_very_near(struct cl_hw *cl_hw, struct cl_sta *cl_sta, struct sk_buff *skb) +{ + bool is_vns = false; + /* This function checks for every TX packet whether it's VNS or not */ + if (!cl_hw->vns_db.enable) + return false; + + if (unlikely(!cl_sta)) { + struct ieee80211_hdr *mac_hdr = (struct ieee80211_hdr *)skb->data; + + spin_lock_bh(&cl_hw->vns_db.lock); + is_vns = cl_vns_mgmt_list_find(cl_hw, mac_hdr->addr1) ? true : false; + spin_unlock_bh(&cl_hw->vns_db.lock); + + CL_VNS_DBG_PER_PACKET("[VNS] mgmt-sta %pM, is_vns = %s\n", + mac_hdr->addr1, is_vns ? "TRUE" : "FALSE"); + + return is_vns; + } + is_vns = cl_sta->vns_db.is_very_near; + + CL_VNS_DBG_PER_PACKET("[VNS] assoc-sta %pM, is_vns = %s\n", + cl_sta->addr, is_vns ? "TRUE" : "FALSE"); + + return is_vns; +} + +void cl_vns_sta_add(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + /* Update is_very_near according to mgmt list */ + bool is_vns = false; + + if (!cl_hw->vns_db.enable) + return; + + spin_lock_bh(&cl_hw->vns_db.lock); + is_vns = cl_vns_mgmt_list_find_and_remove(cl_hw, cl_sta->addr); + spin_unlock_bh(&cl_hw->vns_db.lock); + + if (is_vns) { + CL_VNS_DBG("[VNS] sta %pM connected - is_vns = TRUE\n", cl_sta->addr); + cl_sta->vns_db.is_very_near = true; + cl_sta->vns_db.prev_decision = true; + cl_msg_tx_set_vns(cl_hw, cl_sta->sta_idx, true); + } else { + CL_VNS_DBG("[VNS] sta %pM connected - is_vns = FALSE\n", cl_sta->addr); + } +} + +void cl_vns_handle_rssi(struct cl_hw *cl_hw, struct cl_sta *cl_sta, s8 rssi[MAX_ANTENNAS]) +{ + /* Collect rssi samples */ + int i; + + if (!cl_hw->vns_db.enable) + return; + + for (i = 0; i < cl_hw->num_antennas; i++) + cl_sta->vns_db.rssi_sum[i] += rssi[i]; + + cl_sta->vns_db.rssi_samples++; +} + +void cl_vns_recovery(struct cl_hw *cl_hw) +{ + CL_VNS_DBG("[VNS] Recovery\n"); + cl_sta_loop_bh(cl_hw, cl_vns_recovery_sta); +} + +int cl_vns_cli(struct cl_hw *cl_hw, struct cli_params *cli_params) +{ + u32 expected_params = 0; + bool set_rssi_auto_rsp_thr = false; + bool set_dbg = false; + bool set_rssi_hyst = false; + bool set_pwr_limit = false; + bool set_pwr_mode = false; + bool set_dbg_per_packet = false; + bool print_sta_state = false; + bool set_rssi_thr = false; + + switch (cli_params->option) { + case 'a': + set_rssi_auto_rsp_thr = true; + expected_params = 1; + break; + case 'd': + set_dbg = true; + expected_params = 1; + break; + case 'h': + set_rssi_hyst = true; + expected_params = 1; + break; + case 'l': + set_pwr_limit = true; + expected_params = 1; + break; + case 'm': + set_pwr_mode = true; + expected_params = 1; + break; + case 'p': + set_dbg_per_packet = true; + expected_params = 1; + break; + case 's': + print_sta_state = true; + expected_params = 0; + break; + case 't': + set_rssi_thr = true; + expected_params = 1; + break; + case '?': + return cl_vns_cli_help(cl_hw); + default: + cl_dbg_err(cl_hw, "Illegal option (%c) - try '?' for help\n", cli_params->option); + goto out_err; + } + + if (expected_params != cli_params->num_params) { + cl_dbg_err(cl_hw, "Wrong number of arguments (expected %u) (actual %u)\n", + expected_params, cli_params->num_params); + goto out_err; + } + + if (set_rssi_auto_rsp_thr) { + cl_hw->conf->ci_vns_rssi_auto_resp_thr = (s8)cli_params->params[0]; + pr_debug("[VNS] rssi auto response threshold = %d\n", + cl_hw->conf->ci_vns_rssi_auto_resp_thr); + return 0; + } + + if (set_dbg) { + cl_hw->vns_db.dbg = (bool)cli_params->params[0]; + pr_debug("[VNS] debug = %s\n", cl_hw->vns_db.dbg ? "enable" : "disable"); + return 0; + } + + if (set_pwr_limit) { + cl_hw->conf->ci_vns_pwr_limit = (s8)cli_params->params[0]; + pr_debug("[VNS] power limit = %d\n", cl_hw->conf->ci_vns_pwr_limit); + return 0; + } + + if (set_rssi_hyst) { + cl_hw->conf->ci_vns_rssi_hys = (s8)cli_params->params[0]; + pr_debug("[VNS] rssi hystersis = %d\n", cl_hw->conf->ci_vns_rssi_hys); + return 0; + } + + if (set_pwr_mode) { + cl_hw->conf->ci_vns_pwr_mode = (u8)cli_params->params[0]; + pr_debug("[VNS] power mode = %u\n", cl_hw->conf->ci_vns_pwr_mode); + return 0; + } + + if (set_dbg_per_packet) { + cl_hw->vns_db.dbg_per_packet = (bool)cli_params->params[0]; + pr_debug("[VNS] debug per packet = %s\n", + cl_hw->vns_db.dbg_per_packet ? "enable" : "disable"); + return 0; + } + + if (set_rssi_thr) { + cl_hw->conf->ci_vns_rssi_thr = (s8)cli_params->params[0]; + pr_debug("[VNS] rssi threshold = %d\n", cl_hw->conf->ci_vns_rssi_thr); + return 0; + } + + if (print_sta_state) + return cl_vns_print_sta_state(cl_hw); + +out_err: + return -EIO; +} From patchwork Thu Jun 17 16:02:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77C0DC48BE5 for ; Thu, 17 Jun 2021 16:11:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FBAF61428 for ; Thu, 17 Jun 2021 16:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229580AbhFQQNG (ORCPT ); Thu, 17 Jun 2021 12:13:06 -0400 Received: from mail-eopbgr10062.outbound.protection.outlook.com ([40.107.1.62]:13120 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233713AbhFQQLx (ORCPT ); Thu, 17 Jun 2021 12:11:53 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SSMpkF0YvcL0Dk8ncLNHpS/LTUIVRcK5uhdpMr7UoppuyVFipfHtS2B181rynawnJ74lpsD/Jm9gPNZnxnmpbhwgdrcG1j3/59xMHEKvMzYjtVJ1masTe+VEp5dYjalv0me03ofgClJk0CU7R4d/TUVPIaoI0LiUL1dvGVLJzuozuhQp8+OGtR9MLu/J3kNmiN/AT1Qbi67WOC3rEeVDSUF+1tfWYgbHPMoeBuPjSe8zI61kZIF/PbZON7cuK4wKII6ossEwlq95sYR7E98GjmiA70p4l7l1h6udu7DgRliofdmGH9riT0sGZJtaI60vr98WO6nMswv14IV8NrZidw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/zj9/ivXdi6XLVKAukd4eP6IpgdaQCFPAgiT9M9l0SA=; b=c+sYEdIKLvJ6tepdKTFsq6+tYEMwe+4hhW9IxPZSelcHmbYTxd+TT5qBPe9e93rH8WEp66g08rDnMzweVoOmMnnc1/8TXak4f4bOzqlo+k2Qm1u2xI9p/fwI7vgQDt7hrCEHismIvKzsRB3aoU0fz+34vRub6u7kkw0NS5vjeUDHu1G1+iwAWNCnIqFCc/slpbceGUpllcM5xpah7B8AVZo0W0vKSo8wsYEkBjGcdyap09FqU4GaH6JvdFYcASySxbZFyyT8AOxjAfPQ3RRlf6qLX9bL4psbT+7UWb+tQKa1cxyvgtn0QTe+mxdPtWoIBFTI7wI5v0iDP8F0wUsT2g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/zj9/ivXdi6XLVKAukd4eP6IpgdaQCFPAgiT9M9l0SA=; b=dBJxpzcxFCFgPGdOB6/orGiYj5u9xaBlYMijZwGgoN07ia0UmNul4Kb9G4kkQxHFi7QKhKpaCcfQ+uL8Szfx1a7u05B/3YoE3OuyisH8EAQSgjCeQoK9NpbPqGu4ihewNgCQl5hXOIrMjWWVTuyWIYc/bZgZiQ0EpRzmOzRVooQ= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM0P192MB0515.EURP192.PROD.OUTLOOK.COM (2603:10a6:208:45::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:08:01 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:01 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/wrs/wrs.c | 1159 ++++++++++++++++++++ 1 file changed, 1159 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs.c b/drivers/net/wireless/celeno/cl8k/wrs/wrs.c new file mode 100644 index 000000000000..5e2af5d34c8e --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs.c @@ -0,0 +1,1159 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include +#include "wrs/wrs.h" +#include "wrs/wrs_stats.h" +#include "wrs/wrs_tables.h" +#include "wrs/wrs_rssi.h" +#include "env_det.h" +#include "utils/math.h" +#include "rssi.h" +#include "band.h" +#include "rate_ctrl.h" +#include "chip.h" +#include "ext/dyn_bcast_rate.h" +#include "reg/reg_mac_hw.h" +#include "data_rates.h" +#include "rsrc_mgmt.h" + +static void cl_wrs_reset_params_cntrs(struct cl_wrs_params *wrs_params) +{ + wrs_params->frames_total = 0; + wrs_params->fail_total = 0; + wrs_params->ba_not_rcv_total = 0; + wrs_params->epr_acc = 0; + wrs_params->up_same_time_cnt = 0; + wrs_params->down_time_cnt = 0; +} + +static bool cl_wrs_down_epr_check(struct cl_wrs_db *wrs_db, struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params, u8 drop_factor, + enum cl_wrs_decision decision) +{ + u16 curr_rate_idx = wrs_params->rate_idx; + struct cl_wrs_table *curr_rate = &wrs_params->table[curr_rate_idx]; + u64 curr_epr_acc = curr_rate->epr_acc; + u32 curr_total = curr_rate->frames_total; + u16 down_rate_idx = curr_rate->rate_down.rate_idx; + struct cl_wrs_table *down_rate = &wrs_params->table[down_rate_idx]; + u64 down_epr_acc = down_rate->epr_acc; + u32 down_total = down_rate->frames_total; + u16 down_data_rate = 0; + u64 condition1 = 0, condition2 = 0; + bool down_decision = false, allow_penalty = true; + + if (wrs_params->calc_ba_not_rcv) { + curr_total += curr_rate->ba_not_rcv_total; + down_total += down_rate->ba_not_rcv_total; + } + + /* + * In the EPR of down candidate is better than or equal to current EPR => return true + * + * (1) curr_epr <= down_epr * factor(%) + * + * curr_epr_acc down_epr_acc factor + * (2) -------------- <= -------------- * -------- + * curr_total down_total 100 + * + * (3) curr_epr_acc * down_total * 100 <= down_epr_acc * curr_total * factor + * + * (4) conditation1 <= conditation2 + * down_epr_acc + * If (down_total == 0) we use down_data_rate instead of: -------------- + * down_total + */ + if (down_total) { + condition1 = curr_epr_acc * down_total * 100; + condition2 = down_epr_acc * curr_total * drop_factor; + } else { + down_data_rate = cl_data_rates_get_x10(wrs_params->tx_params.mode, + down_rate->rate.bw, + down_rate->rate.nss, + down_rate->rate.mcs, + down_rate->rate.gi); + + condition1 = curr_epr_acc * 100; + condition2 = (u64)down_data_rate * curr_total * drop_factor; + allow_penalty = false; + } + + wrs_params->penalty_decision_dn = wrs_db->step_down; + + if (condition2 && condition1 <= condition2) { + down_decision = true; + + if (allow_penalty) { + /* + * The penalty is calculated as follow: + * + * penalty = MAX_STEP * penalty_factor + * epr_curr + * penalty = MAX_STEP * (100% - 100% * ----------) + * epr_down + * + * conditation1 + * penalty = MAX_STEP * (100% - 100% --------------) + * conditation2 + */ + + u64 penalty_factor = 100 - div64_u64(condition1 * 100, condition2); + u16 max_step = wrs_db->time_th_max_up - wrs_db->step_down; + + wrs_params->penalty_decision_dn += + div64_u64(max_step * penalty_factor, 100); + } + + if (decision != WRS_DECISION_SAME) + wrs_pr_info(wrs_db, + "[WRS] EPR check: sta = %u, pkt_curr = %u, pkt_down = %u, " + "epr_curr = %llu, epr_down * %u%% = %llu, penalty = %u\n", + wrs_sta->sta_idx, + curr_total, + down_total, + div64_u64(curr_epr_acc, curr_total * 10), + drop_factor, + down_total ? + div64_u64(down_epr_acc * drop_factor, down_total * 1000) : + (down_data_rate / 10), + wrs_params->penalty_decision_dn); + } + + return down_decision; +} + +static void cl_wrs_time_thr_max_handler(struct cl_wrs_db *wrs_db, + struct cl_wrs_table *table, u8 up_idx) +{ + /* + * Check if there are at least two UP rates, + * and all UP rates reached max time threshold + */ + u8 i = 0; + u8 time_th_max = 0; + + for (i = 0; i < WRS_TABLE_NODE_UP_MAX; i++) { + if (table->rate_up[i].rate_idx == WRS_INVALID_RATE) + continue; + + if (table->rate_up[i].time_th != wrs_db->time_th_max_up) + return; + + time_th_max++; + } + + if (time_th_max < 2) + return; + + /* Find the next max rate, and decrease its time threshold by 1 */ + i = 0; + while (i < WRS_TABLE_NODE_UP_MAX) { + up_idx++; + if (up_idx == WRS_TABLE_NODE_UP_MAX) + up_idx = WRS_TABLE_NODE_UP_MCS; + + if (table->rate_up[up_idx].rate_idx != WRS_INVALID_RATE) { + /* + * If all up rates reached max time threshold,the first up + * rate will always be selected. + * To overcome it, we decrease the time threshold of the next + * up rate by 1 (so it will be samller and selected next time) + */ + table->rate_up[up_idx].time_th--; + break; + } + + i++; + } +} + +static bool cl_wrs_find_up_candidate(struct cl_wrs_db *wrs_db, struct cl_wrs_params *wrs_params, + u16 *up_rate_idx, u32 *up_time_th) +{ + bool up_rate_valid = false; + u8 up_idx = 0; + u8 up_candidate = 0; + u16 rate_idx = 0; + struct cl_wrs_table *table = &wrs_params->table[wrs_params->rate_idx]; + + *up_rate_idx = WRS_INVALID_RATE; + *up_time_th = U32_MAX; + + for (up_idx = 0; up_idx < WRS_TABLE_NODE_UP_MAX; up_idx++) { + rate_idx = table->rate_up[up_idx].rate_idx; + + if (rate_idx == WRS_INVALID_RATE) + continue; + + if (wrs_db->quick_up_en && table->rate_up[up_idx].quick_up_check) { + *up_rate_idx = rate_idx; + *up_time_th = wrs_db->quick_up_interval; + up_rate_valid = true; + up_candidate = up_idx; + break; + } else if (table->rate_up[up_idx].time_th < *up_time_th) { + *up_rate_idx = rate_idx; + *up_time_th = table->rate_up[up_idx].time_th; + up_rate_valid = true; + up_candidate = up_idx; + } + } + + if (wrs_db->time_th_max_up == *up_time_th) + cl_wrs_time_thr_max_handler(wrs_db, table, up_candidate); + + return up_rate_valid; +} + +static bool cl_wrs_epr_immeidate_down(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params, + u16 down_rate_idx) +{ + if (cl_wrs_down_epr_check(wrs_db, wrs_sta, wrs_params, + wrs_db->immediate_drop_epr_factor, + WRS_DECISION_DOWN_IMMEDIATE)) { + /* + * If there are several immediate drops in a row ignore them, + * because it is probably not realted to bad TX rate + */ + wrs_params->immediate_drop_cntr++; + + if (wrs_params->immediate_drop_cntr > wrs_db->immediate_drop_max_in_row) { + wrs_params->immediate_drop_ignore++; + + cl_wrs_tables_reset(wrs_db, wrs_sta, wrs_params); + cl_wrs_reset_params_cntrs(wrs_params); + + wrs_pr_info(wrs_db, + "[WRS] sta %u - ignore immediate down decision (cntr=%u)\n", + wrs_sta->sta_idx, wrs_params->immediate_drop_cntr); + return true; + } + + cl_wrs_decision_make(cl_hw, wrs_db, wrs_sta, wrs_params, + WRS_DECISION_DOWN_IMMEDIATE, down_rate_idx); + return true; + } + + return false; +} + +static void cl_wrs_decision_up(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params, + u16 up_rate_idx, u32 up_th) +{ + enum cl_wrs_decision up_decision = (up_th == wrs_db->quick_up_interval) ? + WRS_DECISION_UP_QUICK : WRS_DECISION_UP; + + cl_wrs_decision_make(cl_hw, wrs_db, wrs_sta, wrs_params, up_decision, up_rate_idx); +} + +static void cl_wrs_decision_same(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params, + u16 rate_idx) +{ + cl_wrs_decision_make(cl_hw, wrs_db, wrs_sta, wrs_params, WRS_DECISION_SAME, rate_idx); +} + +static void cl_wrs_epr_decision(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params) +{ + u16 curr_rate_idx = wrs_params->rate_idx; + struct cl_wrs_table *table = &wrs_params->table[curr_rate_idx]; + u16 down_rate_idx = table->rate_down.rate_idx; + u16 up_rate_idx = 0; + u16 down_th = table->rate_down.time_th; + u32 up_th = 0; + bool up_rate_valid = false; + + /* Check if we transmitted enough frames for taking decision */ + if ((wrs_params->frames_total + wrs_params->ba_not_rcv_total) < + wrs_db->min_frames_for_decision) + return; + + up_rate_valid = cl_wrs_find_up_candidate(wrs_db, wrs_params, &up_rate_idx, &up_th); + + /* RSSI protect */ + if (wrs_db->rssi_protect_en) + if (cl_wrs_rssi_prot_decision(cl_hw, wrs_db, wrs_sta, up_rate_valid, + up_rate_idx, down_rate_idx)) + return; + + if (down_rate_idx != curr_rate_idx) { + /* Down immediate */ + if (wrs_db->immediate_drop_en) + if (cl_wrs_epr_immeidate_down(cl_hw, wrs_db, wrs_sta, + wrs_params, down_rate_idx)) + return; + + /* Down */ + if (wrs_params->down_time_cnt >= down_th) { + if (cl_wrs_down_epr_check(wrs_db, wrs_sta, wrs_params, + wrs_db->epr_factor, WRS_DECISION_DOWN)) { + cl_wrs_decision_make(cl_hw, wrs_db, wrs_sta, wrs_params, + WRS_DECISION_DOWN, down_rate_idx); + return; + } + + wrs_params->down_time_cnt = 0; + } + } + + /* Up-same */ + if (wrs_params->up_same_time_cnt >= up_th) { + if (up_rate_valid) + cl_wrs_decision_up(cl_hw, wrs_db, wrs_sta, wrs_params, up_rate_idx, up_th); + else + cl_wrs_decision_same(cl_hw, wrs_db, wrs_sta, wrs_params, curr_rate_idx); + + return; + } + + /* + * If there is no valid UP rate and the EPR is more + * than EPR down threshold => make a same decision + */ + if (!up_rate_valid && + !cl_wrs_down_epr_check(wrs_db, wrs_sta, wrs_params, + wrs_db->epr_factor, WRS_DECISION_SAME)) + cl_wrs_decision_same(cl_hw, wrs_db, wrs_sta, wrs_params, curr_rate_idx); +} + +static void cl_wrs_divide_weights_by_two(struct cl_wrs_table *table_node) +{ + u8 up_idx = 0; + struct cl_wrs_table_node *rate_up; + + /* + * Converge weights - divide all weights by 2 + * (make sure they do not go below their init value) + */ + if (table_node->rate_down.rate_idx != WRS_INVALID_RATE) + table_node->rate_down.time_th = max(table_node->rate_down.time_th >> 1, + WRS_INIT_MSEC_WEIGHT_DOWN); + + for (up_idx = 0; up_idx < WRS_TABLE_NODE_UP_MAX; up_idx++) { + rate_up = &table_node->rate_up[up_idx]; + + if (rate_up->rate_idx != WRS_INVALID_RATE) + rate_up->time_th = max(rate_up->time_th >> 1, WRS_INIT_MSEC_WEIGHT_UP); + + if (rate_up->time_th == WRS_INIT_MSEC_WEIGHT_UP) + rate_up->quick_up_check = false; + } +} + +static void cl_wrs_converge_weights(struct cl_wrs_params *wrs_params) +{ + /* + * Converge weights - divide the weights by 2 (except for the current rate), + * and reset PER counters (except for current rate, down rate, and down-down rate). + */ + u16 i; + u16 curr_idx = wrs_params->rate_idx; + u16 down_idx = wrs_params->table[curr_idx].rate_down.rate_idx; + u16 down2_idx = wrs_params->table[down_idx].rate_down.rate_idx; + + for (i = 0; i < wrs_params->table_size; i++) { + if (i == curr_idx) + continue; + + cl_wrs_divide_weights_by_two(&wrs_params->table[i]); + + if (i != down_idx && i != down2_idx) { + wrs_params->table[i].frames_total = 0; + wrs_params->table[i].ba_not_rcv_total = 0; + wrs_params->table[i].epr_acc = 0; + } + } +} + +static void cl_wrs_converge_weights_idle_decision(struct cl_hw *cl_hw, + struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params) +{ + /* + * Continue normal converge (just like during traffic). + * After 6 seconds reset table, and select rate based on RSSI. + */ + if (!wrs_db->converge_idle_en) + return; + + wrs_params->converge_time_idle += wrs_db->interval; + + if (wrs_params->converge_mode == WRS_CONVERGE_MODE_RESET) { + if (wrs_params->converge_time_idle < wrs_db->converge_idle_interval_reset) { + cl_wrs_converge_weights(wrs_params); + } else { + wrs_params->converge_mode = WRS_CONVERGE_MODE_RSSI; + wrs_params->converge_time_idle = 0; + + wrs_pr_info(wrs_db, "[WRS] Converge weights: sta %u - RSSI\n", + wrs_sta->sta_idx); + + /* Reset table and choose new rate based on RSSI */ + cl_wrs_tables_reset(wrs_db, wrs_sta, wrs_params); + + cl_wrs_rssi_set_rate(cl_hw, wrs_db, wrs_sta); + } + } else { + if (wrs_params->converge_time_idle < wrs_db->converge_idle_interval_rssi) + return; + + /* Choose new rate based on RSSI */ + wrs_params->converge_time_idle = 0; + cl_wrs_rssi_set_rate(cl_hw, wrs_db, wrs_sta); + } +} + +static void cl_wrs_converge_weights_idle_reset(struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params) +{ + /* There was traffic in last maintenance interval - reset converge parameteres */ + wrs_params->converge_time_idle = 0; + + if (wrs_params->converge_mode != WRS_CONVERGE_MODE_RESET) { + wrs_params->converge_mode = WRS_CONVERGE_MODE_RESET; + wrs_pr_info(wrs_db, "[WRS] Converge weights: sta %u - RESET\n", + wrs_sta->sta_idx); + } +} + +static void cl_wrs_converge_weights_trfc_decision(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_wrs_db *wrs_db, + struct cl_wrs_params *wrs_params) +{ + u32 converge_interval = 0; + + if (!wrs_db->converge_trfc_en) + return; + + if (cl_motion_sense_is_static(cl_hw, cl_sta) && cl_env_det_is_clean(cl_hw)) + converge_interval = wrs_db->converge_trfc_interval_static; + else + converge_interval = wrs_db->converge_trfc_interval_motion; + + wrs_params->converge_time_trfc += wrs_db->interval; + + if (wrs_params->converge_time_trfc >= converge_interval) { + wrs_params->converge_time_trfc = 0; + cl_wrs_converge_weights(wrs_params); + } +} + +static u32 cl_wrs_get_sync_attempts(struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params) +{ + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + + return cl_sta->wrs_info.sync_attempts; +} + +static void cl_wrs_sta_no_sync_handler(struct cl_hw *cl_hw, + struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params) +{ + unsigned long time_delta = jiffies_to_msecs(jiffies - wrs_params->no_sync_timestamp); + + if (time_delta < wrs_db->sync_timeout) + return; + + if (cl_wrs_get_sync_attempts(wrs_sta, wrs_params) < wrs_db->sync_min_attempts) { + /* + * Rate not synced but there is also hardly no traffic - + * change mode to synced! + */ + wrs_params->sync = true; + wrs_params->sync_timestamp = jiffies; + } else { + struct cl_wrs_table *wrs_table = &wrs_params->table[wrs_params->rate_idx]; + struct cl_wrs_rate *curr_rate = &wrs_table->rate; + + if (!cl_hw->ate_db.active) + pr_warn("[WRS] NO SYNC - sta = %u, bw = %u, nss = %u, mcs = %u, gi = %u\n", + wrs_sta->sta_idx, curr_rate->bw, curr_rate->nss, + curr_rate->mcs, curr_rate->gi); + + if (WRS_IS_DECISION_UP(wrs_params->last_decision)) { + cl_wrs_decision_make(cl_hw, wrs_db, wrs_sta, wrs_params, + WRS_DECISION_DOWN_NO_SYNC, + wrs_table->rate_down.rate_idx); + } else { + /* If the last decision was DOWN - change state to SYNCED. */ + wrs_params->sync = true; + wrs_params->sync_timestamp = jiffies; + } + } +} + +static void cl_wrs_update_ba_not_rcv(struct cl_wrs_db *wrs_db, struct cl_wrs_params *wrs_params) +{ + unsigned long time_since_sync = jiffies_to_msecs(jiffies - wrs_params->sync_timestamp); + + wrs_params->calc_ba_not_rcv = (wrs_db->ba_not_rcv_force || + (time_since_sync < wrs_db->ba_not_rcv_time_since_sync)); +} + +static void _cl_wrs_tx_cntrs_reset(struct cl_wrs_info *wrs_info) +{ + wrs_info->epr_acc = 0; + wrs_info->tx_success = 0; + wrs_info->tx_fail = 0; + wrs_info->ba_not_rcv = 0; + wrs_info->ba_not_rcv_consecutive_max = 0; +} + +static void cl_wrs_tx_cntrs_read(struct cl_wrs_sta *wrs_sta, + struct cl_wrs_tx_cntrs *tx_cntrs) +{ + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + struct cl_wrs_info *wrs_info = &cl_sta->wrs_info; + + tx_cntrs->epr_acc = wrs_info->epr_acc; + tx_cntrs->total = wrs_info->tx_success + wrs_info->tx_fail; + tx_cntrs->fail = wrs_info->tx_fail; + tx_cntrs->ba_not_rcv = wrs_info->ba_not_rcv; + tx_cntrs->ba_not_rcv_consecutive = wrs_info->ba_not_rcv_consecutive_max; + + _cl_wrs_tx_cntrs_reset(wrs_info); +} + +static void _cl_wrs_sta_maintenance(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_wrs_params *wrs_params) +{ + struct cl_wrs_db *wrs_db = &cl_hw->wrs_db; + struct cl_wrs_sta *wrs_sta = &cl_sta->wrs_sta; + struct cl_wrs_tx_cntrs tx_cntrs = {0}; + + if (!wrs_params->sync) { + cl_wrs_sta_no_sync_handler(cl_hw, wrs_db, wrs_sta, wrs_params); + return; + } + + cl_wrs_update_ba_not_rcv(wrs_db, wrs_params); + cl_wrs_tx_cntrs_read(wrs_sta, &tx_cntrs); + + if (wrs_params->is_fixed_rate) { + cl_wrs_stats_per_update(wrs_db, wrs_sta, wrs_params, &tx_cntrs); + return; + } + + wrs_params->down_time_cnt += wrs_db->interval; + wrs_params->up_same_time_cnt += wrs_db->interval; + + if ((tx_cntrs.total + tx_cntrs.ba_not_rcv) < wrs_db->converge_idle_packet_th) { + /* + * Very few frames were sent in last maintenance interval + * Check if weights should be converged + */ + cl_wrs_converge_weights_idle_decision(cl_hw, wrs_db, wrs_sta, wrs_params); + + cl_wrs_stats_per_update(wrs_db, wrs_sta, wrs_params, &tx_cntrs); + + return; + } + + /* There was traffic in last maintenance interval - reset converge parameteres */ + cl_wrs_converge_weights_idle_reset(wrs_db, wrs_sta, wrs_params); + + cl_wrs_stats_per_update(wrs_db, wrs_sta, wrs_params, &tx_cntrs); + + wrs_params->quick_up_check = + (tx_cntrs.ba_not_rcv_consecutive >= wrs_db->quick_up_ba_thr) ? 1 : 0; + cl_wrs_epr_decision(cl_hw, wrs_db, wrs_sta, wrs_params); + + cl_wrs_converge_weights_trfc_decision(cl_hw, cl_sta, wrs_db, wrs_params); +} + +static void cl_wrs_sta_maintenance(struct cl_hw *cl_hw, struct cl_sta *cl_sta) +{ + _cl_wrs_sta_maintenance(cl_hw, cl_sta, &cl_sta->wrs_sta.su_params); +} + +static void cl_wrs_cca_calc(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, u8 max_bw) +{ + u32 cca_primary_new = mac_hw_edca_cca_busy_get(cl_hw); + u32 cca_sec80_new = (max_bw > CHNL_BW_80) ? mac_hw_add_cca_busy_sec_80_get(cl_hw) : 0; + u32 cca_sec40_new = (max_bw > CHNL_BW_40) ? mac_hw_add_cca_busy_sec_40_get(cl_hw) : 0; + u32 cca_sec20_new = mac_hw_add_cca_busy_sec_20_get(cl_hw); + + u32 cca_primary_diff = cca_primary_new - wrs_db->cca_primary; + u32 cca_sec80_diff = cca_sec80_new - wrs_db->cca_sec80; + u32 cca_sec40_diff = cca_sec40_new - wrs_db->cca_sec40; + u32 cca_sec20_diff = cca_sec20_new - wrs_db->cca_sec20; + + wrs_db->cca_primary = cca_primary_new; + wrs_db->cca_sec80 = cca_sec80_new; + wrs_db->cca_sec40 = cca_sec40_new; + wrs_db->cca_sec20 = cca_sec20_new; + wrs_db->cca_timestamp = jiffies; + + /* Increase by 25% */ + cca_primary_diff = cca_primary_diff * WRS_CCA_PRIMARY_FACTOR >> WRS_CCA_PRIMARY_SHIFT; + + /* Adjacent interference - if secondary is higher than primary by 25%. */ + wrs_db->adjacent_interference80 = (cca_sec80_diff > cca_primary_diff); + wrs_db->adjacent_interference40 = (cca_sec40_diff > cca_primary_diff); + wrs_db->adjacent_interference20 = (cca_sec20_diff > cca_primary_diff); +} + +static void cl_wrs_cca_maintenance(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db) +{ + u8 max_bw = wrs_db->max_cap.bw; + + if (max_bw == CHNL_BW_20) + return; + + if (jiffies_to_msecs(jiffies - wrs_db->cca_timestamp) > WRS_CCA_PERIOD_MS) + cl_wrs_cca_calc(cl_hw, wrs_db, max_bw); +} + +static void cl_wrs_maintenance(unsigned long data) +{ + struct cl_hw *cl_hw = (struct cl_hw *)data; + struct cl_wrs_db *wrs_db = &cl_hw->wrs_db; + + cl_wrs_cca_maintenance(cl_hw, wrs_db); + + cl_wrs_lock(wrs_db); + cl_sta_loop(cl_hw, cl_wrs_sta_maintenance); + cl_wrs_unlock(wrs_db); +} + +static void cl_wrs_down_decision_weights_update(struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, + u16 new_rate_idx, + struct cl_wrs_params *wrs_params) +{ + u16 old_rate_idx = wrs_params->rate_idx; + u8 up_idx = 0; + u16 down_th_min = wrs_db->time_th_min; + u16 step = wrs_db->step_down; + u16 *th_down = &wrs_params->table[old_rate_idx].rate_down.time_th; + u16 *th_up = NULL; + struct cl_wrs_table *table_node = &wrs_params->table[new_rate_idx]; + + /* Decrease the weight from old rate to new rate */ + if (*th_down > (down_th_min + step)) + *th_down -= step; + else + *th_down = down_th_min; + + /* Increase the weight from new rate to old rate */ + for (up_idx = 0; up_idx < WRS_TABLE_NODE_UP_MAX; up_idx++) { + if (old_rate_idx == table_node->rate_up[up_idx].rate_idx) { + th_up = &table_node->rate_up[up_idx].time_th; + table_node->rate_up[up_idx].quick_up_check = !!wrs_params->quick_up_check; + step = wrs_params->penalty_decision_dn; + *th_up = min_t(u16, *th_up + step, wrs_db->time_th_max_up); + break; + } + } + + wrs_pr_info(wrs_db, + "[WRS] Down update - sta = %u, " + "down weight [%u-->%u] = %u, up weight [%u-->%u] = %u\n", + wrs_sta->sta_idx, old_rate_idx, new_rate_idx, + *th_down, new_rate_idx, old_rate_idx, th_up ? *th_up : 0); +} + +static void cl_wrs_up_same_decision_weights_update(struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params) +{ + u16 curr_rate_idx = wrs_params->rate_idx; + u16 down_rate_idx = wrs_params->table[curr_rate_idx].rate_down.rate_idx; + u8 up_idx = 0; + u16 up_th_min = wrs_db->time_th_min; + u16 step = wrs_db->step_up_same; + u16 *th_down = &wrs_params->table[curr_rate_idx].rate_down.time_th; + u16 *th_up = NULL; + u16 th_down_orig = *th_down; + u16 th_up_orig = 0; + struct cl_wrs_table *table_node = &wrs_params->table[down_rate_idx]; + + /* Increase the weight from current rate to down rate */ + *th_down = min_t(u16, *th_down + step, wrs_db->time_th_max_down); + + /* Decrease the weight from down rate to current rate */ + for (up_idx = 0; up_idx < WRS_TABLE_NODE_UP_MAX; up_idx++) { + if (curr_rate_idx == table_node->rate_up[up_idx].rate_idx) { + th_up = &table_node->rate_up[up_idx].time_th; + table_node->rate_up[up_idx].quick_up_check = false; + + th_up_orig = *th_up; + + if (*th_up > (up_th_min + step)) + *th_up -= step; + else + *th_up = up_th_min; + break; + } + } + + if (th_up && (th_up_orig != *th_up || th_down_orig != *th_down)) + wrs_pr_info(wrs_db, + "[WRS] Up/same update - sta = %u, " + "down weight [%u-->%u] = %u, up weight [%u-->%u] = %u\n", + wrs_sta->sta_idx, curr_rate_idx, + down_rate_idx, *th_down, down_rate_idx, curr_rate_idx, *th_up); +} + +void cl_wrs_init(struct cl_hw *cl_hw) +{ + struct cl_wrs_db *wrs_db = &cl_hw->wrs_db; + + /* Default configuration */ + wrs_db->debug_level = DBG_LVL_ERROR; + wrs_db->rssi_protect_en = true; + wrs_db->rssi_protect_mode = WRS_RSSI_PROT_MODE_RSSI; + wrs_db->rssi_protect_up_thr = WRS_RSSI_PROTECT_UP_THR; + wrs_db->rssi_protect_dn_thr = WRS_RSSI_PROTECT_DN_THR; + wrs_db->min_frames_for_decision = WRS_MIN_FRAMES_FOR_DECISION; + wrs_db->epr_factor = WRS_EPR_FACTOR; + wrs_db->converge_idle_en = true; + wrs_db->converge_idle_interval_reset = WRS_CONVERGE_IDLE_INTERVAL_RESET; + wrs_db->converge_idle_interval_rssi = WRS_CONVERGE_IDLE_INTERVAL_RSSI; + wrs_db->converge_idle_packet_th = WRS_CONVERGE_IDLE_PACKET_TH; + wrs_db->converge_trfc_en = true; + wrs_db->converge_trfc_interval_static = WRS_CONVERGE_TRFC_INTERVAL_STATIC; + wrs_db->converge_trfc_interval_motion = WRS_CONVERGE_TRFC_INTERVAL_MOTION; + wrs_db->immediate_drop_en = true; + wrs_db->immediate_drop_epr_factor = WRS_IMMEDIATE_DROP_EPR_FACTOR; + wrs_db->immediate_drop_max_in_row = WRS_IMMEDIATE_DROP_MAX_IN_ROW; + wrs_db->time_th_min = WRS_MSEC_WEIGHT_MIN; + wrs_db->time_th_max_up = WRS_MSEC_WEIGHT_MAX_UP; + wrs_db->time_th_max_down = WRS_MSEC_WEIGHT_MAX_DOWN; + wrs_db->step_down = WRS_MSEC_STEP_DOWN; + wrs_db->step_up_same = WRS_MSEC_STEP_UP_SAME; + wrs_db->interval = msecs_round(WRS_MAINTENANCE_PERIOD_MS); + wrs_db->conservative_mcs_noisy_env = false; + wrs_db->conservative_nss_noisy_env = false; + wrs_db->quick_up_en = true; + wrs_db->quick_up_ba_thr = WRS_QUICK_UP_BA_THR; + wrs_db->quick_up_interval = msecs_round(WRS_QUICK_UP_INTERVAL_MS); + wrs_db->quick_down_en = true; + wrs_db->quick_down_epr_factor = WRS_QUICK_DOWN_EPR_FACTOR; + wrs_db->quick_down_agg_thr = WRS_QUICK_DOWN_AGG_THR; + wrs_db->quick_down_pkt_thr = WRS_QUICK_DOWN_PKT_THR; + wrs_db->ba_not_rcv_collision_filter = true; + /* Environment of 2.4 is much more noisy, so 'BA not received' are ignored. */ + wrs_db->ba_not_rcv_force = cl_band_is_24g(cl_hw) ? false : true; + wrs_db->ba_not_rcv_time_since_sync = WRS_BA_NOT_RCV_TIME_SINCE_SYNC; + wrs_db->sync_timeout = WRS_SYNC_TIMEOUT; + wrs_db->sync_min_attempts = WRS_SYNC_MIN_ATTEMPTS; + + /* Init WRS periodic timer */ + cl_timer_init(&wrs_db->timer_maintenance, + cl_wrs_maintenance, + (unsigned long)cl_hw, + wrs_db->interval, true); + + if (!cl_hw->chip->conf->ce_production_mode) { + wrs_db->cca_timestamp = jiffies; + cl_timer_enable(&wrs_db->timer_maintenance); + } + + spin_lock_init(&wrs_db->lock); + + if ((cl_hw->conf->ci_wrs_fixed_rate[WRS_FIXED_PARAM_MODE] != -1) && + (cl_hw->conf->ci_wrs_fixed_rate[WRS_FIXED_PARAM_BW] != -1) && + (cl_hw->conf->ci_wrs_fixed_rate[WRS_FIXED_PARAM_NSS] != -1) && + (cl_hw->conf->ci_wrs_fixed_rate[WRS_FIXED_PARAM_MCS] != -1) && + (cl_hw->conf->ci_wrs_fixed_rate[WRS_FIXED_PARAM_GI] != -1)) + wrs_db->is_fixed_rate = WRS_FIXED_FALLBACK_DIS; +} + +inline void cl_wrs_lock_bh(struct cl_wrs_db *wrs_db) +{ + spin_lock_bh(&wrs_db->lock); +} + +inline void cl_wrs_unlock_bh(struct cl_wrs_db *wrs_db) +{ + spin_unlock_bh(&wrs_db->lock); +} + +inline void cl_wrs_lock(struct cl_wrs_db *wrs_db) +{ + spin_lock(&wrs_db->lock); +} + +inline void cl_wrs_unlock(struct cl_wrs_db *wrs_db) +{ + spin_unlock(&wrs_db->lock); +} + +void cl_wrs_tx_param_sync(struct cl_wrs_db *wrs_db, struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params) +{ + if (wrs_params->sync) + return; + + /* Reset the tx Counters */ + cl_wrs_tx_cntrs_reset(wrs_sta, wrs_params); + + /* Reset counters */ + cl_wrs_reset_params_cntrs(wrs_params); + + /* Change state to SYNCED */ + wrs_params->sync = true; + wrs_params->sync_timestamp = jiffies; + + wrs_pr_trace(wrs_db, "[WRS] Sync - timestamp = %u, sta = %u, rate_idx = %u\n", + jiffies_to_msecs(jiffies), + wrs_sta->sta_idx, + wrs_params->rate_idx); +} + +void cl_wrs_tx_params_update(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params, + u16 new_rate_idx, bool is_sync_required) +{ + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + struct cl_wrs_tx_params *tx_params = &wrs_params->tx_params; + struct cl_wrs_rate *rate = &wrs_params->table[new_rate_idx].rate; + u16 fallback_rate_idx = wrs_params->table[new_rate_idx].rate_down.rate_idx; + struct cl_wrs_rate *rate_fallback = &wrs_params->table[fallback_rate_idx].rate; + + cl_dyn_bcast_rate_change(cl_hw, cl_sta, tx_params->mcs, rate->mcs); + + tx_params->bw = rate->bw; + tx_params->nss = rate->nss; + tx_params->mcs = rate->mcs; + tx_params->gi = rate->gi; + tx_params->mode = wrs_sta->mode; + tx_params->fallback_en = (wrs_params->is_fixed_rate != WRS_FIXED_FALLBACK_DIS); + + wrs_pr_trace(wrs_db, + "[WRS] Tx params update - " + "sta = %u, rate_idx = %u, bw = %u, nss = %u, mcs = %u, gi = %u\n", + wrs_sta->sta_idx, new_rate_idx, tx_params->bw, + tx_params->nss, tx_params->mcs, tx_params->gi); + + wrs_params->rate_idx = new_rate_idx; + + /* Converge - restart the time for converging weights of all old rates */ + wrs_params->converge_time_trfc = 0; + + cl_wrs_tx_param_set(cl_hw, wrs_sta, wrs_params, tx_params, rate_fallback); + + if (is_sync_required) { + wrs_params->sync = false; + wrs_params->no_sync_timestamp = jiffies; + } else { + wrs_params->sync = true; + } + + /* Reset Counters */ + cl_wrs_reset_params_cntrs(wrs_params); +} + +void cl_wrs_decision_make(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params, + enum cl_wrs_decision decision, u16 new_rate_idx) +{ + if (WRS_IS_DECISION_DOWN(decision)) { + cl_wrs_down_decision_weights_update(wrs_db, wrs_sta, new_rate_idx, wrs_params); + } else if (WRS_IS_DECISION_UP(decision)) { + cl_wrs_up_same_decision_weights_update(wrs_db, wrs_sta, wrs_params); + + if (wrs_params->rate_idx != wrs_params->table[new_rate_idx].rate_down.rate_idx) { + /* + * In case the down rate is different from the previous rate, + * update down rate index and reset the thresholds + */ + struct cl_wrs_table_node *rate_down = + &wrs_params->table[new_rate_idx].rate_down; + + rate_down->rate_idx = wrs_params->rate_idx; + rate_down->time_th = WRS_INIT_MSEC_WEIGHT_DOWN; + } + } else if (decision == WRS_DECISION_SAME) { + cl_wrs_up_same_decision_weights_update(wrs_db, wrs_sta, wrs_params); + + /* Reset counters besides down_time_cnt */ + wrs_params->frames_total = 0; + wrs_params->fail_total = 0; + wrs_params->ba_not_rcv_total = 0; + wrs_params->epr_acc = 0; + wrs_params->up_same_time_cnt = 0; + } + + cl_wrs_decision_update(wrs_db, wrs_sta, wrs_params, decision, new_rate_idx); + + if (WRS_IS_DECISION_DOWN(decision) || WRS_IS_DECISION_UP(decision)) + cl_wrs_tx_params_update(cl_hw, wrs_db, wrs_sta, wrs_params, + new_rate_idx, true); +} + +void cl_wrs_decision_update(struct cl_wrs_db *wrs_db, struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params, enum cl_wrs_decision decision, + u16 new_rate_idx) +{ + wrs_params->last_decision = decision; + wrs_params->decision_cnt[decision]++; + + if (decision != WRS_DECISION_DOWN_IMMEDIATE) + wrs_params->immediate_drop_cntr = 0; + + if (decision == WRS_DECISION_SAME) + return; + + wrs_pr_trace(wrs_db, + "[WRS] Decision update - timestamp [%u] sta [%u] decision [%s]\n", + jiffies_to_msecs(jiffies), + wrs_sta->sta_idx, + WRS_DECISION_STR(decision)); +} + +void cl_wrs_fixed_rate_set(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params, + u8 is_fixed_rate, u8 mode, u8 bw, u8 nss, u8 mcs, u8 gi) +{ + u16 rate_idx = 0; + + if (!is_fixed_rate) { + wrs_params->is_fixed_rate = WRS_AUTO_RATE; + wrs_pr_verbose(wrs_db, "[WRS] Station %u was set to auto rate!\n", + wrs_sta->sta_idx); + cl_wrs_rssi_set_rate(cl_hw, wrs_db, wrs_sta); + return; + } + + if (mode != wrs_sta->mode) { + /* Set fixed rate with a different format-mode */ + struct cl_wrs_tx_params *tx_params = &wrs_params->tx_params; + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + + if (cl_band_is_6g(cl_hw) && mode != WRS_MODE_HE) { + wrs_pr_verbose(wrs_db, "[WRS] Invalid format mode [%u] for 6GHz band\n", + mode); + return; + } + + cl_dyn_bcast_rate_change(cl_hw, cl_sta, tx_params->mcs, mcs); + + tx_params->bw = bw; + tx_params->nss = nss; + tx_params->mcs = mcs; + tx_params->gi = gi; + tx_params->mode = mode; + tx_params->fallback_en = (wrs_params->is_fixed_rate != WRS_FIXED_FALLBACK_DIS); + + wrs_params->is_fixed_rate = is_fixed_rate; + + cl_wrs_tx_param_set(cl_hw, wrs_sta, wrs_params, tx_params, NULL); + wrs_pr_verbose(wrs_db, + "[WRS] Station %u set to %s - " + "mode=%u, bw=%u, nss=%u, mcs=%u, gi=%u\n", + wrs_sta->sta_idx, FIXED_RATE_STR(is_fixed_rate), + mode, bw, nss, mcs, gi); + return; + } + + rate_idx = cl_wrs_tables_find_rate_idx(wrs_params, bw, nss, mcs, gi); + + if (rate_idx == WRS_INVALID_RATE) { + wrs_pr_err(wrs_db, + "[WRS] Invalid fixed rate - mode=%u, bw=%u, nss=%u, mcs=%u, gi=%u\n", + mode, bw, nss, mcs, gi); + return; + } + + wrs_params->is_fixed_rate = is_fixed_rate; + cl_wrs_tx_params_update(cl_hw, wrs_db, wrs_sta, wrs_params, rate_idx, false); + wrs_pr_verbose(wrs_db, + "[WRS] Station %u set to %s - mode=%u, bw=%u, nss=%u, mcs=%u, gi=%u\n", + wrs_sta->sta_idx, FIXED_RATE_STR(is_fixed_rate), + mode, bw, nss, mcs, gi); +} + +void cl_wrs_quick_down_check(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params) +{ + struct cl_wrs_tx_cntrs tx_cntrs = {0}; + struct cl_wrs_table *table = NULL; + u16 curr_rate_idx = 0; + u16 down_rate_idx = 0; + + if (!wrs_params->sync || + wrs_params->is_fixed_rate || + !WRS_IS_DECISION_UP(wrs_params->last_decision)) + return; + + cl_wrs_update_ba_not_rcv(wrs_db, wrs_params); + cl_wrs_tx_cntrs_read(wrs_sta, &tx_cntrs); + cl_wrs_stats_per_update(wrs_db, wrs_sta, wrs_params, &tx_cntrs); + + curr_rate_idx = wrs_params->rate_idx; + table = &wrs_params->table[curr_rate_idx]; + down_rate_idx = table->rate_down.rate_idx; + + /* Check if we transmitted enough frames for taking decision */ + if (wrs_params->frames_total < wrs_db->min_frames_for_decision) + return; + + /* Down decision check */ + if (down_rate_idx != curr_rate_idx && + cl_wrs_down_epr_check(wrs_db, wrs_sta, wrs_params, + wrs_db->quick_down_epr_factor, WRS_DECISION_DOWN_QUICK)) + cl_wrs_decision_make(cl_hw, wrs_db, wrs_sta, wrs_params, + WRS_DECISION_DOWN_QUICK, down_rate_idx); +} + +bool cl_wrs_up_mcs1(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params) +{ + /* + * In case of big packets (4300 in VHT and 5400 in HE) and low + * rate (BW 20, NSS 1, MCS 0), firmware will increase rate to MCS 1, + * and give an indication to driver (set rate_fix_mcs1 in cl_agg_tx_report). + * WRS should also move to MCS 1, and give the maximum time + * penalty time from MCS 0 toMCS 1. + */ + u16 curr_rate_idx = wrs_params->rate_idx; + u16 up_rate_idx = 0; + struct cl_wrs_table *table = &wrs_params->table[curr_rate_idx]; + + if (!table || wrs_params->is_fixed_rate) + return false; + + if (table->rate.bw != CHNL_BW_20 || + table->rate.nss != WRS_SS_1 || + table->rate.mcs != WRS_MCS_0) + return false; + + up_rate_idx = cl_wrs_tables_find_rate_idx(wrs_params, + CHNL_BW_20, WRS_SS_1, WRS_MCS_1, table->rate.gi); + + if (up_rate_idx == WRS_INVALID_RATE) + return false; + + wrs_params->table[up_rate_idx].rate_down.time_th = wrs_db->time_th_max_up; + + cl_wrs_tx_cntrs_reset(wrs_sta, wrs_params); + cl_wrs_decision_update(wrs_db, wrs_sta, wrs_params, WRS_DECISION_UP_MCS1, up_rate_idx); + cl_wrs_tx_params_update(cl_hw, wrs_db, wrs_sta, wrs_params, + up_rate_idx, true); + + return true; +} + +void cl_wrs_tx_param_set(struct cl_hw *cl_hw, struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params, + struct cl_wrs_tx_params *tx_params, + struct cl_wrs_rate *rate_fallback) +{ + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + struct cl_bf_sta_db *bf_db = &cl_sta->bf_db; + struct cl_wrs_info *wrs_info = NULL; + u8 ltf = 0; + u8 ltf_fallback = 0; + u8 sta_idx = cl_sta->sta_idx; + union cl_rate_ctrl_info rate_ctrl; + union cl_rate_ctrl_info rate_ctrl_fallback; + union cl_rate_ctrl_info_he rate_ctrl_he; + + if (cl_hw->ate_db.active) + return; + + rate_ctrl_he.word = 0; + + wrs_info = &cl_sta->wrs_info; + + wrs_params->data_rate = cl_data_rates_get(tx_params->mode, + tx_params->bw, + tx_params->nss, + tx_params->mcs, + tx_params->gi); + + rate_ctrl.word = cl_rate_ctrl_generate(cl_hw, cl_sta, tx_params->mode, + tx_params->bw, tx_params->nss, + tx_params->mcs, tx_params->gi, + tx_params->fallback_en); + + /* For fallback rate use same mode (if it is NULL use same rate). */ + if (rate_fallback) { + rate_ctrl_fallback.word = cl_rate_ctrl_generate(cl_hw, + cl_sta, + tx_params->mode, + rate_fallback->bw, + rate_fallback->nss, + rate_fallback->mcs, + rate_fallback->gi, + tx_params->fallback_en); + ltf_fallback = cl_map_gi_to_ltf(tx_params->mode, rate_fallback->gi); + } else { + rate_ctrl_fallback.word = rate_ctrl.word; + } + + /* Save current BF state and SS for the fallback rate */ + bf_db->is_on = rate_ctrl.field.tx_bf; + bf_db->is_on_fallback = rate_ctrl_fallback.field.tx_bf; + bf_db->num_ss = tx_params->nss; + bf_db->num_ss_fallback = rate_fallback ? rate_fallback->nss : tx_params->nss; + + /* Reset counters */ + wrs_info->tx_success = 0; + wrs_info->tx_fail = 0; + + /* Mark rate as unsynced */ + wrs_info->synced = false; + wrs_info->quick_rate_check = false; + wrs_info->sync_attempts = 0; + + ltf = cl_map_gi_to_ltf(tx_params->mode, tx_params->gi); + + if (tx_params->mode == WRS_MODE_HE) + rate_ctrl_he.field.spatial_conf = RATE_CNTRL_HE_SPATIAL_CONF_DEF; + + /* Send new rate to firmware */ + cl_msg_tx_update_rate_dl(cl_hw, sta_idx, rate_ctrl.word, + rate_ctrl_fallback.word, tx_params->bw, + RATE_OP_MODE_STA_SU, + ltf, ltf_fallback, rate_ctrl_he.word); + + /* + * TODO: Limit by SU/TX if active function will take control + * over MU-SU/TX-RX. + */ + cl_rsrc_mgmt_rates_update(cl_hw, cl_sta); +} + +s8 cl_wrs_rssi_eq_calc(struct cl_hw *cl_hw, struct cl_wrs_sta *wrs_sta, + bool read_clear, s8 *sorted_rssi) +{ + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + struct cl_wrs_rssi *wrs_rssi = &cl_sta->wrs_rssi; + int i; + + if (wrs_rssi->cnt == 0) { + memcpy(sorted_rssi, cl_sta->last_rssi, cl_hw->num_antennas); + goto sort; + } + + for (i = 0; i < cl_hw->num_antennas; i++) + sorted_rssi[i] = (s8)(wrs_rssi->sum[i] / wrs_rssi->cnt); + + if (read_clear) + memset(wrs_rssi, 0, sizeof(struct cl_wrs_rssi)); + +sort: + /* Sort RSSI values in descending order */ + cl_rssi_sort_descending(sorted_rssi, cl_hw->num_antennas); + + /* Calc equivalent RSSI */ + return cl_rssi_calc_equivalent(cl_hw, sorted_rssi); +} + +void cl_wrs_tx_cntrs_reset(struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params) +{ + struct cl_sta *cl_sta = container_of(wrs_sta, struct cl_sta, wrs_sta); + struct cl_wrs_info *wrs_info = &cl_sta->wrs_info; + + _cl_wrs_tx_cntrs_reset(wrs_info); +} From patchwork Thu Jun 17 16:02:08 2021 Content-Type: text/plain; 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Thu, 17 Jun 2021 16:08:32 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 241/256] cl8k: add wrs/wrs_ap.c Date: Thu, 17 Jun 2021 16:02:08 +0000 Message-Id: <20210617160223.160998-242-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:07:02 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a0c8b2fd-2063-4653-c96a-08d931a9f215 X-MS-TrafficTypeDiagnostic: AM8P192MB0978: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:590; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Tcj6EOuZzk21DjAmbRKm6QzFtUPtrWHRAbdHIC2o6St3x4g/8Syn3G/G6W3UmoxEkNCsHkX5EO4g91kL9QazScrF+VOrW4URI/NsABZOfPcq4wCQ13cL9T0EGU+ka2kU0wZFC5WB2i2bg5gbkEW8eEjCn35pwkL85HRxex5dUA//tgU1mprNJM2NpKbNdzI+bUVuI0OBL8Iw9JZq+Vo6f96nfip8TG05gWehKBl1oNxhDdoSNtAhGEcM9NDeRSiznlzTqthuvlhgnxV4OF6HbGClswQH8dNhagZG+B+jJ2koE6pLlmYGZfQdB2g098z2Hm2Kck0z2Qk7ExqLEXI9XD7R381zvY/Y7sYiW+5S4dGzznlHQXzdHbPUo+4b32WMM8pfQqI1Bx+kNKvCCKW6n0I7XJLFnGal9hmR0jq+bqKzvR5ACY9RMQhZfQxR3hdULmzyqE/5+t8XbSsxcHpdWb1I/EsaHgEZAGvtUwVHBggid/hRBymFUm9uRzIVYYuClns2Xm0pyJD/gcG+I7SaaCiXy5S/48/r7ixFfqLeo/ecks1ROkN7wpfitTQUUZA6sLok4q24gu9mI6/VuFTEk1twUP2ZmG8omeYp4clir4V08UGr0Az9vS/ByMV2ntirQdtImuvRWAD1Bk1Z/R72j/XOCa/7rfRkwLugpQT+Wz5Gceyxk2oogMIqSb+TVqZXMpxlNEvFB2VZa8zKIniqDw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(136003)(396003)(376002)(39850400004)(366004)(16526019)(107886003)(5660300002)(66556008)(83380400001)(26005)(186003)(1076003)(2616005)(316002)(66476007)(66946007)(9686003)(2906002)(6512007)(8676002)(508600001)(52116002)(55236004)(6486002)(38350700002)(86362001)(38100700002)(6916009)(8936002)(6506007)(956004)(4326008)(54906003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4eQ8STadqusGwRv/Tm25PBVSW0DZ2oWVHszV0gqAtycW7Fq/9woSjUUtQBcDB5EG1ndtAzhpDkn1Km22k6lgigMp4TUKORISTzk39qEYin0RiqIRfIvavSNOy9sudQnOpKSee0/hUwJUN4SD13FUAl3fPRaSESm3AcEUz8VSNicZ5jknSoItnP/h38ievjheA+EfEC+Zt5FQw2u1FsPhvf31t+se5RqoNUV6AjMbKysmmqOwlsYfHsHt4F3ympf64al1ioraclbjezq+HKZvrZbS5CPDnSWNpjVK68GpemBcBSj3pqp10EYcYQI7sncg1fmP+lLeIbGoslIALLYc8t6v8OUUIH3Tr7EwjE5grpJ1mgEGEgvvlaUVDgmVzotAuuQ2t0IueJMiH5KrZuREpWQgE+MoviX9lwFfXyZipruRhc2ilHj1/jFNz7ZNSNyhFa5JnvzCdFSrgoR5gcsXCh1bQFigWTZIGBsgCKZrzLeHjBlU4P8XZlsJrZKDtJ1Fmr/uqhNz/Lpwe+OR7wMngJD/d+gzQFCD90Wbc+QpJGQNIW2Fh+shzZxF4Mg7mZ0yDL/LwzEQBHkMS4EeSclammJ03/84EVes7W7+L3g2CD7p7UnFXG6cCl8UQ0oLwNRxhcyJZ6eStKI0xqw8ASyv2nmCwnTILe6I+7E+86EMc1Ki46ZKR/IeOvx9bWwfKywqcB6VWy2UUnIIDfLvgnp0vVuhOMLOO65WuSMMof7h1YP+E2TXALkuYZN8G/YzgmZ8zFjImqTv1+AZmlHyUqsmtINwzIo7M2qYr3O+IpMH2OtO9bP3prPsuRl1uHi+EoC/ze1Kpnei1RtkdMP8QAT//Kzc3Chui1UQ3BTQlmLqEvZ3NoKw1+oXKIAMKLlKVJqrKI5X7KSAzIPdiNS5VZvKKKUHO4dTJ6DRqWRN60fXOl0qn30h0waYWayLfEDp7YBDw/jxmEUt89Xj8Qy7q751wW7BRYCl6y0GIy53geueu/cigVOAqw2mR/iTSiaNoEjfoue9eFnBTJmt7yuQhWPyjSnOmZgXewJ2U61m4y+fEo5zdJEYmFjKQNLa7lQhrDVC1wzR02lRzxkr7YZcqzdoNpOarkYPZZVRHozWxGSS/LKdPNK1kEJfhiXhbuwc0D1cRdxunWa1Lnel8GT5MdKr14J49dBJPotKeZtfUgLdNIpARiUt3nElk3uCDs4s5AeAw8fGyfJXF97BFBI4Xho3LoKEQoJwZmaKNUK6RVvqVQX1oG7W+KkMrtpBXhJxP37b0T4DQJc6atsN9LSY2exRK7qnNRa92KJfocw6ReTweGoGTD0611z+dYFRyQ/9Kqwy X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: a0c8b2fd-2063-4653-c96a-08d931a9f215 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:07:03.2474 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PibeUNrj9TMzsfO/AVK94/jV92Ug8bI8tlPdwBkazG6BqPVBXM/v8MhHwbOnklzG8uQU7SdTlw77BS2AMOa4Dg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB0978 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.c | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.c -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.c b/drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.c new file mode 100644 index 000000000000..8ac8f7f8c644 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: MIT +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#include "wrs/wrs_ap.h" + +static void cl_wrs_ap_set_bitmap(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db) +{ + u8 mcs, bw, nss, rate_idx; + + memset(wrs_db->ap_supported_rates, 0, sizeof(wrs_db->ap_supported_rates)); + + for (bw = cl_hw->conf->ci_wrs_min_bw; bw <= wrs_db->max_cap.bw; bw++) + for (nss = 0; nss <= wrs_db->max_cap.nss; nss++) + for (mcs = 0; mcs <= wrs_db->max_cap.mcs; mcs++) { + rate_idx = mcs + (nss * WRS_MCS_MAX); + wrs_db->ap_supported_rates[bw] |= BIT(rate_idx); + } +} + +static void cl_wrs_ap_capab_print(struct cl_hw *cl_hw) +{ + struct cl_wrs_db *wrs_db = &cl_hw->wrs_db; + struct cl_wrs_rate *max_cap = &wrs_db->max_cap; + u8 bw_mhz = BW_TO_MHZ(max_cap->bw); + + pr_debug("\n"); + pr_debug("AP max capabilities\n"); + pr_debug("-------------------\n"); + pr_debug("Band : %ug\n", cl_hw->conf->ci_band_num); + pr_debug("Mode : %s\n", WRS_MODE_STR(wrs_db->mode)); + pr_debug("BW : %uMHz\n", bw_mhz); + pr_debug("NSS : %u\n", max_cap->nss); + pr_debug("MCS : %u\n", max_cap->mcs); + pr_debug("GI : %u\n", max_cap->gi); +} + +void cl_wrs_ap_capab_set(struct cl_hw *cl_hw) +{ + struct cl_wrs_db *wrs_db = &cl_hw->wrs_db; + struct cl_wrs_rate *max_cap = &wrs_db->max_cap; + u8 conf_bw = cl_hw->conf->ce_channel_bandwidth; + u8 conf_nss = cl_hw->conf->ce_tx_nss - 1; + u8 conf_gi = cl_hw->conf->ha_short_guard_interval; + + switch (cl_hw->conf->ce_wireless_mode) { + case WIRELESS_MODE_HE: + case WIRELESS_MODE_HT_VHT_HE: + wrs_db->mode = WRS_MODE_HE; + max_cap->bw = conf_bw; + max_cap->nss = conf_nss; + max_cap->mcs = WRS_MCS_11; + max_cap->gi = conf_gi ? WRS_GI_VSHORT : 0; + break; + case WIRELESS_MODE_HT_VHT: + wrs_db->mode = WRS_MODE_VHT; + max_cap->bw = conf_bw; + max_cap->nss = conf_nss; + max_cap->mcs = WRS_MCS_9; + max_cap->gi = conf_gi ? WRS_GI_SHORT : 0; + break; + case WIRELESS_MODE_HT: + wrs_db->mode = WRS_MODE_HT; + max_cap->bw = min_t(u8, conf_bw, CHNL_BW_80); + max_cap->nss = conf_nss; + max_cap->mcs = WRS_MCS_7; + max_cap->gi = conf_gi ? WRS_GI_SHORT : 0; + break; + case WIRELESS_MODE_LEGACY: + default: + if (cl_hw->conf->ha_hw_mode == HW_MODE_B) { + wrs_db->mode = WRS_MODE_CCK; + max_cap->mcs = WRS_MCS_3; + } else { + wrs_db->mode = WRS_MODE_OFDM; + max_cap->mcs = WRS_MCS_7; + } + + max_cap->bw = CHNL_BW_20; + max_cap->nss = 0; + max_cap->gi = 0; + break; + } + + if (cl_hw->conf->ci_wrs_max_bw < max_cap->bw) { + max_cap->bw = cl_hw->conf->ci_wrs_max_bw; + pr_debug("[WRS] Max BW limited to %uMHz\n", BW_TO_MHZ(max_cap->bw)); + } + + cl_wrs_ap_set_bitmap(cl_hw, wrs_db); + + cl_wrs_ap_capab_print(cl_hw); +} + +void cl_wrs_ap_capab_modify_bw(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, u8 max_bw) +{ + wrs_db->max_cap.bw = max_bw; + + cl_wrs_ap_set_bitmap(cl_hw, wrs_db); +} From patchwork Thu Jun 17 16:02:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A408C2B9F4 for ; Thu, 17 Jun 2021 16:09:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 550026141F for ; Thu, 17 Jun 2021 16:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232422AbhFQQLz (ORCPT ); Thu, 17 Jun 2021 12:11:55 -0400 Received: from mail-db8eur05on2086.outbound.protection.outlook.com ([40.107.20.86]:16332 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231422AbhFQQKm (ORCPT ); Thu, 17 Jun 2021 12:10:42 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XUSjieThwToc1cP3qADyBFWSn6SJb/PrMBfwvCOCMVNJFAhepayBjFAgvuzY5K+EZPRzbs3q7ZEezbPUaO1BoGu/+p3TItfnP0Vtyogmqiw9GW+mttQZbXuCStHMV9/OSTKQhlizbuDHiQp0XsxSv72uHKRZgeFoi4X3wxTznzP5GeOvkr1GCyF3tY9O1umnFB6tQmH80RUNf3CPe7QAnpMoG/Q3HBJ8RVPoFGNj8gQMysQuv6k9/bDMB4qWLBZ9E8QfJXHl5D8RD5A59/o4BxOL9IuFcIZPrBw2ToTbl+llUeQU6OWvjJorMDUtje5W1KzrpGFWO5MfLlj3w77jXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W7tPEW+ikQB2FDc2cXVMiynz6jWjngko8lAjq2ToarQ=; b=VITyI6wRLaencpTwlpdAzeOUOYsWoNuhY8wT0NJNHTEAP+PF462JtZUAwQf//D6uBNVi8b1P4SFguZEV27WSCUTgnqtaRcleR1n7pNYCNWY9hAgPdpD5Q8NW4gwqCob2QXfsb/5LjZ7kEfg9UUgaSnurxevcf9JyJucANMiPDA7ZyiOPwfP0jWD227lDwkT5oyyNBGqMS8NAXLP2LLPn/KpaX6yol2Rus6ed0ZL2k4TV36K5nmFhi8GnW8pu6pZVQHVmv+857SPZkw+6+z9eBdY9cBmX9NblHn5bua/J9JlYgjzQCLmoFQGwHu9Nl6V4foLHmH8vvQ0v1pylRJGVow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W7tPEW+ikQB2FDc2cXVMiynz6jWjngko8lAjq2ToarQ=; b=2oa7lBvMOfg1MmLvrRkUiPv3D4FAGTRjqDH2A3TIZJZxvSKo1gMFUKYPq1XYofJPz19kpl2Mls1orf7Fco/Fh7HoG9IliXBPepMIEGTUCmcbB2H7VH1eWwwn4MQN6PWZrUFKYEKZLp4XpVQfoZJHL8tSjuMTSVLhNFoIgcJrDIY= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1014.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fc::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:08:32 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:32 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.h new file mode 100644 index 000000000000..a01e9b46bf68 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_ap.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_AP_H +#define CL_WRS_AP_H + +#include "wrs/wrs_db.h" +#include "hw.h" + +void cl_wrs_ap_capab_set(struct cl_hw *cl_hw); +void cl_wrs_ap_capab_modify_bw(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, u8 max_bw); + +#endif /* CL_WRS_AP_H */ From patchwork Thu Jun 17 16:02:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F25ABC2B9F4 for ; Thu, 17 Jun 2021 16:10:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE3F561426 for ; Thu, 17 Jun 2021 16:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233669AbhFQQM1 (ORCPT ); Thu, 17 Jun 2021 12:12:27 -0400 Received: from mail-db8eur05on2051.outbound.protection.outlook.com ([40.107.20.51]:48736 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233943AbhFQQLX (ORCPT ); Thu, 17 Jun 2021 12:11:23 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=USBg7fj6eqDy56dm/6jqlFMobtJMcGkxjUPhA6i5gFivfBmm22iRTzSJaLj/IsbFPQnAWZB3lHPktigh95I80TaxHVtuNmb4NRmeaLSsDXrnZAS5MwT31ZTkiGtZaSuchfCGMq3JEcmLj8pDd22KMoXR8haSUwOfajr949rYkv76SAypxwNw87BZ2UYyPkKmMVzLWgRjVuAR9cC5tgRlqpPCLOTMoa5e6Na2i9Wz6aDt5ek4YVddI1bpJSO/lHPeq+N7vAJzxB8aRvNwrG/L0wLJ0vdjsjU2H59z3oQ++2Zk4nqZHhk3HIqcX0S3twApywaKaKAxXjOOfC0uoDuj9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GG08x7DVOj4aEC7A63/3ufvNtczDFQzg/w/HBu55rEA=; b=JU1X8k7IMPuGJ5m6uvLo3L1UiwQVgsWF+XxOb7yP/glCoei/42mjETxYl+NO5Jbu+XDwswLDCf/6dcVF/BvJ/lAC+1Yip507uXmbd8ol6GjJX1bgG0nzN++zHigbo8o/ngg3/UNMI8aWUF1BXn+rC3awLStMbDEsCJNUBzb8a9Htr3ieJv0CrqnNdpBm9ZjewDT5VwfpSqztBvwbajGyP1KlNHzZYoF0XzysNJ8HoIjtr7hZKjIK/w78vt0ss1Vh48doC9aQZ1tqW/Bb9E6OSxShgZqe0hQDBLWGQn7/HbfGZ7cdHzzbZOkIhfj/FUAmMVcLwUkCkQXsgRG+xjD/UA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GG08x7DVOj4aEC7A63/3ufvNtczDFQzg/w/HBu55rEA=; b=HFlT+7d10m+lnNK6xrxX4i65slEpj1pneJgR24Gt648oaEWIC5QK4Dzl0W43HFQd1+RZCIGPgojdxUPvsea7qlRDEhS2IfyA3wV6pcaYYvduxAcosca6QJRZ1o2xM+dyxRbYQeztrRinz8qCjHR0hrsn2jWe8fhRMeBMEFPulJE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM8P192MB0978.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1e9::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16; Thu, 17 Jun 2021 16:08:33 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:33 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/wrs/wrs_api.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_api.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_api.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_api.h new file mode 100644 index 000000000000..016d606633a0 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_api.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_API_H +#define CL_WRS_API_H + +#include "hw.h" +#include "vif.h" + +/* Driver --> WRS */ +void cl_wrs_api_init(struct cl_hw *cl_hw); +void cl_wrs_api_close(struct cl_hw *cl_hw); +void cl_wrs_api_sta_add(struct cl_hw *cl_hw, struct ieee80211_sta *sta); +void cl_wrs_api_sta_remove(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +void cl_wrs_api_bss_set_bw(struct cl_hw *cl_hw, u8 bw); +void cl_wrs_api_bw_changed(struct cl_hw *cl_hw, struct ieee80211_sta *sta, u8 bw); +void cl_wrs_api_nss_changed(struct cl_hw *cl_hw, struct ieee80211_sta *sta, u8 nss); +void cl_wrs_api_recovery(struct cl_hw *cl_hw); +void cl_wrs_api_beamforming_sync(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +void cl_wrs_api_quick_down_check(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_wrs_params *wrs_params); +void cl_wrs_api_rate_sync(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_wrs_params *wrs_params); +bool cl_wrs_api_up_mcs1(struct cl_hw *cl_hw, struct cl_sta *cl_sta, + struct cl_wrs_params *wrs_params); +void cl_wrs_api_set_smps_mode(struct cl_hw *cl_hw, struct ieee80211_sta *sta, const u8 bw); +u16 cl_wrs_api_get_sta_data_rate(struct cl_sta *cl_sta); +int cl_wrs_api_cli(struct cl_hw *cl_hw, struct cl_vif *cl_vif, struct cli_params *cli_params); + +#endif /* CL_WRS_API_H */ From patchwork Thu Jun 17 16:02:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ED54C2B9F4 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/wrs/wrs_cli.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_cli.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_cli.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_cli.h new file mode 100644 index 000000000000..7c7cbd9177fa --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_cli.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_CLI_H +#define CL_WRS_CLI_H + +#include "wrs/wrs_db.h" +#include "hw.h" + +int cl_wrs_cli(struct cl_hw *cl_hw, struct cl_vif *cl_vif, struct cli_params *cli_params); + +#endif /* CL_WRS_CLI_H */ From patchwork Thu Jun 17 16:02:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACC41C2B9F4 for ; Thu, 17 Jun 2021 16:11:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95E5F6141F for ; Thu, 17 Jun 2021 16:11:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232180AbhFQQNM (ORCPT ); Thu, 17 Jun 2021 12:13:12 -0400 Received: from mail-db8eur05on2058.outbound.protection.outlook.com ([40.107.20.58]:36864 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233781AbhFQQL7 (ORCPT ); Thu, 17 Jun 2021 12:11:59 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kt1FSoY7daiI6LKREicrclJVQtOKphK38yBIAQMnZaGGhnNJRg8k8BHIHFzkwAixmw2ylGhFh6bbh5m8SX4viDswWMYk74dwSLVUaD9hebdaQPnie9+FGjYjahNleqmNYMFjgMICu4iI2OaRZhTUkqU/KGY0W8h0n9rtMnoZda6uFr9UF7KraGv/AJqgI13PhIaJRaFSJYUx9jPvnwb6pHwGba51whZIl3BmipThWtwx0XSdPvwmT6aD9kvGMzWdN2AP/8mUAlrYMT/b1rBGNgimOvk1bzzC3I8s56S2e9J/bxza0mGg8Uw+fNxDcEx5reUStZENs92FLQN3mMWseg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EvTMS/5/SxHTkFZ93yvrieO7ZTesUdv0to0lY4ZohGs=; b=W2unwqNqx+PzGhHdFZLrBWBRnh+dFsZ+3nJjVnfPq7xPkZkDF9+30pMP6Vy6dqDCX1uYvD/wschoogPAvBqYugrXZ4vfn5zMiXIsHBtlpbFec7Lo0FyvKZnFgHSF5vruNrz4HKS7lyAL2t/G2lAYhV2E+5urwnk9/F19bHEM9a86Mj24KjWuVT6QePy+p/j4F1LZOqx2YPpWVP/bUT7ZkTxc8DWQqsP8z6OWOhQJpiNaNe7GVTQ/herwBEE0RdXfvPf3sIhApLuZEyoA1cekvMc6N+Hy7q3riH6tzKBFt5Oy+87MKC1a2rVygazuXIWGN1om10vuW12HkcSzB2cEgw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EvTMS/5/SxHTkFZ93yvrieO7ZTesUdv0to0lY4ZohGs=; b=kV836SW4LDA9kL7mA7u4ltvJh1wtTt+px8nx2ubUONUSi3KUGbd5MNjQOFw4jY+jHfGwxYf9j9Ps7sjW7ETTDXNwkWpUGc5eKGNl+SeHTDIXA99YjvbtGoZWGNZeANHZr8fqnm+h24CwURXlMe2z2xr7besFDZ7tmHSaqrCihKk= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM8P192MB0978.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1e9::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16; Thu, 17 Jun 2021 16:08:34 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:34 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/wrs/wrs_db.h | 386 ++++++++++++++++++ 1 file changed, 386 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_db.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_db.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_db.h new file mode 100644 index 000000000000..2eefa0abaf8d --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_db.h @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_DB_H +#define CL_WRS_DB_H + +#include "debug.h" +#include "utils/timer.h" +#include "def.h" +#include "wrs/wrs_tables.h" + +#define WRS_MAINTENANCE_PERIOD_MS 40 +#define WRS_DATA_RATE_FACTOR 10 +#define WRS_RSSI_PROTECT_UP_THR 10 +#define WRS_RSSI_PROTECT_DN_THR 10 +#define WRS_MIN_FRAMES_FOR_DECISION 15 +#define WRS_EPR_FACTOR 105 +#define WRS_CONVERGE_IDLE_PACKET_TH 5 +#define WRS_CONVERGE_IDLE_INTERVAL_RESET 6000 /* 6 sec */ +#define WRS_CONVERGE_IDLE_INTERVAL_RSSI 2000 /* 2 sec */ +#define WRS_CONVERGE_TRFC_INTERVAL_STATIC 30000 /* 30 sec */ +#define WRS_CONVERGE_TRFC_INTERVAL_MOTION 1000 /* 1 sec */ +#define WRS_IMMEDIATE_DROP_EPR_FACTOR 70 /* 70% */ +#define WRS_IMMEDIATE_DROP_MAX_IN_ROW U32_MAX +#define WRS_SYNC_MIN_ATTEMPTS 4 +#define WRS_SYNC_TIMEOUT 1000 /* 1 sec */ +#define WRS_QUICK_UP_BA_THR 5 +#define WRS_QUICK_UP_INTERVAL_MS 1000 +#define WRS_QUICK_DOWN_EPR_FACTOR 85 +#define WRS_QUICK_DOWN_AGG_THR 3 +#define WRS_QUICK_DOWN_PKT_THR 60 +#define WRS_RSSI_PROTECT_SHIFT 7 +#define WRS_RSSI_PROTECT_BUF_SZ_OLD BIT(WRS_RSSI_PROTECT_SHIFT) /* 2 ^ 7 = 128 */ +#define WRS_RSSI_PROTECT_BUF_SZ_NEW 3 +#define WRS_BA_NOT_RCV_TIME_SINCE_SYNC 1000 +#define WRS_CCA_PERIOD_MS 1000 +#define WRS_CCA_PRIMARY_SHIFT 7 +#define WRS_CCA_PRIMARY_FACTOR 160 /* 160 / 2^7 = 1.25 = 25% */ + +enum cl_wrs_rssi_prot_mode { + WRS_RSSI_PROT_MODE_RSSI, /* Up/down based on rssi */ + WRS_RSSI_PROT_MODE_NEIGHBOR, /* Up/down based on neighbors */ + + WRS_RSSI_PROTECT_MODE_MAX +}; + +enum cl_wrs_fixed_rate { + WRS_AUTO_RATE, + WRS_FIXED_FALLBACK_EN, + WRS_FIXED_FALLBACK_DIS, + + WRS_FIXED_RATE_MAX +}; + +enum cl_wrs_fixed_param { + WRS_FIXED_PARAM_MODE, + WRS_FIXED_PARAM_BW, + WRS_FIXED_PARAM_NSS, + WRS_FIXED_PARAM_MCS, + WRS_FIXED_PARAM_GI, + + WRS_FIXED_PARAM_MAX +}; + +#define FIXED_RATE_STR(x) \ + (((x) == WRS_AUTO_RATE) ? "auto rate" : \ + (((x) == WRS_FIXED_FALLBACK_EN) ? "fixed rate (fallbacks enabled)" : \ + "fixed rate (fallbacks disabled)")) + +enum cl_wrs_decision { + WRS_DECISION_NONE, + WRS_DECISION_SAME, + WRS_DECISION_UP, + WRS_DECISION_UP_QUICK, + WRS_DECISION_UP_RSSI, + WRS_DECISION_UP_MCS1, + WRS_DECISION_DOWN, + WRS_DECISION_DOWN_RSSI, + WRS_DECISION_DOWN_IMMEDIATE, + WRS_DECISION_DOWN_QUICK, + WRS_DECISION_DOWN_NO_SYNC, + WRS_DECISION_RSSI_MGMT, + + WRS_DECISION_MAX, +}; + +enum cl_wrs_mcs { + WRS_MCS_0, + WRS_MCS_1, + WRS_MCS_2, + WRS_MCS_3, + WRS_MCS_4, + WRS_MCS_5, + WRS_MCS_6, + WRS_MCS_7, + WRS_MCS_8, + WRS_MCS_9, + WRS_MCS_10, + WRS_MCS_11, + WRS_MCS_MAX, +}; + +#define WRS_MCS_MAX_CCK WRS_MCS_4 +#define WRS_MCS_MAX_OFDM WRS_MCS_8 +#define WRS_MCS_MAX_HT WRS_MCS_8 +#define WRS_MCS_MAX_VHT WRS_MCS_10 +#define WRS_MCS_MAX_HE WRS_MCS_MAX + +enum cl_wrs_ss { + WRS_SS_1, + WRS_SS_2, + WRS_SS_3, + WRS_SS_4, + + WRS_SS_MAX +}; + +enum cl_wrs_gi { + WRS_GI_LONG, + WRS_GI_SHORT, + WRS_GI_VSHORT, + + WRS_GI_MAX +}; + +#define WRS_GI_MAX_HT WRS_GI_VSHORT +#define WRS_GI_MAX_VHT WRS_GI_VSHORT +#define WRS_GI_MAX_HE WRS_GI_MAX + +enum cl_wrs_ltf { + LTF_X1, + LTF_X2, + LTF_X4, + LTF_MAX +}; + +enum cl_wrs_converge_mode { + WRS_CONVERGE_MODE_RESET, + WRS_CONVERGE_MODE_RSSI, + + WRS_CONVERGE_MODE_MAX, +}; + +enum cl_wrs_mode { + WRS_MODE_CCK, + WRS_MODE_OFDM, + WRS_MODE_HT, + WRS_MODE_VHT, + WRS_MODE_HE, + + WRS_MODE_MAX, +}; + +#define wrs_pr(wrs_db, level, ...) \ + do { \ + if ((level) <= (wrs_db)->debug_level) \ + pr_debug(__VA_ARGS__); \ + } while (0) + +#define wrs_pr_verbose(wrs_db, ...) wrs_pr(wrs_db, DBG_LVL_VERBOSE, ##__VA_ARGS__) +#define wrs_pr_err(wrs_db, ...) wrs_pr(wrs_db, DBG_LVL_ERROR, ##__VA_ARGS__) +#define wrs_pr_warn(wrs_db, ...) wrs_pr(wrs_db, DBG_LVL_WARNING, ##__VA_ARGS__) +#define wrs_pr_trace(wrs_db, ...) wrs_pr(wrs_db, DBG_LVL_TRACE, ##__VA_ARGS__) +#define wrs_pr_info(wrs_db, ...) wrs_pr(wrs_db, DBG_LVL_INFO, ##__VA_ARGS__) + +/* m MUST be power of 2 ! */ +#define WRS_INC_POW2(c, m) (((c) + 1) & ((m) - 1)) + +#define WRS_INC(c, m) \ + do { \ + (c)++; \ + if ((c) == (m)) \ + (c) = 0; \ + } while (0) + +#define WRS_IS_DECISION_UP(decision) \ + (((decision) >= WRS_DECISION_UP) && ((decision) <= WRS_DECISION_UP_MCS1)) +#define WRS_IS_DECISION_DOWN(decision) \ + (((decision) >= WRS_DECISION_DOWN) && ((decision) <= WRS_DECISION_DOWN_NO_SYNC)) + +#define WRS_DECISION_STR(decision) ( \ + (decision) == WRS_DECISION_NONE ? "NONE" : \ + (decision) == WRS_DECISION_SAME ? "SAME" : \ + (decision) == WRS_DECISION_UP ? "UP" : \ + (decision) == WRS_DECISION_UP_QUICK ? "UP QUICK" : \ + (decision) == WRS_DECISION_UP_RSSI ? "UP RSSI" : \ + (decision) == WRS_DECISION_UP_MCS1 ? "UP MCS1" : \ + (decision) == WRS_DECISION_DOWN ? "DOWN" : \ + (decision) == WRS_DECISION_DOWN_RSSI ? "DOWN RSSI" : \ + (decision) == WRS_DECISION_DOWN_IMMEDIATE ? "DOWN IMMEDIATE" : \ + (decision) == WRS_DECISION_DOWN_QUICK ? "DOWN QUICK" : \ + (decision) == WRS_DECISION_DOWN_NO_SYNC ? "DOWN NO_SYNC" : \ + (decision) == WRS_DECISION_RSSI_MGMT ? "RSSI MGMT" : \ + "ERROR") + +#define WRS_MODE_STR(mode) ( \ + (mode) == WRS_MODE_CCK ? "CCK" : \ + (mode) == WRS_MODE_OFDM ? "OFDM" : \ + (mode) == WRS_MODE_HT ? "HT" : \ + (mode) == WRS_MODE_VHT ? "VHT" : \ + (mode) == WRS_MODE_HE ? "HE" : \ + "ERR") + +#define WRS_CONVERGE_MODE_STR(mode) \ + ((mode) == WRS_CONVERGE_MODE_RESET ? "RESET" : "RSSI") + +#define WRS_BW_STR(bw) ( \ + (bw) == CHNL_BW_20 ? "20" : \ + (bw) == CHNL_BW_40 ? "40" : \ + (bw) == CHNL_BW_80 ? "80" : \ + (bw) == CHNL_BW_160 ? "160" : \ + "ERR") + +#define WRS_GI_STR(gi) ( \ + (gi) == WRS_GI_LONG ? "Long" : \ + (gi) == WRS_GI_SHORT ? "Short" : \ + (gi) == WRS_GI_VSHORT ? "VeryShort" : \ + "ERROR") + +struct cl_wrs_tx_cntrs { + u64 epr_acc; + u32 total; + u32 fail; + u32 ba_not_rcv; + u32 ba_not_rcv_consecutive; +}; + +struct cl_wrs_tx_params { + u16 mode : 3, /* Mode - 0 = CCK, 1 = OFDM, 2 = HT, 3 = VHT, 4 = HE. */ + gi : 2, /* GI - O = Long, 1 = Short, 2 = Very short. */ + bw : 2, /* Bandwidth - 0 = 20M, 1 = 40M, 2 = 80M, 3 = 160M. */ + nss : 3, /* Spatial Streams - 0 = 1SS, 1 = 2SS, .. 7 = 8SS. */ + mcs : 4, /* MCS - CCK (0 - 3), OFDM/HT (0 - 7), VHT (0 - 9), HE (0 - 11). */ + fallback_en : 1, + is_fixed : 1; +}; + +struct cl_wrs_logger { + unsigned long timestamp; + u16 rate_idx; + u32 success; + u32 fail; + u32 ba_not_rcv; + u16 down_rate_idx; + u16 up_rate_idx; + u16 curr_epr; + u16 down_epr; + u16 down_epr_factorized; + u16 penalty; + u16 up_time; + enum cl_wrs_decision decision; + u16 new_rate_idx; +}; + +struct cl_wrs_per_stats { + struct list_head list; + u8 mcs; + u8 bw; + u8 nss; + u8 gi; + u32 frames_total; + u32 frames_failed; + u64 epr_acc; +}; + +struct cl_wrs_rssi_prot_db { + s8 samples_old[WRS_RSSI_PROTECT_BUF_SZ_OLD]; + s8 samples_new[WRS_RSSI_PROTECT_BUF_SZ_NEW]; + u8 curr_idx_old; + u8 curr_idx_new; + s32 sum; +}; + +struct cl_wrs_params { + u8 is_fixed_rate : 2, + quick_up_check : 1, + rsv : 5; + u32 up_same_time_cnt; + u32 down_time_cnt; + enum cl_wrs_converge_mode converge_mode; + u32 converge_time_idle; + u32 converge_time_trfc; + u16 data_rate; + u16 rate_idx; + struct cl_wrs_table *table; + u16 table_size; + u16 penalty_decision_dn; + struct cl_wrs_tx_params tx_params; + enum cl_wrs_decision last_decision; + u32 decision_cnt[WRS_DECISION_MAX]; + struct list_head list_rates; + u32 frames_total; + u32 fail_total; + u32 ba_not_rcv_total; + u64 epr_acc; + bool calc_ba_not_rcv; + bool sync; + unsigned long sync_timestamp; + unsigned long no_sync_timestamp; + u32 immediate_drop_cntr; + u32 immediate_drop_ignore; +}; + +struct cl_wrs_sta { + u8 sta_idx; + bool smps_enable; + u8 assoc_bw; + u8 gi_cap[CHNL_BW_MAX]; + u64 supported_rates[CHNL_BW_MAX]; + enum cl_wrs_mode mode; + struct cl_wrs_rate max_rate_cap; + struct cl_wrs_rssi_prot_db rssi_prot_db; + struct cl_wrs_params su_params; +}; + +struct cl_wrs_db { + /* General */ + spinlock_t lock; + enum cl_dbg_level debug_level; + /* Timer */ + struct cl_timer timer_maintenance; + u32 interval; + /* Fixed rate */ + u8 is_fixed_rate; + /* Conservative initial rate */ + bool conservative_mcs_noisy_env; + bool conservative_nss_noisy_env; + /* Immediate drop */ + bool immediate_drop_en; + u8 immediate_drop_epr_factor; + u32 immediate_drop_max_in_row; + /* Converge idle */ + bool converge_idle_en; + u32 converge_idle_interval_reset; + u32 converge_idle_interval_rssi; + u32 converge_idle_packet_th; + /* Converge traffic */ + bool converge_trfc_en; + u32 converge_trfc_interval_static; + u32 converge_trfc_interval_motion; + /* Supported rates */ + u8 mode; + u64 ap_supported_rates[CHNL_BW_MAX]; /* Bit array for each bw */ + struct cl_wrs_rate max_cap; + /* RSSI protect */ + bool rssi_protect_en; + u8 rssi_protect_mode; + s8 rssi_protect_up_thr; + s8 rssi_protect_dn_thr; + /* Time + step thresholds */ + u16 time_th_min; + u16 time_th_max_up; + u16 time_th_max_down; + u16 step_down; + u16 step_up_same; + /* Quick up */ + bool quick_up_en; + u8 quick_up_ba_thr; + u16 quick_up_interval; + /* Quick down */ + bool quick_down_en; + u8 quick_down_epr_factor; + u8 quick_down_agg_thr; + u16 quick_down_pkt_thr; + /* BA not received */ + bool ba_not_rcv_collision_filter; + bool ba_not_rcv_force; + u32 ba_not_rcv_time_since_sync; + /* Sync */ + u16 sync_timeout; + u8 sync_min_attempts; + /* CCA counters */ + unsigned long cca_timestamp; + u32 cca_primary; + u32 cca_sec80; + u32 cca_sec40; + u32 cca_sec20; + bool adjacent_interference20; + bool adjacent_interference40; + bool adjacent_interference80; + /* All the rest */ + u32 min_frames_for_decision; + u8 epr_factor; +}; + +#endif /* CL_WRS_DB_H */ From patchwork Thu Jun 17 16:02:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AD42C49EA5 for ; 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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/wrs/wrs_rssi.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_rssi.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_rssi.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_rssi.h new file mode 100644 index 000000000000..2a7f64c88aa5 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_rssi.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_RSSI_H +#define CL_WRS_RSSI_H + +#include "hw.h" +#include "wrs/wrs_db.h" + +bool cl_wrs_rssi_set_rate(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta); + +void cl_wrs_rssi_prot_start(struct cl_hw *cl_hw, struct cl_sta *cl_sta); +bool cl_wrs_rssi_prot_decision(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, bool up_rate_valid, + u8 up_rate_idx, u8 down_rate_idx); +void cl_wrs_rssi_prot_dbg(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta); +void cl_wrs_rssi_prot_config(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + bool enable, bool mode, s32 rssi_up_thr, s32 rssi_dn_thr); + +#endif /* CL_WRS_RSSI_H */ From patchwork Thu Jun 17 16:02:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1553C48BE5 for ; Thu, 17 Jun 2021 16:13:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE62761059 for ; Thu, 17 Jun 2021 16:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232879AbhFQQOI (ORCPT ); Thu, 17 Jun 2021 12:14:08 -0400 Received: from mail-db8eur05on2058.outbound.protection.outlook.com ([40.107.20.58]:36864 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230217AbhFQQNC (ORCPT ); Thu, 17 Jun 2021 12:13:02 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=P6kiNRRbJvdfzMdFDL5FRsljgFiVAPIukLURWERrwBzpj4AX2DCcZnMZonHpQ+YGgHtRO7XXxS4vkrauk05ciUSnM21wmxmsJ7E8iBksNeNl4nuQE0w9QT9IV7PYiVagbOxvU+CMbJxV4C78h48XHrRDdPJzdRr2ithWGLVMyZYvkd63P5mLyU704TulXA5CFyzH2GBk1WpFSEQUWnakLnQjgRDXvKzYxAbdKtZkzotlAYCRaJYuOmieW5yCgXU+gZyye1NMRu5S0CJu7G9cFwFoKS7mGqHlSf6DTelDtDUGzY5+dfPGF6qvOMoaTqWFKD44XRuQ1zOojrGi4QASAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Rei7KdCF2VCadfU16T4RbQVJDr+hC1d+W6L5PGjkau0=; b=LhzA+Rh5KX1QkLNzGC5WYk3LxPrAEXwRGsAQYGnJyST6OPCFDIKX7xB9+EgQPPxYrY+KZ9cnxpEWSwHtZp4MPeKqk3V07zYsO64c+sTXOChFXd/BoDouLvjie7AFzJes6d/wv5gNPzK5ur8K6003s/hRbUhMPLzzZh5+qamCDW0xG5z8N38An4eAu0Qm74gfbqK3bbjoOBxvdpee26T/oDWbOHZCpI52u2T0EYEu+Z/cHTy8MN/4LYHLpMx1tMv06q9hLVYys32Z3Oz1OvwxGUBtXXcZIU2sJvPjiLojTzTteROsfRqxTLaSY6IFPdR8QCbtuUMVEEg2f1pZtwBPlQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Rei7KdCF2VCadfU16T4RbQVJDr+hC1d+W6L5PGjkau0=; b=0y26qD12s0Z93u1364qZ35eBubFn+kqQSxsQy57se6TPvT+dI3dvyyi+mpXC6iRXF0x4Lf4DGgP+PGruq1WhKmdYFQSsmANDhN07fMh53ROod0C8X3ldEn0IgdEcHEvyNA4uPi7YMR9JliY6YQK55e0w7NKWdbZpYtzH18ApMbE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM8P192MB0978.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1e9::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16; Thu, 17 Jun 2021 16:08:36 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:36 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 251/256] cl8k: add wrs/wrs_sta.h Date: Thu, 17 Jun 2021 16:02:18 +0000 Message-Id: <20210617160223.160998-252-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:07:14 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a1dcf2b1-4557-4b3a-d96c-08d931a9f92d X-MS-TrafficTypeDiagnostic: AM8P192MB0978: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YjU97uA87WBbFR3UBNx9HZEHWTCkKLXM6/yj+pSZ15K5ek+qFyX+zab9TOYFglyxTjJ9qbQrbshzYurMhAFS2YKAEWIoE8JpbuzVeLJwb2xJLwHZyq391ucVpMPYmLYC7Fac1OWLjT1xTGLlb+p6sOJ1kCixro3f2Rkubsa+wrUnouZsOtrUiKeJbIX2SjEqcnAyEq9hRrSjWEkmmKdXvnIffiLhnTleAKbscoE1j2xR/NndxvwDteWAOkISvGeNdrbgMea9kcBQhOOOFBsiVKbAlXkMIRzZ0Wek9unQFV9JDtvzp2wh3BK9PeQguCM5Km2NU/rudZ0lyVKmmS3D1G/VrKWGt83pUyyYwbnKOldQ6lOsmA8yaTwkI0Iz4RIzIY4T0SRgT6BqgMeQhKLWSBxseYas6/RhSY6z5Fau4Qy+0oHttYkG8WbiqzdGd0nv57A9kkUdMlr2Jo8OaBZbJUlzBTJP5Ir1UQQjXDkKO9P35+SQT/9rzsCKF+IepStCfHAZv/VNgF6BfcRKPkTfZceec5520reZsF9Bc+mYF0ZXZr+m+J7FTAQNV7wRHCkG9TvfweqR7fzEdKow6APSd+YHOEBqcFYrSOMrwMSQEVWmNkKUsHqsax1kBV25EEAIOiA0m432ztwciNcp09jqnCpLmQ+nUeoI/7qOTujlr8N8//OAMoDHTprcBFieXPBqKcrZ2RmNOPsc2RgpF3Ag2Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(346002)(136003)(396003)(376002)(39850400004)(366004)(16526019)(107886003)(5660300002)(66556008)(83380400001)(26005)(186003)(1076003)(2616005)(316002)(66476007)(66946007)(9686003)(2906002)(6512007)(8676002)(508600001)(52116002)(55236004)(6486002)(38350700002)(86362001)(38100700002)(6916009)(8936002)(6506007)(956004)(4326008)(54906003)(36756003)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +0dUeI4qkKw37pRRV3P2NmF05NrxCO8rQVwljiazVMWgb73rdg66NhJeR3CHVxXvrsEb06aXTGKoLu5s57oAU2SoHwl2+RF+XcijowR5YO3/QbDqb2PFAyoV+QeoaE7XYSjmuyxr0xfD33y15jiC71mFR4PO+uLdiD+YBQGNSDNJ0QL6WnUF1Gfm4u03OoARUqd+075AhcTbh1aszmI4D/n/M5CFDaAbJqoCxOwRfIi6+rSbnIPKK2tC79VAuH1K1ePMDt81G0ZHoXGXXjUwKirZ0FDpwIfxFF01txjZQbc2qZ2SgnqA4zyyZiSqHbrmNBNU1d7+2asYwdaW5jHu+57a4BjA24vo7KTQOrUF21WROla2ZkwZLkdtQmevYitys2pi+ngCq8MaFUGQ1hJNoQ2OA0ZHO8TOVA2NXioY52sRIekNTQQLWXKUw22mINbhY+uFr+3CsbSqf+KpePOo622Eh/ZHIIwM861rNOd6bcWQHABF95ZJ4RJEDOctmcVE7JYCaXl7GloP/SVo3aAnvXEDnE6hxvwSbR0+YYYo0tKskMGkJ5uOVCkxlO+mJEI4Af90NzV3irys+OUElm7QH865RZOyl5S71qr1DpYCkX1AxMK00f1l/5vYRYR9nYgavShWD1GPkyV4DtjMbqOg0E/CBvt4cnWDE2kUZ6OXLjAZ9nhDva7DcMLs6fjP9qez9vJGzKP8348ujNbjR1y4vM0MJr8EDYqJ+5nuU9U5ztjUSa3jOULXNu1B0ZorV6EUQ44rTmOnLswMNbV3WRBMxhtVhGJm98POoRqKxJMfX7xWgf/9bgT3Mtcw2/vm+QY5QehZjgkmL2TFFyvKUifGRxFR5fZ9lC2gx7zwRYTPM/UhcweQjGmGOLPaHlFenqa/UNEhd+dM+ywVo1tMSoWXxOVNBRXFwFLdB5PeUmwCveFGUtLxPwNxt0euL8yQNFZ/sBk5CPKs31pnWLV8VXpyta42wKzJvmZlEn+u1gtQaQDTllbjaG1TZw19FYTbMiSCtNWvsvKuifQi9t70Ay7VVJYlqw/u6v/3ifw+KCoOOulf6+O0w8HHEiyGC/r8SzjpfO4q6Q0NxKr/vjyHBE4BavVQFloJGoyo9cmJ9cOOKIqIoFWNNsxS7REa/twQ8kSg+jzn918iZ1WwLcmBrdUcaTsfqfYvh7UUUxhDGZzPokd7ZY+07b7ZYwbowi5vy5Wlj9Ye2GqCbxDo3YC8difnfVR8YF7ojHhK/puRgYWv36yjInZvffC5/xRvHx3WjwACiRO60QTTIfZm5K6iwTVbZGlNgeERkDBp++U3EujWVabheMJeVmablvad8W+0sxhN X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: a1dcf2b1-4557-4b3a-d96c-08d931a9f92d X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:07:15.0835 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vNXo5290GN0MY7Es+W24va8l50uRWoe6+3p0jVLG4e2KyAbccrtbmJf16qFMJT4f+iEvvOVToq6JabhqkCPkyQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8P192MB0978 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/wrs/wrs_sta.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_sta.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_sta.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_sta.h new file mode 100644 index 000000000000..a7a06f71c548 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_sta.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_STA_H +#define CL_WRS_STA_H + +#include "wrs/wrs_db.h" +#include "vif.h" +#include "hw.h" + +void cl_wrs_sta_add(struct cl_hw *cl_hw, struct ieee80211_sta *sta); +void cl_wrs_sta_remove(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, struct cl_sta *cl_sta); +struct cl_wrs_sta *cl_wrs_sta_get(struct cl_hw *cl_hw, u8 sta_idx); +void cl_wrs_sta_print_list(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db); +void cl_wrs_sta_select_first_rate(struct cl_hw *cl_hw, struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, struct cl_wrs_params *wrs_params); +void cl_wrs_sta_capabilities_set(struct cl_wrs_db *wrs_db, struct ieee80211_sta *sta); +void cl_wrs_sta_set_supported_rate(struct cl_wrs_sta *wrs_sta, u8 bw, u8 nss, u8 mcs); + +#endif /* CL_WRS_STA_H */ From patchwork Thu Jun 17 16:02:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48071C48BE5 for ; Thu, 17 Jun 2021 16:10:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 31AEF61428 for ; Thu, 17 Jun 2021 16:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232389AbhFQQMW (ORCPT ); Thu, 17 Jun 2021 12:12:22 -0400 Received: from mail-eopbgr80084.outbound.protection.outlook.com ([40.107.8.84]:36933 "EHLO EUR04-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233933AbhFQQLQ (ORCPT ); Thu, 17 Jun 2021 12:11:16 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EAB0dRzmN07j0OAb7vaW5VQmBDdQ3s0kec0CA5q81/jPbEqiB/vNWrgzQoQJJkqw3srlBIXas5RftGH4zaVoNUrv4wD63S55kerYffY1Bgt14uusEwjSHn0Efb6+8hU7V8EwlT1MVAwyuDP7j2gzYuYRCmyco5u25sO+Zy03KVZKfcv7UfwZC53HaqUM9ZeDgYAB+DooyboJM6hRZEW9gfXjV5yJCQtTcBFeLoWRpqImvm3MQqRQR2oSfVMs9m4OTvwaUPrHo4qQIdaUBJbG0vbU78r+kX/ya8uSw4huGh8LP9IRB9MQKToNSHAx9UqvGUrOoeFsSmadIqlAw+7Deg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+N5tuTY8MeA/SqUy4cLwcRZLrPtFaUfkWEYDrkKQ32s=; b=fY+hmtYOIp0bXrgiWi3AnUaWb9vowHnDaaTVanBmcdpeM/2S7fPcOkahZK64UDFEHuVzWr1W6AWpYR1NFUkrlHnSN4gwydQEL/p3LAFG8FnKQTWHnyEKt1o3Xe8qE51+3TrJ6PwlEJooToDKAnIOp4yZg3/ITqcIK6XKF1xBDPQJjf2CN/aIdpggkIw55l4KQWlscbxOiGTBfLFH3qSuBJEfZW0b/woD3Cn/9udub8Tq/DbjdHceAGvTY7Hr+C11JZd1i577T0IrHNqXRwGks/0vPUY0oW+E5NEw8bTiFtPnfV0mPOur3y1XYXH0gUVgvcct+ay76cBcHAqgVLclwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+N5tuTY8MeA/SqUy4cLwcRZLrPtFaUfkWEYDrkKQ32s=; b=yvSafP1eE1opsU4RI34W6Cv29XYjs0U/iwQwDobQLnBD9O8qkh8ML0fHuqrgFeKNj4hMTjJII4UyG+5ceYe9XDaMBZbwyn36+E6mupqcaKvYMvSr4lQ5EGIUO2awckq5gnlcFDa/3BDQNeDDw1qKBGnWGORyiDz1HRMwh02eCEE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1014.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fc::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:08:36 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:36 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 253/256] cl8k: add wrs/wrs_stats.h Date: Thu, 17 Jun 2021 16:02:20 +0000 Message-Id: <20210617160223.160998-254-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:07:16 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8873fd94-0db1-49a8-3d9b-08d931a9fa81 X-MS-TrafficTypeDiagnostic: AM9P192MB1014: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: glylfrWB11omQPG7Rm/nlBV7PWU3s2OFCspxt1ymbf00DnOPbnlK1b8K0BHXLJhKZDvb3Tf4J0XqGz0S+P/tHchWP4JBVuGOTSsD2f+t1ceL++ttZT6FCYhqwSf3WEMpHBRJo+NwTvbZmtx24PxxZaXa8WW5nFD7I40fA28QWxAYigGLFX9kCah/wLtwlqf3timseaMN27GOVaOC0O0tXbp54Zj9Ct9rqS6NnBxBQdACfHl2Sucv6IfADP1CoMPCXZ5bXwJbbz/wDYYUqukvcyG+ldLMpHk89eK1f3NWCJA9Bjg5F26YUzHUwC8fiPWdSwcYGslKwCpP1QtE3ebZAS2YQpF3Os4b3q61TQi89Xc8POFwbkgXW7IJ2XyJBSE7EKMY4Jk9cOpgo98szxrXhKzr7QbMXHj/Mancl/+gz0PZ3RQz90s04HmZ24HeFpFI6vvVYn8c89QWN867pdQipOwdUare2su8Fc1+LdL0KUhYm7GCqBCQ72u3XmYtKmZtO+ijUDOwu0yjgv+MwMl4Ecw7I0UleGhvvmgSYKleaj5NRKM6SBEZFdCtOFeZfDecGK1txZ/9XIBZ6NnWZVeKzMG/91AlqhZB+XYxL/dBlOHfrtykjvHecMbrr93qMCNVu36Tav845erCPOZpTuuudh+01roLBn7A8cXSwU4WbnQcooVGDhPvF0oYs9ozn6oiBJqcWg3ZA8kqkw88dLgsVw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(39850400004)(346002)(376002)(396003)(136003)(316002)(86362001)(66946007)(54906003)(4326008)(956004)(55236004)(66556008)(66476007)(508600001)(36756003)(8676002)(26005)(2616005)(6666004)(5660300002)(6506007)(107886003)(6916009)(83380400001)(2906002)(52116002)(1076003)(16526019)(38350700002)(38100700002)(6486002)(8936002)(186003)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pMf1EZXJw1Uv2fO6f5PAwI787GTBa9KmLc5ckMULobdSYvGfRhfwYzw17TvBgxA2AL0e5dYzfKQ4T0R1ZlBaErlEgawKWxOZcZCL0stM/FBjhLJgk3HLp4R6pYNnzPdrOs+3TCYN093FJQEhFTUb7N1IKw68uCV6VCO9JUdqyzCWgLYOH+QgxhWcHJVYjsqpDkFiM/YL2zc9a0d6tSx9KoG+BkgOcRhlTB3tS74WFd6s9Z5lvC1+ESvYw/fxFMrEl19vVNAAdTOU6VUedt1ymlBUjjRCFamCXbhgPBWWZglQEEj3mjGSX95veghVgy1j2dtXGIZejoNW5BAVaGUWcC3rI5+QWtMiR7vDxm1y8v9+u8swaYj0oxwI8EvFA3q0eIzXB3dVnlFODwFThKWTJ+btntxEUm7WXAg4gP8djo+lxnGwSW6Q05c7v/jPulHcTZ3x5CnOGkKuyhsrrFDnlNer+T4l9gK5Ws2IebzhXbKqffgSx40nGtFRJPcMahcJZHZ/dqN/5Aohb5Mvgl9CsHaYFLLD+9Jdi4ANXfEwLKTVudrZkVdR4JggjTaHNvi3xDQa/rVj8UhJtgFobTl/H2juED1dslDs0hMiWWvDfS/TgmQfpG97LWkCsneHnH/KuYaBTTRhPMOrh/8CwK/aB6uUgR4/YpnopNQ9YAwr91koFvCL0k7a3IAKmf7n0s9HWuRkdSEJoh+a/F84Z/Z0fYSAPynxwRC4dVG19wBfapU4bzoLvrnEnswGNx0BJ7qXwXxkQ+QNorhlB1AUepCyOb6AcBCwpMo68Lf0lKmMv7bK6Tq+NUycIuji627yMfe5eKX5mtGluSwb7uA6/TBY+rJygg6kQYBufTrPYOaQKfx5TxN/9kQf3A51Ky/0pCIJNNJGmKIoCppPFYYvz+6NV6hNibYX6VikEiRypK4LZXHM4/1vHh2h05lbt7Dpp7TEF0xJIjHPXZBygNLVkwn3GyGs762AO+XnJx/UMPfDskd991I+sroizLKFwk7LQAJ/4GRdsI9kRNcg2/Rpk/cGnmjZ8xDXqcZwML4sFiwieFfJ9u6crTexnH8ceuafbepdb8NJERZYGapjelVontHRCObu650VICNk8xjzNVXVcogqYTPLThvRqrgBnqkRUupwWLLhjmYpgu4Piw5qYU3xWx/bz8NmOFAh3GjgYypaAQJJcamBPArzqs3caAJGBibh7pvu5sNu2pBbREWWLm6e5BHLuyhf3zd/MVFtwNwrCWa26CgvV/tcnQy1KiVa0kW1xbt2D5qpiOXIrX/Z9YIOt81XmyX/j1CVo93kNG7MGGuZRUF9fnvVVfotixsjvWgR X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8873fd94-0db1-49a8-3d9b-08d931a9fa81 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:07:17.3296 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0v3XjDcGzO0+3Pq2cdSNdnBL7TlcmpVNrI1kFlCM8Jggd7dyHXo67T4BoEzBai/6HWVGncJrDmgrpXQ6nlRZ8g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1014 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/wrs/wrs_stats.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_stats.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_stats.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_stats.h new file mode 100644 index 000000000000..2af2c95bda80 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_stats.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_STATS_H +#define CL_WRS_STATS_H + +#include "wrs/wrs_db.h" + +struct cl_hw; + +void cl_wrs_stats_per_update(struct cl_wrs_db *wrs_db, + struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params, + struct cl_wrs_tx_cntrs *tx_cntrs); +void cl_wrs_stats_per_print(struct cl_hw *cl_hw, + struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params); +void cl_wrs_stats_per_reset(struct cl_wrs_params *wrs_params); +void cl_wrs_stats_per_init(struct cl_wrs_params *wrs_params); +void cl_wrs_stats_per_remove(struct cl_wrs_params *wrs_params); +void cl_wrs_stats_decision_print(struct cl_wrs_params *wrs_params); +void cl_wrs_stats_decision_reset(struct cl_wrs_params *wrs_params); + +#endif /* CL_WRS_STATS_H */ From patchwork Thu Jun 17 16:02:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viktor Barna X-Patchwork-Id: 462680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 428F6C48BE5 for ; Thu, 17 Jun 2021 16:10:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EB856141F for ; Thu, 17 Jun 2021 16:10:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232417AbhFQQMu (ORCPT ); Thu, 17 Jun 2021 12:12:50 -0400 Received: from mail-db8eur05on2083.outbound.protection.outlook.com ([40.107.20.83]:54592 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231196AbhFQQLq (ORCPT ); Thu, 17 Jun 2021 12:11:46 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QIg8U1JJF837EIACupFbGxbbICbV0QW5CxZIC8fZAwNza69fSWq7u14T0kHZv9SCo2lqVxrv9kntwyUfF5ss+7oj3KbLU37pm/PSYsuMyaBhoD7+jmMD280e2I06F156zxzsJUUBRTcFUL+yHCY4BEzHX9qRUvZO0jmx4bxA5GH4THKWk9JBYx0FTc/8G7fokc7kV2Zhq67sYQ5xdEajVZuU4BNlvChYHNNDCLcCa0nWNFn3cO29rpkEFzPwOE06y7K8dscMBUu5dXMPR8YpSukHxwAmm+Q/d51A5D2kGHvfqETgmzrAnk7jkS0dGvV+SwuAAhZDL1LFjoQmnaa1mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9HptxUT8lsxJVlBKSUc/uzT4Bxm30hRzP+5ZLopMe08=; b=QdPI3GaqXLerIuOfvnfyQuiHkNeofXQ+s67g/sBCloJneivN+uQop3vA1eYQrTdn+qEtIAzQNu34jxqYaz3nFspKP4BYv25UZ7DZibabSgkjDYrjTmzqSBQlpBenYAt2stHDzcJHfi1p76u8kDMdzerCfxMoDv6oP2KrCWrql/tUUDYqXQTMtUH3W31nbNY5/DyHWr3qZa2Q1Rz3h51hm6ulkBDjEKKHZHH4NqGYhRJ7kj9U67XInE9v4MNAV0DWLAWoc+QbGL6LV7UcsaVTXnAxFBomR0fx9A6EOIjRxup+UpyS1sOyQyCfLkqwRBhaI0wJbe6DjHbRSJG3TPeorA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=celeno.com; dmarc=pass action=none header.from=celeno.com; dkim=pass header.d=celeno.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=celeno.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9HptxUT8lsxJVlBKSUc/uzT4Bxm30hRzP+5ZLopMe08=; b=JqP38W8ss4uHrn7hobGLbQxoims/oUoE/5usK+Q6NQnnYVsY5UBQCvgYrgwa8EOHxCzPZZbJUCmhYGAO4b8oplLGZdF7xvI0Cp/Cozn2IZDxbBOTtnweTvJp0cEdljeW5Omkqdh/kV9HpdcUxjiCB5I8H/jFt0IfS0eia5g6BaI= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=celeno.com; Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) by AM9P192MB1014.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:1fc::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Thu, 17 Jun 2021 16:08:37 +0000 Received: from AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f]) by AM9P192MB1412.EURP192.PROD.OUTLOOK.COM ([fe80::1847:5583:4db7:102f%4]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 16:08:37 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 255/256] cl8k: add wrs/wrs_tables.h Date: Thu, 17 Jun 2021 16:02:22 +0000 Message-Id: <20210617160223.160998-256-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:07:19 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0acb7621-d6a9-4929-8d57-08d931a9fc11 X-MS-TrafficTypeDiagnostic: AM9P192MB1014: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:459; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bf2rY+inH4A2WHNpADYfsAxG838SNKyoVmpVBxqP3EYvtx4Al+Rm0F9g2HJxhcOMZBOL9QMeqJSTU/9INp2rOqfHj/cyu60xEO9CCvRh405fTIrq3cPidDJ52q2bAdMN2krLc+Ph+0Fopm91iYYp7CMJ/9tponj68q2hOm26Qhry1kdqWlrkH3Hp/J+FHnTLcYRBMDtqPY1YmlseOyiFEKMQ98E8lyTripU9mf7jWoU6js/yJXE8fpWxxp2phuzSGmSFBReGUZZiaoI43ukZ7j1ssln1ltibBnf/2t4DfrXw0zJ4aNDI4HEb/ItU54mPieRWz0DFsiVE0vSTyW+zCNB0TOGGqhN68VOykGoW8qImEn1JTfmq4m24mB9kV5f9Dz8Qgczl4WjYhNrgYvuFtu32DbKai5BZKBR9p8+Z2zYS7eLivgKqT6LgVJWYvyyMTtov2uLqDdVSiqJx4UtwqufTTvnnwUVGd1odbMNXfiW4D6d68AgbCKeYTn4RfiBYhlRQbyOqcWg4bSwVWKuAKsX5mWGLt9v51fus/m1V5FTXIn6IPDLYp76hAmy6jcmS8dI+mPm5VIYDJ16yNwOSJXDprkte4+cgewLEc7r4H+KjMOLgQzIY06UYmycf+1FatmyuHcOglNfK9ETfiOCp1kLnVzic8tM9BWNghX0GPzlysAgCyJqFwt/L9EQAMcQyXA9r8JLl6eEh7sXweKNBuw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(39850400004)(346002)(376002)(396003)(136003)(316002)(86362001)(66946007)(54906003)(4326008)(956004)(55236004)(66556008)(66476007)(508600001)(36756003)(8676002)(26005)(2616005)(6666004)(5660300002)(6506007)(107886003)(6916009)(83380400001)(2906002)(52116002)(1076003)(16526019)(38350700002)(38100700002)(6486002)(8936002)(186003)(9686003)(6512007)(69590400013)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nHIdfwpU05T3R3iGGj2QTrPsLxjb96astKArziWAFJun0NwZgMOk7BUO0Axm93dDDnDC/URymQJaCnwoCV836nzdMq44CqVlJUvzviMmspZ+BP0QIfnEKlVmSJsJs46tcDDfOP+wHIf5hmxjrUUibNE6NVtHnKaAmJJMylGtxtQenOgphQn7LSuz3cqWmVILPQcAdSDebKjgylr/Ek7oI9kWoFmXIMu6IO/DV0sm3cKbVDwy+rhAYy52UsGfROB9vmCpa7Zy2j48kyK9UUsNf4beSGl1wr1GQa6QRUHU/akQS6lgZbpmkJ6XI+6jdS+Oj+wESTJYvfArNQX8jGsGQjwHlqYzZVLNVnMRl9uHLkfbnW16INO4oA3PJhMtJ5Lo3CeLmo67OwHYsi4E/ymUfO2qE7Yfprza1w5qAU8MQbtZItDd+XmfPb1s/+0hLB8HqGNQKcY8Xsb4eA5Iujm3w/LcjzqcgVdl3N4dMcMDFQkf/lUaOTbNGinjcYdDIc6jfMa4lZAciVb2plQP7YGXGb6qPXmSAZGpQqySUCOKXW5nw8A6P9Bq/jV/fOW8zLeMzuDSoQJovMtzkM5Mh3vmCVDkS7MgqiVQaAyzUrZQg6pTMqj/K180vM0+hJmOT791gzSHS56fU1bUbXXJbEFG1X2IjGsAUQzR6wPsp4Uq69zkDONVC8tsfzr+LR5jX3nk0lOFUB8Vuldh3c426QbJ2bQYfL0CFnBZJJiMaXWFzyogJeiMxTjd8tWnl4EHDsiD8sGbATiKqHnHTGpea9dBc1qx2wAim7h2kW21E11mPGU1rmM1hnJ0IW88mik6H4RxhZcGv6HTpKLCh/IyLUNYe36rpVNoBEik1c1mH4/TQeXDuAVS/AArCGVvZc8657fvH+bVu48nNfxfyzxWnGwUQZJCNjrOVfc1asDCUJvQ0EDuUSfiNNO+BVZ70DOW+Zrz1watkKAz9Fwm21DkPuafwOQT1Due/dS/6atSaMW31lZkqjbAS24+1an7WL14jiUFIjxZR0NKkUd1kEeyqG7lWxXRY4iGkPIsWI+vMv0ABRvhut7bGyvNZ2Vl8jz78nz+/tP+66zBvju7B5OqDPiAC+/CNKZUnNnookalVE8EgOcS0cKfxex1etws+VuGJ/XfeOM/aKIuS1hY3klB5NIWG7ANk9zv17vaQM2pyQxXcddCOgXdI7qCFR6P805f8gP2EA52Ntr+8yKHhNdvncV4aOn9Lk8bFrZvnPbJB8pGW2KUweYAZZGn2JplgfgvhiR0fPZI43rnj2DElQetf1gvnhOxEbKt1YpIGqw7QQZX1AALJQbkoUOnE1X5LePNF4kM X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0acb7621-d6a9-4929-8d57-08d931a9fc11 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:07:19.9750 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JBwzQJ3a910liFBncVOeyacGMhXhjLW1ACa35/W33maO2xcGzAmXerNvtgbawWXCy9WiR8YbtpK8ba/nZqCOJw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1014 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- .../net/wireless/celeno/cl8k/wrs/wrs_tables.h | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/wrs/wrs_tables.h -- 2.30.0 diff --git a/drivers/net/wireless/celeno/cl8k/wrs/wrs_tables.h b/drivers/net/wireless/celeno/cl8k/wrs/wrs_tables.h new file mode 100644 index 000000000000..250755533f28 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/wrs/wrs_tables.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_WRS_TABLES_H +#define CL_WRS_TABLES_H + +#include + +/* Rate Table Size */ +#define WRS_HE_RATE_TABLE_SIZE (WRS_MCS_MAX_HE * WRS_SS_MAX * CHNL_BW_MAX * WRS_GI_MAX_HE) +#define WRS_HT_VHT_RATE_TABLE_SIZE (WRS_MCS_MAX_VHT * WRS_SS_MAX * CHNL_BW_MAX * WRS_GI_MAX_VHT) + +/* Initial Thresholds */ +#define WRS_INIT_MSEC_WEIGHT_DOWN (WRS_MAINTENANCE_PERIOD_MS * 3) /* Msec */ +#define WRS_INIT_MSEC_WEIGHT_UP (WRS_MAINTENANCE_PERIOD_MS * 3) /* Msec */ + +#define WRS_MSEC_WEIGHT_MIN (WRS_MAINTENANCE_PERIOD_MS * 2) /* Msec */ +#define WRS_MSEC_WEIGHT_MAX_UP 30000 /* Msec */ +#define WRS_MSEC_WEIGHT_MAX_DOWN 4000 /* Msec */ +#define WRS_MSEC_STEP_DOWN 5000 /* Msec */ +#define WRS_MSEC_STEP_UP_SAME 1000 /* Msec */ +#define WRS_INVALID_RATE ((u16)(~0)) + +enum cl_wrs_table_node_up { + WRS_TABLE_NODE_UP_MCS, + WRS_TABLE_NODE_UP_BW, + WRS_TABLE_NODE_UP_NSS, + WRS_TABLE_NODE_UP_BF, + WRS_TABLE_NODE_UP_GI, + + WRS_TABLE_NODE_UP_MAX +}; + +struct cl_wrs_table_validity { + bool is_valid; + u16 new_rate_idx; +}; + +struct cl_wrs_table_node { + u16 rate_idx; + u16 time_th; + bool quick_up_check; +}; + +struct cl_wrs_rate { + u16 mcs : 4, + nss : 3, + bw : 2, + gi : 2, + rsv : 2; +}; + +struct cl_wrs_table { + struct cl_wrs_rate rate; + struct cl_wrs_table_node rate_down; + struct cl_wrs_table_node rate_up[WRS_TABLE_NODE_UP_MAX]; + u32 frames_total; + u32 ba_not_rcv_total; + u64 epr_acc; +}; + +struct cl_hw; +struct cl_wrs_db; +struct cl_wrs_sta; +struct cl_wrs_params; + +void cl_wrs_tables_global_build(void); +void cl_wrs_tables_print(struct cl_hw *cl_hw, struct cl_wrs_params *wrs_params); +void cl_wrs_tables_reset(struct cl_wrs_db *wrs_db, struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params); +void cl_wrs_tables_build(struct cl_hw *cl_hw, struct cl_wrs_sta *wrs_sta, + struct cl_wrs_params *wrs_params); +u16 cl_wrs_tables_find_rate_idx(struct cl_wrs_params *wrs_params, + u8 bw, u8 nss, u8 mcs, u8 gi); + +#endif /* CL_WRS_TABLES_H */ From patchwork Thu Jun 17 16:02:23 2021 Content-Type: text/plain; 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Thu, 17 Jun 2021 16:08:37 +0000 From: viktor.barna@celeno.com To: linux-wireless@vger.kernel.org Cc: Kalle Valo , "David S . Miller" , Jakub Kicinski , Aviad Brikman , Eliav Farber , Oleksandr Savchenko , Shay Bar , Viktor Barna Subject: [RFC v1 256/256] wireless: add Celeno vendor Date: Thu, 17 Jun 2021 16:02:23 +0000 Message-Id: <20210617160223.160998-257-viktor.barna@celeno.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com> References: <20210617160223.160998-1-viktor.barna@celeno.com> X-Originating-IP: [62.216.42.54] X-ClientProxiedBy: PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) To AM9P192MB1412.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:38b::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (62.216.42.54) by PR3PR09CA0018.eurprd09.prod.outlook.com (2603:10a6:102:b7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18 via Frontend Transport; Thu, 17 Jun 2021 16:07:20 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 359411c2-f2ae-4bf4-60d5-08d931a9fcd5 X-MS-TrafficTypeDiagnostic: AM9P192MB1014: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xw9UInACHGxvUOZz6jlx00eK9GjQYw1lnaHH/dK8CSdSLe7G2G5Tcz57Xwia2bKQWEJsBWkjFB+1a6eGB0J57Gbs7eB3fEC2ASKfyx5DYcgwzHSku/+KUvoBvGGs0EqTo8YYqjnlLSexuThlRdEVeBph4E0tgYYN8Rd3/g3W8s+Hl9PLLA1UY48gzyL4H7GQ11NNVkyUUpDH4KTz0r8psHZ+CJfQpLARE0etSoq2CcyijvxA8UtoN+eSDtN+vKfQAeXBce0opZx+fL8MIUjpJQCM5+UY1TDSyFP0foUaqwQNmeDhpyOyZmuh90utZ7c0Sis0iUBa1EKqG/e140U4IFrfBYLexdAyD/4PKNRKcDMAxh82Do7Q/uLKLYIDijufSD2pWTSE8emvozHA+b4PmszhSYdkoXvK1LpzSvb3upcpuOMZ2lU2kW1eCmn4MSXnaJYaGSiulOCRH2WjfLWL4bi6Km98ENvaM3Jg++w/DAi90DnDs5ZTDzESAkQXAQUfU8SmTy58e3k4whBEPRomZywH95d+TG+B5OZhfB3C/nsapvixTYvVFfxBox2vG1/PTlNLO9D15nZifVN0m7WOMLy29YWylQvGzH7Dna+qKNwiZRbPepfmN+GJfA+ot99zEt3RpcEyJAZsuU3cMYEg2X7+NnoJ4xRfOc1+Gnm5ioB5YLj2svmbX5eAXroK8VTE X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM9P192MB1412.EURP192.PROD.OUTLOOK.COM; PTR:; CAT:NONE; SFS:(366004)(39850400004)(346002)(376002)(396003)(136003)(316002)(86362001)(66946007)(54906003)(4326008)(956004)(55236004)(66556008)(66476007)(508600001)(36756003)(8676002)(26005)(2616005)(5660300002)(6506007)(107886003)(6916009)(83380400001)(2906002)(52116002)(1076003)(16526019)(38350700002)(38100700002)(6486002)(8936002)(186003)(9686003)(6512007)(69590400013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WbAAUbPguhGVLw0lJrAvhZVcohI1FMJbikK3QRb5JWgc5zzfbXu9drdGtsQgm+clXcI0R2xlnMNSxWtDFNxPAp4ZqUtC2wG/Xx3L9AHoHQrLd8/U+Br/eT0+/AxE8MA04xONwFT7VygMDgQLsjBIkTRvQTA9aWHITkQUl7oR8chDVk3pB/Nx/h3YYgK9sKLUxI9n9E3xIQaLV4kwjonhYtvOhhTov0ed/h5OjGVJZCv/ns4gCeJ2s446AqY93tLv0NqMTbPIY7gCUciP3EtbbniGT35E+IVr9PReNlvoXtYkU53HUrORCVmMwqNZrX8jV29OlaI8GVOydQvqFLJ1QzUgVv8boJmxEVJfPznwEhiY8wKtbLQy9wcHRWyeOxupRibOS8CzF9ahhKbsRo/qGh5LXPpiXWCKPR8EnQifD3hgMsSeNBmpLugel3D9r+5LEfG9IxHx8Oiu97vuPESpHpfu1W/VpswlgVA2MFI4Og8cLbWxpo43U4QmMSGa7McLyTE4tQ34vImgim0nLtO48l95W9ga+HXUETk1f+IcvLVHAT+kEStVyzGwyeh3ZsZ9YjB+ONKEEA4oL1Wuq5QeeBEpq8xm+4lA+KHJ6cHHKF+jmbNuEIwBgQvxPolhZ4hxKjJHkLyKK1tFlVwaQwz+2IOmIB0DpT9k4DAQxDuKkvkQRw/yAhcOQpuq5HWJZxFar7v47zMS3X3OCDLc8ksrMFxPpufWCNMJg4mEEGAiAtik241YG0J3uGoTO6Uc279FUtXipW1TDel1ep1qDr9GnuLDZi/ccNugYlMA3FHTVKMcb2sKM6Su62Uq57QTwg2YSMUByG53vy5z7ubwNoaH+3DkCBOTLMS4KOXxEupB9SmncUWOphr7sLjvDQSb/xs/Z/F1e8njz59V6hg/NPaU1f8A6d6Y2rLF6bGatGNAf9/Pw7EPp6c8VQ8TSU/Pq4k+XCs/L9jItFsD67XtOTmHj5TznFZm2HNnqGcBmiWDulgMNx7jRZ6Gq8SppKLaYdSK6G3yjadGewhK0JwPeujzOaDbB0uPgfVm3LuGCD8kO7x3vYS+3wVGoM6tqNAaOU5x4WuTmnqEpPhwc3ert8LtRfg0fNQ1FuIB4wAlJiBh+gz8aKGYnjYzUZ66FXcb2X/KG+3ys5cO/NL8vPLP8qPib2NBKT52e9jPRHpYAu5ErNGP95WsdgK1fBtd503P11/FfThsWppiqJWojZxqRjPYpdx6DY93YKlKXUCIZsYficqTxwVRktvx8UVWM1ckMvclibeL0GmpLw3erX7q0NWCOKL0aMLu7RdfH8Bh6hV6tYsFlfHQeL9pLx3wQ86TcNwl X-OriginatorOrg: celeno.com X-MS-Exchange-CrossTenant-Network-Message-Id: 359411c2-f2ae-4bf4-60d5-08d931a9fcd5 X-MS-Exchange-CrossTenant-AuthSource: AM9P192MB1412.EURP192.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 16:07:21.2195 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f313103b-4c9f-4fd3-b5cf-b97f91c4afa8 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6HM57R6EZt8uMehErTUqJLZCFQau8eNLl1zv2YIVwsVYvTUXUo9DCItD3TO7X1TCkuNdDBm26PGutVMYpq0CHg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P192MB1014 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Viktor Barna (Part of the split. Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/Kconfig | 1 + drivers/net/wireless/Makefile | 1 + 2 files changed, 2 insertions(+) -- 2.30.0 diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 7add2002ff4c..444c81e3da06 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig @@ -35,6 +35,7 @@ source "drivers/net/wireless/st/Kconfig" source "drivers/net/wireless/ti/Kconfig" source "drivers/net/wireless/zydas/Kconfig" source "drivers/net/wireless/quantenna/Kconfig" +source "drivers/net/wireless/celeno/Kconfig" config PCMCIA_RAYCS tristate "Aviator/Raytheon 2.4GHz wireless support" diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile index 80b324499786..3eb57351d0e5 100644 --- a/drivers/net/wireless/Makefile +++ b/drivers/net/wireless/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_WLAN_VENDOR_ST) += st/ obj-$(CONFIG_WLAN_VENDOR_TI) += ti/ obj-$(CONFIG_WLAN_VENDOR_ZYDAS) += zydas/ obj-$(CONFIG_WLAN_VENDOR_QUANTENNA) += quantenna/ +obj-$(CONFIG_WLAN_VENDOR_CELENO) += celeno/ # 16-bit wireless PCMCIA client drivers obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o