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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w43-v6si1966530qvj.262.2018.08.02.22.22.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 02 Aug 2018 22:22:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=IONlEmNk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:48998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flSXe-0001bZ-AE for patch@linaro.org; Fri, 03 Aug 2018 01:22:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38907) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flSXF-0001ZU-Pn for qemu-devel@nongnu.org; Fri, 03 Aug 2018 01:21:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flSXF-0004r1-0R for qemu-devel@nongnu.org; Fri, 03 Aug 2018 01:21:57 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:35719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1flSXE-0004qs-Q5; Fri, 03 Aug 2018 01:21:56 -0400 Received: by mail-pf1-x435.google.com with SMTP id p12-v6so2615636pfh.2; Thu, 02 Aug 2018 22:21:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KwnVk0FZbRL5sACB19TJDzQlDaPoBQkUgoOUVam8cLY=; b=IONlEmNk88TmkodRPAfdCYzL/ar8iEHhfeH/KTBwhDSRQokqbmnhmrLXfDbyGBJAEd M2Qy3ynz2VIMOGsJTYvqu1OH/GxRp2bLwZ+x9VHKDSSEC2g8lpFR5zO0hrjcAiVJncIW 3pOscdSjcq6lwV/Ed5b7sadKSJFTN17BL4VewAfxP6hqoXM7rm5Uzq4nkUI3dtMPW+nF Vraa56+x8wkyUe3soQz+72DUjcSfezzKbBOOYuES7vgK8nxj60KocKyXe7jHPwrw1kql 0WYiqXFc2rfEdIgK1tzpUNMYbqWuV4dT8r3LfOWIqt95XqJnuIh9JARUEqcWl/CB2Zdh oj6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KwnVk0FZbRL5sACB19TJDzQlDaPoBQkUgoOUVam8cLY=; b=qemnsBw7D5q8T+rE3pTlP7GZdu8xF6+1HMrjGeAy22zoT+t05dzIV+QLk+6PYkuJSx 4dCHkm5T+fhxZQ9Fz5qZ2sNjDjShQWu6Rcn6KFhE5oZm9BQaW/zA5pcVaGqQkS2RDCnV c5aRFsA1byOvqf38spjem+MVUkZmHZbST3MiW1clv6h7vl2bhY+hllV1KsFD7Fjow8hy QQcr+Cgor7s0MFrIEEO/Zxe9oLVS4x80sTFMz+/ZrUVsNJ1xrSP829JGfHYdFuR0HFBQ OrQNRjnQ9EAYBlDgvZ8DXjrHfxQwcamvYxBxW261uy86kuIwP3BRpEv5AcZ4x1Q/dFuk 46Ag== X-Gm-Message-State: AOUpUlGRbQN4VNfaYe0smmjVh2qcmB4s/7jCUyzVhadUX1XCc6pDlq75 LniItnuJ2+nxWBIFA13Kebo= X-Received: by 2002:a65:6203:: with SMTP id d3-v6mr2208615pgv.420.1533273715820; Thu, 02 Aug 2018 22:21:55 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id l127-v6sm5635688pfc.55.2018.08.02.22.21.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 22:21:54 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 03 Aug 2018 14:51:48 +0930 From: Joel Stanley To: Peter Maydell Date: Fri, 3 Aug 2018 14:51:35 +0930 Message-Id: <20180803052137.10602-2-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180803052137.10602-1-joel@jms.id.au> References: <20180803052137.10602-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v4 1/3] MAINTAINERS: Add NRF51 entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This contains the NRF51, and the machine that uses it, the BBC micro:bit. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v3: fix spelling of mailing list add stefan's reviewed-by --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/MAINTAINERS b/MAINTAINERS index c48d9271cf15..5a0d2e327d4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -656,6 +656,14 @@ F: include/hw/*/*aspeed* F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h +NRF51 +M: Joel Stanley +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/nrf51_soc.c +F: hw/arm/microbit.c +F: include/hw/arm/nrf51_soc.h + CRIS Machines ------------- Axis Dev88 From patchwork Fri Aug 3 05:21:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 143377 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp42546ljj; Thu, 2 Aug 2018 22:22:36 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfGMNjaQRH1ivE47r7lC59zfXWyfEvwKhlqlSDrXPZoPfogXAYhilCxxbPqE4c9tcgIJNHa X-Received: by 2002:a37:7401:: with SMTP id p1-v6mr2245993qkc.154.1533273756749; Thu, 02 Aug 2018 22:22:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533273756; cv=none; d=google.com; s=arc-20160816; b=n4iNzncwfQceP+QGFk/3oys4YKo3HjxO1GjOqGsE7QwUf2Md1AA15umxQnZ5t0Ujq6 Sx8NrZ3sqG25a3mPsjZ5mKuLbJdmCg9yiE3NBJElX35z23/dCG1tLRRsl+V5H4pe2Vmf 8xaYPs25/ug4VUMebbSA0I0oX5p89pBbZQC2+I0epqiT4+Fnl9yFhupNQSNPBFp+vUdm zlVfmpSNul9KuCxlarWsZkjPxSQLac9jV8lIcNACxnkLVN0ST9s6kXCaQ62Uc60TJ3h6 Hj7fPqTTXFvkQbOoZUKEJlvDR0Gz6PP+SBBJMCxqZ00aDJM3kWRt4cKHoebOK1C74gZg cZmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=th/eolquJgzA4DlWC5APMPqqPtdXm2JcWzD8RmtGkw0=; b=XlTDJeAhRMmVoiL7DIkUg4mfFMDuhSMFwRj3mpO6o0PaVM6v2JeO/G0Zhjvyw/rHC4 k5RxKwZRKujUOVGs6iSOCk9IgdGHWmU4NR2BgUPn+hRBo6gtyPf1ZaNcVzntbVrBV4g/ EZGuaZOvBHY02xNLKjeyWYVqgZ/8GiBeLUuckF6tstwbNyg8VOZRHVZKd4V3FpiW+8e3 czvQLK/6l01FnmuP8raEJcKwDEyF2foZaIhqisvujbuUUbpLvYP4CW5RBvSg1O2de2DM Wr9TgSpDkGFhGPc3C3hj8OTbNKQwz1Lz1wjRr5iPTeZ9sUhFGCg4mgBsACeB6ZBJGzjX he1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=FVcU0+iZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h4-v6si1742013qva.66.2018.08.02.22.22.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 02 Aug 2018 22:22:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=FVcU0+iZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:49000 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flSXs-0001jK-3z for patch@linaro.org; Fri, 03 Aug 2018 01:22:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flSXO-0001gl-06 for qemu-devel@nongnu.org; Fri, 03 Aug 2018 01:22:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flSXM-0004tT-Kd for qemu-devel@nongnu.org; Fri, 03 Aug 2018 01:22:06 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:41458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1flSXM-0004tF-CT; Fri, 03 Aug 2018 01:22:04 -0400 Received: by mail-pg1-x542.google.com with SMTP id z8-v6so2282792pgu.8; Thu, 02 Aug 2018 22:22:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=th/eolquJgzA4DlWC5APMPqqPtdXm2JcWzD8RmtGkw0=; b=FVcU0+iZqPTOqRp3NrpGNkVx3Zb3Kmv+xSOtUYrpiY8tB1BebLdp5DShz4sgLF2JwB jw03sFlb0DNEsLiZjUVm8aExBks8OilmitTYLMbD6jGWcq2RT8b/1qcvROrtNlmy2T/2 dmLlE+EzLV8tDDjtLEGbVuR77jwUm2duAU5BMMFJ0wNpsBkN+SLGwNdVLoVUBotQvnd8 NWGu/mtYe1/nzHVVi6r+YUFN8/5QNWqGiKNw7UM+E+q8csH3Km2e7NYTnLrArjRk5fRo Sxu3egG5H3jOXOqZo8Mga93YQ5X3xtMB8xDwxga9T05At8qZRdlcGpIDQ/9s67f+YZQS F6zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=th/eolquJgzA4DlWC5APMPqqPtdXm2JcWzD8RmtGkw0=; b=R1p1T3uYMVlJFwXnt0fNAIddcNcIrbc/Fju7NI+YcZUPWpblwvlj5JvczEYNrH74im mHP0M4X1H7/sPQk1/TUcS+Db2vF9i7OAHcVs6gslFFXER6PW/FqmBR5oIzLV1Nu08Cx/ RNuebzF5j//j9BgRyjZ0j1k0e1laDt31XkqFIBMpy+SUrmUPIrIiRql4fekRaZIIK0SX L99r7YNOnphYUUmynxf8WHqeUYjwkKWvvitNroKPi4Rcc075sFsVohCJqr1Uo8XUu0l5 dkraKvkgDDWsGU+I87QDWFMMhGliB/qSo6NF2HwevEZIP/Re1j9RBWQiRy5pgQyJX1Zt tMVw== X-Gm-Message-State: AOUpUlH64CQ/ToRNtuu7AZXPx7zU6uvXhNRiACNQTrTykubVfNh9Io8G JqIC5sjFWC+oXPgWDjZS+TA= X-Received: by 2002:a63:d946:: with SMTP id e6-v6mr2280774pgj.24.1533273723271; Thu, 02 Aug 2018 22:22:03 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id y4-v6sm4900520pfm.137.2018.08.02.22.21.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 22:22:02 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 03 Aug 2018 14:51:56 +0930 From: Joel Stanley To: Peter Maydell Date: Fri, 3 Aug 2018 14:51:36 +0930 Message-Id: <20180803052137.10602-3-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180803052137.10602-1-joel@jms.id.au> References: <20180803052137.10602-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v4 2/3] arm: Add Nordic Semiconductor nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley --- v2: put memory as struct fileds in state structure pass OBJECT(s) as owner, not NULL Add missing addresses for ficr Fix flash and sram sizes for microbit Embed cpu object in state object an initalise it without use of armv7m_init Link to datasheet v3: rebase nrf51 on m0 changes remove unused kernel_filename clarify flash and sram size make flash and sram size properties of the soc state v4: set the number of interrupts to 32 --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/nrf51_soc.c | 119 ++++++++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 42 +++++++++++ 4 files changed, 163 insertions(+) create mode 100644 hw/arm/nrf51_soc.c create mode 100644 include/hw/arm/nrf51_soc.h -- 2.17.1 diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index e704cb6e34d7..3432721d7d08 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -102,6 +102,7 @@ CONFIG_STM32F2XX_SYSCFG=y CONFIG_STM32F2XX_ADC=y CONFIG_STM32F2XX_SPI=y CONFIG_STM32F205_SOC=y +CONFIG_NRF51_SOC=y CONFIG_CMSDK_APB_TIMER=y CONFIG_CMSDK_APB_UART=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index b1e4f8f006aa..e31875ec69bc 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -36,3 +36,4 @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o obj-$(CONFIG_IOTKIT) += iotkit.o obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c new file mode 100644 index 000000000000..27b57e64735c --- /dev/null +++ b/hw/arm/nrf51_soc.c @@ -0,0 +1,119 @@ +/* + * Nordic Semiconductor nRF51 SoC + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/devices.h" +#include "hw/misc/unimp.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" +#include "cpu.h" + +#include "hw/arm/nrf51_soc.h" + +#define IOMEM_BASE 0x40000000 +#define IOMEM_SIZE 0x20000000 + +#define FICR_BASE 0x10000000 +#define FICR_SIZE 0x000000fc + +#define FLASH_BASE 0x00000000 +#define SRAM_BASE 0x20000000 + +/* The size and base is for the NRF51822 part. If other parts + * are supported in the future, add a sub-class of NRF51SoC for + * the specific variants */ +#define NRF51822_FLASH_SIZE (256 * 1024) +#define NRF51822_SRAM_SIZE (16 * 1024) + +static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) +{ + NRF51State *s = NRF51_SOC(dev_soc); + Error *err = NULL; + + if (!s->board_memory) { + error_setg(errp, "memory property was not set"); + return; + } + + object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", + &err); + object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); + + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); + + memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, + &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_set_readonly(&s->flash, true); + memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + + memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + + create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.private", 0xF0000000, 0x10000000); +} + +static void nrf51_soc_init(Object *obj) +{ + NRF51State *s = NRF51_SOC(obj); + + memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); + + object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE); + object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error_abort); + qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default()); + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0")); + qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); +} + +static Property nrf51_soc_properties[] = { + DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), + DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLASH_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = nrf51_soc_realize; + dc->props = nrf51_soc_properties; +} + +static const TypeInfo nrf51_soc_info = { + .name = TYPE_NRF51_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51State), + .instance_init = nrf51_soc_init, + .class_init = nrf51_soc_class_init, +}; + +static void nrf51_soc_types(void) +{ + type_register_static(&nrf51_soc_info); +} +type_init(nrf51_soc_types) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h new file mode 100644 index 000000000000..838bccd815df --- /dev/null +++ b/include/hw/arm/nrf51_soc.h @@ -0,0 +1,42 @@ +/* + * Nordic Semiconductor nRF51 SoC + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_SOC_H +#define NRF51_SOC_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/arm/arm-m-profile.h" + +#define TYPE_NRF51_SOC "nrf51-soc" +#define NRF51_SOC(obj) \ + OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) + +typedef struct NRF51State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + ARMMProfileState cpu; + + MemoryRegion iomem; + MemoryRegion sram; + MemoryRegion flash; + + uint32_t sram_size; + uint32_t flash_size; + + MemoryRegion *board_memory; + + MemoryRegion container; + +} NRF51State; + +#endif + From patchwork Fri Aug 3 05:21:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 143378 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp43645ljj; Thu, 2 Aug 2018 22:24:18 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdPZaB7HCSsMHnvMIjcgFdRdzdV1MDS8uAmMrBgaRwuwKLOmrrLTUdh9lmsFWWY4Pgb+qVn X-Received: by 2002:ac8:2908:: with SMTP id y8-v6mr2380977qty.45.1533273858238; Thu, 02 Aug 2018 22:24:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533273858; cv=none; d=google.com; s=arc-20160816; b=VcTpyza7Cv60KNg4r2LE6SRvhWS3aeNxFMAklYY07VHD2z4toH22VcRdRpyMTQfuPD kV1h7pTCds4cSm/bRc8ZTWrur4acA0awDtC6e8whlrhmxVoIfQaDiE4Mp+OLMNewZAeJ AMTbV1jDmCaL43kO3xCRsiTtoMBT6QZRnhXs2W1CIdNIKlINYrfVsDUQ9JIeTyaRr7Yi JqH4psoLQ7o0xvrWIl6dxEhJ9CsXEdd6D0M+BLbYlGCWd9tkJxtjhqVbs+zsWYgHWrZY gIx9qGMu3md8vZtbQiQKXLRilIGfg3E7ouHqdU7AGALdMzvrN5xfhimv8Uc5w3Qssowd odVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uVpIy0tbum8TS+4LeuR9ToTnLJtiAlEi8k9IZIn1ZjE=; b=pK1p5C+ygcWW1c7qGhTlgmTbJqVhFKWo7eHNfNTT2FRcgdroFDpe8pWEXtAIFNMwWt raya9ZaRQoVMLqeFQRR7RukVWTinT0Tdu5LVXgDwUMXKpp+7pMNKCJzVHkgBEu4thDtE 3081OQgyHhMf9WYLhog/AV1OHvUPfdTNHWpiYQdIxWhUaJxYr3S5hIIC6btnBgTvOsbA DvMNxbYpjYYrraCRHW/WJ+zlJCONuIy22F/02zxwy2p7kq7H7ezLlQJi1Ii4qhFZNbMT 2KE+ONaQZOwo3AFVcF0AX4cyl9K8aFfuWK10xxwHmIlqvhIeZXCwpDL0488QtC0T67hk trqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=nMwAWy+F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v4 3/3] arm: Add BBC micro:bit machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?utf-8?q?Steffen_G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v2: - Instead of setting kernel filename property, load the image directly - Add link to hardware overview website v3: - Rebase microbit on m0 changes - Remove hard-coded flash size and retrieve from the soc - Add Stefan's reviewed-by --- hw/arm/Makefile.objs | 2 +- hw/arm/microbit.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 hw/arm/microbit.c -- 2.17.1 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index e31875ec69bc..2798a257921d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -36,4 +36,4 @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o obj-$(CONFIG_IOTKIT) += iotkit.o obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o -obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o microbit.o diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c new file mode 100644 index 000000000000..ecf64e883f4f --- /dev/null +++ b/hw/arm/microbit.c @@ -0,0 +1,54 @@ +/* + * BBC micro:bit machine + * http://tech.microbit.org/hardware/ + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" + +#include "hw/arm/nrf51_soc.h" + +typedef struct { + MachineState parent; + + NRF51State nrf51; +} MICROBITMachineState; + +#define TYPE_MICROBIT_MACHINE "microbit" + +#define MICROBIT_MACHINE(obj) \ + OBJECT_CHECK(MICROBITMachineState, obj, TYPE_MICROBIT_MACHINE) + +static void microbit_init(MachineState *machine) +{ + MICROBITMachineState *s = g_new(MICROBITMachineState, 1); + MemoryRegion *system_memory = get_system_memory(); + Object *soc; + + object_initialize(&s->nrf51, sizeof(s->nrf51), TYPE_NRF51_SOC); + soc = OBJECT(&s->nrf51); + object_property_add_child(OBJECT(machine), "nrf51", soc, &error_fatal); + object_property_set_link(soc, OBJECT(system_memory), + "memory", &error_abort); + + object_property_set_bool(soc, true, "realized", &error_abort); + + arm_m_profile_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + NRF51_SOC(soc)->flash_size); +} + +static void microbit_machine_init(MachineClass *mc) +{ + mc->desc = "BBC micro:bit"; + mc->init = microbit_init; + mc->max_cpus = 1; +} +DEFINE_MACHINE("microbit", microbit_machine_init);