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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id w71sm7554666pfc.164.2021.06.14.20.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 20:07:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/5] target/s390x: Expose load_psw and get_psw_mask to cpu.h Date: Mon, 14 Jun 2021 20:07:40 -0700 Message-Id: <20210615030744.1252385-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615030744.1252385-1-richard.henderson@linaro.org> References: <20210615030744.1252385-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruixin.bao@ibm.com, jonathan.albrecht@linux.vnet.ibm.com, cohuck@redhat.com, qemu-s390x@nongnu.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to s390_cpu_set_psw and s390_cpu_get_psw_mask at the same time. Adjust so that they compile for user-only. Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 3 ++ target/s390x/internal.h | 5 --- target/s390x/cc_helper.c | 2 +- target/s390x/excp_helper.c | 28 ++++++------ target/s390x/helper.c | 89 ++++++++++++++++++++------------------ target/s390x/sigp.c | 3 +- 6 files changed, 69 insertions(+), 61 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2464d4076c..b26ae8fff2 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -845,6 +845,9 @@ int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, int s390_cpu_restart(S390CPU *cpu); void s390_init_sigp(void); +/* helper.c */ +void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); +uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 11515bb617..4a18b74d10 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -235,10 +235,6 @@ int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, const char *cc_name(enum cc_op cc_op); uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr); -#ifndef CONFIG_USER_ONLY -void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); -#endif /* CONFIG_USER_ONLY */ - /* cpu.c */ #ifndef CONFIG_USER_ONLY @@ -303,7 +299,6 @@ void s390_cpu_gdb_init(CPUState *cs); void s390_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void do_restart_interrupt(CPUS390XState *env); #ifndef CONFIG_USER_ONLY -uint64_t get_psw_mask(CPUS390XState *env); void s390_cpu_recompute_watchpoints(CPUState *cs); void s390x_tod_timer(void *opaque); void s390x_cpu_timer(void *opaque); diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index e7039d0d18..e7a74d66dd 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -509,7 +509,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src, #ifndef CONFIG_USER_ONLY void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); cpu_loop_exit(env_cpu(env)); } diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 20625c2c8f..9c361428c8 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -252,7 +252,7 @@ static void do_program_interrupt(CPUS390XState *env) lowcore->pgm_ilen = cpu_to_be16(ilen); lowcore->pgm_code = cpu_to_be16(env->int_pgm_code); - lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env)); + lowcore->program_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr); mask = be64_to_cpu(lowcore->program_new_psw.mask); addr = be64_to_cpu(lowcore->program_new_psw.addr); @@ -260,7 +260,7 @@ static void do_program_interrupt(CPUS390XState *env) cpu_unmap_lowcore(lowcore); - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); } static void do_svc_interrupt(CPUS390XState *env) @@ -272,14 +272,14 @@ static void do_svc_interrupt(CPUS390XState *env) lowcore->svc_code = cpu_to_be16(env->int_svc_code); lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen); - lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env)); + lowcore->svc_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen); mask = be64_to_cpu(lowcore->svc_new_psw.mask); addr = be64_to_cpu(lowcore->svc_new_psw.addr); cpu_unmap_lowcore(lowcore); - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); /* When a PER event is pending, the PER exception has to happen immediately after the SERVICE CALL one. */ @@ -348,12 +348,12 @@ static void do_ext_interrupt(CPUS390XState *env) mask = be64_to_cpu(lowcore->external_new_psw.mask); addr = be64_to_cpu(lowcore->external_new_psw.addr); - lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env)); + lowcore->external_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr); cpu_unmap_lowcore(lowcore); - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); } static void do_io_interrupt(CPUS390XState *env) @@ -373,7 +373,7 @@ static void do_io_interrupt(CPUS390XState *env) lowcore->subchannel_nr = cpu_to_be16(io->nr); lowcore->io_int_parm = cpu_to_be32(io->parm); lowcore->io_int_word = cpu_to_be32(io->word); - lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env)); + lowcore->io_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr); mask = be64_to_cpu(lowcore->io_new_psw.mask); addr = be64_to_cpu(lowcore->io_new_psw.addr); @@ -381,7 +381,7 @@ static void do_io_interrupt(CPUS390XState *env) cpu_unmap_lowcore(lowcore); g_free(io); - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); } typedef struct MchkExtSaveArea { @@ -457,14 +457,14 @@ static void do_mchk_interrupt(CPUS390XState *env) lowcore->clock_comp_save_area = cpu_to_be64(env->ckc >> 8); lowcore->mcic = cpu_to_be64(mcic); - lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env)); + lowcore->mcck_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr); mask = be64_to_cpu(lowcore->mcck_new_psw.mask); addr = be64_to_cpu(lowcore->mcck_new_psw.addr); cpu_unmap_lowcore(lowcore); - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); } void s390_cpu_do_interrupt(CPUState *cs) @@ -592,9 +592,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) and MVCS instrutions are not used. */ env->per_perc_atmid |= env->psw.mask & (PSW_MASK_ASC) >> 46; - /* Remove all watchpoints to re-execute the code. A PER exception - will be triggered, it will call load_psw which will recompute - the watchpoints. */ + /* + * Remove all watchpoints to re-execute the code. A PER exception + * will be triggered, it will call s390_cpu_set_psw which will + * recompute the watchpoints. + */ cpu_watchpoint_remove_all(cs, BP_CPU); cpu_loop_exit_noexc(cs); } diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 7678994feb..d311903b94 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -104,44 +104,6 @@ void s390_handle_wait(S390CPU *cpu) } } -void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) -{ - uint64_t old_mask = env->psw.mask; - - env->psw.addr = addr; - env->psw.mask = mask; - - /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */ - if (!tcg_enabled()) { - return; - } - env->cc_op = (mask >> 44) & 3; - - if ((old_mask ^ mask) & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(env_cpu(env)); - } - - if (mask & PSW_MASK_WAIT) { - s390_handle_wait(env_archcpu(env)); - } -} - -uint64_t get_psw_mask(CPUS390XState *env) -{ - uint64_t r = env->psw.mask; - - if (tcg_enabled()) { - env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, - env->cc_vr); - - r &= ~PSW_MASK_CC; - assert(!(env->cc_op & ~3)); - r |= (uint64_t)env->cc_op << 44; - } - - return r; -} - LowCore *cpu_map_lowcore(CPUS390XState *env) { LowCore *lowcore; @@ -168,7 +130,7 @@ void do_restart_interrupt(CPUS390XState *env) lowcore = cpu_map_lowcore(env); - lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env)); + lowcore->restart_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr); mask = be64_to_cpu(lowcore->restart_new_psw.mask); addr = be64_to_cpu(lowcore->restart_new_psw.addr); @@ -176,7 +138,7 @@ void do_restart_interrupt(CPUS390XState *env) cpu_unmap_lowcore(lowcore); env->pending_int &= ~INTERRUPT_RESTART; - load_psw(env, mask, addr); + s390_cpu_set_psw(env, mask, addr); } void s390_cpu_recompute_watchpoints(CPUState *cs) @@ -266,7 +228,7 @@ int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch) sa->grs[i] = cpu_to_be64(cpu->env.regs[i]); } sa->psw.addr = cpu_to_be64(cpu->env.psw.addr); - sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env)); + sa->psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(&cpu->env)); sa->prefix = cpu_to_be32(cpu->env.psa); sa->fpc = cpu_to_be32(cpu->env.fpc); sa->todpr = cpu_to_be32(cpu->env.todpr); @@ -323,8 +285,53 @@ int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len) cpu_physical_memory_unmap(sa, len, 1, len); return 0; } +#else +/* For user-only, tcg is always enabled. */ +#define tcg_enabled() true #endif /* CONFIG_USER_ONLY */ +void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) +{ +#ifndef CONFIG_USER_ONLY + uint64_t old_mask = env->psw.mask; +#endif + + env->psw.addr = addr; + env->psw.mask = mask; + + /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */ + if (!tcg_enabled()) { + return; + } + env->cc_op = (mask >> 44) & 3; + +#ifndef CONFIG_USER_ONLY + if ((old_mask ^ mask) & PSW_MASK_PER) { + s390_cpu_recompute_watchpoints(env_cpu(env)); + } + + if (mask & PSW_MASK_WAIT) { + s390_handle_wait(env_archcpu(env)); + } +#endif +} + +uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) +{ + uint64_t r = env->psw.mask; + + if (tcg_enabled()) { + env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, + env->cc_vr); + + r &= ~PSW_MASK_CC; + assert(!(env->cc_op & ~3)); + r |= (uint64_t)env->cc_op << 44; + } + + return r; +} + void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) { S390CPU *cpu = S390_CPU(cs); diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index c604f17710..c2d5cdf061 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -235,7 +235,8 @@ static void sigp_restart(CPUState *cs, run_on_cpu_data arg) cpu_synchronize_state(cs); /* * Set OPERATING (and unhalting) before loading the restart PSW. - * load_psw() will then properly halt the CPU again if necessary (TCG). + * s390_cpu_set_psw() will then properly halt the CPU again if + * necessary (TCG). */ s390_cpu_set_state(S390_CPU_STATE_OPERATING, cpu); do_restart_interrupt(&cpu->env); From patchwork Tue Jun 15 03:07:41 2021 Content-Type: text/plain; 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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id w71sm7554666pfc.164.2021.06.14.20.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 20:07:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/5] target/s390x: Do not modify cpu state in s390_cpu_get_psw_mask Date: Mon, 14 Jun 2021 20:07:41 -0700 Message-Id: <20210615030744.1252385-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615030744.1252385-1-richard.henderson@linaro.org> References: <20210615030744.1252385-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruixin.bao@ibm.com, jonathan.albrecht@linux.vnet.ibm.com, cohuck@redhat.com, qemu-s390x@nongnu.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to use this function for debugging, and debug should not modify cpu state (even non-architectural cpu state) lest we introduce heisenbugs. Signed-off-by: Richard Henderson --- target/s390x/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/target/s390x/helper.c b/target/s390x/helper.c index d311903b94..559fc3573f 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -321,12 +321,12 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) uint64_t r = env->psw.mask; if (tcg_enabled()) { - env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, - env->cc_vr); + uint64_t cc = calc_cc(env, env->cc_op, env->cc_src, + env->cc_dst, env->cc_vr); + assert(cc <= 3); r &= ~PSW_MASK_CC; - assert(!(env->cc_op & ~3)); - r |= (uint64_t)env->cc_op << 44; + r |= cc << 44; } return r; From patchwork Tue Jun 15 03:07:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 460483 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp3861580jae; Mon, 14 Jun 2021 20:10:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAu06XSal/qLvheY+9p2+3J5IcUwJArxhjwIpOLvQEjoOZL15LwW4PYgGkrJiakVxNoOA6 X-Received: by 2002:a05:6102:21c4:: with SMTP id r4mr2643654vsg.28.1623726632338; Mon, 14 Jun 2021 20:10:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623726632; cv=none; d=google.com; s=arc-20160816; b=PnINnb5X6wK8KmKG3KmVnwwGfAa7XcG/hy5K2E4f1f0aMZwyDQG1N3lG1sQzsMBYK3 iXNn8WvuUuxy/dbSlfgnkzbROUnrN/qmXBGiMA0DCvaGNhSWfByPqfrUGUwBDAVHZBkx lp+aacOPS9c1VWWf7Ali24+Wk1aYiDIEFkxzKBQjzzRhVVxyPpDPcWNUQxALqkQCiTVj eeWYlwRqBtrkXV4tLCIGJ7PKmmuBIvrbJKzpaeenLpntWxjQClSFnfqmfhsG4arGzwrB 8vXEEClG1GillwKIHRNr/w5itkZALeUYuEf3mEL6EQVgFy8Nv0dxJF/eDlxuTHhZe8my 9y4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/6xkphnJBNo/K1DX+n+4XklxOsTRpwFklbH0yf7ANvo=; b=RjicZLuMlWKmCxM/YwPh2JHgPjGfSOpQePN4wbNq9uTYFWOrsoHMpz2qqarZuMrUnA li1DIhkfO/sUO+oqs4HHlFzpbwuxmjFl14Q7QeyGyFGM/h685iXdqwIEe6BH7FbcBuxs uBNAQvI5hZRKcw5Wxn8EgA/7JIxTGivOoXapqxU56OcDXXWVsSpAXX60RhppyNG5q9MC hPzCJ03luQeczHe6pxW9zUBOpulPs5sl7rWc+3SXmofzMxA3B45NkMjDTRbzGLu97ya0 wNtOtN/uNdzY3gu9lR+Hj2pI2sViMwvGsdmGNwgXPtGqVJ4Jb1q70ORGAxKx0AnAstDI 23gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="orK1N/ok"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id w71sm7554666pfc.164.2021.06.14.20.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 20:07:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/5] target/s390x: Improve s390_cpu_dump_state vs cc_op Date: Mon, 14 Jun 2021 20:07:42 -0700 Message-Id: <20210615030744.1252385-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615030744.1252385-1-richard.henderson@linaro.org> References: <20210615030744.1252385-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruixin.bao@ibm.com, jonathan.albrecht@linux.vnet.ibm.com, cohuck@redhat.com, qemu-s390x@nongnu.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use s390_cpu_get_psw_mask so that we print the correct architectural value of psw.mask. Do not print cc_op unless tcg_enabled. Signed-off-by: Richard Henderson --- target/s390x/helper.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 559fc3573f..1445b74451 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -338,12 +338,14 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) CPUS390XState *env = &cpu->env; int i; - if (env->cc_op > 3) { - qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n", - env->psw.mask, env->psw.addr, cc_name(env->cc_op)); + qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64, + s390_cpu_get_psw_mask(env), env->psw.addr); + if (!tcg_enabled()) { + qemu_fprintf(f, "\n"); + } else if (env->cc_op > 3) { + qemu_fprintf(f, " cc %15s\n", cc_name(env->cc_op)); } else { - qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n", - env->psw.mask, env->psw.addr, env->cc_op); + qemu_fprintf(f, " cc %02x\n", env->cc_op); } for (i = 0; i < 16; i++) { From patchwork Tue Jun 15 03:07:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 460482 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp3861527jae; Mon, 14 Jun 2021 20:10:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzE/wsk4PCIVWcEijrHz36E/ShLRCLewvxlnT1m7/LVEvyzqGJF3G9MwtnffDltut2AVdjL X-Received: by 2002:a67:f5c5:: with SMTP id t5mr2960404vso.50.1623726626385; Mon, 14 Jun 2021 20:10:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623726626; cv=none; d=google.com; s=arc-20160816; b=Kfv5rMiHX6r6obFqzzLXa+hu4lMDogj9LH7CSwG85sFgQBEpNxbzfCXGqO3LJP+jkV r3Xho3S+x8cHzsU23wFtZI9pesmrvWPyzOoZU164ZdqtxQrtsYhkXUFik5NPrqhylsNU a2dn2BQ5mN5Y+P7ZOn4UtqAQHwotHZdobW2f3/o4NCNAnznY8rOqZqpvsy4/2wnOJLqg +odkHH/+HC0lonGTlpgZp4ygxqD7sd9c6foWhLu20Dd0Hdy9BK6BnEiREDs7HOQ3iEJ+ v73d/ZyPO8GYLy5eCrV4wDNFhCgSbQQuFrbbaCnBClQQSYos0DwbdJTbBAoicOyZbuqw PaQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rxs30+5uAa9OunefGQHMVoUkynnQ1zCC+uwySj1YTHA=; b=w5ToiZzhMc/4Cjd0QiG+eH+9w7qckoPZnmHN58K5pjpLXt9wzOJekkRcV5tAcA+YBW dvMEezrCBydcjUVv0zBBcG4OWLbQyqRnFbQxGrefviA4GgcA1VXkDVSO19d4e4mOkZ6q D/hZYKDyy4jTirMwVg59awffa22eVwE1GuPiPXSWQm2yxcX8c4lghXD43glK5XMJgxXd UFVa9TneEuxol1VVwtZX+hRJg06+mmrwOH7CUc0+ed03yEtzkxb9PmDvtb+Mu3NZtn3L T5xjzLtIkmo+jNDxrnBjyYP/0zCP+7GpE7W/crsXCe7FXKZjCQb5njalrCh7g6JQ5jwA WEtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ph5NFs73; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id w71sm7554666pfc.164.2021.06.14.20.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 20:07:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/5] target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub Date: Mon, 14 Jun 2021 20:07:43 -0700 Message-Id: <20210615030744.1252385-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615030744.1252385-1-richard.henderson@linaro.org> References: <20210615030744.1252385-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruixin.bao@ibm.com, jonathan.albrecht@linux.vnet.ibm.com, cohuck@redhat.com, qemu-s390x@nongnu.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No change in behaviour, as gdbstub was correctly written to install and extract the cc value. Signed-off-by: Richard Henderson --- target/s390x/gdbstub.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index d6fce5ff1e..5b4e38a13b 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -31,18 +31,10 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; - uint64_t val; - int cc_op; switch (n) { case S390_PSWM_REGNUM: - if (tcg_enabled()) { - cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, - env->cc_vr); - val = deposit64(env->psw.mask, 44, 2, cc_op); - return gdb_get_regl(mem_buf, val); - } - return gdb_get_regl(mem_buf, env->psw.mask); + return gdb_get_regl(mem_buf, s390_cpu_get_psw_mask(env)); case S390_PSWA_REGNUM: return gdb_get_regl(mem_buf, env->psw.addr); case S390_R0_REGNUM ... S390_R15_REGNUM: @@ -59,10 +51,7 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) switch (n) { case S390_PSWM_REGNUM: - env->psw.mask = tmpl; - if (tcg_enabled()) { - env->cc_op = extract64(tmpl, 44, 2); - } + s390_cpu_set_psw(env, tmpl, env->psw.addr); break; case S390_PSWA_REGNUM: env->psw.addr = tmpl; From patchwork Tue Jun 15 03:07:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 460484 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp3861615jae; Mon, 14 Jun 2021 20:10:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwLWiJa1UmH1v46H7gHiW7qjP/iL4rmgXlkDd4KuoEVx36IvRxolatmz8u6hLZiq3VtznVZ X-Received: by 2002:a67:b30b:: with SMTP id a11mr3050111vsm.32.1623726637011; Mon, 14 Jun 2021 20:10:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623726637; cv=none; d=google.com; s=arc-20160816; b=MoBxsbdToyAW2eUEHHJwpB3cBnflxRzwyGKbkNEvMgUhV02VOZvH5RaUPlQ0TsPBMu eQV7hRFzIXkOL0bo0vYO59HKqBOZLiPWMCK+uzODi2cPPiFMqU3p68wQhwmrsw7UqWf1 9AVIO6MiPelafgA0bOo33sUX/mfv6wN1OPMqJXSBCLfunLLu3ve6SL626m2Hw6Cvy+x5 IguOhd9S9mtMkxnqXtF9FtlJ1dp0P0ewkgml+F8ucz3fCnQ2Dv3domlzmPVjgPR93DkI RpvF6U2zPMUdYhuRoPHCbPo8akqYZZ0fbZkDhy0KPbAza8R/+pUqJ9uCPin3on+oKkdp zjkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TQf3IjdFQae4tidY+aDNVPg91NNd8BgJC+OISDGWpvo=; b=V/mi9Df3namElRSTwTiSJdfKXJ2ZLbBXdsdUusgSsHtrWVWv2GBxZlIv/KYpmbOsht /cnKZLL5P7cHuryBHQpB2uFv/xE9zNiLIj0HAZYijYWEeDSv9IBUvYoHIhdm+cEkjwEG jbFHiBGSlBEjtxIY+iZxYItHLPs7irV/Ql5CH/bKji++CGVLqlS9qyZv88qlmCT27Oz6 ObArOmBrLRgVR8g1GM5yyTcKZckz76oPhum65w8uGKhdpQaVqxCIIdYDE2g8G7QvMtAj kOrOs698oQl3+oIgnQb6Bch94xP1Fij038y8vbzk1RHN9xWJvkLp9UcXrrsA1nFTcT0/ 7L4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RQ4TCrKN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id w71sm7554666pfc.164.2021.06.14.20.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 20:07:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/5] linux-user/s390x: Save and restore psw.mask properly Date: Mon, 14 Jun 2021 20:07:44 -0700 Message-Id: <20210615030744.1252385-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615030744.1252385-1-richard.henderson@linaro.org> References: <20210615030744.1252385-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruixin.bao@ibm.com, jonathan.albrecht@linux.vnet.ibm.com, cohuck@redhat.com, qemu-s390x@nongnu.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At present, we're referencing env->psw.mask directly, which fails to ensure that env->cc_op is incorporated or updated. Use s390_cpu_{set_psw,get_psw_mask} to fix this. Mirror the kernel's cleaning of the psw.mask in save_sigregs and restore_sigregs. Ignore PSW_MASK_RI for now, as qemu does not support that. Signed-off-by: Richard Henderson --- linux-user/s390x/signal.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/linux-user/s390x/signal.c b/linux-user/s390x/signal.c index ef136dae33..bf8a8fbfe9 100644 --- a/linux-user/s390x/signal.c +++ b/linux-user/s390x/signal.c @@ -112,15 +112,23 @@ get_sigframe(struct target_sigaction *ka, CPUS390XState *env, size_t frame_size) return (sp - frame_size) & -8ul; } +#define PSW_USER_BITS (PSW_MASK_DAT | PSW_MASK_IO | PSW_MASK_EXT | \ + PSW_MASK_MCHECK | PSW_MASK_PSTATE | PSW_ASC_PRIMARY) +#define PSW_MASK_USER (PSW_MASK_ASC | PSW_MASK_CC | PSW_MASK_PM | \ + PSW_MASK_64 | PSW_MASK_32) + static void save_sigregs(CPUS390XState *env, target_sigregs *sregs) { + uint64_t psw_mask = s390_cpu_get_psw_mask(env); int i; /* * Copy a 'clean' PSW mask to the user to avoid leaking * information about whether PER is currently on. + * TODO: qemu does not support PSW_MASK_RI; it will never be set. */ - __put_user(env->psw.mask, &sregs->regs.psw.mask); + psw_mask = PSW_USER_BITS | (psw_mask & PSW_MASK_USER); + __put_user(psw_mask, &sregs->regs.psw.mask); __put_user(env->psw.addr, &sregs->regs.psw.addr); for (i = 0; i < 16; i++) { @@ -289,7 +297,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, static void restore_sigregs(CPUS390XState *env, target_sigregs *sc) { - target_ulong prev_addr; + uint64_t prev_addr, prev_mask, mask, addr; int i; for (i = 0; i < 16; i++) { @@ -297,9 +305,28 @@ static void restore_sigregs(CPUS390XState *env, target_sigregs *sc) } prev_addr = env->psw.addr; - __get_user(env->psw.mask, &sc->regs.psw.mask); - __get_user(env->psw.addr, &sc->regs.psw.addr); - trace_user_s390x_restore_sigregs(env, env->psw.addr, prev_addr); + __get_user(mask, &sc->regs.psw.mask); + __get_user(addr, &sc->regs.psw.addr); + trace_user_s390x_restore_sigregs(env, addr, prev_addr); + + /* + * Use current psw.mask to preserve PER bit. + * TODO: + * if (!is_ri_task(current) && (user_sregs.regs.psw.mask & PSW_MASK_RI)) + * return -EINVAL; + * Simply do not allow it to be set in mask. + */ + prev_mask = s390_cpu_get_psw_mask(env); + mask = (prev_mask & ~PSW_MASK_USER) | (mask & PSW_MASK_USER); + /* Check for invalid user address space control. */ + if ((mask & PSW_MASK_ASC) == PSW_ASC_HOME) { + mask = (mask & ~PSW_MASK_ASC) | PSW_ASC_PRIMARY; + } + /* Check for invalid amode. */ + if (mask & PSW_MASK_64) { + mask |= PSW_MASK_32; + } + s390_cpu_set_psw(env, mask, addr); for (i = 0; i < 16; i++) { __get_user(env->aregs[i], &sc->regs.acrs[i]);