From patchwork Wed Aug 1 03:39:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143222 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp345316ljj; Tue, 31 Jul 2018 20:40:03 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdHzb3oCodQj0qfMKoJF2A9p+eJHnOMlKSj6WB8+jE8kxAwnsRRrgDKoRJYjeMk/DXdDDRk X-Received: by 2002:a62:225d:: with SMTP id i90-v6mr24694989pfi.246.1533094803526; Tue, 31 Jul 2018 20:40:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533094803; cv=none; d=google.com; s=arc-20160816; b=Gf3IUBTrEYAMpCM310VegGkHK88GVEhIby88UfAOmlaOJoBsy7KtVX/CE8EnsyRgbI DQSSti346kZiYuLVvo5iezHz6PsDzE/RLgMOBDgmUl2kD+gOVvTXusiIVvXe4sLW+GTm nm2f2iAU/tKvRa38orTacRBfhIBvWLPzgZkgKJTK+7dL4uhTQh4mrhp/bKU/kjppQ8wI SpQduTbVsaJDHY88r9HOS3sBeU1e4Aq3cpgbvEIK2Rm/GwCWbCJHAy1waeUdTboj3jl8 tedjRWMLr9CW/j2cfpfe5OgINaX5qQ8aFDEu1I0+esqas1VcO1bcyHcLA92o4P52oaOz 5DgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5Xw0RIVpxvacSPHYYpL7pln2k8GJFB8lDAJIEPLAue0=; b=spf3iycaSrIIRrgHepQaHXwbyT356cP/tG6bsiCWLjQ6RYfo4NJ0+Rjlzoa7xYnF8q zYiHNLoJFuGekP+fzSmBXO+4CAWfDBh2IkxTTDJntoQQL8FM2XoZVvowaecrG/5Z72sX bVJ11xl+fO3I6w9oXBJM/oteqiG6eNRiWWjZGiFwvTeAcemEPF+FDpm2eqP0korWUX1O dt/ifIS3cdqPNQI15tAit7qpq78yysR1a1d2V+f6rLgK7LIf1IV4Sx2Hca1nSenEZMgL H05fesNBbsQwNZvbvoD4zdeWQF7KKQsi1fAOuYa/4xdx1qSj6VOyDyCVD8J+6zvzBz2n W4ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=R5+DXHo8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 194-v6si13066959pgf.651.2018.07.31.20.40.03; Tue, 31 Jul 2018 20:40:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=R5+DXHo8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731682AbeHAFXU (ORCPT + 5 others); Wed, 1 Aug 2018 01:23:20 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:37792 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730957AbeHAFXU (ORCPT ); Wed, 1 Aug 2018 01:23:20 -0400 Received: by mail-pl0-f67.google.com with SMTP id d5-v6so2560021pll.4 for ; Tue, 31 Jul 2018 20:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y2Xim6wZcJhjsafQ7hCOBFR4DJdA4YrNANwR9AoDSRg=; b=R5+DXHo8bfJAG+6yqGLz4bsROhYHFYVXz78bAOjEscpMxI2J91pWNCSwF7WE3HCUZo b2IymvEjrr9wKZiL9MnT2smndkkxaOUF1vstW2Bcd127nxnclKiqqXDbl6MTuyOXbilc l9lli/NM292mNTBoePfbc2S27whW1+ur9odyM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y2Xim6wZcJhjsafQ7hCOBFR4DJdA4YrNANwR9AoDSRg=; b=OsAAo09vik64LH0mz7Q21lYIXXV3g/OeqV25Cl9kcunjTujB//gSQvfGRNreAXqITP ywO9K0PJjpa0+m9SiyWym5DqqjjzloIWj+ib9yBgwii6j/wIRcE/OFckQnfGo5RpQN+E wfzLjcwqFlv2TxJYJ6ZrZi3rnUooLbp+f9JI5PQySRD+SBsFz6C8dHvWEBTIpGcn4CRy r/M3NXZsZONTZ2w3RyR5Ok8bEHEdO6yNcVKNdd1CSYXh7jGE2hkiNbEUOgB0K+qgNjbE 4vUEn7ZRSNkfJz+ePsHPaR61wVq14V0Vzna9eC5ymUXd4rBFTSj/jM/MNKzs8wmPoVsb WMTA== X-Gm-Message-State: AOUpUlFUYV3Esr5e7qRbLWpOWVpxX6TeGq0XquMXlnJjpgSesn75D/sU Ok/x8pIc52O5twJyNc7Sn6++ X-Received: by 2002:a17:902:760d:: with SMTP id k13-v6mr22703733pll.56.1533094793555; Tue, 31 Jul 2018 20:39:53 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730e:f0ae:ac4e:9cdd:28a2:4bf9]) by smtp.gmail.com with ESMTPSA id d19-v6sm34879545pgi.50.2018.07.31.20.39.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 20:39:52 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, lee.jones@linaro.org, arnd@arndb.de Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 01/10] dt-bindings: clock: Add syscon support to Actions Semi Owl SoCs Date: Wed, 1 Aug 2018 09:09:06 +0530 Message-Id: <20180801033915.15880-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> References: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since the clock and reset management units are sharing the same memory map, document the clock bindings to support System Controller. Signed-off-by: Manivannan Sadhasivam --- .../bindings/clock/actions,owl-cmu.txt | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt index d1e60d297387..649c95fc4582 100644 --- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt @@ -9,8 +9,6 @@ Required Properties: - compatible: should be one of the following, "actions,s900-cmu" "actions,s700-cmu" -- reg: physical base address of the controller and length of memory mapped - region. - clocks: Reference to the parent clocks ("hosc", "losc") - #clock-cells: should be 1. @@ -21,6 +19,13 @@ All available clocks are defined as preprocessor macros in corresponding dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be used in device tree sources. +The CMU registers are part of the system-controller block on Owl SoCs. + +Parent node should have the following properties : +- compatible: "syscon", "simple-mfd" +- reg: physical base address of the controller and length of memory mapped + region. + External clocks: The hosc clock used as input for the plls is generated outside the SoC. It is @@ -31,11 +36,15 @@ Actions Semi S900 CMU also requires one more clock: Example: Clock Management Unit node: - cmu: clock-controller@e0160000 { - compatible = "actions,s900-cmu"; + sysctrl: system-controller@e0160000 { + compatible = "syscon", "simple-mfd"; reg = <0x0 0xe0160000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; + + cmu: clock-controller { + compatible = "actions,s900-cmu"; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; }; Example: UART controller node that consumes clock generated by the clock From patchwork Wed Aug 1 03:39:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143226 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp345810ljj; Tue, 31 Jul 2018 20:40:44 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd72rff5WJr8m1KyzHYcfYnDxSEPerWx70qWVO9QHsTla1NJPtylGn61WEEasrQDUse2D4V X-Received: by 2002:a17:902:b28c:: with SMTP id u12-v6mr22551805plr.16.1533094844397; Tue, 31 Jul 2018 20:40:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533094844; cv=none; d=google.com; s=arc-20160816; b=L4KQbnT9Ftj4ENa19cDn9tkui8cX2XcRHTZrfljLBXMJL1zjncgiEovsV0AiNYSk3c rPrvzqTpjUmfnVxSBTxlQ3sKB2PZtKr/jHCOR54iGxxxddXOriw28j2anHIeXc40oETP s43K2LDlGCBa+kXT5mDrJ3gtkpnIZ0Eu4ig863EVyYsFL+Yt9KvmghN/150rTGbN9Jdq 0ybgef1ac8v7XtA4T4lYgUjvyghDuowCzal0+6lg0T3T+TC3ElrldV2UpxjkRRVZ+1UP nh+szMhc+wZJEdm60LgGXLgvA7YGYnxyN3u+0HddgQZtBpFHMhBzxuLA7I3TOtbHE5BL sFeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EEXePn8UN7dSUqDfcuEGMAS0yjzNV2Obe2xVPKlNrSQ=; b=Io305MTOkbmoS5oxXHICc28ykNGIS/VL2rsWWX2OaGfa77wD0wY4zsE0m3IVXkEBjw 1CbgQuR+TCAnsF/61zPHffbmLC2aLm8Ufi6ojFLP6J7+nNUt9UQGnRTnvRxl777ImMgx +qY2cJlmiWSOWnc4N0pSHgCSgQcGSqI6fItz1uWaRCLVIbhO0Wma5NqRQq0/dnlzoex6 k3Wf5FKYhV5rRK+4aopvzLTxhu7MKJacUMQjfpJmwo7HkceZGYUSlBSQVP3gOeOHWE/f SEXVMMS+JVmjDEAyXT4AChY0C1LzvhFd2L1mqRNzpX94QCVkk1KQNOoxeYDZbsSsUDX0 Y8WQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eQwdBQRj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i13-v6si14705366pgl.104.2018.07.31.20.40.44; Tue, 31 Jul 2018 20:40:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eQwdBQRj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732996AbeHAFYK (ORCPT + 5 others); Wed, 1 Aug 2018 01:24:10 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:47028 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732949AbeHAFYJ (ORCPT ); Wed, 1 Aug 2018 01:24:09 -0400 Received: by mail-pf1-f193.google.com with SMTP id u24-v6so7102967pfn.13 for ; Tue, 31 Jul 2018 20:40:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M7OYzCo+MTkBBAhtXTEUhwR+M+Mzm5uYQjGa03VQRRQ=; b=eQwdBQRjut1X7ipS/tHZLRByxGcWzAjH38jgUhYt5SpllPcqPF9FfHVJWjkh5Oaw1i RqoDYnAt/kEB3oIvoqyLiSVc3LN9zKeCR6SwdLTcAAuA3EoQOlYwP+21YnHL0DH3Gx/S B+dyQpgIdTHGZyW6/JMmPSmEUg4U8MODm1q40= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M7OYzCo+MTkBBAhtXTEUhwR+M+Mzm5uYQjGa03VQRRQ=; b=c/nenlB9IvGM2aW+d25Mk0l55VBnyaBNH7i5Rtdq5VWBUAEQVR+QTgJkUiq/w5E1ar WJ3lSsMG5W5sxCr1Nx1FrxEQGBVAEI+PKtU0aGldnBp4y6VqCckvu/TXcKtyVDD8ruDf X6c51SZDVCN4BBJ164RbbbCamqTDux5F+dlLDNZlvirLLsi5Dn8J2UtqRDhXspZ291lZ nftGJKpY6Pl82KDJ0j2to/i1Fzdov6PS08AVCXwNOE4YAAMJi5Sz+Q5UGI41mjjxleFT RqzwXT05wVou/XcCJdGUZboDy0F3ncCBNzGIboG74NDK7vzUgXSpzKs7bKH8rPIiTmvk /hSg== X-Gm-Message-State: AOUpUlE/1i8G8KwGbsfsbdSBipZTlQrzluqLgexcI/PsUHYkzDAI/ZgU +NWWlzGU7fX99wggk41JBlqY X-Received: by 2002:a63:d309:: with SMTP id b9-v6mr22821207pgg.163.1533094842491; Tue, 31 Jul 2018 20:40:42 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730e:f0ae:ac4e:9cdd:28a2:4bf9]) by smtp.gmail.com with ESMTPSA id d19-v6sm34879545pgi.50.2018.07.31.20.40.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 20:40:41 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, lee.jones@linaro.org, arnd@arndb.de Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 05/10] dt-bindings: reset: Add Actions Semi S700 SoC RMU support Date: Wed, 1 Aug 2018 09:09:10 +0530 Message-Id: <20180801033915.15880-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> References: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add RMU (Reset Management Unit) support for the Actions Semi S700 SoC which is a part of the Actions Semi Owl family series. Signed-off-by: Manivannan Sadhasivam --- .../bindings/reset/actions,owl-reset.txt | 8 +++-- include/dt-bindings/reset/actions,s700-rmu.h | 34 +++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/reset/actions,s700-rmu.h -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/reset/actions,owl-reset.txt b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt index 38e2c7051d86..a29950cb2db0 100644 --- a/Documentation/devicetree/bindings/reset/actions,owl-reset.txt +++ b/Documentation/devicetree/bindings/reset/actions,owl-reset.txt @@ -7,12 +7,14 @@ controller binding usage. The RMU registers are part of the system-controller block on Owl SoCs. Required properties: -- compatible: Should be "actions,s900-rmu" +- compatible: Should be one of the following, + "actions,s900-rmu" + "actions,s700-rmu" - #reset-cells: Should be 1 All available resets are defined as preprocessor macros in corresponding -dt-bindings/reset/actions,s900-rmu.h header and can be used in device -tree sources. +dt-bindings/reset/actions,s900-rmu.h or actions,s700-rmu.h header and can +be used in device tree sources. Parent node should have the following properties : - compatible: "syscon", "simple-mfd" diff --git a/include/dt-bindings/reset/actions,s700-rmu.h b/include/dt-bindings/reset/actions,s700-rmu.h new file mode 100644 index 000000000000..8c5d4d1b8bd4 --- /dev/null +++ b/include/dt-bindings/reset/actions,s700-rmu.h @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// +// Device Tree binding constants for Actions Semi S700 Reset Management Unit +// +// Copyright (c) 2018 Linaro Ltd. + +#ifndef _DT_BINDINGS_ACTIONS_S700_RESET_H +#define _DT_BINDINGS_ACTIONS_S700_RESET_H + +#define S700_RESET_AUDIO 0 +#define S700_RESET_CSI 1 +#define S700_RESET_DE 2 +#define S700_RESET_DSI 3 +#define S700_RESET_GPIO 4 +#define S700_RESET_I2C0 5 +#define S700_RESET_I2C1 6 +#define S700_RESET_I2C2 7 +#define S700_RESET_I2C3 8 +#define S700_RESET_KEY 9 +#define S700_RESET_LCD0 10 +#define S700_RESET_SI 11 +#define S700_RESET_SPI0 12 +#define S700_RESET_SPI1 13 +#define S700_RESET_SPI2 14 +#define S700_RESET_SPI3 15 +#define S700_RESET_UART0 16 +#define S700_RESET_UART1 17 +#define S700_RESET_UART2 18 +#define S700_RESET_UART3 19 +#define S700_RESET_UART4 20 +#define S700_RESET_UART5 21 +#define S700_RESET_UART6 22 + +#endif /* _DT_BINDINGS_ACTIONS_S700_RESET_H */ From patchwork Wed Aug 1 03:39:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143229 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp346197ljj; Tue, 31 Jul 2018 20:41:18 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdGGgNTT+FwIluHWKTDcjCEBscCPpkCFzYTGsO3t8QzRRGkZE4EOjAEtTyncI1jSNYmqMlq X-Received: by 2002:a17:902:b08d:: with SMTP id p13-v6mr23575340plr.0.1533094878752; Tue, 31 Jul 2018 20:41:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533094878; cv=none; d=google.com; s=arc-20160816; b=C/ZMGI4CUl0+WzlIhZmhdLQ+If/jQGr+vmqObPde75Hbn5Pd/AXPK/I8+rkqx4TpzW wR2dhCz8zII+UvebyHlMPOvPNrZQA968eIY7o0bUywPUbm7xcNYz+DAOFzH8ZpRefT6J OKkhg3AtIguu2s9d4xVIzJGKSYWLFccm07zZ4zwfEMc26SWLnBirxiJIsMIiuYrPXn1X n/pgxPMpPNIB3BtlPzzoukcdBGmqrQjPcuh6VaZ3f+BMabsXGB12+tn64mPaoBMy0cvt ADh96NV4NrILzwwDmniiWKhR29wP6WxgkFd9RP0Gv+V6yCuOA59Eus3i42evEhK6guCA FVBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xQxjNylUk5FX7q/CN1+L9s3yB8Qc0iyubk6EkfSA0WY=; b=niZ1AyKYXF/gq51ATdPsmGKkcDQ663PvTqLgnTYH9koBSpu+YNTmm8Z5pTd7WYStwa w5p3mgSz1rDyfRCNprR+AD3w3Z4bYr3m71dXf2lEvf6I+sv2+joytFeM9PxAciSkcpZb MN5NelTd/X11ulFo7XMGsL/5hmMPO+/mVAqk+CDHZa42IUm0ethrcx8DyOPF2SJ3tia2 qL9MK+qWt146n43FSBA8Ukh8ieTYDiAvaAF+9E5xqjW/9M3FL+UlAPkVa5LZqC1vQMn3 Ja2eWzt23jXk5P91Gc3rTBU9rviXVKqXI1GwttSmjwNmjC68UB7yKtx4OZ6CAhzC/jKh 1Gng== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JmFhY6wU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w4-v6si14056701ply.481.2018.07.31.20.41.18; Tue, 31 Jul 2018 20:41:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JmFhY6wU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727014AbeHAFYo (ORCPT + 5 others); Wed, 1 Aug 2018 01:24:44 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:46869 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727086AbeHAFYo (ORCPT ); Wed, 1 Aug 2018 01:24:44 -0400 Received: by mail-pg1-f193.google.com with SMTP id p23-v6so10084762pgv.13 for ; Tue, 31 Jul 2018 20:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PxN+gf+w78+YADjbR42aBtvvvKplQHOIyk/hNieyCu8=; b=JmFhY6wUal35qg8LmhjBsMdp6u3hji2Hb352hv2kWfSX7DpHfw8LaudjgDh/0WxWa/ +dytEaqbTKV81tlJVWYR4763uQvZuZ1Bozk/tCD/Um3r4hz2cJElj7QJRwfxiNZbXAMZ 5fRaYx4Xwp2K1ikpWHbcuX2+qEeCee6HEuI14= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PxN+gf+w78+YADjbR42aBtvvvKplQHOIyk/hNieyCu8=; b=QBf7PT0vPg0dX7pl1l7W7U+R93uQmxrgekb2C4Vjda0YTT0b2FS8+RnHptxF5tByhD ntAWTzU9ONOkWlmfZj3BUEN3/reH3J3+3kRYz2UcQBHsb9vXVHzc1okZSwzz/ITeljY3 Dzhud59pVmUv0dYDsXo1oFlVMzZlwxuDN5BpMG0sOiySyqqyMKFqT00w2a/YYTq2vIkZ ifUZv+v9Ry+coZbLr5So1FJg06fHdUilL7sZ9X7W9lYQYdVtNs5bLS+B3aaM3ZmhSgwL zYeQY26pKiI+0fvyKM0BKw/beoppQC1x8UxE2WO17Lfb2ZWYHOgl+vMeMtWDR1W0gViH TFSg== X-Gm-Message-State: AOUpUlE7gnCqTT0OJLy/IT6hG+Ry86NrcAAJ9M6VU1g1Owk5+ML2+eAm nBsYw+xcNxNVWNZ5roxf9UIL X-Received: by 2002:a63:3c0c:: with SMTP id j12-v6mr22584952pga.440.1533094876797; Tue, 31 Jul 2018 20:41:16 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730e:f0ae:ac4e:9cdd:28a2:4bf9]) by smtp.gmail.com with ESMTPSA id d19-v6sm34879545pgi.50.2018.07.31.20.41.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 20:41:16 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, lee.jones@linaro.org, arnd@arndb.de Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 08/10] reset: Add Actions Semi S900 SoC Reset Management Unit support Date: Wed, 1 Aug 2018 09:09:13 +0530 Message-Id: <20180801033915.15880-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> References: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Reset Management Unit (RMU) support for Actions Semi S900 SoC of the Owl family series. RMU belongs to the Owl SoCs system-controller which also includes CMU (Clock Management Unit). Signed-off-by: Manivannan Sadhasivam --- drivers/reset/Kconfig | 6 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-owl.c | 192 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+) create mode 100644 drivers/reset/reset-owl.c -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index c0b292be1b72..90627430569b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -73,6 +73,12 @@ config RESET_MESON help This enables the reset driver for Amlogic Meson SoCs. +config RESET_OWL + bool "Actions Semi Owl SoCs Reset Driver" if COMPILE_TEST + default ARCH_ACTIONS + help + This enables the reset controller driver for Actions Semi Owl SoCs. + config RESET_OXNAS bool diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index c1261dcfe9ad..fa655319cf17 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o +obj-$(CONFIG_RESET_OWL) += reset-owl.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o diff --git a/drivers/reset/reset-owl.c b/drivers/reset/reset-owl.c new file mode 100644 index 000000000000..c4f07691fb36 --- /dev/null +++ b/drivers/reset/reset-owl.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Actions Semi Owl SoCs Reset Management Unit driver +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include +#include +#include + +#include + +#define CMU_DEVRST0 0x00a8 +#define CMU_DEVRST1 0x00ac + +struct owl_reset_map { + u32 reg; + u32 bit; +}; + +struct owl_reset_hw { + const struct owl_reset_map *resets; + u32 num_resets; +}; + +struct owl_reset { + struct reset_controller_dev rcdev; + const struct owl_reset_hw *hw; + struct regmap *regmap; +}; + +static const struct owl_reset_map s900_resets[] = { + [S900_RESET_DMAC] = { CMU_DEVRST0, BIT(0) }, + [S900_RESET_SRAMI] = { CMU_DEVRST0, BIT(1) }, + [S900_RESET_DDR_CTL_PHY] = { CMU_DEVRST0, BIT(2) }, + [S900_RESET_NANDC0] = { CMU_DEVRST0, BIT(3) }, + [S900_RESET_SD0] = { CMU_DEVRST0, BIT(4) }, + [S900_RESET_SD1] = { CMU_DEVRST0, BIT(5) }, + [S900_RESET_PCM1] = { CMU_DEVRST0, BIT(6) }, + [S900_RESET_DE] = { CMU_DEVRST0, BIT(7) }, + [S900_RESET_LVDS] = { CMU_DEVRST0, BIT(8) }, + [S900_RESET_SD2] = { CMU_DEVRST0, BIT(9) }, + [S900_RESET_DSI] = { CMU_DEVRST0, BIT(10) }, + [S900_RESET_CSI0] = { CMU_DEVRST0, BIT(11) }, + [S900_RESET_BISP_AXI] = { CMU_DEVRST0, BIT(12) }, + [S900_RESET_CSI1] = { CMU_DEVRST0, BIT(13) }, + [S900_RESET_GPIO] = { CMU_DEVRST0, BIT(15) }, + [S900_RESET_EDP] = { CMU_DEVRST0, BIT(16) }, + [S900_RESET_AUDIO] = { CMU_DEVRST0, BIT(17) }, + [S900_RESET_PCM0] = { CMU_DEVRST0, BIT(18) }, + [S900_RESET_HDE] = { CMU_DEVRST0, BIT(21) }, + [S900_RESET_GPU3D_PA] = { CMU_DEVRST0, BIT(22) }, + [S900_RESET_IMX] = { CMU_DEVRST0, BIT(23) }, + [S900_RESET_SE] = { CMU_DEVRST0, BIT(24) }, + [S900_RESET_NANDC1] = { CMU_DEVRST0, BIT(25) }, + [S900_RESET_SD3] = { CMU_DEVRST0, BIT(26) }, + [S900_RESET_GIC] = { CMU_DEVRST0, BIT(27) }, + [S900_RESET_GPU3D_PB] = { CMU_DEVRST0, BIT(28) }, + [S900_RESET_DDR_CTL_PHY_AXI] = { CMU_DEVRST0, BIT(29) }, + [S900_RESET_CMU_DDR] = { CMU_DEVRST0, BIT(30) }, + [S900_RESET_DMM] = { CMU_DEVRST0, BIT(31) }, + [S900_RESET_USB2HUB] = { CMU_DEVRST1, BIT(0) }, + [S900_RESET_USB2HSIC] = { CMU_DEVRST1, BIT(1) }, + [S900_RESET_HDMI] = { CMU_DEVRST1, BIT(2) }, + [S900_RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) }, + [S900_RESET_UART6] = { CMU_DEVRST1, BIT(4) }, + [S900_RESET_UART0] = { CMU_DEVRST1, BIT(5) }, + [S900_RESET_UART1] = { CMU_DEVRST1, BIT(6) }, + [S900_RESET_UART2] = { CMU_DEVRST1, BIT(7) }, + [S900_RESET_SPI0] = { CMU_DEVRST1, BIT(8) }, + [S900_RESET_SPI1] = { CMU_DEVRST1, BIT(9) }, + [S900_RESET_SPI2] = { CMU_DEVRST1, BIT(10) }, + [S900_RESET_SPI3] = { CMU_DEVRST1, BIT(11) }, + [S900_RESET_I2C0] = { CMU_DEVRST1, BIT(12) }, + [S900_RESET_I2C1] = { CMU_DEVRST1, BIT(13) }, + [S900_RESET_USB3] = { CMU_DEVRST1, BIT(14) }, + [S900_RESET_UART3] = { CMU_DEVRST1, BIT(15) }, + [S900_RESET_UART4] = { CMU_DEVRST1, BIT(16) }, + [S900_RESET_UART5] = { CMU_DEVRST1, BIT(17) }, + [S900_RESET_I2C2] = { CMU_DEVRST1, BIT(18) }, + [S900_RESET_I2C3] = { CMU_DEVRST1, BIT(19) }, +}; + +static const struct owl_reset_hw s900_reset_hw = { + .resets = s900_resets, + .num_resets = ARRAY_SIZE(s900_resets), +}; + +static inline struct owl_reset *to_owl_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct owl_reset, rcdev); +} + +static int owl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->hw->resets[id]; + + return regmap_update_bits(reset->regmap, map->reg, map->bit, 0); +} + +static int owl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->hw->resets[id]; + + return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit); +} + +static int owl_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + owl_reset_assert(rcdev, id); + udelay(1); + owl_reset_deassert(rcdev, id); + + return 0; +} + +static int owl_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct owl_reset *reset = to_owl_reset(rcdev); + const struct owl_reset_map *map = &reset->hw->resets[id]; + u32 reg; + int ret; + + ret = regmap_read(reset->regmap, map->reg, ®); + if (ret) + return ret; + + /* + * The reset control API expects 0 if reset is not asserted, + * which is the opposite of what our hardware uses. + */ + return !(map->bit & reg); +} + +static const struct reset_control_ops owl_reset_ops = { + .assert = owl_reset_assert, + .deassert = owl_reset_deassert, + .reset = owl_reset_reset, + .status = owl_reset_status, +}; + +static int owl_reset_probe(struct platform_device *pdev) +{ + struct owl_reset *reset; + struct regmap *regmap; + const struct owl_reset_hw *hw; + + hw = of_device_get_match_data(&pdev->dev); + if (!hw) + return -EINVAL; + + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + regmap = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node)); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "failed to get regmap\n"); + return PTR_ERR(regmap); + } + + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.ops = &owl_reset_ops; + reset->rcdev.nr_resets = hw->num_resets; + reset->hw = hw; + reset->regmap = regmap; + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + +static const struct of_device_id owl_reset_of_match[] = { + { .compatible = "actions,s900-rmu", .data = &s900_reset_hw }, + { /* sentinel */ } +}; + +static struct platform_driver owl_reset_driver = { + .probe = owl_reset_probe, + .driver = { + .name = "owl-reset", + .of_match_table = owl_reset_of_match, + }, +}; +builtin_platform_driver(owl_reset_driver); From patchwork Wed Aug 1 03:39:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143231 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp346438ljj; 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[209.132.180.67]) by mx.google.com with ESMTP id m9-v6si13403089pgq.172.2018.07.31.20.41.39; Tue, 31 Jul 2018 20:41:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hij93kMT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731952AbeHAFZF (ORCPT + 5 others); Wed, 1 Aug 2018 01:25:05 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34787 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731932AbeHAFZF (ORCPT ); Wed, 1 Aug 2018 01:25:05 -0400 Received: by mail-pf1-f195.google.com with SMTP id k19-v6so7112796pfi.1 for ; Tue, 31 Jul 2018 20:41:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pMtZkUiBZBqnYApmovi97PV8cm0Fy0bqoc/nFXRacRI=; b=hij93kMT5GeMSDfBuPnFlKTJS36dUKeGmXoOl95ekzU5LUOIV6V4MMYJfNZR/fq9kP UKkTm4JW1YEZDeIPLLLJ5/ZPWOz2NF0PCkJvhUYcKG9Bp7OTcHwEdruU+tE2XCVxpJgy qYIxPDZNT88bUZBKqOH0MXZHLmTPKl5T5a444= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pMtZkUiBZBqnYApmovi97PV8cm0Fy0bqoc/nFXRacRI=; b=KQWPwKUIx2co3PLhtYUZo3H+mMfvzYjbzoL1xiy1dr4DrT/NjLZMP4ML/aCpp7jSxb U8PK5+mV0qs+UL9tUF2fSSybxhRx88V/x6D3xnPfNMuHfbRndKDz23qucEwLy06xB8hu 5RM/qu/QMc3owir/8AaCU80kpXA520988QY1l59lLOC4BYJlolrr75on/2/mKDnYqnh9 Y/28nl7OH8A4548JduAGzMJFXhnuit5l+7BwQbvME9Xa7d9YdYah5e0qOGI0mdcjSGk2 H7dr12RoqqrMdFksK0UqD5RzjGg3QWR7ReK9jPRWrSzrbpVNOLH2d6bbN0WVAJj3MJrN vRVA== X-Gm-Message-State: AOUpUlG5s2/9XklYAn/penh+3oMtqtxcDm2VWp7GZ0/s4ehJGax+Vwy+ iR1NxpgrHc3RnLUFHvLD77Tt X-Received: by 2002:a63:c60:: with SMTP id 32-v6mr23092486pgm.155.1533094897467; Tue, 31 Jul 2018 20:41:37 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730e:f0ae:ac4e:9cdd:28a2:4bf9]) by smtp.gmail.com with ESMTPSA id d19-v6sm34879545pgi.50.2018.07.31.20.41.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Jul 2018 20:41:36 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, lee.jones@linaro.org, arnd@arndb.de Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 10/10] MAINTAINERS: Add entry for Actions Semi Owl SoCs Reset Management Unit Date: Wed, 1 Aug 2018 09:09:15 +0530 Message-Id: <20180801033915.15880-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> References: <20180801033915.15880-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add entry for Actions Semi Reset Management Unit driver and its bindings under ARCH_ACTIONS. Currently only S700 and S900 SoCs of the Owl family are supported. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/MAINTAINERS b/MAINTAINERS index 9c292ef3c210..25934ae77ba6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1146,13 +1146,17 @@ F: arch/arm64/boot/dts/actions/ F: drivers/clk/actions/ F: drivers/clocksource/owl-* F: drivers/pinctrl/actions/* +F: drivers/reset/reset-owl.c F: drivers/soc/actions/ F: include/dt-bindings/power/owl-* +F: include/dt-bindings/reset/actions,s700-rmu.h +F: include/dt-bindings/reset/actions,s900-rmu.h F: include/linux/soc/actions/ F: Documentation/devicetree/bindings/arm/actions.txt F: Documentation/devicetree/bindings/clock/actions,s900-cmu.txt F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt F: Documentation/devicetree/bindings/power/actions,owl-sps.txt +F: Documentation/devicetree/bindings/reset/actions,owl-reset.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt ARM/ADS SPHERE MACHINE SUPPORT