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Sat, 12 Jun 2021 16:05:07 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Rob Herring Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c Date: Sat, 12 Jun 2021 21:34:14 +0530 Message-Id: <20210612160422.330705-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com> References: <20210612160422.330705-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.205] X-ClientProxiedBy: MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.205) by MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend Transport; 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Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/kernel/smp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 547dc508f7d1..eea0c9d11d9f 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -8,6 +8,7 @@ * Copyright (C) 2017 SiFive */ +#define pr_fmt(fmt) "riscv: " fmt #include #include #include @@ -114,7 +115,7 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) if (ipi_ops && ipi_ops->ipi_inject) ipi_ops->ipi_inject(mask); else - pr_warn("SMP: IPI inject method not available\n"); + pr_warn("IPI inject method not available\n"); } static void send_ipi_single(int cpu, enum ipi_message_type op) @@ -126,7 +127,7 @@ static void send_ipi_single(int cpu, enum ipi_message_type op) if (ipi_ops && ipi_ops->ipi_inject) ipi_ops->ipi_inject(cpumask_of(cpu)); else - pr_warn("SMP: IPI inject method not available\n"); + pr_warn("IPI inject method not available\n"); } #ifdef CONFIG_IRQ_WORK @@ -242,7 +243,7 @@ void smp_send_stop(void) cpumask_clear_cpu(smp_processor_id(), &mask); if (system_state <= SYSTEM_RUNNING) - pr_crit("SMP: stopping secondary CPUs\n"); + pr_crit("stopping secondary CPUs\n"); send_ipi_mask(&mask, IPI_CPU_STOP); } @@ -252,7 +253,7 @@ void smp_send_stop(void) udelay(1); if (num_online_cpus() > 1) - pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", + pr_warn("failed to stop secondary CPUs %*pbl\n", cpumask_pr_args(cpu_online_mask)); } From patchwork Sat Jun 12 16:04:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 459245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B26F4C49360 for ; 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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from CO6PR04MB7812.namprd04.prod.outlook.com (10.242.165.134) by CO6PR04MB7795.namprd04.prod.outlook.com (10.242.164.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.23; Sat, 12 Jun 2021 16:05:18 +0000 Received: from CO6PR04MB7812.namprd04.prod.outlook.com ([fe80::a153:b7f8:c87f:89f8]) by CO6PR04MB7812.namprd04.prod.outlook.com ([fe80::a153:b7f8:c87f:89f8%9]) with mapi id 15.20.4219.025; Sat, 12 Jun 2021 16:05:18 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Rob Herring Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible Date: Sat, 12 Jun 2021 21:34:16 +0530 Message-Id: <20210612160422.330705-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com> References: <20210612160422.330705-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.205] X-ClientProxiedBy: MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.205) by MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend Transport; 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It is now possible to have specialized hardware (such as RISC-V AIA) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote TLB flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 14 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 720b443c4528..009c56fa102d 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -1,39 +1,73 @@ // SPDX-License-Identifier: GPL-2.0 +/* + * TLB flush implementation. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ #include #include #include #include +static void ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (!riscv_use_ipi_for_rfence()) + sbi_remote_sfence_vma(NULL, 0, -1); + else + on_each_cpu(ipi_flush_tlb_all, NULL, 1); +} + +struct flush_range_data { + unsigned long start; + unsigned long size; +}; + +static void ipi_flush_range(void *info) +{ + struct flush_range_data *data = info; + + /* local cpu is the only cpu present in cpumask */ + if (data->size <= PAGE_SIZE) + local_flush_tlb_page(data->start); + else + local_flush_tlb_all(); } /* - * This function must not be called with cmask being null. + * This function must not be called with NULL cpumask. * Kernel may panic if cmask is NULL. */ -static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, - unsigned long size) +static void flush_range(struct cpumask *cmask, unsigned long start, + unsigned long size) { + struct flush_range_data info; struct cpumask hmask; unsigned int cpuid; if (cpumask_empty(cmask)) return; + info.start = start; + info.size = size; + cpuid = get_cpu(); if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { - /* local cpu is the only cpu present in cpumask */ - if (size <= PAGE_SIZE) - local_flush_tlb_page(start); - else - local_flush_tlb_all(); + ipi_flush_range(&info); } else { - riscv_cpuid_to_hartid_mask(cmask, &hmask); - sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size); + if (!riscv_use_ipi_for_rfence()) { + riscv_cpuid_to_hartid_mask(cmask, &hmask); + sbi_remote_sfence_vma(cpumask_bits(&hmask), + start, size); + } else { + on_each_cpu_mask(cmask, ipi_flush_range, &info, 1); + } } put_cpu(); @@ -41,16 +75,16 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); + flush_range(mm_cpumask(mm), 0, -1); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); + flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); + flush_range(mm_cpumask(vma->vm_mm), start, end - start); } From patchwork Sat Jun 12 16:04:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 459244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7E5BC48BE8 for ; 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Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/Kconfig.socs | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index ed963761fbd2..2687a0902ec4 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -27,6 +27,7 @@ config SOC_VIRT select GOLDFISH select RTC_DRV_GOLDFISH if RTC_CLASS select SIFIVE_PLIC + select RISCV_ACLINT_SWI help This enables support for QEMU Virt Machine. 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Sat, 12 Jun 2021 16:05:35 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Rob Herring Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Date: Sat, 12 Jun 2021 21:34:19 +0530 Message-Id: <20210612160422.330705-8-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com> References: <20210612160422.330705-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.205] X-ClientProxiedBy: MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.205) by MA1PR0101CA0052.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend Transport; 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This patch extends the CLINT driver to support both CLINT device and ACLINT MTIMER device. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index dfdcd94c1fd5..ca329c450810 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -2,8 +2,15 @@ /* * Copyright (C) 2020 Western Digital Corporation or its affiliates. * - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a - * CLINT MMIO timer device. + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT + * MMIO device which is a composite device capable of injecting M-mode + * software interrupts and M-mode timer interrupts. + * + * The RISC-V ACLINT specification is modular in nature and defines + * separate devices for M-mode software interrupt (MSWI), M-mode timer + * (MTIMER) and S-mode software interrupt (SSWI). + * + * This is a common driver for CLINT device and ACLINT MTIMER device. */ #define pr_fmt(fmt) "clint: " fmt @@ -21,14 +28,20 @@ #include #include -#ifndef CONFIG_RISCV_M_MODE +#ifdef CONFIG_RISCV_M_MODE #include + +u64 __iomem *clint_time_val; +EXPORT_SYMBOL(clint_time_val); #endif #define CLINT_IPI_OFF 0 #define CLINT_TIMER_CMP_OFF 0x4000 #define CLINT_TIMER_VAL_OFF 0xbff8 +#define ACLINT_MTIMER_CMP_OFF 0x0000 +#define ACLINT_MTIMER_VAL_OFF 0x7ff8 + /* CLINT manages IPI and Timer for RISC-V M-mode */ static u32 __iomem *clint_ipi_base; static u64 __iomem *clint_timer_cmp; @@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; -#ifdef CONFIG_RISCV_M_MODE -u64 __iomem *clint_time_val; -EXPORT_SYMBOL(clint_time_val); -#endif - static void clint_send_ipi(const struct cpumask *target) { unsigned int cpu; @@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np) return -ENODEV; } - clint_ipi_base = base + CLINT_IPI_OFF; - clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; - clint_timer_val = base + CLINT_TIMER_VAL_OFF; + if (of_device_is_compatible(np, "riscv,aclint-mtimer")) { + clint_ipi_base = NULL; + clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF; + clint_timer_val = base + ACLINT_MTIMER_VAL_OFF; + } else { + clint_ipi_base = base + CLINT_IPI_OFF; + clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; + clint_timer_val = base + CLINT_TIMER_VAL_OFF; + } clint_timer_freq = riscv_timebase; #ifdef CONFIG_RISCV_M_MODE @@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np) goto fail_free_irq; } - riscv_set_ipi_ops(&clint_ipi_ops); - clint_clear_ipi(); + if (clint_ipi_base) { + riscv_set_ipi_ops(&clint_ipi_ops); + clint_clear_ipi(); + } return 0; @@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np) TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt); From patchwork Sat Jun 12 16:04:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 459242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE377C48BCF for ; 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Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b706dd20ff2b..aee0123438f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15693,6 +15693,15 @@ S: Maintained F: drivers/mtd/nand/raw/r852.c F: drivers/mtd/nand/raw/r852.h +RISC-V ACLINT DRIVERS +M: Anup Patel +L: linux-riscv@lists.infradead.org +S: Supported +F: Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml +F: Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml +F: drivers/clocksource/timer-clint.c +F: drivers/irqchip/irq-aclint-swi.c + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt