From patchwork Fri Jul 27 09:37:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143020 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp599278ljj; Fri, 27 Jul 2018 02:39:40 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdIP6+/qindxdY/eYFzR4Ox5GqMU3G7tHADxWiyxasCXOhcrpjnpOezRV6dE5yEPfxf6CK0 X-Received: by 2002:a65:66d7:: with SMTP id c23-v6mr5380860pgw.427.1532684380692; Fri, 27 Jul 2018 02:39:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684380; cv=none; d=google.com; s=arc-20160816; b=hNY//FB/g2VXftm9QLNGkq8Qz/VvBA06WtDLhkdQiUo3aK3g8MOEl6dqnLEkDObjh5 S8/OZJy97dwzjk+10eySYbcvtugDYxCx9E57b8MKgtXdZeK0yWIMRitF+QHyrfximGNs Yxg55troWTz8Ev3wbumvbz2un12txSsJx1Ha0hyQ7Xg6vn+2ypV1S45fwMTBg/QCcHxR 5UijMg4m8fruh0ca7CdIhn//J3my6YF0Jfbb2Rg1GafeklVAlG/rOBJ+zY7hz81jDq1E F6s97fdZ2qumpIbKiKNWwQ4niJy0lu6sEoHKUNnSWk11403Q+RhCPck8cTOMRZYZc4AQ qNWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=JvO9kZzIcehpQuqaePH+VudAPlD8kmg/tF90oQwdldo=; b=AuwH877sXTltrSOpxCqE4LVVf9bEQPw062cm6R9aeSRwXOeo4QPfGphzf2InPHbHBp vev6qjGezU+/j5rgQOldI2+BJUpn03UvRylPQFiNYd5H+kfeZUNP9hrOOHmEvulgXFNo jW75BgYSTy6eLGTwl4aac2yMFt30driMjmedsSjScxYO9Zo47qS9FqMRTg3DcN+0y2K8 7pAg0a1u7UuTgyfZ3K/jPW2/IHeHy6SAOVlm3YXzOzDlePn7NdsM5Mz7vVFGt3+YCWZK SNdvi2lJKnmwbd2MxzEeFtZ640Ja2s5x0gIZ9sQmM9fT/RBmCP3bv5j3YCLr7MBaJ3be VxwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DlIVFCrV; spf=pass (google.com: domain of gcc-patches-return-482506-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482506-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id t9-v6si3578849pgr.244.2018.07.27.02.39.40 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:39:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482506-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DlIVFCrV; spf=pass (google.com: domain of gcc-patches-return-482506-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482506-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=quxaKRJ1QSfMiTkA L52YfXi8P4jqIdCZB4ZJ7hKDQZA5s8ZEBDVgz75byCUiGGbfO5Y6vWKt5fDAWo+s BuaiPuVq/g55Nahlo9LDwtuH69X2tv7yOqSFpNBwI70QqK6d68PpbOHuhPt4aP4R 4aa/ZvPaRe85dkYD2z43AThVFFk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=Gg+PysZT8KLoSyotG/Nhf3 CKslM=; b=DlIVFCrVGCOonnBhIadH4G5r1xmbesqE3wsXm1gI0SaTOkVFJPleGB OYwdntla1FiUBc9us6TvsM6SiEtPjMTxeh3Y4oij6oWHg+99HIahZ7NCqC+qi1PL n6hURvDm54DtOVSYNpOgavSqKC97f+REl+gcW6Zr83eX45bmOiQcU= Received: (qmail 47054 invoked by alias); 27 Jul 2018 09:38:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 46747 invoked by uid 89); 27 Jul 2018 09:38:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2858815BE; Fri, 27 Jul 2018 02:38:24 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A41693F575; Fri, 27 Jul 2018 02:38:22 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org, joseph@codesourcery.com, jason@redhat.com, nathan@acm.org Cc: Richard Earnshaw , rguenther@suse.de Subject: [PATCH 01/11] Add __builtin_speculation_safe_value Date: Fri, 27 Jul 2018 10:37:45 +0100 Message-Id: <1532684275-13041-2-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 This patch defines a new intrinsic function __builtin_speculation_safe_value. A generic default implementation is defined which will attempt to use the backend pattern "speculation_safe_barrier". If this pattern is not defined, or if it is not available, then the compiler will emit a warning, but compilation will continue. Note that the test spec-barrier-1.c will currently fail on all targets. This is deliberate, the failure will go away when appropriate action is taken for each target backend. gcc: * builtin-types.def (BT_FN_PTR_PTR_VAR): New function type. (BT_FN_I1_I1_VAR, BT_FN_I2_I2_VAR, BT_FN_I4_I4_VAR): Likewise. (BT_FN_I8_I8_VAR, BT_FN_I16_I16_VAR): Likewise. * builtin-attrs.def (ATTR_NOVOPS_NOTHROW_LEAF_LIST): New attribute list. * builtins.def (BUILT_IN_SPECULATION_SAFE_VALUE_N): New builtin. (BUILT_IN_SPECULATION_SAFE_VALUE_PTR): New internal builtin. (BUILT_IN_SPECULATION_SAFE_VALUE_1): Likewise. (BUILT_IN_SPECULATION_SAFE_VALUE_2): Likewise. (BUILT_IN_SPECULATION_SAFE_VALUE_4): Likewise. (BUILT_IN_SPECULATION_SAFE_VALUE_8): Likewise. (BUILT_IN_SPECULATION_SAFE_VALUE_16): Likewise. * builtins.c (expand_speculation_safe_value): New function. (expand_builtin): Call it. * doc/cpp.texi: Document predefine __HAVE_SPECULATION_SAFE_VALUE. * doc/extend.texi: Document __builtin_speculation_safe_value. * doc/md.texi: Document "speculation_barrier" pattern. * doc/tm.texi.in: Pull in TARGET_SPECULATION_SAFE_VALUE and TARGET_HAVE_SPECULATION_SAFE_VALUE. * doc/tm.texi: Regenerated. * target.def (have_speculation_safe_value, speculation_safe_value): New hooks. * targhooks.c (default_have_speculation_safe_value): New function. (default_speculation_safe_value): New function. * targhooks.h (default_have_speculation_safe_value): Add prototype. (default_speculation_safe_value): Add prototype. c-family: * c-common.c (speculation_safe_resolve_call): New function. (speculation_safe_resolve_params): New function. (speculation_safe_resolve_return): New function. (resolve_overloaded_builtin): Handle __builtin_speculation_safe_value. * c-cppbuiltin.c (c_cpp_builtins): Add pre-define for __HAVE_SPECULATION_SAFE_VALUE. testsuite: * c-c++-common/spec-barrier-1.c: New test. * c-c++-common/spec-barrier-2.c: New test. * gcc.dg/spec-barrier-3.c: New test. --- gcc/builtin-attrs.def | 2 + gcc/builtin-types.def | 6 + gcc/builtins.c | 60 ++++++++++ gcc/builtins.def | 22 ++++ gcc/c-family/c-common.c | 164 ++++++++++++++++++++++++++++ gcc/c-family/c-cppbuiltin.c | 7 +- gcc/doc/cpp.texi | 4 + gcc/doc/extend.texi | 91 +++++++++++++++ gcc/doc/md.texi | 15 +++ gcc/doc/tm.texi | 31 ++++++ gcc/doc/tm.texi.in | 4 + gcc/target.def | 35 ++++++ gcc/targhooks.c | 32 ++++++ gcc/targhooks.h | 3 + gcc/testsuite/c-c++-common/spec-barrier-1.c | 38 +++++++ gcc/testsuite/c-c++-common/spec-barrier-2.c | 17 +++ gcc/testsuite/gcc.dg/spec-barrier-3.c | 13 +++ 17 files changed, 543 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/c-c++-common/spec-barrier-1.c create mode 100644 gcc/testsuite/c-c++-common/spec-barrier-2.c create mode 100644 gcc/testsuite/gcc.dg/spec-barrier-3.c diff --git a/gcc/builtin-attrs.def b/gcc/builtin-attrs.def index 300ba65..e245e4d 100644 --- a/gcc/builtin-attrs.def +++ b/gcc/builtin-attrs.def @@ -129,6 +129,8 @@ DEF_ATTR_TREE_LIST (ATTR_NOTHROW_LIST, ATTR_NOTHROW, ATTR_NULL, ATTR_NULL) DEF_ATTR_TREE_LIST (ATTR_NOTHROW_LEAF_LIST, ATTR_LEAF, ATTR_NULL, ATTR_NOTHROW_LIST) +DEF_ATTR_TREE_LIST (ATTR_NOVOPS_NOTHROW_LEAF_LIST, ATTR_NOVOPS, \ + ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_LIST, ATTR_CONST, \ ATTR_NULL, ATTR_NOTHROW_LIST) DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_LEAF_LIST, ATTR_CONST, \ diff --git a/gcc/builtin-types.def b/gcc/builtin-types.def index b01095c..70fae35 100644 --- a/gcc/builtin-types.def +++ b/gcc/builtin-types.def @@ -763,6 +763,12 @@ DEF_FUNCTION_TYPE_VAR_1 (BT_FN_VOID_LONG_VAR, BT_VOID, BT_LONG) DEF_FUNCTION_TYPE_VAR_1 (BT_FN_VOID_ULL_VAR, BT_VOID, BT_ULONGLONG) +DEF_FUNCTION_TYPE_VAR_1 (BT_FN_PTR_PTR_VAR, BT_PTR, BT_PTR) +DEF_FUNCTION_TYPE_VAR_1 (BT_FN_I1_I1_VAR, BT_I1, BT_I1) +DEF_FUNCTION_TYPE_VAR_1 (BT_FN_I2_I2_VAR, BT_I2, BT_I2) +DEF_FUNCTION_TYPE_VAR_1 (BT_FN_I4_I4_VAR, BT_I4, BT_I4) +DEF_FUNCTION_TYPE_VAR_1 (BT_FN_I8_I8_VAR, BT_I8, BT_I8) +DEF_FUNCTION_TYPE_VAR_1 (BT_FN_I16_I16_VAR, BT_I16, BT_I16) DEF_FUNCTION_TYPE_VAR_2 (BT_FN_INT_FILEPTR_CONST_STRING_VAR, BT_INT, BT_FILEPTR, BT_CONST_STRING) diff --git a/gcc/builtins.c b/gcc/builtins.c index 839a818..c954f11 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -6881,6 +6881,55 @@ inline_expand_builtin_string_cmp (tree exp, rtx target, bool is_memcmp) const_str_n, mode, is_memcmp); } +/* Expand a call to __builtin_speculation_safe_value_. MODE + represents the size of the first argument to that call, or VOIDmode + if the argument is a pointer. IGNORE will be true if the result + isn't used. */ +static rtx +expand_speculation_safe_value (machine_mode mode, tree exp, rtx target, + bool ignore) +{ + rtx val, failsafe; + unsigned nargs = call_expr_nargs (exp); + + tree arg0 = CALL_EXPR_ARG (exp, 0); + + if (mode == VOIDmode) + { + mode = TYPE_MODE (TREE_TYPE (arg0)); + gcc_assert (GET_MODE_CLASS (mode) == MODE_INT); + } + + val = expand_expr (arg0, NULL_RTX, mode, EXPAND_NORMAL); + + /* An optional second argument can be used as a failsafe value on + some machines. If it isn't present, then the failsafe value is + assumed to be 0. */ + if (nargs > 1) + { + tree arg1 = CALL_EXPR_ARG (exp, 1); + failsafe = expand_expr (arg1, NULL_RTX, mode, EXPAND_NORMAL); + } + else + failsafe = const0_rtx; + + /* If the result isn't used, the behavior is undefined. It would be + nice to emit a warning here, but path splitting means this might + happen with legitimate code. So simply drop the builtin + expansion in that case; we've handled any side-effects above. */ + if (ignore) + return const0_rtx; + + /* If we don't have a suitable target, create one to hold the result. */ + if (target == NULL || GET_MODE (target) != mode) + target = gen_reg_rtx (mode); + + if (GET_MODE (val) != mode && GET_MODE (val) != VOIDmode) + val = convert_modes (mode, VOIDmode, val, false); + + return targetm.speculation_safe_value (mode, target, val, failsafe); +} + /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). @@ -7992,6 +8041,17 @@ expand_builtin (tree exp, rtx target, rtx subtarget, machine_mode mode, case BUILT_IN_GOACC_PARLEVEL_SIZE: return expand_builtin_goacc_parlevel_id_size (exp, target, ignore); + case BUILT_IN_SPECULATION_SAFE_VALUE_PTR: + return expand_speculation_safe_value (VOIDmode, exp, target, ignore); + + case BUILT_IN_SPECULATION_SAFE_VALUE_1: + case BUILT_IN_SPECULATION_SAFE_VALUE_2: + case BUILT_IN_SPECULATION_SAFE_VALUE_4: + case BUILT_IN_SPECULATION_SAFE_VALUE_8: + case BUILT_IN_SPECULATION_SAFE_VALUE_16: + mode = get_builtin_sync_mode (fcode - BUILT_IN_SPECULATION_SAFE_VALUE_1); + return expand_speculation_safe_value (mode, exp, target, ignore); + default: /* just do library call, if unknown builtin */ break; } diff --git a/gcc/builtins.def b/gcc/builtins.def index aacbd51..ad90d44 100644 --- a/gcc/builtins.def +++ b/gcc/builtins.def @@ -1003,6 +1003,28 @@ DEF_BUILTIN (BUILT_IN_EMUTLS_REGISTER_COMMON, true, true, true, ATTR_NOTHROW_LEAF_LIST, false, !targetm.have_tls) +/* Suppressing speculation. Users are expected to use the first (N) + variant, which will be translated internally into one of the other + types. */ + +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_N, "speculation_safe_value", + BT_FN_VOID_VAR, ATTR_NOVOPS_NOTHROW_LEAF_LIST) + +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_PTR, + "speculation_safe_value_ptr", BT_FN_PTR_PTR_VAR, + ATTR_NOVOPS_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_1, "speculation_safe_value_1", + BT_FN_I1_I1_VAR, ATTR_NOVOPS_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_2, "speculation_safe_value_2", + BT_FN_I2_I2_VAR, ATTR_NOVOPS_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_4, "speculation_safe_value_4", + BT_FN_I4_I4_VAR, ATTR_NOVOPS_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_8, "speculation_safe_value_8", + BT_FN_I8_I8_VAR, ATTR_NOVOPS_NOTHROW_LEAF_LIST) +DEF_GCC_BUILTIN (BUILT_IN_SPECULATION_SAFE_VALUE_16, + "speculation_safe_value_16", BT_FN_I16_I16_VAR, + ATTR_NOVOPS_NOTHROW_LEAF_LIST) + /* Exception support. */ DEF_BUILTIN_STUB (BUILT_IN_UNWIND_RESUME, "__builtin_unwind_resume") DEF_BUILTIN_STUB (BUILT_IN_CXA_END_CLEANUP, "__builtin_cxa_end_cleanup") diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index f5e1111..e368fd2 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -6457,6 +6457,122 @@ builtin_type_for_size (int size, bool unsignedp) return type ? type : error_mark_node; } +/* Work out the size of the first argument of a call to + __builtin_speculation_safe_value. Only pointers and integral types + are permitted. Return -1 if the argument type is not supported or + the size is too large; 0 if the argument type is a pointer or the + size if it is integral. */ +static enum built_in_function +speculation_safe_value_resolve_call (tree function, vec *params) +{ + /* Type of the argument. */ + tree type; + int size; + + if (vec_safe_is_empty (params)) + { + error ("too few arguments to function %qE", function); + return BUILT_IN_NONE; + } + + type = TREE_TYPE ((*params)[0]); + if (TREE_CODE (type) == ARRAY_TYPE && c_dialect_cxx ()) + { + /* Force array-to-pointer decay for C++. */ + (*params)[0] = default_conversion ((*params)[0]); + type = TREE_TYPE ((*params)[0]); + } + + if (POINTER_TYPE_P (type)) + return BUILT_IN_SPECULATION_SAFE_VALUE_PTR; + + if (!INTEGRAL_TYPE_P (type)) + goto incompatible; + + if (!COMPLETE_TYPE_P (type)) + goto incompatible; + + size = tree_to_uhwi (TYPE_SIZE_UNIT (type)); + if (size == 1 || size == 2 || size == 4 || size == 8 || size == 16) + return ((enum built_in_function) + ((int) BUILT_IN_SPECULATION_SAFE_VALUE_1 + exact_log2 (size))); + + incompatible: + /* Issue the diagnostic only if the argument is valid, otherwise + it would be redundant at best and could be misleading. */ + if (type != error_mark_node) + error ("operand type %qT is incompatible with argument %d of %qE", + type, 1, function); + + return BUILT_IN_NONE; +} + +/* Validate and coerce PARAMS, the arguments to ORIG_FUNCTION to fit + the prototype for FUNCTION. The first argument is mandatory, a second + argument, if present, must be type compatible with the first. */ +static bool +speculation_safe_value_resolve_params (location_t loc, tree orig_function, + vec *params) +{ + tree val; + + if (params->length () == 0) + { + error_at (loc, "too few arguments to function %qE", orig_function); + return false; + } + + else if (params->length () > 2) + { + error_at (loc, "too many arguments to function %qE", orig_function); + return false; + } + + val = (*params)[0]; + if (TREE_CODE (TREE_TYPE (val)) == ARRAY_TYPE) + val = default_conversion (val); + if (!(TREE_CODE (TREE_TYPE (val)) == POINTER_TYPE + || TREE_CODE (TREE_TYPE (val)) == INTEGER_TYPE)) + { + error_at (loc, + "expecting argument of type pointer or of type integer " + "for argument 1"); + return false; + } + (*params)[0] = val; + + if (params->length () == 2) + { + tree val2 = (*params)[1]; + if (TREE_CODE (TREE_TYPE (val2)) == ARRAY_TYPE) + val2 = default_conversion (val2); + if (!(TREE_TYPE (val) == TREE_TYPE (val2) + || useless_type_conversion_p (TREE_TYPE (val), TREE_TYPE (val2)))) + { + error_at (loc, "both arguments must be compatible"); + return false; + } + (*params)[1] = val2; + } + + return true; +} + +/* Cast the result of the builtin back to the type of the first argument, + preserving any qualifiers that it might have. */ +static tree +speculation_safe_value_resolve_return (tree first_param, tree result) +{ + tree ptype = TREE_TYPE (first_param); + tree rtype = TREE_TYPE (result); + ptype = TYPE_MAIN_VARIANT (ptype); + + if (tree_int_cst_equal (TYPE_SIZE (ptype), TYPE_SIZE (rtype))) + return convert (ptype, result); + + return result; +} + /* A helper function for resolve_overloaded_builtin in resolving the overloaded __sync_ builtins. Returns a positive power of 2 if the first operand of PARAMS is a pointer to a supported data type. @@ -7111,6 +7227,54 @@ resolve_overloaded_builtin (location_t loc, tree function, /* Handle BUILT_IN_NORMAL here. */ switch (orig_code) { + case BUILT_IN_SPECULATION_SAFE_VALUE_N: + { + tree new_function, first_param, result; + enum built_in_function fncode + = speculation_safe_value_resolve_call (function, params);; + + first_param = (*params)[0]; + if (fncode == BUILT_IN_NONE + || !speculation_safe_value_resolve_params (loc, function, params)) + return error_mark_node; + + if (targetm.have_speculation_safe_value (true)) + { + new_function = builtin_decl_explicit (fncode); + result = build_function_call_vec (loc, vNULL, new_function, params, + NULL); + + if (result == error_mark_node) + return result; + + return speculation_safe_value_resolve_return (first_param, result); + } + else + { + /* This target doesn't have, or doesn't need, active mitigation + against incorrect speculative execution. Simply return the + first parameter to the builtin. */ + if (!targetm.have_speculation_safe_value (false)) + /* The user has invoked __builtin_speculation_safe_value + even though __HAVE_SPECULATION_SAFE_VALUE is not + defined: emit a warning. */ + warning_at (input_location, 0, + "this target does not define a speculation barrier; " + "your program will still execute correctly, " + "but incorrect speculation may not be be " + "restricted"); + + /* If the optional second argument is present, handle any side + effects now. */ + if (params->length () == 2 + && TREE_SIDE_EFFECTS ((*params)[1])) + return build2 (COMPOUND_EXPR, TREE_TYPE (first_param), + (*params)[1], first_param); + + return first_param; + } + } + case BUILT_IN_ATOMIC_EXCHANGE: case BUILT_IN_ATOMIC_COMPARE_EXCHANGE: case BUILT_IN_ATOMIC_LOAD: diff --git a/gcc/c-family/c-cppbuiltin.c b/gcc/c-family/c-cppbuiltin.c index bdb5691..4fcf3a6 100644 --- a/gcc/c-family/c-cppbuiltin.c +++ b/gcc/c-family/c-cppbuiltin.c @@ -1361,7 +1361,12 @@ c_cpp_builtins (cpp_reader *pfile) cpp_define (pfile, "__WCHAR_UNSIGNED__"); cpp_atomic_builtins (pfile); - + + /* Show support for __builtin_speculation_safe_value () if the target + has been updated to fully support it. */ + if (targetm.have_speculation_safe_value (false)) + cpp_define (pfile, "__HAVE_SPECULATION_SAFE_VALUE"); + #ifdef DWARF2_UNWIND_INFO if (dwarf2out_do_cfi_asm ()) cpp_define (pfile, "__GCC_HAVE_DWARF2_CFI_ASM"); diff --git a/gcc/doc/cpp.texi b/gcc/doc/cpp.texi index 3f7a8fc..efad2c8 100644 --- a/gcc/doc/cpp.texi +++ b/gcc/doc/cpp.texi @@ -2381,6 +2381,10 @@ If GCC cannot determine the current date, it will emit a warning message These macros are defined when the target processor supports atomic compare and swap operations on operands 1, 2, 4, 8 or 16 bytes in length, respectively. +@item __HAVE_SPECULATION_SAFE_VALUE +This macro is defined with the value 1 to show that this version of GCC +supports @code{__builtin_speculation_safe_value}. + @item __GCC_HAVE_DWARF2_CFI_ASM This macro is defined when the compiler is emitting DWARF CFI directives to the assembler. When this is defined, it is possible to emit those same diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 954e8a1..0ba1931 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -10948,6 +10948,7 @@ is called and the @var{flag} argument passed to it. @findex __builtin_powi @findex __builtin_powif @findex __builtin_powil +@findex __builtin_speculation_safe_value @findex _Exit @findex _exit @findex abort @@ -11592,6 +11593,96 @@ check its compatibility with @var{size}. @end deftypefn +@deftypefn {Built-in Function} @var{type} __builtin_speculation_safe_value (@var{type} val, @var{type} failval) + +This built-in function can be used to help mitigate against unsafe +speculative execution. @var{type} may be any integral type or any +pointer type. + +@enumerate +@item +If the CPU is not speculatively executing the code, then @var{val} +is returned. +@item +If the CPU is executing speculatively then either: +@itemize +@item +The function may cause execution to pause until it is known that the +code is no-longer being executed speculatively (in which case +@var{val} can be returned, as above); or +@item +The function may use target-dependent speculation tracking state to cause +@var{failval} to be returned when it is known that speculative +execution has incorrectly predicted a conditional branch operation. +@end itemize +@end enumerate + +The second argument, @var{failval}, is optional and defaults to zero +if omitted. + +GCC defines the preprocessor macro +@code{__HAVE_BUILTIN_SPECULATION_SAFE_VALUE} for targets that have been +updated to support this builtin. + +The built-in function can be used where a variable appears to be used in a +safe way, but the CPU, due to speculative execution may temporarily ignore +the bounds checks. Consider, for example, the following function: + +@smallexample +int array[500]; +int f (unsigned untrusted_index) +@{ + if (untrusted_index < 500) + return array[untrusted_index]; + return 0; +@} +@end smallexample + +If the function is called repeatedly with @code{untrusted_index} less +than the limit of 500, then a branch predictor will learn that the +block of code that returns a value stored in @code{array} will be +executed. If the function is subsequently called with an +out-of-range value it will still try to execute that block of code +first until the CPU determines that the prediction was incorrect +(the CPU will unwind any incorrect operations at that point). +However, depending on how the result of the function is used, it might be +possible to leave traces in the cache that can reveal what was stored +at the out-of-bounds location. The built-in function can be used to +provide some protection against leaking data in this way by changing +the code to: + +@smallexample +int array[500]; +int f (unsigned untrusted_index) +@{ + if (untrusted_index < 500) + return array[__builtin_speculation_safe_value (untrusted_index)]; + return 0; +@} +@end smallexample + +The built-in function will either cause execution to stall until the +conditional branch has been fully resolved, or it may permit +speculative execution to continue, but using 0 instead of +@code{untrusted_value} if that exceeds the limit. + +If accessing any memory location is potentially unsafe when speculative +execution is incorrect, then the code can be rewritten as + +@smallexample +int array[500]; +int f (unsigned untrusted_index) +@{ + if (untrusted_index < 500) + return *__builtin_speculation_safe_value (&array[untrusted_index], NULL); + return 0; +@} +@end smallexample + +which will cause a @code{NULL} pointer to be used for the unsafe case. + +@end deftypefn + @deftypefn {Built-in Function} int __builtin_types_compatible_p (@var{type1}, @var{type2}) You can use the built-in function @code{__builtin_types_compatible_p} to diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 734bc76..00c1239 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -7032,6 +7032,21 @@ should be defined to an instruction that orders both loads and stores before the instruction with respect to loads and stores after the instruction. This pattern has no operands. +@cindex @code{speculation_barrier} instruction pattern +@item @samp{speculation_barrier} +If the target can support speculative execution, then this pattern should +be defined to an instruction that will block subsequent execution until +any prior speculation conditions has been resolved. The pattern must also +ensure that the compiler cannot move memory operations past the barrier, +so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no +operands. + +If this pattern is not defined then the default expansion of +@code{__builtin_speculation_safe_value} will emit a warning. You can +suppress this warning by defining this pattern with a final condition +of @code{0} (zero), which tells the compiler that a speculation +barrier is not needed for this target. + @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern @item @samp{sync_compare_and_swap@var{mode}} This pattern, if defined, emits code for an atomic compare-and-swap diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index ff6d514..15b0ab8 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -11948,6 +11948,37 @@ maintainer is familiar with. @end defmac +@deftypefn {Target Hook} bool TARGET_HAVE_SPECULATION_SAFE_VALUE (bool @var{active}) +This hook is used to determine the level of target support for + @code{__builtin_speculation_safe_value}. If called with an argument + of false, it returns true if the target has been modified to support + this builtin. If called with an argument of true, it returns true + if the target requires active mitigation execution might be speculative. + + The default implementation returns false if the target does not define + a pattern named @code{speculation_barrier}. Else it returns true + for the first case and whether the pattern is enabled for the current + compilation for the second case. +@end deftypefn + +@deftypefn {Target Hook} rtx TARGET_SPECULATION_SAFE_VALUE (machine_mode @var{mode}, rtx @var{result}, rtx @var{val}, rtx @var{failval}) +This target hook can be used to generate a target-specific code + sequence that implements the @code{__builtin_speculation_safe_value} + built-in function. The function must always return @var{val} in + @var{result} in mode @var{mode} when the cpu is not executing + speculatively, but must never return that when speculating until it + is known that the speculation will not be unwound. The hook supports + two primary mechanisms for implementing the requirements. The first + is to emit a speculation barrier which forces the processor to wait + until all prior speculative operations have been resolved; the second + is to use a target-specific mechanism that can track the speculation + state and to return @var{failval} if it can determine that + speculation must be unwound at a later time. + + The default implementation simply copies @var{val} to @var{result} and + emits a @code{speculation_barrier} instruction if that is defined. +@end deftypefn + @deftypefn {Target Hook} void TARGET_RUN_TARGET_SELFTESTS (void) If selftests are enabled, run any selftests for this target. @end deftypefn diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 2f97151..94ad868 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -8109,4 +8109,8 @@ maintainer is familiar with. @end defmac +@hook TARGET_HAVE_SPECULATION_SAFE_VALUE + +@hook TARGET_SPECULATION_SAFE_VALUE + @hook TARGET_RUN_TARGET_SELFTESTS diff --git a/gcc/target.def b/gcc/target.def index ff89e72..d598067 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4196,6 +4196,41 @@ DEFHOOK hook_bool_void_true) DEFHOOK +(have_speculation_safe_value, +"This hook is used to determine the level of target support for\n\ + @code{__builtin_speculation_safe_value}. If called with an argument\n\ + of false, it returns true if the target has been modified to support\n\ + this builtin. If called with an argument of true, it returns true\n\ + if the target requires active mitigation execution might be speculative.\n\ + \n\ + The default implementation returns false if the target does not define\n\ + a pattern named @code{speculation_barrier}. Else it returns true\n\ + for the first case and whether the pattern is enabled for the current\n\ + compilation for the second case.", +bool, (bool active), default_have_speculation_safe_value) + +DEFHOOK +(speculation_safe_value, +"This target hook can be used to generate a target-specific code\n\ + sequence that implements the @code{__builtin_speculation_safe_value}\n\ + built-in function. The function must always return @var{val} in\n\ + @var{result} in mode @var{mode} when the cpu is not executing\n\ + speculatively, but must never return that when speculating until it\n\ + is known that the speculation will not be unwound. The hook supports\n\ + two primary mechanisms for implementing the requirements. The first\n\ + is to emit a speculation barrier which forces the processor to wait\n\ + until all prior speculative operations have been resolved; the second\n\ + is to use a target-specific mechanism that can track the speculation\n\ + state and to return @var{failval} if it can determine that\n\ + speculation must be unwound at a later time.\n\ + \n\ + The default implementation simply copies @var{val} to @var{result} and\n\ + emits a @code{speculation_barrier} instruction if that is defined.", +rtx, (machine_mode mode, rtx result, rtx val, rtx failval), + default_speculation_safe_value) + + +DEFHOOK (can_use_doloop_p, "Return true if it is possible to use low-overhead loops (@code{doloop_end}\n\ and @code{doloop_begin}) for a particular loop. @var{iterations} gives the\n\ diff --git a/gcc/targhooks.c b/gcc/targhooks.c index 9b06d7a..06de1e3 100644 --- a/gcc/targhooks.c +++ b/gcc/targhooks.c @@ -2314,4 +2314,36 @@ default_preferred_else_value (unsigned, tree type, unsigned, tree *) return build_zero_cst (type); } +/* Default implementation of TARGET_HAVE_SPECULATION_SAFE_VALUE. */ +bool +default_have_speculation_safe_value (bool active) +{ +#ifdef HAVE_speculation_barrier + return active ? HAVE_speculation_barrier : true; +#else + return false; +#endif +} + +/* Default implementation of the speculation-safe-load builtin. This + implementation simply copies val to result and generates a + speculation_barrier insn, if such a pattern is defined. */ +rtx +default_speculation_safe_value (machine_mode mode ATTRIBUTE_UNUSED, + rtx result, rtx val, + rtx failval ATTRIBUTE_UNUSED) +{ + emit_move_insn (result, val); + +#ifdef HAVE_speculation_barrier + /* Assume the target knows what it is doing: if it defines a + speculation barrier, but it is not enabled, then assume that one + isn't needed. */ + if (HAVE_speculation_barrier) + emit_insn (gen_speculation_barrier ()); +#endif + + return result; +} + #include "gt-targhooks.h" diff --git a/gcc/targhooks.h b/gcc/targhooks.h index 8d234cf..74ffe5f 100644 --- a/gcc/targhooks.h +++ b/gcc/targhooks.h @@ -285,4 +285,7 @@ extern bool default_stack_clash_protection_final_dynamic_probe (rtx); extern void default_select_early_remat_modes (sbitmap); extern tree default_preferred_else_value (unsigned, tree, unsigned, tree *); +extern bool default_have_speculation_safe_value (bool); +extern rtx default_speculation_safe_value (machine_mode, rtx, rtx, rtx); + #endif /* GCC_TARGHOOKS_H */ diff --git a/gcc/testsuite/c-c++-common/spec-barrier-1.c b/gcc/testsuite/c-c++-common/spec-barrier-1.c new file mode 100644 index 0000000..e4b44f2 --- /dev/null +++ b/gcc/testsuite/c-c++-common/spec-barrier-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O" } */ + +/* Test that __builtin_speculation_safe_value returns the correct value. */ +/* This test will cause an unfiltered warning to be emitted on targets + that have not implemented support for speculative execution + barriers. They should fix that rather than disabling this + test. */ +char a = 1; +short b = 2; +int c = 3; +long d = 4; +long long e = 5; +int *f = (int*) &c; +#ifdef __SIZEOF_INT128__ +__int128 g = 9; +#endif + +int main () +{ + if (__builtin_speculation_safe_value (a) != 1) + __builtin_abort (); + if (__builtin_speculation_safe_value (b) != 2) + __builtin_abort (); + if (__builtin_speculation_safe_value (c) != 3) + __builtin_abort (); + if (__builtin_speculation_safe_value (d) != 4) + __builtin_abort (); + if (__builtin_speculation_safe_value (e) != 5) + __builtin_abort (); + if (__builtin_speculation_safe_value (f) != &c) + __builtin_abort (); +#ifdef __SIZEOF_INT128__ + if (__builtin_speculation_safe_value (g) != 9) + __builtin_abort (); +#endif + return 0; +} diff --git a/gcc/testsuite/c-c++-common/spec-barrier-2.c b/gcc/testsuite/c-c++-common/spec-barrier-2.c new file mode 100644 index 0000000..b09567e --- /dev/null +++ b/gcc/testsuite/c-c++-common/spec-barrier-2.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ + +/* Even on targets that don't need the optional failval parameter, + side-effects on the operand should still be calculated. */ + +int x = 3; +volatile int y = 9; + +int main () +{ + int z = __builtin_speculation_safe_value (x, y++); + if (z != 3 || y != 10) + __builtin_abort (); + return 0; +} + +/* { dg-prune-output "this target does not define a speculation barrier;" } */ diff --git a/gcc/testsuite/gcc.dg/spec-barrier-3.c b/gcc/testsuite/gcc.dg/spec-barrier-3.c new file mode 100644 index 0000000..3ed4d39 --- /dev/null +++ b/gcc/testsuite/gcc.dg/spec-barrier-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-Wpedantic" } */ + +/* __builtin_speculation_safe_value returns a value with the same type + as its first argument. There should be a warning if that isn't + type-compatible with the use. */ +int * +f (int x) +{ + return __builtin_speculation_safe_value (x); /* { dg-warning "returning 'int' from a function with return type 'int \\*' makes pointer from integer without a cast" } */ +} + +/* { dg-prune-output "this target does not define a speculation barrier;" } */ From patchwork Fri Jul 27 09:37:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143019 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp598767ljj; Fri, 27 Jul 2018 02:39:05 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfr5Xlu3oki9oB6XfklQjPCZFNSDpiSq9zQrGeoV6VuU/bhDjFZmP3B8c2Bad2YWaTB3qxy X-Received: by 2002:a63:ab4c:: with SMTP id k12-v6mr5329543pgp.386.1532684345581; Fri, 27 Jul 2018 02:39:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684345; cv=none; d=google.com; s=arc-20160816; b=RY/KHCeX9fvob38eLb6MUk6m+VgJS3seRxoVt/QyBK40XWDxN6j1uvKCeOUJ78jqLg R2GE13pqjhF7q8xFwL/Nh11+FOUqbahwPIZugNMpURh5voCUxoLsTZ4vKOt0FSPXAorh nVpZo2xq9UhEKWMU7jyDNjKg/6Eodv4Wx/pMzlHa+6QVVvK+tdzQBCvpT+UTQ9DUVY1Y NZhmSGKQUfWQF5ZXT4R7KWBhMSHMCD3hkn+R3Hs7e3isNjEHQiK6Ukx9bJR20r/B8jud tbM2TPJCbI8S2vFdp34uKCCkadQWXlmFlpXtj6vQQAlEN+U59Xp7jpIpkPH2+fwGoj77 WxsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=m8RvBy1C1FfkZciGh9kBFMLkklyo+EfjWH9/QV02BGM=; b=fPB9ACmhkVe+It5+RQsXHdfdrt+TFL9SWz6vvfs2ndK+WjgUBfl1Z4XH7PbHOUdFoU NZ3BGr03EUv84rby2EjiezymrkqJDOfPq/mTpjRmmx8QJnaFG8RhWK6gtvPoWrGjGbo+ vS9A9HZlSlFTIUP7WS8PMY3k50zlpP6KxKoMMzBnsFkgoo8+pB+Ydf47nl1z4UvooJGx vRxBB4LH8smTwX+vdpOkUTax6ZovbCXcvbvj4+ZCzWhGmb9k8wc3YHVaIBUT0WegZ6Nl AOu5HeylixZWcv9kT96kVSCbuqWTqSua3AQ+gtaMHpDH+EROHXPjtK3y2X7ysj/N6/mV ZjVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wrFjtk7R; spf=pass (google.com: domain of gcc-patches-return-482505-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482505-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id o189-v6si3426482pga.577.2018.07.27.02.39.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:39:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482505-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wrFjtk7R; spf=pass (google.com: domain of gcc-patches-return-482505-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482505-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=Dswplxvvt/XxhXc1 kUR/uvwpM3VYRmkYbljP5v2UxA6ge2cCyWea8VkcBUmRq5lbBQEd2AAoaMlFn7UX QlIQsZoTT6VCzHKIF3pwMKhznC8xXd5abtmb+Ws10w4yUHesyXxP3tMBMszr/KeG D1xZb0LdqB2ol6HuyxCSU+dawJk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=AdI5PGpkQBGUs5pQsM0Q7+ rCcK8=; b=wrFjtk7Ri+K0XVyU2V0toRzq8xh8sBOSCvt4nedvoD/nAhxTM6i3sY zh7hgNvbrxUgPIHUTWO82ktCapk5hPmqUag00S1TC6ZUc90vvR9nSBmUQdWT6aST XVlrEl6E1lipIcjFUP1+V+MionQF2ZSB2HD9Y13+vBMzkmQvP/ZKk= Received: (qmail 46741 invoked by alias); 27 Jul 2018 09:38:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 46592 invoked by uid 89); 27 Jul 2018 09:38:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=wireless, Wireless, 1687, enumerators X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09BDB1682; Fri, 27 Jul 2018 02:38:25 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6631C3F575; Fri, 27 Jul 2018 02:38:24 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 02/11] Arm - add speculation_barrier pattern Date: Fri, 27 Jul 2018 10:37:46 +0100 Message-Id: <1532684275-13041-3-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 This patch defines a speculation barrier for AArch32. * config/arm/unspecs.md (unspecv): Add VUNSPEC_SPECULATION_BARRIER. * config/arm/arm.md (speculation_barrier): New expand. (speculation_barrier_insn): New pattern. --- gcc/config/arm/arm.md | 21 +++++++++++++++++++++ gcc/config/arm/unspecs.md | 1 + 2 files changed, 22 insertions(+) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 361a026..ca2a2f5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12012,6 +12012,27 @@ (define_insn "" [(set_attr "length" "4") (set_attr "type" "coproc")]) +(define_expand "speculation_barrier" + [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)] + "TARGET_EITHER" + " + /* Don't emit anything for Thumb1 and suppress the warning from the + generic expansion. */ + if (!TARGET_32BIT) + DONE; + " +) + +;; Generate a hard speculation barrier when we have not enabled speculation +;; tracking. +(define_insn "*speculation_barrier_insn" + [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)] + "TARGET_32BIT" + "isb\;dsb\\tsy" + [(set_attr "type" "block") + (set_attr "length" "8")] +) + ;; Vector bits common to IWMMXT and Neon (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index b05f85e..1941673 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -168,6 +168,7 @@ (define_c_enum "unspecv" [ VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction. VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction. VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction. + VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier. ]) ;; Enumerators for NEON unspecs. From patchwork Fri Jul 27 09:37:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143018 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp598611ljj; Fri, 27 Jul 2018 02:38:54 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdMIWBlgX3d9jxjJ5FXvjEjx1yN5CZnn/yteU+cqUSJA4Ezzb8Y0OsQO10J0HhTdqnZsiaj X-Received: by 2002:a17:902:1d4a:: with SMTP id u10-v6mr5385764plu.267.1532684334122; Fri, 27 Jul 2018 02:38:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684334; cv=none; d=google.com; s=arc-20160816; b=0TxlwnIXX5E0Msf3CRynre8OiwImoeqsVVSnsZn+AyB9PgJ/Vgd+v57vjw5sdA/OYz HLXVx2Vjg2VW/XuZwfLIN7ZhRnX/N6qNtWSs6rVqB/YBgdoZiSeGWaQzqdKEE/vmMLKz dKNGC8Vc9zb9UCgpRJKk0EZQWFG6d9ukgsgwm9tJFfksXEx1NWxNIwfnTW3gZFoDTR6Q Q6NB2TLbD/DgedLw4to+2tBIeenIROKhrXJshJDo5qwNtit0/UyJrykV2StOqekrUlGi FurGLFIgUgzrmnpccTUvmJGIzePUeTbAh5rYaudy87ueEGDl/zVtsBz1GisCboRfXaTx xx3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=WW/GzLumh7o2IWzFZ6L0Y8ZXueWnV6LFQILu2i02ucM=; b=okgdahJQO92nQ2IKfj1LuDep7G5kBGuXEwFdcmafG4OHlHXzvxGwfUTu4l4ALQhags csPsdobfxQIM8l6vp5kHWmD496ERY8MmW9F8G0e3MB0AOJsE/L812zvkYUb4gPw4xW4k fzIh0GL3vn00OxKzLHiXWsO2fFIkNdwuPMPKWX8//B2FEYSf2KTASLp+5PAtE1e1AhTk Icf1tGj52xd+5EpymNX2nAoDgQXfcP1OerPUWk44Bv4l2lET/SnRKnwZFqyXW2MRXBgg SlKF84LFvN/RE7GqU0KHTnGGr8E+p5cWeT2EPAo6zWYsTJVWXgVZvyarkDhStRooH7di DdfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rOnCX0CH; spf=pass (google.com: domain of gcc-patches-return-482504-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482504-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id f18-v6si3278854pgd.16.2018.07.27.02.38.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:38:54 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482504-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rOnCX0CH; spf=pass (google.com: domain of gcc-patches-return-482504-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482504-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=Zp31cV/5MyooHfeT x+3LHqHotQqRQ1ASh4ttMd0MXDqbMtRd/qjcdznksrAN3VgSvE8PKvjKs+plWLDF u/f7yRgTKBFEnySiTygCDzZUThQe5wBixrddMN1z+QsgfS2REz8EH42rQx/dCv2s QrbWQ2GzVS8DRJuKImDrt8paFcs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=LXdV+RzKviWvtG9UDSjIeu iVwlk=; b=rOnCX0CHaoWhtbzQeQ1DyuRdU4oiv43rxz9pKdp9aK9mx1+HGa6YuV e0e/Fr0AGFywUNhO+thqG/N3Fsu4ZyyPdn84afjYE1bLjn+dYLJPfnOSf0CflfMB Ldr3+pyhrLeMkiPX/fT46VoJEUmY/3FY5B/52Qq+74A1e0PR38Dzw= Received: (qmail 46679 invoked by alias); 27 Jul 2018 09:38:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 46594 invoked by uid 89); 27 Jul 2018 09:38:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF2711684; Fri, 27 Jul 2018 02:38:25 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4770E3F575; Fri, 27 Jul 2018 02:38:25 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 03/11] AArch64 - add speculation barrier Date: Fri, 27 Jul 2018 10:37:47 +0100 Message-Id: <1532684275-13041-4-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 Similar to Arm, this adds an unconditional speculation barrier for AArch64. * config/aarch64.md (unspecv): Add UNSPECV_SPECULAION_BARRIER. (speculation_barrier): New insn. --- gcc/config/aarch64/aarch64.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index a014a01..c135ada 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -205,6 +205,7 @@ (define_c_enum "unspecv" [ UNSPECV_SET_FPSR ; Represent assign of FPSR content. UNSPECV_BLOCKAGE ; Represent a blockage UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing. + UNSPECV_SPECULATION_BARRIER ; Represent speculation barrier. ] ) @@ -6093,6 +6094,15 @@ (define_expand "set_clobber_cc" (match_operand 1)) (clobber (reg:CC CC_REGNUM))])]) +;; Hard speculation barrier. +(define_insn "speculation_barrier" + [(unspec_volatile [(const_int 0)] UNSPECV_SPECULATION_BARRIER)] + "" + "isb\;dsb\\tsy" + [(set_attr "length" "8") + (set_attr "type" "block")] +) + ;; AdvSIMD Stuff (include "aarch64-simd.md") From patchwork Fri Jul 27 09:37:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143026 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp600349ljj; Fri, 27 Jul 2018 02:40:56 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeoqmqF2duyImbt3Z6gMQUru23mW2EnfpCRJQ+CaNZbTz/qfhQ2Nio/kwM1KcY/fPMSiy6Z X-Received: by 2002:a63:f414:: with SMTP id g20-v6mr5344929pgi.407.1532684456350; Fri, 27 Jul 2018 02:40:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684456; cv=none; d=google.com; s=arc-20160816; b=vELAN8nAAA7+AhyPm45gdcCJqzYK1jgsDFH1FcdJ6x20Hd5o1PN6MzPx+msJxSFspE /Uesqxfpb/XMa4D22wOjPfWO8BWwPrUmJB+kFLTlfwLSb0RyhyLlD6qBgWYtG47HZGVR OyYYfjQF3377lpkfltX1WYmpkWAOJDucMZHU7moGXOOI+Zqi9nFOM7n5virNYdZRwazG AmRzGiab3VizsX2nqEJWjSFp/Gas1Ds9NGUbDuFdsvshb6MKAo2Lk3Pp1cKBvM35iL4L sBcNnB3vAnMtb8pdU3M33C08IvLqiwv7YEf5ZjJlTFbOug1O/pPKpSGCoWHc4k9Za/UT gEGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=32gijPOa+OnV1leuq4zAfyJyZuuOLHLQQdHfOv32sEk=; b=wGIUcKqSAzACVRjJZblklfG52K5ju5EDqfR9OS3XJ4JSubLp2HgtTeOSJ60829y+4o tenmZooE6cd4P0SgbzglULTkR6B2+LQ42CRzTBK1in7gY/89C2JLBbiW38xtqokRpiRs X8pYMMbxqTHoiLRc+hFmFtVkA8F7uNeJr8pmkNATO987/OKOy+8BcBnBL1Kmk7pWEbv0 2ibUWEsFldma4fIvOXiXEkY7M5fK/VfMPViYfSWEvCSLO0vzddfLSrcQN02I+LvWn/w2 asDYU28OhDm2XyhXP2yJXC9gn3BDylUqO+A0vvbvQQf0460M1yvoUokce8XbNcA6gOCB 2VkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wLGuPnlG; spf=pass (google.com: domain of gcc-patches-return-482512-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482512-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id h5-v6si3622567pfd.112.2018.07.27.02.40.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:40:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482512-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wLGuPnlG; spf=pass (google.com: domain of gcc-patches-return-482512-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482512-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=WDHL0d4IqscPGBVu ymhC26Mfl5YLY+L1/6IOuKDeLXqiZzBh3O+ij0TzqWQXjuqk4uXR3V2qQaCLXiL2 Rfit/0TrJ/3PjOjBVk+E/j0+d21wFTU9dSKCe2R58VEaFF05ZUnSmLVndQpFrOkE Hd8MhAlcuy4FLk4YhZQzKgzXEUk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=apGf4Ex1tFSyRL5GEEN8CV EMEt4=; b=wLGuPnlG+VOErcSLFKzJNGIIkFeZdLbDaUTV24Brx7hCFBHnAsPyL4 RRvbtkp1/EdiiQcJTC3+Yit7aNzx53ll4FkyeoR6YSnRvPsrx180AgqCWBp9gyo6 fETV4XKX3FhwrtkVJyCzjjYkIr1GIXDMnZudinbV6w3E3gTRby9Jk= Received: (qmail 48364 invoked by alias); 27 Jul 2018 09:38:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48183 invoked by uid 89); 27 Jul 2018 09:38:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:39 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCf-0006CN-S8 for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from foss.arm.com ([217.140.101.70]:47226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCf-00069d-Jd for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:29 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C05E51688; Fri, 27 Jul 2018 02:38:26 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 28BD63F575; Fri, 27 Jul 2018 02:38:26 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 04/11] AArch64 - Add new option -mtrack-speculation Date: Fri, 27 Jul 2018 10:37:48 +0100 Message-Id: <1532684275-13041-5-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This patch doesn't do anything useful, it simply adds a new command-line option -mtrack-speculation to AArch64. Subsequent patches build on this. * config/aarch64/aarch64.opt (mtrack-speculation): New target option. --- gcc/config/aarch64/aarch64.opt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 1426b45..bc9b22a 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -214,3 +214,7 @@ Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) mverbose-cost-dump Common Undocumented Var(flag_aarch64_verbose_cost) Enables verbose cost model dumping in the debug dump files. + +mtrack-speculation +Target Var(aarch64_track_speculation) +Generate code to track when the CPU might be speculating incorrectly. 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[209.132.180.131]) by mx.google.com with ESMTPS id v11-v6si3403936pgl.27.2018.07.27.02.41.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:41:19 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482514-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Y3oc/N3/"; spf=pass (google.com: domain of gcc-patches-return-482514-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482514-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=ZYaKhXdKUWpaTpd8 3QqE71Pj+F2gQ5E5IqmLL3TuPwT9EbRVjtcgie/OJ71GdGWNQoo/0v/03lJTOBIC hpE6+k+Y/vr8gPFslX+J60tdrudUxV3rDFOy6j5qZN/WRg0x33QNqFTUoqQsLxTN 67wfyxAR0CsqAidUU23VdqvKBF8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=PjEbJquBYbC1WnP0ZTOKQ4 Owb0Y=; b=Y3oc/N3/b46hyx09YhzcpoGGnmOW9J2hU04J3HyHL89MbYHb4Pxclx fe5J3RTJfKT/z4qm27b7M0dB57G6kPKZ3rdfeelfy1O3mfPLtxJ/YhesiixCqIUQ ZEjPS24jU4akH/FGCLx8gLSgtYX1WsJkI+ik4EiCf3cs7PIJAPEuc= Received: (qmail 49392 invoked by alias); 27 Jul 2018 09:38:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48455 invoked by uid 89); 27 Jul 2018 09:38:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy=lcb, Lcb X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:39 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCf-0006C9-P2 for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from foss.arm.com ([217.140.101.70]:47232) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCf-0006BH-DP for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:29 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A1C7816A3; Fri, 27 Jul 2018 02:38:27 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0A1A93F575; Fri, 27 Jul 2018 02:38:26 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 05/11] AArch64 - disable CB[N]Z TB[N]Z when tracking speculation Date: Fri, 27 Jul 2018 10:37:49 +0100 Message-Id: <1532684275-13041-6-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 The CB[N]Z and TB[N]Z instructions do not expose the comparison through the condition code flags. This makes it impossible to track speculative execution through such a branch. We can handle this relatively easily by simply disabling the patterns in this case. A side effect of this is that the split patterns for the atomic operations need to also avoid generating these instructions. They mostly have simple fall-backs for this already. * config/aarch64/aarch64.md (cb1): Disable when aarch64_track_speculation is true. (tb1): Likewise. * config/aarch64/aarch64.c (aarch64_split_compare_regs): Do not generate CB[N]Z when tracking speculation. (aarch64_split_compare_and_swap): Likewise. (aarch64_split_atomic_op): Likewise. --- gcc/config/aarch64/aarch64.c | 33 ++++++++++++++++++++++++++++++--- gcc/config/aarch64/aarch64.md | 6 +++--- 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1369704..90849b5 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -14479,7 +14479,16 @@ aarch64_split_compare_and_swap (rtx operands[]) if (strong_zero_p) { - x = gen_rtx_NE (VOIDmode, rval, const0_rtx); + if (aarch64_track_speculation) + { + /* Emit an explicit compare instruction, so that we can correctly + track the condition codes. */ + rtx cc_reg = aarch64_gen_compare_reg (NE, rval, const0_rtx); + x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + } + else + x = gen_rtx_NE (VOIDmode, rval, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); @@ -14497,7 +14506,16 @@ aarch64_split_compare_and_swap (rtx operands[]) if (!is_weak) { - x = gen_rtx_NE (VOIDmode, scratch, const0_rtx); + if (aarch64_track_speculation) + { + /* Emit an explicit compare instruction, so that we can correctly + track the condition codes. */ + rtx cc_reg = aarch64_gen_compare_reg (NE, scratch, const0_rtx); + x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + } + else + x = gen_rtx_NE (VOIDmode, scratch, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label1), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); @@ -14833,7 +14851,16 @@ aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, aarch64_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out), model_rtx); - x = gen_rtx_NE (VOIDmode, cond, const0_rtx); + if (aarch64_track_speculation) + { + /* Emit an explicit compare instruction, so that we can correctly + track the condition codes. */ + rtx cc_reg = aarch64_gen_compare_reg (NE, cond, const0_rtx); + x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + } + else + x = gen_rtx_NE (VOIDmode, cond, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c135ada..259a07d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -690,7 +690,7 @@ (define_insn "*cb1" (const_int 0)) (label_ref (match_operand 1 "" "")) (pc)))] - "" + "!aarch64_track_speculation" { if (get_attr_length (insn) == 8) return aarch64_gen_far_branch (operands, 1, "Lcb", "\\t%0, "); @@ -720,7 +720,7 @@ (define_insn "*tb1" (label_ref (match_operand 2 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] - "" + "!aarch64_track_speculation" { if (get_attr_length (insn) == 8) { @@ -756,7 +756,7 @@ (define_insn "*cb1" (label_ref (match_operand 1 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] - "" + "!aarch64_track_speculation" { if (get_attr_length (insn) == 8) { From patchwork Fri Jul 27 09:37:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143021 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp599447ljj; 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[209.132.180.131]) by mx.google.com with ESMTPS id n5-v6si3001615plk.352.2018.07.27.02.39.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:39:54 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482507-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TfOiBMDI; spf=pass (google.com: domain of gcc-patches-return-482507-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482507-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=uhc2zH4ZqNrC7e+n UryUsxS+qYasrUgDXvxbRTUjrlpevGbf+lsebWNd21VfdZj45O1VRhnaDsMTwD3q QzIIFhV4QKIvtWzALpdB4ejwCsYw1yCwDpl8Xltra/9Dq9F/GZ93wexh7ndW5AQ+ /yyIx3xMemRmAq9wMBeBiLX58q0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=lT4JbGxaXLqKmnKaYJpRnn Fw790=; b=TfOiBMDI1K6527x5F/m2OPwpmiIja3Lu/HskOzdIVc3M5mrpNn7T2D glagcozoJB6egwZvKDbQmDWPsiVnY4g5JnwF0JhLD6sEPUv/ZdEudxqF+GGB8Mn7 a6xZoUSQdEyWbWY1E1szAQerLL02vTK4HzS++pdP2hKwoqZqg5cWY= Received: (qmail 47680 invoked by alias); 27 Jul 2018 09:38:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47579 invoked by uid 89); 27 Jul 2018 09:38:36 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_PASS autolearn=ham version=3.3.2 spammy=trusted, afterwards, Track, tracker X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6A0B174E; Fri, 27 Jul 2018 02:38:28 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DF9B93F575; Fri, 27 Jul 2018 02:38:27 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 06/11] AArch64 - new pass to add conditional-branch speculation tracking Date: Fri, 27 Jul 2018 10:37:50 +0100 Message-Id: <1532684275-13041-7-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 This patch is the main part of the speculation tracking code. It adds a new target-specific pass that is run just before the final branch reorg pass (so that it can clean up any new edge insertions we make). The pass is only run with -mtrack-speculation is passed on the command line. One thing that did come to light as part of this was that the stack pointer register was not being permitted in comparision instructions. We rely on that for moving the tracking state between SP and the scratch register at function call boundaries. * config/aarch64/aarch64-speculation.cc: New file. * config/aarch64/aarch64-passes.def (pass_track_speculation): Add before pass_reorder_blocks. * config/aarch64/aarch64-protos.h (make_pass_track_speculation): Add prototype. * config/aarch64/aarch64.c (aarch64_conditional_register_usage): Fix X14 and X15 when tracking speculation. * config/aarch64/aarch64.md (register name constants): Add SPECULATION_TRACKER_REGNUM and SPECULATION_SCRATCH_REGNUM. (unspec): Add UNSPEC_SPECULATION_TRACKER. (speculation_barrier): New insn attribute. (cmp): Allow SP in comparisons. (speculation_tracker): New insn. (speculation_barrier): Add speculation_barrier attribute. * config/aarch64/t-aarch64: Add make rule for aarch64-speculation.o. * config.gcc (aarch64*-*-*): Add aarch64-speculation.o to extra_objs. * doc/invoke.texi (AArch64 Options): Document -mtrack-speculation. --- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 3 +- gcc/config/aarch64/aarch64-speculation.cc | 494 ++++++++++++++++++++++++++++++ gcc/config/aarch64/aarch64.c | 13 + gcc/config/aarch64/aarch64.md | 30 +- gcc/config/aarch64/t-aarch64 | 10 + gcc/doc/invoke.texi | 10 +- 8 files changed, 558 insertions(+), 5 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-speculation.cc diff --git a/gcc/config.gcc b/gcc/config.gcc index 78e84c2..b17fdba 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -304,7 +304,7 @@ aarch64*-*-*) extra_headers="arm_fp16.h arm_neon.h arm_acle.h" c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" - extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o" + extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o aarch64-speculation.o" target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.c" target_has_targetm_common=yes ;; diff --git a/gcc/config/aarch64/aarch64-passes.def b/gcc/config/aarch64/aarch64-passes.def index 87747b4..3d6a254 100644 --- a/gcc/config/aarch64/aarch64-passes.def +++ b/gcc/config/aarch64/aarch64-passes.def @@ -19,3 +19,4 @@ . */ INSERT_PASS_AFTER (pass_regrename, 1, pass_fma_steering); +INSERT_PASS_BEFORE (pass_reorder_blocks, 1, pass_track_speculation); diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index bc11a78..e80ffcf 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -554,7 +554,8 @@ enum aarch64_parse_opt_result aarch64_parse_extension (const char *, std::string aarch64_get_extension_string_for_isa_flags (unsigned long, unsigned long); -rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt); +rtl_opt_pass *make_pass_fma_steering (gcc::context *); +rtl_opt_pass *make_pass_track_speculation (gcc::context *); poly_uint64 aarch64_regmode_natural_size (machine_mode); diff --git a/gcc/config/aarch64/aarch64-speculation.cc b/gcc/config/aarch64/aarch64-speculation.cc new file mode 100644 index 0000000..2dd06ae --- /dev/null +++ b/gcc/config/aarch64/aarch64-speculation.cc @@ -0,0 +1,494 @@ +/* Speculation tracking and mitigation (e.g. CVE 2017-5753) for AArch64. + Copyright (C) 2018 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "target.h" +#include "rtl.h" +#include "tree-pass.h" +#include "profile-count.h" +#include "cfg.h" +#include "cfgbuild.h" +#include "print-rtl.h" +#include "cfgrtl.h" +#include "function.h" +#include "basic-block.h" +#include "memmodel.h" +#include "emit-rtl.h" +#include "insn-attr.h" +#include "df.h" +#include "tm_p.h" +#include "insn-config.h" +#include "recog.h" + +/* This pass scans the RTL just before the final branch + re-organisation pass. The aim is to identify all places where + there is conditional control flow and to insert code that tracks + any speculative execution of a conditional branch. + + To do this we reserve a call-clobbered register (so that it can be + initialized very early in the function prologue) that can then be + updated each time there is a conditional branch. At each such + branch we then generate a code sequence that uses conditional + select operations that are not subject to speculation themselves + (we ignore for the moment situations where that might not always be + strictly true). For example, a branch sequence such as: + + B.EQ + ... + : + + is transformed to: + + B.EQ + CSEL tracker, tracker, XZr, ne + ... + : + CSEL tracker, tracker, XZr, eq + + Since we start with the tracker initialized to all bits one, if at any + time the predicted control flow diverges from the architectural program + behavior, then the tracker will become zero (but not otherwise). + + The tracker value can be used at any time at which a value needs + guarding against incorrect speculation. This can be done in + several ways, but they all amount to the same thing. For an + untrusted address, or an untrusted offset to a trusted address, we + can simply mask the address with the tracker with the untrusted + value. If the CPU is not speculating, or speculating correctly, + then the value will remain unchanged, otherwise it will be clamped + to zero. For more complex scenarios we can compare the tracker + against zero and use the flags to form a new selection with an + alternate safe value. + + On implementations where the data processing instructions may + themselves produce speculative values, the architecture requires + that a CSDB instruction will resolve such data speculation, so each + time we use the tracker for protecting a vulnerable value we also + emit a CSDB: we do not need to do that each time the tracker itself + is updated. + + At function boundaries, we need to communicate the speculation + tracking state with the caller or the callee. This is tricky + because there is no register available for such a purpose without + creating a new ABI. We deal with this by relying on the principle + that in all real programs the stack pointer, SP will never be NULL + at a function boundary; we can thus encode the speculation state in + SP by clearing SP if the speculation tracker itself is NULL. After + the call we recover the tracking state back from SP into the + tracker register. The results is that a function call sequence is + transformed to + + MOV tmp, SP + AND tmp, tmp, tracker + MOV SP, tmp + BL + CMP SP, #0 + CSETM tracker, ne + + The additional MOV instructions in the pre-call sequence are needed + because SP cannot be used directly with the AND instruction. + + The code inside a function body uses the post-call sequence in the + prologue to establish the tracker and the pre-call sequence in the + epilogue to re-encode the state for the return. + + The code sequences have the nice property that if called from, or + calling a function that does not track speculation then the stack pointer + will always be non-NULL and hence the tracker will be initialized to all + bits one as we need: we lose the ability to fully track speculation in that + case, but we are still architecturally safe. + + Tracking speculation in this way is quite expensive, both in code + size and execution time. We employ a number of tricks to try to + limit this: + + 1) Simple leaf functions with no conditional branches (or use of + the tracker) do not need to establish a new tracker: they simply + carry the tracking state through SP for the duration of the call. + The same is also true for leaf functions that end in a tail-call. + + 2) Back-to-back function calls in a single basic block also do not + need to re-establish the tracker between the calls. Again, we can + carry the tracking state in SP for this period of time unless the + tracker value is needed at that point in time. + + We run the pass just before the final branch reorganization pass so + that we can handle most of the conditional branch cases using the + standard edge insertion code. The reorg pass will hopefully clean + things up for afterwards so that the results aren't too + horrible. */ + +/* Generate a code sequence to clobber SP if speculating incorreclty. */ +static rtx_insn * +aarch64_speculation_clobber_sp () +{ + rtx sp = gen_rtx_REG (DImode, SP_REGNUM); + rtx tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); + rtx scratch = gen_rtx_REG (DImode, SPECULATION_SCRATCH_REGNUM); + + start_sequence (); + emit_insn (gen_rtx_SET (scratch, sp)); + emit_insn (gen_anddi3 (scratch, scratch, tracker)); + emit_insn (gen_rtx_SET (sp, scratch)); + rtx_insn *seq = get_insns (); + end_sequence (); + return seq; +} + +/* Generate a code sequence to establish the tracker variable from the + contents of SP. */ +static rtx_insn * +aarch64_speculation_establish_tracker () +{ + rtx sp = gen_rtx_REG (DImode, SP_REGNUM); + rtx tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); + start_sequence (); + rtx cc = aarch64_gen_compare_reg (EQ, sp, const0_rtx); + emit_insn (gen_cstoredi_neg (tracker, + gen_rtx_NE (CCmode, cc, const0_rtx), cc)); + rtx_insn *seq = get_insns (); + end_sequence (); + return seq; +} + +/* Main speculation tracking pass. */ +unsigned int +aarch64_do_track_speculation () +{ + basic_block bb; + bool needs_tracking = false; + bool need_second_pass = false; + rtx_insn *insn; + int fixups_pending = 0; + + FOR_EACH_BB_FN (bb, cfun) + { + insn = BB_END (bb); + + if (dump_file) + fprintf (dump_file, "Basic block %d:\n", bb->index); + + while (insn != BB_HEAD (bb) + && NOTE_P (insn)) + insn = PREV_INSN (insn); + + if (control_flow_insn_p (insn)) + { + if (any_condjump_p (insn)) + { + if (dump_file) + { + fprintf (dump_file, " condjump\n"); + dump_insn_slim (dump_file, insn); + } + + rtx src = SET_SRC (pc_set (insn)); + + /* Check for an inverted jump, where the fall-through edge + appears first. */ + bool inverted = GET_CODE (XEXP (src, 2)) != PC; + /* The other edge must be the PC (we assume that we don't + have conditional return instructions). */ + gcc_assert (GET_CODE (XEXP (src, 1 + !inverted)) == PC); + + rtx cond = copy_rtx (XEXP (src, 0)); + gcc_assert (COMPARISON_P (cond) + && REG_P (XEXP (cond, 0)) + && REGNO (XEXP (cond, 0)) == CC_REGNUM + && XEXP (cond, 1) == const0_rtx); + enum rtx_code inv_cond_code + = reversed_comparison_code (cond, insn); + /* We should be able to reverse all conditions. */ + gcc_assert (inv_cond_code != UNKNOWN); + rtx inv_cond = gen_rtx_fmt_ee (inv_cond_code, GET_MODE (cond), + copy_rtx (XEXP (cond, 0)), + copy_rtx (XEXP (cond, 1))); + if (inverted) + std::swap (cond, inv_cond); + + insert_insn_on_edge (gen_speculation_tracker (cond), + BRANCH_EDGE (bb)); + insert_insn_on_edge (gen_speculation_tracker (inv_cond), + FALLTHRU_EDGE (bb)); + needs_tracking = true; + } + else if (GET_CODE (PATTERN (insn)) == RETURN) + { + /* If we already know we'll need a second pass, don't put + out the return sequence now, or we might end up with + two copies. Instead, we'll do all return statements + during the second pass. However, if this is the + first return insn we've found and we already + know that we'll need to emit the code, we can save a + second pass by emitting the code now. */ + if (needs_tracking && ! need_second_pass) + { + rtx_insn *seq = aarch64_speculation_clobber_sp (); + emit_insn_before (seq, insn); + } + else + { + fixups_pending++; + need_second_pass = true; + } + } + else if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) + { + rtx_insn *seq = aarch64_speculation_clobber_sp (); + emit_insn_before (seq, insn); + needs_tracking = true; + } + } + else + { + if (dump_file) + { + fprintf (dump_file, " other\n"); + dump_insn_slim (dump_file, insn); + } + } + } + + FOR_EACH_BB_FN (bb, cfun) + { + rtx_insn *end = BB_END (bb); + rtx_insn *call_insn = NULL; + + if (bb->flags & BB_NON_LOCAL_GOTO_TARGET) + { + rtx_insn *label = NULL; + /* For non-local goto targets we have to recover the + speculation state from SP. Find the last code label at + the head of the block and place the fixup sequence after + that. */ + for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn)) + { + if (LABEL_P (insn)) + label = insn; + /* Never put anything before the basic block note. */ + if (NOTE_INSN_BASIC_BLOCK_P (insn)) + label = insn; + if (INSN_P (insn)) + break; + } + + gcc_assert (label); + emit_insn_after (aarch64_speculation_establish_tracker (), label); + } + + /* Scan the insns looking for calls. We need to pass the + speculation tracking state encoded in to SP. After a call we + restore the speculation tracking into the tracker register. + To avoid unnecessary transfers we look for two or more calls + within a single basic block and eliminate, where possible, + any redundant operations. */ + for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) + { + if (NONDEBUG_INSN_P (insn) + && recog_memoized (insn) >= 0 + && (get_attr_speculation_barrier (insn) + == SPECULATION_BARRIER_TRUE)) + { + if (call_insn) + { + /* This instruction requires the speculation + tracking to be in the tracker register. If there + was an earlier call in this block, we need to + copy the speculation tracking back there. */ + emit_insn_after (aarch64_speculation_establish_tracker (), + call_insn); + call_insn = NULL; + } + + needs_tracking = true; + } + + if (CALL_P (insn)) + { + bool tailcall + = (SIBLING_CALL_P (insn) + || find_reg_note (insn, REG_NORETURN, NULL_RTX)); + + /* Tailcalls are like returns, we can eliminate the + transfer between the tracker register and SP if we + know that this function does not itself need + tracking. */ + if (tailcall && (need_second_pass || !needs_tracking)) + { + /* Don't clear call_insn if it is set - needs_tracking + will be true in that case and so we will end + up putting out mitigation sequences. */ + fixups_pending++; + need_second_pass = true; + break; + } + + needs_tracking = true; + + /* We always need a transfer before the first call in a BB. */ + if (!call_insn) + emit_insn_before (aarch64_speculation_clobber_sp (), insn); + + /* Tail-calls and no-return calls don't need any post-call + reestablishment of the tracker. */ + if (! tailcall) + call_insn = insn; + else + call_insn = NULL; + } + + if (insn == end) + break; + } + + if (call_insn) + { + rtx_insn *seq = aarch64_speculation_establish_tracker (); + + /* Handle debug insns at the end of the BB. Put the extra + insns after them. This ensures that we have consistent + behaviour for the placement of the extra insns between + debug and non-debug builds. */ + for (insn = call_insn; + insn != end && DEBUG_INSN_P (NEXT_INSN (insn)); + insn = NEXT_INSN (insn)) + ; + + if (insn == end) + { + edge e = find_fallthru_edge (bb->succs); + /* We need to be very careful about some calls that + appear at the end of a basic block. If the call + involves exceptions, then the compiler may depend on + this being the last instruction in the block. The + easiest way to handle this is to commit the new + instructions on the fall-through edge and to let + commit_edge_insertions clean things up for us. + + Sometimes, eg with OMP, there may not even be an + outgoing edge after the call. In that case, there's + not much we can do, presumably the compiler has + decided that the call can never return in this + context. */ + if (e) + { + /* We need to set the location lists explicitly in + this case. */ + if (! INSN_P (seq)) + { + start_sequence (); + emit_insn (seq); + seq = get_insns (); + end_sequence (); + } + + for (rtx_insn *list = seq; list; list = NEXT_INSN (list)) + INSN_LOCATION (list) = INSN_LOCATION (call_insn); + + insert_insn_on_edge (seq, e); + } + } + else + emit_insn_after (seq, call_insn); + } + } + + if (needs_tracking) + { + if (need_second_pass) + { + /* We found a return instruction before we found out whether + or not we need to emit the tracking code, but we now + know we do. Run quickly over the basic blocks and + fix up the return insns. */ + FOR_EACH_BB_FN (bb, cfun) + { + insn = BB_END (bb); + + while (insn != BB_HEAD (bb) + && NOTE_P (insn)) + insn = PREV_INSN (insn); + + if ((control_flow_insn_p (insn) + && GET_CODE (PATTERN (insn)) == RETURN) + || (CALL_P (insn) + && (SIBLING_CALL_P (insn) + || find_reg_note (insn, REG_NORETURN, NULL_RTX)))) + { + rtx_insn *seq = aarch64_speculation_clobber_sp (); + emit_insn_before (seq, insn); + fixups_pending--; + } + } + gcc_assert (fixups_pending == 0); + } + + /* Set up the initial value of the tracker, using the incoming SP. */ + insert_insn_on_edge (aarch64_speculation_establish_tracker (), + single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun))); + commit_edge_insertions (); + } + + return 0; +} + +namespace { + +const pass_data pass_data_aarch64_track_speculation = +{ + RTL_PASS, /* type. */ + "speculation", /* name. */ + OPTGROUP_NONE, /* optinfo_flags. */ + TV_MACH_DEP, /* tv_id. */ + 0, /* properties_required. */ + 0, /* properties_provided. */ + 0, /* properties_destroyed. */ + 0, /* todo_flags_start. */ + 0 /* todo_flags_finish. */ +}; + +class pass_track_speculation : public rtl_opt_pass +{ + public: + pass_track_speculation(gcc::context *ctxt) + : rtl_opt_pass(pass_data_aarch64_track_speculation, ctxt) + {} + + /* opt_pass methods: */ + virtual bool gate (function *) + { + return aarch64_track_speculation; + } + + virtual unsigned int execute (function *) + { + return aarch64_do_track_speculation (); + } +}; // class pass_track_speculation. +} // anon namespace. + +/* Create a new pass instance. */ +rtl_opt_pass * +make_pass_track_speculation (gcc::context *ctxt) +{ + return new pass_track_speculation (ctxt); +} diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 90849b5..cca465e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -12587,6 +12587,19 @@ aarch64_conditional_register_usage (void) fixed_regs[i] = 1; call_used_regs[i] = 1; } + + /* When tracking speculation, we need a couple of call-clobbered registers + to track the speculation state. It would be nice to just use + IP0 and IP1, but currently there are numerous places that just + assume these registers are free for other uses (eg pointer + authentication). */ + if (aarch64_track_speculation) + { + fixed_regs[SPECULATION_TRACKER_REGNUM] = 1; + call_used_regs[SPECULATION_TRACKER_REGNUM] = 1; + fixed_regs[SPECULATION_SCRATCH_REGNUM] = 1; + call_used_regs[SPECULATION_SCRATCH_REGNUM] = 1; + } } /* Walk down the type tree of TYPE counting consecutive base elements. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 259a07d..528d03d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -88,6 +88,10 @@ (define_constants (P13_REGNUM 81) (P14_REGNUM 82) (P15_REGNUM 83) + ;; A couple of call-clobbered registers that we need to reserve when + ;; tracking speculation this is not ABI, so is subject to change. + (SPECULATION_TRACKER_REGNUM 15) + (SPECULATION_SCRATCH_REGNUM 14) ] ) @@ -195,6 +199,7 @@ (define_c_enum "unspec" [ UNSPEC_CLASTB UNSPEC_FADDA UNSPEC_REV_SUBREG + UNSPEC_SPECULATION_TRACKER ]) (define_c_enum "unspecv" [ @@ -287,6 +292,11 @@ (define_attr "length" "" ;; no predicated insns. (define_attr "predicated" "yes,no" (const_string "no")) +;; Set to true on an insn that requires the speculation tracking state to be +;; in the tracking register before the insn issues. Otherwise the compiler +;; may chose to hold the tracking state encoded in SP. +(define_attr "speculation_barrier" "true,false" (const_string "false")) + ;; ------------------------------------------------------------------- ;; Pipeline descriptions and scheduling ;; ------------------------------------------------------------------- @@ -3079,7 +3089,7 @@ (define_insn "*divsi3_uxtw" (define_insn "cmp" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:GPI 0 "register_operand" "r,r,r") + (compare:CC (match_operand:GPI 0 "register_operand" "rk,rk,rk") (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")))] "" "@ @@ -6088,6 +6098,21 @@ (define_expand "doloop_end" DONE; }) +;; Track speculation through conditional branches. We assume that +;; SPECULATION_TRACKER_REGNUM is reserved for this purpose when necessary. +(define_insn "speculation_tracker" + [(set (reg:DI SPECULATION_TRACKER_REGNUM) + (unspec [(reg:DI SPECULATION_TRACKER_REGNUM) (match_operand 0)] + UNSPEC_SPECULATION_TRACKER))] + "" + { + operands[1] = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); + output_asm_insn ("csel\\t%1, %1, xzr, %m0", operands); + return ""; + } + [(set_attr "type" "csel")] +) + ;; Helper for aarch64.c code. (define_expand "set_clobber_cc" [(parallel [(set (match_operand 0) @@ -6100,7 +6125,8 @@ (define_insn "speculation_barrier" "" "isb\;dsb\\tsy" [(set_attr "length" "8") - (set_attr "type" "block")] + (set_attr "type" "block") + (set_attr "speculation_barrier" "true")] ) ;; AdvSIMD Stuff diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index 0be1f0d..5d54853 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -67,6 +67,16 @@ cortex-a57-fma-steering.o: $(srcdir)/config/aarch64/cortex-a57-fma-steering.c \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/aarch64/cortex-a57-fma-steering.c +aarch64-speculation.o: $(srcdir)/config/aarch64/aarch64-speculation.cc \ + $(CONFIG_H) \ + $(SYSTEM_H) \ + $(TM_H) \ + $(TARGET_H) \ + $(RTL_BASE_H) \ + $(TREE_PASS_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_SPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/aarch64/aarch64-speculation.cc + comma=, MULTILIB_OPTIONS = $(subst $(comma),/, $(patsubst %, mabi=%, $(subst $(comma),$(comma)mabi=,$(TM_MULTILIB_CONFIG)))) MULTILIB_DIRNAMES = $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9804808..ddba9c8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -598,7 +598,7 @@ Objective-C and Objective-C++ Dialects}. -mpc-relative-literal-loads @gol -msign-return-address=@var{scope} @gol -march=@var{name} -mcpu=@var{name} -mtune=@var{name} @gol --moverride=@var{string} -mverbose-cost-dump} +-moverride=@var{string} -mverbose-cost-dump -mtrack-speculation} @emph{Adapteva Epiphany Options} @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol @@ -14654,6 +14654,14 @@ This option only has an effect if @option{-ffast-math} or precision of division results to about 16 bits for single precision and to 32 bits for double precision. +@item -mtrack-speculation +@itemx -mno-track-speculation +Enable or disable generation of additional code to track speculative +execution through conditional branches. The tracking state can then +be used by the compiler when expanding calls to +@code{__builtin_speculation_safe_copy} to permit a more efficient code +sequence to be generated. + @item -march=@var{name} @opindex march Specify the name of the target architecture and, optionally, one or From patchwork Fri Jul 27 09:37:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143025 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp600177ljj; Fri, 27 Jul 2018 02:40:44 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfjd6q74wxGAJ3VCRetzBYu0T2B2L5AdtYw5kFLbtH2AXPS65F6W438eKrrQDxw6AspHhb+ X-Received: by 2002:a63:8c51:: with SMTP id q17-v6mr5525507pgn.236.1532684444875; Fri, 27 Jul 2018 02:40:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684444; cv=none; d=google.com; s=arc-20160816; b=D5lHVZlIBdrm2ZexaMeMIDUl7g4Jd8lRIo3SsHiX6FH3J+MbE1ytiYQ0o+DlXsp9qt 3GF6+F0sKSvK9Il2YAerbXPTnzKe3sfZwhwGs2LBAoQ+TSeaY0f17tJ485o68W4P2tLI OGUOO1GFy/I/jd+ffR8tObT08mwJqoisx0/Vb+ofm/VJrKbEzHVtqt+0FgunRrz34Pf+ 8sqP88FpgeFR5hTCEqxC8YwjCPm/jO7SYy7/Fb++FIV6bg6KAsISZJi3a7Z03BAnLoQi c6ApKTxxz5DS0NChc8m9WJwDXSHw6p8UvUurNUfh5K8O3GjN2WAt6cwfYaS9N1QIser1 1jeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=4/pAfxltGbLmiFNxVdiCJd4cT4lGGlEBErVX+jbkJdc=; b=GUl+lJMfVCKnBA31+iEvp0pk8FuvV2H9qFpQI5wM0pU1WUgm202IqwxxsRNsDkyxpW 67PjR//qvyI40XcuGwt0xku7X2q2AEFfJEVF94twDyn8om3XN5JdGF46GrgHEQm8Vb1W msUwk4MGBmkj5J4Y/NFNwaJH3vpJdiiDfzcAoDU9PYp93L8ycqeaYAa8auJETRt1AL6c tkzLFH7ILa2tQS5l6le0AjsdE5eCkAMNxTwQzrXuWUDFMbZUd+82LVSCHLusqVTMcQco 3vDT5OOWv3SRUeblZ4phNNsOXfm5VokykMIHxpwwQ01ZNGdHz77tLVA5zVci0q5lLNys MeYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=RZw0UWaq; spf=pass (google.com: domain of gcc-patches-return-482511-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482511-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id d20-v6si3150697pls.477.2018.07.27.02.40.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:40:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482511-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=RZw0UWaq; spf=pass (google.com: domain of gcc-patches-return-482511-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482511-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=rGTFZN1aYFpLZvM8 MF4HF9AhKYd2G0ZmKfi3jpg6YN3W0guncTxcDdkbas0Gl2iJWrazgE7pt2kNaK8F kxpUg9FgmepRgtf7ggIsjYDSdXZKQGFbBpN3EFCsPkY0yIh9BU3fd2gOsx2Xtf0y VG3kN5oXqGySwXydPsJyqOvdiM4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=khxVvZ4VBSs63V6+E9vHOH S9fww=; b=RZw0UWaqPouj5aqHb8bDvMwU8Z4gQTiycpflrhDTcJSroAicd7tojj A0yXbG5QLMzXnQXYAUnMv8uQf8yaeM9PiUuQ4jYfJxPWg8Q6YY6opPSerdOwiu9A 7Xf4srMIqnVDhEko/sCf45stHCaVeQPbNxmGn0GbeCcAzciwPJacQ= Received: (qmail 48235 invoked by alias); 27 Jul 2018 09:38:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48009 invoked by uid 89); 27 Jul 2018 09:38:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:36 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCg-0006D5-JI for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from foss.arm.com ([217.140.101.70]:47238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCg-0006CH-74 for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 87F561682; Fri, 27 Jul 2018 02:38:29 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E46AF3F575; Fri, 27 Jul 2018 02:38:28 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 07/11] AArch64 - use CSDB based sequences if speculation tracking is enabled Date: Fri, 27 Jul 2018 10:37:51 +0100 Message-Id: <1532684275-13041-8-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 In this final patch, now that we can track speculation through conditional branches, we can use this information to use a less expensive CSDB based speculation barrier. * config/aarch64/iterators.md (ALLI_TI): New iterator. * config/aarch64/aarch64.md (despeculate_copy): New expand. (despeculate_copy_insn): New insn. (despeculate_copyti_insn): New insn. (despeculate_simple): New insn (despeculate_simpleti): New insn. * config/aarch64/aarch64.c (aarch64_speculation_safe_value): New function. (TARGET_SPECULATION_SAFE_VALUE): Redefine to aarch64_speculation_safe_value. (aarch64_print_operand): Handle const0_rtx in modifier 'H'. --- gcc/config/aarch64/aarch64.c | 48 ++++++++++++++++++++ gcc/config/aarch64/aarch64.md | 97 +++++++++++++++++++++++++++++++++++++++++ gcc/config/aarch64/iterators.md | 3 ++ 3 files changed, 148 insertions(+) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index cca465e..fc6eb1c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6760,6 +6760,12 @@ aarch64_print_operand (FILE *f, rtx x, int code) break; case 'H': + if (x == const0_rtx) + { + asm_fprintf (f, "xzr"); + break; + } + if (!REG_P (x) || !GP_REGNUM_P (REGNO (x) + 1)) { output_operand_lossage ("invalid operand for '%%%c'", code); @@ -17638,6 +17644,45 @@ aarch64_select_early_remat_modes (sbitmap modes) } } +/* Override the default target speculation_safe_value. */ +static rtx +aarch64_speculation_safe_value (machine_mode mode, + rtx result, rtx val, rtx failval) +{ + /* Maybe we should warn if falling back to hard barriers. They are + likely to be noticably more expensive than the alternative below. */ + if (!aarch64_track_speculation) + return default_speculation_safe_value (mode, result, val, failval); + + if (!REG_P (val)) + val = copy_to_mode_reg (mode, val); + + if (!aarch64_reg_or_zero (failval, mode)) + failval = copy_to_mode_reg (mode, failval); + + switch (mode) + { + case E_QImode: + emit_insn (gen_despeculate_copyqi (result, val, failval)); + break; + case E_HImode: + emit_insn (gen_despeculate_copyhi (result, val, failval)); + break; + case E_SImode: + emit_insn (gen_despeculate_copysi (result, val, failval)); + break; + case E_DImode: + emit_insn (gen_despeculate_copydi (result, val, failval)); + break; + case E_TImode: + emit_insn (gen_despeculate_copyti (result, val, failval)); + break; + default: + gcc_unreachable (); + } + return result; +} + /* Target-specific selftests. */ #if CHECKING_P @@ -18110,6 +18155,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_SELECT_EARLY_REMAT_MODES #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes +#undef TARGET_SPECULATION_SAFE_VALUE +#define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value + #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 528d03d..321a674 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6129,6 +6129,103 @@ (define_insn "speculation_barrier" (set_attr "speculation_barrier" "true")] ) +;; Support for __builtin_speculation_safe_value when we have speculation +;; tracking enabled. Use the speculation tracker to decide whether to +;; copy operand 1 to the target, or to copy the fail value (operand 2). +(define_expand "despeculate_copy" + [(set (match_operand:ALLI_TI 0 "register_operand" "=r") + (unspec_volatile:ALLI_TI + [(match_operand:ALLI_TI 1 "register_operand" "r") + (match_operand:ALLI_TI 2 "aarch64_reg_or_zero" "rZ") + (use (reg:DI SPECULATION_TRACKER_REGNUM)) + (clobber (reg:CC CC_REGNUM))] UNSPECV_SPECULATION_BARRIER))] + "" + " + { + if (operands[2] == const0_rtx) + { + rtx tracker; + if (mode == TImode) + tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); + else + tracker = gen_rtx_REG (mode, SPECULATION_TRACKER_REGNUM); + + emit_insn (gen_despeculate_simple (operands[0], operands[1], + tracker)); + DONE; + } + } + " +) + +;; Patterns to match despeculate_copy. Note that "hint 0x14" is the +;; encoding for CSDB, but will work in older versions of the assembler. +(define_insn "*despeculate_copy_insn" + [(set (match_operand:ALLI 0 "register_operand" "=r") + (unspec_volatile:ALLI + [(match_operand:ALLI 1 "register_operand" "r") + (match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ") + (use (reg:DI SPECULATION_TRACKER_REGNUM)) + (clobber (reg:CC CC_REGNUM))] UNSPECV_SPECULATION_BARRIER))] + "" + { + operands[3] = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); + output_asm_insn ("cmp\\t%3, #0\;csel\\t%0, %1, %2, ne\;hint\t0x14 // csdb", + operands); + return ""; + } + [(set_attr "length" "12") + (set_attr "type" "block") + (set_attr "speculation_barrier" "true")] +) + +;; Pattern to match despeculate_copyti +(define_insn "*despeculate_copyti_insn" + [(set (match_operand:TI 0 "register_operand" "=r") + (unspec_volatile:TI + [(match_operand:TI 1 "register_operand" "r") + (match_operand:TI 2 "aarch64_reg_or_zero" "rZ") + (use (reg:DI SPECULATION_TRACKER_REGNUM)) + (clobber (reg:CC CC_REGNUM))] UNSPECV_SPECULATION_BARRIER))] + "" + { + operands[3] = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); + output_asm_insn + ("cmp\\t%3, #0\;csel\\t%0, %1, %2, ne\;csel\\t%H0, %H1, %H2, ne\;hint\t0x14 // csdb", + operands); + return ""; + } + [(set_attr "length" "16") + (set_attr "type" "block") + (set_attr "speculation_barrier" "true")] +) + +(define_insn "despeculate_simple" + [(set (match_operand:ALLI 0 "register_operand" "=r") + (unspec_volatile:ALLI + [(match_operand:ALLI 1 "register_operand" "r") + (use (match_operand:ALLI 2 "register_operand" ""))] + UNSPECV_SPECULATION_BARRIER))] + "" + "and\\t%0, %1, %2\;hint\t0x14 // csdb" + [(set_attr "type" "block") + (set_attr "length" "8") + (set_attr "speculation_barrier" "true")] +) + +(define_insn "despeculate_simpleti" + [(set (match_operand:TI 0 "register_operand" "=r") + (unspec_volatile:TI + [(match_operand:TI 1 "register_operand" "r") + (use (match_operand:DI 2 "register_operand" ""))] + UNSPECV_SPECULATION_BARRIER))] + "" + "and\\t%0, %1, %2\;and\\t%H0, %H1, %2\;hint\t0x14 // csdb" + [(set_attr "type" "block") + (set_attr "length" "12") + (set_attr "speculation_barrier" "true")] +) + ;; AdvSIMD Stuff (include "aarch64-simd.md") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d846118..450edea 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -35,6 +35,9 @@ (define_mode_iterator SHORT [QI HI]) ;; Iterator for all integer modes (up to 64-bit) (define_mode_iterator ALLI [QI HI SI DI]) +;; Iterator for all integer modes (up to 128-bit) +(define_mode_iterator ALLI_TI [QI HI SI DI TI]) + ;; Iterator for all integer modes that can be extended (up to 64-bit) (define_mode_iterator ALLX [QI HI SI]) From patchwork Fri Jul 27 09:37:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143024 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp599999ljj; Fri, 27 Jul 2018 02:40:33 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe78Ju4IqMhlM/Py1Rebs868nhFPmtUa+cX/V6CZkVubsCE4MUdjKGZiN1t9bwah9/KIDon X-Received: by 2002:a17:902:bb0d:: with SMTP id l13-v6mr5458164pls.5.1532684433050; Fri, 27 Jul 2018 02:40:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684433; cv=none; d=google.com; s=arc-20160816; b=l38s4vEChGJiQrU8+leawrlgew2nTtBd1p2h3/zfsV7Az3qXxitkl8wunXYOx3RDp1 1rxDQRdgqa5MnIKxMIVDuffB4e22sjSWslZrYbHIF+QZMmr32Z0C30HVSWxO8ayK0vk3 oercilkeggWWRzNCIKnEjQDkfHAOKoeZDBDmATzseXx3xWE5rx/HZYZ3om0BxpG0gAty 1a2TUuIZrVMRWaqtcaIRXFhTMcykAT8ilmQyCeWaq9dcTnHroWpgGRWoJDIbcpkwnNjW vdSD3rzrmb73KGBW+Nkcc9HZoC6JgQbT4S/xLd9vWaUJB5WB74GpekiMyAG68ajt0u3S qYZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=9dB6TBlbPYHQrGKJOIGWpjUzEvKlEGF3a3kOyyfJ8vk=; b=yf11mgjuAcz/lFHEFOMtUV4nLE+jOIE/VoL3qzFGQPfcQ7DuorInzkJMEZ+7+ccXoC u1pL8hx2BQjlWE1OCbfFj9Ead4j+PBJvRZbap0JDXlR7QoxahAw5K/thV77ha0UwoqqB jwngdx5UTQSo/FDCsVnNu330cdSWqaiSzSw+tc9lOXgweHCw9fuX4qNv7OQ2NFM2hp75 ZdbVsKR2b/UCCY9mmEFeZMWgH3ZZvMAL8K+sfa9yrOZR22jJYO7foN2XPORkrxk2UR8S c5AO6V/K4aDXQkMwcPZTq+BVBQaeAOKGdNVGgQluTJ+ufpXfYrphnd/PxjqqbJaTf9zB g0mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=k1RzQ8uN; spf=pass (google.com: domain of gcc-patches-return-482510-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482510-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 43-v6si3228760plc.30.2018.07.27.02.40.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:40:33 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482510-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=k1RzQ8uN; spf=pass (google.com: domain of gcc-patches-return-482510-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482510-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=WMcJO2ZgAPcmpHAR BvzWH/VxEzzSipkUXdu48Q6RGYalvHAxyU/HUhuLT+Ef7r10z870Q1aZGc6Mj9kK 17nNq3lOEMNwLGNO4YrsNjRqzAU7PU22kU+hb77nGu1I8XLYUiXtrKgWjoxmDOaX PPl7ZOuWNrrydJu/E4QOloSYulk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=TcYsc1UtBxEnYX3+7/SJAN OGj20=; b=k1RzQ8uNZSzidkeWYTnF7Cl2ZGRr16GFh3M7rmaJC/5oI/6KPqG+e0 9hFB8pouHpYFQOC1bG9UZLGjKvo+8wBtbotPX9cGAI4BtQ0OcLzvWKKxH7gRIroO KnyPzqJBzD5+aNt2nA4Sf997jd3N1Y4DwBtcIRkvcjrVIN+v23KXk= Received: (qmail 48143 invoked by alias); 27 Jul 2018 09:38:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47984 invoked by uid 89); 27 Jul 2018 09:38:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:36 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCh-0006DV-5T for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from foss.arm.com ([217.140.101.70]:47232) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCg-0006BH-PV for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D0281684; Fri, 27 Jul 2018 02:38:30 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C60D03F575; Fri, 27 Jul 2018 02:38:29 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org, rguenther@suse.de Cc: Richard Earnshaw Subject: [PATCH 08/11] targhooks - provide an alternative hook for targets that never execute speculatively Date: Fri, 27 Jul 2018 10:37:52 +0100 Message-Id: <1532684275-13041-9-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This hook adds an alternative implementation for the target hook TARGET_HAVE_SPECULATION_SAFE_VALUE; it can be used by targets that have no CPU implementations that execute code speculatively. All that is needed for such targets now is to add: #undef TARGET_HAVE_SPECULATION_SAFE_VALUE #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed. to where you have your other target hooks and you're done. gcc: * targhooks.h (speculation_safe_value_not_needed): New prototype. * targhooks.c (speculation_safe_value_not_needed): New function. * target.def (have_speculation_safe_value): Update documentation. * doc/tm.texi: Regenerated. --- gcc/doc/tm.texi | 5 +++++ gcc/target.def | 7 ++++++- gcc/targhooks.c | 7 +++++++ gcc/targhooks.h | 1 + 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 15b0ab8..f36e376 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -11959,6 +11959,11 @@ This hook is used to determine the level of target support for a pattern named @code{speculation_barrier}. Else it returns true for the first case and whether the pattern is enabled for the current compilation for the second case. + + For targets that have no processors that can execute instructions + speculatively an alternative implemenation of this hook is available: + simply redefine this hook to @code{speculation_safe_value_not_needed} + along with your other target hooks. @end deftypefn @deftypefn {Target Hook} rtx TARGET_SPECULATION_SAFE_VALUE (machine_mode @var{mode}, rtx @var{result}, rtx @var{val}, rtx @var{failval}) diff --git a/gcc/target.def b/gcc/target.def index d598067..5599eb4 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4206,7 +4206,12 @@ DEFHOOK The default implementation returns false if the target does not define\n\ a pattern named @code{speculation_barrier}. Else it returns true\n\ for the first case and whether the pattern is enabled for the current\n\ - compilation for the second case.", + compilation for the second case.\n\ + \n\ + For targets that have no processors that can execute instructions\n\ + speculatively an alternative implemenation of this hook is available:\n\ + simply redefine this hook to @code{speculation_safe_value_not_needed}\n\ + along with your other target hooks.", bool, (bool active), default_have_speculation_safe_value) DEFHOOK diff --git a/gcc/targhooks.c b/gcc/targhooks.c index 06de1e3..62051a9 100644 --- a/gcc/targhooks.c +++ b/gcc/targhooks.c @@ -2324,6 +2324,13 @@ default_have_speculation_safe_value (bool active) return false; #endif } +/* Alternative implementation of TARGET_HAVE_SPECULATION_SAFE_VALUE + that can be used on targets that never have speculative execution. */ +bool +speculation_safe_value_not_needed (bool active) +{ + return !active; +} /* Default implementation of the speculation-safe-load builtin. This implementation simply copies val to result and generates a diff --git a/gcc/targhooks.h b/gcc/targhooks.h index 74ffe5f..b716b97 100644 --- a/gcc/targhooks.h +++ b/gcc/targhooks.h @@ -286,6 +286,7 @@ extern void default_select_early_remat_modes (sbitmap); extern tree default_preferred_else_value (unsigned, tree, unsigned, tree *); extern bool default_have_speculation_safe_value (bool); +extern bool speculation_safe_value_not_needed (bool); extern rtx default_speculation_safe_value (machine_mode, rtx, rtx, rtx); #endif /* GCC_TARGHOOKS_H */ From patchwork Fri Jul 27 09:37:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143022 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp599666ljj; Fri, 27 Jul 2018 02:40:09 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcg/MubPwapsHSgQltvEB2C0RCQGIe0INsTR2PGZhbne+1F0ZdvCJ3cewuoXU+HAFnvANoT X-Received: by 2002:a63:551e:: with SMTP id j30-v6mr5249255pgb.92.1532684409062; Fri, 27 Jul 2018 02:40:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684409; cv=none; d=google.com; s=arc-20160816; b=rOxMATFnmR860kanTMaoX3+DcjVQwNPO9waZ/MUDTqXMxPvTOXwUWvIdEKkFvda/pg vCRsKdM9+55Tb/lmUhhC1zfWEUPJbvd5ILbrzLcLYAQmKxdQSW5oDHXqkKhZZ8pHMesX GhWrhepPC8ZyK6j/y5tCLzA1+Fde5yFdX2aPHcCZMZchd5yqEYuWjswwuZR98/ioQeXA Ey8oAJN98DNAWALDrrEtED3vjTmR/Wuq3/uo/BRK6q5HEGdhyUtQDZiZTSQfctuTgsDZ WRLl66MjQYWMm3feMA+9vQ7gCS6mAttsXELqan1rBAdQDbMA19INLcUnIPFVzfzAcjAu ikRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=cvguss93BFeJqzAM7MmEMeLFuGRrrK9cCgTuHopjN0I=; b=0dp/VzH97csQAf8RlKPQxQxEecu5SRl8cypcc4hvu3DDCtFF6ijLiuM84Pph8SELuk OPm3zFGeqyjiTt+Do7nDbp3DGn8OuseAVtY5R4Zk6taRjYAJ3ZLI+Bg/05SzLR2pODJ+ 58fL3j8hKrNWNcH6ZVQmsCcS8nZye3pt/kLRJbxoDCC4OTYfGgw6M8QCP+XCGLZxyf+T 0QRfBciJVO7wcbxYSwlJEn/WqqMJInmge/0wjSnJkxmp6SwC+AkG4BMbI9nyt/r6Q+gj i747kWGk2C9PRkBuS+QdSIvHrypb8uObODCc0k+0+OHq4ULe1T0oTL1XbxpvA54QYr4f M8/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DyVV0qGW; spf=pass (google.com: domain of gcc-patches-return-482508-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482508-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id v129-v6si3733092pfv.278.2018.07.27.02.40.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:40:09 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482508-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DyVV0qGW; spf=pass (google.com: domain of gcc-patches-return-482508-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482508-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=KfE70SBqI54QLpiQ nGfQI/dmyyP3sBHrC24aXo/H/NZwiaMJysCUm1UEk81MUcIxnhM1CUE15KKSgtx8 J36s966fkqTmeqhiKnSNODSyqDo3EJf8HLYEZhU4CPHu1jiiH3ExvkGh9jWhynz7 /z8wILeDYZGxLOaBbDKtHlNd7hs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=A5EADpu8VqgRJY0MXvy7pi dvmVQ=; b=DyVV0qGWWy13SzcMIj0TaWp/XEDsOhWD5pNpqpdkJD6S/kIP99LEv2 f0R7ilEMD85eyFRTfBzv3w6xixz7H3ybatXfcbrmQZrfXhCzY8XtuYm9S5fhy+ec nBGYc/W2Xkwkzkv6hBiwO+xRYC1OwJU746syCiF9c2iI3bP+wt2QU= Received: (qmail 48002 invoked by alias); 27 Jul 2018 09:38:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47885 invoked by uid 89); 27 Jul 2018 09:38:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:36 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCi-0006Eg-2E for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from foss.arm.com ([217.140.101.70]:47238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCh-0006CH-QG for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 91CAF1682; Fri, 27 Jul 2018 02:38:31 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CAF1C3F575; Fri, 27 Jul 2018 02:38:30 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org, ni1d@arrl.net Cc: Richard Earnshaw Subject: [PATCH 09/11] pdp11 - example of a port not needing a speculation barrier Date: Fri, 27 Jul 2018 10:37:53 +0100 Message-Id: <1532684275-13041-10-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This patch is intended as an example of all that is needed if the target system doesn't support CPUs that have speculative execution. I've chosen the pdp11 port on the basis that it's old enough that this is likely to be true for all existing implementations and that there is also little chance of that changing in future! * config/pdp11/pdp11.c (TARGET_HAVE_SPECULATION_SAFE_VALUE): Redefine to speculation_safe_value_not_needed. --- gcc/config/pdp11/pdp11.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 1bcdaed..62c653f 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -291,6 +291,9 @@ static bool pdp11_scalar_mode_supported_p (scalar_mode); #undef TARGET_INVALID_WITHIN_DOLOOP #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null + +#undef TARGET_HAVE_SPECULATION_SAFE_VALUE +#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed /* A helper function to determine if REGNO should be saved in the current function's stack frame. */ From patchwork Fri Jul 27 09:37:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143023 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp599849ljj; Fri, 27 Jul 2018 02:40:21 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeoUliD/E1hDkzQa3GDXaVW9eDHtq8qX1l4hV1UxPMM330npbVGSC0gVElnZ6k5ao8f1Bxc X-Received: by 2002:a63:f804:: with SMTP id n4-v6mr5515128pgh.106.1532684421742; Fri, 27 Jul 2018 02:40:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684421; cv=none; d=google.com; s=arc-20160816; b=dkious34Rrt3Bj7Vusz1FmxqJlPWXrYN9ubtkZXjsDt0XNODsLgtZcXA4c0P+b+y64 VCvlkG3LuMm+ym2MIVfFxXe1B1D5pZwzPa/Iq2OT8HtODP9vnyh82Wi50+339/VTfUvI pCIwkCNQg+yoFMY3DQrrtCAkeCfor+L9qyNL6jcHcZntqglvYyvFbPFyHNk75qRWGEyw 7g9uQ6JI9JmLftvliFYDrqa6NKesraKzDm0MnFAb6AxmWlMSgrU8Zy3jUTlza6sUoF85 8q/V1tkuQ66kd0KsKu7X7JIWswXNJJGkOjVcuKtnYIbBtSEOhCEbwq0iYJT/q1xb76BS XJHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=zfwVBwzOLyHocEz+mnje7BhiedRM4ny6sesabYTbU1A=; b=RFHQpAZZsIPfounScSZkFGeN9pGJ4zaL739OCX6qAlQviZD/TK5JObGT8QqDSWatKL g/j8ogFxGilhrkNJ7G16R1yBQ0OgqxwBtmaZj2Muym//uO3I4I8LNZP0Ds1oCRSAYiU7 GQRng0xpQlE/Ri2JCjDRKjvQ4U+KLwYzaXDE7wOl9h1olhAZ9MK6j8Dm+8YfX/PUtWUt 161EQr0NDtpWJ5KPiRdETkBX6UugEz09VAL3kyYpKsEBcQ2YZyrZ3i+NHzuNuhcTAe5J SX2OMhg8hF/rIX30ikSyHuEkGAhAz9gwrnJN7MmtZr2DVjtF9bUHTuAbcRY3FfMSVvHG 0Peg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=EwyKl7vc; spf=pass (google.com: domain of gcc-patches-return-482509-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482509-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id o1-v6si3129442plb.279.2018.07.27.02.40.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:40:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482509-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=EwyKl7vc; spf=pass (google.com: domain of gcc-patches-return-482509-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482509-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=rhW9mGpTWNstCMtP sP5uzIBO0wtfadHI6Jr1ZET+JcAmEgXrI2iRP6skfMm+xcX6zZ2c16C0ekE1DJt6 gJYFtxBO7zdASyZ3FTzR42nUCE+brDj6nj5EwmvGGzWw8XzXl1aYSS6M7Cc7fo2l oTEvAWInhKmNACfy0mRAIwE73AI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=mHi6sG3vxRV66leBRrxpRY kIQrg=; b=EwyKl7vcCIrNMV8rSj2CSUGRxZtmOpYAfbtOuYzKG5W9ugHhf5VJTe fXrOz0MiLIyfhqVMSVjq+lvPvutHYJ4xf8VCfcBn18MUh2efG4ArT2Pxl5jQ8ox4 60a6eYGxB1f84A2Cyf8h3iCHjk+DaQyPQvjpGmdpVarO4ATfzLGBw= Received: (qmail 48043 invoked by alias); 27 Jul 2018 09:38:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47893 invoked by uid 89); 27 Jul 2018 09:38:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy=3019 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:36 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCj-0006FY-89 for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from foss.arm.com ([217.140.101.70]:47232) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCi-0006BH-VP for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:33 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA2A01684; Fri, 27 Jul 2018 02:38:32 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CFE363F575; Fri, 27 Jul 2018 02:38:31 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org, hubicka@ucw.cz, ubizjak@gmail.com Cc: Richard Earnshaw Subject: [PATCH 10/11] x86 - add speculation_barrier pattern Date: Fri, 27 Jul 2018 10:37:54 +0100 Message-Id: <1532684275-13041-11-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This patch adds a speculation barrier for x86, based on my understanding of the required mitigation for that CPU, which is to use an lfence instruction. This patch needs some review by an x86 expert and if adjustments are needed, I'd appreciate it if they could be picked up by the port maintainer. This is supposed to serve as an example of how to deploy the new __builtin_speculation_safe_value() intrinsic on this architecture. * config/i386/i386.md (unspecv): Add UNSPECV_SPECULATION_BARRIER. (speculation_barrier): New insn. --- gcc/config/i386/i386.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 559ad93..73948c1 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -301,6 +301,9 @@ (define_c_enum "unspecv" [ ;; For CLDEMOTE support UNSPECV_CLDEMOTE + + ;; For Speculation Barrier support + UNSPECV_SPECULATION_BARRIER ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -20979,6 +20982,13 @@ (define_insn "cldemote" [(set_attr "type" "other") (set_attr "memory" "unknown")]) +(define_insn "speculation_barrier" + [(unspec_volatile [(const_int 0)] UNSPECV_SPECULATION_BARRIER)] + "" + "lfence" + [(set_attr "type" "other") + (set_attr "length" "3")]) + (include "mmx.md") (include "sse.md") (include "sync.md") From patchwork Fri Jul 27 09:37:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 143027 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp600512ljj; Fri, 27 Jul 2018 02:41:08 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfbZJUniO1opSxyZDo2/4eWZlT29sCZflgZxrhUuw6/vrdrvUIeET+E1xKF2Qh/WcwGP+YI X-Received: by 2002:a62:1157:: with SMTP id z84-v6mr5965620pfi.66.1532684468319; Fri, 27 Jul 2018 02:41:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532684468; cv=none; d=google.com; s=arc-20160816; b=ZxvexV7iF6hmhCwiDZ5EtMvVe1bd9EHl+RsMdmy7c3OKGPv0kiM49aip4AQw2cFTFt uZr4VZVBKSfo4IXkXgDbwolp31PzpmpHlAd+uzTLhRgFxc6iRWT/YrMolrAWMjQeRq6j Px/7GFp3qttEjv62ffoqld00aEa5zPvHc3lK+ExhEU6euWdgTrHb4p5mJjJNmVMKfdMT 1AUda4gQdhcAC7gp4rzF9MLnVObfctCVKWbbfG/66YsVnUZalk19qAypBccqKzaI5hWb EySmCqs4ewvxwkKY2s7lOSzbhjnxzyd9mXQMMhxt7YTWYB+cGJ1Tq8OvLb049UvLgifU bhng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=rz0y83+E++HmFHywSbS0UsCFEKHHs/NJYpdZYXhs7pM=; b=rStRFOchno/bSZt6rsUiyLoTyExQpFIuQ8BKSBoSwtYbVpE54lMRz6XzHcUSEM+3rz vU5wNRmunBzzrn5Cz8j8eR98Q5lu9t8tWQ/M3TrBSKIaPjIFGbqvAewoUvz6Gi9wPpG8 siErmcvRIWO1lTgE6UTxUExR/2S3KWGMixmOHwoF+lUzUFB5P8z9NLK9WpT+58V5ahTi hjLGZdwlXS0hjzutDa7UnYTpUDdB6YuMZrpHx31Xvh64P23w41+TkFsBSLyM1f6b2ngF DlNQOhBme5nam1H7YfN3pTfOjHU9UKMAr9FTFN5XN3tn3lC9jHvtQAbQ3lRYSFtu9yoD y9HA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=m14UaYJC; spf=pass (google.com: domain of gcc-patches-return-482513-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482513-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id w37-v6si3492596pgl.514.2018.07.27.02.41.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 02:41:08 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-482513-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=m14UaYJC; spf=pass (google.com: domain of gcc-patches-return-482513-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-482513-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=OfabSjJi1qbYIOE1 grXUtwqHMWqYWSk1k7N9Jj/7mbfyO8IU3VciKbSkwMc/DtxwiLFZDsxuLODmxBlB A9Bu0O6ptkIJWBV8JfxKevMFtfyLdSizKBLj10NgSr3LUfuwlHBvfC7lOZsmpN9M PYmrLEzSH8X2omuDAUSsTfO321Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=IuXB8MozArRh/bClGg65YM /R2Dw=; b=m14UaYJC57/uIh58hnJmDpuuR7Hti7leSrFaqXduGmaSN3KtkwLGYW XiaZ+Kc8PWm0wBAQ9M1G6cjWpSAfZJdK/QdXKByXvJSY2VNQAyVm6Z+9/RhAGAnM 5c/ZP65m88w5OLOSctEzJVV9uTrHXJoTmCsRQZqrM3QHQfS9ojWmg= Received: (qmail 48428 invoked by alias); 27 Jul 2018 09:38:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48201 invoked by uid 89); 27 Jul 2018 09:38:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.2 spammy=H*Ad:U*wschmidt X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Jul 2018 09:38:38 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizCk-0006GB-If for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:35 -0400 Received: from foss.arm.com ([217.140.101.70]:47232) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizCk-0006BH-90 for gcc-patches@gcc.gnu.org; Fri, 27 Jul 2018 05:38:34 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11B3C1682; Fri, 27 Jul 2018 02:38:34 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.207.74]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 045013F575; Fri, 27 Jul 2018 02:38:32 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, segher@kernel.crashing.org Cc: Richard Earnshaw , wschmidt@linux.ibm.com Subject: [PATCH 11/11] rs6000 - add speculation_barrier pattern Date: Fri, 27 Jul 2018 10:37:55 +0100 Message-Id: <1532684275-13041-12-git-send-email-Richard.Earnshaw@arm.com> In-Reply-To: <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> References: <1531154299-28349-1-git-send-email-Richard.Earnshaw@arm.com> <1532684275-13041-1-git-send-email-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This patch reworks the existing rs6000_speculation_barrier pattern to work with the new __builtin_sepculation_safe_value() intrinsic. The change is trivial as it simply requires renaming the existing speculation barrier pattern. So the total patch is to delete 14 characters! * config/rs6000/rs6000.md (speculation_barrier): Renamed from rs6000_speculation_barrier. * config/rs6000/rs6000.c (rs6000_expand_builtin): Adjust for new barrier pattern name. --- gcc/config/rs6000/rs6000.c | 2 +- gcc/config/rs6000/rs6000.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 1976072..46c6838 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16179,7 +16179,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case MISC_BUILTIN_SPEC_BARRIER: { - emit_insn (gen_rs6000_speculation_barrier ()); + emit_insn (gen_speculation_barrier ()); return NULL_RTX; } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 44d32d9..03870e9 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -12614,7 +12614,7 @@ (define_insn "group_ending_nop" return "ori 2,2,0"; }) -(define_insn "rs6000_speculation_barrier" +(define_insn "speculation_barrier" [(unspec_volatile:BLK [(const_int 0)] UNSPECV_SPEC_BARRIER)] "" "ori 31,31,0")