From patchwork Tue Jun 8 22:29:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 456261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3A82C4743F for ; Tue, 8 Jun 2021 22:30:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B98C561361 for ; Tue, 8 Jun 2021 22:30:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbhFHWce (ORCPT ); Tue, 8 Jun 2021 18:32:34 -0400 Received: from mail-qt1-f171.google.com ([209.85.160.171]:36502 "EHLO mail-qt1-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230507AbhFHWcb (ORCPT ); Tue, 8 Jun 2021 18:32:31 -0400 Received: by mail-qt1-f171.google.com with SMTP id r20so1235360qtp.3 for ; Tue, 08 Jun 2021 15:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GvNr0cURQ5TDqrTkg430MscO613gd9bfT50EURpL3BM=; b=iTRt/yLOjwIyBZ7rxne4pyfDmF7fNCafhlPIXasBUEQuXQCkItKNdHMc3IaYElhipB h+Xu0qQWmi6dD9j5ozTpy2X9cOKh4QhMzmzHy+O2i8K0RwGSZ3l5apqh78guv6sApjHy NPBwBWFH9Ab3BTEWLOlWIhfNQGaR7PN1c5fYc1YJYfPIb1unFReehNP0x7vcgh7JFVsM 7Y6GvKRF48zjK38I/Q2bJeklbH7Uok8snL7VW2z3g+7vCLaAdixsYBtaK3/v0Ws/Ag0n 8Tg0oh/iA8VKoRxR3nJjY+N8JtuTXjGs8CSzankRaXFOXQta4UJl/dRp5bPrbJe97gJY Yalg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GvNr0cURQ5TDqrTkg430MscO613gd9bfT50EURpL3BM=; b=lzfHF/eF8LAmQcBb1BTaTxdf5XrUqRrnKbT4WvlhBfiQFI4w1N0zFAAgAZMyf0ph9H O6maD+x3LWinUuhef9qiZySK2GRFI83hNblNnbFiwKA4O4kPb23gWdt77/kk9Ga6bVAn uKkS6W+2bG9U765HMjvAYGZ+xYODJ7KW4tkF8sikuAeCqv/+BxCblPpQNWICi+PyQ5yY 14LXziCjPxN75b1OgA7CPuKrVx93Ba6S0bBDKT6pTmTxMEQGlEh6okpWef81R7LbaUeQ 9skS/U9d14Rd363CiORwgsiamswQ4E+YWzsmQsOAYApmpw6mYNKQaajRIzfsF66gaJE6 Y4oA== X-Gm-Message-State: AOAM53317F7KTsvn8HkSvrriL+8JxNArk6q9iSnHUXSgZFEutcW8IpOx UtjqTASsLUJdgEPRy3yYIJY6URj2hipwM70I X-Google-Smtp-Source: ABdhPJz9Zb4jsyx6xyqpWTFrCCanff8KX/HO2Z8iTX77W/bHbQOfuE9DgFjUcKaiXI4GsgUyn9BvUA== X-Received: by 2002:ac8:5f4e:: with SMTP id y14mr5294678qta.253.1623191368819; Tue, 08 Jun 2021 15:29:28 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id h19sm10450736qtq.5.2021.06.08.15.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:29:28 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/5] firmware: qcom_scm: Introduce SCM calls to access LMh Date: Tue, 8 Jun 2021 18:29:22 -0400 Message-Id: <20210608222926.2707768-2-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210608222926.2707768-1-thara.gopinath@linaro.org> References: <20210608222926.2707768-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce SCM calls to access/configure limits management hardware(LMh). Signed-off-by: Thara Gopinath Reported-by: kernel test robot --- drivers/firmware/qcom_scm.c | 47 +++++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 4 ++++ include/linux/qcom_scm.h | 13 ++++++++++ 3 files changed, 64 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index ee9cb545e73b..0259e9ffb8a1 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1147,6 +1147,53 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) } EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); +bool qcom_scm_lmh_dcvsh_available(void) +{ + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); + +int qcom_scm_lmh_profile_change(u32 profile_id) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), + .args[0] = profile_id, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_profile_change); + +int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, u32 node_id, u64 version) +{ + dma_addr_t payload_phys; + void *payload_buf; + + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_VAL, QCOM_SCM_VAL), + .args[1] = payload_size, + .args[2] = limit_node, + .args[3] = node_id, + .args[4] = version, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); + if (!payload_buf) + return -ENOMEM; + memcpy(payload_buf, payload, payload_size); + + desc.args[0] = payload_phys; + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 632fe3142462..d92156ceb3ac 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -114,6 +114,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SVC_HDCP 0x11 #define QCOM_SCM_HDCP_INVOKE 0x01 +#define QCOM_SCM_SVC_LMH 0x13 +#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01 +#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 + #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 0165824c5128..0c92197769e7 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -109,6 +109,12 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); + +extern int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, + u32 node_id, u64 version); +extern int qcom_scm_lmh_profile_change(u32 profile_id); +extern bool qcom_scm_lmh_dcvsh_available(void); + #else #include @@ -170,5 +176,12 @@ static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; } + +int qcom_scm_lmh_dcvsh(u32 *payload, u32 payload_size, u64 limit_node, + u32 node_id, u64 version) + { return -ENODEV; } +int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } + +bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } #endif #endif From patchwork Tue Jun 8 22:29:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 456260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA954C48BCF for ; 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[71.163.245.5]) by smtp.googlemail.com with ESMTPSA id h19sm10450736qtq.5.2021.06.08.15.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:29:30 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/5] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Date: Tue, 8 Jun 2021 18:29:24 -0400 Message-Id: <20210608222926.2707768-4-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210608222926.2707768-1-thara.gopinath@linaro.org> References: <20210608222926.2707768-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interrupt support to notify the kernel of h/w initiated frequency throttling by LMh. Convey this to scheduler via thermal presssure interface. Signed-off-by: Thara Gopinath --- drivers/cpufreq/qcom-cpufreq-hw.c | 100 ++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index f86859bf76f1..95e17330aa9d 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -13,6 +13,7 @@ #include #include #include +#include #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) @@ -22,10 +23,13 @@ #define CLK_HW_DIV 2 #define LUT_TURBO_IND 1 +#define HZ_PER_KHZ 1000 + struct qcom_cpufreq_soc_data { u32 reg_enable; u32 reg_freq_lut; u32 reg_volt_lut; + u32 reg_current_vote; u32 reg_perf_state; u8 lut_row_size; }; @@ -33,7 +37,11 @@ struct qcom_cpufreq_soc_data { struct qcom_cpufreq_data { void __iomem *base; struct resource *res; + struct delayed_work lmh_dcvs_poll_work; const struct qcom_cpufreq_soc_data *soc_data; + cpumask_var_t cpus; + unsigned long throttled_freq; + int lmh_dcvs_irq; }; static unsigned long cpu_hw_rate, xo_rate; @@ -251,10 +259,79 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) } } +static inline unsigned long qcom_lmh_vote_to_freq(u32 val) +{ + return (val & 0x3FF) * 19200; +} + +static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) +{ + struct cpufreq_policy policy; + struct dev_pm_opp *opp; + struct device *dev; + unsigned long max_capacity, capacity, freq_hz; + unsigned int val, freq; + + val = readl_relaxed(data->base + data->soc_data->reg_current_vote); + freq = qcom_lmh_vote_to_freq(val); + freq_hz = freq * HZ_PER_KHZ; + + /* Do I need to calculate ceil and floor ? */ + dev = get_cpu_device(cpumask_first(data->cpus)); + opp = dev_pm_opp_find_freq_floor(dev, &freq_hz); + if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) + opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz); + + data->throttled_freq = freq_hz / HZ_PER_KHZ; + + cpufreq_get_policy(&policy, cpumask_first(data->cpus)); + + /* Update thermal pressure */ + max_capacity = arch_scale_cpu_capacity(cpumask_first(data->cpus)); + capacity = data->throttled_freq * max_capacity; + capacity /= policy.cpuinfo.max_freq; + /* Don't pass boost capacity to scheduler */ + if (capacity > max_capacity) + capacity = max_capacity; + arch_set_thermal_pressure(data->cpus, max_capacity - capacity); +} + +static void qcom_lmh_dcvs_poll(struct work_struct *work) +{ + struct qcom_cpufreq_data *data; + + data = container_of(work, struct qcom_cpufreq_data, lmh_dcvs_poll_work.work); + + qcom_lmh_dcvs_notify(data); + /** + * If h/w throttled frequency is higher than what cpufreq has requested for, stop + * polling and switch back to interrupt mechanism + */ + if (data->throttled_freq >= qcom_cpufreq_hw_get(cpumask_first(data->cpus))) + /* Clear the existing interrupts and enable it back */ + enable_irq(data->lmh_dcvs_irq); + else + mod_delayed_work(system_highpri_wq, &data->lmh_dcvs_poll_work, + msecs_to_jiffies(10)); +} + +static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) +{ + struct qcom_cpufreq_data *c_data = data; + + /* Disable interrupt and enable polling */ + disable_irq_nosync(c_data->lmh_dcvs_irq); + qcom_lmh_dcvs_notify(c_data); + mod_delayed_work(system_highpri_wq, &c_data->lmh_dcvs_poll_work, msecs_to_jiffies(10)); + + return 0; +} + static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x110, .reg_volt_lut = 0x114, + .reg_current_vote = 0x704, .reg_perf_state = 0x920, .lut_row_size = 32, }; @@ -285,6 +362,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) void __iomem *base; struct qcom_cpufreq_data *data; int ret, index; + bool lmh_mitigation_enabled = false; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -305,6 +383,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) index = args.args[0]; + lmh_mitigation_enabled = of_property_read_bool(pdev->dev.of_node, "qcom,support-lmh"); + res = platform_get_resource(pdev, IORESOURCE_MEM, index); if (!res) { dev_err(dev, "failed to get mem resource %d\n", index); @@ -329,6 +409,11 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) goto unmap_base; } + if (!alloc_cpumask_var(&data->cpus, GFP_KERNEL)) { + ret = -ENOMEM; + goto unmap_base; + } + data->soc_data = of_device_get_match_data(&pdev->dev); data->base = base; data->res = res; @@ -347,6 +432,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) goto error; } + cpumask_copy(data->cpus, policy->cpus); policy->driver_data = data; ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); @@ -370,6 +456,20 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); } + if (lmh_mitigation_enabled) { + data->lmh_dcvs_irq = platform_get_irq(pdev, index); + if (data->lmh_dcvs_irq < 0) { + ret = data->lmh_dcvs_irq; + goto error; + } + ret = devm_request_irq(dev, data->lmh_dcvs_irq, qcom_lmh_dcvs_handle_irq, + 0, "dcvsh-irq", data); + if (ret) { + dev_err(dev, "Error %d registering irq %x\n", ret, data->lmh_dcvs_irq); + goto error; + } + INIT_DEFERRABLE_WORK(&data->lmh_dcvs_poll_work, qcom_lmh_dcvs_poll); + } return 0; error: kfree(data); From patchwork Tue Jun 8 22:29:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 456262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 683C7C4743F for ; Tue, 8 Jun 2021 22:29:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FC3561361 for ; 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[71.163.245.5]) by smtp.googlemail.com with ESMTPSA id h19sm10450736qtq.5.2021.06.08.15.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:29:31 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/5] arm64: boot: dts: sdm45: Add support for LMh node Date: Tue, 8 Jun 2021 18:29:25 -0400 Message-Id: <20210608222926.2707768-5-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210608222926.2707768-1-thara.gopinath@linaro.org> References: <20210608222926.2707768-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Signed-off-by: Thara Gopinath --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d..fdd8d816f728 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3646,6 +3646,24 @@ swm: swm@c85 { }; }; + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,msm-hw-limits"; + reg = <0 0x17d70800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x4>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,msm-hw-limits"; + reg = <0 0x17d78800 0 0x401>; + interrupts = ; + qcom,lmh-cpu-id = <0x0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + sound: sound { }; @@ -4911,10 +4929,13 @@ cpufreq_hw: cpufreq@17d43000 { reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + qcom,support-lmh = <1>; }; wifi: wifi@18800000 {