From patchwork Mon Jun 7 09:33:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sinthu Raja X-Patchwork-Id: 455536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1813DC47082 for ; Mon, 7 Jun 2021 09:34:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F28B1611C1 for ; Mon, 7 Jun 2021 09:34:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230233AbhFGJgk (ORCPT ); Mon, 7 Jun 2021 05:36:40 -0400 Received: from egress-ip4b.ess.de.barracuda.com ([18.185.115.208]:59650 "EHLO egress-ip4b.ess.de.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230211AbhFGJgj (ORCPT ); Mon, 7 Jun 2021 05:36:39 -0400 Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx-outbound22-128.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 07 Jun 2021 09:34:42 +0000 Received: by mail-pg1-f199.google.com with SMTP id x188-20020a6363c50000b02902104a07607cso4481877pgb.1 for ; Mon, 07 Jun 2021 02:34:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mistralsolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f1pOe6308vus6hP91+4DHt5kXhy3eXU17PRCS8+OFk4=; b=JKj6xF8rFK1hQ3gCfCVRQUQ1hkojttuhz9jMqHIMjAN/LKExNMwob/VHAJCfVPhwIJ iyyXlDpGQpTOOy51g6uOp0AhuHyVok2l8jXfipnlSm2gi4YPe3UrjLmK0ap6e0znfjWO dz0PPuV3YwzZKAHHe8tVB4ks7K6ruVJCuzNBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f1pOe6308vus6hP91+4DHt5kXhy3eXU17PRCS8+OFk4=; b=Pl9UB9upQxftZxS7ixqHYW3pr9r5t2+OTujhmpxxqXcFB5yjEviSONRkbM+kzbhEEo bP1RvjZGZHrdj2Gu7jAZ6g9wcIh2b4LU2vooP7xbIEOqfOoTVRxi4ZcKOtXwyaBJkC3k 5PFrMGlOm6fg2SuzZz5GRGeZezhky3iRA+UiX+j0N+G6UtlNPD1bksJkEnSQ2NlF4Fhr RPA/tO8U/f3ZPK3DxNZ/5E4o53g4fSzhwLK5THURLoc/E7LxlhZWGey91TeC4yX7gV24 WL7PHeO+bFbz/mZdRZu2DcA5wSsXdifSDMpdevu1H6GE2CGNdahxDwa7B5RLI8wFTG+L TbgA== X-Gm-Message-State: AOAM533UtnPkbHCMiAtr0jI4FnmSBsYASL6luQFbqq5UxxKAQyKPPxos JCSAxJnCVZGXOTg63xwxymMNQWe7YbynwL/7Lgq7xNR5DCUKfbQ0ixAd6jmW2khCD90Gxc7oTFM 50dFqPmbq1llXj3D3/17Hzo2QEpAY0qo4g8zRJZ5XwYfAwabfyjqND2UqLg== X-Received: by 2002:a05:6a00:2d2:b029:2e9:c637:f0e3 with SMTP id b18-20020a056a0002d2b02902e9c637f0e3mr16439441pft.22.1623058481437; Mon, 07 Jun 2021 02:34:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfBzGpO4rndMukrh+43M+qS20AX4FHbj+asTRsiYgDcy8T/M5LDx693SDW7nBO6OYR1x/FZQ== X-Received: by 2002:a05:6a00:2d2:b029:2e9:c637:f0e3 with SMTP id b18-20020a056a0002d2b02902e9c637f0e3mr16439420pft.22.1623058481236; Mon, 07 Jun 2021 02:34:41 -0700 (PDT) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id e188sm7567400pfe.23.2021.06.07.02.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 02:34:40 -0700 (PDT) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Device Tree Mailing List , Linux ARM Mailing List , Lokesh Vutla , Amarnath MB , Sinthu Raja Subject: [PATCH V2 1/2] dt-bindings: arm: ti: Add bindings for J721E EAIK Date: Mon, 7 Jun 2021 15:03:13 +0530 Message-Id: <20210607093314.23909-2-sinthu.raja@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210607093314.23909-1-sinthu.raja@ti.com> References: <20210607093314.23909-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1623058482-305760-5423-518-1 X-BESS-VER: 2019.1_20210603.1645 X-BESS-Apparent-Source-IP: 209.85.215.199 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.232772 [from cloudscan15-76.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sinthu Raja J721E EdgeAI Kit (EAIK) is a low cost, small form factor board designed for TI’s J721E SoC. Add DT binding documentation for J721E EAIK Signed-off-by: Amarnath MB Signed-off-by: Sinthu Raja --- Change in V2: - Fix for dt_binding_check error. Documentation/devicetree/bindings/arm/ti/k3.yaml | 2 ++ .../devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index c5aa362e4026..923dd7cf1dc6 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -29,6 +29,8 @@ properties: - description: K3 J721E SoC items: + - enum: + - ti,j721e-eaik - const: ti,j721e - description: K3 J7200 SoC diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml index 6070456a7b67..464cee128811 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -135,7 +135,7 @@ examples: - | / { model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; + compatible = "ti,j721e-eaik", "ti,j721e"; #address-cells = <2>; #size-cells = <2>; From patchwork Mon Jun 7 09:33:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sinthu Raja X-Patchwork-Id: 456143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 470BBC4743F for ; Mon, 7 Jun 2021 09:34:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 323E7611BE for ; Mon, 7 Jun 2021 09:34:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230230AbhFGJgp (ORCPT ); Mon, 7 Jun 2021 05:36:45 -0400 Received: from egress-ip4b.ess.de.barracuda.com ([18.185.115.208]:59806 "EHLO egress-ip4b.ess.de.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230211AbhFGJgo (ORCPT ); Mon, 7 Jun 2021 05:36:44 -0400 Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx-outbound22-128.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 07 Jun 2021 09:34:48 +0000 Received: by mail-pf1-f199.google.com with SMTP id e19-20020aa78c530000b02902e9ca53899dso7421894pfd.22 for ; Mon, 07 Jun 2021 02:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mistralsolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V7JxcpmiqLU86QKh2NcFdnLMmgXJWX3OCDrA9CclY98=; b=CHbBcHzffpPPZUKZjd63/PkNMqNlg+aGMq94w/3CX6x08wIw3gr+WHfRkOYuId38yn 7E4PTmUaC7pEPzcm+Gi2suRWLBXGOEc32WzO4HwpA/NOC4FCeA9QdSGQW4zRm49X/qnZ oLi1QrRTJJ4VkYsBO+98wgSPVSTNzo7EVPAiQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V7JxcpmiqLU86QKh2NcFdnLMmgXJWX3OCDrA9CclY98=; b=Iqn/RD1BDXX26Xw9J3/eQmznsHqEwCjZJ9QsLtUnJOJFo1mObkt1YsOoA9LyPH+TkB 10ncsWKuYiD30ujitM8E5xWoRoR42TLON2TJo7iCT5M/aMHyM1GAdm43+eJc53yGiJ27 5FhetfeTG+0LFQ2qPKlq1U43EzrzlHN5Atetvd1TLKku9gGsHVitytBZLWr66Ck970GN oX6NLLMN8qOAU62kH6KO5A8RBZz4Gj2WsjQ7FSHQEFmYe9PI6G1jC68Bje9Q2MMTxThz Y4VepweVdQt3dq9TBg05HBv2jk+JH/swYSusZTtAAWm5qVRNh0tUARhCqSF4AXpCOeTg YgFw== X-Gm-Message-State: AOAM533iDMrM59iu36bPiwHpSyCTEumitVdlKinXp5lhDTX7Rmu918Mp OAMxnO73tZDJoMF5S06eU/eHvuYxxIYni0PrXiheqgMdClRwMlr/0RfoaZzg9VneE5M1OYTYILu 8pLK0jmQG80yOLls08YEfVvR2R8V4sqlLaPh8gSZ6f485/Mbj2wy7apk4wA== X-Received: by 2002:a17:90a:4a12:: with SMTP id e18mr19748957pjh.213.1623058485378; Mon, 07 Jun 2021 02:34:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwC1VuHsvOb2VMBZXAVGZDIfFPP2YuPEY/aw2PlL+878nVxBE9KPU2XxgwoejIfa0Dbq5D8ug== X-Received: by 2002:a17:90a:4a12:: with SMTP id e18mr19748927pjh.213.1623058485089; Mon, 07 Jun 2021 02:34:45 -0700 (PDT) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id e188sm7567400pfe.23.2021.06.07.02.34.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 02:34:44 -0700 (PDT) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Device Tree Mailing List , Linux ARM Mailing List , Lokesh Vutla , Amarnath MB , Sinthu Raja Subject: [PATCH V2 2/2] arm64: dts: ti: Add support for J721E EAIK Date: Mon, 7 Jun 2021 15:03:14 +0530 Message-Id: <20210607093314.23909-3-sinthu.raja@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210607093314.23909-1-sinthu.raja@ti.com> References: <20210607093314.23909-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1623058487-305760-5428-522-1 X-BESS-VER: 2019.1_20210603.1645 X-BESS-Apparent-Source-IP: 209.85.210.199 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.232772 [from cloudscan15-76.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_MISMATCH_TO, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sinthu Raja J721E EdgeAI Kit (EAIK) is a low cost, small form factor board designed for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high performance vision accelerators, video codec accelerators, latest C71x and C66x DSP, high bandwidth real-time IPs for capture and display, GPU, dedicated safety island and security accelerators. The SoC is power optimized to provide best in class performance for perception, sensor fusion, localization, path planning tasks in robotics, industrial and automotive applications. J721E EAIK supports the following interfaces: * 4 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.0 Type-C port * x3 USB 3.0 Type-A ports * x1 UHS-1 capable µSD card slot * x1 PCIe M.2 E Key with x1 USB2.0, x1 MCASP, x1 MMC, x1 UART * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x4 UART through UART-USB bridge * x4 CAN-FD interface * x1 DP interface * x1 HDMI interface * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi compatible GPIO header * Compact TI 20-Pin connector for JTAG debug * Interface for remote automation. Includes: * power measurement and reset control * boot mode change Add basic support for J721E-EAIK. Signed-off-by: Amarnath MB Signed-off-by: Sinthu Raja --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-j721e-eaik.dts | 342 +++++++++++++++++++++++ 2 files changed, 344 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-eaik.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index d56c742f5a10..00eb2077616e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-eaik.dtb + dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j721e-eaik.dts b/arch/arm64/boot/dts/ti/k3-j721e-eaik.dts new file mode 100644 index 000000000000..decb16274333 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-eaik.dts @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721e.dtsi" +#include +#include +#include + +/ { + compatible = "ti,j721e-eaik", "ti,j721e"; + model = "Texas Instruments J721E EAIK"; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; + + vusb_main: fixedregulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible = "regulator-fixed"; + regulator-name = "vusb-main5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of LM5141 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: fixedregulator-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_mmc1_en_pins_default>; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: gpio-regulator-tps659411 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tps659411"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; +}; + +&main_pmx0 { + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ + J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ + J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ + J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ + >; + }; + + main_i2c3_pins_default: main-i2c3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ + J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ + >; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ + >; + }; + + vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ + >; + }; + + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by System firmware */ + status = "reserved"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +}; + +&main_uart2 { + /* Brought out on RPi header */ + status = "disabled"; +}; + +&main_uart3 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart5 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart6 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart7 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart8 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart9 { + /* Brought out on M.2 E Key */ + status = "disabled"; +}; + +&main_sdhci0 { + /* Unused */ + status = "disabled"; +}; + +&main_sdhci1 { + /* SD Card */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci2 { + /* Unused */ + status = "disabled"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + #address-cells = <1>; + #size-cells = <1>; + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + u-boot,dm-spl; + }; + }; +}; + +&ospi1 { + /* Unused */ + status = "disabled"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + i2c-switch@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + /* PCIe1 M.2 M Key I2C */ + pcie1_m2_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + /* PCIe0 M.2 E Key I2C */ + pcie0_m2_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; + + i2c-switch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + /* CAM0 I2C */ + ti_cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + /* CAM1 I2C */ + rpi_cam0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&main_i2c4 { + /* Unused */ + status = "disabled"; +}; + +&main_i2c5 { + /* Brought out on RPi Header */ + status = "disabled"; +}; + +&main_i2c6 { + /* Unused */ + status = "disabled"; +};