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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id m62-v6sm26390868oik.30.2018.07.23.13.21.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:30 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:16:16 -0500 Message-Id: <20180723201748.25573-8-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::232 Subject: [Qemu-devel] [PATCH 07/99] target/arm: Implement v8M VLLDM and VLSTM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell For v8M the instructions VLLDM and VLSTM support lazy saving and restoring of the secure floating-point registers. Even if the floating point extension is not implemented, these instructions must act as NOPs in Secure state, so they can be used as part of the secure-to-nonsecure call sequence. Fixes: https://bugs.launchpad.net/qemu/+bug/1768295 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180503105730.5958-1-peter.maydell@linaro.org (cherry picked from commit b1e5336a9899016c53d59eba53ebf6abcc21995c) Signed-off-by: Michael Roth --- target/arm/translate.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index db1ce6510a..64b9bf33af 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10783,8 +10783,23 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { /* We don't currently implement M profile FP support, - * so this entire space should give a NOCP fault. + * so this entire space should give a NOCP fault, with + * the exception of the v8M VLLDM and VLSTM insns, which + * must be NOPs in Secure state and UNDEF in Nonsecure state. */ + if (arm_dc_feature(s, ARM_FEATURE_V8) && + (insn & 0xffa00f00) == 0xec200a00) { + /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx + * - VLLDM, VLSTM + * We choose to UNDEF if the RAZ bits are non-zero. + */ + if (!s->v8m_secure || (insn & 0x0040f0ff)) { + goto illegal_op; + } + /* Just NOP since FP support is not implemented */ + break; + } + /* All other insns: NOCP */ gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), default_exception_el(s)); break; From patchwork Mon Jul 23 20:17:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142638 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6504153ljj; Mon, 23 Jul 2018 14:16:12 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf1xP/ABi+Qciff3HlVJIVaB3kYIEtMHTtimPbaBjnL7mYMLyDxOioQgiDLtt0Wg7kVNQ86 X-Received: by 2002:aed:3a24:: with SMTP id n33-v6mr14125429qte.348.1532380572273; Mon, 23 Jul 2018 14:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380572; cv=none; d=google.com; s=arc-20160816; b=Lm9V9BPyw/M33CoN+8d3IAhljNRme+biJHoLJBqoaAvTlE37bFA+LJFFkdI3L0d0s1 WanxqvM2ODHM2Vat3x6u9OxCYTDOpAhxubq+D4UetYxbN5SyV//a25Bv1U2ks27X6S6z wXwddujsOKdvgiUyo5ns7IRn3a9JGCsv8tiwsBbr9uJjYzk5eWHBTdHm/SyPj7rUKeR0 wRx0uIYTYe//6Sj79IKfQaSFqn3m8THIrBo0LG7BdCc9lgUtcBCvgBn/zUCqYPL94/cM O1sAY0tj8fSTzlaPiShsbvI/RG9REauEsgvl6iZBKKG1UfBkkrnNHY4AgaX7qdrmx+OJ 7FGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=OppfwWBPBz1GOM6QzTsx+TJsOuHI0ZxTseXqqx+wcA4=; b=RBJinVRQ4lNJ0+GH+iNZQUfxLODW4DQ5g3uDsaDM+GlbRrm1pwMttBp2G/BrHhomTB ifPQ9iM5o1tXP3eTW+HaQv7v8QsIsW6NxqYysvWd2+X87gLxVEj7QLlZcSBft0YVztXY uZbsq3QSNgo8baGyIltyBWps5go2CNflJLFXEvucQfRmnF7JT3wmDZQ5nVi8Z+Rz4YQ9 13btMic5BH/6AOc5qu7psvvum+k+ka2SfrLfXqNh3F62rjonIVPyrAuURRSi6LlYpBCt 3/2AMGcCmgHqUG254ICou9AAP+L128qE1q6dpXlbeVru7gZhoiccvRzd2OhGNHPJ9arg Ya/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ZQ2c32K5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id o65-v6sm7411173oia.35.2018.07.23.13.20.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:20:50 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:13 -0500 Message-Id: <20180723201748.25573-65-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::243 Subject: [Qemu-devel] [PATCH 64/99] tcg/i386: Fix dup_vec in non-AVX2 codepath X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The VPUNPCKLD* instructions are all "non-destructive source", indicated by "NDS" in the encoding string in the x86 ISA manual. This means that they take two source operands, one of which is encoded in the VEX.vvvv field. We were incorrectly treating them as if they were destructive-source and passing 0 as the 'v' argument of tcg_out_vex_modrm(). This meant we were always using %xmm0 as one of the source operands, causing incorrect results if the register allocator happened to want to use something else. For instance the input AArch64 insn: DUP v26.16b, w21 which becomes TCG IR ops: dup_vec v128,e8,tmp2,x21 st_vec v128,e8,tmp2,env,$0xa40 was assembled to: 0x607c568c: c4 c1 7a 7e 86 e8 00 00 vmovq 0xe8(%r14), %xmm0 0x607c5694: 00 0x607c5695: c5 f9 60 c8 vpunpcklbw %xmm0, %xmm0, %xmm1 0x607c5699: c5 f9 61 c9 vpunpcklwd %xmm1, %xmm0, %xmm1 0x607c569d: c5 f9 70 c9 00 vpshufd $0, %xmm1, %xmm1 0x607c56a2: c4 c1 7a 7f 8e 40 0a 00 vmovdqu %xmm1, 0xa40(%r14) 0x607c56aa: 00 when the vpunpcklwd insn should be "%xmm1, %xmm1, %xmm1". This resulted in our incorrectly setting the output vector to q26=0000320000003200:0000320000003200 when given an input of x21 == 0000000002803200 rather than the expected all-zeroes. Pass the correct source register number to tcg_out_vex_modrm() for these insns. Fixes: 770c2fc7bb70804a Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Message-Id: <20180504153431.5169-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson (cherry picked from commit 7eb30ef0ba2eb59e7430d4848ae8d4bf4e50f768) Signed-off-by: Michael Roth --- tcg/i386/tcg-target.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index d7e59e79c5..5357909fff 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -854,11 +854,11 @@ static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, switch (vece) { case MO_8: /* ??? With zero in a register, use PSHUFB. */ - tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, 0, a); + tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); a = r; /* FALLTHRU */ case MO_16: - tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, 0, a); + tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); a = r; /* FALLTHRU */ case MO_32: @@ -867,7 +867,7 @@ static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, tcg_out8(s, 0); break; case MO_64: - tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, 0, a); + tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); break; default: g_assert_not_reached(); From patchwork Mon Jul 23 20:17:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142640 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6504639ljj; Mon, 23 Jul 2018 14:16:43 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcMU/ZFR2ywbY80IeO0pamXiHB4kWVn/6LPeuL9eVHihpc2tiZtaC7f3fwJFF1uXKwqSPYr X-Received: by 2002:a0c:d1b7:: with SMTP id e52-v6mr12779911qvh.41.1532380603775; Mon, 23 Jul 2018 14:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380603; cv=none; d=google.com; s=arc-20160816; b=m5gqTNVWCvYJcyvLs3xomllOVJzMVdmEMrThYnHPdBBaznE7F1M3L0PkqAkYKCmO8C KYs9E4cMss06HEoQoVY1vzSUQFY/JJtz5sFinqYXh7OLjYo+vBccoz261sZjuSSkOGRG aJiMh6L6UH0paUZr43aApWCz+BkLptYJRRy5Ew7cazFM5nuJNyCIqkL9xg0TUNiCqoOW Chnn+TEK/DbcazGhQneh7BSnu7btJjZNt4ZTJTsuT/X0uXoQOyqvRNZkfkS03B7TyiRX /IkYLvEoNCRPbbdYbX+b8Ds0IEMehyruFUMJ5CwgHhtjuTTMpbiRgdAipRYfRVq2wB8s pkzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xmopYi/nNf6wdml7iVdwwr/MlVD9CKCWQdp5ypLE2TI=; b=dt9xvEMmzWTnxzvjmibTk+Gh+ndUxv48jj2VsfxAJ9HFI9VObHOqbtvChLfsMa2AYG oesWbOpM1awJH4FM7EG6zJV9TBQ/GPh8KqtaedIcPdaQJT0pO3m6YmUZIvR4gsnrLHlz 3Q2UhpyaXzEXJyNFPOlyZaDxHq0mkNBe6i1uS+r9D1D11qLp3P8mV+nHgoUILShW1rC7 QI7IZ0g4PLdASZDMy8dfSvqTzZMRy30AP0ZIM83AjXcJQ18EuGpGAXG3Gyn/U+h+Xifr PWVvPizZpQxb9LnMoBnBsaS88UCupOTs0WWMJHJOASTSP/RLb2RjIAq5cHmYalCMttv7 0XkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Oza78fsP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id s124-v6sm6811118oia.51.2018.07.23.13.20.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:20:52 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:14 -0500 Message-Id: <20180723201748.25573-66-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 65/99] softfloat: Handle default NaN mode after pickNaNMulAdd, not before X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell It is implementation defined whether a multiply-add of (0,inf,qnan) or (inf,0,qnan) raises InvalidaOperation or not, so we let the target-specific pickNaNMulAdd function handle this. This means that we must do the "return the default NaN in default NaN mode" check after the call, not before. Correct the ordering, and restore the comment from the old propagateFloat64MulAddNaN() that warned about this corner case. This fixes a regression from 2.11 for Arm guests where we would incorrectly fail to set the Invalid flag for these cases. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-id: 20180504100547.14621-1-peter.maydell@linaro.org (cherry picked from commit 1839189bbf89889076aadf0c793c1b57977b28d7) Signed-off-by: Michael Roth --- fpu/softfloat.c | 48 ++++++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 20 deletions(-) -- 2.17.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 70e0c40a1c..8401b37bd4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -602,34 +602,42 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, bool inf_zero, float_status *s) { + int which; + if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) { s->float_exception_flags |= float_flag_invalid; } + which = pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), + is_qnan(b.cls), is_snan(b.cls), + is_qnan(c.cls), is_snan(c.cls), + inf_zero, s); + if (s->default_nan_mode) { + /* Note that this check is after pickNaNMulAdd so that function + * has an opportunity to set the Invalid flag. + */ a.cls = float_class_dnan; - } else { - switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s)) { - case 0: - break; - case 1: - a = b; - break; - case 2: - a = c; - break; - case 3: - a.cls = float_class_dnan; - return a; - default: - g_assert_not_reached(); - } + return a; + } - a.cls = float_class_msnan; + switch (which) { + case 0: + break; + case 1: + a = b; + break; + case 2: + a = c; + break; + case 3: + a.cls = float_class_dnan; + return a; + default: + g_assert_not_reached(); } + a.cls = float_class_msnan; + return a; } From patchwork Mon Jul 23 20:17:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142637 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6500441ljj; Mon, 23 Jul 2018 14:11:59 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeoZwmEWMOGYpbFfYrmTAT0OC8DyMnhWfcjjwjeWQzLx7i/ugb93hwZRGcO27rpHmKPOjhC X-Received: by 2002:a37:f44:: with SMTP id z65-v6mr12827904qkg.93.1532380319536; Mon, 23 Jul 2018 14:11:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380319; cv=none; d=google.com; s=arc-20160816; b=tMKGIgmd1pXVhE6F7NDPlwZbp5wSH9eynF63uN8DO+GDI73xg+Suya+m58e5ASI6cf jWSdk+JI6GRMVeE+Ay7YUbAN+DJ5P0agiNE4hJoekiW/HGmEHsvhd+K2K7WSTgRS6Bmu Wfyzk6HPwk2SnuMcQhSc7mizfaCNnaXbmmNZBq67jmoKQdRl5OY/Rqi86paszPm8p+Fi 1JbE9T9rXVAIZnXrCHgeIlFURHgUQZhm7uRKCIFfghmHVFrwtMdcupSPgoaKwrZyCKdX iu1nFhyv/6DcsiCfipZUtfnoL1x20XHyo02u/rB4D+IF/BfWeFB9KyzapjkS1amwNlkj cs4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=R567CLjPuLcmj/VmBI4Kxetfln6noYhEtAG8G2ZZXUI=; b=jr15QycImkBp2B6tKa9JiTiQsAk5UnivQdEmcCWPP4iC7waMSC1H0bqG4II2J52HJN mvbNkIt3ZK4Jn7sCS6gP9Y4yeGIjJyFwNjJAo0cId37XyuNlsFWTqs4xsmDrPwXdHGSK qR5RWupcrAal25DDlhAI9HPVNppdBA3IKrZumo4HWniXBHPMA/qKGf3hdxXjjQHztXc6 MdKFP1FMTvlztdS4jkJwYMEyy8hCjXvqFPm0AANU841k1bovhBhWCJVlSXKBBZg/ewM1 R2j+cI1qV4LVWaR4gC4N5dUyI2DEhfuDaCpBI8JV/L85THdqqzx3qbeN57qfwVmoeRUr g4tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Q+X5h3MG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id m62-v6sm26388292oik.30.2018.07.23.13.20.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:20:54 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:15 -0500 Message-Id: <20180723201748.25573-67-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::242 Subject: [Qemu-devel] [PATCH 66/99] tcg: Limit the number of ops in a TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson In 6001f7729e12 we partially attempt to address the branch displacement overflow caused by 15fa08f845. However, gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqtbX.c is a testcase that contains a TB so large as to overflow anyway. The limit here of 8000 ops produces a maximum output TB size of 24112 bytes on a ppc64le host with that test case. This is still much less than the maximum forward branch distance of 32764 bytes. Cc: qemu-stable@nongnu.org Fixes: 15fa08f845 ("tcg: Dynamically allocate TCGOps") Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson (cherry picked from commit abebf92597186be2bc48d487235da28b1127860f) Signed-off-by: Michael Roth --- tcg/tcg.c | 3 +++ tcg/tcg.h | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index bb24526c93..66997cc653 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -866,6 +866,7 @@ void tcg_func_start(TCGContext *s) /* No temps have been previously allocated for size or locality. */ memset(s->free_temps, 0, sizeof(s->free_temps)); + s->nb_ops = 0; s->nb_labels = 0; s->current_frame_offset = s->frame_start; @@ -1983,6 +1984,7 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) { QTAILQ_REMOVE(&s->ops, op, link); QTAILQ_INSERT_TAIL(&s->free_ops, op, link); + s->nb_ops--; #ifdef CONFIG_PROFILER atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); @@ -2002,6 +2004,7 @@ static TCGOp *tcg_op_alloc(TCGOpcode opc) } memset(op, 0, offsetof(TCGOp, link)); op->opc = opc; + s->nb_ops++; return op; } diff --git a/tcg/tcg.h b/tcg/tcg.h index 30896ca304..17cf764565 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -655,6 +655,7 @@ struct TCGContext { int nb_globals; int nb_temps; int nb_indirects; + int nb_ops; /* goto_tb support */ tcg_insn_unit *code_buf; @@ -844,7 +845,12 @@ static inline TCGOp *tcg_last_op(void) /* Test for whether to terminate the TB for using too many opcodes. */ static inline bool tcg_op_buf_full(void) { - return false; + /* This is not a hard limit, it merely stops translation when + * we have produced "enough" opcodes. We want to limit TB size + * such that a RISC host can reasonably use a 16-bit signed + * branch within the TB. + */ + return tcg_ctx->nb_ops >= 8000; } /* pool based memory allocation */ From patchwork Mon Jul 23 20:17:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142641 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6505391ljj; Mon, 23 Jul 2018 14:17:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcVoBvRIkvONC9xf422qT5f/gT95EE0P4jnSpnzB5YWyNe8FNo/vBm9aOwvyQAzrT/o0Hyi X-Received: by 2002:a37:9f90:: with SMTP id i138-v6mr12798877qke.113.1532380657976; Mon, 23 Jul 2018 14:17:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380657; cv=none; d=google.com; s=arc-20160816; b=Ga8Ql9Pdp9xP8tJJyH6kABKt/R3PyXrLpdUIttKF07uso9Y0dogE9nnABATVnmeOFD AHGtCIpaOdscJBNUsKrQz8yZIURoJ9t6IZ2hxE4k+iHOsoyyNPlXlqvI2zlHtkl7YCNJ neAmSsKNmT7Ck8Hx/p3UJleArMMAfXMoc1lwU09w18eIao0ytIk0enw8bo8UMNYLPzu/ qHw34+th3aOawUpML9cA3TxYoCjt9L4UImM1lE1UMPfSbmTUb0Uk6srP7K7ZLNjRrNvj 0dCE34Ha4sV9tD/nXe17RsiLzIWt5UWymiOEfI9Y7MijJdQ8x4hL8pO9/EaTFjlupC5H LEnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oW1WcFafgHAkdjm0CsLyqQUr/F68AJFRJMt7rynJMsM=; b=fwhdYl1ZxivvmaKPceUai5Hsj5ZPlRZn6tsCGmUjSg8rmO3Y981h+QJXtsGG49uDZq ncX+xe0nC/i5T/WBj2kUol0QT1igWb7+Giv+IQbLEsVSBLH6I+jGgB//NiFUzCUoa76b zoaS00zbKSAHXTUHwVOULyVGw/K0+H0u8Gi+oqtefJNLEHyYH9hI0aDQOJU5GVCzYG+/ ygII5eCO6KM+iiRyqGrg6KYGI9WBJiE/waoK9AFGC2UV9b6jLja8WUuSPLWR3exRwoDI DSEgkmeBl+Sk2iyfKwMydPVLwZIU0QK+XlsD8t8eYYqDp5y6558uWrsatWkv5MEVYf0Y i2IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b="Pll/qB+l"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id u18-v6sm6621311oiv.10.2018.07.23.13.21.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:01 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:18 -0500 Message-Id: <20180723201748.25573-70-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::233 Subject: [Qemu-devel] [PATCH 69/99] target/arm: Fix fp_status_f16 tininess before rounding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In commit d81ce0ef2c4f105 we added an extra float_status field fp_status_fp16 for Arm, but forgot to initialize it correctly by setting it to float_tininess_before_rounding. This currently will only cause problems for the new V8_FP16 feature, since the float-to-float conversion code doesn't use it yet. The effect would be that we failed to set the Underflow IEEE exception flag in all the cases where we should. Add the missing initialization. Fixes: d81ce0ef2c4f105 Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Peter Maydell Message-id: 20180512004311.9299-16-richard.henderson@linaro.org (cherry picked from commit bcc531f0364796104df4443d17f99b5fb494eca2) Signed-off-by: Michael Roth --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 022d8c5787..7ebe3fcadf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -311,6 +311,8 @@ static void arm_cpu_reset(CPUState *s) &env->vfp.fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status); + set_float_detect_tininess(float_tininess_before_rounding, + &env->vfp.fp_status_f16); #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_arm_reset_vcpu(cpu); From patchwork Mon Jul 23 20:17:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142645 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6509638ljj; Mon, 23 Jul 2018 14:22:29 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcIsfxX4/3ijstpBdy4Qh3GOcG62Lpqf8aQkY5QUJjZni+8ptcqSGJuMRURiMOfdmzthzz6 X-Received: by 2002:a0c:e792:: with SMTP id x18-v6mr12819910qvn.3.1532380949622; Mon, 23 Jul 2018 14:22:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380949; cv=none; d=google.com; s=arc-20160816; b=X9Zc+dADH+xcAp8wjytk8RmkCHVoTLP4sk+bPRnwei+EpQMgDIJkk6PsZ0K3cb6tn8 cpZJJiFoz/LTJKhCVPM78ASNu4cmcTkSlLqekQ1z8vwiBMwWKJ+CyJNoZWV69EEAUZ3u Atr6b2uRLlM+6z5heLGHY4D5sn31O3bJf0pJz/quWS24vkt2mC1jXm3vZdo12Zt2ZWEs Ab2aR/3qSJcKKE+oJArZ5uUNHdGukr10YQz9osdlxv+kdK8PKfzFhMyxJmSvez+VsESf lBihhs5NATN7fCmPTAZqVlzC6eMQ4EIJx5KFRxOwUfRm/QI9GchjSG8eOy5MMt8ntBNY +liQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=79FhJ45C6ScQWoWPkygQVM7Ai2fm6uQPtNrO1Wa5grY=; b=syn0178kowaKwuj7LxG88zRs5/TPT2xUstFriuWFNjvO30FNnM9xLLaR2uxRlspQg8 Y/Hx8d9miGLUMrmN2rEeJyT1uPTYut0yLatURcI7X4o4pNXyQaMCoX4ugWkAQ98Ip0Ys 5cvfHl7fgp1WWv0PKMQ0uhO0azsgRVZmCfXacj+XvOeUn5vdHSNtYNUrelb00psIUj2H 2F/wzQ2ALN3aCzoiJwscJuQN+3aC2u79MbIPR5CE+GAL7QLwpTILtr7mQupREbcmSxmx 6HXWI0URUqK2aIKtnOSHkHiJuk5tP7DJYrQBAcdwnhi+qCd4V9wWOco+NskVEpklxAPx Mbdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b="ROoks/k7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id a8-v6sm7948945oia.24.2018.07.23.13.21.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:03 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:19 -0500 Message-Id: <20180723201748.25573-71-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 70/99] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In float-to-integer conversion, if the floating point input converts exactly to the largest or smallest integer that fits in to the result type, this is not an overflow. In this situation we were producing the correct result value, but were incorrectly setting the Invalid flag. For example for Arm A64, "FCVTAS w0, d0" on an input of 0x41dfffffffc00000 should produce 0x7fffffff and set no flags. Fix the boundary case to take the right half of the if() statements. This fixes a regression from 2.11 introduced by the softfloat refactoring. Cc: qemu-stable@nongnu.org Fixes: ab52f973a50 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180510140141.12120-1-peter.maydell@linaro.org (cherry picked from commit 333583757c5e910b040bef793974773635ce1918) Signed-off-by: Michael Roth --- fpu/softfloat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8401b37bd4..9bcaaebe4f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1368,14 +1368,14 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, r = UINT64_MAX; } if (p.sign) { - if (r < -(uint64_t) min) { + if (r <= -(uint64_t) min) { return -r; } else { s->float_exception_flags = orig_flags | float_flag_invalid; return min; } } else { - if (r < max) { + if (r <= max) { return r; } else { s->float_exception_flags = orig_flags | float_flag_invalid; From patchwork Mon Jul 23 20:17:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142649 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6511878ljj; Mon, 23 Jul 2018 14:25:37 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfd/RlDcv7SPououW8/BEEdPFNhvM31D6hPsaYfXhYpyZxh5oA24tmZzcPbv8tvyQCQ8sLY X-Received: by 2002:a0c:86f3:: with SMTP id 48-v6mr12714414qvg.165.1532381136954; Mon, 23 Jul 2018 14:25:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381136; cv=none; d=google.com; s=arc-20160816; b=FSK5tbAMQTY5jtvIL7zvefOqXPAzapg0B1IqMlwL06x/9eAYEVJx0UY9Gzabg5Km8E 1eVbRKoFWbE4tB5SHoARdtGTzG+iVdJaBdKi+SJGeibtZu0RxeF/TNUT+Wks6hGoo/QO uYgozllbjym16q4vA3Mk9GqBB5nT45YlhvvH44w/UPhncAUubNYhww50dZtxrH3LXvCD cZYDZBJb15QFELZQl1pP53vhWU3/qn+3/nCDJr91jJa4PF1P+wGcYv/G7GMlY7ZQO1rp /vKTXdFIWexcfiHQwPisXQq6Phai6u5yi3oMUYM5Xr+vP/6nG78REciH82OfzN+ll+fO zsKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eNFiUdYrtj6V8YdcdUftq0s+w+8iqj79jT1PgkeIBzw=; b=ogucCJ/EDBVacpY7PlzU7Vz6PB7s3ZF0FsQNTUkvmSZ+KX2jq9OK1fzuhhYGlK5pvf nk3GIrHen94y/9TDNmsq7fZ7b665jYRqpnTn73GxUqR/q/Zq8PpxGxTmjftdqT1FydfP /CMZmN7aHOuwybAv6sm1D/+tLkOKFwJOOZfA5dNpRqgdqscNxlcI9LCcjIllffy3NvXw uQ2LyphS/gP+XmkHwd4IPYq+laZwBOWW1wiZ7kia5EiHf20IQY5XIECac1Lqdpz21+5o qzknGJpebnVhSfdFGYy4TAnz2qpwpTPzNho7FmMkkjkFR3WwVQFMiXbmUfY4a4xcAtGj Qy9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=jPwfsqR2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id l204-v6sm6939364oia.45.2018.07.23.13.21.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:07 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:20 -0500 Message-Id: <20180723201748.25573-72-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::231 Subject: [Qemu-devel] [PATCH 71/99] target/arm: Implement vector shifted SCVF/UCVF for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson While we have some of the scalar paths for *CVF for fp16, we failed to decode the fp16 version of these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Message-id: 20180502221552.3873-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit a6117fae4576edfe7a5a5b802a742c33112c0993) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c91329249d..f0fa6045e4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7159,13 +7159,26 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, int immh, int immb, int opcode, int rn, int rd) { - bool is_double = extract32(immh, 3, 1); - int size = is_double ? MO_64 : MO_32; - int elements; + int size, elements, fracbits; int immhb = immh << 3 | immb; - int fracbits = (is_double ? 128 : 64) - immhb; - if (!extract32(immh, 2, 2)) { + if (immh & 8) { + size = MO_64; + if (!is_scalar && !is_q) { + unallocated_encoding(s); + return; + } + } else if (immh & 4) { + size = MO_32; + } else if (immh & 2) { + size = MO_16; + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + } else { + /* immh == 0 would be a failure of the decode logic */ + g_assert(immh == 1); unallocated_encoding(s); return; } @@ -7173,20 +7186,14 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, if (is_scalar) { elements = 1; } else { - elements = is_double ? 2 : is_q ? 4 : 2; - if (is_double && !is_q) { - unallocated_encoding(s); - return; - } + elements = (8 << is_q) >> size; } + fracbits = (16 << size) - immhb; if (!fp_access_check(s)) { return; } - /* immh == 0 would be a failure of the decode logic */ - g_assert(immh); - handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); } From patchwork Mon Jul 23 20:17:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142646 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6510889ljj; Mon, 23 Jul 2018 14:24:12 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcEgj3+ofJK1vdOlQoyTLbjl+eW5SrokVUUwNrow9/+tggx5ilyKWx+1sGcsPU0vc+aWutq X-Received: by 2002:ae9:dec4:: with SMTP id s187-v6mr12581968qkf.322.1532381052277; Mon, 23 Jul 2018 14:24:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381052; cv=none; d=google.com; s=arc-20160816; b=ghsWVzdL+4bddHIy2+ky2PL6hB9n+OTJjy5UQ2HBzQriYLmX73SPljPJoCWoJywwGj tTpivx+aHYHsmSir13sGyUsiHHZN6MQajvsVLCSuawnmGLdiO0M7uDd9XnkCU/jW+WaW VgxEdqgtueuPlxX+vQ5B4Sm18vTfqsIgAi0d24CfLhQn8PrMjXx4mC/iavx18MlQHlmO EjvH80f2rTviO7afOiMM/Vd86KcZPnhE8MlO9dFhOXcOca0rTDuudcwlvuoqAv9higyB cHWX986XmWPG94+7LSnvd+kzjfgTvDQivmwDCDblPz/rntfpSyv1BUq/a1QLa0In36d6 Antg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oQgVzzLW/AKZnSBdmcngVIFMbjpCsGBPKm5s95XcOIA=; b=rM3B5JTND5vM9NZ3FwuxW1xPnffZEFittdsVPTHBb9rAUKcm+azYJJ5oXjS9gFb1vi FlzJDZOsw/STNaYi8qM7+mqZTIyj8XHT+vWszwRdnFOYt90oeH9dh7McamR0gdgXSsNr YGUvGRrC8Xb6dApYI+pFJRw3cD8BWcQnLAMdBfygWCBE7wtPaTHggrlE10nfchVyLuN+ uMjk7TrRh29nk+EGYrPnps+zJLtzhI9jT+Zu18oWMLbCuoW1mXcWxKftyqrFVokFCiAC lsLHYyJNLYH3VBY+H22sGBjKP3tpyc+FEQj5aSBsk2lY6J2L5UO4VkMWdCfIYv8MUXHx TqWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Ip7x2sTS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id x126-v6sm5000488oig.15.2018.07.23.13.21.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:10 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:21 -0500 Message-Id: <20180723201748.25573-73-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22c Subject: [Qemu-devel] [PATCH 72/99] target/arm: Implement vector shifted FCVT for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson While we have some of the scalar paths for FCVT for fp16, we failed to decode the fp16 version of these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Message-id: 20180502221552.3873-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit d0ba8e74acd299b092786ffc30b306638d395a9e) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 63 +++++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f0fa6045e4..61735dc185 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7202,19 +7202,28 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, bool is_q, bool is_u, int immh, int immb, int rn, int rd) { - bool is_double = extract32(immh, 3, 1); int immhb = immh << 3 | immb; - int fracbits = (is_double ? 128 : 64) - immhb; - int pass; + int pass, size, fracbits; TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_rmode, tcg_shift; - if (!extract32(immh, 2, 2)) { - unallocated_encoding(s); - return; - } - - if (!is_scalar && !is_q && is_double) { + if (immh & 0x8) { + size = MO_64; + if (!is_scalar && !is_q) { + unallocated_encoding(s); + return; + } + } else if (immh & 0x4) { + size = MO_32; + } else if (immh & 0x2) { + size = MO_16; + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + } else { + /* Should have split out AdvSIMD modified immediate earlier. */ + assert(immh == 1); unallocated_encoding(s); return; } @@ -7226,11 +7235,12 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, assert(!(is_scalar && is_q)); tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - tcg_fpstatus = get_fpstatus_ptr(false); + tcg_fpstatus = get_fpstatus_ptr(size == MO_16); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + fracbits = (16 << size) - immhb; tcg_shift = tcg_const_i32(fracbits); - if (is_double) { + if (size == MO_64) { int maxpass = is_scalar ? 1 : 2; for (pass = 0; pass < maxpass; pass++) { @@ -7247,20 +7257,37 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, } clear_vec_high(s, is_q, rd); } else { - int maxpass = is_scalar ? 1 : is_q ? 4 : 2; - for (pass = 0; pass < maxpass; pass++) { - TCGv_i32 tcg_op = tcg_temp_new_i32(); + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); + int maxpass = is_scalar ? 1 : ((8 << is_q) >> size); - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + switch (size) { + case MO_16: + if (is_u) { + fn = gen_helper_vfp_toulh; + } else { + fn = gen_helper_vfp_toslh; + } + break; + case MO_32: if (is_u) { - gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); + fn = gen_helper_vfp_touls; } else { - gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); + fn = gen_helper_vfp_tosls; } + break; + default: + g_assert_not_reached(); + } + + for (pass = 0; pass < maxpass; pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, size); + fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); if (is_scalar) { write_fp_sreg(s, rd, tcg_op); } else { - write_vec_element_i32(s, tcg_op, rd, pass, MO_32); + write_vec_element_i32(s, tcg_op, rd, pass, size); } tcg_temp_free_i32(tcg_op); } From patchwork Mon Jul 23 20:17:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142658 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6514337ljj; Mon, 23 Jul 2018 14:28:49 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdpeOv9r/p9BJnDROCqEc7URgifdCQA3mZbl+VnF8YiMs0mS7K/5mObGRJ4QIX0xxwCkDKK X-Received: by 2002:a37:d61b:: with SMTP id t27-v6mr12611058qki.244.1532381329639; Mon, 23 Jul 2018 14:28:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381329; cv=none; d=google.com; s=arc-20160816; b=Tg5JV4IlrpOTcFX4QECbrwLtT4gVhLngU3RyVmCs2TpfVDSuPIdigH2tgOfZAr1kKi tPYG7xHwnqQzIQBAWncsuTj78OlnMrd2lZ57aolmBdoZxh3zu29CbNXN7IZyE65SdZmD 2ii3wbEY26kxeguy/yfp8Tjuae8hggd3jWf8UUCFVH35jUCXnwTLaQVtwTg2WuvRXGic sLXjFRLGG7t9+Ue7LM+lvIk9VZV8WWN6+HUMLQ2fVbeJUlLt2QE1W3X8xHx3L7LOfnnd 2dvey3nwXWvbK8YOU3WiacvKf8whTPUbwnSHgevCC/kPTyBznhqtHVdO4hqMsj6XPs5R yC2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=EAAvhRG8C54tuD9t5OWl5Oz5gtLAuNU9fBik2fQBfos=; b=pDxOGTvSppJiI9iEYMpYVau5bcjZkWSYiekEsj9yVHvdbccdij8NXxvQxT3UsNomJd kJq8HBzbGbcsT0725GHLXMJlNmOzitjzPlkhcnumA2j7zj++QBCA/q7pWytqfhN784FH u1vjukjZx44FOKBv1gSo/hNhT5Skl0EBLEmfntCMQDxiyD5ujcrj9XhFw/GlsJMsw0Xz FtnyR3rZmJd/IP5WtxmaWugSUVCtl49znOvCOiDygzyJGJm6MsvrWmFrXbVQzfBApbTA NEZ7dhJbmMmHX1kQE09k6tE1E0bcIrSXi4HT7Uo9TvackilQglOUuRJPxUFcIbsuzVa4 xvPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=i9QYhJA8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id t131-v6sm8734870oie.34.2018.07.23.13.21.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:12 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:22 -0500 Message-Id: <20180723201748.25573-74-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 73/99] target/arm: Fix float16 to/from int16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The instruction "ucvtf v0.4h, v04h, #2", with input 0x8000u, overflows the intermediate float16 to infinity before we have a chance to scale the output. Use float64 as the intermediate type so that no input argument (uint32_t in this case) can overflow or round before scaling. Given the declared argument, the signed int32_t function has the same problem. When converting from float16 to integer, using u/int32_t instead of u/int16_t means that the bounding is incorrect. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20180502221552.3873-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 88808a022c06f98d81cd3f2d105a5734c5614839) Signed-off-by: Michael Roth --- target/arm/helper.c | 53 ++++++++++++++++++++++++++++++++++++-- target/arm/helper.h | 4 +-- target/arm/translate-a64.c | 4 +-- 3 files changed, 55 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index b14fdab140..c07c1d7f48 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11409,11 +11409,60 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64) VFP_CONV_FIX(uh, s, 32, 32, uint16) VFP_CONV_FIX(ul, s, 32, 32, uint32) VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) -VFP_CONV_FIX_A64(sl, h, 16, 32, int32) -VFP_CONV_FIX_A64(ul, h, 16, 32, uint32) + #undef VFP_CONV_FIX #undef VFP_CONV_FIX_FLOAT #undef VFP_CONV_FLOAT_FIX_ROUND +#undef VFP_CONV_FIX_A64 + +/* Conversion to/from f16 can overflow to infinity before/after scaling. + * Therefore we convert to f64 (which does not round), scale, + * and then convert f64 to f16 (which may round). + */ + +static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst) +{ + return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst); +} + +float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst); +} + +float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst); +} + +static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst) +{ + if (unlikely(float16_is_any_nan(f))) { + float_raise(float_flag_invalid, fpst); + return 0; + } else { + int old_exc_flags = get_float_exception_flags(fpst); + float64 ret; + + ret = float16_to_float64(f, true, fpst); + ret = float64_scalbn(ret, shift, fpst); + old_exc_flags |= get_float_exception_flags(fpst) + & float_flag_input_denormal; + set_float_exception_flags(old_exc_flags, fpst); + + return ret; + } +} + +uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst); +} /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. diff --git a/target/arm/helper.h b/target/arm/helper.h index 34e8cc8904..1969b37f2d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -149,8 +149,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 61735dc185..3c4c9b9fdc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7263,9 +7263,9 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, switch (size) { case MO_16: if (is_u) { - fn = gen_helper_vfp_toulh; + fn = gen_helper_vfp_touhh; } else { - fn = gen_helper_vfp_toslh; + fn = gen_helper_vfp_toshh; } break; case MO_32: From patchwork Mon Jul 23 20:17:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142642 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6505964ljj; Mon, 23 Jul 2018 14:18:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfm9XuGX5tZnpRtICKeN4v3c/Us8JkCMZaI+AsFzNP1VXDr4WpMYSQ3p/z7E+W5UO0MIg69 X-Received: by 2002:aed:36a9:: with SMTP id f38-v6mr14285980qtb.64.1532380703169; Mon, 23 Jul 2018 14:18:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380703; cv=none; d=google.com; s=arc-20160816; b=h7bqeRl/Qllf32RK89VhHyiiVwcd7ZUHy/JFjAs2OPQuVyyFKnwa8tkLjUlfygyzuW NiCYmGBmP2221KVYyl//gmDYYhieAP967n6xWqiHF5C74zR63uCofMyw8Omfjr0kyJGb zJGLw2zFH1fdV951jQDuqrhKFcTbFKU7VoJk1JwUZPM8ahh1qvxwiJFqxIDXXQLuulrb fP73TVh4HVPvknB6Oq1s+nEpE5BcRwVSkWjXrEq/PNZSedvA7AnV9ELUIvH8HXOhc55Q BQykFyB7kK/GeZ8HYLl4V8GxLmr51ucJBb0t3XgcSYh/zTmZhKoOefvigT8o8aDIcu2m 1CTw== ARC-Message-Signature: i=1; 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id o206-v6sm8223354oif.7.2018.07.23.13.21.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:14 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:23 -0500 Message-Id: <20180723201748.25573-75-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::229 Subject: [Qemu-devel] [PATCH 74/99] target/arm: Clear SVE high bits for FMOV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use write_fp_dreg and clear_vec_high to zero the bits that need zeroing for these cases. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20180502221552.3873-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 9a9f1f59521f46e8ff4527d9a2b52f83577e2aa3) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3c4c9b9fdc..639cd95772 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5438,31 +5438,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) if (itof) { TCGv_i64 tcg_rn = cpu_reg(s, rn); + TCGv_i64 tmp; switch (type) { case 0: - { /* 32 bit */ - TCGv_i64 tmp = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, tcg_rn); - tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64)); - tcg_gen_movi_i64(tmp, 0); - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); + write_fp_dreg(s, rd, tmp); tcg_temp_free_i64(tmp); break; - } case 1: - { /* 64 bit */ - TCGv_i64 tmp = tcg_const_i64(0); - tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64)); - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); - tcg_temp_free_i64(tmp); + write_fp_dreg(s, rd, tcg_rn); break; - } case 2: /* 64 bit to top half. */ tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); + clear_vec_high(s, true, rd); break; } } else { From patchwork Mon Jul 23 20:17:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142660 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6516875ljj; Mon, 23 Jul 2018 14:31:46 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfpWeqUmd1xMw+kjjt37srt5IiFSAvsHnIi9Aray3NVomBgA61FByWMFkI2PdncRsuq2X/M X-Received: by 2002:a0c:96eb:: with SMTP id b40-v6mr12957702qvd.235.1532381506097; Mon, 23 Jul 2018 14:31:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381506; cv=none; d=google.com; s=arc-20160816; b=sxX4QEVpoBpXwr5Rpz3rzyCsUw+iapnUf85NmTlkfiCstdy6bLte7hCn2qDMbki5ye RiQ5Shd3DVr6NhMHCUMIT8sRBYQUsz1Wpq2OIZZbGNdNC4cvc3z46aKkeNSU9BFBjSLu a4n4oIhjjVMGMkxKnbCl9YyvJS9M2VTvJ41kpiS78Afjxk7YQqMWd1Fb2gJStNdMmydi H6yzMK1Dlm+07gm+HadR9vXtPqM4fxbyQHxBo6xZtBPI7ADl3A6aNn0dAiiCSEJvbMyD ttXu7JXXZrMV9H5z9JeFxkwl3KQFYevgJVCS9MWOiLjHCaQaFUZVw4OFnr61DyTJyQH7 vScA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Fl9uEjw1xc2dKDewX9QPdz6gea0SzgkVpH8oMMWOvRQ=; b=WcA4vQrSXqOxsFp8HjhAkMR4WtXXaGxZags/im08V/ZWdMMlchY2+WgCqUrjLEbf+v w2OKAjlKrKJ1JCinwrycmnq7C3JfxrGgUZakEdxiJNYkVCqFGjZ7SPlOjKsKUI9ya28L GHRjEbbJFpqaJzc3MQ1BFOF8qeCfeYsGMQg/aH9YwCP1QVOq/IOuA2eUhKIkZVVXOdlV LVq+ZRugRr53V042+afjRlKBUgfVMX/5hxg+rckQLpye7DIhxlhIZYMynJYtA2IkDCOW O8bgC5KlPGr1/2axgxjKSmEhAhyZRm7RqzN9SBULs4E37AIzsPrTbaB2ZBnNg2jdWGPZ fhDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=I28VJK9k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id v5-v6sm1203124oix.36.2018.07.23.13.21.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:19 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:25 -0500 Message-Id: <20180723201748.25573-77-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::230 Subject: [Qemu-devel] [PATCH 76/99] target/arm: Implement FMOV (general) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit 68130236e30a1ec64363f4915349feee181bfbc1) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 639cd95772..b05f9bfe91 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5457,6 +5457,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); clear_vec_high(s, true, rd); break; + case 3: + /* 16 bit */ + tmp = tcg_temp_new_i64(); + tcg_gen_ext16u_i64(tmp, tcg_rn); + write_fp_dreg(s, rd, tmp); + tcg_temp_free_i64(tmp); + break; + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_rd = cpu_reg(s, rd); @@ -5474,6 +5483,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) /* 64 bits from top half */ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); break; + case 3: + /* 16 bit */ + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); + break; + default: + g_assert_not_reached(); } } } @@ -5513,6 +5528,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) case 0xa: /* 64 bit */ case 0xd: /* 64 bit to top half of quad */ break; + case 0x6: /* 16-bit float, 32-bit int */ + case 0xe: /* 16-bit float, 64-bit int */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ default: /* all other sf/type/rmode combinations are invalid */ unallocated_encoding(s); From patchwork Mon Jul 23 20:17:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142659 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6515840ljj; Mon, 23 Jul 2018 14:30:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd4j1YXIjvCJ9ECmK2h6fzqVqHkk1BNZVWjuDtAJggCQLx3mii9Lkh+O2+ES1mByw/YQX8F X-Received: by 2002:a37:d401:: with SMTP id l1-v6mr12675029qki.221.1532381434518; Mon, 23 Jul 2018 14:30:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381434; cv=none; d=google.com; s=arc-20160816; b=rMO+HEHZVcEhwPMzJ9ibLviRSwEPo/zlWMknW4/Rsq5pd7RGYvtflU3HYjUCQBvJLW iZLRoJ59XzgncorafF7FrVXlTbMRqcLeW+ANPGOk1HElsmHAl04R1Z99jUOeIchxCbl5 umi2SuG/QkShR2CgySB7nzeI60JxZwajU+mkYaXynFKLDwDWTOpiOK63iHlOZpsxHTrI 0Xt691AJEzwVsQ9LJ+fTv3tBmENXfj84OLU+iHEhoQZg5TDYfgSi2P6S1v3tr0geLQXq X23/1n8AohQwsq9ILxOyE1383fsMpelhdMBIsRvWRHfT0wje+WXsCLSn4VHT4g7j3/4p 7p1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=FdarBSs+mctGDElKHbhV5ZEMxApRQE8DJ91JheNMCxs=; b=y9P/8EEJ4qieIg7NoATtNsiUg29ITHJdRoXheD1CStZ59Neily+scA5eOiIA+ZxmTn C3nFS39eDfKkSpGz6d5RLsmwdnDiWxUNuP9JKWzngNCEQYiQW9ziZIhO8i+m03YJpkrV R4I8I8x1bDu8zz/jkYVuJJ06kIdhE03xWJmKF6C72PMnG6/UKpIUW9BI/onyBvxcjRX4 ejcDcC6I6qkr3GFQe+0CK63pvFqAWCaf0a4dJtbcdGoBoBT7s4JrWQGXnexTGYW7WCQk UMbE+mSJArmk1eIk54nAl6KmT61ngU9yUUh3gKczyyrRUkOrOFUFjFUgNEYqs1JCi+yc FM4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=jeRJCdyv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id e125-v6sm9839232oig.4.2018.07.23.13.21.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:21 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:26 -0500 Message-Id: <20180723201748.25573-78-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 77/99] target/arm: Implement FCVT (scalar, integer) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 564a0632504fad840491aa9a59453f4e64a316c4) Signed-off-by: Michael Roth --- target/arm/helper.c | 38 ++++++++++++++- target/arm/helper.h | 6 +++ target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++------- 3 files changed, 122 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index c07c1d7f48..1043d6ed32 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11416,8 +11416,12 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) #undef VFP_CONV_FIX_A64 /* Conversion to/from f16 can overflow to infinity before/after scaling. - * Therefore we convert to f64 (which does not round), scale, - * and then convert f64 to f16 (which may round). + * Therefore we convert to f64, scale, and then convert f64 to f16; or + * vice versa for conversion to integer. + * + * For 16- and 32-bit integers, the conversion to f64 never rounds. + * For 64-bit integers, any integer that would cause rounding will also + * overflow to f16 infinity, so there is no double rounding problem. */ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst) @@ -11435,6 +11439,16 @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst); } +float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst); +} + +float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst); +} + static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst) { if (unlikely(float16_is_any_nan(f))) { @@ -11464,6 +11478,26 @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst) return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst); } +uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst); +} + /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 1969b37f2d..ce89968b2d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -151,6 +151,10 @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) @@ -177,6 +181,8 @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b05f9bfe91..33be611bdb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5268,11 +5268,11 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, bool itof, int rmode, int scale, int sf, int type) { bool is_signed = !(opcode & 1); - bool is_double = type; TCGv_ptr tcg_fpstatus; - TCGv_i32 tcg_shift; + TCGv_i32 tcg_shift, tcg_single; + TCGv_i64 tcg_double; - tcg_fpstatus = get_fpstatus_ptr(false); + tcg_fpstatus = get_fpstatus_ptr(type == 3); tcg_shift = tcg_const_i32(64 - scale); @@ -5290,8 +5290,9 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_int = tcg_extend; } - if (is_double) { - TCGv_i64 tcg_double = tcg_temp_new_i64(); + switch (type) { + case 1: /* float64 */ + tcg_double = tcg_temp_new_i64(); if (is_signed) { gen_helper_vfp_sqtod(tcg_double, tcg_int, tcg_shift, tcg_fpstatus); @@ -5301,8 +5302,10 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, } write_fp_dreg(s, rd, tcg_double); tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single = tcg_temp_new_i32(); + break; + + case 0: /* float32 */ + tcg_single = tcg_temp_new_i32(); if (is_signed) { gen_helper_vfp_sqtos(tcg_single, tcg_int, tcg_shift, tcg_fpstatus); @@ -5312,6 +5315,23 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, } write_fp_sreg(s, rd, tcg_single); tcg_temp_free_i32(tcg_single); + break; + + case 3: /* float16 */ + tcg_single = tcg_temp_new_i32(); + if (is_signed) { + gen_helper_vfp_sqtoh(tcg_single, tcg_int, + tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_uqtoh(tcg_single, tcg_int, + tcg_shift, tcg_fpstatus); + } + write_fp_sreg(s, rd, tcg_single); + tcg_temp_free_i32(tcg_single); + break; + + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_int = cpu_reg(s, rd); @@ -5328,8 +5348,9 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - if (is_double) { - TCGv_i64 tcg_double = read_fp_dreg(s, rn); + switch (type) { + case 1: /* float64 */ + tcg_double = read_fp_dreg(s, rn); if (is_signed) { if (!sf) { gen_helper_vfp_tosld(tcg_int, tcg_double, @@ -5347,9 +5368,14 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_shift, tcg_fpstatus); } } + if (!sf) { + tcg_gen_ext32u_i64(tcg_int, tcg_int); + } tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single = read_fp_sreg(s, rn); + break; + + case 0: /* float32 */ + tcg_single = read_fp_sreg(s, rn); if (sf) { if (is_signed) { gen_helper_vfp_tosqs(tcg_int, tcg_single, @@ -5371,14 +5397,39 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_temp_free_i32(tcg_dest); } tcg_temp_free_i32(tcg_single); + break; + + case 3: /* float16 */ + tcg_single = read_fp_sreg(s, rn); + if (sf) { + if (is_signed) { + gen_helper_vfp_tosqh(tcg_int, tcg_single, + tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_touqh(tcg_int, tcg_single, + tcg_shift, tcg_fpstatus); + } + } else { + TCGv_i32 tcg_dest = tcg_temp_new_i32(); + if (is_signed) { + gen_helper_vfp_toslh(tcg_dest, tcg_single, + tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_toulh(tcg_dest, tcg_single, + tcg_shift, tcg_fpstatus); + } + tcg_gen_extu_i32_i64(tcg_int, tcg_dest); + tcg_temp_free_i32(tcg_dest); + } + tcg_temp_free_i32(tcg_single); + break; + + default: + g_assert_not_reached(); } gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); - - if (!sf) { - tcg_gen_ext32u_i64(tcg_int, tcg_int); - } } tcg_temp_free_ptr(tcg_fpstatus); @@ -5548,7 +5599,20 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) /* actual FP conversions */ bool itof = extract32(opcode, 1, 1); - if (type > 1 || (rmode != 0 && opcode > 1)) { + if (rmode != 0 && opcode > 1) { + unallocated_encoding(s); + return; + } + switch (type) { + case 0: /* float32 */ + case 1: /* float64 */ + break; + case 3: /* float16 */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } From patchwork Mon Jul 23 20:17:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142643 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6508464ljj; Mon, 23 Jul 2018 14:21:15 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfEVz+0Uly54P+nSfOpzdLq9rUhYbfv6uKf5cn/cNw3R0v4AXIv+iikhufF/29BmHYpesfF X-Received: by 2002:a0c:aac9:: with SMTP id g9-v6mr12637225qvb.78.1532380874924; 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id r133-v6sm7511499oia.33.2018.07.23.13.21.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:23 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:27 -0500 Message-Id: <20180723201748.25573-79-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22c Subject: [Qemu-devel] [PATCH 78/99] target/arm: Implement FCVT (scalar, fixed-point) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 2752728016bef06e7c9cfb961019272859beeca4) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 33be611bdb..c5be901b5f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5454,8 +5454,21 @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) bool sf = extract32(insn, 31, 1); bool itof; - if (sbit || (type > 1) - || (!sf && scale < 32)) { + if (sbit || (!sf && scale < 32)) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: /* float32 */ + case 1: /* float64 */ + break; + case 3: /* float16 */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } From patchwork Mon Jul 23 20:17:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142639 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6504504ljj; Mon, 23 Jul 2018 14:16:37 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdY0C3/yPFjwYxU+G9LZzWXmn3kzsjip3eo4QLEbuUnpHoUhwD5HCqKVPUboEnIEjxCBF8D X-Received: by 2002:a37:61cd:: with SMTP id v196-v6mr13451780qkb.101.1532380597314; Mon, 23 Jul 2018 14:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532380597; cv=none; d=google.com; s=arc-20160816; b=iMUxtPiquMKV40F8bMiRogSZdo3nw/ibG5B2R5znWUxv2xs8Uc9n+Tg2RxAoOptGQt BzX4wojEANhLFNuI0kF6GLc9ZSY55csuHyJDTvT/bKG+tqZn6GgqP5ss8gR4hW7+vcKa pWdTbIa2yUTjhj+nTra0bVFbHtDGErzdBniUAT9Nq9NLebSyWmuL3yBJoWrOW+viQ8FM Jxh8wsDrOnPP1xWdEKCiC0oS+eo2Udzz23AGx7PLgbUu3NTIP8PZm4kXpwzjV2L1+5VI v8RFNoWQWyMezQUqf207GDLuupoqHJDK8ZN99FunOi7Yu/GeFBTyJpokyJcp437B+D2k V63Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ZheyVE/pjPhu9F8cg6sWew5iy2ewnczU/RjVypp3QrE=; b=qUkI1yfUlhivPpf/kOQ9CF+0J4jmj0vD1qdTqaylt+h5W7k70OtHwVma861iaex/lF xd0V7vZXvAZRa7aZMGeckSO15Fl5fqA2EG+drajuT7AVkK5fl97PCh0TM+eT5VEl1Hq+ 7QnOy3KStjnDwKIhNq5UontB28FDBxI6bmKRP6RLgNOP52S90nm1IegJjkGkQVyERcLY XARcbULPtiNWaYotiTHt5GfaUjyM5xZn3EyBv/UdtScT465UfpMagLLHPgokuOWZ8QDu Lk/JiQnR3XWTMImRhift8AaAbD4Bq8fPulgEN/7TDVlFgforF62wCr6UkdvrMUU6L8wq CahQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=pwkq1aac; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id w204-v6sm12600096oif.2.2018.07.23.13.21.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:25 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:28 -0500 Message-Id: <20180723201748.25573-80-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 3d99d931266eaeaf7e83703a53f32232cd6faad7) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c5be901b5f..bcb3b5c5e7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -614,6 +614,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) +{ + TCGv_i32 v = tcg_temp_new_i32(); + + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + return v; +} + /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). * If SVE is not enabled, then there are only 128 bits in the vector. */ @@ -4638,11 +4646,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) { TCGv_ptr fpst = NULL; - TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_op = read_fp_hreg(s, rn); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (opcode) { case 0x0: /* FMOV */ tcg_gen_mov_i32(tcg_res, tcg_op); @@ -7538,13 +7544,10 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_op2); tcg_temp_free_i64(tcg_res); } else { - TCGv_i32 tcg_op1 = tcg_temp_new_i32(); - TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); + TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); TCGv_i64 tcg_res = tcg_temp_new_i64(); - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); @@ -8085,13 +8088,10 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, fpst = get_fpstatus_ptr(true); - tcg_op1 = tcg_temp_new_i32(); - tcg_op2 = tcg_temp_new_i32(); + tcg_op1 = read_fp_hreg(s, rn); + tcg_op2 = read_fp_hreg(s, rm); tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - switch (fpopcode) { case 0x03: /* FMULX */ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); @@ -12010,11 +12010,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) } if (is_scalar) { - TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_op = read_fp_hreg(s, rn); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (fpop) { case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ From patchwork Mon Jul 23 20:17:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142661 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6520112ljj; Mon, 23 Jul 2018 14:35:45 -0700 (PDT) X-Google-Smtp-Source: AAOMgpetdA/am3s2br0eclLhUp8wFlfbA4pqjhpEbxjuTQVt/6UvbF/7JP3nUsROSPwrnjPkRPW9 X-Received: by 2002:ac8:1738:: with SMTP id w53-v6mr14078909qtj.421.1532381745702; Mon, 23 Jul 2018 14:35:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381745; cv=none; d=google.com; s=arc-20160816; b=Xnq7GbDHxiGCTy/XzYknOfCiJiY6PTg6ctBm1aTTdIS+eGA/UXjkDCpcFfeuBcHjNQ FuZ8Qp3UTC4C68aIxg4A9BzRDOWD25w3qp6mcu4VkfiXdG/EK3W1mF23d8kD9304JkJ6 X4idfH6R63deX6gyrCK/WfVey2wSBf+ifX+UwWk43GnsjUTtv1hVxiCjGUp5ewpprHCL kmyVXT4I4VctDdjoyZV794fnhFlUEXWR9x4Tla6dPM1IgiTrsKbeTzTJ0M4LN6NT+etD DkD/iQRCS/eY9y1y+REV4Mo/ycUA15OW9gwfapsaDXAnTR/zpAoVOSg/HhuEEzVzCVk3 HQkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6hjUj8XyV2DypjsCvz3iBwG01puPwJvqRnMj7VRoXbI=; b=ozqO6Rf9Me3oeqsf3EuRIlycUVj6QkbNu0G0nc0AMK1RqB4mPY1ji/1nBU1sTFxaqT 6+Jm/1L6A2MI55fnnH8caZie6M+CMN/4UfXwyCUx6cS0wG31mHgIE6dTEuROlBAJ30pn jo+m0SXTAymTMXvc/PRAeDQx379I22+K7mDJifGKZeyc+ot/lgtI4zeZ58NJf+ymx9+q mdl4Iu93Ypq6Nu/F/17ovYSgGJUsKv2O271CP5cSVvHpP33HtsTUCEMAgI6Prto0goRN VbwVIoE1PJ+60iPycQ5VWUGUfR3p/mS0wiSs6BQCx7w5+/P38htYW5TLebUvYinXnBpL 7d0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=S430aq4Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id q124-v6sm7914349oif.8.2018.07.23.13.21.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:28 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:29 -0500 Message-Id: <20180723201748.25573-81-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 80/99] target/arm: Implement FP data-processing (2 source) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We missed all of the scalar fp16 binary operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit b8f5171cf01420a9f0ee895c5591e9b9914f391a) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bcb3b5c5e7..5260849f03 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5056,6 +5056,61 @@ static void handle_fp_2src_double(DisasContext *s, int opcode, tcg_temp_free_i64(tcg_res); } +/* Floating-point data-processing (2 source) - half precision */ +static void handle_fp_2src_half(DisasContext *s, int opcode, + int rd, int rn, int rm) +{ + TCGv_i32 tcg_op1; + TCGv_i32 tcg_op2; + TCGv_i32 tcg_res; + TCGv_ptr fpst; + + tcg_res = tcg_temp_new_i32(); + fpst = get_fpstatus_ptr(true); + tcg_op1 = read_fp_hreg(s, rn); + tcg_op2 = read_fp_hreg(s, rm); + + switch (opcode) { + case 0x0: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x3: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x4: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x5: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x7: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FNMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); + break; + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_res); +} + /* Floating point data-processing (2 source) * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -5088,6 +5143,16 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn) } handle_fp_2src_double(s, opcode, rd, rn, rm); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + handle_fp_2src_half(s, opcode, rd, rn, rm); + break; default: unallocated_encoding(s); } From patchwork Mon Jul 23 20:17:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142662 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6520920ljj; Mon, 23 Jul 2018 14:36:51 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeny4vroclIjuC1De5mTDThq7QjcpmZ/UeJe+bB4d71AehwIMJB3+7VpyzdwOjpfWwi2u3y X-Received: by 2002:a0c:ba0f:: with SMTP id w15-v6mr12806549qvf.9.1532381810937; Mon, 23 Jul 2018 14:36:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381810; cv=none; d=google.com; s=arc-20160816; b=ompS8moZ2duQDhQhgLqY/NdcrvfOfzJ7xWLGDmAINnNv1fLbEk1Rc7PVLhWlRpLtf1 B2ZZ+vds7ctabGsZnLqfzGjLJx0R34vXXbP3OvVLBSVJUMyAIEucXIjLN8BMPY6ynSWN PCePECJZV8DEAWT7ZGBfoBkK887bemNGYdsHV//ZsayBT6V+VDMAWsvU/Z4YH+v42dUA I1CVx/Sg5Kp+CdqIkpaZkvFQ5HGGo1evURJQaFUS9yx9ZHxJDkcGRza2urjefD/7+zR5 P8XEdCnOeG6viNeSJ/XPb0VQp+8CYi3eOG8yZ8DArzyL4XNK9iJh1ABKvXVU2/NCjJ20 s92A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=GU6mHHNnptLNGjZsRkDztjlgUH/p7DOB0aYBTtKmDOg=; b=DrKIr+8JabIqouDBQvBDYe1LkUDejlmSuGwhJlH5O1F57wGwmwOXa5yoJDwKNMSb4v VhhAGR32bZNNcRm9u1XcXxnJe+qwHvrpbFflHjX9JrLjVcBz4VLc5pt2gu5Y/JrHQUPP IPkStT3CR5UUPfyDPVV2OlebDRXSPIPbnWMLia/AVE5ZXUujzTn6JPSxHbuH4fPEPlMA QRk3TESWVa/mjUTOXU2lPJS1mXHpQJJNr/G4fmBXWPNWfkhkTs49RDnO+dpvBxXJSW95 Y+QEEA2tCfBCt+ijLdZknSOP2PbRpJeFAQNdku94bSE33qZir85NIOBDIv3UNTGbWDJl FIsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=d3Xi68jk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id i204-v6sm19824135oia.41.2018.07.23.13.21.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:32 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:30 -0500 Message-Id: <20180723201748.25573-82-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22c Subject: [Qemu-devel] [PATCH 81/99] target/arm: Implement FP data-processing (3 source) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We missed all of the scalar fp16 fma operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 95f9864fde6078e2d2c036a07cc4fe44f199be96) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5260849f03..9880a5d047 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5234,6 +5234,44 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, tcg_temp_free_i64(tcg_res); } +/* Floating-point data-processing (3 source) - half precision */ +static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, + int rd, int rn, int rm, int ra) +{ + TCGv_i32 tcg_op1, tcg_op2, tcg_op3; + TCGv_i32 tcg_res = tcg_temp_new_i32(); + TCGv_ptr fpst = get_fpstatus_ptr(true); + + tcg_op1 = read_fp_hreg(s, rn); + tcg_op2 = read_fp_hreg(s, rm); + tcg_op3 = read_fp_hreg(s, ra); + + /* These are fused multiply-add, and must be done as one + * floating point operation with no rounding between the + * multiplication and addition steps. + * NB that doing the negations here as separate steps is + * correct : an input NaN should come out with its sign bit + * flipped if it is a negated-input. + */ + if (o1 == true) { + tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); + } + + if (o0 != o1) { + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); + } + + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); + + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_op3); + tcg_temp_free_i32(tcg_res); +} + /* Floating point data-processing (3 source) * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 * +---+---+---+-----------+------+----+------+----+------+------+------+ @@ -5263,6 +5301,16 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) } handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); + break; default: unallocated_encoding(s); } From patchwork Mon Jul 23 20:17:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142650 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6511889ljj; Mon, 23 Jul 2018 14:25:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcxkeSQQg3KTzatM1MuFlxR0qaJCrXcXV16Yyh+Utvo3Y8AVWKNQ+IOnlOkberv/Ip8uZOl X-Received: by 2002:a37:d197:: with SMTP id o23-v6mr13178184qkl.210.1532381138019; Mon, 23 Jul 2018 14:25:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381138; cv=none; d=google.com; s=arc-20160816; b=IuNVUTs7szsg/j5reXQ26fG1gY8GHVS3l4cop+9TYKGGQA8jdni/D6FUso350QlU1G ICIU2AjSwmf0U62PcyyOPAkglU0IA4/vQ8Aongnjwtbk2N+B0ndNViM7npMuinot/ze9 rqd2MQFwkfM91KL7cQGmRrYKv4YM6oQ2KJcdzurKegGdWiGtmGSoPo2jvKYVCgnUDbb2 jmHLcf+bZzZcX8amUThZalvstUcoST5iJsdxXOsENDoMzmqIDzjsZ5/TfXbgs6k4CqiD r01mi4ZUqIi8YR/iMN85HHp9GseoRXjuiNRQouWfSzT2Sqnb3sR6N2l48aZApemy0rth NwqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=WSnvSXMbdx8hUZexpfJ0bUF04M4al43hgNTbrqASRV8=; b=KK4KbsKd/OqsWMH/bNoyQ5ERLisYZKKfNBXBa/mLyTraQZ/1p+B0aWUsnw2/x1Tjit +uTFxsTV7+bz29RJ+yH/U+FbLkPtv+l/9kSCxKdJiFkuQBmRwwVBdWC2Z6KWuhcI5f2t Z0gshYuK3Jz7wfAJ51ZvwGnEaRR514xDu1OVGeIWew/LkO4KT1hTw2R1XOMFtMqZ/HSa 2PFuJGr8LS+bxWT5iTFze0eKcl15meA1E0D0/4zlV76iUvCmrVfznxF1Or2qUks/EgJg q5EfVjt1rq6Qlm2judsk0tLOpmLXCJrDjY28K+dsiacDNv7Z7jhX9PqW4kvrDGZOL9sI qeTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=VYxrYdxc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id v202-v6sm9033537oie.47.2018.07.23.13.21.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:35 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:31 -0500 Message-Id: <20180723201748.25573-83-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22a Subject: [Qemu-devel] [PATCH 82/99] target/arm: Implement FCMP for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-stable@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée These where missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Tested-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20180512003217.9105-9-richard.henderson@linaro.org [rth: Diagnose lack of FP16 before fp_access_check] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell (cherry picked from commit 7a1929256ea1a03df12625e75ed571c60dca5bfb) Signed-off-by: Michael Roth --- target/arm/helper-a64.c | 10 +++++ target/arm/helper-a64.h | 2 + target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++-------- 3 files changed, 83 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index afb25ad20c..35df07adb9 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -85,6 +85,16 @@ static inline uint32_t float_rel_to_flags(int res) return flags; } +uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status) +{ + return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); +} + +uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status) +{ + return float_rel_to_flags(float16_compare(x, y, fp_status)); +} + uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) { return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ef4ddfe9d8..5c0b9bd799 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,8 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) +DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9880a5d047..05d51ecbdc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4469,14 +4469,14 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) } } -static void handle_fp_compare(DisasContext *s, bool is_double, +static void handle_fp_compare(DisasContext *s, int size, unsigned int rn, unsigned int rm, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags = tcg_temp_new_i64(); - TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); - if (is_double) { + if (size == MO_64) { TCGv_i64 tcg_vn, tcg_vm; tcg_vn = read_fp_dreg(s, rn); @@ -4493,19 +4493,35 @@ static void handle_fp_compare(DisasContext *s, bool is_double, tcg_temp_free_i64(tcg_vn); tcg_temp_free_i64(tcg_vm); } else { - TCGv_i32 tcg_vn, tcg_vm; + TCGv_i32 tcg_vn = tcg_temp_new_i32(); + TCGv_i32 tcg_vm = tcg_temp_new_i32(); - tcg_vn = read_fp_sreg(s, rn); + read_vec_element_i32(s, tcg_vn, rn, 0, size); if (cmp_with_zero) { - tcg_vm = tcg_const_i32(0); + tcg_gen_movi_i32(tcg_vm, 0); } else { - tcg_vm = read_fp_sreg(s, rm); + read_vec_element_i32(s, tcg_vm, rm, 0, size); } - if (signal_all_nans) { - gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); - } else { - gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + + switch (size) { + case MO_32: + if (signal_all_nans) { + gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } else { + gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } + break; + case MO_16: + if (signal_all_nans) { + gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } else { + gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } + break; + default: + g_assert_not_reached(); } + tcg_temp_free_i32(tcg_vn); tcg_temp_free_i32(tcg_vm); } @@ -4526,16 +4542,35 @@ static void handle_fp_compare(DisasContext *s, bool is_double, static void disas_fp_compare(DisasContext *s, uint32_t insn) { unsigned int mos, type, rm, op, rn, opc, op2r; + int size; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); op = extract32(insn, 14, 2); rn = extract32(insn, 5, 5); opc = extract32(insn, 3, 2); op2r = extract32(insn, 0, 3); - if (mos || op || op2r || type > 1) { + if (mos || op || op2r) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + size = MO_32; + break; + case 1: + size = MO_64; + break; + case 3: + size = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4544,7 +4579,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn) return; } - handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); + handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); } /* Floating point conditional compare @@ -4558,16 +4593,35 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) unsigned int mos, type, rm, cond, rn, op, nzcv; TCGv_i64 tcg_flags; TCGLabel *label_continue = NULL; + int size; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); cond = extract32(insn, 12, 4); rn = extract32(insn, 5, 5); op = extract32(insn, 4, 1); nzcv = extract32(insn, 0, 4); - if (mos || type > 1) { + if (mos) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + size = MO_32; + break; + case 1: + size = MO_64; + break; + case 3: + size = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4588,7 +4642,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) gen_set_label(label_match); } - handle_fp_compare(s, type, rn, rm, false, op); + handle_fp_compare(s, size, rn, rm, false, op); if (cond < 0x0e) { gen_set_label(label_continue); From patchwork Mon Jul 23 20:17:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142647 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6511542ljj; Mon, 23 Jul 2018 14:25:10 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeB6kGD/z1YKB1Q8ijbHFYDmsZz0TjLGVRn/X5Ns/gAfhWvK+kR1v9ZbcRaT/5M//IZyyuz X-Received: by 2002:a0c:df14:: with SMTP id g20-v6mr12688143qvl.183.1532381110257; Mon, 23 Jul 2018 14:25:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381110; cv=none; d=google.com; s=arc-20160816; b=weo/dVSEQ2r4Oal7kALsV/DrQ61eEwK1EK5S/CqlQKhBA7d4y3pU1iPKwjNj3oonyi i7yIO+EAqf5ltK3YaRi1aITxb5BWM+QTpipKfSLx1Ny+bLyJlaqAHDmItzYdd16pgghD uVF/6vF2j69AmTfOqhPLMbTBdJiw9zscYb+AE/Ogzub4yR5U1nrBN+ot+YB90zAqvVCc 0BbC/oVc2Mi8Tk518U7sUW9NvcRpz96XrTkVwRBfhBO0buLCHay4S1iBGGN/SoDZWIwR M5o8Q5j0VHZfnO07czVN+yJuY7gubjTBQiyQsnvCjFAwPvNiHIxxmGuh9IUAdYt01PVX MqxA== ARC-Message-Signature: i=1; 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id e125-v6sm9840061oig.4.2018.07.23.13.21.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:37 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:32 -0500 Message-Id: <20180723201748.25573-84-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::234 Subject: [Qemu-devel] [PATCH 83/99] target/arm: Implement FCSEL for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-stable@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée These were missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Tested-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20180512003217.9105-10-richard.henderson@linaro.org [rth: Fix erroneous check vs type] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell (cherry picked from commit ace97feef3613194900d4eb9ffc6819b840fbaeb) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 05d51ecbdc..7075f27e05 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4660,15 +4660,34 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) unsigned int mos, type, rm, cond, rn, rd; TCGv_i64 t_true, t_false, t_zero; DisasCompare64 c; + TCGMemOp sz; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); cond = extract32(insn, 12, 4); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (mos || type > 1) { + if (mos) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + sz = MO_32; + break; + case 1: + sz = MO_64; + break; + case 3: + sz = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4677,11 +4696,11 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) return; } - /* Zero extend sreg inputs to 64 bits now. */ + /* Zero extend sreg & hreg inputs to 64 bits now. */ t_true = tcg_temp_new_i64(); t_false = tcg_temp_new_i64(); - read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32); - read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32); + read_vec_element(s, t_true, rn, 0, sz); + read_vec_element(s, t_false, rm, 0, sz); a64_test_cc(&c, cond); t_zero = tcg_const_i64(0); @@ -4690,7 +4709,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) tcg_temp_free_i64(t_false); a64_free_cc(&c); - /* Note that sregs write back zeros to the high bits, + /* Note that sregs & hregs write back zeros to the high bits, and we've already done the zero-extension. */ write_fp_dreg(s, rd, t_true); tcg_temp_free_i64(t_true); From patchwork Mon Jul 23 20:17:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142663 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6522958ljj; Mon, 23 Jul 2018 14:39:31 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd9R3ehFkNiPjhYaD+8aqqBgqWVEA4gCxZNrn+AEn3+JghZVjSwSOVcpufNg9ctY2mLKqJh X-Received: by 2002:a37:c88b:: with SMTP id t11-v6mr13061241qkl.426.1532381971287; Mon, 23 Jul 2018 14:39:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381971; cv=none; d=google.com; s=arc-20160816; b=ha+cfAj+DR5JzUk50aHQQ5K78xJo/dt89MZCWuN1M9fOaZIwyxUQYs7hvlVXIaIqeG fdDS+Utz9zUGIF8ap/szmW+DKbhahoQMRUWbv7/vRMi/sGD/xUyqgTRtkE7RpLqMw5qe Y5C1XIw9FISKhF2pOgiGHrdntOJ6/F3wANO5no3/M4Yzd0bZC/VF3sohVFn+l7jrvUqC izpTRt80nwa6OHFc5Io7KUyP9+kjGE1T6Prt2sA1LcWldCwFDRmBpo9cD1egdKB1pd7i MBA1Yc/F28NXqxHATqgvKdmRa5uey8Q352y7VrOx7igLd+wG6zVZazIPmDtkQFK/s2dA Uo3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=9tH4pupl7s1gkH526KWx8Yj77S7uAqfJTbdOKzq4alk=; b=IuWDExhxaB963fUo5nhfE65JzX1qYg4nOq740scQ6Vl8+6Enyz3xb9TRzeJ22pUoxD rix5i0xRrbANtZMiEaB1g0WHvQfa3gpznYo04UfyIZ5Pl32v913Y5wRL2NdKz1IPqTse Blpe2ZO9Z/yhq+6Cxr65xjTpsrRh8g2WM17Er3bjvpIM0UubidCdQEmM42AJnOMFU/+9 B9PFLHBBHRoNSS8AHUswNJuuoYjKW0VtoLD6HBHj1Qdvf3WALh5LIV0uvjymVFKnK2jD rJCxi1mspG3jU2uYUCM7QEYyVeZ1/ezdNgIJdxfyIoVt99nVWjJd8PveaiAw61oZtCZ0 1HsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=IKye51sg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id m7-v6sm7929283oia.32.2018.07.23.13.21.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:39 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:33 -0500 Message-Id: <20180723201748.25573-85-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::230 Subject: [Qemu-devel] [PATCH 84/99] target/arm: Implement FMOV (immediate) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-stable@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée All the hard work is already done by vfp_expand_imm, we just need to make sure we pick up the correct size. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Tested-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20180512003217.9105-11-richard.henderson@linaro.org [rth: Merge unallocated_encoding check with TCGMemOp conversion.] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell (cherry picked from commit 6ba28ddb9be37bdb67e3e38007a53ccbdcd010df) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7075f27e05..f4587c3814 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5431,11 +5431,25 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) { int rd = extract32(insn, 0, 5); int imm8 = extract32(insn, 13, 8); - int is_double = extract32(insn, 22, 2); + int type = extract32(insn, 22, 2); uint64_t imm; TCGv_i64 tcg_res; + TCGMemOp sz; - if (is_double > 1) { + switch (type) { + case 0: + sz = MO_32; + break; + case 1: + sz = MO_64; + break; + case 3: + sz = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -5444,7 +5458,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) return; } - imm = vfp_expand_imm(MO_32 + is_double, imm8); + imm = vfp_expand_imm(sz, imm8); tcg_res = tcg_const_i64(imm); write_fp_dreg(s, rd, tcg_res); From patchwork Mon Jul 23 20:17:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142648 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6511721ljj; Mon, 23 Jul 2018 14:25:24 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd/Ip4EETLSckZMB5tp20ZUT9oS/EG8CkdbblhuGXRyWo3umgEYY8Sc9EDV5LQZv1HGaEUP X-Received: by 2002:a37:cf50:: with SMTP id e77-v6mr13029479qkj.74.1532381124572; Mon, 23 Jul 2018 14:25:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532381124; cv=none; d=google.com; s=arc-20160816; b=qg/E9V0auKP62a/O8SbebS6ZW3GtCymW2AISf4d9VqoMGfH//Jv//ht1BIt3gSMbsh bGDEUfR3avc78jWPMegY/xDrtLQM7FDVK4O1UXFf+ffHZrdGrEtDKRXuwkAQS8sBwA8V s9/CxwUxIIRxh0jmIIH3Sfd/7qA2AlP2kOUTOTZY11eonbK2ScA4volQQl/j3K3QewDO jOHuQkAJb0uhbVnbMzlmYYD04cSAw0xmO/Gj+BjvIVv4t8p0X6KcThx+E6mDQuMvvDDv MnajKBjgJeylZpmxaJ+gvMJCSwFdPuyK2qev9WjHNlj+FybZNybOWzlBakLv9JVKJk26 IEVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8+VpBNagLMbQDxPV1taJiZlYPM1RVAX3Yfi4C69c1rI=; b=EICay1bz9abZvVwWE13SJ1UVp8VB4J/HCZ0YoAvAIelihqzlF5hRVvGZEhfpAPL960 S9ncIhuqiex8hdZfRUpHziu+CX9hEVPv0lbCprlKrsnsPHNWSUGiIEM2c/jXfCouByzx 16SoLOSWGD1h+hcmHB2znYNUX+4zGmDhwsgMdRNTZZ7ygWmdbaNLCQRIV2FOaprfxtj3 /3eOMqaoSVugdX1tqdGbbpYr1+IEZVNknj3AzEVpArgnP3FB0zUpCClB6f2g//wkR9ot 6FJoHMVvpQdjEjwCqkpXH2BM8sGNf0w2pgDmm+QUFqgrr2PcZqkWAyPPc1P6AKiTcjxE 1mXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=D+Xa2p7n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id q63-v6sm1776773oia.54.2018.07.23.13.21.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:41 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:34 -0500 Message-Id: <20180723201748.25573-86-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22c Subject: [Qemu-devel] [PATCH 85/99] target/arm: Fix sqrt_f16 exception raising X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-stable@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée We are meant to explicitly pass fpst, not cpu_env. Cc: qemu-stable@nongnu.org Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 905edee9101c54cda5b72286b7f7607cf1c3c4d1) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f4587c3814..618f5268cc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4733,7 +4733,8 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; case 0x3: /* FSQRT */ - gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env); + fpst = get_fpstatus_ptr(true); + gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); break; case 0x8: /* FRINTN */ case 0x9: /* FRINTP */ From patchwork Mon Jul 23 20:17:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142664 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6527067ljj; Mon, 23 Jul 2018 14:44:57 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeoONTPvH9HEi13E/wkrpdfIyuCxmtWiuJxPKNQJeZly2kMbXRHX6Ta+OqLcyCKeQ7Irtzs X-Received: by 2002:ac8:71d0:: with SMTP id i16-v6mr14256523qtp.111.1532382297577; Mon, 23 Jul 2018 14:44:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532382297; cv=none; d=google.com; s=arc-20160816; b=cbJEBF+tY9vSS5J2Oa60p2W2tIWyrhqKdVb5/zoR5cliT1aYSJFX58MHmr319ye6pE 3zzIgbZV1gPcJ39pUpSUSeraRUPdpAeIwqY+ZkKh3gUJvWDW/tf58zmYZ87dOB68SnkJ ZXZWc78EYtjFoVG0UKhQJAHZ0L/chOaZlVr3Gsv/ws038G/qHbTWuiZXwlwp/dnG8Gf8 FfwFuMRyAj3OYy91toZZq3hY6h8DXHHiibU+yMamP9WZAcjawrcuDEhPzoWEoySTDsvI WWmPMPO+etYdtsB4wVGa7oQWMag7Wkv02aogJsBONbIRNY2MXWn1JxRPaiwmkcrnANfo 5APw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eyN2xqzxccTS5JZm6NGArfM+iXBtgcgfJ9nYhuRKytg=; b=dN6ThinS62ozu0x4pyeUORaTwVwOAEqX3BE449FfWREd00oWTmOr7uTkL/MiJEBxO4 Cvp8CT4ekKoEyG3aKhpNb7KFr5Seod+OKpar87boHpkTbyoKqdJUECvqPEeac71rt3mS kBtL4ryVfZTEFTY79vO7eKfyxOK09mIagoNvv6SRG3R8OW9LLPYOYFZcKN46HbGHWfFu 8LOknpAR6Qc2hhbyJ0u76dRvTvy+pQ4dlqh62xiZxa+xwdXg5TJq1fccppJBWD9B4XoM bVI4Q42Igx8KRcalu1Hubr5g4I+WgKphsEaouqqwGWdwPK0A0wV+e4EZxk8M81m4IUA4 WQXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=CVYcqBBI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id a8-v6sm7950609oia.24.2018.07.23.13.21.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:21:59 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:41 -0500 Message-Id: <20180723201748.25573-93-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::242 Subject: [Qemu-devel] [PATCH 92/99] tcg: Reduce max TB opcode count X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Also, assert that we don't overflow any of two different offsets into the TB. Both unwind and goto_tb both record a uint16_t for later use. This fixes an arm-softmmu test case utilizing NEON in which there is a TB generated that runs to 7800 opcodes, and compiles to 96k on an x86_64 host. This overflows the 16-bit offset in which we record the goto_tb reset offset. Because of that overflow, we install a jump destination that goes to neverland. Boom. With this reduced op count, the same TB compiles to about 48k for aarch64, ppc64le, and x86_64 hosts, and neither assertion fires. Cc: qemu-stable@nongnu.org Reported-by: "Jason A. Donenfeld" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson (cherry picked from commit 9f754620651d3432114f4bb89c7f12cbea814b3e) Signed-off-by: Michael Roth --- tcg/aarch64/tcg-target.inc.c | 2 +- tcg/arm/tcg-target.inc.c | 2 +- tcg/i386/tcg-target.inc.c | 2 +- tcg/mips/tcg-target.inc.c | 2 +- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c | 2 +- tcg/sparc/tcg-target.inc.c | 4 ++-- tcg/tcg.c | 13 ++++++++++++- tcg/tcg.h | 6 ++++-- tcg/tci/tcg-target.inc.c | 2 +- 10 files changed, 26 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index be3192078d..4562d36d1b 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1733,7 +1733,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); } tcg_out_insn(s, 3207, BR, TCG_REG_TMP); - s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); + set_jmp_reset_offset(s, a0); break; case INDEX_op_goto_ptr: diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 56a32a470f..e1fbf465cb 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1822,7 +1822,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movi32(s, COND_AL, base, ptr - dil); } tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); + set_jmp_reset_offset(s, args[0]); } break; case INDEX_op_goto_ptr: diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5357909fff..ccde8801a5 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2245,7 +2245,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1, (intptr_t)(s->tb_jmp_target_addr + a0)); } - s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); + set_jmp_reset_offset(s, a0); break; case INDEX_op_goto_ptr: /* jmp to the given host address (could be epilogue) */ diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index ca5f1d4894..cff525373b 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1744,7 +1744,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); } tcg_out_nop(s); - s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); + set_jmp_reset_offset(s, a0); break; case INDEX_op_goto_ptr: /* jmp to the given host address (could be epilogue) */ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 86f7de5f7e..c2f729ee8f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -2025,10 +2025,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); - s->tb_jmp_reset_offset[args[0]] = c = tcg_current_code_size(s); + set_jmp_reset_offset(s, args[0]); if (USE_REG_TB) { /* For the unlinked case, need to reset TCG_REG_TB. */ - c = -c; + c = -tcg_current_code_size(s); assert(c == (int16_t)c); tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); } diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 9af6dcef05..17c435ade5 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1783,7 +1783,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* and go there */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); } - s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); + set_jmp_reset_offset(s, a0); /* For the unlinked path of goto_tb, we need to reset TCG_REG_TB to the beginning of this TB. */ diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index bc673bd8c6..04bdc3df5e 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1388,12 +1388,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); tcg_out_nop(s); } - s->tb_jmp_reset_offset[a0] = c = tcg_current_code_size(s); + set_jmp_reset_offset(s, a0); /* For the unlinked path of goto_tb, we need to reset TCG_REG_TB to the beginning of this TB. */ if (USE_REG_TB) { - c = -c; + c = -tcg_current_code_size(s); if (check_fit_i32(c, 13)) { tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); } else { diff --git a/tcg/tcg.c b/tcg/tcg.c index 66997cc653..9c1de541d6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -293,6 +293,14 @@ TCGLabel *gen_new_label(void) return l; } +static void set_jmp_reset_offset(TCGContext *s, int which) +{ + size_t off = tcg_current_code_size(s); + s->tb_jmp_reset_offset[which] = off; + /* Make sure that we didn't overflow the stored offset. */ + assert(s->tb_jmp_reset_offset[which] == off); +} + #include "tcg-target.inc.c" static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend) @@ -3354,7 +3362,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) break; case INDEX_op_insn_start: if (num_insns >= 0) { - s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); + size_t off = tcg_current_code_size(s); + s->gen_insn_end_off[num_insns] = off; + /* Assert that we do not overflow our stored offset. */ + assert(s->gen_insn_end_off[num_insns] == off); } num_insns++; for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { diff --git a/tcg/tcg.h b/tcg/tcg.h index 17cf764565..755860e50d 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -848,9 +848,11 @@ static inline bool tcg_op_buf_full(void) /* This is not a hard limit, it merely stops translation when * we have produced "enough" opcodes. We want to limit TB size * such that a RISC host can reasonably use a 16-bit signed - * branch within the TB. + * branch within the TB. We also need to be mindful of the + * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] + * and TCGContext.gen_insn_end_off[]. */ - return tcg_ctx->nb_ops >= 8000; + return tcg_ctx->nb_ops >= 4000; } /* pool based memory allocation */ diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index cc949bea85..62ed097254 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -574,7 +574,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, /* Indirect jump method. */ TODO(); } - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); + set_jmp_reset_offset(s, args[0]); break; case INDEX_op_br: tci_out_label(s, arg_label(args[0])); From patchwork Mon Jul 23 20:17:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 142636 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp6458629ljj; Mon, 23 Jul 2018 13:21:53 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdGOEx7dkiuS9idVSR0C55XSiUVmM6sa3V0qInC78Xot71rAT5d1/+1CUizJMQEGNOSMEJI X-Received: by 2002:aed:35fb:: with SMTP id d56-v6mr13477244qte.17.1532377313799; Mon, 23 Jul 2018 13:21:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532377313; cv=none; d=google.com; s=arc-20160816; b=G26uEf7z2j8Ispr35vUj4wIaoqdRdLXgcMHlM6smr312UcTzSZg9VFB+X35U0Ydudt WAy6QlBY7cH/k+KrXYVptZFFXzqRnw81jjIuwR3iByS87saPS6o6rWQYbwRdeVxUGLnQ M6/nsK1gtMkFUq4TYfVR+To6w4P9s67f6x2yvPL8Q8JOAMT6Pk4oY+x84T6bWHBKIVgM 2u0i/RtN75uw5QIqpFW8iPPn7g+WLKOjv24o91tvDiVDlXl7lWPzJrJ1aewAexqBB+LA 2YZhN+iT3kRyqDqHkoI+Tr/6YlNQY+fJ9L+HKVtdZOPCLyTMIAf50miEtFdvsnGvSF21 b5DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=biOW1GJVIC0Bmz/mcpkMKH6ikxHoUwXFzn86ZR5EJ2Q=; b=LogazCdKXXGctsefoWDdfkJlA1CSdIJB2pMk5FCU9X8UbQ/TqRVy1MAJcIxNt/ug/V QxiqWA0NMAtl/vKa1d060Zj02cEq7kaWXre5hsbOwhAS1Iks5B8MFEQdJCi1/qJVeb6/ LQoBxd+Rv8GWq7jLyqFS8UUHhyh4Godz74CAM5amdBxuXdJLFO3Nf7hckmtvTqVcZrfH ljLuG7TYYRs5YLZNDZU9gSqVQKjy1GPXgGZmXRK5jyoaU0+ynK7bPtpB9CCmPNkayRsz YqTsLvi0ln9PjTf+c0m6Re1uPcHKFivQs4HorW3gxW/S8bXKFnvGHCbQL3BPnLoOVePk B9wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=WZR7BSt0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id d191-v6sm11780876oig.16.2018.07.23.13.18.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:18:34 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:17:48 -0500 Message-Id: <20180723201748.25573-100-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 99/99] tcg/i386: Mark xmm registers call-clobbered X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When host vector registers and operations were introduced, I failed to mark the registers call clobbered as required by the ABI. Fixes: 770c2fc7bb7 Cc: qemu-stable@nongnu.org Reported-by: Jason A. Donenfeld Signed-off-by: Richard Henderson (cherry picked from commit 672189cd586ea38a2c1d8ab91eb1f9dcff5ceb05) Signed-off-by: Michael Roth --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ccde8801a5..5727999bb3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3529,7 +3529,7 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; } - tcg_target_call_clobber_regs = 0; + tcg_target_call_clobber_regs = ALL_VECTOR_REGS; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);