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[88.1.72.161]) by smtp.gmail.com with ESMTPSA id q19sm12737909wmd.1.2017.05.08.08.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 May 2017 08:16:06 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, trini@konsulko.com, marex@denx.de Date: Mon, 8 May 2017 17:15:57 +0200 Message-Id: <1494256561-7385-2-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Cc: xuejiancheng@hisilicon.com, u-boot@lists.denx.de, daniel.thompson@linaro.org, elder@linaro.org Subject: [U-Boot] [PATCHv3 1/5] ARM64: dts: hi3798cv200-poplar: add device tree bindings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" pulled from linux-next tag 20170505 Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm/dts/hi3798cv200-poplar.dts | 162 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 411 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 677 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts new file mode 100644 index 0000000..b914287 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -0,0 +1,162 @@ +/* + * DTS File for HiSilicon Poplar Development Board + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +#include +#include "hi3798cv200.dtsi" + +/ { + model = "HiSilicon Poplar Development Board"; + compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; + + aliases { + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + user-led0 { + label = "USER-LED0"; + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "USER-LED1"; + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "USER-LED2"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + user-led3 { + label = "USER-LED3"; + gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; +}; + +&gmac1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ð_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + + eth_phy1: phy@3 { + reg = <3>; + }; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = "LS-GPIO-E", "", + "", "", + "", "LS-GPIO-F", + "", "LS-GPIO-J"; +}; + +&gpio2 { + status = "okay"; + gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", + "LS-GPIO-L", "LS-GPIO-G", + "LS-GPIO-K", "", + "", ""; +}; + +&gpio3 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "LS-GPIO-C", "", + "", "LS-GPIO-B"; +}; + +&gpio4 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "LS-GPIO-D", + "", ""; +}; + +&gpio5 { + status = "okay"; + gpio-line-names = "", "USER-LED-1", + "USER-LED-2", "", + "", "LS-GPIO-A", + "", ""; +}; + +&gpio6 { + status = "okay"; + gpio-line-names = "", "", + "", "USER-LED-0", + "", "", + "", ""; +}; + +&gpio10 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "", + "USER-LED-3", ""; +}; + +&i2c0 { + status = "okay"; + label = "LS-I2C0"; +}; + +&i2c2 { + status = "okay"; + label = "LS-I2C1"; +}; + +&ir { + status = "okay"; +}; + +&spi0 { + status = "okay"; + label = "LS-SPI0"; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + label = "LS-UART0"; +}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi new file mode 100644 index 0000000..75865f8 --- /dev/null +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -0,0 +1,411 @@ +/* + * DTS File for HiSilicon Hi3798cv200 SoC. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +/ { + compatible = "hisilicon,hi3798cv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ + <0x0 0xf1002000 0x0 0x100>; /* GICC */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc: soc@f0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xf0000000 0x10000000>; + + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + + gmacphyrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>, + <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>; + }; + }; + + sysctrl: system-controller@8000000 { + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; + reg = <0x8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + uart0: serial@8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b00000 0x1000>; + interrupts = ; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b02000 0x1000>; + interrupts = ; + clocks = <&crg HISTB_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b10000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C0_CLK>; + status = "disabled"; + }; + + i2c1: i2c@8b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b11000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C1_CLK>; + status = "disabled"; + }; + + i2c2: i2c@8b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b12000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C2_CLK>; + status = "disabled"; + }; + + i2c3: i2c@8b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C3_CLK>; + status = "disabled"; + }; + + i2c4: i2c@8b14000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C4_CLK>; + status = "disabled"; + }; + + spi0: spi@8b1a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8b1a000 0x1000>; + interrupts = ; + num-cs = <1>; + cs-gpios = <&gpio7 1 0>; + clocks = <&crg HISTB_SPI0_CLK>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "snps,dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + gpio0: gpio@8b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b20000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@8b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b21000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio2: gpio@8b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b22000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio3: gpio@8b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b23000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio4: gpio@8b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b24000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio5: gpio@8004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8004000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio6: gpio@8b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b26000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio7: gpio@8b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b27000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio8: gpio@8b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b28000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio9: gpio@8b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b29000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio10: gpio@8b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2a000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio11: gpio@8b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2b000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio12: gpio@8b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2c000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gmac0: ethernet@9840000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9840000 0x1000>, + <0x984300c 0x4>; + interrupts = ; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, + <&crg 0xcc 10>, + <&gmacphyrst 0>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + gmac1: ethernet@9841000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9841000 0x1000>, + <0x9843010 0x4>; + interrupts = ; + clocks = <&crg HISTB_ETH1_MAC_CLK>, + <&crg HISTB_ETH1_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 9>, + <&crg 0xcc 11>, + <&gmacphyrst 1>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + ir: ir@8001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x8001000 0x1000>; + interrupts = ; + clocks = <&sysctrl HISTB_IR_CLK>; + status = "disabled"; + }; + }; +}; diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 0000000..181c0f0 --- /dev/null +++ b/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 + + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 0000000..884fd91 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif From patchwork Mon May 8 15:15:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 98821 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1378979qge; Mon, 8 May 2017 08:17:51 -0700 (PDT) X-Received: by 10.80.150.194 with SMTP id z2mr15847644eda.43.1494256671271; Mon, 08 May 2017 08:17:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494256671; cv=none; d=google.com; s=arc-20160816; b=XSyhTUnfHU45L6NN4u+2leiEkleZo6GDPo8t2NxGokSFTMxgmX9yMrVbih7JiEfmPJ 6NDcpHyYC5OxnQrRmJlJo9UiI0mzRWK2StM7SuJ/ED0Mor9REaWnyTBhSkkmnpT5nUyV /TfhN+lS4fnwmjDVBZwY1hWox9jhPRg7zyugQdhHOsOvLGZzH7JJ7XRRHt3NpnnqJrpC bX5J92IkLKSDuyg0cExxMQvuduj+ZNSKJ0AX+ljkWtRFxIVD06c+mvZbel/ULMdIYN3u 6iL7O0Ps/AjFT33jZf/5T48CPibVAWm07/FaMMwc6FdkLpHm/NSzENijM23faTZ+gV9O Eahg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=GW3HOC+JVpp3dyydbsI7YOse56szj1gbGQfX4EGpA5Y=; b=Gp/BU5EesE0oxbRYtaHZB2vsAKaNrBKd0WLRcE+zr2WmGRkSd+7FRTwiaWcL5ADfBC 9XikTKzJ6SZwmedKaH6lLwUrSHefL6Fok4SCdUwoM3OiQCwE4UjZ3nGqkz/p8RSJClTT WM2MrcehG6G9FnkWTz5YQiGbshw6UEKyCkjZhUzTL6QNrWSB+U4axcdz9UqnE7fUPjhq cIBelnm2B7TZQdpz9Xx94aD6EtVhTp37hvEsa/z5l5B6RdxqH4WU1o3jQ53j1LmMc9tV pIrXxosltxTLEcMC58s0Xp8Xj0kRNqWxNdxMi+IWBencLIM0vTpvTET4mGhlZqzpl/J9 mVrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. 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[88.1.72.161]) by smtp.gmail.com with ESMTPSA id q19sm12737909wmd.1.2017.05.08.08.16.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 May 2017 08:16:07 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, trini@konsulko.com, marex@denx.de Date: Mon, 8 May 2017 17:15:58 +0200 Message-Id: <1494256561-7385-3-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Cc: xuejiancheng@hisilicon.com, u-boot@lists.denx.de, daniel.thompson@linaro.org, elder@linaro.org Subject: [U-Boot] [PATCHv3 2/5] ARM64: dts: poplar: add usb-ehci node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" --- arch/arm/dts/hi3798cv200-poplar.dts | 5 +++++ arch/arm/dts/hi3798cv200.dtsi | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts index b914287..998472a 100644 --- a/arch/arm/dts/hi3798cv200-poplar.dts +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -76,6 +76,10 @@ }; }; +&usb_ehci { + status = "okay"; +}; + &gpio1 { status = "okay"; gpio-line-names = "LS-GPIO-E", "", @@ -159,4 +163,5 @@ status = "okay"; label = "LS-UART0"; }; + /* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi index 75865f8..275282c 100644 --- a/arch/arm/dts/hi3798cv200.dtsi +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -106,6 +106,12 @@ #reset-cells = <2>; }; + usb_ehci:ehci@9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x100>; + status = "disabled"; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; From patchwork Mon May 8 15:15:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 98823 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1379202qge; Mon, 8 May 2017 08:18:22 -0700 (PDT) X-Received: by 10.80.184.51 with SMTP id j48mr43205606ede.165.1494256702657; Mon, 08 May 2017 08:18:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494256702; cv=none; d=google.com; s=arc-20160816; b=jKj18D/+mYSaU+4r5C+vJ9a46pjbZn+OMlU6ARsQwDXVi8RxCPgKX5e2PrAlbTWeEf czhOFXHapo/GL/BardBoMoYePQJb0UirVwCd396LDcI5saX4s+Bqs2ZIYTRlq/s4TaXS b3SfRPMJyiKDgARYI8J1kqM5aG1lkpdW975Uj8M8pVJroLStCnwZSForpw5IH2ShurtG Q/o+cNwvi0RPrAfKRl1CdfULhXoD7rGvnuqTS3reu01iEPGDDTe43TlOdghotymWklcI kGyoR+zLGsHwn3sit2I+RhSLyvJIPtnWdKF7lCgc3WLynnY0O1up/vOrP1jPQF3sFWNF KdYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=R5LZ+gOPyCK4TxZI5F4y3eyULVU4qWDRw9yzJ0TNxAw=; b=GIGQZxEFD9fLLQpb6WXOytmQQeOogc/cjWxyoIdfeQE9Zj67vFbzUM2qlSVi5vJOsC XSMWfGKi6S9f6dmDlz8THqZFKG34rMMbsniLVUuPaRLxPPEhOfmz6h4tlmPrTt2q909I BkG3X4l/X+NCmo3o9emMyfKld+X1Wm8u035YIgaaKg8NeNp12tC2SbpIQYC99XMRTtNj lhKyuG454phLmLgyOuO1shW+0dikhW9rQ/r8KQMDefcxGKexcA6sbrUJF1LzGpAGAc35 xFkYUFW2MkPnDUk109vc/1Le5eUlaRuN25GZIZzRUfeUMv6XkqBoHX8VGoZVVHsFChZM Oy1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. 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[88.1.72.161]) by smtp.gmail.com with ESMTPSA id q19sm12737909wmd.1.2017.05.08.08.16.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 May 2017 08:16:08 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, trini@konsulko.com, marex@denx.de Date: Mon, 8 May 2017 17:15:59 +0200 Message-Id: <1494256561-7385-4-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Cc: xuejiancheng@hisilicon.com, u-boot@lists.denx.de, daniel.thompson@linaro.org, elder@linaro.org Subject: [U-Boot] [PATCHv3 3/5] ARM64: dts: poplar: add clock frequency to the console node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" --- arch/arm/dts/hi3798cv200.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi index 275282c..377303f 100644 --- a/arch/arm/dts/hi3798cv200.dtsi +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -116,6 +116,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; interrupts = ; + clock = <75000000>; clocks = <&sysctrl HISTB_UART0_CLK>; clock-names = "apb_pclk"; status = "disabled"; From patchwork Mon May 8 15:16:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 98824 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1379532qge; Mon, 8 May 2017 08:19:12 -0700 (PDT) X-Received: by 10.80.138.145 with SMTP id j17mr8708676edj.141.1494256752089; Mon, 08 May 2017 08:19:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494256752; cv=none; d=google.com; s=arc-20160816; b=lnlozDYaVVQOgDpUDV1QOJZuF8xvkwUuFC2/m9TSzgEIkqKgVfgitpvZ/OcQVWTpV0 0caDDZk3o/M9hIrZv6jt1oGzu7mSRy3CIJHj5GQbMm9BVpDso/l6jwQTrBc7/MQGShRJ e3dSkTpfmmfhImvo8JoOkcheXmrxvtnMurLZbLSX73kOHCQzU3fLEH9FFC0RdF5FeRaF 8l/eOj8boTqZbPze6W2/lh2dH+vQ1cuXx3ASy5xWNB54MroNnCfCjjz0mN22PDtyWktu WKUq5y89wiU0S7NMful/E7nGTSlJ15t7o8y23QxftRjp3flJeMRV6krJVCArJa0sF71d ERgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=Soz1IydivRmERa8arkUoYCoj7SACb6sRRn7lmUepI3c=; b=R3jpE55VfHv+pP3tSM+jogrgwBauC+3+xDHooFP6tt5iWyzRJ+svI2mojoNQxIAVz0 68XRNv4GxSXWV5Nrgttw/hktjbEu/vkbQqyQHTsIeNN+VjHeStebA0ITu9QyhwL+shu8 F3WrcsK/uBSixuU/CLvlHvtl48GTfziBpBJn0suYsBzWZ5ajMwwTg58qkYhp4+WUf/rR Bsd4d5uMmfIf2u9VPsMD8LJ//LAA1om3QA5pnW0GiLOpqcy/MPDQ2ggPMJrCM1gyC9lj JWNjHFh0tjSaKP91H4i9ZpIK5i1WY+1Jy/GJmhayREK/2LWasm1p7dlx7Tgg/9QjXIBa G1UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. 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[88.1.72.161]) by smtp.gmail.com with ESMTPSA id q19sm12737909wmd.1.2017.05.08.08.16.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 May 2017 08:16:10 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, trini@konsulko.com, marex@denx.de Date: Mon, 8 May 2017 17:16:00 +0200 Message-Id: <1494256561-7385-5-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Cc: xuejiancheng@hisilicon.com, u-boot@lists.denx.de, daniel.thompson@linaro.org, elder@linaro.org Subject: [U-Boot] [PATCHv3 4/5] driver: mmc: update debug info X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver is used in another board; remove board information from the driver debug log. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Tom Rini --- drivers/mmc/hi6220_dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index fdaf1e4..d795198 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -20,7 +20,7 @@ static int hi6220_dwmci_core_init(struct dwmci_host *host, int index) { - host->name = "HiKey DWMMC"; + host->name = "Hisilicon DWMMC"; host->dev_index = index; From patchwork Mon May 8 15:16:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 98822 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1379166qge; Mon, 8 May 2017 08:18:17 -0700 (PDT) X-Received: by 10.80.168.5 with SMTP id j5mr45506490edc.128.1494256697673; Mon, 08 May 2017 08:18:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494256697; cv=none; d=google.com; s=arc-20160816; b=wlbgb3HNro+0Zw++kcT4gJmCXU/jIKS4fcTAREfxAXSSFdZBYtaetXGjNaw9Lc5wzp tR8g2fWMnzqVUR/vi9sZIfko1BoRv0VTTfEyTjuHtXqQ2/voKXeEP7s8vfKF38t+4vZY Q3rtJKG6VN1wutaPuF5GMP3SDq2pTYY7+jtYA/EnoqlEh2K19NJXsQVbPUCbJ+j8bkqA R+u1EJ1LZny67CMBNgnqI5Hj7pEPeO+MstE71tdbvN5JeXRWaGq5DmtZNfsxnf+g65PE nPybAadL3r6LcDugqLQy+gqeDB1AXYFTUIQTi7wjNjfVVXAXujStnpFiEbpbmrfwkFIz Awww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=NWUJQWVx/Hu0cPEE4n+vDanFDFh6R3O9kta2mQ6+gGQ=; b=H/CQYf62V4XjG+gckzrSZsond3pm3v1c53N/KxmQw+pnJNrLCNpCQKJ1zYDb/tXKNC muuqKRPeMSwRsXOaxnPBWvgWB3JBKQFskUvrb9zCcKEtRkO0O9bGbk2UISvacESN8PC/ tuBhb6SuBWbHerTeUNWRHnB0dJOidr00q6BxrOfPyc3gxg2979p7NhTtuzXI2PD0cSwt 1pk/npJA3eEgugjuWrQIigDs/GCyRaZ/meISRkyiNlvEDkU5ARwbPztNIFVyk4GCN45z h4qt+AFwkM53oVJ0ahpzogoftPvVnvu7W+D+BVA8vmSoKVGbd+dKHSjtN2ay4Lu+mgc/ CK0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. 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[88.1.72.161]) by smtp.gmail.com with ESMTPSA id q19sm12737909wmd.1.2017.05.08.08.16.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 May 2017 08:16:11 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, trini@konsulko.com, marex@denx.de Date: Mon, 8 May 2017 17:16:01 +0200 Message-Id: <1494256561-7385-6-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1494256561-7385-1-git-send-email-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Cc: xuejiancheng@hisilicon.com, u-boot@lists.denx.de, daniel.thompson@linaro.org, elder@linaro.org Subject: [U-Boot] [PATCHv3 5/5] ARM64: poplar: hi3798cv200: u-boot support for Poplar 96Boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This port adds support for: 1) Serial 2) eMMC 3) USB It has been tested with ARM TRUSTED FIRMWARE running u-boot as the BL33 executable [see board's README] eMMC has been tested for reading and booting the loader[1] and linux kernels as well as saving the u-boot environment. USB has been tested with ASIX networking adapter and SanDisk 7.4GB drive. PSCI has been tested via the reset call. The firwmare upgrade process has been tested via TFTP and USB FAT filesystem containing the fastboot.bin image in one of the partitions. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Tom Rini --- arch/arm/Kconfig | 12 ++ arch/arm/include/asm/arch-hi3798cv200/dwmmc.h | 13 ++ .../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 50 +++++ board/hisilicon/poplar/Kconfig | 15 ++ board/hisilicon/poplar/MAINTAINERS | 6 + board/hisilicon/poplar/Makefile | 7 + board/hisilicon/poplar/README | 232 +++++++++++++++++++++ board/hisilicon/poplar/poplar.c | 155 ++++++++++++++ configs/poplar_defconfig | 26 +++ include/configs/poplar.h | 86 ++++++++ 10 files changed, 602 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/dwmmc.h create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 board/hisilicon/poplar/Kconfig create mode 100644 board/hisilicon/poplar/MAINTAINERS create mode 100644 board/hisilicon/poplar/Makefile create mode 100644 board/hisilicon/poplar/README create mode 100644 board/hisilicon/poplar/poplar.c create mode 100644 configs/poplar_defconfig create mode 100644 include/configs/poplar.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1df6b36..d41e047 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -816,6 +816,17 @@ config TARGET_HIKEY Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. +config TARGET_POPLAR + bool "Support Poplar 96boards Enterprise Edition Platform" + select ARM64 + select DM + select OF_CONTROL + select DM_SERIAL + select DM_USB + help + Support for Poplar 96boards EE platform. It features a HI3798cv200 + SoC, with 4xA53 CPU, MaliT720 GPU, and 1GB RAM. + config TARGET_LS1012AQDS bool "Support ls1012aqds" select ARCH_LS1012A @@ -1145,6 +1156,7 @@ source "board/grinn/chiliboard/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" +source "board/hisilicon/poplar/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" diff --git a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h new file mode 100644 index 0000000..1060d94 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _HI3798cv200_DWMMC_H_ +#define _HI3798cv200_DWMMC_H_ + +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); + +#endif /* _HI3798cv200_DWMMC_H_ */ diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..1bd0d78 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__ + +#define REG_BASE_PERI_CTRL 0xF8A20000 +#define REG_BASE_CRG 0xF8A22000 + +/* DEVICES */ +#define REG_BASE_EHCI 0XF9890000 +#define REG_BASE_MCI 0xF9830000 + +/* PERI control registers (4KB) */ + /* USB2 PHY01 configuration register */ +#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) + +/* PERI CRG registers (4KB) */ + /* USB2 CTRL0 clock and soft reset */ +#define PERI_CRG46 (REG_BASE_CRG + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20) + + /* USB2 PHY clock and soft reset */ +#define PERI_CRG47 (REG_BASE_CRG + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14) + + +#endif diff --git a/board/hisilicon/poplar/Kconfig b/board/hisilicon/poplar/Kconfig new file mode 100644 index 0000000..3397295 --- /dev/null +++ b/board/hisilicon/poplar/Kconfig @@ -0,0 +1,15 @@ +if TARGET_POPLAR + +config SYS_BOARD + default "poplar" + +config SYS_VENDOR + default "hisilicon" + +config SYS_SOC + default "hi3798cv200" + +config SYS_CONFIG_NAME + default "poplar" + +endif diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS new file mode 100644 index 0000000..0cc01c8 --- /dev/null +++ b/board/hisilicon/poplar/MAINTAINERS @@ -0,0 +1,6 @@ +Poplar BOARD +M: Jorge Ramirez-Ortiz +S: Maintained +F: board/hisilicon/poplar +F: include/configs/poplar.h +F: configs/poplar_defconfig diff --git a/board/hisilicon/poplar/Makefile b/board/hisilicon/poplar/Makefile new file mode 100644 index 0000000..101545d --- /dev/null +++ b/board/hisilicon/poplar/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2017 Linaro +# Jorge Ramirez-Ortiz +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := poplar.o diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README new file mode 100644 index 0000000..b35382b --- /dev/null +++ b/board/hisilicon/poplar/README @@ -0,0 +1,232 @@ +================================================================================ + Board Information +================================================================================ + +Developed by HiSilicon, the board features the Hi3798C V200 with an +integrated quad-core 64-bit ARM Cortex A53 processor and high +performance Mali T720 GPU, making it capable of running any commercial +set-top solution based on Linux or Android. Its high performance +specification also supports a premium user experience with up to H.265 +HEVC decoding of 4K video at 60 frames per second. + +SOC Hisilicon Hi3798CV200 +CPU Quad-core ARM Cortex-A53 64 bit +DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB +USB Two USB 2.0 ports One USB 3.0 ports +CONSOLE USB-micro port for console support +ETHERNET 1 GBe Ethernet +PCIE One PCIe 2.0 interfaces +JTAG 8-Pin JTAG +EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot +DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor +WIFI 802.11AC 2*2 with Bluetooth +CONNECTORS One connector for Smart Card One connector for TSI + + +================================================================================ + BUILD INSTRUCTIONS +================================================================================ + +Compile from source: +==================== + +Get all the sources + + > mkdir -p ~/poplar/src ~/poplar/bin + > cd ~/poplar/src + > git clone https://github.com/Linaro/poplar-l-loader.git l-loader + > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf + > git clone https://github.com/Linaro/poplar-u-boot.git u-boot + + +Compile U-Boot: +=============== + + Prerequisite: + # sudo apt-get install device-tree-compiler + + > cd ~/poplar/src/u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig + > make CROSS_COMPILE=aarch64-linux-gnu- + > cp u-boot.bin ~/poplar/bin + +Compile ARM Trusted Firmware (ATF): +=================================== + + > cd ~/poplar/src/atf + > make CROSS_COMPILE=aarch64-linux-gnu- all fip \ + SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar + +Copy resulting binaries + > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/ + > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/ + +Compile l-loader: +================= + + > cd ~/poplar/src/l-loader + > make clean + > make CROSS_COMPILE=arm-linux-gnueabi- + + Due to BootROM requiremets, rename l-loader.bin to fastboot.bin: + > cp l-loader.bin ~/poplar/bin/fastboot.bin + + +================================================================================ + FLASH INSTRUCTIONS +================================================================================ + +Two methods: + +Using USB debrick support: + Copy fastboot.bin to a FAT partition on the USB drive and reboot the + poplar board while pressing S3(usb_boot). + + The system will execute the new u-boot and boot into a shell which you + can then use to write to eMMC. + +Using U-BOOT from shell: + 1) using AXIS usb ethernet dongle and tftp + 2) using FAT formated USB drive + + +1. TFTP (USB ethernet dongle) +============================= + +Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board. +Copy fastboot.bin to your tftp server. +In u-boot make sure your network is properly setup. + +Then + +=> tftp 0x30000000 fastboot.bin +starting USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 1 USB Device(s) found +USB1: USB EHCI 1.00 +scanning bus 1 for devices... 3 USB Device(s) found + scanning usb for storage devices... 0 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found +Waiting for Ethernet connection... done. +Using asx0 device +TFTP from server 192.168.1.4; our IP address is 192.168.1.10 +Filename 'poplar/fastboot.bin'. +Load address: 0x30000000 +Loading: ################################################################# + ################################################################# + ############################################################### + 2 MiB/s +done +Bytes transferred = 983040 (f0000 hex) + +=> mmc write 0x30000000 0 0x780 + +MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK +=> reset + + +2. USING USB FAT DRIVE +======================= + +Copy fastboot.bin to any partition on a FAT32 formated usb flash drive. +Enter the uboot prompt + +=> fatls usb 0:2 + 983040 fastboot.bin + +1 file(s), 0 dir(s) + +=> fatload usb 0:2 0x30000000 fastboot.bin +reading fastboot.bin +983040 bytes read in 44 ms (21.3 MiB/s) + +=> mmc write 0x30000000 0 0x780 + +MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK + + +================================================================================ + BOOT TRACE +================================================================================ + +Bootrom start +Boot Media: eMMC +Decrypt auxiliary code ...OK + +lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000 + +Entry boot auxiliary code + +Auxiliary code - v1.00 +DDR code - V1.1.2 20160205 +Build: Mar 24 2016 - 17:09:44 +Reg Version: v134 +Reg Time: 2016/03/18 09:44:55 +Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg + +Boot auxiliary code success +Bootrom success + +LOADER: Switched to aarch64 mode +LOADER: Entering ARM TRUSTED FIRMWARE +LOADER: CPU0 executes at 0x000ce000 + +INFO: BL1: 0xe1000 - 0xe7000 [size = 24576] +NOTICE: Booting Trusted Firmware +NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL1: Built : 17:51:33, Apr 30 2017 +INFO: BL1: RAM 0xe1000 - 0xe7000 +INFO: BL1: Loading BL2 +INFO: Loading image id=1 at address 0xe9000 +INFO: Image id=1 loaded at address 0xe9000, size = 0x5008 +NOTICE: BL1: Booting BL2 +INFO: Entry point address = 0xe9000 +INFO: SPSR = 0x3c5 +NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL2: Built : 17:51:33, Apr 30 2017 +INFO: BL2: Loading BL31 +INFO: Loading image id=3 at address 0x129000 +INFO: Image id=3 loaded at address 0x129000, size = 0x8038 +INFO: BL2: Loading BL33 +INFO: Loading image id=5 at address 0x37000000 +INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17 +NOTICE: BL1: Booting BL31 +INFO: Entry point address = 0x129000 +INFO: SPSR = 0x3cd +INFO: Boot bl33 from 0x37000000 for 364311 Bytes +NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL31: Built : 17:51:33, Apr 30 2017 +INFO: BL31: Initializing runtime services +INFO: BL31: Preparing for EL3 exit to normal world +INFO: Entry point address = 0x37000000 +INFO: SPSR = 0x3c9 + + +U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar + +Model: HiSilicon Poplar Development Board +BOARD: Hisilicon HI3798cv200 Poplar +DRAM: 1 GiB +MMC: Hisilicon DWMMC: 0 +In: serial@f8b00000 +Out: serial@f8b00000 +Err: serial@f8b00000 +Net: Net Initialization Skipped +No ethernet found. + +Hit any key to stop autoboot: 0 +starting USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 1 USB Device(s) found +USB1: USB EHCI 1.00 +scanning bus 1 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found + +USB device 0: + Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade + Type: Removable Hard Disk + Capacity: 7632.0 MB = 7.4 GB (15630336 x 512) +... is now current device +Scanning usb 0:1... +=> diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c new file mode 100644 index 0000000..4569187 --- /dev/null +++ b/board/hisilicon/poplar/poplar.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region poplar_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = poplar_mem_map; + +int checkboard(void) +{ + puts("BOARD: Hisilicon HI3798cv200 Poplar\n"); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size(NULL, 0x80000000); + + return 0; +} + +int dram_init_banksize(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = i * gd->bd->bi_dram[i - 1].size; + gd->bd->bi_dram[i].size = get_ram_size( (void *) + gd->bd->bi_dram[i].start, 0x10000000); + } + + return 0; +} + +static void usb2_phy_config(void) +{ + const u32 config[] = { + /* close EOP pre-emphasis. open data pre-emphasis */ + 0xa1001c, + /* Rcomp = 150mW, increase DC level */ + 0xa00607, + /* keep Rcomp working */ + 0xa10700, + /* Icomp = 212mW, increase current drive */ + 0xa00aab, + /* EMI fix: rx_active not stay 1 when error packets received */ + 0xa11140, + /* Comp mode select */ + 0xa11041, + /* adjust eye diagram */ + 0xa0098c, + /* adjust eye diagram */ + 0xa10a0a, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(config); i++) { + writel(config[i], PERI_CTRL_USB0); + clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22)); + udelay(20); + } +} + +static void usb2_phy_init(void) +{ + /* reset usb2 controller bus/utmi/roothub */ + setbits_le32(PERI_CRG46, + USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | + USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ); + udelay(200); + + /* reset usb2 phy por/utmi */ + setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1); + udelay(200); + + /* open usb2 ref clk */ + setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN); + udelay(300); + + /* cancel usb2 power on reset */ + clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ); + udelay(500); + + usb2_phy_config(); + + /* cancel usb2 port reset, wait comp circuit stable */ + clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1); + mdelay(10); + + /* open usb2 controller clk */ + setbits_le32(PERI_CRG46, + USB2_BUS_CKEN | USB2_OHCI48M_CKEN | USB2_OHCI12M_CKEN | + USB2_OTG_UTMI_CKEN | USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN); + udelay(200); + + /* cancel usb2 control reset */ + clrbits_le32(PERI_CRG46, + USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | + USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ); + udelay(200); +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8); + if (ret) + printf("mmc init error (%d)\n", ret); + + return ret; +} + +int board_init(void) +{ + usb2_phy_init(); + + return 0; +} + diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig new file mode 100644 index 0000000..8f9f40f --- /dev/null +++ b/configs/poplar_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_TARGET_POPLAR=y +CONFIG_IDENT_STRING="poplar" +CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar" +CONFIG_SYS_PROMPT="poplar# " +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_ISO_PARTITION=n +CONFIG_MMC_DW=y +CONFIG_MMC_DW_K3=y +CONFIG_PL011_SERIAL=y +CONFIG_PSCI_RESET=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_NET=y +# CONFIG_CMD_IMLS is not set +# CONFIG_DM_GPIO is not set +CONFIG_LIB_RAND=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y + diff --git a/include/configs/poplar.h b/include/configs/poplar.h new file mode 100644 index 0000000..db208c1 --- /dev/null +++ b/include/configs/poplar.h @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2017 Linaro + * + * Jorge Ramirez-Ortiz + * + * Configuration for Poplar 96boards CE. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _POPLAR_H_ +#define _POPLAR_H_ + +#include + +/* DRAM banks */ +#define CONFIG_NR_DRAM_BANKS 4 + +/* SYS */ +#define CONFIG_SYS_BOOTM_LEN 0x1400000 +#define CONFIG_SYS_INIT_SP_ADDR 0x200000 +#define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +/* ATF bl33.bin load address (must match) */ +#define CONFIG_SYS_TEXT_BASE 0x37000000 + +/* PL010/PL011 */ +#define CONFIG_PL01X_SERIAL + +/* USB configuration */ +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* SD/MMC */ +#define CONFIG_BOUNCE_BUFFER + +/***************************************************************************** + * Initial environment variables + *****************************************************************************/ + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#ifndef CONFIG_SPL_BUILD +#include +#include +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loader_mmc_blknum=0x0\0" \ + "loader_mmc_nblks=0x780\0" \ + "env_mmc_blknum=0xF0000\0" \ + "env_mmc_nblks=0x80\0" \ + "kernel_addr_r=0x30000000\0" \ + "pxefile_addr_r=0x32000000\0" \ + "scriptaddr=0x32000000\0" \ + "fdt_addr_r=0x32200000\0" \ + "ramdisk_addr_r=0x32400000\0" \ + BOOTENV + + +/* Command line configuration */ +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET 0xF0000 /* env_mmc_blknum */ +#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */ +#define CONFIG_CMD_ENV +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG + +/* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* _POPLAR_H_ */