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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id m2sm2620578pgu.85.2021.06.04.11.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:35:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Date: Fri, 4 Jun 2021 11:35:04 -0700 Message-Id: <20210604183506.916654-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604183506.916654-1-richard.henderson@linaro.org> References: <20210604183506.916654-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fprintf+assert has been in place since the beginning. It is prior to the fp_access_check, so we're still good to raise sigill here. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381 Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8713dfec17..2477b55c53 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13234,8 +13234,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x7f: /* FSQRT (vector) */ break; default: - fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); - g_assert_not_reached(); + unallocated_encoding(s); + return; } From patchwork Fri Jun 4 18:35:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 454154 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp663210jae; Fri, 4 Jun 2021 11:37:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy9IwENjKHylPvZQTgn+iyLLtPSYNor6BMaieoNlmu4SWIGHHMAm3rqwxGQ8BdWKiuLs7z0 X-Received: by 2002:a05:6e02:118c:: with SMTP id y12mr5008269ili.288.1622831867265; Fri, 04 Jun 2021 11:37:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622831867; cv=none; d=google.com; s=arc-20160816; b=Yo3x+5jHGnn0ZZqYRi7HrKRq3xMcKyxSXl3rLhsNqN642Mz2im6CucJ+tPXDD3HYU5 pAAvYjkjEFpKXO2jrkjvDhncvMrFTtfQgz3CTTSp/zoxCz/3Z4bT1PY4HagFQbxtp83w JznC7G6SOChp0kiHGZ2m0ydoC6lnfLeP4M4Iifdnv2dm6Aip9cRxDGnskCqOBhssMgKS yS8+uXfCF6SYSrI0yVnsc9/GgM6rWRDCxaddnelOU/rtzZnDbEdIZM4E8Qxbn44NjOkj m2YIh+sKeLHlN9jNzvrGqttVHARSFsJBdinnQBqnnfsOHK1x6Olm0BbX7z2lmgpnIasl uDrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ngf2a8fv1Pxh8onF7826WEkLyZRw0BsqH4cjJDshQJU=; b=jC2jPTxJdG/J01QsyC+ti0Lbpuoy5xbII35hr8FciO1cwc6huhZUE1cF/ZDwgT/+nH 7UWekiIWt6IRqf2ViGeLPGTxH7b10EyOkcvkEtOJDbrvT0/UY/gsFL57EVzCye1IDSxp Q611uDEI1btry5vZe403VM87QUTKoamkhDABBQwK1BavY2mP9D9to8c2AvjpBfMlQiAo lgLUXRKlGGxFDIZQef0WjijwWAbmBp7F2vP7VGaSgSw18igdVwiLVDOUuAgoVCDV5HtJ mbgcMC5pp1EySQ5wSnNUl9wgt4+BNC8wnDFmt1UpIiYkQWxbsOgRsjbB/6VOwdV37VbI vU6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BahkTYL1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id m2sm2620578pgu.85.2021.06.04.11.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:35:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: Remove fprintf from disas_simd_mod_imm Date: Fri, 4 Jun 2021 11:35:05 -0700 Message-Id: <20210604183506.916654-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604183506.916654-1-richard.henderson@linaro.org> References: <20210604183506.916654-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The default of this switch is truly unreachable. The switch selector is 3 bits, and all 8 cases are present. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2477b55c53..9bb15ca618 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -8291,7 +8291,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) } break; default: - fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); g_assert_not_reached(); } From patchwork Fri Jun 4 18:35:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 454152 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp661995jae; Fri, 4 Jun 2021 11:35:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxj3/z+ZKnOybi3sSU7kLIlv1w/lqOnadO3hHfDu+vGdm1klotDQ64tPRX/6w9QWV8Lr3sw X-Received: by 2002:a05:6638:12c1:: with SMTP id v1mr2207669jas.97.1622831753503; Fri, 04 Jun 2021 11:35:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622831753; cv=none; d=google.com; s=arc-20160816; b=QVUEZ5eShRnPyp87PKliKhSt543YzUW1+6amcrqhT1HTHNWT7NL/BBynZokobuW2Rz 2k0M15IbNYor1BcqNE9Kua5JNe6Mp+QclD+F0+HCDG95cAtqPF0x4pYZLRb+LVtz7aBk 4nxms2ZMtHKmVeQrAebSj6FCrY2TNnNWtdMY013fd/mirfKGSLHbSVze/Hct8myiv7gS ImSO+9IdYPIaLZi9CkDNcarkyX5V07kqY27tzi5QyGW6+Wpxsq+pZYU1gTxLqp6Nw1VP 7y/+VMWSOCErOt934zUJPgIKcQfC21t77Go2Ahbt4ZB2bv5SD9H3gdSIGRHJlS1/V5ON vdRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X+8qtmFFIjwvz+51Kl21uuhzPS5UApPgPi1mRnqjng8=; b=srnvphoymhEkRdXmSDX4Brn8ZfZxNCjp3ZXutUlatTyEKhbi/iHjaQp7Ztdoe7frDv oPqGZbAetxjM/WFpUCbqECuvQRmIWmLpvKA6U+g5DyXOQTpqCrFM8Xrx9MWtnuXbXJO8 NKBm2Km2RWPw2EJ8gG66iNib1Ea2ybVeKKdxgWWy/6xCYxU6LyCb5L5d/p6BIqb6fCk8 ZLu//ppReFXROTtlzPqUAksMRu44DRHarPWFUGuP1Bsqb7jab9IpQ96t6aq8QD4m1shg mClIVNRXCuP7KekHayEFdesuRUV6Jo94NXjHvUNZo7jbfDH3iHpFlFZfTxApTfYq/YHl Yj2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EkngAqwx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id m2sm2620578pgu.85.2021.06.04.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:35:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Date: Fri, 4 Jun 2021 11:35:06 -0700 Message-Id: <20210604183506.916654-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604183506.916654-1-richard.henderson@linaro.org> References: <20210604183506.916654-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fprintf+assert has been in place since the beginning. It is after to the fp_access_check, so we need to move the check up. Fold that in to the pairwise filter. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 82 +++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 32 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bb15ca618..7f74d0e81a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11989,12 +11989,57 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) */ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) { - int opcode, fpopcode; - int is_q, u, a, rm, rn, rd; - int datasize, elements; - int pass; + int opcode = extract32(insn, 11, 3); + int u = extract32(insn, 29, 1); + int a = extract32(insn, 23, 1); + int is_q = extract32(insn, 30, 1); + int rm = extract32(insn, 16, 5); + int rn = extract32(insn, 5, 5); + int rd = extract32(insn, 0, 5); + /* + * For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + int fpopcode = opcode | (a << 3) | (u << 4); + int datasize = is_q ? 128 : 64; + int elements = datasize / 16; + bool pairwise; TCGv_ptr fpst; - bool pairwise = false; + int pass; + + switch (fpopcode) { + case 0x0: /* FMAXNM */ + case 0x1: /* FMLA */ + case 0x2: /* FADD */ + case 0x3: /* FMULX */ + case 0x4: /* FCMEQ */ + case 0x6: /* FMAX */ + case 0x7: /* FRECPS */ + case 0x8: /* FMINNM */ + case 0x9: /* FMLS */ + case 0xa: /* FSUB */ + case 0xe: /* FMIN */ + case 0xf: /* FRSQRTS */ + case 0x13: /* FMUL */ + case 0x14: /* FCMGE */ + case 0x15: /* FACGE */ + case 0x17: /* FDIV */ + case 0x1a: /* FABD */ + case 0x1c: /* FCMGT */ + case 0x1d: /* FACGT */ + pairwise = false; + break; + case 0x10: /* FMAXNMP */ + case 0x12: /* FADDP */ + case 0x16: /* FMAXP */ + case 0x18: /* FMINNMP */ + case 0x1e: /* FMINP */ + pairwise = true; + break; + default: + unallocated_encoding(s); + return; + } if (!dc_isar_feature(aa64_fp16, s)) { unallocated_encoding(s); @@ -12005,31 +12050,6 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) return; } - /* For these floating point ops, the U, a and opcode bits - * together indicate the operation. - */ - opcode = extract32(insn, 11, 3); - u = extract32(insn, 29, 1); - a = extract32(insn, 23, 1); - is_q = extract32(insn, 30, 1); - rm = extract32(insn, 16, 5); - rn = extract32(insn, 5, 5); - rd = extract32(insn, 0, 5); - - fpopcode = opcode | (a << 3) | (u << 4); - datasize = is_q ? 128 : 64; - elements = datasize / 16; - - switch (fpopcode) { - case 0x10: /* FMAXNMP */ - case 0x12: /* FADDP */ - case 0x16: /* FMAXP */ - case 0x18: /* FMINNMP */ - case 0x1e: /* FMINP */ - pairwise = true; - break; - } - fpst = fpstatus_ptr(FPST_FPCR_F16); if (pairwise) { @@ -12152,8 +12172,6 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); break; default: - fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", - __func__, insn, fpopcode, s->pc_curr); g_assert_not_reached(); }