From patchwork Wed Jul 18 14:14:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142288 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594770ljj; Wed, 18 Jul 2018 07:17:00 -0700 (PDT) X-Google-Smtp-Source: AAOMgpegBz++bG8RaRX97ne8Sx+N3YGwx6Yg8dwpOgurbs1f/Q4VDpCJTjtj2cVpSrFg+2w8HA3F X-Received: by 2002:a62:a05:: with SMTP id s5-v6mr5361069pfi.147.1531923420515; Wed, 18 Jul 2018 07:17:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923420; cv=none; d=google.com; s=arc-20160816; b=FxcRxBpeq9BI2AmUq3CZiENjLEPIu8S7xlzTwMpM4n9DJgN+R6u98Jz4JyJj2uajIm pxaBG6PRJCqD6olNNCYkVdtxGq9Anh5TR/6sYDKKto1OFaXJSVx/QrwgDeNjn36UVz+h C5pMzD2g8/4eXGdMi6YeLidwdKe3w7jK/vniMjVnSzr/pxSMWb3neY+uBzsyIPTK+Bqk Us7lfEBowxDE3MzuLAGJnOKfMWwxrOuvX8sqQN0u18VqVrCiRR8awgA9z3YWhq9Kiw9w vQJuaE4fKFOJJV0PokK7SaPSG3Etl6vZ0wHwaNX2s3mp7+L37SmQsvAa0owaN6CuqMh2 CvJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/GPmg1Kl8k3s5K+o69nOxLlQCd1vHPI9xsxXkygilx8=; b=gihpnudV09WsUu5Pv2KsgupfeQlUCL5yNcBNwM4yvoEjFoxJaMje1NrsdLnHDuajGu HEFNLr4WCyfqC4X4t3QjQcfeoEi3jLG/QdmxQbqNoDHSQaSHGvrwUDWhKsu65qIS9iII Z6TZ6chOCvevn50oHdF1zJ0OnV6JTQf6myLjSIgusdM2Sd0kAF9kTybuvkWUHpqlHQnI +UCpjGjyyiDv6TYvI3qUS3DM2DUPSULivmgRpZFCwYqGr5e5s39T9ODfbMCg/qvRJ5f2 aXJ1ZHuZyD79R5DZSAK4hIsi1cbjUiZ9nQHnlruPUfFnDTs97X5Mp77ENrGKjtz/lh4C RdHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3-v6si3501710plh.34.2018.07.18.07.17.00; Wed, 18 Jul 2018 07:17:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731562AbeGROzF (ORCPT + 31 others); Wed, 18 Jul 2018 10:55:05 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9694 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730982AbeGROy1 (ORCPT ); Wed, 18 Jul 2018 10:54:27 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id EE7F3ADD7473F; Wed, 18 Jul 2018 22:16:03 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:55 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 2/9] scsi: hisi_sas: tidy channel interrupt handler for v3 hw Date: Wed, 18 Jul 2018 22:14:26 +0800 Message-ID: <1531923273-193768-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan The ISR of channel interrupt of v3 hw is a little long and messy. This patch tidies it by relocating CHL_INT1 and CHL_INT2 handling to new function separately. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 156 ++++++++++++++++----------------- 1 file changed, 78 insertions(+), 78 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 4b7688a..d7c3774 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1333,11 +1333,83 @@ static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) }, }; -static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) +static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { - struct hisi_hba *hisi_hba = p; + u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); struct device *dev = hisi_hba->dev; + int i; + + irq_value &= ~irq_msk; + if (!irq_value) + return; + + for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { + const struct hisi_sas_hw_error *error = &port_axi_error[i]; + + if (!(irq_value & error->irq_msk)) + continue; + + dev_err(dev, "%s error (phy%d 0x%x) found!\n", + error->msg, phy_no, irq_value); + queue_work(hisi_hba->wq, &hisi_hba->rst_work); + } + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); +} + +static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); + u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; struct pci_dev *pci_dev = hisi_hba->pci_dev; + struct device *dev = hisi_hba->dev; + + irq_value &= ~irq_msk; + if (!irq_value) + return; + + if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { + dev_warn(dev, "phy%d identify timeout\n", phy_no); + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); + } + + if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { + u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, + STP_LINK_TIMEOUT_STATE); + + dev_warn(dev, "phy%d stp link timeout (0x%x)\n", + phy_no, reg_value); + if (reg_value & BIT(4)) + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); + } + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); + + if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && + (pci_dev->revision == 0x20)) { + u32 reg_value; + int rc; + + rc = hisi_sas_read32_poll_timeout_atomic( + HILINK_ERR_DFX, reg_value, + !((reg_value >> 8) & BIT(phy_no)), + 1000, 10000); + if (rc) { + disable_phy_v3_hw(hisi_hba, phy_no); + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, + BIT(CHL_INT2_RX_INVLD_DW_OFF)); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); + mdelay(1); + enable_phy_v3_hw(hisi_hba, phy_no); + } + } +} + +static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) +{ + struct hisi_hba *hisi_hba = p; u32 irq_msk; int phy_no = 0; @@ -1347,84 +1419,12 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) while (irq_msk) { u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); - u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT1); - u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT2); - u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT1_MSK); - u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no, - CHL_INT2_MSK); - - irq_value1 &= ~irq_msk1; - irq_value2 &= ~irq_msk2; - - if ((irq_msk & (4 << (phy_no * 4))) && - irq_value1) { - int i; - - for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { - const struct hisi_sas_hw_error *error = - &port_axi_error[i]; - - if (!(irq_value1 & error->irq_msk)) - continue; - - dev_err(dev, "%s error (phy%d 0x%x) found!\n", - error->msg, phy_no, irq_value1); - queue_work(hisi_hba->wq, &hisi_hba->rst_work); - } - - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT1, irq_value1); - } - if (irq_msk & (8 << (phy_no * 4)) && irq_value2) { - struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; - - if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { - dev_warn(dev, "phy%d identify timeout\n", - phy_no); - hisi_sas_notify_phy_event(phy, - HISI_PHYE_LINK_RESET); - - } + if (irq_msk & (4 << (phy_no * 4))) + handle_chl_int1_v3_hw(hisi_hba, phy_no); - if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { - u32 reg_value = hisi_sas_phy_read32(hisi_hba, - phy_no, STP_LINK_TIMEOUT_STATE); - - dev_warn(dev, "phy%d stp link timeout (0x%x)\n", - phy_no, reg_value); - if (reg_value & BIT(4)) - hisi_sas_notify_phy_event(phy, - HISI_PHYE_LINK_RESET); - } - - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT2, irq_value2); - - if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && - (pci_dev->revision == 0x20)) { - u32 reg_value; - int rc; - - rc = hisi_sas_read32_poll_timeout_atomic( - HILINK_ERR_DFX, reg_value, - !((reg_value >> 8) & BIT(phy_no)), - 1000, 10000); - if (rc) { - disable_phy_v3_hw(hisi_hba, phy_no); - hisi_sas_phy_write32(hisi_hba, phy_no, - CHL_INT2, - BIT(CHL_INT2_RX_INVLD_DW_OFF)); - hisi_sas_phy_read32(hisi_hba, phy_no, - ERR_CNT_INVLD_DW); - mdelay(1); - enable_phy_v3_hw(hisi_hba, phy_no); - } - } - } + if (irq_msk & (8 << (phy_no * 4))) + handle_chl_int2_v3_hw(hisi_hba, phy_no); if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { hisi_sas_phy_write32(hisi_hba, phy_no, From patchwork Wed Jul 18 14:14:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142281 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594038ljj; Wed, 18 Jul 2018 07:16:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd3XLFageW3a4lszA9K1Wfm7YX4Gvvcoxh14HVEafU/P0Q1/TupNcrj+2IpHt8pGhFnu1Et X-Received: by 2002:a63:5055:: with SMTP id q21-v6mr5730979pgl.397.1531923383041; Wed, 18 Jul 2018 07:16:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923383; cv=none; d=google.com; s=arc-20160816; b=fD5VS0dYW0ul6rhdDkP8HQe/dlKYy3bK5ycWOBlFa+2o0aSJRyM7CyLbNDBxF4Q14e 61bAp6KgllEkpo2KqcUmxYrYeHy5M3LSl9lxupOGw1c694PF84n5wJv6mqW9hU7bNVul b/BhetgQUX9QB05kfQ6FgErngq1vwfgoUrU/reieFGoE0iJZMLvztSNwI7uODX4zZgPo e56K8cMXe7Inmq6wUj0nDVIUna7LCLHjONKYF89k7R0rUOc7bVC86T0xpOFpYpKb903q Udk96d/xVG18IPYQuIvn//ZaxodXrUz2l9+0i0mErIEpMkrhuhLtQqkfgH+tKBsUq/Bf iPuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id s11-v6si3182834plp.464.2018.07.18.07.16.22; Wed, 18 Jul 2018 07:16:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731262AbeGROy1 (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:27 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9695 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730869AbeGROy0 (ORCPT ); Wed, 18 Jul 2018 10:54:26 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 09F4353F9BD3E; Wed, 18 Jul 2018 22:16:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:56 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 3/9] scsi: hisi_sas: Fix the failure of recovering PHY from STP link timeout Date: Wed, 18 Jul 2018 22:14:27 +0800 Message-ID: <1531923273-193768-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan There is an issue that link reset can't recover PHY when STP link timeout. Because current process of enabling PHY for v3 hw will wait last transmission done. The time of one transmission depends IO size, disk model and so on. Normally, it should be shorter than 50ms. But the last transmission could be never done for some abnormal scenarios, such as STP link timeout. This patch is to fix the issue. Check PHY status after starting process of enabling PHY for 50ms. If the PHY is still active, we disable it forcibly by PHY reset. Of course, we need to clear the PHY reset bit when enable PHY. Besides, the function disable_phy_v3_hw() should not be suitable to call in interrupts for hilink bug for this 50ms delay. Then, we do link reset for hilink bug directly. The change is that we don't clear the invalid dword count register. This is better. Because we should not clear such error count while not saved. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index d7c3774..70a6aa2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -120,6 +120,8 @@ #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) #define PHY_CFG_DC_OPT_OFF 2 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) +#define PHY_CFG_PHY_RST_OFF 3 +#define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) #define PHY_CTRL (PORT_BASE + 0x14) #define PHY_CTRL_RESET_OFF 0 @@ -760,15 +762,25 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); cfg |= PHY_CFG_ENA_MSK; + cfg &= ~PHY_CFG_PHY_RST_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + u32 state; cfg &= ~PHY_CFG_ENA_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); + + mdelay(50); + + state = hisi_sas_read32(hisi_hba, PHY_STATE); + if (state & BIT(phy_no)) { + cfg |= PHY_CFG_PHY_RST_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); + } } static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) @@ -1385,8 +1397,6 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); } - hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); - if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && (pci_dev->revision == 0x20)) { u32 reg_value; @@ -1396,15 +1406,11 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) HILINK_ERR_DFX, reg_value, !((reg_value >> 8) & BIT(phy_no)), 1000, 10000); - if (rc) { - disable_phy_v3_hw(hisi_hba, phy_no); - hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, - BIT(CHL_INT2_RX_INVLD_DW_OFF)); - hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); - mdelay(1); - enable_phy_v3_hw(hisi_hba, phy_no); - } + if (rc) + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); } + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); } static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) From patchwork Wed Jul 18 14:14:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142283 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594179ljj; Wed, 18 Jul 2018 07:16:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeQX7w4UViOPR/OJWhyGMH86Qhmijk7vHPayIkTjOy3DzDXboImlxcOLZFnjYrByCx0RLIL X-Received: by 2002:a63:40c7:: with SMTP id n190-v6mr5983798pga.116.1531923388816; Wed, 18 Jul 2018 07:16:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923388; cv=none; d=google.com; s=arc-20160816; b=TDn6zH9ieBCn8SpARSZWzCLu53wrbyqsOjNt5O/hTd5ZcoRJT8GTrzeI6COvc+h3gK YJGPNTAunFaOOYfR6LMD/Ig4r4TtV265KYadThXMr2xxMSxL5dWGhub11yJqEvUrP4ev Wj6bKh8Q6tnkGTbHY/EIhek3eS27WqdPEWFVymMT0tTQ3jT0bI0mSomLQvqJQPplvDau DMYctfHb2ujC1kPeWUeVU9GAiZNiP9fi8CN43r08/HReou2tBrB745D14jhNHl8YIT0c 5XHwbItIyqJ2b83bp8bleYy0n/q4e1SgHRaFW6zjWsl2trG4PI7PkNMRfJN0vzsBTukX Kqug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=vgugLv0tvv97A+I98L7QWof4KST3s+YanhYNcyqNlQc=; b=qZlcSBxEOS1DUQFhnWchEYpKA6vI8taZK1KiUJafUse5fHeRqulS3N+lIJvI5Wj4DU 3Eg5DQ3DE5ZcPHU87TlwBuOvt4DGGevpILEaV2mSJcNyIipZXdtAtyiRWyKDC89SFqOu xGu8qj5gsrnBN+xi3EOFbtYNDaLSnwS4cVi9/S1pOkT3og9MSON7as40W5aRAkVZ/PQN rb09MOc8HDaH06SVkEBZKAyPgvYAsMW8tCDHWikcdNRFW37BTHBvmySz//JnPqPxxWrh gqjaUH2HFDj2lhRsfoh4b3T8tDmPHu7E+sB4dvGY51mC/ps/MzrW6RyVAu+vMZ3/Hyr9 QDWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a7-v6si3590736pfg.200.2018.07.18.07.16.28; Wed, 18 Jul 2018 07:16:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731379AbeGROyc (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:32 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9695 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731246AbeGROyb (ORCPT ); Wed, 18 Jul 2018 10:54:31 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 43CCBDFABF429; Wed, 18 Jul 2018 22:16:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:56 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 4/9] scsi: hisi_sas: tidy host controller reset function a bit Date: Wed, 18 Jul 2018 22:14:28 +0800 Message-ID: <1531923273-193768-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan This patch tidies host controller reset function by putting some code to two new functions, and exports these two functions out, so that they could be used by FLR feature to be realised. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 3 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 61 ++++++++++++++++++++++------------- 2 files changed, 42 insertions(+), 22 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 0ff9115..6c7d2e2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -320,6 +320,7 @@ struct hisi_hba { const struct hisi_sas_hw *hw; /* Low level hw interface */ unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)]; struct work_struct rst_work; + u32 phy_state; }; /* Generic HW DMA host memory structures */ @@ -480,4 +481,6 @@ extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy, enum hisi_sas_phy_event event); extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba); extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max); +extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba); +extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba); #endif diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index ed671af..b0bcd14 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1309,22 +1309,12 @@ static void hisi_sas_terminate_stp_reject(struct hisi_hba *hisi_hba) } } -static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) +void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba) { - struct device *dev = hisi_hba->dev; struct Scsi_Host *shost = hisi_hba->shost; - u32 old_state, state; - int rc; - - if (!hisi_hba->hw->soft_reset) - return -1; - - if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) - return -1; down(&hisi_hba->sem); - dev_info(dev, "controller resetting...\n"); - old_state = hisi_hba->hw->get_phys_state(hisi_hba); + hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba); scsi_block_requests(shost); hisi_hba->hw->wait_cmds_complete_timeout(hisi_hba, 100, 5000); @@ -1333,15 +1323,13 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) del_timer_sync(&hisi_hba->timer); set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); - rc = hisi_hba->hw->soft_reset(hisi_hba); - if (rc) { - dev_warn(dev, "controller reset failed (%d)\n", rc); - clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); - up(&hisi_hba->sem); - scsi_unblock_requests(shost); - clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); - return rc; - } +} +EXPORT_SYMBOL_GPL(hisi_sas_controller_reset_prepare); + +void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba) +{ + struct Scsi_Host *shost = hisi_hba->shost; + u32 state; /* Init and wait for PHYs to come up and all libsas event finished. */ hisi_hba->hw->phys_init(hisi_hba); @@ -1357,7 +1345,36 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); state = hisi_hba->hw->get_phys_state(hisi_hba); - hisi_sas_rescan_topology(hisi_hba, old_state, state); + hisi_sas_rescan_topology(hisi_hba, hisi_hba->phy_state, state); +} +EXPORT_SYMBOL_GPL(hisi_sas_controller_reset_done); + +static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) +{ + struct device *dev = hisi_hba->dev; + struct Scsi_Host *shost = hisi_hba->shost; + int rc; + + if (!hisi_hba->hw->soft_reset) + return -1; + + if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) + return -1; + + dev_info(dev, "controller resetting...\n"); + hisi_sas_controller_reset_prepare(hisi_hba); + + rc = hisi_hba->hw->soft_reset(hisi_hba); + if (rc) { + dev_warn(dev, "controller reset failed (%d)\n", rc); + clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); + up(&hisi_hba->sem); + scsi_unblock_requests(shost); + clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); + return rc; + } + + hisi_sas_controller_reset_done(hisi_hba); dev_info(dev, "controller reset complete\n"); return 0; From patchwork Wed Jul 18 14:14:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142289 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594890ljj; 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[209.132.180.67]) by mx.google.com with ESMTP id 73-v6si3635673pgh.343.2018.07.18.07.17.05; Wed, 18 Jul 2018 07:17:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731527AbeGROzE (ORCPT + 31 others); Wed, 18 Jul 2018 10:55:04 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9691 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731037AbeGROy1 (ORCPT ); Wed, 18 Jul 2018 10:54:27 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D19062DA4D696; Wed, 18 Jul 2018 22:16:03 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:56 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 5/9] scsi: hisi_sas: relocate some common code for v3 hw Date: Wed, 18 Jul 2018 22:14:29 +0800 Message-ID: <1531923273-193768-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan Much code of PM suspend function also exists in soft reset function. This is not concise. So, this patch relocates the common code of these two functions to a separate function. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 50 ++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 23 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 70a6aa2..3577843 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -210,6 +210,8 @@ #define AXI_MASTER_CFG_BASE (0x5000) #define AM_CTRL_GLOBAL (0x0) +#define AM_CTRL_SHUTDOWN_REQ_OFF 0 +#define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) #define AM_CURR_TRANS_RETURN (0x150) #define AM_CFG_MAX_TRANS (0x5010) @@ -1976,11 +1978,11 @@ static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) } -static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) +static int disable_host_v3_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; + u32 status, reg_val; int rc; - u32 status; interrupt_disable_v3_hw(hisi_hba); hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); @@ -1990,14 +1992,32 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) mdelay(10); - hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); + reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + + AM_CTRL_GLOBAL); + reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; + hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + + AM_CTRL_GLOBAL, reg_val); /* wait until bus idle */ rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100); if (rc) { - dev_err(dev, "axi bus is not idle, rc = %d\n", rc); + dev_err(dev, "axi bus is not idle, rc=%d\n", rc); + return rc; + } + + return 0; +} + +static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) +{ + struct device *dev = hisi_hba->dev; + int rc; + + rc = disable_host_v3_hw(hisi_hba); + if (rc) { + dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); return rc; } @@ -2456,9 +2476,8 @@ static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) struct hisi_hba *hisi_hba = sha->lldd_ha; struct device *dev = hisi_hba->dev; struct Scsi_Host *shost = hisi_hba->shost; - u32 device_state, status; + u32 device_state; int rc; - u32 reg_val; if (!pdev->pm_cap) { dev_err(dev, "PCI PM not supported\n"); @@ -2471,25 +2490,10 @@ static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) scsi_block_requests(shost); set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); flush_workqueue(hisi_hba->wq); - /* disable DQ/PHY/bus */ - interrupt_disable_v3_hw(hisi_hba); - hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); - hisi_sas_kill_tasklets(hisi_hba); - hisi_sas_stop_phys(hisi_hba); - - reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + - AM_CTRL_GLOBAL); - reg_val |= 0x1; - hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + - AM_CTRL_GLOBAL, reg_val); - - /* wait until bus idle */ - rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + - AM_CURR_TRANS_RETURN, status, - status == 0x3, 10, 100); + rc = disable_host_v3_hw(hisi_hba); if (rc) { - dev_err(dev, "axi bus is not idle, rc = %d\n", rc); + dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); scsi_unblock_requests(shost); From patchwork Wed Jul 18 14:14:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142285 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594445ljj; Wed, 18 Jul 2018 07:16:43 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeqo9G84iiov3Ao6ALIh3HD0+FSKE/gpjohVVKQepiKC6fbAlbbCDKz6vllAWPMxTdAr4Av X-Received: by 2002:a63:d916:: with SMTP id r22-v6mr5844900pgg.381.1531923403242; Wed, 18 Jul 2018 07:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923403; cv=none; d=google.com; s=arc-20160816; b=AHMJY+oAWV1Zs44Qt3KvA7PyBjyS9/iGX5VS6FBp8H6mxKZ1Mj7EykHiyKZf31ZGr2 aRYmkegBedWK4578jfcfxZMWfOmpCKLYmM/ritAgf9GB2VMoPfN77HpGOVdX4revZTAg F78EvEUHZFVXIbMq8Km1gooH9S+hor4CvPQZRgX7CULcnIarVfR1UquyqGWE7tvBeQbp tSNlBp7LPdiw6XOTYSBDH05aR3+tEY4pR1uyQKYn6EhPJVAVfPlEAI5Ny7O8bxR0Cso1 dXCeDfYaAhRkiXokvypYxgL8xJOxwEFp8Wo50eS4jVcyURTmdrIDujUADs3ZcP35keuZ 1KsQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id j61-v6si3351881plb.68.2018.07.18.07.16.42; Wed, 18 Jul 2018 07:16:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731473AbeGROyr (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:47 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9697 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730987AbeGROy3 (ORCPT ); Wed, 18 Jul 2018 10:54:29 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 272E06796FA1F; Wed, 18 Jul 2018 22:16:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:57 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 6/9] scsi: hisi_sas: Implement handlers of PCIe FLR for v3 hw Date: Wed, 18 Jul 2018 22:14:30 +0800 Message-ID: <1531923273-193768-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan This patch implements handlers of PCIe FLR for v3 hw, reset_prepare() and reset_done(). User can issue FLR through sysfs interface, as v3 hw support PCIe FLR. Then if we don't implement these two handlers, our SAS controller will not work after executing FLR. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 3577843..3d20fcf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -2465,6 +2465,41 @@ static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) return PCI_ERS_RESULT_DISCONNECT; } +static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) +{ + struct sas_ha_struct *sha = pci_get_drvdata(pdev); + struct hisi_hba *hisi_hba = sha->lldd_ha; + struct device *dev = hisi_hba->dev; + int rc; + + dev_info(dev, "FLR prepare\n"); + set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); + hisi_sas_controller_reset_prepare(hisi_hba); + + rc = disable_host_v3_hw(hisi_hba); + if (rc) + dev_err(dev, "FLR: disable host failed rc=%d\n", rc); +} + +static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) +{ + struct sas_ha_struct *sha = pci_get_drvdata(pdev); + struct hisi_hba *hisi_hba = sha->lldd_ha; + struct device *dev = hisi_hba->dev; + int rc; + + hisi_sas_init_mem(hisi_hba); + + rc = hw_init_v3_hw(hisi_hba); + if (rc) { + dev_err(dev, "FLR: hw init failed rc=%d\n", rc); + return; + } + + hisi_sas_controller_reset_done(hisi_hba); + dev_info(dev, "FLR done\n"); +} + enum { /* instances of the controller */ hip08, @@ -2556,6 +2591,8 @@ static int hisi_sas_v3_resume(struct pci_dev *pdev) .error_detected = hisi_sas_error_detected_v3_hw, .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, .slot_reset = hisi_sas_slot_reset_v3_hw, + .reset_prepare = hisi_sas_reset_prepare_v3_hw, + .reset_done = hisi_sas_reset_done_v3_hw, }; static struct pci_driver sas_v3_pci_driver = { From patchwork Wed Jul 18 14:14:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142280 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp593995ljj; Wed, 18 Jul 2018 07:16:20 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd/X6gv2JDxVdMWthSOdzNeTEZT3qMdR+i4KQncv44Q9OBR7R7UXLBPDnsPbl3fuPF2oYaq X-Received: by 2002:a65:4888:: with SMTP id n8-v6mr6073267pgs.149.1531923380530; Wed, 18 Jul 2018 07:16:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923380; cv=none; d=google.com; s=arc-20160816; b=M95Y9xXzdxhF2K5xRq5MwBybB+U+DZ0n2aDKZxMlXjqjgL2YHSnJ2ijR1H3fGXQE9b 3kjw35RHBff02QRg1/UCn7Cry2SClkEBRG4nCYJnYQRI3XGLK4xm1EoRfz9c1Axd+zze Q43PuNXD6Px1FEVOUFXsAvgMOvAS67cS6OZ7Fhh/9pdkLpqrj4jBHxPCZwlGcciB5MQs qBfrixQk0eagn7QjyRoobe73d+e//zGQFo09rC+MV9bMHFymFth/8rz3K0G3DoZvrsTg icQOYAMEvf/SaWpHdh+9Vqh4x3fLcKrXNhwr4H2hHfU8d2O+2UxOm3f2sjliMbo8U2lf vwDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=IKS5NREnjUkqhJghh+4agBaGCRtS9c4z9aGkXoq8nuQ=; b=yxffLQM05c2cIpTiMljwrxBoQbTR4Wb3pQchuERkRT8eQS3itFSPbzamfekH1khsxK IT6+YLBozyK8hv6u57Ndlq/BuyX5+Xn6j7q4uXIWtP6Z1rSl+gUhOykPj59eZQHnyytH IQuVD+BZylRYeeIVHBuharHGg/SDw7bs9ecbftPI2NIwECr6klOyr3KgGfO4/0Yp7r4m ILWwxB0bFleLNlzfL43wGy/M5xcjffATK5hWTrSQvmMzFEFf0DjNvAP6R2IgByEvzNdV GwqxUXYZtBAr8qmI7mUDdyGPpR7ZJIQHYLyySSzV6MfQMqgQPMUKzHSF0Y+wx0QnCg1S JW2g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 65-v6si3467581pld.451.2018.07.18.07.16.20; Wed, 18 Jul 2018 07:16:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731161AbeGROyZ (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:25 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9693 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727083AbeGROyY (ORCPT ); Wed, 18 Jul 2018 10:54:24 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id E03B06D0FE8C; Wed, 18 Jul 2018 22:16:03 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:57 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 7/9] scsi: hisi_sas: Tidy hisi_sas_task_prep() Date: Wed, 18 Jul 2018 22:14:31 +0800 Message-ID: <1531923273-193768-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen To decrease the usage of spinlock during delivery IO, relocate some code in hisi_sas_task_prep(). Also an invalid comment is removed. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index b0bcd14..432a38a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -296,8 +296,8 @@ static int hisi_sas_task_prep(struct sas_task *task, struct device *dev = hisi_hba->dev; int dlvry_queue_slot, dlvry_queue, rc, slot_idx; int n_elem = 0, n_elem_req = 0, n_elem_resp = 0; - unsigned long flags, flags_dq; struct hisi_sas_dq *dq; + unsigned long flags; int wr_q_index; if (!sas_port) { @@ -393,16 +393,17 @@ static int hisi_sas_task_prep(struct sas_task *task, slot = &hisi_hba->slot_info[slot_idx]; - spin_lock_irqsave(&dq->lock, flags_dq); + spin_lock_irqsave(&dq->lock, flags); wr_q_index = hisi_hba->hw->get_free_slot(hisi_hba, dq); if (wr_q_index < 0) { - spin_unlock_irqrestore(&dq->lock, flags_dq); + spin_unlock_irqrestore(&dq->lock, flags); rc = -EAGAIN; goto err_out_tag; } list_add_tail(&slot->delivery, &dq->list); - spin_unlock_irqrestore(&dq->lock, flags_dq); + list_add_tail(&slot->entry, &sas_dev->list); + spin_unlock_irqrestore(&dq->lock, flags); dlvry_queue = dq->id; dlvry_queue_slot = wr_q_index; @@ -440,9 +441,6 @@ static int hisi_sas_task_prep(struct sas_task *task, break; } - spin_lock_irqsave(&dq->lock, flags); - list_add_tail(&slot->entry, &sas_dev->list); - spin_unlock_irqrestore(&dq->lock, flags); spin_lock_irqsave(&task->task_state_lock, flags); task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); @@ -818,7 +816,6 @@ static void hisi_sas_do_release_task(struct hisi_hba *hisi_hba, struct sas_task hisi_sas_slot_task_free(hisi_hba, task, slot); } -/* hisi_hba.lock should be locked */ static void hisi_sas_release_task(struct hisi_hba *hisi_hba, struct domain_device *device) { From patchwork Wed Jul 18 14:14:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 142284 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp594223ljj; Wed, 18 Jul 2018 07:16:31 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcd2Z1eEnskUaC9F3bXes8a8Sl6vWRTsxJhgjL2RaGWxN+fzhaOzZxaYd4Hu3uKilt12t0g X-Received: by 2002:a62:cac5:: with SMTP id y66-v6mr5356007pfk.187.1531923391052; Wed, 18 Jul 2018 07:16:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531923391; cv=none; d=google.com; s=arc-20160816; b=E5K29buJnD/ybWl4o5wWD07SJ5yEhxRB8z+paIfGdqv8Tz9zEzDR2vcHMeWur4s+u1 qgCrC/n18n7V++t4PJD6u8PadEEiyMYJGzdIeUArodsmZqy79HadXA+cPDMLeqf+grNw 5XJjLP33hwonG549q3eaq3DIREtWybzArWX8HGJwc9unuM2529vI6ByxvjmQ8o4U4XQl hh6Y3TOtm2LqQAnoQU8OQ9cmQbah3NF3F+L/nq7ERsv4MDWykh3j8tUWsRUUfixfvZ3y dEwq/CtEHTlilCx6LkFC349hvX1tRgXjnXQWvJYKPwAOl0Nvy/+DymdVjgHsDdiAINvo dOPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=OE4k+14CEYXAP3hbmNPKWpXxRVbhSYT7UtfBIQV6gO0=; b=vfbwyJS9UoT9V8/wPVZgD+d6dsD55qAWKTag7EuyckDkDWcxemSMZdIjTiRvqArY26 B8xFIhxe3jl4Xpu1QH4rVFtX1xSgJXH0Q8j72GXTbx2yNeopfT//VrnvlpGJTzw4e23c Birla/wqTqUD6YNeUwrSD+gSQPzwDaYlctUdb0G5TNL6Mvu+98W6uzUd19mTdcPn7xRh d1Jv1CVwYal6eUhaM3wcWx3nXRETNn/4W/EQK31M2OZYMKVZ42PGwPaz0a1rZkKpz+yy C1wOrdTtsyCWwC2YAf2WfG3jzHVHcJYcXUdE2st5paXlE/kRnqIPXOSsgEE5zLQNZqOE dngw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si3310991plz.379.2018.07.18.07.16.30; Wed, 18 Jul 2018 07:16:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731438AbeGROyf (ORCPT + 31 others); Wed, 18 Jul 2018 10:54:35 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9698 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730869AbeGROye (ORCPT ); Wed, 18 Jul 2018 10:54:34 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3572F1F098290; Wed, 18 Jul 2018 22:16:04 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.382.0; Wed, 18 Jul 2018 22:15:58 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 9/9] scsi: hisi_sas: Add SATA FIS check for v3 hw Date: Wed, 18 Jul 2018 22:14:33 +0800 Message-ID: <1531923273-193768-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1531923273-193768-1-git-send-email-john.garry@huawei.com> References: <1531923273-193768-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add a check ERR bit of status to decide whether there is something wrong with initial register-D2H FIS. If error exist, PHY link reset the channel to restart OOB. Directly call work HISI_PHYE_LINK_RESET replacing disable_phy_vx_hw() and enable_phy_vx_hw(). Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 3 +-- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 5a3d6a7..9c5c5a6 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -3240,8 +3240,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p) if (fis->status & ATA_ERR) { dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no, fis->status); - disable_phy_v2_hw(hisi_hba, phy_no); - enable_phy_v2_hw(hisi_hba, phy_no); + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); res = IRQ_NONE; goto end; } diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 70e2299..08b503e2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1191,6 +1191,16 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); initial_fis = &hisi_hba->initial_fis[phy_no]; fis = &initial_fis->fis; + + /* check ERR bit of Status Register */ + if (fis->status & ATA_ERR) { + dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", + phy_no, fis->status); + hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); + res = IRQ_NONE; + goto end; + } + sas_phy->oob_mode = SATA_OOB_MODE; attached_sas_addr[0] = 0x50; attached_sas_addr[7] = phy_no;