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Tue, 1 Jun 2021 06:13:32 +0000 From: Jacky Bai To: linus.walleij@linaro.org, shawnguo@kernel.org, aisheng.dong@nxp.com, stefan@agner.ch, robh+dt@kernel.org Cc: linux-imx@nxp.com, festevam@gmail.com, kernel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding Date: Tue, 1 Jun 2021 14:23:37 +0800 Message-Id: <20210601062338.1969040-1-ping.bai@nxp.com> X-Mailer: git-send-email 2.26.2 X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:3:17::15) To DBBPR04MB7930.eurprd04.prod.outlook.com (2603:10a6:10:1ea::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:3:17::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; Tue, 1 Jun 2021 06:13:29 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f89975ad-8d7c-47d9-6739-08d924c461b7 X-MS-TrafficTypeDiagnostic: DB7PR04MB5241: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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The first 4 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8ULP Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_config_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc"; + reg = <0x298c0000 0x10000>; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = + <0x0138 0x08F0 0x4 0x3 0x3>, + <0x013C 0x08EC 0x4 0x3 0x3>; + }; + }; + +...