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Ferst" X-Patchwork-Id: 451419 Delivered-To: patch@linaro.org Received: by 2002:a02:c735:0:0:0:0:0 with SMTP id h21csp2098185jao; Tue, 1 Jun 2021 12:36:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFUVwZkwMwPofyMMUek9VDta4VeQZ8t3J9rEtdG0UF0YEWgllC32P4U6ovgycfjifP2VaW X-Received: by 2002:ab0:4950:: with SMTP id a16mr17716152uad.140.1622576169907; Tue, 01 Jun 2021 12:36:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622576169; cv=none; d=google.com; s=arc-20160816; b=iWvDxjYil8NIozB02DwUjxT13iT5I88iDzWXLtO3QgJvVtJx++CFehNF8YKGfkJLqr OruWyx1x2xSkMLGvz6n6R0gD4gYifMM7fIeVFoJANKOi7jB+BZkKx+jLQNAoJGlAGcCS C7IKNeIXdKVsX/9fjEVkHQ/T2ZN1uBscC4GRq3tEV+K0ZdncAP7fmlcISpWERaDEO3Ow W5SC0GmaQdBd9iPwj8f4DO8HbJucVK1qjXjv9YgbRq3uTYdWZmf0OQA7ZJDKr/5xN2aU Wtz5efdhSTt0zzsvbtS6MS+EdwiqzAusJSaYcJST7EHz/TKdIGUhN5gsMQ0M+VJtGcwe 4ztg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=lXUg0HMlO9ev+KJbZvX+0/gN7MlCeDySpBPHpNOcEWA=; b=F1nLooFcTAZqwFZnyyzrOSDAuM4U3rKqxQme+Xrjz6bvbYZkTC1Hm2Xlo7QCb/4j4M knPTBAp2nzjpWqkOZmJ30bcj+I//WE4FlDPiSKc3zH7X9ghmryxp2rDRXOrDJhF/nrQj chPfl6HJimi1c8Jr4XTagSf7qniFY5TMe30afvz+FcncT3l4MrQJSJ2SPNJQl+wCFGxO P0JGNHwrpUo/+BPBDShi/CHXjczDPWhPcyIaolFq8DvUeHhxw+6SDq3zEuqX0AhvpKI8 qKIVsiL3z0x5B21Y2A27yPmg8nAbZp9xpMO0xIG/ltzF5NtEpswSz/nn2wnGgM+1N9yF lbwg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a16si538840uap.228.2021.06.01.12.36.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:36:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:57368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABN-0001Mk-6h for patch@linaro.org; Tue, 01 Jun 2021 15:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loAB3-0001Lw-5K; Tue, 01 Jun 2021 15:35:49 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAB1-0002Jl-N1; Tue, 01 Jun 2021 15:35:48 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:40 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id CFF4580148C; Tue, 1 Jun 2021 16:35:39 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions Date: Tue, 1 Jun 2021 16:35:15 -0300 Message-Id: <20210601193528.2533031-2-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:40.0331 (UTC) FILETIME=[4DE60FB0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These will be used by the decodetree trans_* functions to early-exit when the instruction set is not enabled. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e16a2721e2..11fd3342a0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7664,6 +7664,32 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } +/* + * Helpers for trans_* functions to check for specific insns flags. + * Use token pasting to ensure that we use the proper flag with the + * proper variable. + */ +#define REQUIRE_INSNS_FLAGS(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ + return false; \ + } \ + } while (0) + +#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ + return false; \ + } \ + } while (0) + +/* Then special-case the check for 64-bit so that we elide code for ppc32. */ +#if TARGET_LONG_BITS == 32 +# define REQUIRE_64BIT(CTX) return false +#else +# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) +#endif + #include "translate/fp-impl.c.inc" #include "translate/vmx-impl.c.inc" From patchwork Tue Jun 1 19:35:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. Ferst" X-Patchwork-Id: 451420 Delivered-To: patch@linaro.org Received: by 2002:a02:c735:0:0:0:0:0 with SMTP id h21csp2098360jao; Tue, 1 Jun 2021 12:36:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSAx0u7sAZdYBgsRMll8dYNQiYc3ubtGsuux2tzQJ/TFVtY7eC7Vtly4kU/jSHlStJGaNq X-Received: by 2002:a67:2c09:: with SMTP id s9mr13153828vss.44.1622576173573; Tue, 01 Jun 2021 12:36:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622576173; cv=none; d=google.com; s=arc-20160816; b=UGiJvXtuLhqNtFGG1fGI+VfPkAeOyjgczMHNrBN9EV2THDBTPAu/Lt6c/iZDJwsHgL r73Objr8Ujrg+b2b6Vcsp8R91VWM0AZ4/mOfuQ5wKfx3TsgYDyTeQ299JuQWn9z52j0A gnLZ5b5LWqikte5T82FFx6UKrLOI74Nvd23HhyavO7yO2V1+Rae7fk9lC1W7eDrc8oHC HnaC0/viHozzVWLdUGXizcDPg+Pbmf9Stx/b5RoA6FMDRMLYEg9rSKG/oFYiOaEDWPvm luUWWI/4CV25XxM19sD+hkk7mOKmnDx11MXDI+K8nIxVpnJxr7grg+1eMZ34Cgw3WToc 4hrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=k+t/ZDyiETUTxOTsaNdKGCHu3bMxNu33K2rLtkN3n1I=; b=mrS99vjKIPJZuzPZ6DdN1usihhfSBxfKywJ4vGoNalGTksuQ3OQ1bZ9on4Su8fq0d9 SeO6CH5dSH1f9pa7rLFsf8nz+SFzBk3fvUpf3We98VyTDM6/pgX59/d6Fj3OrcsO9zlm 6s6Jovild8qP78dEjWQeqSwlIApKtVtl/my0K76zF03YVbI/KeJ+x39jtOZVxxR9pvmy u7En8E48HF3dMd6HESG67Q7iWgByspF31G6oP8va3MZUVWeG/9/l0B/QfffO6HHX0OOc B3DT5LCkK2JP/tC/8fWw2rQrraHJunPS3+lIW8lD7l1icEo6/eQYBy35AzZXlJf8tKxC blTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 34si4634498uap.261.2021.06.01.12.36.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:36:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:57506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABQ-0001Sg-TP for patch@linaro.org; Tue, 01 Jun 2021 15:36:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loAB5-0001Ph-MC; Tue, 01 Jun 2021 15:35:51 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAB4-0002Jl-6u; Tue, 01 Jun 2021 15:35:51 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:40 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 5596E80148B; Tue, 1 Jun 2021 16:35:40 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn Date: Tue, 1 Jun 2021 16:35:16 -0300 Message-Id: <20210601193528.2533031-3-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:40.0815 (UTC) FILETIME=[4E2FE9F0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson With prefixed instructions, the number of instructions remaining until the page crossing is no longer constant. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 11fd3342a0..d2c9fd9dd7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8821,9 +8821,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { ctx->base.max_insns = 1; - } else { - int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - ctx->base.max_insns = MIN(ctx->base.max_insns, bound); } } @@ -8874,6 +8871,12 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) gen_invalid(ctx); } + /* End the TB when crossing a page boundary. */ + if (ctx->base.is_jmp == DISAS_NEXT && + !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } + translator_loop_temp_check(&ctx->base); } From patchwork Tue Jun 1 19:35:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. Ferst" X-Patchwork-Id: 451422 Delivered-To: patch@linaro.org Received: by 2002:a02:c735:0:0:0:0:0 with SMTP id h21csp2101438jao; Tue, 1 Jun 2021 12:39:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIWyt87Qo9Q6KmcN+VujkF87GqjFd1elp9970ShJ94XWJEmR/5vWcNJFKfEvsy/4cU0fMV X-Received: by 2002:a05:6102:e08:: with SMTP id o8mr20400270vst.29.1622576388274; Tue, 01 Jun 2021 12:39:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622576388; cv=none; d=google.com; s=arc-20160816; b=bUJnzpnXjS82kMOJKcltQFIKodEEPZQev8OVb+uMRKmz4pFW7mhoLgnXgKswYY9bjt JLFI4LUT4Am4T/1U7w06VqRU9gVCD1KPKPQlsseDwbzEa6yZCvuHVvcWlr0axLgv+CC1 CRQCIgEfx1knAnTKbQd/3RmfT6Dk+n4SGKRHO5xm47H3H1xdeQ747u+t1/VnM003PVQA oWmHzcTuqtE+NONw8XiHgWntXYC5d44hOmHvqn/jjnT+XdZkIiYuoYPTb9FU5vaomy6r v1RonqJWlXOk+C4TYoEfdNw+YvOJA3nu/WDMyTkB00Uv2Ovd4EqwXTkB8ox1Hy3fH85P cCvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=J9Pxl+c+odjsiLYyr4ghGYieqmD4EvuSR/fL4fy7RFk=; b=yqP/bgCorQAH7RlWW7D6bzEWf+GqCwzZJtuLHDpMYefCmnpI+OBMZfNBpLEv7+ddsC 9ZTQwEkvvykVBDhA7Or7x+O9A2DYVzx4DSThP9tsPR6nEdW7vTfAJSzV6rCp+PqcMPCJ Vl76RT5XJgk5y1wNAXVw0SZCD1PazxuXbV+QVzxXOBn2B0El2A3h+IBJxbq8FBUm9j+3 yKN8yTdD+f4FU3wuzRVMkrMaA6wnKoCU2a6t+Q42SNSgerRhGcEUWQGIs2p2uhexcqoe It/8plZX1JERBnSrudEK6xf0rR7sYZ20U65QumWMDLxMi8sBHnC978Z9qPxb7dFln1Qp VqYw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x20si590083vso.293.2021.06.01.12.39.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:39:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAEt-0007sb-KI for patch@linaro.org; Tue, 01 Jun 2021 15:39:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loAB9-0001X7-OQ; Tue, 01 Jun 2021 15:35:55 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAB6-0002Jl-Ol; Tue, 01 Jun 2021 15:35:54 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:41 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id C65E080148C; Tue, 1 Jun 2021 16:35:40 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns Date: Tue, 1 Jun 2021 16:35:17 -0300 Message-Id: <20210601193528.2533031-4-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:41.0284 (UTC) FILETIME=[4E777A40:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Luis Pires Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/cpu.h | 1 + target/ppc/insn32.decode | 18 +++++++++++ target/ppc/insn64.decode | 18 +++++++++++ target/ppc/meson.build | 9 ++++++ target/ppc/translate.c | 37 ++++++++++++++++++---- target/ppc/translate/fixedpoint-impl.c.inc | 18 +++++++++++ 6 files changed, 95 insertions(+), 6 deletions(-) create mode 100644 target/ppc/insn32.decode create mode 100644 target/ppc/insn64.decode create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b0934d9be4..ad34c479ec 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -144,6 +144,7 @@ enum { POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ + POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */ /* Exception subtypes for POWERPC_EXCP_PROGRAM */ /* FP exceptions */ POWERPC_EXCP_FP = 0x10, diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode new file mode 100644 index 0000000000..a3a8ae06bf --- /dev/null +++ b/target/ppc/insn32.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 32-bit insns (opcode space 0) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode new file mode 100644 index 0000000000..a38b1f84dc --- /dev/null +++ b/target/ppc/insn64.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) +# +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a6a53a8d5c..a4f18ff414 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -20,6 +20,15 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( ppc_ss.add(libdecnumber) +gen = [ + decodetree.process('insn32.decode', + extra_args: '--static-decode=decode_insn32'), + decodetree.process('insn64.decode', + extra_args: ['--static-decode=decode_insn64', + '--insnwidth=64']), +] +ppc_ss.add(gen) + ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d2c9fd9dd7..f3f464c654 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7690,6 +7690,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif +#include "decode-insn32.c.inc" +#include "decode-insn64.c.inc" +#include "translate/fixedpoint-impl.c.inc" + #include "translate/fp-impl.c.inc" #include "translate/vmx-impl.c.inc" @@ -8850,11 +8854,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, return true; } +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + return opc1(insn) == 1; +} + static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = cs->env_ptr; + target_ulong pc; uint32_t insn; bool ok; @@ -8862,18 +8873,32 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); - ctx->cia = ctx->base.pc_next; - insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); - ctx->base.pc_next += 4; + ctx->cia = pc = ctx->base.pc_next; + insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; - ok = decode_legacy(cpu, ctx, insn); + if (!is_prefix_insn(ctx, insn)) { + ok = (decode_insn32(ctx, insn) || + decode_legacy(cpu, ctx, insn)); + } else if ((pc & 63) == 0) { + /* + * Power v3.1, section 1.9 Exceptions: + * attempt to execute a prefixed instruction that crosses a + * 64-byte address boundary (system alignment error). + */ + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); + ok = true; + } else { + uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; + ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); + } if (!ok) { gen_invalid(ctx); } /* End the TB when crossing a page boundary. */ - if (ctx->base.is_jmp == DISAS_NEXT && - !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) { + if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { ctx->base.is_jmp = DISAS_TOO_MANY; } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc new file mode 100644 index 0000000000..be75085cee --- /dev/null +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -0,0 +1,18 @@ +/* + * Power ISA decode for Fixed-Point Facility instructions + * + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ From patchwork Tue Jun 1 19:35:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. Ferst" X-Patchwork-Id: 451427 Delivered-To: patch@linaro.org Received: by 2002:a02:c735:0:0:0:0:0 with SMTP id h21csp2104562jao; Tue, 1 Jun 2021 12:43:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxPE92+pmpY++qAmca1cq5YNZO8LS2P4YKX28H/nmK78OrEViG8J0DNF580kax1IoMLnepy X-Received: by 2002:a05:6122:c8e:: with SMTP id ba14mr9716427vkb.6.1622576590351; Tue, 01 Jun 2021 12:43:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622576590; cv=none; d=google.com; s=arc-20160816; b=PSGTY7lKuYkVcpeHc1S6XEggh7cr2c5Z1+Y6qJtjHJBAItRCRoBrgLxmnSP5Q8MKTF IDk59Eed4Tgz06WQKgLNedEuAiPly6jdxyJYzhCm0J/UtznzP3TefeJIbFuTufielyBR dba1NSV6zZvPZ1PzADUXfrQx9+m22P8udgbuajqPVKOSsLqDGqjvFENLoYsrnnqyogYZ 1pVd3MW5PAO+v+MYl3lrRVKZBwDZd7SMlS8ksQoQ/g/n1dxxl3vZpUSG58PtW5vAgJPq 53q3LpEch/2VN90+6kW6KcZvvCmYy+sYw9V3dbuatVu8CnawjEbQ5QCyVUVS7oeXZeAq F4/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=NjoqE5Hz5YsBRMRggETgPIwZ0Nz681H/w4iN8rbajvY=; b=G+SGrh96mkUqObBZuUTpeH05/MEYcr14tjLvZrhXLNOfODth4SUefg3596NJBT1UrB kM9LI/IGDEMe0odM5NU/hhjbK3yPDHMuWtI5WKq9GlRD9iR60A2HYmEr+HkmXkOm++cA 33biFvnmwoxPF7lZemIGwcPwgwi6Iio5NGhtlrXWdMPgAjfl2APwZcbuLNmOIUsRYX/b l7BXzRQs6fSUA5PAeKxMgP+5QHNclcGbsUBGvy8YrkDfrMRFuoTMOvdj+N1LGk9Xixol wpvbBF5mkK9pbAQdF7G2PEH/DzfMjRGd5pMliQNNgsL+YYfylg2JUtO2BxEQZwzkw5+x fvDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x12si604900vsj.420.2021.06.01.12.43.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:43:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:48372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAI9-0005xs-Mo for patch@linaro.org; Tue, 01 Jun 2021 15:43:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABB-0001fe-My; Tue, 01 Jun 2021 15:35:57 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAB9-0002Jl-Pf; Tue, 01 Jun 2021 15:35:57 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:41 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 4D22A80148B; Tue, 1 Jun 2021 16:35:41 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Date: Tue, 1 Jun 2021 16:35:18 -0300 Message-Id: <20210601193528.2533031-5-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:41.0753 (UTC) FILETIME=[4EBF0A90:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 8 ++++ target/ppc/insn64.decode | 12 ++++++ target/ppc/translate.c | 29 -------------- target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a3a8ae06bf..e7c062d8b4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -16,3 +16,11 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&D rt ra si:int64_t +@D ...... rt:5 ra:5 si:s16 &D + +### Fixed-Point Arithmetic Instructions + +ADDI 001110 ..... ..... ................ @D +ADDIS 001111 ..... ..... ................ @D diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index a38b1f84dc..1965088915 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -16,3 +16,15 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +# Format MLS:D and 8LS:D +&PLS_D rt ra si:int64_t r:bool +%pls_si 32:s18 0:16 +@PLS_D ...... .. ... r:1 .. .................. \ + ...... rt:5 ra:5 ................ \ + &PLS_D si=%pls_si + +### Fixed-Point Arithmetic Instructions + +PADDI 000001 10 0--.-- .................. \ + 001110 ..... ..... ................ @PLS_D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f3f464c654..3012c7447a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1760,19 +1760,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); /* addze addze. addzeo addzeo.*/ GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) -/* addi */ -static void gen_addi(DisasContext *ctx) -{ - target_long simm = SIMM(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - /* li case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm); - } -} /* addic addic.*/ static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) { @@ -1792,20 +1779,6 @@ static void gen_addic_(DisasContext *ctx) gen_op_addic(ctx, 1); } -/* addis */ -static void gen_addis(DisasContext *ctx) -{ - target_long simm = SIMM(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - /* lis case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm << 16); - } -} - /* addpcis */ static void gen_addpcis(DisasContext *ctx) { @@ -7817,10 +7790,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), -GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index be75085cee..344a3ed54b 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -16,3 +16,47 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ + +/* + * Incorporate CIA into the constant when R=1. + * Validate that when R=1, RA=0. + */ +static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) +{ + d->rt = a->rt; + d->ra = a->ra; + d->si = a->si; + if (a->r) { + if (unlikely(a->ra != 0)) { + gen_invalid(ctx); + return false; + } + d->si += ctx->cia; + } + return true; +} + +static bool trans_ADDI(DisasContext *ctx, arg_D *a) +{ + if (a->ra) { + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); + } else { + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); + } + return true; +} + +static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a) +{ + arg_D d; + if (!resolve_PLS_D(ctx, &d, a)) { + return true; + } + return trans_ADDI(ctx, &d); +} + +static bool trans_ADDIS(DisasContext *ctx, arg_D *a) +{ + a->si <<= 16; + return trans_ADDI(ctx, a); +} From patchwork Tue Jun 1 19:35:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. 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[209.51.188.17]) by mx.google.com with ESMTPS id w22si3493025uam.190.2021.06.01.12.40.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:40:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:39440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAFA-0008Md-2k for patch@linaro.org; Tue, 01 Jun 2021 15:40:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABE-0001nM-Dw; Tue, 01 Jun 2021 15:36:00 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABC-0002Jl-PV; Tue, 01 Jun 2021 15:36:00 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:42 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id C0FFA80148B; Tue, 1 Jun 2021 16:35:41 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 05/14] target/ppc: Implement PNOP Date: Tue, 1 Jun 2021 16:35:19 -0300 Message-Id: <20210601193528.2533031-6-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:42.0252 (UTC) FILETIME=[4F0B2EC0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The illegal suffix behavior matches what was observed in a POWER10 DD2.0 machine. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 67 ++++++++++++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 11 ++++ 2 files changed, 78 insertions(+) -- 2.25.1 diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 1965088915..9aa5097a98 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -28,3 +28,70 @@ PADDI 000001 10 0--.-- .................. \ 001110 ..... ..... ................ @PLS_D + +### Prefixed No-operation Instruction + +@PNOP 000001 11 0000-- 000000000000000000 \ + ................................ + +{ + [ + ## Invalid suffixes: Branch instruction + # bc[l][a] + INVALID ................................ \ + 010000-------------------------- @PNOP + # b[l][a] + INVALID ................................ \ + 010010-------------------------- @PNOP + # bclr[l] + INVALID ................................ \ + 010011---------------0000010000- @PNOP + # bcctr[l] + INVALID ................................ \ + 010011---------------1000010000- @PNOP + # bctar[l] + INVALID ................................ \ + 010011---------------1000110000- @PNOP + + ## Invalid suffixes: rfebb + INVALID ................................ \ + 010011---------------0010010010- @PNOP + + ## Invalid suffixes: context synchronizing other than isync + # sc + INVALID ................................ \ + 010001------------------------1- @PNOP + # scv + INVALID ................................ \ + 010001------------------------01 @PNOP + # rfscv + INVALID ................................ \ + 010011---------------0001010010- @PNOP + # rfid + INVALID ................................ \ + 010011---------------0000010010- @PNOP + # hrfid + INVALID ................................ \ + 010011---------------0100010010- @PNOP + # urfid + INVALID ................................ \ + 010011---------------0100110010- @PNOP + # stop + INVALID ................................ \ + 010011---------------0101110010- @PNOP + # mtmsr w/ L=0 + INVALID ................................ \ + 011111---------0-----0010010010- @PNOP + # mtmsrd w/ L=0 + INVALID ................................ \ + 011111---------0-----0010110010- @PNOP + + ## Invalid suffixes: Service Processor Attention + INVALID ................................ \ + 000000----------------100000000- @PNOP + ] + + ## Valid suffixes + PNOP ................................ \ + -------------------------------- @PNOP +} diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 344a3ed54b..ce034a14a7 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -60,3 +60,14 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a) a->si <<= 16; return trans_ADDI(ctx, a); } + +static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a) +{ + gen_invalid(ctx); + return true; +} + +static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a) +{ + return true; +} From patchwork Tue Jun 1 19:35:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. Ferst" X-Patchwork-Id: 451421 Delivered-To: patch@linaro.org Received: by 2002:a02:c735:0:0:0:0:0 with SMTP id h21csp2098966jao; Tue, 1 Jun 2021 12:36:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIse74B6oqhRJEsvWccf35N3KarkDSnONgunhsCJTMAYORIdWumoLZGeup1ZfVPIJwfRYn X-Received: by 2002:a05:6402:44:: with SMTP id f4mr34669113edu.364.1622576195322; Tue, 01 Jun 2021 12:36:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622576195; cv=none; d=google.com; s=arc-20160816; b=zJ8U19EAVV0+ZQT/D9OuuFtZozNADXVJ8UvANrCbE0RGdK86v+/A8mvV06KEtWLUBK xTMclM6S4wmXW04pK8/+s3fA/mpNNDHO5nvOdPwuD2AKnnChdtoeYm99UyN8HDJtlvk/ rNekZ2Tpitj01dfOo4bk7yYXMaPTZT5mrvtawbm9rMCLdwoqGMUeQhRp4q8APgJ4pX0f Kt1WRMWtvYbSg/RuEXCheYxcZXjztamQjFqDPZzctnVAJ4mEaUZBAqrPdGDB/HZi4qOn XAtfm4uXCjcYGZZBXxyxDUZ6sUaSF+y2hW8z1/InTPabvTo3j7rrxtgdrxOVxIWyul1Q hxJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=Fd8yB8o0z7TvfMNl8d1KSPGrvTfMqdlPaf0X6MCyUTo=; b=I40VbWPbwOVt4ts/DZ5kXaRykE31QIVCtKvR6miZ7s9xAxcsSY8q897Lz9VUbDgWeU JL61Oqq1RnTzr40dnLm2fC62XJ4TDw1lBqk79ArGb3saLuNIOairlSKOwwb2VtfC0Plj fqF/YXPvhGiwhdt+6rfCsW/t9hNKR+oVd+OdaxKq06nLOFKAIna0U14+WHuuBqX4mmE/ 8BpD8roCc/OXVP6TPpa8egIkFe/i5IPW3UBUZkJvyfn4t5Lm/5YDwBf9/78Yn333lY8t nj/rBEDctUMXPLwjvx72IUA9LyvLXV0xilUwH7am+L7Q+SFypbtvioofSFIMfsFnDiV2 bb1w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g14si30048edu.359.2021.06.01.12.36.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:36:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:58264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABm-000202-6f for patch@linaro.org; Tue, 01 Jun 2021 15:36:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABH-0001w8-I2; Tue, 01 Jun 2021 15:36:03 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABF-0002Jl-Fw; Tue, 01 Jun 2021 15:36:03 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:42 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 4584C80148C; Tue, 1 Jun 2021 16:35:42 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree Date: Tue, 1 Jun 2021 16:35:20 -0300 Message-Id: <20210601193528.2533031-7-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:42.0753 (UTC) FILETIME=[4F57A110:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 37 ++++++ target/ppc/translate.c | 147 ++++----------------- target/ppc/translate/fixedpoint-impl.c.inc | 89 +++++++++++++ 3 files changed, 150 insertions(+), 123 deletions(-) -- 2.25.1 diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e7c062d8b4..70f64c235b 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -20,6 +20,43 @@ &D rt ra si:int64_t @D ...... rt:5 ra:5 si:s16 &D +%ds_si 2:s14 !function=times_4 +@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si + +&X rt ra rb +@X ...... rt:5 ra:5 rb:5 .......... . &X + +### Fixed-Point Load Instructions + +LBZ 100010 ..... ..... ................ @D +LBZU 100011 ..... ..... ................ @D +LBZX 011111 ..... ..... ..... 0001010111 - @X +LBZUX 011111 ..... ..... ..... 0001110111 - @X + +LHZ 101000 ..... ..... ................ @D +LHZU 101001 ..... ..... ................ @D +LHZX 011111 ..... ..... ..... 0100010111 - @X +LHZUX 011111 ..... ..... ..... 0100110111 - @X + +LHA 101010 ..... ..... ................ @D +LHAU 101011 ..... ..... ................ @D +LHAX 011111 ..... ..... ..... 0101010111 - @X +LHAXU 011111 ..... ..... ..... 0101110111 - @X + +LWZ 100000 ..... ..... ................ @D +LWZU 100001 ..... ..... ................ @D +LWZX 011111 ..... ..... ..... 0000010111 - @X +LWZUX 011111 ..... ..... ..... 0000110111 - @X + +LWA 111010 ..... ..... ..............10 @DS +LWAX 011111 ..... ..... ..... 0101010101 - @X +LWAUX 011111 ..... ..... ..... 0101110101 - @X + +LD 111010 ..... ..... ..............00 @DS +LDU 111010 ..... ..... ..............01 @DS +LDX 011111 ..... ..... ..... 0000010101 - @X +LDUX 011111 ..... ..... ..... 0000110101 - @X + ### Fixed-Point Arithmetic Instructions ADDI 001110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3012c7447a..d9238d1d10 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3323,54 +3323,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) #endif -#define GEN_LD(name, ldop, opc, type) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_LDU(name, ldop, opc, type) \ -static void glue(gen_, name##u)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0 || \ - rA(ctx->opcode) == rD(ctx->opcode))) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - if (type == PPC_64B) \ - gen_addr_imm_index(ctx, EA, 0x03); \ - else \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_LDUX(name, ldop, opc2, opc3, type) \ -static void glue(gen_, name##ux)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0 || \ - rA(ctx->opcode) == rD(ctx->opcode))) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ static void glue(gen_, name##x)(DisasContext *ctx) \ { \ @@ -3389,21 +3341,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) -#define GEN_LDS(name, ldop, op, type) \ -GEN_LD(name, ldop, op | 0x20, type); \ -GEN_LDU(name, ldop, op | 0x21, type); \ -GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ -GEN_LDX(name, ldop, 0x17, op | 0x00, type) - -/* lbz lbzu lbzux lbzx */ -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); -/* lha lhau lhaux lhax */ -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); -/* lhz lhzu lhzux lhzx */ -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); -/* lwz lwzu lwzux lwzx */ -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); - #define GEN_LDEPX(name, ldop, opc2, opc3) \ static void glue(gen_, name##epx)(DisasContext *ctx) \ { \ @@ -3424,47 +3361,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) #endif #if defined(TARGET_PPC64) -/* lwaux */ -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); -/* lwax */ -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); -/* ldux */ -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); -/* ldx */ -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); - /* CI load/store variants */ GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) -static void gen_ld(DisasContext *ctx) -{ - TCGv EA; - if (Rc(ctx->opcode)) { - if (unlikely(rA(ctx->opcode) == 0 || - rA(ctx->opcode) == rD(ctx->opcode))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - } - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_imm_index(ctx, EA, 0x03); - if (ctx->opcode & 0x02) { - /* lwa (lwau is undefined) */ - gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); - } else { - /* ld - ldu */ - gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); - } - if (Rc(ctx->opcode)) { - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); - } - tcg_temp_free(EA); -} - /* lq */ static void gen_lq(DisasContext *ctx) { @@ -7637,6 +7539,14 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } +/* + * Helpers for decodetree used by !function for decoding arguments. + */ +static int times_4(DisasContext *ctx, int x) +{ + return x * 4; +} + /* * Helpers for trans_* functions to check for specific insns flags. * Use token pasting to ensure that we use the proper flag with the @@ -7663,6 +7573,21 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif +/* + * Helpers for implementing sets of trans_* functions. + * Defer the implementation of NAME to FUNC, with optional extra arguments. + */ +#define TRANS(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { return FUNC(ctx, a, __VA_ARGS__); } + +#define TRANS64(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } + +/* TODO: More TRANS* helpers for extra insn_flags checks. */ + + #include "decode-insn32.c.inc" #include "decode-insn64.c.inc" #include "translate/fixedpoint-impl.c.inc" @@ -7847,7 +7772,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, PPC_NONE, PPC2_ISA300), #endif #if defined(TARGET_PPC64) -GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), #endif @@ -8213,34 +8137,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09), GEN_PPC64_R4(rldimi, 0x1E, 0x06), #endif -#undef GEN_LD -#undef GEN_LDU -#undef GEN_LDUX #undef GEN_LDX_E -#undef GEN_LDS -#define GEN_LD(name, ldop, opc, type) \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDU(name, ldop, opc, type) \ -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDUX(name, ldop, opc2, opc3, type) \ -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), -#define GEN_LDS(name, ldop, op, type) \ -GEN_LD(name, ldop, op | 0x20, type) \ -GEN_LDU(name, ldop, op | 0x21, type) \ -GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ -GEN_LDX(name, ldop, 0x17, op | 0x00, type) - -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) + #if defined(TARGET_PPC64) -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) /* HV/P7 and later only */ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index ce034a14a7..6140dd41ca 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -36,6 +36,95 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) return true; } +/* + * Fixed-Point Load/Store Instructions + */ + +static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update, + bool store, MemOp mop) +{ + TCGv ea; + + if (update && (ra == 0 || (!store && ra == rt))) { + gen_invalid(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + + ea = tcg_temp_new(); + if (ra) { + tcg_gen_add_tl(ea, cpu_gpr[ra], displ); + } else { + tcg_gen_mov_tl(ea, displ); + } + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(ea, ea); + } + mop ^= ctx->default_tcg_memop_mask; + if (store) { + tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop); + } else { + tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop); + } + if (update) { + tcg_gen_mov_tl(cpu_gpr[ra], ea); + } + tcg_temp_free(ea); + + return true; +} + +static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store, + MemOp mop) +{ + return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop); +} + +static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update, + bool store, MemOp mop) +{ + return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop); +} + +/* Load Byte and Zero */ +TRANS(LBZ, do_ldst_D, false, false, MO_UB) +TRANS(LBZX, do_ldst_X, false, false, MO_UB) +TRANS(LBZU, do_ldst_D, true, false, MO_UB) +TRANS(LBZUX, do_ldst_X, true, false, MO_UB) + +/* Load Halfword and Zero */ +TRANS(LHZ, do_ldst_D, false, false, MO_UW) +TRANS(LHZX, do_ldst_X, false, false, MO_UW) +TRANS(LHZU, do_ldst_D, true, false, MO_UW) +TRANS(LHZUX, do_ldst_X, true, false, MO_UW) + +/* Load Halfword Algebraic */ +TRANS(LHA, do_ldst_D, false, false, MO_SW) +TRANS(LHAX, do_ldst_X, false, false, MO_SW) +TRANS(LHAU, do_ldst_D, true, false, MO_SW) +TRANS(LHAXU, do_ldst_X, true, false, MO_SW) + +/* Load Word and Zero */ +TRANS(LWZ, do_ldst_D, false, false, MO_UL) +TRANS(LWZX, do_ldst_X, false, false, MO_UL) +TRANS(LWZU, do_ldst_D, true, false, MO_UL) +TRANS(LWZUX, do_ldst_X, true, false, MO_UL) + +/* Load Word Algebraic */ +TRANS64(LWA, do_ldst_D, false, false, MO_SL) +TRANS64(LWAX, do_ldst_X, false, false, MO_SL) +TRANS64(LWAUX, do_ldst_X, true, false, MO_SL) + +/* Load Doubleword */ +TRANS64(LD, do_ldst_D, false, false, MO_Q) +TRANS64(LDX, do_ldst_X, false, false, MO_Q) +TRANS64(LDU, do_ldst_D, true, false, MO_Q) +TRANS64(LDUX, do_ldst_X, true, false, MO_Q) + +/* + * Fixed-Point Arithmetic Instructions + */ + static bool trans_ADDI(DisasContext *ctx, arg_D *a) { if (a->ra) { From patchwork Tue Jun 1 19:35:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. 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[209.51.188.17]) by mx.google.com with ESMTPS id j23si2830667eje.501.2021.06.01.12.40.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:40:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:39398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAFA-0008LC-AU for patch@linaro.org; Tue, 01 Jun 2021 15:40:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABK-00023C-97; Tue, 01 Jun 2021 15:36:06 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABI-0002Jl-LH; Tue, 01 Jun 2021 15:36:06 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id BF2B980148B; Tue, 1 Jun 2021 16:35:42 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions Date: Tue, 1 Jun 2021 16:35:21 -0300 Message-Id: <20210601193528.2533031-8-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:43.0252 (UTC) FILETIME=[4FA3C540:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 15 +++++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++ 2 files changed, 31 insertions(+) -- 2.25.1 diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 9aa5097a98..547bd1736f 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -24,6 +24,21 @@ ...... rt:5 ra:5 ................ \ &PLS_D si=%pls_si +### Fixed-Point Load Instructions + +PLBZ 000001 10 0--.-- .................. \ + 100010 ..... ..... ................ @PLS_D +PLHZ 000001 10 0--.-- .................. \ + 101000 ..... ..... ................ @PLS_D +PLHA 000001 10 0--.-- .................. \ + 101010 ..... ..... ................ @PLS_D +PLWZ 000001 10 0--.-- .................. \ + 100000 ..... ..... ................ @PLS_D +PLWA 000001 00 0--.-- .................. \ + 101001 ..... ..... ................ @PLS_D +PLD 000001 00 0--.-- .................. \ + 111001 ..... ..... ................ @PLS_D + ### Fixed-Point Arithmetic Instructions PADDI 000001 10 0--.-- .................. \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 6140dd41ca..7687f31d6f 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store, return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop); } +static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update, + bool store, MemOp mop) +{ + arg_D d; + if (!resolve_PLS_D(ctx, &d, a)) { + return true; + } + return do_ldst_D(ctx, &d, update, store, mop); +} + static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update, bool store, MemOp mop) { @@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB) TRANS(LBZX, do_ldst_X, false, false, MO_UB) TRANS(LBZU, do_ldst_D, true, false, MO_UB) TRANS(LBZUX, do_ldst_X, true, false, MO_UB) +TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB) /* Load Halfword and Zero */ TRANS(LHZ, do_ldst_D, false, false, MO_UW) TRANS(LHZX, do_ldst_X, false, false, MO_UW) TRANS(LHZU, do_ldst_D, true, false, MO_UW) TRANS(LHZUX, do_ldst_X, true, false, MO_UW) +TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW) /* Load Halfword Algebraic */ TRANS(LHA, do_ldst_D, false, false, MO_SW) TRANS(LHAX, do_ldst_X, false, false, MO_SW) TRANS(LHAU, do_ldst_D, true, false, MO_SW) TRANS(LHAXU, do_ldst_X, true, false, MO_SW) +TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW) /* Load Word and Zero */ TRANS(LWZ, do_ldst_D, false, false, MO_UL) TRANS(LWZX, do_ldst_X, false, false, MO_UL) TRANS(LWZU, do_ldst_D, true, false, MO_UL) TRANS(LWZUX, do_ldst_X, true, false, MO_UL) +TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL) /* Load Word Algebraic */ TRANS64(LWA, do_ldst_D, false, false, MO_SL) TRANS64(LWAX, do_ldst_X, false, false, MO_SL) TRANS64(LWAUX, do_ldst_X, true, false, MO_SL) +TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL) /* Load Doubleword */ TRANS64(LD, do_ldst_D, false, false, MO_Q) TRANS64(LDX, do_ldst_X, false, false, MO_Q) TRANS64(LDU, do_ldst_D, true, false, MO_Q) TRANS64(LDUX, do_ldst_X, true, false, MO_Q) +TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q) /* * Fixed-Point Arithmetic Instructions From patchwork Tue Jun 1 19:35:22 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id e26si4334368uaf.208.2021.06.01.12.40.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 Jun 2021 12:40:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:39666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loAFE-0008Vc-4d for patch@linaro.org; Tue, 01 Jun 2021 15:40:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loABN-0002B4-4z; Tue, 01 Jun 2021 15:36:09 -0400 Received: from [201.28.113.2] (port=31942 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loABL-0002Jl-BT; Tue, 01 Jun 2021 15:36:08 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 43E4C80148C; Tue, 1 Jun 2021 16:35:43 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree Date: Tue, 1 Jun 2021 16:35:22 -0300 Message-Id: <20210601193528.2533031-9-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:43.0737 (UTC) FILETIME=[4FEDC690:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 22 ++++++ target/ppc/translate.c | 85 +--------------------- target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++ 3 files changed, 49 insertions(+), 82 deletions(-) -- 2.25.1 diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 70f64c235b..00ec0f4328 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS LDX 011111 ..... ..... ..... 0000010101 - @X LDUX 011111 ..... ..... ..... 0000110101 - @X +### Fixed-Point Store Instructions + +STB 100110 ..... ..... ................ @D +STBU 100111 ..... ..... ................ @D +STBX 011111 ..... ..... ..... 0011010111 - @X +STBUX 011111 ..... ..... ..... 0011110111 - @X + +STH 101100 ..... ..... ................ @D +STHU 101101 ..... ..... ................ @D +STHX 011111 ..... ..... ..... 0110010111 - @X +STHUX 011111 ..... ..... ..... 0110110111 - @X + +STW 100100 ..... ..... ................ @D +STWU 100101 ..... ..... ................ @D +STWX 011111 ..... ..... ..... 0010010111 - @X +STWUX 011111 ..... ..... ..... 0010110111 - @X + +STD 111110 ..... ..... ..............00 @DS +STDU 111110 ..... ..... ..............01 @DS +STDX 011111 ..... ..... ..... 0010010101 - @X +STDUX 011111 ..... ..... ..... 0010110101 - @X + ### Fixed-Point Arithmetic Instructions ADDI 001110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d9238d1d10..3c3cb1b664 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3299,7 +3299,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ } +#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) +#endif GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) @@ -3432,52 +3434,6 @@ static void gen_lq(DisasContext *ctx) #endif /*** Integer store ***/ -#define GEN_ST(name, stop, opc, type) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_STU(name, stop, opc, type) \ -static void glue(gen_, stop##u)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - if (type == PPC_64B) \ - gen_addr_imm_index(ctx, EA, 0x03); \ - else \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_STUX(name, stop, opc2, opc3, type) \ -static void glue(gen_, name##ux)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ static void glue(gen_, name##x)(DisasContext *ctx) \ { \ @@ -3495,19 +3451,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) -#define GEN_STS(name, stop, op, type) \ -GEN_ST(name, stop, op | 0x20, type); \ -GEN_STU(name, stop, op | 0x21, type); \ -GEN_STUX(name, stop, 0x17, op | 0x01, type); \ -GEN_STX(name, stop, 0x17, op | 0x00, type) - -/* stb stbu stbux stbx */ -GEN_STS(stb, st8, 0x06, PPC_INTEGER); -/* sth sthu sthux sthx */ -GEN_STS(sth, st16, 0x0C, PPC_INTEGER); -/* stw stwu stwux stwx */ -GEN_STS(stw, st32, 0x04, PPC_INTEGER); - #define GEN_STEPX(name, stop, opc2, opc3) \ static void glue(gen_, name##epx)(DisasContext *ctx) \ { \ @@ -3529,8 +3472,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) #endif #if defined(TARGET_PPC64) -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) @@ -8166,31 +8107,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) #endif -#undef GEN_ST -#undef GEN_STU -#undef GEN_STUX #undef GEN_STX_E -#undef GEN_STS -#define GEN_ST(name, stop, opc, type) \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STU(name, stop, opc, type) \ -GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STUX(name, stop, opc2, opc3, type) \ -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), -#define GEN_STS(name, stop, op, type) \ -GEN_ST(name, stop, op | 0x20, type) \ -GEN_STU(name, stop, op | 0x21, type) \ -GEN_STUX(name, stop, 0x17, op | 0x01, type) \ -GEN_STX(name, stop, 0x17, op | 0x00, type) - -GEN_STS(stb, st8, 0x06, PPC_INTEGER) -GEN_STS(sth, st16, 0x0C, PPC_INTEGER) -GEN_STS(stw, st32, 0x04, PPC_INTEGER) + #if defined(TARGET_PPC64) -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 7687f31d6f..adeee33289 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q) TRANS64(LDUX, do_ldst_X, true, false, MO_Q) TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q) +/* Store Byte */ +TRANS(STB, do_ldst_D, false, true, MO_UB) +TRANS(STBX, do_ldst_X, false, true, MO_UB) +TRANS(STBU, do_ldst_D, true, true, MO_UB) +TRANS(STBUX, do_ldst_X, true, true, MO_UB) + +/* Store Halfword */ +TRANS(STH, do_ldst_D, false, true, MO_UW) +TRANS(STHX, do_ldst_X, false, true, MO_UW) +TRANS(STHU, do_ldst_D, true, true, MO_UW) +TRANS(STHUX, do_ldst_X, true, true, MO_UW) + +/* Store Word */ +TRANS(STW, do_ldst_D, false, true, MO_UL) +TRANS(STWX, do_ldst_X, false, true, MO_UL) +TRANS(STWU, do_ldst_D, true, true, MO_UL) +TRANS(STWUX, do_ldst_X, true, true, MO_UL) + +/* Store Doubleword */ +TRANS64(STD, do_ldst_D, false, true, MO_Q) +TRANS64(STDX, do_ldst_X, false, true, MO_Q) +TRANS64(STDU, do_ldst_D, true, true, MO_Q) +TRANS64(STDUX, do_ldst_X, true, true, MO_Q) + /* * Fixed-Point Arithmetic Instructions */ From patchwork Tue Jun 1 19:35:23 2021 Content-Type: text/plain; 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Tue, 01 Jun 2021 15:36:11 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Tue, 1 Jun 2021 16:35:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id BC6D580148B; Tue, 1 Jun 2021 16:35:43 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions Date: Tue, 1 Jun 2021 16:35:23 -0300 Message-Id: <20210601193528.2533031-10-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> References: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 01 Jun 2021 19:35:44.0221 (UTC) FILETIME=[5037A0D0:01D7571D] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org, luis.pires@eldorado.org.br, lagarcia@br.ibm.com, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn64.decode | 12 ++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++ 2 files changed, 16 insertions(+) -- 2.25.1 diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 547bd1736f..72c5944a53 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \ PLD 000001 00 0--.-- .................. \ 111001 ..... ..... ................ @PLS_D +### Fixed-Point Store Instructions + +PSTW 000001 10 0--.-- .................. \ + 100100 ..... ..... ................ @PLS_D +PSTB 000001 10 0--.-- .................. \ + 100110 ..... ..... ................ @PLS_D +PSTH 000001 10 0--.-- .................. \ + 101100 ..... ..... ................ @PLS_D + +PSTD 000001 00 0--.-- .................. \ + 111101 ..... ..... ................ @PLS_D + ### Fixed-Point Arithmetic Instructions PADDI 000001 10 0--.-- .................. \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index adeee33289..2d2d874146 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB) TRANS(STBX, do_ldst_X, false, true, MO_UB) TRANS(STBU, do_ldst_D, true, true, MO_UB) TRANS(STBUX, do_ldst_X, true, true, MO_UB) +TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB) /* Store Halfword */ TRANS(STH, do_ldst_D, false, true, MO_UW) TRANS(STHX, do_ldst_X, false, true, MO_UW) TRANS(STHU, do_ldst_D, true, true, MO_UW) TRANS(STHUX, do_ldst_X, true, true, MO_UW) +TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW) /* Store Word */ TRANS(STW, do_ldst_D, false, true, MO_UL) TRANS(STWX, do_ldst_X, false, true, MO_UL) TRANS(STWU, do_ldst_D, true, true, MO_UL) TRANS(STWUX, do_ldst_X, true, true, MO_UL) +TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL) /* Store Doubleword */ TRANS64(STD, do_ldst_D, false, true, MO_Q) TRANS64(STDX, do_ldst_X, false, true, MO_Q) TRANS64(STDU, do_ldst_D, true, true, MO_Q) TRANS64(STDUX, do_ldst_X, true, true, MO_Q) +TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q) /* * Fixed-Point Arithmetic Instructions