From patchwork Mon May 31 18:17:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 450674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEB8BC47082 for ; Mon, 31 May 2021 18:18:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA1BD6124B for ; Mon, 31 May 2021 18:18:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231826AbhEaSUF (ORCPT ); Mon, 31 May 2021 14:20:05 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59198 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230288AbhEaSUE (ORCPT ); Mon, 31 May 2021 14:20:04 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14VII5v8078806; Mon, 31 May 2021 13:18:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622485085; bh=NTOU/toCq2bT4bwJWBm9sz5V4G6tb09L1YtZxu4df1w=; h=From:To:Subject:Date:In-Reply-To:References; b=M8BVz4Spe73DM6lVA8Yrj1Dvkot9+tnTBCG/vPisgOeXFryeKk668rThcJZUOXCFJ VCK0oW0iw+vMemW7NiNS4hjmaretM69tk06nuMrZ8N9UrG2mpCmdT3xzl0+oFS2FuA LVefCeJjlj/pt74KbE+B79dUkhp09bIeOZgswI+8= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14VII56g104242 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 31 May 2021 13:18:05 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 31 May 2021 13:18:05 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 31 May 2021 13:18:05 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14VIHwdG118543; Mon, 31 May 2021 13:18:02 -0500 From: Pratyush Yadav To: Tudor Ambarus , Michael Walle , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , , , Subject: [PATCH v2 1/6] mtd: spi-nor: core: use 2 data bytes for template ops Date: Mon, 31 May 2021 23:47:52 +0530 Message-ID: <20210531181757.19458-2-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210531181757.19458-1-p.yadav@ti.com> References: <20210531181757.19458-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The template ops used in spi_nor_spimem_check_pp() and spi_nor_spimem_check_readop() currently set the data phase to 1 byte long. This is problematic for 8D-8D-8D protocol where odd length data phase is invalid since one cycle transfers 2 bytes and odd number of bytes would mean half a cycle is left over. This could result in a controller rejecting the op as "not supported" even though it actually supports the protocol. Change the data length to 2 bytes in these templates. One might argue that this should only be done for 8D-8D-8D operations but when talking about these templates, there is no functional difference between one and two bytes, even in STR modes. Signed-off-by: Pratyush Yadav Reviewed-by: Michael Walle --- (no changes since v1) drivers/mtd/spi-nor/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f6a6ef2d8bd8..d521ca577884 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2143,7 +2143,7 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor, struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), SPI_MEM_OP_ADDR(3, 0, 0), SPI_MEM_OP_DUMMY(1, 0), - SPI_MEM_OP_DATA_IN(1, NULL, 0)); + SPI_MEM_OP_DATA_IN(2, NULL, 0)); spi_nor_spimem_setup_op(nor, &op, read->proto); @@ -2169,7 +2169,7 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor, struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), SPI_MEM_OP_ADDR(3, 0, 0), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, NULL, 0)); + SPI_MEM_OP_DATA_OUT(2, NULL, 0)); spi_nor_spimem_setup_op(nor, &op, pp->proto); From patchwork Mon May 31 18:17:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 450673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7ABEC47082 for ; Mon, 31 May 2021 18:18:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB8C76124B for ; Mon, 31 May 2021 18:18:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232062AbhEaSUI (ORCPT ); Mon, 31 May 2021 14:20:08 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59200 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230351AbhEaSUE (ORCPT ); Mon, 31 May 2021 14:20:04 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14VII83s078813; Mon, 31 May 2021 13:18:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622485088; bh=moH2ZY+xmI5k70xNoKzxtoVfAjiFgQzTAD/mpB3NYvw=; h=From:To:Subject:Date:In-Reply-To:References; b=PfRJmqmAUyqOuPK2Jt1RKEtjynUr3xOi3nROnR0HbgKbfM9XICfYv8yQ8gvV76PYi +3i8bj0pCJD9hoGwGoQVr+6tKhAPqWKWiL6yPeMibtRqmJQNvMwpxaYvY8SJPq+gCt QNr1PkLmA6sXlOnfdukvcFAmBe9oJ2gnEz4/EMI8= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14VII8Yo027498 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 31 May 2021 13:18:08 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 31 May 2021 13:18:08 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 31 May 2021 13:18:08 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14VIHwdH118543; Mon, 31 May 2021 13:18:05 -0500 From: Pratyush Yadav To: Tudor Ambarus , Michael Walle , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , , , Subject: [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode Date: Mon, 31 May 2021 23:47:53 +0530 Message-ID: <20210531181757.19458-3-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210531181757.19458-1-p.yadav@ti.com> References: <20210531181757.19458-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Octal DTR configuration is stored in the CFR5V register. This register is 1 byte wide. But 1 byte long transactions are not allowed in 8D-8D-8D mode. Since the next byte address does not contain any register, it is safe to write any value to it. Write a 0 to it. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/mtd/spi-nor/spansion.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index ee82dcd75310..e6bf5c9eee6a 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -65,10 +65,18 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable) if (ret) return ret; - if (enable) - *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; - else - *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + if (enable) { + buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + } else { + /* + * The register is 1-byte wide, but 1-byte transactions are not + * allowed in 8D-8D-8D mode. Since there is no register at the + * next location, just initialize the value to 0 and let the + * transaction go on. + */ + buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + buf[1] = 0; + } op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), @@ -76,7 +84,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable) SPINOR_REG_CYPRESS_CFR5V, 1), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); + SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); if (!enable) spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); From patchwork Mon May 31 18:17:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 450672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D727BC47080 for ; Mon, 31 May 2021 18:18:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B5458600EF for ; Mon, 31 May 2021 18:18:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232146AbhEaSUR (ORCPT ); Mon, 31 May 2021 14:20:17 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57546 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232116AbhEaSUP (ORCPT ); Mon, 31 May 2021 14:20:15 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14VIIESF129967; Mon, 31 May 2021 13:18:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622485095; bh=Fu8WvY6/rtLls9Y273CPvcnnzDx3DcNBfQsHz4ua8x8=; h=From:To:Subject:Date:In-Reply-To:References; b=xl/YcaysWm93KAdXX+ysTbABNSvUBkYAUTx9M1XhQyklygP9QPlvN8GrhKSC0LLpM 8mOHzG+ZuLtKLFmGZDMjBtc+K0X4+qwOkvLZOn1Mha4+5cZg65DfQL9tXcBUbQifer 29xftLSfXHsCZtvm6x5nEeamsTEQTabBzZSRHlJU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14VIIEJT027570 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 31 May 2021 13:18:14 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 31 May 2021 13:18:14 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 31 May 2021 13:18:14 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14VIHwdJ118543; Mon, 31 May 2021 13:18:12 -0500 From: Pratyush Yadav To: Tudor Ambarus , Michael Walle , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , , , Subject: [PATCH v2 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode Date: Mon, 31 May 2021 23:47:55 +0530 Message-ID: <20210531181757.19458-5-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210531181757.19458-1-p.yadav@ti.com> References: <20210531181757.19458-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In 8D-8D-8D mode two bytes are transferred per cycle. So an odd number of bytes cannot be transferred because it would leave a residual half cycle at the end. Consider such a transfer invalid and reject it. Signed-off-by: Pratyush Yadav Reviewed-by: Mark Brown --- Changes in v2: - Add Mark's R-by (spell corrected). drivers/spi/spi-mem.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 1513553e4080..ab9eefbaa1d9 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -162,7 +162,17 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, bool spi_mem_dtr_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->cmd.nbytes != 2) + if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2) + return false; + + if (op->addr.nbytes && op->addr.buswidth == 8 && op->addr.nbytes % 2) + return false; + + if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2) + return false; + + if (op->data.dir != SPI_MEM_NO_DATA && + op->dummy.buswidth == 8 && op->data.nbytes % 2) return false; return spi_mem_check_buswidth(mem, op);