From patchwork Thu May 27 16:12:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 449247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40FD5C4708B for ; Thu, 27 May 2021 16:14:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2735E613C5 for ; Thu, 27 May 2021 16:14:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237286AbhE0QP5 (ORCPT ); Thu, 27 May 2021 12:15:57 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:47556 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237219AbhE0QPA (ORCPT ); Thu, 27 May 2021 12:15:00 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14RGCErn027551; Thu, 27 May 2021 18:13:05 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=lhIzyMB3zCeRcGYJfgFXnoCQIPHUSlhrp5nHGanC4TA=; b=eU0svrHAYFpVKvArcV6Up8RWPbB6JNsnCe5W0dmYmC3ouIhfvT/mFAuQJl1wB64lhnzQ opmNqVZ1wBo14ddEEk8Kcjeh2Z3aHiQ1vmNpKYjV2rRHTXLDfSSsBl9JLpC1QQOEBB/k pnCjdzXhObwW9hBFf3D/hNinVLqxJjQkcN/qBL1yA6cXwB90QhjuwLBYLOQbQtUHulPk WaGALKkDRH7ccnxVSy3iaqtdYcZCtRB9Mz9FGzE4FaB9m9zOGXTPcOszwepKull1IXrE tCUkBz6tuu7/Uru9Kmc7cSlazAbZb7m6AoHjaOQ06qdWgDsyo1qsnfarCzIHovcG/OnC 6w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 38t0fr4ypg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 May 2021 18:13:05 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D8D65100034; Thu, 27 May 2021 18:13:03 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C99ED236566; Thu, 27 May 2021 18:13:03 +0200 (CEST) Received: from localhost (10.75.127.47) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 18:13:03 +0200 From: To: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , CC: , Subject: [PATCH v3 1/3] mtd: spinand: Add spinand_block_unlock() helper Date: Thu, 27 May 2021 18:12:50 +0200 Message-ID: <20210527161252.16620-2-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527161252.16620-1-patrice.chotard@foss.st.com> References: <20210527161252.16620-1-patrice.chotard@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-27_09:2021-05-27,2021-05-27 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Patrice Chotard Put code responsible of block unlocking in spinand_block_unlock(). This function will be needed by the future SPI-NAND resume ops. Signed-off-by: Patrice Chotard --- drivers/mtd/nand/spi/core.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 17f63f95f4a2..095742e5bc2b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1074,12 +1074,30 @@ static int spinand_detect(struct spinand_device *spinand) return 0; } +static int spinand_block_unlock(struct spinand_device *spinand) +{ + struct nand_device *nand = spinand_to_nand(spinand); + int ret = 0, i; + + for (i = 0; i < nand->memorg.ntargets; i++) { + ret = spinand_select_target(spinand, i); + if (ret) + return ret; + + ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); + if (ret) + return ret; + } + + return ret; +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev = &spinand->spimem->spi->dev; struct mtd_info *mtd = spinand_to_mtd(spinand); struct nand_device *nand = mtd_to_nanddev(mtd); - int ret, i; + int ret; /* * We need a scratch buffer because the spi_mem interface requires that @@ -1137,15 +1155,9 @@ static int spinand_init(struct spinand_device *spinand) } /* After power up, all blocks are locked, so unlock them here. */ - for (i = 0; i < nand->memorg.ntargets; i++) { - ret = spinand_select_target(spinand, i); - if (ret) - goto err_manuf_cleanup; - - ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); - if (ret) - goto err_manuf_cleanup; - } + ret = spinand_block_unlock(spinand); + if (ret) + goto err_manuf_cleanup; ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); if (ret) From patchwork Thu May 27 16:12:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 449248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF267C47089 for ; Thu, 27 May 2021 16:14:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D8EC6128B for ; Thu, 27 May 2021 16:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237278AbhE0QP4 (ORCPT ); Thu, 27 May 2021 12:15:56 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:18720 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237172AbhE0QPA (ORCPT ); Thu, 27 May 2021 12:15:00 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14RGD6SP000884; Thu, 27 May 2021 18:13:07 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=XodMrfCljA3jV/VNq/KtupAAUjvI0NBdv4/HUVQcJTY=; b=RCL1bwDNHnkkjAVsoVA2e7zuqA4nZaC21d96kcxY+zK9+Yt/QNMTrzN4atOXuXdRJMug azw0Eq8+QS9Ew3nqHsO5YHuMkbWa6brYmuLc5NZESxGn74Dz+OcH/dylPzGvKrIHsUyY HJstXAzysl5xolm1UecmlilBPheBfrQy+x3EkNtvOez6P6738LVHz1O+qHY3F8Kqirf7 F3I+2RFuhrrd1t6hMML3mKDfsIxYpQrZdp42KURW4pC3L+oox0wIyIt+6eS/nLgb22Fg 2gB/z63zRZAPWhmHFRQL90SiqtSczXIlp+uPYSGzKp8+yx2iDJqkAihkwkv/qY3IYmRQ kA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 38t7k3av0b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 May 2021 18:13:07 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 51025100039; Thu, 27 May 2021 18:13:05 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 424E9236565; Thu, 27 May 2021 18:13:05 +0200 (CEST) Received: from localhost (10.75.127.46) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 18:13:04 +0200 From: To: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , CC: , Subject: [PATCH v3 3/3] mtd: spinand: add SPI-NAND MTD resume handler Date: Thu, 27 May 2021 18:12:52 +0200 Message-ID: <20210527161252.16620-4-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527161252.16620-1-patrice.chotard@foss.st.com> References: <20210527161252.16620-1-patrice.chotard@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-27_09:2021-05-27,2021-05-27 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Patrice Chotard After power up, all SPI NAND's blocks are locked. Only read operations are allowed, write and erase operations are forbidden. The SPI NAND framework unlocks all the blocks during its initialization. During a standby low power, the memory is powered down, losing its configuration. During the resume, the QSPI driver state is restored but the SPI NAND framework does not reconfigured the memory. This patch adds SPI-NAND MTD PM handlers for resume ops. SPI NAND resume op re-initializes SPI NAND flash to its probed state. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard --- Changes in v3: - Add spinand_read_cfg() call to repopulate cache Changes in v2: - Add helper spinand_block_unlock(). - Add spinand_ecc_enable() call. - Remove some dev_err(). - Fix commit's title and message. drivers/mtd/nand/spi/core.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 1f699ad84f1b..e3fcbcf381c3 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1099,6 +1099,38 @@ static int spinand_block_unlock(struct spinand_device *spinand) return ret; } +static void spinand_mtd_resume(struct mtd_info *mtd) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + int ret; + + ret = spinand_reset_op(spinand); + if (ret) + return; + + ret = spinand_read_cfg(spinand); + if (ret) + return; + + ret = spinand_init_quad_enable(spinand); + if (ret) + return; + + ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); + if (ret) + return; + + ret = spinand_manufacturer_init(spinand); + if (ret) + return; + + ret = spinand_block_unlock(spinand); + if (ret) + return; + + spinand_ecc_enable(spinand, false); +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev = &spinand->spimem->spi->dev; @@ -1186,6 +1218,7 @@ static int spinand_init(struct spinand_device *spinand) mtd->_block_isreserved = spinand_mtd_block_isreserved; mtd->_erase = spinand_mtd_erase; mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; + mtd->_resume = spinand_mtd_resume; if (nand->ecc.engine) { ret = mtd_ooblayout_count_freebytes(mtd);