From patchwork Thu May 27 23:54:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 449197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EF42C47089 for ; Thu, 27 May 2021 23:54:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50783613D1 for ; Thu, 27 May 2021 23:54:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236662AbhE0Xz6 (ORCPT ); Thu, 27 May 2021 19:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236603AbhE0Xz4 (ORCPT ); Thu, 27 May 2021 19:55:56 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77747C061574; Thu, 27 May 2021 16:54:21 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id v5so3003371ljg.12; Thu, 27 May 2021 16:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i3Db6hbvHeZRlQz3yJZ5MPocVpsCmv5ymDT86VWu2zQ=; b=d1eBKOslTKyE2dqb+tm8wELc7sqTsXLvEStG91hCJJVU80pL+oCUHsGimmvvXSoRlk 2oSbwMmN0k46I7XXO/hJl5bacEw0uSyS5qric2iRO+JAxiHYrwJEPR9NzXvCrK0b2/pU 7N0OLlm43c4teZ+KxqY3EDICEj+GP6ZHVPSzWMRdv603Y5z3X+x7miSM/GCaxQPQvMby SHJYSiQHQ6TstXtSIISSLMkAEBou8bcMFc/EnW8g++M7lKE5UEdt5QwQu0MgjE6DTCcS janbllcc1UcGNiD+rG3+jwG7+wnEYu8bPxhNE/iKj+GWIKG4RkKgOU40P78ldK/1boAj 5FMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i3Db6hbvHeZRlQz3yJZ5MPocVpsCmv5ymDT86VWu2zQ=; b=hzPkFNE0xiuJ+1LVFYlSjVok0zkusdrUCHaPextlTD7poZmkHiuQcxSg6p+x+TySUG moxRuyL992vyl2H8/oHe09qZEjcpOsvo/K9mtTmDLX23yJOokPqxaf9BY8fNppAlmg11 ccV0T6GabiajwUi9joeqmnqaXiOPNYQN4WEdwf31rQZ/I13qP1QcZfWFzihxm5UGU15X DJSBq8ZvB4Yr4wpGuzWeUJcsQ31yhOME6PfbnLtU5tctHtmTqYdsfny1qMloA6s+XJ9m CWs6xy1C/FGK1B0c/8QZV8NBqsoTSGdZcwDYDACfJdpEcF7ZDqnrk98Nu49yDMA09jQS yg1w== X-Gm-Message-State: AOAM532WscqdWqpP4yIJpCOrqsYlAJHd6DnC0qbCMzHvufqual7SEzLL LZdmWQicWeYlt9HF3Fiq2eo= X-Google-Smtp-Source: ABdhPJxxTPcoO39qE3rFbQG7e7iOHcJXlRoz7fcEdGNTz2oBejv8blW+BjE0RNJXEsLiplR2aTBbEA== X-Received: by 2002:a2e:8e62:: with SMTP id t2mr4426224ljk.20.1622159659853; Thu, 27 May 2021 16:54:19 -0700 (PDT) Received: from localhost.localdomain (46-138-12-55.dynamic.spd-mgts.ru. [46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:19 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 02/14] soc/tegra: regulators: Bump voltages on system reboot Date: Fri, 28 May 2021 02:54:01 +0300 Message-Id: <20210527235413.23120-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Ensure that SoC voltages are at a level suitable for a system reboot. This is important for some devices that use CPU reset method for the rebooting. SoC CPU and core voltages now are be restored to a level that is suitable for rebooting. This patch fixes hang on reboot on Asus Transformer TF101, it was also reported as fixing some of reboot issues on Toshiba AC100. Reported-by: Nikola Milosavljević Tested-by: Nikola Milosavljević # TF101 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/regulators-tegra20.c | 75 +++++++++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 75 +++++++++++++++++++++++++- 2 files changed, 148 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 367a71a3cd10..3479be5ee494 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,7 +22,10 @@ struct tegra_regulator_coupler { struct regulator_dev *core_rdev; struct regulator_dev *cpu_rdev; struct regulator_dev *rtc_rdev; - int core_min_uV; + struct notifier_block reboot_notifier; + int core_min_uV, cpu_min_uV; + bool sys_reboot_mode_req; + bool sys_reboot_mode; }; static inline struct tegra_regulator_coupler * @@ -242,6 +246,10 @@ static int tegra20_cpu_voltage_update(struct tegra_regulator_coupler *tegra, if (cpu_uV < 0) return cpu_uV; + /* store boot voltage level */ + if (!tegra->cpu_min_uV) + tegra->cpu_min_uV = cpu_uV; + /* * CPU's regulator may not have any consumers, hence the voltage * must not be changed in that case because CPU simply won't @@ -250,6 +258,10 @@ static int tegra20_cpu_voltage_update(struct tegra_regulator_coupler *tegra, if (!cpu_min_uV_consumers) cpu_min_uV = cpu_uV; + /* restore boot voltage level */ + if (tegra->sys_reboot_mode) + cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV); + if (cpu_min_uV > cpu_uV) { err = tegra20_core_rtc_update(tegra, core_rdev, rtc_rdev, cpu_uV, cpu_min_uV); @@ -290,6 +302,8 @@ static int tegra20_regulator_balance_voltage(struct regulator_coupler *coupler, return -EINVAL; } + tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req); + if (rdev == cpu_rdev) return tegra20_cpu_voltage_update(tegra, cpu_rdev, core_rdev, rtc_rdev); @@ -303,6 +317,51 @@ static int tegra20_regulator_balance_voltage(struct regulator_coupler *coupler, return -EPERM; } +static int tegra20_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra, + bool sys_reboot_mode) +{ + int err; + + if (!tegra->core_rdev || !tegra->rtc_rdev || !tegra->cpu_rdev) + return 0; + + WRITE_ONCE(tegra->sys_reboot_mode_req, true); + + /* + * Some devices use CPU soft-reboot method and in this case we + * should ensure that voltages are sane for the reboot by restoring + * the minimum boot levels. + */ + err = regulator_sync_voltage_rdev(tegra->cpu_rdev); + if (err) + return err; + + err = regulator_sync_voltage_rdev(tegra->core_rdev); + if (err) + return err; + + WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode); + + return 0; +} + +static int tegra20_regulator_reboot(struct notifier_block *notifier, + unsigned long event, void *cmd) +{ + struct tegra_regulator_coupler *tegra; + int ret; + + if (event != SYS_RESTART) + return NOTIFY_DONE; + + tegra = container_of(notifier, struct tegra_regulator_coupler, + reboot_notifier); + + ret = tegra20_regulator_prepare_reboot(tegra, true); + + return notifier_from_errno(ret); +} + static int tegra20_regulator_attach(struct regulator_coupler *coupler, struct regulator_dev *rdev) { @@ -335,6 +394,14 @@ static int tegra20_regulator_detach(struct regulator_coupler *coupler, { struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler); + /* + * We don't expect regulators to be decoupled during reboot, + * this may race with the reboot handler and shouldn't ever + * happen in practice. + */ + if (WARN_ON_ONCE(system_state > SYSTEM_RUNNING)) + return -EPERM; + if (tegra->core_rdev == rdev) { tegra->core_rdev = NULL; return 0; @@ -359,13 +426,19 @@ static struct tegra_regulator_coupler tegra20_coupler = { .detach_regulator = tegra20_regulator_detach, .balance_voltage = tegra20_regulator_balance_voltage, }, + .reboot_notifier.notifier_call = tegra20_regulator_reboot, }; static int __init tegra_regulator_coupler_init(void) { + int err; + if (!of_machine_is_compatible("nvidia,tegra20")) return 0; + err = register_reboot_notifier(&tegra20_coupler.reboot_notifier); + WARN_ON(err); + return regulator_coupler_register(&tegra20_coupler.coupler); } arch_initcall(tegra_regulator_coupler_init); diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 0e776b20f625..18fe53d0a870 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,7 +23,10 @@ struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; struct regulator_dev *cpu_rdev; - int core_min_uV; + struct notifier_block reboot_notifier; + int core_min_uV, cpu_min_uV; + bool sys_reboot_mode_req; + bool sys_reboot_mode; }; static inline struct tegra_regulator_coupler * @@ -172,6 +176,10 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (cpu_uV < 0) return cpu_uV; + /* store boot voltage level */ + if (!tegra->cpu_min_uV) + tegra->cpu_min_uV = cpu_uV; + /* * CPU's regulator may not have any consumers, hence the voltage * must not be changed in that case because CPU simply won't @@ -195,6 +203,10 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (err) return err; + /* restore boot voltage level */ + if (tegra->sys_reboot_mode) + cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV); + if (core_min_limited_uV > core_uV) { pr_err("core voltage constraint violated: %d %d %d\n", core_uV, core_min_limited_uV, cpu_uV); @@ -263,9 +275,56 @@ static int tegra30_regulator_balance_voltage(struct regulator_coupler *coupler, return -EINVAL; } + tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req); + return tegra30_voltage_update(tegra, cpu_rdev, core_rdev); } +static int tegra30_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra, + bool sys_reboot_mode) +{ + int err; + + if (!tegra->core_rdev || !tegra->cpu_rdev) + return 0; + + WRITE_ONCE(tegra->sys_reboot_mode_req, true); + + /* + * Some devices use CPU soft-reboot method and in this case we + * should ensure that voltages are sane for the reboot by restoring + * the minimum boot levels. + */ + err = regulator_sync_voltage_rdev(tegra->cpu_rdev); + if (err) + return err; + + err = regulator_sync_voltage_rdev(tegra->core_rdev); + if (err) + return err; + + WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode); + + return 0; +} + +static int tegra30_regulator_reboot(struct notifier_block *notifier, + unsigned long event, void *cmd) +{ + struct tegra_regulator_coupler *tegra; + int ret; + + if (event != SYS_RESTART) + return NOTIFY_DONE; + + tegra = container_of(notifier, struct tegra_regulator_coupler, + reboot_notifier); + + ret = tegra30_regulator_prepare_reboot(tegra, true); + + return notifier_from_errno(ret); +} + static int tegra30_regulator_attach(struct regulator_coupler *coupler, struct regulator_dev *rdev) { @@ -292,6 +351,14 @@ static int tegra30_regulator_detach(struct regulator_coupler *coupler, { struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler); + /* + * We don't expect regulators to be decoupled during reboot, + * this may race with the reboot handler and shouldn't ever + * happen in practice. + */ + if (WARN_ON_ONCE(system_state > SYSTEM_RUNNING)) + return -EPERM; + if (tegra->core_rdev == rdev) { tegra->core_rdev = NULL; return 0; @@ -311,13 +378,19 @@ static struct tegra_regulator_coupler tegra30_coupler = { .detach_regulator = tegra30_regulator_detach, .balance_voltage = tegra30_regulator_balance_voltage, }, + .reboot_notifier.notifier_call = tegra30_regulator_reboot, }; static int __init tegra_regulator_coupler_init(void) { + int err; + if (!of_machine_is_compatible("nvidia,tegra30")) return 0; + err = register_reboot_notifier(&tegra30_coupler.reboot_notifier); + WARN_ON(err); + return regulator_coupler_register(&tegra30_coupler.coupler); } arch_initcall(tegra_regulator_coupler_init); From patchwork Thu May 27 23:54:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 449196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F7F6C47091 for ; Thu, 27 May 2021 23:54:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25E9E613BA for ; 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[46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:20 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 03/14] soc/tegra: Add stub for soc_is_tegra() Date: Fri, 28 May 2021 02:54:02 +0300 Message-Id: <20210527235413.23120-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add stub required for compile-testing of drivers. Signed-off-by: Dmitry Osipenko --- include/soc/tegra/common.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 98027a76ce3d..744280ecab5f 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,6 +6,15 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__ +#include + +#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +#else +static inline bool soc_is_tegra(void) +{ + return false; +} +#endif #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Thu May 27 23:54:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 449195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 079E3C4707F for ; Thu, 27 May 2021 23:54:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E02B6613F5 for ; Thu, 27 May 2021 23:54:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236802AbhE0X4M (ORCPT ); Thu, 27 May 2021 19:56:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236753AbhE0X4B (ORCPT ); Thu, 27 May 2021 19:56:01 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B91EC061574; Thu, 27 May 2021 16:54:25 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id q7so2638784lfr.6; Thu, 27 May 2021 16:54:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rnerspnEzqAlo5tFahbuBNU//nCYjRUznFzUAfdsm2c=; b=W9VQ2wIL8udELW+mjeEANbSp0NbMpqTcWd3zzQge3KVAPke1ePmuxSsBo+tjVfj6F7 Vcek1WDmZce7Nn1lbwxgU91PhSsILH3prUTmhkwBWYX7gOrFKmD8wJiq/1L2vBRde6ml YQrqRXoXw3ZB9uEISq28rVX3h9gmK10aw+fmd0pNEJguvf5t+miLyG1WXXqBEDUyrKgR EaWFhNaSeZCjq8HNvCsjjf8dT2pvLPiMzbhwPomdUjeBtQl4jV5wlxNa5ZzB8UFuETpf CgQc6zuygUW/CFMVTuoj7VZr3ZJqzn/DTvyVl3ON8GcUOdDK+QeCqd9P4gCEM5AMMW00 rKqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rnerspnEzqAlo5tFahbuBNU//nCYjRUznFzUAfdsm2c=; b=duCBvKpZO858+0sZ7Dc9kSbJS84f3ohFLwutzjAjfH8INmZ0moY3E3xiAG1lhnNjBz jbUBCEg2s9psYoXynukdlH1YdryuzEjg41WLJbLsPjbBj0qrz/k8whOBUAeD+s8L3Rxw CuFNtm+jsY6GSrseFH9fSbu0UvDRIVr/H22txZv7LdKW27lUj6jcitB+/gzthjAcVJls LanoRnrdhMXaJ78pIqWA285nKcA0FZIjsjwaZ1wbTPfTo2DFpIVL6C/Gu1KZlC3i+e2I fqTyR1QIpXCiAKJA7VTUAzdY2N2Go8A9Uk/l4YSmw081Y4DOH473ejoxVOOiYqdPiVUg CZsw== X-Gm-Message-State: AOAM5323vfeRYHl6pCbfjW7SmsFTeJgfY9AnEx7Em0EDbvQ6qbbKgcnb 5+lT8mNO6mlHyWssLMxrQf4= X-Google-Smtp-Source: ABdhPJx64pQjQFmCdpu3GQu/S6DWgFWLmvpLv1srmJm9lgnb8y6KEbK2MZdnrpljTJwOS7G1Hb6mBw== X-Received: by 2002:ac2:520a:: with SMTP id a10mr3975038lfl.180.1622159663729; Thu, 27 May 2021 16:54:23 -0700 (PDT) Received: from localhost.localdomain (46-138-12-55.dynamic.spd-mgts.ru. [46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:23 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 06/14] clk: tegra: Add stubs needed for compile-testing Date: Fri, 28 May 2021 02:54:05 +0300 Message-Id: <20210527235413.23120-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add stubs needed for compile-testing of Tegra memory drivers. Signed-off-by: Dmitry Osipenko --- include/linux/clk/tegra.h | 96 ++++++++++++++++++++++++++++++--------- 1 file changed, 75 insertions(+), 21 deletions(-) diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index f7ff722a03dd..9400f0554c60 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -123,20 +123,6 @@ static inline void tegra_cpu_clock_resume(void) } #endif -extern int tegra210_plle_hw_sequence_start(void); -extern bool tegra210_plle_hw_sequence_is_enabled(void); -extern void tegra210_xusb_pll_hw_control_enable(void); -extern void tegra210_xusb_pll_hw_sequence_start(void); -extern void tegra210_sata_pll_hw_control_enable(void); -extern void tegra210_sata_pll_hw_sequence_start(void); -extern void tegra210_set_sata_pll_seq_sw(bool state); -extern void tegra210_put_utmipll_in_iddq(void); -extern void tegra210_put_utmipll_out_iddq(void); -extern int tegra210_clk_handle_mbist_war(unsigned int id); -extern void tegra210_clk_emc_dll_enable(bool flag); -extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); -extern void tegra210_clk_emc_update_setting(u32 emc_src_value); - struct clk; struct tegra_emc; @@ -144,17 +130,10 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, unsigned long max_rate, void *arg); - -void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, - void *cb_arg); -int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); - typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, unsigned long rate); typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, unsigned long rate); -void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, - tegra124_emc_complete_timing_change_cb *complete_cb); struct tegra210_clk_emc_config { unsigned long rate; @@ -176,8 +155,83 @@ struct tegra210_clk_emc_provider { const struct tegra210_clk_emc_config *config); }; +#ifdef CONFIG_ARCH_TEGRA +void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, + void *cb_arg); +int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); + +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb); + +int tegra210_plle_hw_sequence_start(void); +bool tegra210_plle_hw_sequence_is_enabled(void); +void tegra210_xusb_pll_hw_control_enable(void); +void tegra210_xusb_pll_hw_sequence_start(void); +void tegra210_sata_pll_hw_control_enable(void); +void tegra210_sata_pll_hw_sequence_start(void); +void tegra210_set_sata_pll_seq_sw(bool state); +void tegra210_put_utmipll_in_iddq(void); +void tegra210_put_utmipll_out_iddq(void); +int tegra210_clk_handle_mbist_war(unsigned int id); +void tegra210_clk_emc_dll_enable(bool flag); +void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); +void tegra210_clk_emc_update_setting(u32 emc_src_value); + int tegra210_clk_emc_attach(struct clk *clk, struct tegra210_clk_emc_provider *provider); void tegra210_clk_emc_detach(struct clk *clk); +#else +static inline void +tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, + void *cb_arg) +{ +} + +static inline int +tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) +{ + return 0; +} + +static inline void +tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) +{ +} + +static inline int tegra210_plle_hw_sequence_start(void) +{ + return 0; +} + +static inline bool tegra210_plle_hw_sequence_is_enabled(void) +{ + return false; +} + +static inline int tegra210_clk_handle_mbist_war(unsigned int id) +{ + return 0; +} + +static inline int +tegra210_clk_emc_attach(struct clk *clk, + struct tegra210_clk_emc_provider *provider) +{ + return 0; +} + +static inline void tegra210_xusb_pll_hw_control_enable(void) {} +static inline void tegra210_xusb_pll_hw_sequence_start(void) {} +static inline void tegra210_sata_pll_hw_control_enable(void) {} +static inline void tegra210_sata_pll_hw_sequence_start(void) {} +static inline void tegra210_set_sata_pll_seq_sw(bool state) {} +static inline void tegra210_put_utmipll_in_iddq(void) {} +static inline void tegra210_put_utmipll_out_iddq(void) {} +static inline void tegra210_clk_emc_dll_enable(bool flag) {} +static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {} +static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {} +static inline void tegra210_clk_emc_detach(struct clk *clk) {} +#endif #endif /* __LINUX_CLK_TEGRA_H_ */ From patchwork Thu May 27 23:54:07 2021 Content-Type: text/plain; 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[46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:25 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 08/14] memory: tegra: Enable compile testing for all drivers Date: Fri, 28 May 2021 02:54:07 +0300 Message-Id: <20210527235413.23120-9-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable compile testing for all Tegra memory drivers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index a70967a56e52..71bba2345bce 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -2,16 +2,18 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y - depends on ARCH_TEGRA + depends on ARCH_TEGRA || (COMPILE_TEST && COMMON_CLK) select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. +if TEGRA_MC + config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST select DEVFREQ_GOV_SIMPLE_ONDEMAND select PM_DEVFREQ help @@ -23,7 +25,7 @@ config TEGRA20_EMC config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST select PM_OPP help This driver is for the External Memory Controller (EMC) found on @@ -34,8 +36,8 @@ config TEGRA30_EMC config TEGRA124_EMC tristate "NVIDIA Tegra124 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_124_SOC - select TEGRA124_CLK_EMC + depends on ARCH_TEGRA_124_SOC || COMPILE_TEST + select TEGRA124_CLK_EMC if ARCH_TEGRA select PM_OPP help This driver is for the External Memory Controller (EMC) found on @@ -49,10 +51,12 @@ config TEGRA210_EMC_TABLE config TEGRA210_EMC tristate "NVIDIA Tegra210 External Memory Controller driver" - depends on TEGRA_MC && ARCH_TEGRA_210_SOC + depends on ARCH_TEGRA_210_SOC || COMPILE_TEST select TEGRA210_EMC_TABLE help This driver is for the External Memory Controller (EMC) found on Tegra210 chips. The EMC controls the external DRAM on the board. This driver is required to change memory timings / clock rate for external memory. + +endif From patchwork Thu May 27 23:54:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 449193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6F5BC47090 for ; Thu, 27 May 2021 23:54:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6757613D4 for ; Thu, 27 May 2021 23:54:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236880AbhE0X4V (ORCPT ); Thu, 27 May 2021 19:56:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236758AbhE0X4M (ORCPT ); Thu, 27 May 2021 19:56:12 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FBEFC061343; Thu, 27 May 2021 16:54:30 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id i9so2580076lfe.13; Thu, 27 May 2021 16:54:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NrCxAlPUucoEt+gGLLTmwPl8GAwFzF+H/pcyQba15ag=; b=jn8q6M74Aum7oOl5gO6NuflqDNTgVvEfxsU/MPXrBns79VMVx2shzWP08sdWAKBcb0 tMAS2cYdK7C7gxs8ebar7Cx+SWHHK1IZiqG1jnFF7B6moOUATpvB9LN8BE5Ab0BmRnW3 gMrXDm4CWVOtHjzQ+4jWv69KjNcw/zjbxqWRk5VnJUD3TWafFDFXqWQreBY1DSMTnzuW SiDOTLqqxGhITmNxf/ptBnH9FjsL/2dMz9LAy+ptoEQd/vjenOXwQTFO0HX9VlxQywlT xWymIe84+TE5OCT2xmJl6nwWbAjv7klcKt+oj6ol219MMMkFayMJoXKXJ/iw4U5bk7Ql lYAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NrCxAlPUucoEt+gGLLTmwPl8GAwFzF+H/pcyQba15ag=; b=GKxTRFGmdUWqexrF07hm7cNFzW+6ze7X6h7ou1wrCfbnms5csKmEHwLeDORtLUu/RB 745IWd46F/GPQwS9DCHU1OIJP8/zY+UxNmEURh3GfwDSJ/tgvhXkHhK+jqGsCngXAblq 5h4+af2+oFqYDSgBA+iiHQx89UKiPxedii7W3i6v3pUgpjEqeJSigcipCtd1N4y5woSs G5P7H37zWWRuLx1yvgM1eguH6CggbyDfY59mZjyCVY+rsDCSs490uw1IR9KNV/EbaP15 XEVEL04PFT+vnSNTbR4bsbfwRswZRUWZ6SVxhajfJdykRRw7DY9Myf0CjFww/NLVZj3s t1tA== X-Gm-Message-State: AOAM533EJuhZWT+81qoI1uA2UYkOJE1RzbUMbHcLyoEyp+XI0UFFtOJP aq4a5mDOB34/kOne9pzyPRQ= X-Google-Smtp-Source: ABdhPJyQE8q4cgpfVKMvIKWpEjH6pj+T8w4vBUPMWPUwUWrrYhb6b8TI5pR36dPs7JttCDS9WE/XSg== X-Received: by 2002:a19:8609:: with SMTP id i9mr3957774lfd.72.1622159668572; Thu, 27 May 2021 16:54:28 -0700 (PDT) Received: from localhost.localdomain (46-138-12-55.dynamic.spd-mgts.ru. [46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:28 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 11/14] dt-bindings: soc: tegra-pmc: Document core power domain Date: Fri, 28 May 2021 02:54:10 +0300 Message-Id: <20210527235413.23120-12-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Document the new core power domain properties. Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 43fd2f8927d0..0afec83cc723 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -301,6 +301,33 @@ patternProperties: additionalProperties: false + core-domain: + type: object + description: | + The vast majority of hardware blocks of Tegra SoC belong to a + Core power domain, which has a dedicated voltage rail that powers + the blocks. + + properties: + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + required: - compatible - reg @@ -325,6 +352,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x7000e400 0x400>; + core-supply = <®ulator>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; @@ -338,17 +366,24 @@ examples: nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; resets = <&tegra_car 198>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; }; From patchwork Thu May 27 23:54:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 449192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6629BC47091 for ; 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[46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:30 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 13/14] soc/tegra: pmc: Add driver state syncing Date: Fri, 28 May 2021 02:54:12 +0300 Message-Id: <20210527235413.23120-14-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add driver state syncing that is invoked once all PMC consumers are attached and ready. The consumers are the power domain clients. The synchronization callback is invoked once all client drivers are probed, the driver core handles this for us. This callback informs PMC driver that all voltage votes are initialized by each PD client and it's safe to begin voltage scaling of the core power domain. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 23 +++++++++++++++++++++++ include/soc/tegra/pmc.h | 7 +++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 62f0f928658d..e8e5636f01f8 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -429,6 +429,8 @@ struct tegra_pmc { struct irq_chip irq; struct notifier_block clk_nb; + + bool core_domain_state_synced; }; static struct tegra_pmc *pmc = &(struct tegra_pmc) { @@ -1303,6 +1305,11 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) return err; } +bool tegra_pmc_core_domain_state_synced(void) +{ + return pmc->core_domain_state_synced; +} + static int tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, unsigned int level) @@ -3792,6 +3799,21 @@ static const struct of_device_id tegra_pmc_match[] = { { } }; +static void tegra_pmc_sync_state(struct device *dev) +{ + int err; + + pmc->core_domain_state_synced = true; + + /* this is a no-op if core regulator isn't used */ + mutex_lock(&pmc->powergates_lock); + err = dev_pm_opp_sync_regulators(dev); + mutex_unlock(&pmc->powergates_lock); + + if (err) + dev_err(dev, "failed to sync regulators: %d\n", err); +} + static struct platform_driver tegra_pmc_driver = { .driver = { .name = "tegra-pmc", @@ -3800,6 +3822,7 @@ static struct platform_driver tegra_pmc_driver = { #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, #endif + .sync_state = tegra_pmc_sync_state, }, .probe = tegra_pmc_probe, }; diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 361cb64246f7..d186bccd125d 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -171,6 +171,8 @@ int tegra_io_rail_power_off(unsigned int id); void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode); +bool tegra_pmc_core_domain_state_synced(void); + #else static inline int tegra_powergate_power_on(unsigned int id) { @@ -227,6 +229,11 @@ static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) { } +static inline bool tegra_pmc_core_domain_state_synced(void) +{ + return false; +} + #endif /* CONFIG_SOC_TEGRA_PMC */ #if defined(CONFIG_SOC_TEGRA_PMC) && defined(CONFIG_PM_SLEEP) From patchwork Thu May 27 23:54:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 449191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CF36C4708C for ; Thu, 27 May 2021 23:55:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A7D461178 for ; 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[46.138.12.55]) by smtp.gmail.com with ESMTPSA id t129sm319000lff.109.2021.05.27.16.54.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 16:54:31 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v5 14/14] soc/tegra: regulators: Support core domain state syncing Date: Fri, 28 May 2021 02:54:13 +0300 Message-Id: <20210527235413.23120-15-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210527235413.23120-1-digetx@gmail.com> References: <20210527235413.23120-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The core voltage shall not drop until state of core domain is synced, i.e. all device drivers that use core domain are loaded and ready. Support core domain state syncing. The core domain driver invokes the core-regulator voltage syncing once the state of domain is synced, at this point the core voltage is allowed to go lower than the level left after bootloader. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 3479be5ee494..b8ce9fd0650d 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -17,6 +17,8 @@ #include #include +#include + struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; @@ -42,6 +44,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra20 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -62,7 +79,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; } diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 18fe53d0a870..e74bbc9c7859 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -18,6 +18,7 @@ #include #include +#include struct tegra_regulator_coupler { struct regulator_coupler coupler; @@ -43,6 +44,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra30 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -63,7 +79,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; }