From patchwork Wed May 26 15:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87CDBC47089 for ; Wed, 26 May 2021 15:23:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FFF861378 for ; Wed, 26 May 2021 15:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235441AbhEZPY7 (ORCPT ); Wed, 26 May 2021 11:24:59 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57164 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235396AbhEZPY6 (ORCPT ); Wed, 26 May 2021 11:24:58 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNKSo076748; Wed, 26 May 2021 10:23:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042600; bh=tiiN7makazoom7pCtyD0iCir4iR2Oy+IqqShZdnezTE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I3O+BFF7WXi1/Usorz2skRjQlEDLzU/xcXlr1fe6iT2SiBznJ+9ppkUW+dCVzK5h4 l+xn9qiMsUA9v9eFVBmdDDaWaDVe7vUJmO+OJivOYJGU0N1Y3wdlFfCotQzp4LiJCl zlTfO+TjALGUe1mMVIA2C0czqvVgY2p5j3g2Srt8= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNKUI078202 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:20 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:19 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:19 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9JZ056314; Wed, 26 May 2021 10:23:15 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 01/18] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes Date: Wed, 26 May 2021 20:52:51 +0530 Message-ID: <20210526152308.16525-2-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Kocialkowski As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default (zero value) is kept to Tx so only the rkisp1 driver, which uses D-PHY in Rx mode, needs to be adapted. Signed-off-by: Paul Kocialkowski Signed-off-by: Pratyush Yadav --- (no changes since v1) include/linux/phy/phy-mipi-dphy.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index a877ffee845d..0f57ef46a8b5 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -6,6 +6,19 @@ #ifndef __PHY_MIPI_DPHY_H_ #define __PHY_MIPI_DPHY_H_ +/** + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode + * + * A MIPI D-PHY can be used to transmit or receive data. + * Since some controllers can support both, the direction to enable is specified + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode. + */ + +enum phy_mipi_dphy_submode { + PHY_MIPI_DPHY_SUBMODE_TX = 0, + PHY_MIPI_DPHY_SUBMODE_RX, +}; + /** * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set * From patchwork Wed May 26 15:22:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E1CDC47088 for ; Wed, 26 May 2021 15:23:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40286613D7 for ; Wed, 26 May 2021 15:23:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235085AbhEZPZL (ORCPT ); Wed, 26 May 2021 11:25:11 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59196 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235470AbhEZPZJ (ORCPT ); Wed, 26 May 2021 11:25:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNUZL001547; Wed, 26 May 2021 10:23:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042610; bh=pEYv/cVE8dpSFqbeMd7nSL6UuSjcYO8ph/UZQDKS7+g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bscH4fWQadjdVVcQPI0Aq/PIEhgMbuTtGhCuPdWwCp1Hu3fuhly+Gniw9wXjTgsBz gpcoSVRRHuuXWgswp+blEYud8l/qBiIHKpgKXah4xybgeJPHjw8jl0EJ3af1LTDeVc kvCOXKMUNwunomPNs7kpPhYI648B0PvwY4h+H/BI= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNUA5093201 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:30 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:30 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:30 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jb056314; Wed, 26 May 2021 10:23:25 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 03/18] phy: cdns-dphy: Allow setting mode Date: Wed, 26 May 2021 20:52:53 +0530 Message-ID: <20210526152308.16525-4-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow callers to set the PHY mode. The main mode should always be PHY_MODE_MIPI_DPHY but the submode can either be PHY_MIPI_DPHY_SUBMODE_RX or PHY_MIPI_DPHY_SUBMODE_TX. Update the ops based on the requested submode. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/phy/cadence/cdns-dphy.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 8656f2102a91..7d5f7b333893 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -365,11 +365,41 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } +static int cdns_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + const struct cdns_dphy_driver_data *ddata; + + ddata = of_device_get_match_data(dphy->dev); + if (!ddata) + return -EINVAL; + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (submode == PHY_MIPI_DPHY_SUBMODE_TX) { + if (!ddata->tx) + return -EOPNOTSUPP; + + dphy->ops = ddata->tx; + } else if (submode == PHY_MIPI_DPHY_SUBMODE_RX) { + if (!ddata->rx) + return -EOPNOTSUPP; + + dphy->ops = ddata->rx; + } else { + return -EOPNOTSUPP; + } + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, .power_on = cdns_dphy_power_on, .power_off = cdns_dphy_power_off, + .set_mode = cdns_dphy_set_mode, }; static int cdns_dphy_probe(struct platform_device *pdev) From patchwork Wed May 26 15:22:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56211C47082 for ; Wed, 26 May 2021 15:23:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34321613D3 for ; Wed, 26 May 2021 15:23:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235450AbhEZPZ3 (ORCPT ); Wed, 26 May 2021 11:25:29 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57266 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235507AbhEZPZ0 (ORCPT ); Wed, 26 May 2021 11:25:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNeHt076862; Wed, 26 May 2021 10:23:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042620; bh=W9KtbhWc69uFW7TWtNV1CvIGGgRjw1aPelfSIlmtk3k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BkGYJ3+bQW2YTFj1iMj9YPRtjxTYbX+9sNeZCVqwyDvmPwAYmueKYpk+y3P+r/ZFn 2yRflgihVz7KMTzL3OmwHNNLY3eKRC3fQhfnVupQ3LVTwY+gOl1FU4qde1QkCcxS0a Qty/V8mqyCU40PVxEPGoO9BTKtLUXcJvLKlHczI4= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNebX093422 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:40 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:40 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:40 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jd056314; Wed, 26 May 2021 10:23:35 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 05/18] media: ov5640: Use runtime PM to control sensor power Date: Wed, 26 May 2021 20:52:55 +0530 Message-ID: <20210526152308.16525-6-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Calling s_power subdev callback is discouraged. Instead, the subdevs should use runtime PM to control its power. Use runtime PM callbacks to control sensor power. The pm counter is incremented when the stream is started and decremented when the stream is stopped. Refactor s_stream() a bit to make this new control flow easier. Add a helper to choose whether mipi or dvp set_stream needs to be called. The logic flow is also changed to make it a bit clearer. Signed-off-by: Pratyush Yadav --- Changes in v2: - New in v2. drivers/media/i2c/Kconfig | 2 +- drivers/media/i2c/ov5640.c | 124 +++++++++++++++++++++++-------------- 2 files changed, 77 insertions(+), 49 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 462c0e059754..5588fc1cc14a 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -914,7 +914,7 @@ config VIDEO_OV2740 config VIDEO_OV5640 tristate "OmniVision OV5640 sensor support" - depends on OF + depends on OF && PM depends on GPIOLIB && VIDEO_V4L2 && I2C select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index 5b9cc71df473..4ed5758e2398 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -238,8 +239,6 @@ struct ov5640_dev { /* lock to protect all members below */ struct mutex lock; - int power_count; - struct v4l2_mbus_framefmt fmt; bool pending_fmt_change; @@ -1277,6 +1276,14 @@ static int ov5640_set_stream_mipi(struct ov5640_dev *sensor, bool on) on ? 0x00 : 0x0f); } +static int ov5640_set_stream(struct ov5640_dev *sensor, bool on) +{ + if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) + return ov5640_set_stream_mipi(sensor, on); + else + return ov5640_set_stream_dvp(sensor, on); +} + static int ov5640_get_sysclk(struct ov5640_dev *sensor) { /* calculate sysclk */ @@ -2155,37 +2162,6 @@ static int ov5640_set_power(struct ov5640_dev *sensor, bool on) /* --------------- Subdev Operations --------------- */ -static int ov5640_s_power(struct v4l2_subdev *sd, int on) -{ - struct ov5640_dev *sensor = to_ov5640_dev(sd); - int ret = 0; - - mutex_lock(&sensor->lock); - - /* - * If the power count is modified from 0 to != 0 or from != 0 to 0, - * update the power state. - */ - if (sensor->power_count == !on) { - ret = ov5640_set_power(sensor, !!on); - if (ret) - goto out; - } - - /* Update the power count. */ - sensor->power_count += on ? 1 : -1; - WARN_ON(sensor->power_count < 0); -out: - mutex_unlock(&sensor->lock); - - if (on && !ret && sensor->power_count == 1) { - /* restore controls */ - ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler); - } - - return ret; -} - static int ov5640_try_frame_interval(struct ov5640_dev *sensor, struct v4l2_fract *fi, u32 width, u32 height) @@ -2681,6 +2657,7 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl) { struct v4l2_subdev *sd = ctrl_to_sd(ctrl); struct ov5640_dev *sensor = to_ov5640_dev(sd); + struct device *dev = &sensor->i2c_client->dev; int ret; /* v4l2_ctrl_lock() locks our own mutex */ @@ -2690,7 +2667,7 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl) * not apply any controls to H/W at this time. Instead * the controls will be restored right after power-up. */ - if (sensor->power_count == 0) + if (pm_runtime_suspended(dev)) return 0; switch (ctrl->id) { @@ -2939,39 +2916,56 @@ static int ov5640_enum_mbus_code(struct v4l2_subdev *sd, static int ov5640_s_stream(struct v4l2_subdev *sd, int enable) { struct ov5640_dev *sensor = to_ov5640_dev(sd); + struct device *dev = &sensor->i2c_client->dev; int ret = 0; mutex_lock(&sensor->lock); - if (sensor->streaming == !enable) { - if (enable && sensor->pending_mode_change) { + if (sensor->streaming == enable) + goto out; + + if (enable) { + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + goto out; + } + + if (sensor->pending_mode_change) { ret = ov5640_set_mode(sensor); if (ret) - goto out; + goto put_pm; } - if (enable && sensor->pending_fmt_change) { + if (sensor->pending_fmt_change) { ret = ov5640_set_framefmt(sensor, &sensor->fmt); if (ret) - goto out; + goto put_pm; sensor->pending_fmt_change = false; } - if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) - ret = ov5640_set_stream_mipi(sensor, enable); - else - ret = ov5640_set_stream_dvp(sensor, enable); + ret = ov5640_set_stream(sensor, enable); + if (ret) + goto put_pm; + } else { + ret = ov5640_set_stream(sensor, enable); + if (ret) + goto out; - if (!ret) - sensor->streaming = enable; + pm_runtime_put(dev); } + + sensor->streaming = enable; + goto out; + +put_pm: + pm_runtime_put(dev); out: mutex_unlock(&sensor->lock); return ret; } static const struct v4l2_subdev_core_ops ov5640_core_ops = { - .s_power = ov5640_s_power, .log_status = v4l2_ctrl_subdev_log_status, .subscribe_event = v4l2_ctrl_subdev_subscribe_event, .unsubscribe_event = v4l2_event_subdev_unsubscribe, @@ -3037,6 +3031,29 @@ static int ov5640_check_chip_id(struct ov5640_dev *sensor) return ret; } +static int ov5640_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5640_dev *sensor = to_ov5640_dev(subdev); + + return ov5640_set_power(sensor, false); +} + +static int ov5640_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5640_dev *sensor = to_ov5640_dev(subdev); + int ret = 0; + + ret = ov5640_set_power(sensor, true); + if (ret) + return ret; + + return __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); +} + static int ov5640_probe(struct i2c_client *client) { struct device *dev = &client->dev; @@ -3162,13 +3179,17 @@ static int ov5640_probe(struct i2c_client *client) if (ret) goto entity_cleanup; + pm_runtime_enable(dev); + pm_runtime_set_suspended(dev); + ret = v4l2_async_register_subdev_sensor(&sensor->sd); if (ret) - goto free_ctrls; + goto error_pm; return 0; -free_ctrls: +error_pm: + pm_runtime_disable(dev); v4l2_ctrl_handler_free(&sensor->ctrls.handler); entity_cleanup: media_entity_cleanup(&sensor->sd.entity); @@ -3178,17 +3199,23 @@ static int ov5640_probe(struct i2c_client *client) static int ov5640_remove(struct i2c_client *client) { + struct device *dev = &client->dev; struct v4l2_subdev *sd = i2c_get_clientdata(client); struct ov5640_dev *sensor = to_ov5640_dev(sd); v4l2_async_unregister_subdev(&sensor->sd); media_entity_cleanup(&sensor->sd.entity); + pm_runtime_disable(dev); v4l2_ctrl_handler_free(&sensor->ctrls.handler); mutex_destroy(&sensor->lock); return 0; } +static const struct dev_pm_ops ov5640_pm_ops = { + SET_RUNTIME_PM_OPS(ov5640_suspend, ov5640_resume, NULL) +}; + static const struct i2c_device_id ov5640_id[] = { {"ov5640", 0}, {}, @@ -3205,6 +3232,7 @@ static struct i2c_driver ov5640_i2c_driver = { .driver = { .name = "ov5640", .of_match_table = ov5640_dt_ids, + .pm = &ov5640_pm_ops, }, .id_table = ov5640_id, .probe_new = ov5640_probe, From patchwork Wed May 26 15:22:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CFD1C4708D for ; Wed, 26 May 2021 15:24:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 528BE613D8 for ; Wed, 26 May 2021 15:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235496AbhEZPZb (ORCPT ); Wed, 26 May 2021 11:25:31 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:57286 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235448AbhEZPZa (ORCPT ); Wed, 26 May 2021 11:25:30 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFNpY3076891; Wed, 26 May 2021 10:23:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042631; bh=pa6nQIVZcdm7Nv79anocZJUgCF885/mvEjU3jtVZ7kU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=htWtkJbU9DTXY9r65ZK8WChykbFkmIjf2KJDahZz5GJlEWVktn7Tsj1eVbyyTH0A/ qPFSbuwUjvwzDmokigqgDNTgp+HtTPtljMGIEvhq+u2T9s9ZdQm/ZdynGWGEKiMZg/ rl8+X3F9kJX0G3Z9+GWDw+N3IkK843TE7F9228pQ= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFNpw6078777 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:23:51 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:23:50 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:23:50 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jf056314; Wed, 26 May 2021 10:23:45 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 07/18] media: cadence: csi2rx: Soft reset the streams before starting capture Date: Wed, 26 May 2021 20:52:57 +0530 Message-ID: <20210526152308.16525-8-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 459326de2eff..80a50284e525 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -39,6 +39,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -150,12 +151,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + int i; + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); udelay(10); writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + usleep_range(10, 20); + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } } static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) From patchwork Wed May 26 15:22:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4E2AC47088 for ; Wed, 26 May 2021 15:24:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC5BC613C9 for ; Wed, 26 May 2021 15:24:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235507AbhEZPZq (ORCPT ); Wed, 26 May 2021 11:25:46 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59280 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235540AbhEZPZk (ORCPT ); Wed, 26 May 2021 11:25:40 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFO1Mt001716; Wed, 26 May 2021 10:24:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042641; bh=+Fnp8KoXJxyvVWGYh0lljVtokCpVdrXxDej3meTiGfw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lpKrBIXkngD4dYPvXBY1iierWocjKGHP8C1YbaD2xHxBoOpT7eirqz7jv1ojO2h3l Y8xUIIdtHEv9n6FN1VxHJFsqzcPym+bWNvTC3LZERekREpOvpxN+BDlWcFbVM5cpW2 jnLIOfN0h1sylUFnFdnRQPXAwmy5ZF5lsqhf03cI= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFO1OL115377 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:01 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:00 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:00 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jh056314; Wed, 26 May 2021 10:23:56 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 09/18] media: cadence: csi2rx: Fix stream data configuration Date: Wed, 26 May 2021 20:52:59 +0530 Message-ID: <20210526152308.16525-10-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Firstly, there is no VC_EN bit present in the STREAM_DATA_CFG register. Bit 31 is part of the VL_SELECT field. Remove it completely. Secondly, it makes little sense to enable ith virtual channel for ith stream. Sure, there might be a use-case that demands it. But there might also be a use case that demands all streams to use the 0th virtual channel. Prefer this case over the former because it is less arbitrary and also makes it very clear what the limitations of the current driver is instead of giving a false impression that multiple virtual channels are supported. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/media/platform/cadence/cdns-csi2rx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index ecc43a618c34..1df21f462f3c 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -48,7 +48,6 @@ #define CSI2RX_STREAM_STATUS_RDY BIT(31) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) -#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) @@ -301,8 +300,11 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); - writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT | - CSI2RX_STREAM_DATA_CFG_VC_SELECT(i), + /* + * Enable one virtual channel. When multiple virtual channels + * are supported this will have to be changed. + */ + writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0), csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); writel(CSI2RX_STREAM_CTRL_START, From patchwork Wed May 26 15:23:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 781C8C47082 for ; Wed, 26 May 2021 15:25:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D72B613D7 for ; Wed, 26 May 2021 15:25:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235574AbhEZP0n (ORCPT ); Wed, 26 May 2021 11:26:43 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59298 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235522AbhEZP0T (ORCPT ); Wed, 26 May 2021 11:26:19 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14QFOBEt001745; Wed, 26 May 2021 10:24:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622042651; bh=BMdz5PIJ0bDUzRjPQ3h1Ef4Vn0+hXXShPYDakbVNwWY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LKyZ1j1jo5rtIHOGp+W2Y09byBc3lfx05EF4zJS7YJIbAfGP6NBpjQqRsSPEXDZNj vZpv13I3KS/chm0DPrdYI2k3Rdzs8nY4SWzcBHUHkhnd18wFymedxaefQVTd0LXPW5 X95OJkP55aYdSXQlbNSbGmOtTnlsOw71Ibd9Xd/k= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14QFOB2t101445 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 May 2021 10:24:11 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:11 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jj056314; Wed, 26 May 2021 10:24:06 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 11/18] dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX Date: Wed, 26 May 2021 20:53:01 +0530 Message-ID: <20210526152308.16525-12-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can have up to 32 threads but the current driver only supports using one. So add an entry for that one thread. Signed-off-by: Pratyush Yadav --- Changes in v2: - Add all 64 threads, instead of having only the one thread being currently used by the driver. drivers/dma/ti/k3-psil-j721e.c | 73 ++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c index 7580870ed746..34e3fc565a37 100644 --- a/drivers/dma/ti/k3-psil-j721e.c +++ b/drivers/dma/ti/k3-psil-j721e.c @@ -58,6 +58,14 @@ }, \ } +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ static struct psil_ep j721e_src_ep_map[] = { /* SA2UL */ @@ -138,6 +146,71 @@ static struct psil_ep j721e_src_ep_map[] = { PSIL_PDMA_XY_PKT(0x4707), PSIL_PDMA_XY_PKT(0x4708), PSIL_PDMA_XY_PKT(0x4709), + /* CSI2RX */ + PSIL_CSI2RX(0x4940), + PSIL_CSI2RX(0x4941), + PSIL_CSI2RX(0x4942), + PSIL_CSI2RX(0x4943), + PSIL_CSI2RX(0x4944), + PSIL_CSI2RX(0x4945), + PSIL_CSI2RX(0x4946), + PSIL_CSI2RX(0x4947), + PSIL_CSI2RX(0x4948), + PSIL_CSI2RX(0x4949), + PSIL_CSI2RX(0x494a), + PSIL_CSI2RX(0x494b), + PSIL_CSI2RX(0x494c), + PSIL_CSI2RX(0x494d), + PSIL_CSI2RX(0x494e), + PSIL_CSI2RX(0x494f), + PSIL_CSI2RX(0x4950), + PSIL_CSI2RX(0x4951), + PSIL_CSI2RX(0x4952), + PSIL_CSI2RX(0x4953), + PSIL_CSI2RX(0x4954), + PSIL_CSI2RX(0x4955), + PSIL_CSI2RX(0x4956), + PSIL_CSI2RX(0x4957), + PSIL_CSI2RX(0x4958), + PSIL_CSI2RX(0x4959), + PSIL_CSI2RX(0x495a), + PSIL_CSI2RX(0x495b), + PSIL_CSI2RX(0x495c), + PSIL_CSI2RX(0x495d), + PSIL_CSI2RX(0x495e), + PSIL_CSI2RX(0x495f), + PSIL_CSI2RX(0x4960), + PSIL_CSI2RX(0x4961), + PSIL_CSI2RX(0x4962), + PSIL_CSI2RX(0x4963), + PSIL_CSI2RX(0x4964), + PSIL_CSI2RX(0x4965), + PSIL_CSI2RX(0x4966), + PSIL_CSI2RX(0x4967), + PSIL_CSI2RX(0x4968), + PSIL_CSI2RX(0x4969), + PSIL_CSI2RX(0x496a), + PSIL_CSI2RX(0x496b), + PSIL_CSI2RX(0x496c), + PSIL_CSI2RX(0x496d), + PSIL_CSI2RX(0x496e), + PSIL_CSI2RX(0x496f), + PSIL_CSI2RX(0x4970), + PSIL_CSI2RX(0x4971), + PSIL_CSI2RX(0x4972), + PSIL_CSI2RX(0x4973), + PSIL_CSI2RX(0x4974), + PSIL_CSI2RX(0x4975), + PSIL_CSI2RX(0x4976), + PSIL_CSI2RX(0x4977), + PSIL_CSI2RX(0x4978), + PSIL_CSI2RX(0x4979), + PSIL_CSI2RX(0x497a), + PSIL_CSI2RX(0x497b), + PSIL_CSI2RX(0x497c), + PSIL_CSI2RX(0x497d), + PSIL_CSI2RX(0x497e), + PSIL_CSI2RX(0x497f), /* CPSW9 */ PSIL_ETHERNET(0x4a00), /* CPSW0 */ From patchwork Wed May 26 15:23:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56EB3C47088 for ; Wed, 26 May 2021 15:24:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B416613DC for ; Wed, 26 May 2021 15:24:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233940AbhEZP02 (ORCPT ); Wed, 26 May 2021 11:26:28 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59440 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235541AbhEZP0T (ORCPT ); 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Wed, 26 May 2021 10:24:26 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jm056314; Wed, 26 May 2021 10:24:22 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 14/18] media: dt-bindings: Add DT bindings for TI J721E CSI2RX driver Date: Wed, 26 May 2021 20:53:04 +0530 Message-ID: <20210526152308.16525-15-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by: Pratyush Yadav --- Changes in v2: - Rename to ti,j721e-csi2rx.yaml - Add an entry in MAINTAINERS. - Add a description for the binding. - Change compatible to ti,j721e-csi2rx to make it SoC specific. - Remove description from dmas, reg, power-domains. - Remove a limit of 2 from #address-cells and #size-cells. - Fix add ^ to csi-bridge subnode regex. - Make ranges mandatory. - Add unit address in example. - Add a reference to cdns,csi2rx in csi-bridge subnode. - Expand the example to include the csi-bridge subnode as well. - Re-order subject prefixes. .../bindings/media/ti,j721e-csi2rx.yaml | 101 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml new file mode 100644 index 000000000000..db87cfd65bed --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721E CSI2RX Wrapper Device Tree Bindings + +description: | + The TI J721E CSI2RX Wrapper is a wrapper around Cadence CSI2RX bridge that + enables sending captured frames to memory over PSI-L DMA. In the J721E + Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the + CSI_RX_IF section. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: ti,j721e-csi2rx + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx0 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ranges: true + + "#address-cells": true + + "#size-cells": true + +patternProperties: + "^csi-bridge@": + type: object + description: CSI2 bridge node. + $ref: cdns,csi2rx.yaml# + +required: + - compatible + - reg + - dmas + - dma-names + - power-domains + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x4500000 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cdns_csi2rx: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x4504000 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + + reg = <0>; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2cf140a02063..1f9de488564d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18336,6 +18336,7 @@ TI J721E CSI2RX DRIVER M: Pratyush Yadav L: linux-media@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml F: drivers/media/platform/ti/j721e-csi2rx/ TI DAVINCI MACHINE SUPPORT From patchwork Wed May 26 15:23:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 448357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85656C4708F for ; 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Wed, 26 May 2021 10:24:32 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 26 May 2021 10:24:31 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 26 May 2021 10:24:31 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jn056314; Wed, 26 May 2021 10:24:27 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 15/18] media: dt-bindings: Convert Cadence CSI2RX binding to YAML Date: Wed, 26 May 2021 20:53:05 +0530 Message-ID: <20210526152308.16525-16-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Cadence CSI2RX binding to use YAML schema. Signed-off-by: Pratyush Yadav --- Changes in v2: - New in v2. .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ----------- .../bindings/media/cdns,csi2rx.yaml | 164 ++++++++++++++++++ 2 files changed, 164 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt deleted file mode 100644 index 6b02a0657ad9..000000000000 --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +++ /dev/null @@ -1,100 +0,0 @@ -Cadence MIPI-CSI2 RX controller -=============================== - -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI -lanes in input, and 4 different pixel streams in output. - -Required properties: - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * sys_clk: main clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties: - - phys: phandle to the external D-PHY, phy-names must be provided - - phy-names: must contain "dphy", if the implementation uses an - external D-PHY - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 input - 1 Stream 0 output - 2 Stream 1 output - 3 Stream 2 output - 4 Stream 3 output - - The stream output port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design.Since there is only one endpoint per port, - the endpoints are not numbered. - - -Example: - -csi2rx: csi-bridge@0d060000 { - compatible = "cdns,csi2rx"; - reg = <0x0d060000 0x1000>; - clocks = <&byteclock>, <&byteclock> - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "sys_clk", "p_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2rx_in_sensor: endpoint { - remote-endpoint = <&sensor_out_csi2rx>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2rx_out_grabber0: endpoint { - remote-endpoint = <&grabber0_in_csi2rx>; - }; - }; - - port@2 { - reg = <2>; - - csi2rx_out_grabber1: endpoint { - remote-endpoint = <&grabber1_in_csi2rx>; - }; - }; - - port@3 { - reg = <3>; - - csi2rx_out_grabber2: endpoint { - remote-endpoint = <&grabber2_in_csi2rx>; - }; - }; - - port@4 { - reg = <4>; - - csi2rx_out_grabber3: endpoint { - remote-endpoint = <&grabber3_in_csi2rx>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml new file mode 100644 index 000000000000..ff5dd4211ac9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence MIPI-CSI2 RX controller + +description: | + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI + lanes in input, and 4 different pixel streams in output. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: cdns,csi2rx + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 6 + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: sys_clk # main clock + - const: p_clk # register bank clock + - const: pixel_if0_clk # pixel stream 0 output clock + - const: pixel_if1_clk # pixel stream 1 output clock + - const: pixel_if2_clk # pixel stream 2 output clock + - const: pixel_if3_clk # pixel stream 3 output clock + + phys: + maxItems: 1 + description: phandle to the external D-PHY + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 input + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + maxItems: 1 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 0 output + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 1 output + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 2 output + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 3 output + + required: + - port@0 + + +dependencies: + phys: [ 'phy-names' ] + phy-names: [ 'phys' ] + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + csi2rx: csi-bridge@d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; + }; From patchwork Wed May 26 15:23:08 2021 Content-Type: text/plain; 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Wed, 26 May 2021 10:24:47 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14QFN9Jq056314; Wed, 26 May 2021 10:24:42 -0500 From: Pratyush Yadav To: Maxime Ripard , Mauro Carvalho Chehab , Rob Herring , Pratyush Yadav , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , , , , , CC: Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: [PATCH v2 18/18] phy: dt-bindings: cdns, dphy: add power-domains property Date: Wed, 26 May 2021 20:53:08 +0530 Message-ID: <20210526152308.16525-19-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210526152308.16525-1-p.yadav@ti.com> References: <20210526152308.16525-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This property is needed on TI platforms to enable the PD of the DPHY before it can be used. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- Changes in v2: - Add power-domain to the example. - Add Laurent's R-by. - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index 3bb5be05e825..d5a5e1f0b671 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -30,6 +30,9 @@ properties: "#phy-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -39,11 +42,13 @@ additionalProperties: false examples: - | + #include dphy0: phy@fd0e0000{ compatible = "cdns,dphy"; reg = <0xfd0e0000 0x1000>; clocks = <&psm_clk>, <&pll_ref_clk>; clock-names = "psm", "pll_ref"; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; #phy-cells = <0>; };