From patchwork Mon Jul 9 11:43:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 141388 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2563188ljj; Mon, 9 Jul 2018 04:44:12 -0700 (PDT) X-Google-Smtp-Source: AAOMgpenhslB/um6YMzAQAA/j/BZVPF2LHwHyrz0BhO2B0MBd3r3sdM+3PjF1rklre5VWuDX5UAZ X-Received: by 2002:a17:902:d807:: with SMTP id a7-v6mr20027893plz.214.1531136652493; Mon, 09 Jul 2018 04:44:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531136652; cv=none; d=google.com; s=arc-20160816; b=kLIAmkAIT9gklQeKwR43z2pC2fg/k+qhQKwo3CGXMDVeWHWpPNR90qnVZhHS/+A8HA A3eLIIQH/WtAtVjZtLXrz3g7oxyJbvWKWJXjG6+TywU85lGwXjrVWij0NSpvTtYQeGlw jm49H6hgUvEeoHHiDb/91B+UMeVuUNCIYLb0f/LlVeMdFVSKehYAfrk8u1YOIprd+u5W iOjOghxdwA/w42+TuOVdGrReFo4cZnHQMv7G6NgO7WDjn+jipSKU55wZcrHLtrj537Zc 1LyXyqUYMW2FBcLdygvQbd+ceUCuyl35ASC9j4S5rbaWP8KrTlq8NM+CKnpw4Svv2aGT LNnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=APdBDEY611XaPq8bea03PTPjzHjIlKVJbIaqVWgr9zM=; b=iuNBeRPHoAIDpzwFufLD1tkvEzFi8mi4IW91n55GvdxGWQV54Lekk2/kPvSyzNzKlb 8RDy6Cf4gjz03PHIBS0Fv3LPMmQ7R1xHBX7dQVojLiYAZPEnKuzWG9JHNU703TEktiP3 kmqlHYxZeKa8Z6B5+xdgftTB5I6hn6ty7xuTKlYZAiVDswjgfoA+c1xH+juT8gaHz/y0 c63EXe3nKArOvLjHiMlAFU+wptZvDH50vfto0WJSEzqN+ZbWU35olzmCKRLvLoBWGIUx qrWv3qai+jKvAFDRM9Pnzxd5HmPBKCpbwp4rgcNUFiIuPP24fzM6SspADF7lTsTx0XrH YJ9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=krGIEz4i; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v14-v6si11150033pga.270.2018.07.09.04.44.12; Mon, 09 Jul 2018 04:44:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=krGIEz4i; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754529AbeGILoK (ORCPT + 13 others); Mon, 9 Jul 2018 07:44:10 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:36436 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754523AbeGILoH (ORCPT ); Mon, 9 Jul 2018 07:44:07 -0400 Received: by mail-pl0-f65.google.com with SMTP id a7-v6so5932238plp.3 for ; Mon, 09 Jul 2018 04:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=6BLPkOT/SgEgQAvO08/wD9B+TzSAkRr3OD36saLthVg=; b=krGIEz4i4NdigSSlPbjl9Y+cWuquQd3yMIMxvCdLjIbXTfU9rP6NzwGhxRVfSqbvup 4NwX9wDbE7Fmxgxhi0oj0AbguwfwK/BfsbuM8ZyvxMJ7d0IQhvG7Vf7CZXdmR+thymRN /6SBPXd3WuxYJGI+Y+0/xSh6qA85sUt28Nrjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=6BLPkOT/SgEgQAvO08/wD9B+TzSAkRr3OD36saLthVg=; b=ncGxn5tw+w3uuDwT3PW9L36AHBdsdrTHN4xsxjsWew8mQhft2qtYJcZacA4erueaKM AzFg+qEs68DnO8m1SXhVe3sRqXq7RG8kU2v9fdtq0hsRH6TlJWQ7VrnqQJdl+ONM2Vmx o8ZYM1lYjlQsRV5O7/77eXYwpfmjVbvWqBkvIlzv3O6Doa8wfhGXw/iCyBbeXYl3FZOu wSSG1MNqzt3k2ZR9id2uQGy949R0dUGLlS5Y4NrR7NrKM3LsjMPymY0w499N8aBOCdc+ Ufpi+ubby9bzxI8IBaX6+o5n3vBNqaKVtG47BPtlUufoazZ4x6VAsS4SHSew5bSHYmQb FPyg== X-Gm-Message-State: APt69E1eujRUzGf8V7GRJAjgnkEmudTZBSBKZsLisX/QlehM6LNlT1YP FKc7y031ofkcd8ZOzomY1TUuOg== X-Received: by 2002:a17:902:6b86:: with SMTP id p6-v6mr20395916plk.75.1531136646865; Mon, 09 Jul 2018 04:44:06 -0700 (PDT) Received: from localhost ([103.249.91.93]) by smtp.gmail.com with ESMTPSA id n18-v6sm32311344pfa.50.2018.07.09.04.44.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Jul 2018 04:44:06 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, vivek.gautam@codeaurora.org, andy.gross@linaro.org, Zhang Rui , linux-pm@vger.kernel.org Subject: [PATCH v6 2/7] thermal: tsens: Add support to split up register address space into two Date: Mon, 9 Jul 2018 17:13:24 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are two banks of registers for v2 TSENS IPs: SROT and TM. On older SoCs these were contiguous, leading to DTs mapping them as one register address space of size 0x2000. In newer SoCs, these two banks are not contiguous anymore. Fixing old DTs to split the address space into allows us to have cleaner common code e.g. get_temp() that is shared across new and old platforms. But we need to add logic to init_common() to differentiate between old and new DTs and adjust associated offsets for the TM register bank so that the old DTs will continue to function correctly. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-8996.c | 2 +- drivers/thermal/qcom/tsens-common.c | 11 +++++++++++ drivers/thermal/qcom/tsens.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Bjorn Andersson diff --git a/drivers/thermal/qcom/tsens-8996.c b/drivers/thermal/qcom/tsens-8996.c index e1f7781..60765b1 100644 --- a/drivers/thermal/qcom/tsens-8996.c +++ b/drivers/thermal/qcom/tsens-8996.c @@ -28,7 +28,7 @@ static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp) unsigned int sensor_addr; int last_temp = 0, last_temp2 = 0, last_temp3 = 0, ret; - sensor_addr = STATUS_OFFSET + s->hw_id * 4; + sensor_addr = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; ret = regmap_read(tmdev->map, sensor_addr, &code); if (ret) return ret; diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index b1449ad..4a741b0 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "tsens.h" @@ -126,11 +127,21 @@ static const struct regmap_config tsens_config = { int __init init_common(struct tsens_device *tmdev) { void __iomem *base; + struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); + if (!op) + return -EINVAL; base = of_iomap(tmdev->dev->of_node, 0); if (!base) return -EINVAL; + if (op->num_resources > 1) { + tmdev->tm_offset = 0; + } else { + /* old DTs where SROT and TM were in a contiguous 2K block */ + tmdev->tm_offset = 0x1000; + } + tmdev->map = devm_regmap_init_mmio(tmdev->dev, base, &tsens_config); if (IS_ERR(tmdev->map)) { iounmap(base); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index dc56e1e..d785b37 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -77,6 +77,7 @@ struct tsens_device { struct device *dev; u32 num_sensors; struct regmap *map; + u32 tm_offset; struct tsens_context ctx; const struct tsens_ops *ops; struct tsens_sensor sensor[0]; From patchwork Mon Jul 9 11:43:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 141392 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2563600ljj; Mon, 9 Jul 2018 04:44:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfTlJEnEahK9uisZdQzhs4v/CVjyx5YPn07abuq0ryFB2mnJ7125EdI+VRAGitbYySo3Z/p X-Received: by 2002:a17:902:6b05:: with SMTP id o5-v6mr20396737plk.67.1531136678006; Mon, 09 Jul 2018 04:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531136678; cv=none; d=google.com; s=arc-20160816; b=Sr9+/KgyzUJ6UhwkCRQMS0o7ZsIF1XRoxDRMo12Q5PzkqEhaiXZp3XO0ms7FlJOkmz ziPxMowkYNIdrVdahrg5jLJzDmI2YQ5S/bzydilRgT3thnsMGqtRpHtxrSBPbIoJTyn/ zC/7tCdnFAcCaWDENo/9JnfeKRu+R7w8nw1BfSyVwN2rHku3NMJG9iN2hWJsIIiSUvdu P8xPqt6Ck3xEpXfThaDCr40wMf5dlouAINiE87+5cOxpc3UrsLcWJcLmDfAV3N3HTXoc YVBKVbsD05nfHVnBcSd5Nvsb0GjGvNyXl5aODKxDbYjxQXeO/ZDQZLUjWimSqPqbyket dREw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=yR8kzBODD0FCZnVM19tmGH1OYdrgydz0JwhLhxNBmig=; b=dsGVJI7n55EUq664VWUblDXQd7EtLS6X5ioi/Gec8x12JJ1rlgM5UReOuk2SU+xABX Wa+yPNgvJnL7K8ub4gaG1asHGGmoHko3yU+Hhru4AlLo0mXTRv1lZZ1ajaJEA6oqA6rc hB2D7gPIv1bsu+NEmyyAYIr+ZVsOO8VIDkxj6yRREsNaf0Qg3YI22hVpSP2JwIK0o9Yo mdYozC2NG83E0kYDsEMibSSvFCPzCULwuBe5Y8eSIA0fwzH+RwIFLX5EMyu4aOkmS/tc VCVghjIELRc2tdcu6ZskhWaAoNgZ0OdIlPIBXz/2PBOCfP0+tdXm74vIFm8guA5PnrMQ x4jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hAup5eMo; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9-v6si14053314pgn.177.2018.07.09.04.44.37; Mon, 09 Jul 2018 04:44:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hAup5eMo; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932881AbeGILof (ORCPT + 13 others); Mon, 9 Jul 2018 07:44:35 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:37145 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932869AbeGILoa (ORCPT ); Mon, 9 Jul 2018 07:44:30 -0400 Received: by mail-pf0-f195.google.com with SMTP id x10-v6so3643810pfm.4 for ; Mon, 09 Jul 2018 04:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=AsozHnJmlM1Of3480z5nTOd6XCOnsdEnjdMHZCjbbAY=; b=hAup5eMoPxA523Cjg6SMQConJmXEjj54Sk0Me6o3bkRNSYA0WI2FFe8s4aiivtMIUq lXK8/7jo0zC9YXvUDf15ho1TLOdTyZAGe8OvJ9PklF3kSrQsrRMokVlxgpuODfthfg/a njknPWlYuOdnlpRoHlHFseyyQBDpkWfNycfLE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=AsozHnJmlM1Of3480z5nTOd6XCOnsdEnjdMHZCjbbAY=; b=BtKXno+U0H8OEUUtezA0xdIMVmh+ziGvW/i2SxEzcgdBr2QAmh96ftc/CsKZH987cd 9fiM0dn/RYlmKbGnrJ0SA0LyAOMJeyULE6p3rYld0qw5Dj98NzGuotFWZ1mxoE2Ee+p3 FSdyaq5I39URNnAoTAccXUZkRqz7pfYVaGp0+GPu7e+QFwCPSYd4ZxZGCHgyoISXxXzV B86v4o2aArlQZk73hHgy++HhmyDmxgE105jPxMiyQWM15yp5kHglxbFLoLtGHbwHrBsb dlTvKyUoTjGLimugIqzYn6c13EOQkRo2y37hvyXL/2Pa+0Gu/5f/fkusdvt5Vh4JJf8v XdhA== X-Gm-Message-State: APt69E2HsOhsVkMTTYRyUZ8BOBOaVPGz02gutoFQc36tprQS/ZV8L1e2 SOMW+mqFZXprEz4rgMO/9TEbzQ== X-Received: by 2002:a63:6c05:: with SMTP id h5-v6mr12679444pgc.367.1531136670324; Mon, 09 Jul 2018 04:44:30 -0700 (PDT) Received: from localhost ([103.249.91.93]) by smtp.gmail.com with ESMTPSA id l79-v6sm24741945pfj.179.2018.07.09.04.44.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Jul 2018 04:44:29 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, vivek.gautam@codeaurora.org, andy.gross@linaro.org, Zhang Rui , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 6/7] dt: thermal: tsens: Document the fallback DT property for v2 of TSENS IP Date: Mon, 9 Jul 2018 17:13:28 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We want to create common code for v2 of the TSENS IP block that is used in a large number of Qualcomm SoCs. "qcom,tsens-v2" should be able to handle most of the common functionality start with a common get_temp() function. It is also necessary to split out the memory regions for the TM and SROT register banks because their offsets are not constant across SoC families. Signed-off-by: Amit Kucheria --- .../devicetree/bindings/thermal/qcom-tsens.txt | 25 +++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 06195e8..8f963b1 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -1,10 +1,16 @@ * QCOM SoC Temperature Sensor (TSENS) Required properties: -- compatible : - - "qcom,msm8916-tsens" : For 8916 Family of SoCs - - "qcom,msm8974-tsens" : For 8974 Family of SoCs - - "qcom,msm8996-tsens" : For 8996 Family of SoCs +- compatible: + Must be one of the following: + - "qcom,msm8916-tsens" (MSM8916) + - "qcom,msm8974-tsens" (MSM8974) + - "qcom,msm8996-tsens" (MSM8996) + - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) + - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) + The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with + version 2 of the TSENS IP. MSM8996 is the only exception beacause the generic + property did not exist when support was added. - reg: Address range of the thermal registers - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. @@ -12,7 +18,7 @@ Required properties: - Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify nvmem cells -Example: +Example 1 (legacy support before a fallback tsens-v2 propoerty was introduced): tsens: thermal-sensor@900000 { compatible = "qcom,msm8916-tsens"; reg = <0x4a8000 0x2000>; @@ -20,3 +26,12 @@ tsens: thermal-sensor@900000 { nvmem-cell-names = "caldata", "calsel"; #thermal-sensor-cells = <1>; }; + +Example 2 (for any platform containing v2 of the TSENS IP): +tsens0: tsens@c222000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc263000 0x1ff>, /* TM */ + <0xc222000 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; + };