From patchwork Fri May 21 12:49:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 445952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE4DFC43460 for ; Fri, 21 May 2021 12:50:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ABD86613E3 for ; Fri, 21 May 2021 12:50:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234282AbhEUMvh (ORCPT ); Fri, 21 May 2021 08:51:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:33524 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234471AbhEUMv1 (ORCPT ); Fri, 21 May 2021 08:51:27 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A5BEC613DD; Fri, 21 May 2021 12:49:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601403; bh=Eo+Q/n/ObHKYPA8KdmfJSeka049NRwoo0j4Nc78qMAM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S7mAlvhails2QDce0UEUE5pSdbFrXQgTe0wQ0BT0JeYpvxalnkvc8GPXDKOsaeT+c 0LVAWUShmJWd7gu9H8fu/MFT3MQZEy8ko9/7KJ6CvS++2KJjvTfUydORnDBvc66Jak x+MaNuFzcT9p8NEp43E8t/Kdm1/l1cf134Knd64YT9ObRwZYSVfYi0LPuYY04qqrip qUsu9UpI21WpbglGBbYtldFWOGxOz1cskzFaQRJQLBMeuBl9voyIIB/rg4cFt+xzLE kmLgonDfx5cuWuC6xFxoF1B/rx7FzctL99/jwHCKxiukKicTFD30XtDJwoz1cIRokt XkqCKqEj+W+mQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 01/13] drm/dsc: Add dsc pps header init function Date: Fri, 21 May 2021 18:19:30 +0530 Message-Id: <20210521124946.3617862-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We required a helper to create and set the dsc_dce_header, so add the dsc_dce_header and API drm_dsc_dsi_pps_header_init Signed-off-by: Vinod Koul --- drivers/gpu/drm/drm_dsc.c | 11 +++++++++++ include/drm/drm_dsc.h | 16 ++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index ff602f7ec65b..0c1b745090e2 100644 --- a/drivers/gpu/drm/drm_dsc.c +++ b/drivers/gpu/drm/drm_dsc.c @@ -49,6 +49,17 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header) } EXPORT_SYMBOL(drm_dsc_dp_pps_header_init); +void drm_dsc_dsi_pps_header_init(struct dsc_dce_header *dsc_header) +{ + memset(dsc_header, 0, sizeof(*dsc_header)); + + dsc_header->bp0 = 0x0A; + dsc_header->bp1 = 1; + dsc_header->bp4 = 10; + dsc_header->bp6 = 128; +} +EXPORT_SYMBOL(drm_dsc_dsi_pps_header_init); + /** * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes * @rc_buffer_block_size: block size code, according to DPCD offset 62h diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index bbe120f461e5..5a3bbeb3e12f 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -602,8 +602,24 @@ struct drm_dsc_pps_infoframe { struct drm_dsc_picture_parameter_set pps_payload; } __packed; +struct dsc_dce_header { + u8 bp0; + u8 bp1; + u8 bp2; + u8 bp3; + u8 bp4; + u8 bp5; + u8 bp6; +} __packed; + +struct drm_dsi_dsc_infoframe { + struct dsc_dce_header dsc_header; + struct drm_dsc_picture_parameter_set pps_payload; +} __packed; + void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); +void drm_dsc_dsi_pps_header_init(struct dsc_dce_header *dsc_header); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); From patchwork Fri May 21 12:49:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D19BC433ED for ; Fri, 21 May 2021 12:50:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FEB4613DE for ; Fri, 21 May 2021 12:50:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230378AbhEUMvk (ORCPT ); Fri, 21 May 2021 08:51:40 -0400 Received: from mail.kernel.org ([198.145.29.99]:33630 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbhEUMvb (ORCPT ); Fri, 21 May 2021 08:51:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 14B946128A; Fri, 21 May 2021 12:50:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601408; bh=evW5pHUN/T4rGcgEYxzNl0VVIeE5qNWtjDjSxJvpPkQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=swpkH1OlMp8m3dC3Op2knzSP+7dNpwV+GLpnTqKTP6Rv9cOr4ZuDrQg1RerHShygz GWLDF2inM+t6mnDbG2UCW7r6z/TwN1q7YgMWTOaDoVRGulMbiBXG8zG4/5b91XLUTP rDwf1hQ18aLr1h+gRkhRnfQT8Lqeyrv1Hyxyq9Mt1y1Imwn3MLM8ZTGY/hqHpwX4uB TeSq+8VtHdoDVNt4FL7T80PylE2tHdIJvqLYj8bApZz92UPSMmy3eukhXnaatygXaK Jd9UQgB4pJ7MrivQRrAButxeohwGiHLp1cdP/JL73buJlKi0PQaKtPGYBKrDtL3LMS uVKjiCutUDDQg== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Rob Herring , devicetree@vger.kernel.org Subject: [RFC PATCH 02/13] dt-bindings: msm/dsi: Document Display Stream Compression (DSC) parameters Date: Fri, 21 May 2021 18:19:31 +0530 Message-Id: <20210521124946.3617862-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DSC enables streams to be compressed before we send to panel. This requires DSC enabled encoder and a panel to be present. So we add this information in board DTS and find if DSC can be enabled and the parameters required to configure DSC are added to binding document along with example Signed-off-by: Vinod Koul --- .../devicetree/bindings/display/msm/dsi.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index b9a64d3ff184..83d2fb92267e 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -48,6 +48,13 @@ Optional properties: - pinctrl-n: the "sleep" pinctrl state - ports: contains DSI controller input and output ports as children, each containing one endpoint subnode. +- qcom,mdss-dsc-enabled: Display Stream Compression (DSC) is enabled +- qcom,mdss-slice-height: DSC slice height in pixels +- qcom,mdss-slice-width: DSC slice width in pixels +- qcom,mdss-slice-per-pkt: DSC slices per packet +- qcom,mdss-bit-per-component: DSC bits per component +- qcom,mdss-bit-per-pixel: DSC bits per pixel +- qcom,mdss-block-prediction-enable: Block prediction mode of DSC enabled DSI Endpoint properties: - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's @@ -188,6 +195,14 @@ Example: qcom,master-dsi; qcom,sync-dual-dsi; + qcom,mdss-dsc-enabled; + qcom,mdss-slice-height = <16>; + qcom,mdss-slice-width = <540>; + qcom,mdss-slice-per-pkt = <1>; + qcom,mdss-bit-per-component = <8>; + qcom,mdss-bit-per-pixel = <8>; + qcom,mdss-block-prediction-enable; + qcom,mdss-mdp-transfer-time-us = <12000>; pinctrl-names = "default", "sleep"; From patchwork Fri May 21 12:49:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06509C433B4 for ; Fri, 21 May 2021 12:50:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E15F5613E2 for ; Fri, 21 May 2021 12:50:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234605AbhEUMvs (ORCPT ); Fri, 21 May 2021 08:51:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:33738 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234634AbhEUMvk (ORCPT ); Fri, 21 May 2021 08:51:40 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6DCE8613DD; Fri, 21 May 2021 12:50:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601417; bh=4+MmQy7ngfpHoR3Ye/vZCDRGZwp0ZIwfKlbILCno4hc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UKjQFQDGi+QcgZa1ClVhplIfhxtKJoQjIPJsFlO4XA127uiH5UqjSJZrRzg0Fobcp MxFIR6+9eWYFICb1hlLbqymJKrUlQ8afxSyFmFYrbbfuYViYXitphko/+gJvnAMEGG w6loKaTB53av3M6lcsFIXQw3svhNjXEMllVjM15VRVSnLOolqlc7S/D6czx1aUOcZZ +NG9PGCZL/Vm45XzBdwX9OWA/CFEQJEc1QKjyqSOGBLPQSLK+PNIB3a41xb83IGnDu wMA4GqlJyt4hSQd1y5EyS6okR4jLLhf0+/BkJF7nd7bKFHOqIIO67dMua4hHrfjtUD jnWey3eUqYnew== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 03/13] drm/msm/dsi: add support for dsc data Date: Fri, 21 May 2021 18:19:33 +0530 Message-Id: <20210521124946.3617862-5-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DSC needs some configuration from device tree, add support to read and store these params and add DSC structures in msm_drv Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/dsi/dsi_host.c | 170 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 32 ++++++ 2 files changed, 202 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8a10e4343281..864d3c655e73 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -156,6 +156,7 @@ struct msm_dsi_host { struct regmap *sfpb; struct drm_display_mode *mode; + struct msm_display_dsc_config *dsc; /* connected device info */ struct device_node *device_node; @@ -1744,6 +1745,168 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; } +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e +}; + +/* only 8bpc, 8bpp added */ +static char min_qp[DSC_NUM_BUF_RANGES] = { + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 +}; + +static char max_qp[DSC_NUM_BUF_RANGES] = { + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 +}; + +static char bpg_offset[DSC_NUM_BUF_RANGES] = { + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 +}; + +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc) +{ + int i; + + dsc->drm.rc_model_size = 8192; + dsc->drm.first_line_bpg_offset = 15; + dsc->drm.rc_edge_factor = 6; + dsc->drm.rc_tgt_offset_high = 3; + dsc->drm.rc_tgt_offset_low = 3; + dsc->drm.simple_422 = 0; + dsc->drm.convert_rgb = 1; + dsc->drm.vbr_enable = 0; + + /* handle only bpp = bpc = 8 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) + dsc->drm.rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; + + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + dsc->drm.rc_range_params[i].range_min_qp = min_qp[i]; + dsc->drm.rc_range_params[i].range_max_qp = max_qp[i]; + dsc->drm.rc_range_params[i].range_bpg_offset = bpg_offset[i]; + } + + dsc->drm.initial_offset = 6144; + dsc->drm.initial_xmit_delay = 512; + dsc->drm.initial_scale_value = 32; + dsc->drm.first_line_bpg_offset = 12; + dsc->drm.line_buf_depth = dsc->drm.bits_per_component + 1; + + /* bpc 8 */ + dsc->drm.flatness_min_qp = 3; + dsc->drm.flatness_max_qp = 12; + dsc->det_thresh_flatness = 7; + dsc->drm.rc_quant_incr_limit0 = 11; + dsc->drm.rc_quant_incr_limit1 = 11; + dsc->drm.mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; + + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of + * params are calculated + */ + + i = dsc->drm.slice_width % 3; + switch (i) { + case 0: + dsc->slice_last_group_size = 2; + break; + + case 1: + dsc->slice_last_group_size = 0; + break; + + case 2: + dsc->slice_last_group_size = 0; + break; + + default: + break; + } + + return 0; +} + +static int dsi_host_parse_dsc(struct msm_dsi_host *msm_host, + struct device_node *np) +{ + struct device *dev = &msm_host->pdev->dev; + struct msm_display_dsc_config *dsc; + bool is_dsc_enabled; + u32 data; + int ret; + + is_dsc_enabled = of_property_read_bool(np, "qcom,mdss-dsc-enabled"); + + if (!is_dsc_enabled) + return 0; + + dsc = kzalloc(sizeof(*dsc), GFP_KERNEL); + if (!dsc) + return -ENOMEM; + + ret = of_property_read_u32(np, "qcom,mdss-dsc-version", &data); + if (ret) { + dsc->drm.dsc_version_major = 0x1; + dsc->drm.dsc_version_minor = 0x1; + } else { + dsc->drm.dsc_version_major = (data >> 4) & 0xf; + dsc->drm.dsc_version_minor = data & 0xf; + } + + ret = of_property_read_u32(np, "qcom,mdss-scr-version", &data); + if (ret) + dsc->scr_rev = 0; + else + dsc->scr_rev = data & 0xff; + + ret = of_property_read_u32(np, "qcom,mdss-slice-height", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read dsc slice height\n"); + goto err; + } + dsc->drm.slice_height = data; + + ret = of_property_read_u32(np, "qcom,mdss-slice-width", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read dsc slice width\n"); + goto err; + } + dsc->drm.slice_width = data; + + ret = of_property_read_u32(np, "qcom,mdss-slice-per-pkt", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read mdss-slice-per-pkt\n"); + goto err; + } + dsc->slice_per_pkt = data; + + ret = of_property_read_u32(np, "qcom,mdss-bit-per-component", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read mdss-bit-per-component\n"); + goto err; + } + dsc->drm.bits_per_component = data; + + ret = of_property_read_u32(np, "qcom,mdss-bit-per-pixel", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read bit-per-pixel\n"); + goto err; + } + dsc->drm.bits_per_pixel = data; + + dsc->drm.block_pred_enable = of_property_read_bool(np, + "qcom,mdss-block-prediction-enable"); + + dsi_populate_dsc_params(dsc); + + msm_host->dsc = dsc; + + return 0; + +err: + kfree(dsc); + return ret; +} + static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) { struct device *dev = &msm_host->pdev->dev; @@ -1763,6 +1926,13 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) return 0; } + ret = dsi_host_parse_dsc(msm_host, np); + if (ret) { + DRM_DEV_ERROR(dev, "%s: invalid dsc configuration %d\n", __func__, ret); + ret = -EINVAL; + goto err; + } + ret = dsi_host_parse_lane_data(msm_host, endpoint); if (ret) { DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 2668941df529..26661dd43936 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -70,6 +71,16 @@ enum msm_mdp_plane_property { #define MSM_GPU_MAX_RINGS 4 #define MAX_H_TILES_PER_DISPLAY 2 +/** + * enum msm_display_compression_type - compression method used for pixel stream + * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed + * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used + */ +enum msm_display_compression_type { + MSM_DISPLAY_COMPRESSION_NONE, + MSM_DISPLAY_COMPRESSION_DSC, +}; + /** * enum msm_display_caps - features/capabilities supported by displays * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported @@ -134,6 +145,24 @@ struct msm_drm_thread { struct kthread_worker *worker; }; +/* DSC config */ +struct msm_display_dsc_config { + struct drm_dsc_config drm; + u8 scr_rev; + + u32 initial_lines; + u32 pkt_per_line; + u32 bytes_in_slice; + u32 bytes_per_pkt; + u32 eol_byte_num; + u32 pclk_per_line; + u32 slice_last_group_size; + u32 slice_per_pkt; + u32 det_thresh_flatness; + u32 extra_width; + u32 pps_delay_ms; +}; + struct msm_drm_private { struct drm_device *dev; @@ -227,6 +256,9 @@ struct msm_drm_private { /* Properties */ struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; + /* DSC configuration */ + struct msm_display_dsc_config *dsc; + /* VRAM carveout, used when no IOMMU: */ struct { unsigned long size; From patchwork Fri May 21 12:49:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444676 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp947026jac; 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[23.128.96.18]) by mx.google.com with ESMTP id m18si422285ili.129.2021.05.21.05.50.40; Fri, 21 May 2021 05:50:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=cebzmsoq; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234655AbhEUMv6 (ORCPT + 17 others); Fri, 21 May 2021 08:51:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:33836 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234673AbhEUMvo (ORCPT ); Fri, 21 May 2021 08:51:44 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D126F6128A; Fri, 21 May 2021 12:50:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601421; bh=9SoiHu6HAdAusAoi4raCnnFpxv209nzRo5hMIPpogYg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cebzmsoqNT0A2AJNtcOjFrWosZBsZew71Do9d5qaQy5KPgjDxlHms/QE/OZyvrwmq 5VX/GJ2IF2C5AYgmvvIg7l+X/4KXeanB1l1DGxClPk0BLzkZ/41wszknt/i1oTsBbF /MKqOy69Wc9lKimXmn0Xh0h0r9InwrNn8EeDIjGu+wgo+B2xiEvYhPyEjOxgDZaPpH 3CMGK27fwb4HbQ4WW7JVQtQTEAPo9fkoCDeK+mmibCx858bL96KNMjqfxuU8ezg0hy g+nsas1XW2RtbXHT2n/7jAxHrxPNkrEGAQDLt1H+gJ3DmY7U4sg20L1oi9sa0ykD37 RnX//g5cLKhcQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Date: Fri, 21 May 2021 18:19:34 +0530 Message-Id: <20210521124946.3617862-6-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In SDM845, DSC can be enabled by writing to pingpong block registers, so add support for DSC in hw_pp Signed-off-by: Vinod Koul --- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++++++++ 2 files changed, 46 insertions(+) -- 2.26.3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 245a7a62b5c6..07fc131ca9aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -28,6 +28,9 @@ #define PP_FBC_MODE 0x034 #define PP_FBC_BUDGET_CTL 0x038 #define PP_FBC_LOSSY_MODE 0x03C +#define PP_DSC_MODE 0x0a0 +#define PP_DCE_DATA_IN_SWAP 0x0ac +#define PP_DCE_DATA_OUT_SWAP 0x0c8 #define PP_DITHER_EN 0x000 #define PP_DITHER_BITDEPTH 0x004 @@ -245,6 +248,32 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) return line; } +static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp) +{ + struct dpu_hw_blk_reg_map *c = &pp->hw; + + DPU_REG_WRITE(c, PP_DSC_MODE, 1); + return 0; +} + +static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp) +{ + struct dpu_hw_blk_reg_map *c = &pp->hw; + + DPU_REG_WRITE(c, PP_DSC_MODE, 0); +} + +static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) +{ + struct dpu_hw_blk_reg_map *pp_c = &pp->hw; + int data; + + data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP); + data |= BIT(18); /* endian flip */ + DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data); + return 0; +} + static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, unsigned long features) { @@ -256,6 +285,9 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config; c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; c->ops.get_line_count = dpu_hw_pp_get_line_count; + c->ops.setup_dsc = dpu_hw_pp_setup_dsc; + c->ops.enable_dsc = dpu_hw_pp_dsc_enable; + c->ops.disable_dsc = dpu_hw_pp_dsc_disable; if (test_bit(DPU_PINGPONG_DITHER, &features)) c->ops.setup_dither = dpu_hw_pp_setup_dither; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 845b9ce80e31..5058e41ffbc0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -124,6 +124,20 @@ struct dpu_hw_pingpong_ops { */ void (*setup_dither)(struct dpu_hw_pingpong *pp, struct dpu_hw_dither_cfg *cfg); + /** + * Enable DSC + */ + int (*enable_dsc)(struct dpu_hw_pingpong *pp); + + /** + * Disable DSC + */ + void (*disable_dsc)(struct dpu_hw_pingpong *pp); + + /** + * Setup DSC + */ + int (*setup_dsc)(struct dpu_hw_pingpong *pp); }; struct dpu_hw_pingpong { From patchwork Fri May 21 12:49:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB3BC433ED for ; Fri, 21 May 2021 12:50:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C4829613D9 for ; Fri, 21 May 2021 12:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231246AbhEUMwS (ORCPT ); Fri, 21 May 2021 08:52:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:34042 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234783AbhEUMv6 (ORCPT ); Fri, 21 May 2021 08:51:58 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 116D3613DF; Fri, 21 May 2021 12:50:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601434; bh=IJdaAJsGZtOuXPGkO/yJepto4E3r/nhHQEJSn5d6nzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mg84n5785SSsuasRZZAL7KfM6X/vWVQVg9V4H5Quty+P6KbLN0DakaqNPmWvrRKFu MtJ6NwrNDzqDSwNje+ToUdKiXLh9c7dK4OSGyb+QcoExyAkF2XeBojqW8P+WANAiKw X9IXsZakJg+GbmftXTQ203RW44BY0+742Rar42RS0ZbJuyNZ0faBxZo1zwnUxBnLcN Tj7KkoZVXyz/LmFpURNZJ/oVbrK5oJA9jHVhHdsuRyowEFxn242tKi+3BdMf+g3EmM SH9c4RzzVyZNlPHfSJlNXDmeTs0VYjgk5J+UdlwQnhiDkIjJkleNfKsSK8mnlfZYtM VopQOOR+1OEkg== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 05/13] drm/msm/dsi: add support for dsc data Date: Fri, 21 May 2021 18:19:37 +0530 Message-Id: <20210521124946.3617862-9-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DSC needs some configuration from device tree, add support to read and store these params and add DSC structures in msm_drv Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/dsi/dsi_host.c | 171 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 32 ++++++ 2 files changed, 203 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8a10e4343281..e0c0f627d15e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -156,6 +156,7 @@ struct msm_dsi_host { struct regmap *sfpb; struct drm_display_mode *mode; + struct msm_display_dsc_config *dsc; /* connected device info */ struct device_node *device_node; @@ -1744,6 +1745,168 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; } +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e +}; + +/* only 8bpc, 8bpp added */ +static char min_qp[DSC_NUM_BUF_RANGES] = { + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 +}; + +static char max_qp[DSC_NUM_BUF_RANGES] = { + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 +}; + +static char bpg_offset[DSC_NUM_BUF_RANGES] = { + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 +}; + +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc) +{ + int i; + + dsc->drm.rc_model_size = 8192; + dsc->drm.first_line_bpg_offset = 15; + dsc->drm.rc_edge_factor = 6; + dsc->drm.rc_tgt_offset_high = 3; + dsc->drm.rc_tgt_offset_low = 3; + dsc->drm.simple_422 = 0; + dsc->drm.convert_rgb = 1; + dsc->drm.vbr_enable = 0; + + /* handle only bpp = bpc = 8 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) + dsc->drm.rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; + + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + dsc->drm.rc_range_params[i].range_min_qp = min_qp[i]; + dsc->drm.rc_range_params[i].range_max_qp = max_qp[i]; + dsc->drm.rc_range_params[i].range_bpg_offset = bpg_offset[i]; + } + + dsc->drm.initial_offset = 6144; + dsc->drm.initial_xmit_delay = 512; + dsc->drm.initial_scale_value = 32; + dsc->drm.first_line_bpg_offset = 12; + dsc->drm.line_buf_depth = dsc->drm.bits_per_component + 1; + + /* bpc 8 */ + dsc->drm.flatness_min_qp = 3; + dsc->drm.flatness_max_qp = 12; + dsc->det_thresh_flatness = 7; + dsc->drm.rc_quant_incr_limit0 = 11; + dsc->drm.rc_quant_incr_limit1 = 11; + dsc->drm.mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; + + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of + * params are calculated + */ + + i = dsc->drm.slice_width % 3; + switch (i) { + case 0: + dsc->slice_last_group_size = 2; + break; + + case 1: + dsc->slice_last_group_size = 0; + break; + + case 2: + dsc->slice_last_group_size = 0; + break; + + default: + break; + } + + return 0; +} + +static int dsi_host_parse_dsc(struct msm_dsi_host *msm_host, + struct device_node *np) +{ + struct device *dev = &msm_host->pdev->dev; + struct msm_display_dsc_config *dsc; + bool is_dsc_enabled; + u32 data; + int ret; + + is_dsc_enabled = of_property_read_bool(np, "qcom,mdss-dsc-enabled"); + + if (!is_dsc_enabled) + return 0; + + dsc = kzalloc(sizeof(*dsc), GFP_KERNEL); + if (!dsc) + return -ENOMEM; + + ret = of_property_read_u32(np, "qcom,mdss-dsc-version", &data); + if (ret) { + dsc->drm.dsc_version_major = 0x1; + dsc->drm.dsc_version_minor = 0x1; + } else { + dsc->drm.dsc_version_major = (data >> 4) & 0xf; + dsc->drm.dsc_version_minor = data & 0xf; + } + + ret = of_property_read_u32(np, "qcom,mdss-scr-version", &data); + if (ret) + dsc->scr_rev = 0; + else + dsc->scr_rev = data & 0xff; + + ret = of_property_read_u32(np, "qcom,mdss-slice-height", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read dsc slice height\n"); + goto err; + } + dsc->drm.slice_height = data; + + ret = of_property_read_u32(np, "qcom,mdss-slice-width", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read dsc slice width\n"); + goto err; + } + dsc->drm.slice_width = data; + + ret = of_property_read_u32(np, "qcom,mdss-slice-per-pkt", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read mdss-slice-per-pkt\n"); + goto err; + } + dsc->slice_per_pkt = data; + + ret = of_property_read_u32(np, "qcom,mdss-bit-per-component", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read mdss-bit-per-component\n"); + goto err; + } + dsc->drm.bits_per_component = data; + + ret = of_property_read_u32(np, "qcom,mdss-bit-per-pixel", &data); + if (ret) { + DRM_DEV_ERROR(dev, "failed to read bit-per-pixel\n"); + goto err; + } + dsc->drm.bits_per_pixel = data; + + dsc->drm.block_pred_enable = of_property_read_bool(np, + "qcom,mdss-block-prediction-enable"); + + dsi_populate_dsc_params(dsc); + + msm_host->dsc = dsc; + + return 0; + +err: + kfree(dsc); + return ret; +} + static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) { struct device *dev = &msm_host->pdev->dev; @@ -1763,6 +1926,14 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) return 0; } + ret = dsi_host_parse_dsc(msm_host, np); + if (ret) { + DRM_DEV_ERROR(dev, "%s: invalid dsc configuration %d\n", + __func__, ret); + ret = -EINVAL; + goto err; + } + ret = dsi_host_parse_lane_data(msm_host, endpoint); if (ret) { DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 2668941df529..26661dd43936 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -70,6 +71,16 @@ enum msm_mdp_plane_property { #define MSM_GPU_MAX_RINGS 4 #define MAX_H_TILES_PER_DISPLAY 2 +/** + * enum msm_display_compression_type - compression method used for pixel stream + * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed + * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used + */ +enum msm_display_compression_type { + MSM_DISPLAY_COMPRESSION_NONE, + MSM_DISPLAY_COMPRESSION_DSC, +}; + /** * enum msm_display_caps - features/capabilities supported by displays * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported @@ -134,6 +145,24 @@ struct msm_drm_thread { struct kthread_worker *worker; }; +/* DSC config */ +struct msm_display_dsc_config { + struct drm_dsc_config drm; + u8 scr_rev; + + u32 initial_lines; + u32 pkt_per_line; + u32 bytes_in_slice; + u32 bytes_per_pkt; + u32 eol_byte_num; + u32 pclk_per_line; + u32 slice_last_group_size; + u32 slice_per_pkt; + u32 det_thresh_flatness; + u32 extra_width; + u32 pps_delay_ms; +}; + struct msm_drm_private { struct drm_device *dev; @@ -227,6 +256,9 @@ struct msm_drm_private { /* Properties */ struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; + /* DSC configuration */ + struct msm_display_dsc_config *dsc; + /* VRAM carveout, used when no IOMMU: */ struct { unsigned long size; From patchwork Fri May 21 12:49:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 445948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49614C43460 for ; Fri, 21 May 2021 12:51:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 319DA613D9 for ; Fri, 21 May 2021 12:51:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234162AbhEUMwZ (ORCPT ); Fri, 21 May 2021 08:52:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:34102 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234829AbhEUMwC (ORCPT ); Fri, 21 May 2021 08:52:02 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 750C8613D9; Fri, 21 May 2021 12:50:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601439; bh=Gb5d67i9Q4U15xb2aE7Imj0HQ2P/vErp6AIgUyNfqvg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I3LsPb4rQpeFHtPNwU8iI/BmV9ZRJNNwyEIakasGihBN8gev7lksE929hszuv3Bro kVeBnMBqjTzLgpZuuYJP7v1R313RDqd7+0aMclaJVsmPhn8Mq1J72rtQsnl12zK8Tu WZ01DkU6C5y0GbmrUbPsVJKoLcTzYFo5Ktmh5bMSAe9E68VFrwkIRyGRyi4eVt4djw WlWAJFaaKIEfPhe5GNHfF454i62OfzAE4PuW8ucha0Tm2iJ6HDf/GhDCWP+ux7vNwb WMScJXW07GnGg2n4E8H9IQWX08TJBI04r6CLPURJsCWHIaB644ziMw5ksnfC8qcD4z D9isIvcGV1IeQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 06/13] drm/msm/disp/dpu1: Add DSC support in RM Date: Fri, 21 May 2021 18:19:38 +0530 Message-Id: <20210521124946.3617862-10-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add the bits in RM to enable the DSC blocks Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + 3 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d6717d6672f7..d56c05146dfe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -165,6 +165,7 @@ struct dpu_global_state { uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index fd2d104f0a91..4da6d72b7996 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -11,6 +11,7 @@ #include "dpu_hw_intf.h" #include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" +#include "dpu_hw_dsc.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_intf_destroy(hw); } } + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) { + struct dpu_hw_dsc *hw; + + if (rm->intf_blks[i]) { + hw = to_dpu_hw_dsc(rm->dsc_blks[i]); + dpu_hw_dsc_destroy(hw); + } + } return 0; } @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; } + for (i = 0; i < cat->dsc_count; i++) { + struct dpu_hw_dsc *hw; + const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; + + hw = dpu_hw_dsc_init(dsc->id, mmio, cat); + if (IS_ERR_OR_NULL(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed dsc object creation: err %d\n", rc); + goto fail; + } + rm->dsc_blks[dsc->id - DSC_0] = &hw->base; + } + return 0; fail: @@ -476,6 +498,9 @@ static int _dpu_rm_reserve_intf( } global_state->intf_to_enc_id[idx] = enc_id; + + global_state->dsc_to_enc_id[0] = enc_id; + global_state->dsc_to_enc_id[1] = enc_id; return 0; } @@ -567,6 +592,8 @@ void dpu_rm_release(struct dpu_global_state *global_state, ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->intf_to_enc_id, ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id); + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); } int dpu_rm_reserve( @@ -640,6 +667,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->dspp_to_enc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break; + case DPU_HW_BLK_DSC: + hw_blks = rm->dsc_blks; + hw_to_enc_id = global_state->dsc_to_enc_id; + max_blks = ARRAY_SIZE(rm->dsc_blks); + break; default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..278d2a510b80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -30,6 +30,7 @@ struct dpu_rm { struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; uint32_t lm_max_width; }; From patchwork Fri May 21 12:49:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96D21C43461 for ; Fri, 21 May 2021 12:51:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 770E1613E4 for ; Fri, 21 May 2021 12:51:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234992AbhEUMw1 (ORCPT ); Fri, 21 May 2021 08:52:27 -0400 Received: from mail.kernel.org ([198.145.29.99]:34150 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234707AbhEUMwG (ORCPT ); Fri, 21 May 2021 08:52:06 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D82D96128A; Fri, 21 May 2021 12:50:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601443; bh=L0xwOq04an7+Pz3OpZctKSdmZivqWGnbevwnOTd9LK0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rgn+1H/17yJtWqL3+pUjns/pIN8nRYXCbEAidZfTyTls4BiEtYxRN3zHxlGUIkYvh xUDGUNCTWvpryQUIYt9tcc0h1BmO5sExIQQutoEqejKTp/T7I90ysdzSspoNkpYjFC QhPeQsRhxJid8PrsCghlHc0LWoaVaqk6bYMIyMIHnBAlYC9kypQmjrhXbXYsaSoz2x rbGx1m0p+LWB35bMH7/CBqZxqGVOxb41C5IFnWeO1kVj2SV14yD5VsJw49PNo79u0s 49+tdz6VlWw6iWm9dzdVq+mdAsFX+ReNIM3O2odR2JSQsrne2zh6LJinex1eQqV63p g4XmI13yaZiVg== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 07/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Date: Fri, 21 May 2021 18:19:39 +0530 Message-Id: <20210521124946.3617862-11-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add SDM845 DSC blocks into hw_catalog Signed-off-by: Vinod Koul --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b569030a0847..1bf599e8ffe0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -40,6 +40,8 @@ #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) +#define DSC_SDM845_MASK BIT(DPU_DSC) + #define PINGPONG_SDM845_SPLIT_MASK \ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) @@ -751,6 +753,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk), PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk), }; + +/************************************************************* + * DSC sub blocks config + *************************************************************/ +#define DSC_BLK(_name, _id, _base) \ + {\ + .name = _name, .id = _id, \ + .base = _base, .len = 0x140, \ + .features = DSC_SDM845_MASK, \ + } + +static struct dpu_dsc_cfg sdm845_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000), + DSC_BLK("dsc_1", DSC_1, 0x80400), + DSC_BLK("dsc_2", DSC_2, 0x80800), + DSC_BLK("dsc_3", DSC_3, 0x80c00), +}; + /************************************************************* * INTF sub blocks config *************************************************************/ @@ -1053,6 +1073,8 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .mixer = sdm845_lm, .pingpong_count = ARRAY_SIZE(sdm845_pp), .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm845_dsc), + .dsc = sdm845_dsc, .intf_count = ARRAY_SIZE(sdm845_intf), .intf = sdm845_intf, .vbif_count = ARRAY_SIZE(sdm845_vbif), From patchwork Fri May 21 12:49:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 445947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EB28C43462 for ; Fri, 21 May 2021 12:51:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1623E613D9 for ; Fri, 21 May 2021 12:51:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235046AbhEUMw3 (ORCPT ); Fri, 21 May 2021 08:52:29 -0400 Received: from mail.kernel.org ([198.145.29.99]:34214 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234858AbhEUMwL (ORCPT ); Fri, 21 May 2021 08:52:11 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4579D613D8; Fri, 21 May 2021 12:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601448; bh=0XahmhIFMEbevuz651JK1SuRalOKFeJShM5ZS9hUNOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p+b1dMuLcyV319Bhe3jSEigdayqKsFhF//ypqJCP+tluFH8ZmM8eq2gAlvlHrHLhG DM7rm48oYDW1OO42JBNc98oyZmjUCZwM3wiAVVBGBry1AAAwK7CK9NkoHxqmQGCbel MNp2RrXN7BjXR4PEqdURurAdn5zsJv5d5aUJzfjM/l2gHWboplc1+q3Bjl/4clH1tH 98w47KacMrvjiyAqlv4lewKUCj+5utIiFXscIPz/fBLWV/QsIeLUgEhp1WyMuaG60J L1vzriacLSu4IPLeYspBAA3IrFfoDsNdexO/Gii5yGjsCzMUzCLRjNeg5C/4/uPiQB cV3CdAQkUn3AQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Fri, 21 May 2021 18:19:40 +0530 Message-Id: <20210521124946.3617862-12-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2d4645e01ebf..aeea6add61ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff @@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, @@ -128,7 +132,7 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, ctx->pending_intf_flush_mask); - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX)); } static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) @@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3)); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, From patchwork Fri May 21 12:49:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37938C43460 for ; Fri, 21 May 2021 12:51:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1EE52613DD for ; Fri, 21 May 2021 12:51:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235094AbhEUMwb (ORCPT ); Fri, 21 May 2021 08:52:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:34316 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234911AbhEUMwP (ORCPT ); Fri, 21 May 2021 08:52:15 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A822D613E1; Fri, 21 May 2021 12:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601452; bh=Y6oR0c4fZFzazX3E5d47MSfaK8VBELYA/cqVKr86K0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SyD6SrfwUWsrUjTwyqnxtuT3D4gOGroTKnqxSpmqMuTgvKgJbFkfyT/dCHaspgSvp Gvc0+KJVKbvCAscrHU/G6A38DgOnXRYmmJKYHAXy2CyTAKtqtPEo69MPVO+cGpExM0 ZtLyWSTFM34U7t+BH0IZQ/IFul+wXktg5O6/WZ9aNqxHHsU9qqLhK0emt/zOE275dY KLAVHARpFGzLPSLtZdxxO0JXSJ89R9OU3ZKT+b4sTIKDW76DG3oULAPmEJrxGdTn55 +f6QLzq6dV4iPyAz9uMmMVTvzOAkTyE5UHy0hvWm2a+cz97NtE8FOKhVUA1RrU5+TN zDNxaAgGyvQew== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 09/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d Date: Fri, 21 May 2021 18:19:41 +0530 Message-Id: <20210521124946.3617862-13-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We cannot enable mode_3d when we are using the DSC. So pass configuration to detect DSC is enabled and not enable mode_3d when we are using DSC We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc enabled and pass this to .setup_intf_cfg() Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index ecbc4be98980..d43b804528eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -336,6 +336,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( return BLEND_3D_NONE; } +static inline bool dpu_encoder_helper_get_dsc_mode(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc = phys_enc->parent; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + + if (priv->dsc) + return true; + + return false; +} + /** * dpu_encoder_helper_split_config - split display configuration helper function * This helper function may be used by physical encoders to configure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2be39b9144e..5fe87881c30c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -69,6 +69,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); + intf_cfg.dsc = dpu_encoder_helper_get_dsc_mode(phys_enc); + ctl->ops.setup_intf_cfg(ctl, &intf_cfg); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index aeea6add61ee..f059416311ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -121,7 +121,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) return ctx->pending_flush_mask; } -static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) +static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); @@ -522,7 +522,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, intf_cfg |= (cfg->intf & 0xF) << 4; - if (cfg->mode_3d) { + /* In DSC we can't set merge, so check for dsc too */ + if (cfg->mode_3d && !cfg->dsc) { intf_cfg |= BIT(19); intf_cfg |= (cfg->mode_3d - 0x1) << 20; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..347a653c1e01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid + * @dsc: DSC is enabled * @stream_sel: Stream selection for multi-stream interfaces */ struct dpu_hw_intf_cfg { @@ -46,6 +47,7 @@ struct dpu_hw_intf_cfg { enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; + bool dsc; int stream_sel; }; From patchwork Fri May 21 12:49:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 040A0C433B4 for ; Fri, 21 May 2021 12:51:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD962613E1 for ; Fri, 21 May 2021 12:51:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234962AbhEUMwd (ORCPT ); Fri, 21 May 2021 08:52:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:34150 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234801AbhEUMwY (ORCPT ); Fri, 21 May 2021 08:52:24 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7ACF7613DF; Fri, 21 May 2021 12:50:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601461; bh=3WhEDhnS7RTHdaVDcW/UbFzQLps8YMMTUjDx51lcUJc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QUOI9BwLA3XMgriCsTlGzo4Ojgk83j2xh3TH+0xcN+5O5fIAkUABzXoaJdlQf6vCG oW5FnmkrOqfSTzAd54DiMtAQOvaA6sK3JdsXYk9AbXf8UHL2OBeFPgcvNf5MLL0zX6 oQjBXLuOXBOLXpuZT5E/uknzU2Nij7DukUEu9EtU4jN1IKVGzPRppyD+c30+j3+Jwp m+F0R9g8Cs+jRO3PSOrtyf0FeHe+2y+CoGBONDgEuKCPAemt2eElZrDNn7IjtaaJ1s ji4wo8YcaXsxWkU2IWXOGf4lzwdv7WCzI6+ELFjt2sX4pEqaPgr0IeWx0w80jXZolM jcxPW29wq5ECQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 10/13] drm/msm/disp/dpu1: Add support for DSC in encoder Date: Fri, 21 May 2021 18:19:43 +0530 Message-Id: <20210521124946.3617862-15-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When DSC is enabled in DT, we need to configure the encoder for DSC configuration, calculate DSC parameters for the given timing. This patch adds that support by adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled in DT Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 190 +++++++++++++++++++- 1 file changed, 189 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 8d942052db8a..18cb1274a8bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -21,12 +21,17 @@ #include "dpu_hw_intf.h" #include "dpu_hw_ctl.h" #include "dpu_hw_dspp.h" +#include "dpu_hw_dsc.h" #include "dpu_formats.h" #include "dpu_encoder_phys.h" #include "dpu_crtc.h" #include "dpu_trace.h" #include "dpu_core_irq.h" +#define DSC_MODE_SPLIT_PANEL BIT(0) +#define DSC_MODE_MULTIPLEX BIT(1) +#define DSC_MODE_VIDEO BIT(2) + #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) @@ -135,6 +140,7 @@ enum dpu_enc_rc_states { * @cur_slave: As above but for the slave encoder. * @hw_pp: Handle to the pingpong blocks used for the display. No. * pingpong blocks can be different than num_phys_encs. + * @hw_dsc Handle to the DSC blocks used for the display. * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped * for partial update right-only cases, such as pingpong * split where virtual pingpong does not generate IRQs @@ -180,6 +186,7 @@ struct dpu_encoder_virt { struct dpu_encoder_phys *cur_master; struct dpu_encoder_phys *cur_slave; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; bool intfs_swapped; @@ -566,6 +573,8 @@ static struct msm_display_topology dpu_encoder_get_topology( struct drm_display_mode *mode) { struct msm_display_topology topology = {0}; + struct drm_encoder *drm_enc; + struct msm_drm_private *priv; int i, intf_count = 0; for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) @@ -1008,7 +1017,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; - int num_lm, num_ctl, num_pp; + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; + int num_lm, num_ctl, num_pp, num_dsc; int i, j; if (!drm_enc) { @@ -1061,11 +1071,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->base.id, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL; + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL; + cstate = to_dpu_crtc_state(drm_crtc->state); for (i = 0; i < num_lm; i++) { @@ -1810,10 +1825,179 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) nsecs_to_jiffies(ktime_to_ns(wakeup_time))); } +static int dpu_encoder_dsc_update_pic_dim(struct msm_display_dsc_config *dsc, + int pic_width, int pic_height) +{ + if (!dsc || !pic_width || !pic_height) { + DPU_ERROR("invalid input: pic_width=%d pic_height=%d\n", + pic_width, pic_height); + return -EINVAL; + } + + if ((pic_width % dsc->drm.slice_width) || (pic_height % dsc->drm.slice_height)) { + DPU_ERROR("pic_dim=%dx%d has to be multiple of slice=%dx%d\n", + pic_width, pic_height, dsc->drm.slice_width, dsc->drm.slice_height); + return -EINVAL; + } + + dsc->drm.pic_width = pic_width; + dsc->drm.pic_height = pic_height; + + return 0; +} + +static void +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width) +{ + int slice_per_pkt, slice_per_intf; + int bytes_in_slice, total_bytes_per_intf; + + if (!dsc || !dsc->drm.slice_width || !dsc->slice_per_pkt) { + DPU_ERROR("Invalid DSC/slices\n"); + return; + } + + slice_per_pkt = dsc->slice_per_pkt; + slice_per_intf = DIV_ROUND_UP(width, dsc->drm.slice_width); + + /* + * If slice_per_pkt is greater than slice_per_intf then default to 1. + * This can happen during partial update. + */ + if (slice_per_pkt > slice_per_intf) + slice_per_pkt = 1; + + bytes_in_slice = DIV_ROUND_UP(dsc->drm.slice_width * + dsc->drm.bits_per_pixel, 8); + total_bytes_per_intf = bytes_in_slice * slice_per_intf; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3); + dsc->bytes_in_slice = bytes_in_slice; + dsc->bytes_per_pkt = bytes_in_slice * slice_per_pkt; + dsc->pkt_per_line = slice_per_intf / slice_per_pkt; +} + +static void +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc, + u32 enc_ip_width) +{ + int ssm_delay, total_pixels, soft_slice_per_enc; + + soft_slice_per_enc = enc_ip_width / dsc->drm.slice_width; + + /* + * minimum number of initial line pixels is a sum of: + * 1. sub-stream multiplexer delay (83 groups for 8bpc, + * 91 for 10 bpc) * 3 + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 + * 3. the initial xmit delay + * 4. total pipeline delay through the "lock step" of encoder (47) + * 5. 6 additional pixels as the output of the rate buffer is + * 48 bits wide + */ + ssm_delay = ((dsc->drm.bits_per_component < 10) ? 84 : 92); + total_pixels = ssm_delay * 3 + dsc->drm.initial_xmit_delay + 47; + if (soft_slice_per_enc > 1) + total_pixels += (ssm_delay * 3); + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm.slice_width); +} + +static bool +dpu_encoder_dsc_ich_reset_override_needed(struct msm_display_dsc_config *dsc, bool pu_en) +{ + /* As per the DSC spec, ICH_RESET can be either end of the slice line + * or at the end of the slice. HW internally generates ich_reset at + * end of the slice line if DSC_MERGE is used or encoder has two + * soft slices. However, if encoder has only 1 soft slice and DSC_MERGE + * is not used then it will generate ich_reset at the end of slice. + * + * Now as per the spec, during one PPS session, position where + * ich_reset is generated should not change. Now if full-screen frame + * has more than 1 soft slice then HW will automatically generate + * ich_reset at the end of slice_line. But for the same panel, if + * partial frame is enabled and only 1 encoder is used with 1 slice, + * then HW will generate ich_reset at end of the slice. This is a + * mismatch. Prevent this by overriding HW's decision. + */ + return pu_en && dsc && (dsc->drm.slice_count > 1) && + (dsc->drm.slice_width == dsc->drm.pic_width); +} + +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc, + struct dpu_hw_pingpong *hw_pp, + struct msm_display_dsc_config *dsc, + u32 common_mode, bool ich_reset) +{ + if (hw_dsc->ops.dsc_config) + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, ich_reset); + + if (hw_dsc->ops.dsc_config_thresh) + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); + + if (hw_pp->ops.setup_dsc) + hw_pp->ops.setup_dsc(hw_pp); + + if (hw_pp->ops.enable_dsc) + hw_pp->ops.enable_dsc(hw_pp); +} + +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, + struct msm_display_dsc_config *dsc) +{ + /* coding only for 2LM, 2enc, 1 dsc config */ + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; + int this_frame_slices; + int intf_ip_w, enc_ip_w; + int ich_res, dsc_common_mode; + int pic_width, pic_height; + int i; + + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { + hw_pp[i] = dpu_enc->hw_pp[i]; + hw_dsc[i] = dpu_enc->hw_dsc[i]; + + if (!hw_pp[i] || !hw_dsc[i]) { + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); + return; + } + } + + dsc_common_mode = 0; + pic_width = dsc->drm.pic_width; + pic_height = dsc->drm.pic_height; + + dpu_encoder_dsc_update_pic_dim(dsc, pic_width, pic_height); + + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; + if (enc_master->intf_mode == INTF_MODE_VIDEO) + dsc_common_mode |= DSC_MODE_VIDEO; + + this_frame_slices = pic_width / dsc->drm.slice_width; + intf_ip_w = this_frame_slices * dsc->drm.slice_width; + + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w); + + /* + * dsc merge case: when using 2 encoders for the same stream, + * no. of slices need to be same on both the encoders. + */ + enc_ip_w = intf_ip_w / 2; + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); + + ich_res = dpu_encoder_dsc_ich_reset_override_needed(dsc, false); + + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, ich_res); +} + void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; struct dpu_encoder_phys *phys; + struct msm_drm_private *priv; bool needs_hw_reset = false; unsigned int i; @@ -1841,6 +2025,10 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); } } + + priv = drm_enc->dev->dev_private; + if (priv->dsc) + dpu_encoder_prep_dsc(dpu_enc, priv->dsc); } void dpu_encoder_kickoff(struct drm_encoder *drm_enc) From patchwork Fri May 21 12:49:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 445945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6478DC43462 for ; Fri, 21 May 2021 12:51:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CA7D613E1 for ; Fri, 21 May 2021 12:51:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235195AbhEUMwf (ORCPT ); Fri, 21 May 2021 08:52:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:34520 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235021AbhEUMw2 (ORCPT ); Fri, 21 May 2021 08:52:28 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E14876128A; Fri, 21 May 2021 12:51:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601465; bh=eVVDh8nCN1Yb9AXj+WoqxP1WMiIq4cunVQYwXJ411+s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FB68gwgtGq+RZ4lPSxPU+13XhnB3Z1HeAi0q79m3DM6PjhpWtWjDip5fcFjxrhvM+ ol7wYkrEr/NS9MtlEPiMHD5yeRWP/rNHxZq/8s5zBSsycfFi/dKlY8U7G7Vp9LFHDK 0TPbbcvegHUcB+CFnPLq3eobXs3T2Qh0NrwKe3TXRhEBu9bWPlTlhlsmWZpbGuHNKV d+puPRLs5D9EuQjNB2ZGpFT8MHAOlRq50wK0+8TfTxTFhFHVKNumlwUfWr11TapcJp OHdKcxj4MVyXluooa23nXv8aiPKvyA1FHPCfRmUVf4GRGlqYtATn9Rt5czTjmcvivR q+TIbdNhsEpaQ== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 11/13] drm/msm/disp/dpu1: Add support for DSC in topology Date: Fri, 21 May 2021 18:19:44 +0530 Message-Id: <20210521124946.3617862-16-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For DSC to work we typically need a 2,2,1 configuration. This should suffice for resolutions upto 4k. For more resolutions like 8k this won't work. Furthermore, we can use 1 DSC encoder in lesser resulutions, but that is not power efficient according to Abhinav, so it is recommended to always use 2 encoders. So for now we blindly create 2,2,1 topology when DSC is enabled Co-developed-by: Abhinav Kumar Signed-off-by: Abhinav Kumar Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 18cb1274a8bb..bffb40085c67 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -609,8 +609,22 @@ static struct msm_display_topology dpu_encoder_get_topology( topology.num_enc = 0; topology.num_intf = intf_count; + drm_enc = &dpu_enc->base; + priv = drm_enc->dev->dev_private; + if (priv && priv->dsc) { + /* In case of Display Stream Compression DSC, we would use + * 2 encoders, 2 line mixers and 1 interface + * this is power optimal and can drive upto (including) 4k + * screens + */ + topology.num_enc = 2; + topology.num_intf = 1; + topology.num_lm = 2; + } + return topology; } + static int dpu_encoder_virt_atomic_check( struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state, From patchwork Fri May 21 12:49:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88976C433ED for ; Fri, 21 May 2021 12:51:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70225613DD for ; Fri, 21 May 2021 12:51:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234695AbhEUMwo (ORCPT ); Fri, 21 May 2021 08:52:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:34372 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235118AbhEUMwc (ORCPT ); Fri, 21 May 2021 08:52:32 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4F988613DE; Fri, 21 May 2021 12:51:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601470; bh=VAT+6TRJEy5p0xfa5NF7lAjHEvfhUuINzi99UFg1nws=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X8O9zxzzqcVkrceHF1QQ7lUyOOIQ3/UO3b+ofCxLgjbpBSwrJjyrYCiBsMaK1GtGy wqR6MB60CNfHqvN2Hn+LkUBOUeG9zHp11zOvgOM8hNKLKLB9NueARrqs/WEjW9W7c/ xNt8gFm1l6evsvj/lRNbkieAphJ3BzcucWhL9HOBr7Ozo85EQhVsxf0UAOsujYjWa4 CIv7rZPhk1kbYlG10oRUFMbeLYu5odGzqLQ7OMugPnLW3oFNC9CKN4Lo79WuFuioMR myP13sivRYBMcnrjwlhD7Aq7YnAsq3D8O14G0ecovFs5pziMtP+c+4lm5INLDlQbu0 SN24pwojeUbSw== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 12/13] drm/msm/dsi: Add support for DSC configuration Date: Fri, 21 May 2021 18:19:45 +0530 Message-Id: <20210521124946.3617862-17-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When DSC is enabled, we need to configure DSI registers accordingly and configure the respective stream compression registers. Add support to calculate the register setting based on DSC params and timing information and configure these registers. Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++ drivers/gpu/drm/msm/dsi/dsi_host.c | 118 ++++++++++++++++++++++++++--- 2 files changed, 118 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 50eb4d1b8fdd..b8e9e608abfc 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -2310,4 +2310,14 @@ static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000 #define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c + +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0 + +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4 + +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8 + +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac + #endif /* DSI_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 864d3c655e73..e26545fc82e0 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -954,6 +954,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) u32 va_end = va_start + mode->vdisplay; u32 hdisplay = mode->hdisplay; u32 wc; + u32 data; DBG(""); @@ -972,7 +973,69 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) hdisplay /= 2; } + if (msm_host->dsc) { + struct msm_display_dsc_config *dsc = msm_host->dsc; + + /* update dsc params with timing params */ + dsc->drm.pic_width = mode->hdisplay; + dsc->drm.pic_height = mode->vdisplay; + + /* Divide the display by 3 but keep back/font porch and + * pulse width same + */ + h_total -= hdisplay; + hdisplay /= 3; + h_total += hdisplay; + ha_end = ha_start + hdisplay; + } + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { + if (msm_host->dsc) { + struct msm_display_dsc_config *dsc = msm_host->dsc; + u32 reg, intf_width, slice_per_intf, width; + u32 total_bytes_per_intf; + + /* first calculate dsc parameters and then program + * compress mode registers + */ + intf_width = hdisplay; + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm.slice_width); + + /* If slice_per_pkt > slice_per_intf, then use 1 + * This can happen during partial update + */ + if (dsc->slice_per_pkt > slice_per_intf) + dsc->slice_per_pkt = 1; + + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm.slice_width * 8, 8); + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3); + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->slice_per_pkt; + dsc->pkt_per_line = slice_per_intf / dsc->slice_per_pkt; + + width = dsc->pclk_per_line; + reg = dsc->bytes_per_pkt << 16; + reg |= (0x0b << 8); /* dtype of compressed image */ + + /* pkt_per_line: + * 0 == 1 pkt + * 1 == 2 pkt + * 2 == 4 pkt + * 3 pkt is not supported + * above translates to ffs() - 1 + */ + reg |= (ffs(dsc->pkt_per_line) - 1) << 6; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + reg |= dsc->eol_byte_num << 4; + reg |= 1; + + dsi_write(msm_host, + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); + } + dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -991,19 +1054,50 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ + if (msm_host->dsc) { + struct msm_display_dsc_config *dsc = msm_host->dsc; + u32 reg, reg_ctrl, reg_ctrl2; + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf; + + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); + + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm.slice_width); + bytes_in_slice = DIV_ROUND_UP(dsc->drm.slice_width * + dsc->drm.bits_per_pixel, 8); + dsc->drm.slice_chunk_size = bytes_in_slice; + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; + dsc->pkt_per_line = slice_per_intf / dsc->slice_per_pkt; + + reg = 0x39 << 8; + reg |= ffs(dsc->pkt_per_line) << 6; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + reg |= dsc->eol_byte_num << 4; + reg |= 1; + + reg_ctrl |= reg; + reg_ctrl2 |= bytes_in_slice; + + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg); + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); + } + /* image data and 1 byte write_memory_start cmd */ - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; + if (!msm_host->dsc) + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; + else + wc = mode->hdisplay / 2 + 1; + + data = DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | + DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(msm_host->channel) | + DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(MIPI_DSI_DCS_LONG_WRITE); - dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, - DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | - DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( - msm_host->channel) | - DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( - MIPI_DSI_DCS_LONG_WRITE)); + dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, data); - dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, - DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | - DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); + data = DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | + DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay); + dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, data); } } @@ -2111,6 +2205,7 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; struct platform_device *pdev = msm_host->pdev; + struct msm_drm_private *priv; int ret; msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); @@ -2130,6 +2225,9 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, } msm_host->dev = dev; + priv = dev->dev_private; + priv->dsc = msm_host->dsc; + ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); if (ret) { pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); From patchwork Fri May 21 12:49:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 445944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FB00C43460 for ; Fri, 21 May 2021 12:51:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6EE2961353 for ; Fri, 21 May 2021 12:51:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235409AbhEUMxD (ORCPT ); Fri, 21 May 2021 08:53:03 -0400 Received: from mail.kernel.org ([198.145.29.99]:34838 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235214AbhEUMwh (ORCPT ); Fri, 21 May 2021 08:52:37 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id B158B613DF; Fri, 21 May 2021 12:51:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601474; bh=jEvngLW/cjGIBmD812MSfH6Z7qHrHgE9F0mc+LlnVCU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eYH2aO+avVrOJeVmpIWkod3vEau0fORf9Df3DZDMoskPVFvaUvPY+5szCcRutxyor my/mvi2OEBri3/ZHX84NlAG9J6Zi50Ukj4foiizCf540o36gs0yeyf2JOAjTkENiKr IEkFzsYiZ51NtQuzVrPhuQb3pDd/zTwNRyYjDAvn/zDDr82dpjYXzpg2ANpeadLb4Q vYGPdPWRxaonJ8oCAhedKvcyTFZrD0KLhqfFPSqGJF1QfvlPokiljPLqAx4I8l/h9j mGurVFDjsR6red27U+RBw8U0+HIeCtypozMPYBw84krdbWWpiGGB+LADU0cOc4AbTa erFTEMQAFEt+Q== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH 13/13] drm/msm/dsi: Pass DSC params to drm_panel Date: Fri, 21 May 2021 18:19:46 +0530 Message-Id: <20210521124946.3617862-18-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When DSC is enabled, we need to pass the DSC parameters to panel driver as well, so add a dsc parameter in panel and set it when DSC is enabled Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/dsi/dsi_host.c | 5 +++++ include/drm/drm_panel.h | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index e26545fc82e0..7fc7002eda78 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1700,6 +1700,7 @@ static int dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + struct drm_panel *panel; int ret; if (dsi->lanes > msm_host->num_data_lanes) @@ -1719,6 +1720,10 @@ static int dsi_host_attach(struct mipi_dsi_host *host, if (msm_host->dev) queue_work(msm_host->workqueue, &msm_host->hpd_work); + panel = msm_dsi_host_get_panel(host); + if (panel) + panel->dsc = &msm_host->dsc->drm; + return 0; } diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h index 33605c3f0eba..27a7808a29f2 100644 --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -171,6 +171,13 @@ struct drm_panel { * Panel entry in registry. */ struct list_head list; + + /** + * @dsc: + * + * Panel DSC pps payload to be sent + */ + struct drm_dsc_config *dsc; }; void drm_panel_init(struct drm_panel *panel, struct device *dev,