From patchwork Thu May 20 23:07:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8564CC43470 for ; Thu, 20 May 2021 23:08:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 686E4613B6 for ; Thu, 20 May 2021 23:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232585AbhETXKE (ORCPT ); Thu, 20 May 2021 19:10:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233113AbhETXKD (ORCPT ); Thu, 20 May 2021 19:10:03 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8156EC061761; Thu, 20 May 2021 16:08:40 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id a2so26881190lfc.9; Thu, 20 May 2021 16:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4wjkerGjnODWZW9w3YSKmK8x5ot3hbK6hwMuTDmldcE=; b=eY+JcN50EErXfJJBHxuOt6AxKLX5cM00mV5NGLoPgAIKNZxqPRMaG0FnienMoaG5SV /+kB14sss/j2hn7khi3mnGNY+hu8x0EtJv3xy56MOyqGQBVl2tLnuGTrwjIAX/O01ecn q0ytzsaDaJ73gmOfBgsWjCdaF/jzKEioVYEpaYVDdNyorgAjLfGcBBC/nx+d6kD8FseV mmfdHzk2NwbKtQXNEzJ3kSg97304srhrirFdZyi23nkpgHPtfaL4xf/TdlIKx2hGM3SK jPjG8EwnRTuzzNMW0Tu6Rfk+XIku5nIqPNTUdVLlPHtJ8twLHFphwhR4AcZpQXbGWfYW PlFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4wjkerGjnODWZW9w3YSKmK8x5ot3hbK6hwMuTDmldcE=; b=D5W54YktIo5eeZ3J+PzEF3NZr9ynK52JxEUfNkJCnhfVw5flmhN8s0BoLsrIk5zEuF /utlOP97IoHFoF5JCOR33lC2VXU8hoZ54qR2Su22+8hBpB7cK465nSFFCvOjPQ7k7zzF LhAJa53V2o+JVGC+qJMC4rA6oz+Trf15Wes2cQKclfd+Bo+T5PqoKq9+f+FHQxEnhoRY YUff0LOqQxUGqbvUTxlw1bBzvX0Qra7SoFvaxtEzySVlinEQyDcCWs19F2gc5LK5Ur2J bbbma8MKEHj90WwnJvtgfvGEp7GWYCvGlnh6TiFVwyyINXm2wAwFwUhfTE1fH1B/ccyz 9dUw== X-Gm-Message-State: AOAM5304SDb4lXgblePiTc0M3BcyQx8P/3dLlnFz4Ga0gXfcL+0UAszL xvJthSrXaVzeoUcWPKnVyxk= X-Google-Smtp-Source: ABdhPJyIlz9t4Ds3YgggFlv9Ncz2YTCg7pWLILTlZ7oCF4wxyxUhe0yQiOCr2vbdtbuhCU1robe2hw== X-Received: by 2002:ac2:5289:: with SMTP id q9mr4613760lfm.141.1621552118935; Thu, 20 May 2021 16:08:38 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:38 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 01/13] regulator: core: Add regulator_sync_voltage_rdev() Date: Fri, 21 May 2021 02:07:39 +0300 Message-Id: <20210520230751.26848-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Some NVIDIA Tegra devices use a CPU soft-reset method for the reboot and in this case we need to restore the coupled voltages to the state that is suitable for hardware during boot. Add new regulator_sync_voltage_rdev() helper which is needed by regulator drivers in order to sync voltage of a coupled regulators. Acked-by: Mark Brown Signed-off-by: Dmitry Osipenko --- drivers/regulator/core.c | 23 +++++++++++++++++++++++ include/linux/regulator/driver.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index f192bf19492e..ead0b6d2af45 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -4105,6 +4105,29 @@ int regulator_set_voltage_time_sel(struct regulator_dev *rdev, } EXPORT_SYMBOL_GPL(regulator_set_voltage_time_sel); +int regulator_sync_voltage_rdev(struct regulator_dev *rdev) +{ + int ret; + + regulator_lock(rdev); + + if (!rdev->desc->ops->set_voltage && + !rdev->desc->ops->set_voltage_sel) { + ret = -EINVAL; + goto out; + } + + /* balance only, if regulator is coupled */ + if (rdev->coupling_desc.n_coupled > 1) + ret = regulator_balance_voltage(rdev, PM_SUSPEND_ON); + else + ret = -EOPNOTSUPP; + +out: + regulator_unlock(rdev); + return ret; +} + /** * regulator_sync_voltage - re-apply last regulator output voltage * @regulator: regulator source diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index 4ea520c248e9..35e5a611db81 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -540,6 +540,7 @@ int regulator_set_current_limit_regmap(struct regulator_dev *rdev, int regulator_get_current_limit_regmap(struct regulator_dev *rdev); void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay); +int regulator_sync_voltage_rdev(struct regulator_dev *rdev); /* * Helper functions intended to be used by regulator drivers prior registering From patchwork Thu May 20 23:07:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0061AC433ED for ; Thu, 20 May 2021 23:08:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F0500611AE for ; Thu, 20 May 2021 23:08:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233176AbhETXKF (ORCPT ); Thu, 20 May 2021 19:10:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233153AbhETXKF (ORCPT ); Thu, 20 May 2021 19:10:05 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4858C061761; Thu, 20 May 2021 16:08:42 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id v8so21919859lft.8; Thu, 20 May 2021 16:08:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PZ7rCy2VE/t2KfttY6Z1tGootvL+h1fkg+mpjvNoBrY=; b=PeeRFLmZ8TfYZ0GQg6iH6bin0T0xVY/jqEd73UEXmr4dg6GlvydWE8xF2wWkWC00q2 WUHBXTKMbMdw5MvVrgFfp/w+9p9K2oVN7hPN/Bwmqj+VOu2AtKlh4GmP750h3FzFLvt0 6M02EjPDkcS0DD6XP80R89DkilSTNLIf/naW7Fm6W7IOd21uMxSzhLPsdQLGtedGoNl8 SXW9ugRaKqzmX68Ez+mu3DjPj8FtkSglqm5sj3zMj9Jo1TQ8NmXhiZrn58NnAWDHqyR8 N7mWZs2i/U+3KEG0azqWRFZtmsbqUCVXlY5j6im5hBZJa6VrtchVKoVgL7JfsqTKTKxB mwog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PZ7rCy2VE/t2KfttY6Z1tGootvL+h1fkg+mpjvNoBrY=; b=bmfya/k/2fP8iVzlYR/4s2wcrW5W+XpHBvYJuebzkffQWXpAIMzezjyYX7TluLfkZI E5QRkocjWBAHbABzkQdRtFHjl1mLF5T1maLqL9EbC1voogwYuCydOLD/BpvqjndvAqb1 M5hUCdzOLjjyIup+eo1HkQFZD5C9szgKnLNK+3sozd9LGMjEGoqpu0CZW61oZmroU6dF YhRdxXQOjPfrGR+4/WRilpXYKc9cVmvS7liVvX5zw4IiAAmOy7ixGUUdaBnnKB/v+Kho PD/UllPKrsLk5vA9X+3ZuASH/LZ28DNj53rvjXbjrAB/zA0BfKnv4PY62PT1VxpViR7R x81w== X-Gm-Message-State: AOAM5329VoIxXW7JrJdB0zUHRP1EUKiGYEp/4mfIdXpQJSbGF3cNCV6U PsSOgVnh3ta4y2zmn95QxcQ= X-Google-Smtp-Source: ABdhPJx0EilwJMtqaOHlPCOecysO9SMYaZpGuzqOf68nFRPexJLbkCYWarSwMAKdV6aJqE5OA0bsDQ== X-Received: by 2002:ac2:4906:: with SMTP id n6mr4668917lfi.352.1621552121344; Thu, 20 May 2021 16:08:41 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 03/13] soc/tegra: Add stub for soc_is_tegra() Date: Fri, 21 May 2021 02:07:41 +0300 Message-Id: <20210520230751.26848-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add stub required for compile-testing of drivers. Signed-off-by: Dmitry Osipenko --- include/soc/tegra/common.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 98027a76ce3d..744280ecab5f 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,6 +6,15 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__ +#include + +#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +#else +static inline bool soc_is_tegra(void) +{ + return false; +} +#endif #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Thu May 20 23:07:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A840C43617 for ; Thu, 20 May 2021 23:08:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A016613CA for ; Thu, 20 May 2021 23:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233251AbhETXKM (ORCPT ); Thu, 20 May 2021 19:10:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233232AbhETXKH (ORCPT ); Thu, 20 May 2021 19:10:07 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA09C061761; Thu, 20 May 2021 16:08:44 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id w15so21770435ljo.10; Thu, 20 May 2021 16:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ru1Y5AhCOlhA7q2BKIbg+3l43tX1d5MlWRnc4jqFnM=; b=t4DPbheCJLYB6Y2YvuMw8oTIGEInCL4pXOndvs24PIpcVEDFDWYQsS782+HuvSZBot FiqPAPURVwCbVbIV1QAcMvf/q9gHOglllhrj6EzPjOSdJImXSrOuCC16Qo/tjJUsK4Yt 4hXAf7LApyp6ilHDhM4u0dYt4iaElkjpxnwvuv1p7HVvNf5Faz1GR0HTaK1WSKoDBuo7 JO6UDJZhVnE8+k7TnHw2wiuwlaWg3oNbe0U0vinIC5A0K+X4IQwDl9wVPY5HFnmIRv7n 4Om3sHsdVfMy+nsM9l48a/oK1ghM3GFkF3xaB6VtwNuAh9NmDOna+ubS4ZHN9nTHTlti 4KuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ru1Y5AhCOlhA7q2BKIbg+3l43tX1d5MlWRnc4jqFnM=; b=NNabUAHUbyf9nW4oNr3HsfIgjyVBWmpQC+bPU1ZINIjsua0KgA9EJFfJsFEIqJ5pmU bLzbKO0vigOWDMPhen6v8BXwIw/+xcla+kIsDaR/db2eZRFO2bOE2p2FvmZQi2ycZvFc vS/huZHAXrHB+WMUW1elRmWPP+HF/jgZzXKl12Enog+5IhQOmkU377brzKhR0PCPOA1y 3wIc47g5DDERUMFr657qRce22fHe49BsSuNF80g5rgukl1y6Oxww1shZZr7e1X/nSoin r8k6SnpjZs3shInKVrdOkkvtD9+cSL821CWYWbKOWIg50ppuKf8Zlj9JFRZaAk0Y4JML TKzg== X-Gm-Message-State: AOAM533x0cClX/6Ar9hAS4Q24TEV6vkp77x5PahetznueIrit7XCAaK5 x4vUqnNiz5FeGLV1TGOvEeU= X-Google-Smtp-Source: ABdhPJw/ysGQ7427eYQET0NAy6+evYOUqKtx2xtDlmMkJLzkbdWOfRMxbxW9hh0/e2L5YHJAOiwryA== X-Received: by 2002:a2e:a0cb:: with SMTP id f11mr4675154ljm.72.1621552122338; Thu, 20 May 2021 16:08:42 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 04/13] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Date: Fri, 21 May 2021 02:07:42 +0300 Message-Id: <20210520230751.26848-5-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add common helper which initializes OPP table for Tegra SoC core devices. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/common.c | 97 ++++++++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 22 +++++++++ 2 files changed, 119 insertions(+) diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 3dc54f59cafe..cd33e99249c3 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -3,9 +3,16 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ +#define dev_fmt(fmt) "tegra-soc: " fmt + +#include +#include +#include #include +#include #include +#include static const struct of_device_id tegra_machine_match[] = { { .compatible = "nvidia,tegra20", }, @@ -31,3 +38,93 @@ bool soc_is_tegra(void) return match != NULL; } + +static int tegra_core_dev_init_opp_state(struct device *dev) +{ + unsigned long rate; + struct clk *clk; + int err; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clk: %pe\n", clk); + return PTR_ERR(clk); + } + + rate = clk_get_rate(clk); + if (!rate) { + dev_err(dev, "failed to get clk rate\n"); + return -EINVAL; + } + + /* first dummy rate-setting initializes voltage vote */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + return err; + } + + return 0; +} + +/** + * devm_tegra_core_dev_init_opp_table() - initialize OPP table + * @dev: device for which OPP table is initialized + * @params: pointer to the OPP table configuration + * + * This function will initialize OPP table and sync OPP state of a Tegra SoC + * core device. + * + * Return: 0 on success or errorno. + */ +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + u32 hw_version; + int err; + + err = devm_pm_opp_set_clkname(dev, NULL); + if (err) { + dev_err(dev, "failed to set OPP clk: %d\n", err); + return err; + } + + /* Tegra114+ doesn't support OPP yet */ + if (!of_machine_is_compatible("nvidia,tegra20") && + !of_machine_is_compatible("nvidia,tegra30")) + return -ENODEV; + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + err = devm_pm_opp_set_supported_hw(dev, &hw_version, 1); + if (err) { + dev_err(dev, "failed to set OPP supported HW: %d\n", err); + return err; + } + + /* + * Older device-trees have an empty OPP table, we will get + * -ENODEV from devm_pm_opp_of_add_table() in this case. + */ + err = devm_pm_opp_of_add_table(dev); + if (err) { + if (err == -ENODEV) + dev_err_once(dev, "OPP table not found, please update device-tree\n"); + else + dev_err(dev, "failed to add OPP table: %d\n", err); + + return err; + } + + if (params->init_state) { + err = tegra_core_dev_init_opp_state(dev); + if (err) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 744280ecab5f..af41ad80ec21 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,15 +6,37 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__ +#include #include +struct device; + +/** + * Tegra SoC core device OPP table configuration + * + * @init_state: pre-initialize OPP state of a device + */ +struct tegra_core_opp_params { + bool init_state; +}; + #ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); + +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params); #else static inline bool soc_is_tegra(void) { return false; } + +static inline int +devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + return -ENODEV; +} #endif #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Thu May 20 23:07:44 2021 Content-Type: text/plain; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:44 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 06/13] clk: tegra: Add stubs needed for compile-testing Date: Fri, 21 May 2021 02:07:44 +0300 Message-Id: <20210520230751.26848-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add stubs needed for compile-testing of Tegra memory drivers. Signed-off-by: Dmitry Osipenko --- include/linux/clk/tegra.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index f7ff722a03dd..d540b2879c26 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -144,17 +144,37 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, unsigned long max_rate, void *arg); +typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +#ifdef CONFIG_ARCH_TEGRA void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, void *cb_arg); int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); -typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, - unsigned long rate); -typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, - unsigned long rate); void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, tegra124_emc_complete_timing_change_cb *complete_cb); +#else +static inline void +tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, + void *cb_arg) +{ +} + +static inline int +tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) +{ + return 0; +} + +static inline void +tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) +{ +} +#endif struct tegra210_clk_emc_config { unsigned long rate; From patchwork Thu May 20 23:07:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A20EBC4363F for ; Thu, 20 May 2021 23:08:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8303E613CA for ; Thu, 20 May 2021 23:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233153AbhETXKS (ORCPT ); Thu, 20 May 2021 19:10:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233197AbhETXKK (ORCPT ); Thu, 20 May 2021 19:10:10 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A25CC061763; Thu, 20 May 2021 16:08:48 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id q7so25562068lfr.6; Thu, 20 May 2021 16:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CLef4wehN1atwulqXH4JMD3Wb9mRwmm7RCBYkfihR6M=; b=XuxxZV+UsNtRpkov9Sh86zbp1PDi+43UKiTfPCa8AAo9V/O2rI0vopCFIxNhG27v8R G7J/7I20w7avnQ50Hd7bproQUrwCf3fOA7Cm7RyjV4z+GkcjaO33TAJbu08MLDtxlqI5 XTO97Mg7X2xu5uzNyZU6Jj8FT7EVJGXr/kDLK2A3DZRAcV+ROTTFdN/xqplrITPhpTmH rdZRXuptqNgjWYRODDEm1fJpI6GLvErzBLcY0H6UHjqJMMISDAvYTvFeRrMUprPcTCtk JaF9YwfFPT+rubfhOW4NyufAwl1agaTRRYH6Jc4QiOqHF4ke/E7FH8FJHf0N3Jf8mc1Q DV+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CLef4wehN1atwulqXH4JMD3Wb9mRwmm7RCBYkfihR6M=; b=ZbvnxKi4PEDPJgve/W1PqE0zOqHX4XFNOjdQ16pr18LznWTAhTyE3gkpc5lgHmWbCa xOfpowRncL/Cjyo3sYj7C6A7opFcZBoTUIH3hX5ztTC2Z8m+LJOY0wEdKByXdj/TGOlI pD5UX6EkY26qyU3tKzo61em9WbQW1rhHplPf4ckFOmtQagmmoPiCnMPgPbeXwerPadyo wp6HjP3pZk095Fl+Eq0X/0WmQhLlaNmUHjayje5dAMrAj5IToF3ZwS1SYgV6GZl3G8EV BoGUuzJdmFtu0tTBtnW7ZkDzsB661OzLY33YeI2q3YBP7ptYo5PH1D60Tv40HryUpvC4 RpXw== X-Gm-Message-State: AOAM532C00SulXDxbEcGiTFgSungLRf6uowF+PTInHIPFDZHepODVCtM knDGi9FNLDXT5NPo3HTjm6g= X-Google-Smtp-Source: ABdhPJw6yrdHBR/OfktJ4jUtzPkIGTTiGC1DIM0+sGbXA5lnzbIBHKd9s4LrtFgo6JvJ4rP/jxovtg== X-Received: by 2002:a19:c3d1:: with SMTP id t200mr4483967lff.421.1621552126852; Thu, 20 May 2021 16:08:46 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:46 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 08/13] memory: tegra: Enable compile testing for all drivers Date: Fri, 21 May 2021 02:07:46 +0300 Message-Id: <20210520230751.26848-9-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable compile testing for all Tegra memory drivers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index a70967a56e52..c63ffa74ab94 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -2,16 +2,18 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y - depends on ARCH_TEGRA + depends on ARCH_TEGRA || COMPILE_TEST select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. +if TEGRA_MC + config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST select DEVFREQ_GOV_SIMPLE_ONDEMAND select PM_DEVFREQ help @@ -23,7 +25,7 @@ config TEGRA20_EMC config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST select PM_OPP help This driver is for the External Memory Controller (EMC) found on @@ -34,8 +36,8 @@ config TEGRA30_EMC config TEGRA124_EMC tristate "NVIDIA Tegra124 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_124_SOC - select TEGRA124_CLK_EMC + depends on ARCH_TEGRA_124_SOC || COMPILE_TEST + select TEGRA124_CLK_EMC if ARCH_TEGRA select PM_OPP help This driver is for the External Memory Controller (EMC) found on @@ -49,10 +51,12 @@ config TEGRA210_EMC_TABLE config TEGRA210_EMC tristate "NVIDIA Tegra210 External Memory Controller driver" - depends on TEGRA_MC && ARCH_TEGRA_210_SOC + depends on ARCH_TEGRA_210_SOC || COMPILE_TEST select TEGRA210_EMC_TABLE help This driver is for the External Memory Controller (EMC) found on Tegra210 chips. The EMC controls the external DRAM on the board. This driver is required to change memory timings / clock rate for external memory. + +endif From patchwork Thu May 20 23:07:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92D8CC433ED for ; Thu, 20 May 2021 23:09:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83AF5613C4 for ; Thu, 20 May 2021 23:09:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233696AbhETXKV (ORCPT ); Thu, 20 May 2021 19:10:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233414AbhETXKO (ORCPT ); Thu, 20 May 2021 19:10:14 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89420C06138E; Thu, 20 May 2021 16:08:51 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id c15so21775056ljr.7; Thu, 20 May 2021 16:08:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lkke/HcONrz1nur5ujlnw3lyx3GmqHu2azh4sgzjwjI=; b=dc5zdhHqU0+LUEcAkUQQErD7HDoaZp37aXI5yU3KLyl8P2h3O79/tcb+YHwpYl36wp sQKequVns1AZ3lp/zLB9VYS+NIw+PhSIk7AEeGVLUfLVB8ZiqUZrx26D8g3ob7Mkbp8P kjSf/jfwoVUAWMU+Q06Fpibn3Z8thPLiNeuduEVkwXNWWnmD+6CB0TVRL44bp+dddPNs ka0oJvNpnNt/g8Q23B3E56OsCEi694G5bGbyXzl95KEm1KC46uuPLSs+kq86SnkFgEeN ALbjDVHeCfHqv+V9cccdp8lQkMTS7auRFkc09TRHcIibKzWBa8OdGUEnsfay22IAWCWH 7Hdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lkke/HcONrz1nur5ujlnw3lyx3GmqHu2azh4sgzjwjI=; b=c6nb9m8PKVEkHps8qizKGwAVGcbmhU6YDzIWwserrZ4aPP9SU0ngiEkewsYgHdQOLM dXet/rLCcoC7ajWop+wub9bCDrWoWuJ37rjNQXY4Y0f07uFWTZ8IWdAp6U+dYDiEoTLW Wt0Jhvpg/SchYKJsBrIdBiiJVn0BCY0Rgvi5KzEgsCDaVVDgxcaIHpSxYWQcGO39jNNN kVWJyoPS+M1GgEV19Iwsihp3FJhEtV+JfYH8k6jfvpemn7viArcjkORoU63UEZXkCPjU GLdHfoccNTYbF5J2A2A42dLSXHlUfInAPOeZbFNz6VuKTDQGN0l46IK6Wu/RTqvh2TMI hXkg== X-Gm-Message-State: AOAM533J506Eg6HX/H+kKb9TprCQsBEe/wpQAgnTBRjOfzEdB1j1w11U XunqxL/ZjfvtxWzjIxq5TvE= X-Google-Smtp-Source: ABdhPJy9pwti41z22kCUOZd9W/EHVVqYpH7wzkEFwJKtBSOBK11OfKUN0Girh6l4Pi6D5L0P83LaGA== X-Received: by 2002:a2e:8859:: with SMTP id z25mr4731480ljj.186.1621552129957; Thu, 20 May 2021 16:08:49 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 11/13] dt-bindings: soc: tegra-pmc: Document core power domain Date: Fri, 21 May 2021 02:07:49 +0300 Message-Id: <20210520230751.26848-12-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Document the new core power domain properties. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 43fd2f8927d0..0afec83cc723 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -301,6 +301,33 @@ patternProperties: additionalProperties: false + core-domain: + type: object + description: | + The vast majority of hardware blocks of Tegra SoC belong to a + Core power domain, which has a dedicated voltage rail that powers + the blocks. + + properties: + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + required: - compatible - reg @@ -325,6 +352,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x7000e400 0x400>; + core-supply = <®ulator>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; @@ -338,17 +366,24 @@ examples: nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; resets = <&tegra_car 198>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; }; From patchwork Thu May 20 23:07:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BC18C2B9FB for ; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:50 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 12/13] soc/tegra: pmc: Add core power domain Date: Fri, 21 May 2021 02:07:50 +0300 Message-Id: <20210520230751.26848-13-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org NVIDIA Tegra SoCs have multiple power domains, each domain corresponds to an external SoC power rail. Core power domain covers vast majority of hardware blocks within a Tegra SoC. The voltage of a power domain should be set to a level which satisfies all devices within the power domain. Add support for the core power domain which controls voltage state of the domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs. The PMC powergate domains now are sub-domains of the core domain, this requires device-tree updating, older DTBs are unaffected. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/Kconfig | 14 ++++ drivers/soc/tegra/pmc.c | 143 +++++++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 7 ++ 3 files changed, 164 insertions(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 976dee036470..7057254604ee 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA20_VOLTAGE_COUPLER @@ -27,6 +28,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA30_VOLTAGE_COUPLER @@ -40,6 +42,7 @@ config ARCH_TEGRA_114_SOC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -51,6 +54,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -66,6 +70,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help @@ -77,6 +82,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -99,6 +105,7 @@ config ARCH_TEGRA_186_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a @@ -115,6 +122,7 @@ config ARCH_TEGRA_194_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra194 SoC. @@ -125,6 +133,7 @@ config ARCH_TEGRA_234_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra234 SoC. @@ -132,6 +141,11 @@ config ARCH_TEGRA_234_SOC endif endif +config SOC_TEGRA_COMMON + bool + select PM_OPP + select PM_GENERIC_DOMAINS + config SOC_TEGRA_FUSE def_bool y depends on ARCH_TEGRA diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 8e3b78bb2ac2..33b6e0885020 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -428,6 +429,8 @@ struct tegra_pmc { struct irq_chip irq; struct notifier_block clk_nb; + + bool core_domain_state_synced; }; static struct tegra_pmc *pmc = &(struct tegra_pmc) { @@ -1302,12 +1305,115 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) return err; } +bool tegra_soc_core_domain_state_synced(void) +{ + return pmc->core_domain_state_synced; +} + +static int +tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, + unsigned int level) +{ + struct dev_pm_opp *opp; + int err; + + opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); + if (IS_ERR(opp)) { + dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", + level, opp); + return PTR_ERR(opp); + } + + mutex_lock(&pmc->powergates_lock); + err = dev_pm_opp_set_opp(pmc->dev, opp); + mutex_unlock(&pmc->powergates_lock); + + dev_pm_opp_put(opp); + + if (err) { + dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", + level, err); + return err; + } + + return 0; +} + +static unsigned int +tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd, + struct dev_pm_opp *opp) +{ + return dev_pm_opp_get_level(opp); +} + +static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) +{ + static struct lock_class_key tegra_core_domain_lock_class; + struct generic_pm_domain *genpd; + const char *rname = "core"; + int err; + + genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = np->name; + genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; + genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; + + err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1); + if (err) + return dev_err_probe(pmc->dev, err, + "failed to set core OPP regulator\n"); + + err = pm_genpd_init(genpd, NULL, false); + if (err) { + dev_err(pmc->dev, "failed to init core genpd: %d\n", err); + return err; + } + + /* + * We have a "PMC pwrgate -> Core" hierarchy of the power domains + * where PMC needs to resume and change performance (voltage) of the + * Core domain from the PMC GENPD on/off callbacks, hence we need + * to annotate the lock in order to remove confusion from the + * lockdep checker when a nested access happens. + */ + lockdep_set_class(&genpd->mlock, &tegra_core_domain_lock_class); + + err = of_genpd_add_provider_simple(np, genpd); + if (err) { + dev_err(pmc->dev, "failed to add core genpd: %d\n", err); + goto remove_genpd; + } + + return 0; + +remove_genpd: + pm_genpd_remove(genpd); + + return err; +} + static int tegra_powergate_init(struct tegra_pmc *pmc, struct device_node *parent) { + struct of_phandle_args child_args, parent_args; struct device_node *np, *child; int err = 0; + /* + * Core power domain is the parent of powergate domains, hence it + * should be registered first. + */ + np = of_get_child_by_name(parent, "core-domain"); + if (np) { + err = tegra_pmc_core_pd_add(pmc, np); + of_node_put(np); + if (err) + return err; + } + np = of_get_child_by_name(parent, "powergates"); if (!np) return 0; @@ -1318,6 +1424,21 @@ static int tegra_powergate_init(struct tegra_pmc *pmc, of_node_put(child); break; } + + if (of_parse_phandle_with_args(child, "power-domains", + "#power-domain-cells", + 0, &parent_args)) + continue; + + child_args.np = child; + child_args.args_count = 0; + + err = of_genpd_add_subdomain(&parent_args, &child_args); + of_node_put(parent_args.np); + if (err) { + of_node_put(child); + break; + } } of_node_put(np); @@ -1361,6 +1482,12 @@ static void tegra_powergate_remove_all(struct device_node *parent) } of_node_put(np); + + np = of_get_child_by_name(parent, "core-domain"); + if (np) { + of_genpd_del_provider(np); + of_genpd_remove_last(np); + } } static const struct tegra_io_pad_soc * @@ -3672,6 +3799,21 @@ static const struct of_device_id tegra_pmc_match[] = { { } }; +static void tegra_pmc_sync_state(struct device *dev) +{ + int err; + + pmc->core_domain_state_synced = true; + + /* this is a no-op if core regulator isn't used */ + mutex_lock(&pmc->powergates_lock); + err = dev_pm_opp_sync_regulators(dev); + mutex_unlock(&pmc->powergates_lock); + + if (err) + dev_err(dev, "failed to sync regulators: %d\n", err); +} + static struct platform_driver tegra_pmc_driver = { .driver = { .name = "tegra-pmc", @@ -3680,6 +3822,7 @@ static struct platform_driver tegra_pmc_driver = { #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, #endif + .sync_state = tegra_pmc_sync_state, }, .probe = tegra_pmc_probe, }; diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index af41ad80ec21..135a6956a18c 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -23,6 +23,8 @@ struct tegra_core_opp_params { #ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +bool tegra_soc_core_domain_state_synced(void); + int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *params); #else @@ -31,6 +33,11 @@ static inline bool soc_is_tegra(void) return false; } +static inline bool tegra_soc_core_domain_state_synced(void) +{ + return false; +} + static inline int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *params)