From patchwork Thu May 20 15:47:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Costa X-Patchwork-Id: 443644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 830D6C43603 for ; Thu, 20 May 2021 15:48:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B3516108D for ; Thu, 20 May 2021 15:48:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241396AbhETPtn (ORCPT ); Thu, 20 May 2021 11:49:43 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:45090 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239128AbhETPtl (ORCPT ); Thu, 20 May 2021 11:49:41 -0400 Received: from mailhost.synopsys.com (mdc-mailhost1.synopsys.com [10.225.0.209]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client CN "mailhost.synopsys.com", Issuer "SNPSica2" (verified OK)) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 215A2C06A6; Thu, 20 May 2021 15:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1621525699; bh=87hJyrxMvoFsZVKKPTNltIEwtsJBX5wGxSe+YuT5l2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=eIGD+KYFIE6QuwwfQ2hn4jysnNuRWrW1bzvwc1nSuf/ES+Hry3t44qlPc+M6gqMJp wsfH06iiaK/Fic95nEXUbHM2obFauANkjm0A+CdaZiNQXvYxZZhsXMiKhM6q+n7kno zirMikfUwuoUhMw3H+XcMGtIjuRBsNBW6crnm1D3DXPk3s9e8cGUrw20SNxcEKpimT F1BAXQIJzixRSF/hpeUP1K118TH91k6Pjtn5sNdTwNWPup4q1QlQAjt5jhkx+hoLqs 4TbkZe1Typzh/hzLvf0lsg9JhGXBe71K+aPnf9+5GgowjXBqY4lF7A+j1GOZ6T8BKa uVkc3jQGTS6GA== Received: from de02dwvm009.internal.synopsys.com (de02dwvm009.internal.synopsys.com [10.225.17.73]) by mailhost.synopsys.com (Postfix) with ESMTP id C0BA3A005D; Thu, 20 May 2021 15:48:17 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Nelson Costa To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Mauro Carvalho Chehab , Hans Verkuil , Laurent Pinchart , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Jose Abreu , Nelson Costa Subject: [RFC v2 1/9] dt-bindings: phy: Document Synopsys DesignWare HDMI RX PHYs e405 and e406 Date: Thu, 20 May 2021 17:47:55 +0200 Message-Id: <570d5fa01a17be017346262b8a9b06d36bebe8f1.1621524721.git.nelson.costa@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Document the device tree bindings for the Synopsys DesignWare HDMI RX PHYs e405 and e406. Signed-off-by: Nelson Costa --- .../bindings/phy/snps,phy-dw-hdmi-e40x.yaml | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml diff --git a/Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml b/Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml new file mode 100644 index 0000000..25bece5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/snps,phy-dw-hdmi-e40x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI PHYs e405/e406 Device Tree Bindings + +maintainers: + - Jose Abreu + - Nelson Costa + +description: | + The Synopsys DesignWare HDMI PHYs e405/e406 are HDMI 2.0 PHY Receivers that + receive video and audio, and send to the HDMI RX Controller. + +properties: + compatible: + oneOf: + - const: snps,dw-hdmi-phy-e405 + - const: snps,dw-hdmi-phy-e406 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: | + phandle to the configuration clock + + clock-names: + const: cfg + + "#phy-cells": + const: 0 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: | + Output port node, multiple endpoints describing the PHY HDMI inputs data + connected to the HDMI RX Controller. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - port + +additionalProperties: false + +examples: + - | + parent { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_e406_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e406"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_e406_phy_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_rx_0>; + }; + + hdmi_e406_phy_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_rx_1>; + }; + + hdmi_e406_phy_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_rx_2>; + }; + + hdmi_e406_phy_3: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_rx_3>; + }; + }; + }; + }; From patchwork Thu May 20 15:47:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Costa X-Patchwork-Id: 443645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2327BC433B4 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=LvLA3agcwc1numgT5zAZRYxHSJOLQUBCJhN/4j68P1cRCvfK1cQKQHvlI7iCFCiEd JP8CIOSWBWSRDKJkhyLnRCHIHc4A3VV6Ps3N/OGN4ilZa+7yp1Lk4curZbspKgycE6 KQyGtLdH0uF0Vve8UnAT1DwCRU6Bqq8f0a1Qcojfzbc+X7jYLBwiXiteZygZebo+K6 CNf+sE11e8TtxtrLBWbW5SHafR2n1Q/dFFMrzbBz+PZ1z9m56zR/ICCWLc4kUTx67k gjAKCgp6M7FXfWoU2/q8HKSvXtt/A9LQwlzsESjDeZCiV400C5LlHDj5K2wZ2hMg63 Y/ImR92rkvEBg== Received: from de02dwvm009.internal.synopsys.com (de02dwvm009.internal.synopsys.com [10.225.17.73]) by mailhost.synopsys.com (Postfix) with ESMTP id DAAD3A0064; Thu, 20 May 2021 15:48:17 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Nelson Costa To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Mauro Carvalho Chehab , Hans Verkuil , Laurent Pinchart , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Jose Abreu , Nelson Costa , Jose Abreu Subject: [RFC v2 3/9] MAINTAINERS: Add entry for Synopsys DesignWare HDMI drivers Date: Thu, 20 May 2021 17:47:57 +0200 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add an entry for Synopsys DesignWare HDMI Receivers drivers and PHYs. Signed-off-by: Jose Abreu Signed-off-by: Nelson Costa --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 04e6df9..e0e7b41 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17304,6 +17304,17 @@ S: Supported F: drivers/net/pcs/pcs-xpcs.c F: include/linux/pcs/pcs-xpcs.h +SYNOPSYS DESIGNWARE HDMI RECEIVERS AND PHY DRIVERS +M: Jose Abreu +M: Nelson Costa +L: linux-media@vger.kernel.org +S: Odd Fixes +F: Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml +F: drivers/media/platform/dwc/* +F: drivers/phy/dwc/* +F: include/linux/phy/dwc/* +F: include/media/dwc/* + SYNOPSYS DESIGNWARE I2C DRIVER M: Jarkko Nikula R: Andy Shevchenko From patchwork Thu May 20 15:47:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Costa X-Patchwork-Id: 443643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34A33C43616 for ; Thu, 20 May 2021 15:48:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C48061006 for ; Thu, 20 May 2021 15:48:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242063AbhETPtq (ORCPT ); Thu, 20 May 2021 11:49:46 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:45108 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239427AbhETPtl (ORCPT ); Thu, 20 May 2021 11:49:41 -0400 Received: from mailhost.synopsys.com (mdc-mailhost1.synopsys.com [10.225.0.209]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client CN "mailhost.synopsys.com", Issuer "SNPSica2" (verified OK)) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 304A0C06AF; Thu, 20 May 2021 15:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1621525699; bh=Cjwofvyx7tHITwroONobhD5qV5HclCkCWYemv1jIgWE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=Kq+uqBqlwabdQhsVDqW454VpYb+VUyQqf1YWWhf/tgbD/Gopy/X2ebO0zpcTJnsfe owHX0kTRWeb+MgIdnMyWKxSB6jr4fa/5ji4r9su+y6fpq+JtfHl+tNUITD4mLH50dg NVrlIM2OQu+//e0tYrfSC3rkCRsha763sCzc8c8zaonD5gBFhDj79BgrwFKzUo05E1 N9UVX2m6gdFubXALErKsDkU7gEka5JJYpyHoDgk28EqXdUwxfKN/cphi4PRPs2A5gn xFx85thtM+BJgiWKyo3hA0dgPxONl93JKeFyk/cwTd33/cbeCgMnDHBxMEliu5GRdU RHqiSSl/YEYig== Received: from de02dwvm009.internal.synopsys.com (de02dwvm009.internal.synopsys.com [10.225.17.73]) by mailhost.synopsys.com (Postfix) with ESMTP id EC288A0067; Thu, 20 May 2021 15:48:17 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Nelson Costa To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Mauro Carvalho Chehab , Hans Verkuil , Laurent Pinchart , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Jose Abreu , Nelson Costa Subject: [RFC v2 4/9] phy: Add PHY standard HDMI opts to the PHY API Date: Thu, 20 May 2021 17:47:58 +0200 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This adds the new options to give support for HDMI PHYs in a standard way. This is mainly useful when the HDMI PHY requires parameters to be passed by "phy_configure" function. For this, the new struct phy_configure_opts_hdmi was added with the required generic and standard parameters. Signed-off-by: Nelson Costa --- include/linux/phy/phy-hdmi.h | 102 +++++++++++++++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 7 ++- 2 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 include/linux/phy/phy-hdmi.h diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h new file mode 100644 index 0000000..62334f4 --- /dev/null +++ b/include/linux/phy/phy-hdmi.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 - present Synopsys, Inc. and/or its affiliates. + * HDMI generic PHY options. + * + * Author: Nelson Costa + */ +#ifndef __PHY_HDMI_H_ +#define __PHY_HDMI_H_ + +#include + +/** + * struct phy_configure_opts_hdmi - HDMI PHY configuration set + * + * This structure is used to represent the configuration state of an + * HDMI PHY. + */ +struct phy_configure_opts_hdmi { + /** + * @color_depth: + * + * Color depth, as specified by HDMI specification, represents the + * number of bits per pixel. + * + * Allowed values: 24, 30, 36, 48 + * + */ + u8 color_depth; + + /** + * @tmds_bit_clock_ratio: + * + * Flag indicating, as specified by HDMI specification, the relation + * between TMDS Clock Rate and TMDS Character Rate. + * + * As specified by HDMI specification: + * + * tmds_bit_clock_ratio = 0, for TMDS Character Rates <= 340 Mcsc + * (TMDS Clock Rate = TMDS Character Rate) + * + * tmds_bit_clock_ratio = 1, for TMDS Character Rates > 340 Mcsc + * (TMDS Clock Rate = TMDS Character Rate / 4) + * + */ + u8 tmds_bit_clock_ratio; + + /** + * @scrambling: + * + * Scrambling, as specified by HDMI specification, enables the technique + * to reduce the EMI/RFI. + * + */ + u8 scrambling; + + /** + * @calibration_acq: + * + * Calibration acquisitions number for the calibration algorithm. + * + */ + unsigned int calibration_acq; + + /** + * @calibration_force: + * + * Flag indicating, to force calibration algorithm even if the MPLL + * status didn't change from previous run calibration. + * + */ + u8 calibration_force; + + /** + * @set_color_depth: + * + * Flag indicating, whether or not reconfigure deep_color + * to requested values. + * + */ + u8 set_color_depth : 1; + + /** + * @set_tmds_bit_clock_ratio: + * + * Flag indicating, whether or not reconfigure tmds_bit_clock_ratio + * to requested values. + * + */ + u8 set_tmds_bit_clock_ratio : 1; + + /** + * @set_scrambling: + * + * Flag indicating, whether or not reconfigure scrambling + * to requested values. + * + */ + u8 set_scrambling : 1; +}; + +#endif /* __PHY_HDMI_H_ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index e435bdb..8b1aaa4 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -18,6 +18,7 @@ #include #include +#include struct phy; @@ -41,7 +42,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_HDMI }; /** @@ -51,10 +53,13 @@ enum phy_mode { * the MIPI_DPHY phy mode. * @dp: Configuration set applicable for phys supporting * the DisplayPort protocol. + * @hdmi Configuration set applicable for phys supporting + * the HDMI protocol. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; struct phy_configure_opts_dp dp; + struct phy_configure_opts_hdmi hdmi; }; /** From patchwork Thu May 20 15:48:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Costa X-Patchwork-Id: 443641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79CCDC43462 for ; Thu, 20 May 2021 15:48:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 51D7061006 for ; Thu, 20 May 2021 15:48:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242998AbhETPuH (ORCPT ); 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Thu, 20 May 2021 15:48:18 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Nelson Costa To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Mauro Carvalho Chehab , Hans Verkuil , Laurent Pinchart , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Jose Abreu , Nelson Costa Subject: [RFC v2 7/9] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings Date: Thu, 20 May 2021 17:48:01 +0200 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This extends the support for more video format timings based on SPECs CEA-861-F and CTA-861-G. NOTE: For the newer SPECs the CEA was unified to the CTA. The CTA-861-G then includes the CEA-861-F timings besides the new timings that are specified. CEA-861-F: Specifies the Video timings for VICs 1-107. CTA-861-G: Specifies the Video timings for VICs 1-107, 108-127, 193-219. With this patch, the array v4l2_dv_timings_presets has support for all video timings specified in CTA-861-G. Signed-off-by: Nelson Costa --- drivers/media/v4l2-core/v4l2-dv-timings.c | 139 +++ include/uapi/linux/v4l2-dv-timings.h | 1595 ++++++++++++++++++++++++++++- 2 files changed, 1733 insertions(+), 1 deletion(-) diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c index 230d65a..0766e0c 100644 --- a/drivers/media/v4l2-core/v4l2-dv-timings.c +++ b/drivers/media/v4l2-core/v4l2-dv-timings.c @@ -133,6 +133,145 @@ const struct v4l2_dv_timings v4l2_dv_timings_presets[] = { V4L2_DV_BT_CEA_4096X2160P50, V4L2_DV_BT_DMT_4096X2160P59_94_RB, V4L2_DV_BT_CEA_4096X2160P60, + V4L2_DV_BT_CEA_720X480P60_PA16_9, + V4L2_DV_BT_CEA_720X480I60_PA16_9, + V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3, + V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3, + V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9, + V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9, + V4L2_DV_BT_CEA_2880X480I60_PA4_3, + V4L2_DV_BT_CEA_2880X480I60_PA16_9, + V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3, + V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3, + V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9, + V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9, + V4L2_DV_BT_CEA_1440X480P60_PA4_3, + V4L2_DV_BT_CEA_1440X480P60_PA16_9, + V4L2_DV_BT_CEA_720X576P50_PA16_9, + V4L2_DV_BT_CEA_1920X1080I50_PA16_9, + V4L2_DV_BT_CEA_720X576I50_PA16_9, + V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3, + V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3, + V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3, + V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9, + V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9, + V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9, + V4L2_DV_BT_CEA_2880X576I50_PA4_3, + V4L2_DV_BT_CEA_2880X576I50_PA16_9, + V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3, + V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3, + V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3, + V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9, + V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9, + V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9, + V4L2_DV_BT_CEA_1440X576P50_PA4_3, + V4L2_DV_BT_CEA_1440X576P50_PA16_9, + V4L2_DV_BT_CEA_2880X480P60_PA4_3, + V4L2_DV_BT_CEA_2880X480P60_PA16_9, + V4L2_DV_BT_CEA_2880X576P50_PA4_3, + V4L2_DV_BT_CEA_2880X576P50_PA16_9, + V4L2_DV_BT_CEA_1920X1080I50_PA16_9, + V4L2_DV_BT_CEA_1920X1080I100_PA16_9, + V4L2_DV_BT_CEA_1280X720P100_PA16_9, + V4L2_DV_BT_CEA_720X576P100_PA4_3, + V4L2_DV_BT_CEA_720X576P100_PA16_9, + V4L2_DV_BT_CEA_1440X576I100_PA4_3, + V4L2_DV_BT_CEA_1440X576I100_PA16_9, + V4L2_DV_BT_CEA_1920X1080I120_PA16_9, + V4L2_DV_BT_CEA_1280X720P120_PA16_9, + V4L2_DV_BT_CEA_720X480P120_PA4_3, + V4L2_DV_BT_CEA_720X480P120_PA16_9, + V4L2_DV_BT_CEA_1440X480I120_PA4_3, + V4L2_DV_BT_CEA_1440X480I120_PA16_9, + V4L2_DV_BT_CEA_720X576P200_PA4_3, + V4L2_DV_BT_CEA_720X576P200_PA16_9, + V4L2_DV_BT_CEA_1440X576I200_PA4_3, + V4L2_DV_BT_CEA_1440X576I200_PA16_9, + V4L2_DV_BT_CEA_720X480P240_PA4_3, + V4L2_DV_BT_CEA_720X480P240_PA16_9, + V4L2_DV_BT_CEA_1440X480I240_PA4_3, + V4L2_DV_BT_CEA_1440X480I240_PA16_9, + V4L2_DV_BT_CEA_1920X1080P120_PA16_9, + V4L2_DV_BT_CEA_1920X1080P100_PA16_9, + V4L2_DV_BT_CEA_1280X720P24_PA64_27, + V4L2_DV_BT_CEA_1280X720P25_PA64_27, + V4L2_DV_BT_CEA_1280X720P30_PA64_27, + V4L2_DV_BT_CEA_1280X720P50_PA64_27, + V4L2_DV_BT_CEA_1280X720P60_PA64_27, + V4L2_DV_BT_CEA_1280X720P100_PA64_27, + V4L2_DV_BT_CEA_1280X720P120_PA64_27, + V4L2_DV_BT_CEA_1920X1080P24_PA64_27, + V4L2_DV_BT_CEA_1920X1080P25_PA64_27, + V4L2_DV_BT_CEA_1920X1080P30_PA64_27, + V4L2_DV_BT_CEA_1920X1080P50_PA64_27, + V4L2_DV_BT_CEA_1920X1080P60_PA64_27, + V4L2_DV_BT_CEA_1920X1080P100_PA64_27, + V4L2_DV_BT_CEA_1920X1080P120_PA64_27, + V4L2_DV_BT_CEA_1680X720P24_PA64_27, + V4L2_DV_BT_CEA_1680X720P25_PA64_27, + V4L2_DV_BT_CEA_1680X720P30_PA64_27, + V4L2_DV_BT_CEA_1680X720P50_PA64_27, + V4L2_DV_BT_CEA_1680X720P60_PA64_27, + V4L2_DV_BT_CEA_1680X720P100_PA64_27, + V4L2_DV_BT_CEA_1680X720P120_PA64_27, + V4L2_DV_BT_CEA_2560X1080P24_PA64_27, + V4L2_DV_BT_CEA_2560X1080P25_PA64_27, + V4L2_DV_BT_CEA_2560X1080P30_PA64_27, + V4L2_DV_BT_CEA_2560X1080P50_PA64_27, + V4L2_DV_BT_CEA_2560X1080P60_PA64_27, + V4L2_DV_BT_CEA_2560X1080P100_PA64_27, + V4L2_DV_BT_CEA_2560X1080P120_PA64_27, + V4L2_DV_BT_CEA_3840X2160P24_PA64_27, + V4L2_DV_BT_CEA_3840X2160P25_PA64_27, + V4L2_DV_BT_CEA_3840X2160P30_PA64_27, + V4L2_DV_BT_CEA_3840X2160P50_PA64_27, + V4L2_DV_BT_CEA_3840X2160P60_PA64_27, + V4L2_DV_BT_CEA_1280X720P48_PA16_9, + V4L2_DV_BT_CEA_1280X720P48_PA64_27, + V4L2_DV_BT_CEA_1680X720P48_PA64_27, + V4L2_DV_BT_CEA_1920X1080P48_PA16_9, + V4L2_DV_BT_CEA_1920X1080P48_PA64_27, + V4L2_DV_BT_CEA_3840X2160P48_PA16_9, + V4L2_DV_BT_CEA_4096X2160P48_PA256_135, + V4L2_DV_BT_CEA_3840X2160P48_PA64_27, + V4L2_DV_BT_CEA_3840X2160P100_PA16_9, + V4L2_DV_BT_CEA_3840X2160P120_PA16_9, + V4L2_DV_BT_CEA_3840X2160P100_PA64_27, + V4L2_DV_BT_CEA_3840X2160P120_PA64_27, + V4L2_DV_BT_CEA_5120X2160P24_PA64_27, + V4L2_DV_BT_CEA_5120X2160P25_PA64_27, + V4L2_DV_BT_CEA_5120X2160P30_PA64_27, + V4L2_DV_BT_CEA_5120X2160P48_PA64_27, + V4L2_DV_BT_CEA_5120X2160P50_PA64_27, + V4L2_DV_BT_CEA_5120X2160P60_PA64_27, + V4L2_DV_BT_CEA_5120X2160P100_PA64_27, + V4L2_DV_BT_CEA_5120X2160P120_PA64_27, + V4L2_DV_BT_CEA_7680X4320P24_PA16_9, + V4L2_DV_BT_CEA_7680X4320P25_PA16_9, + V4L2_DV_BT_CEA_7680X4320P30_PA16_9, + V4L2_DV_BT_CEA_7680X4320P48_PA16_9, + V4L2_DV_BT_CEA_7680X4320P50_PA16_9, + V4L2_DV_BT_CEA_7680X4320P60_PA16_9, + V4L2_DV_BT_CEA_7680X4320P100_PA16_9, + V4L2_DV_BT_CEA_7680X4320P120_PA16_9, + V4L2_DV_BT_CEA_7680X4320P24_PA64_27, + V4L2_DV_BT_CEA_7680X4320P25_PA64_27, + V4L2_DV_BT_CEA_7680X4320P30_PA64_27, + V4L2_DV_BT_CEA_7680X4320P48_PA64_27, + V4L2_DV_BT_CEA_7680X4320P50_PA64_27, + V4L2_DV_BT_CEA_7680X4320P60_PA64_27, + V4L2_DV_BT_CEA_7680X4320P100_PA64_27, + V4L2_DV_BT_CEA_7680X4320P120_PA64_27, + V4L2_DV_BT_CEA_10240X4320P24_PA64_27, + V4L2_DV_BT_CEA_10240X4320P25_PA64_27, + V4L2_DV_BT_CEA_10240X4320P30_PA64_27, + V4L2_DV_BT_CEA_10240X4320P48_PA64_27, + V4L2_DV_BT_CEA_10240X4320P50_PA64_27, + V4L2_DV_BT_CEA_10240X4320P60_PA64_27, + V4L2_DV_BT_CEA_10240X4320P100_PA64_27, + V4L2_DV_BT_CEA_10240X4320P120_PA64_27, + V4L2_DV_BT_CEA_4096X2160P100_PA256_135, + V4L2_DV_BT_CEA_4096X2160P120_PA256_135, { } }; EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets); diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h index b52b67c..900530b 100644 --- a/include/uapi/linux/v4l2-dv-timings.h +++ b/include/uapi/linux/v4l2-dv-timings.h @@ -29,7 +29,14 @@ .bt = { _width , ## args } #endif -/* CEA-861-F timings (i.e. standard HDTV timings) */ +/* CEA-861-F timings (i.e. standard HDTV timings) + * NOTE: For the newer SPECs the CEA was unified to the CTA. + * The CTA-861-G includes the CEA-861-F timings besides the + * new timings that are specified. + * + * CEA-861-F: Specifies the Video timings for VICs 1-107 + * CTA-861-G: Specifies the Video timings for VICs 1-107, 108-127, 193-219 + */ #define V4L2_DV_BT_CEA_640X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ @@ -297,6 +304,1592 @@ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \ } +/* VIC=3 */ +#define V4L2_DV_BT_CEA_720X480P60_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ + 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 3) \ +} + +/* VIC=7 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X480I60_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ + 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 7) \ +} + +/* VIC=8 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \ + 13500000, 19, 62, 57, 4, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 8) \ +} + +/* VIC=8 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \ + 13500000, 19, 62, 57, 5, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 8) \ +} + +/* VIC=9 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \ + 13500000, 19, 62, 57, 4, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 9) \ +} + +/* VIC=9 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \ + 13500000, 19, 62, 57, 5, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 9) \ +} + +/* VIC=10 */ +#define V4L2_DV_BT_CEA_2880X480I60_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 480, 1, 0, \ + 54000000, 76, 248, 228, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 10) \ +} + +/* VIC=11 */ +#define V4L2_DV_BT_CEA_2880X480I60_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 480, 1, 0, \ + 54000000, 76, 248, 228, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 11) \ +} + +/* VIC=12 */ +#define V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \ + 54000000, 76, 248, 228, 4, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 12) \ +} + +/* VIC=12 */ +#define V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \ + 54000000, 76, 248, 228, 5, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 12) \ +} + +/* VIC=13 */ +#define V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \ + 54000000, 76, 248, 228, 4, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 13) \ +} + +/* VIC=13 */ +#define V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \ + 54000000, 76, 248, 228, 5, 3, 15, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 13) \ +} + +/* VIC=14 */ +#define V4L2_DV_BT_CEA_1440X480P60_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 480, 0, 0, \ + 54000000, 32, 124, 120, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 14) \ +} + +/* VIC=15 */ +#define V4L2_DV_BT_CEA_1440X480P60_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 480, 0, 0, \ + 54000000, 32, 124, 120, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 15) \ +} + +/* VIC=18 */ +#define V4L2_DV_BT_CEA_720X576P50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ + 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 18) \ +} + +/* VIC=22 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X576I50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ + 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 22) \ +} + +/* VIC=23 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \ + 13500000, 12, 63, 69, 2, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 23) \ +} + +/* VIC=23 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \ + 13500000, 12, 63, 69, 3, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 23) \ +} + +/* VIC=23 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \ + 13500000, 12, 63, 69, 4, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 23) \ +} + +/* VIC=24 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \ + 13500000, 12, 63, 69, 2, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 24) \ +} + +/* VIC=24 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \ + 13500000, 12, 63, 69, 3, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 24) \ +} + +/* VIC=24 */ +/* Note: these are the nominal timings, for HDMI links this format is typically + * double-clocked to meet the minimum pixelclock requirements. + */ +#define V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \ + 13500000, 12, 63, 69, 4, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 24) \ +} + +/* VIC=25 */ +#define V4L2_DV_BT_CEA_2880X576I50_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 576, 1, 0, \ + 54000000, 48, 252, 276, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 25) \ +} + +/* VIC=26 */ +#define V4L2_DV_BT_CEA_2880X576I50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 576, 1, 0, \ + 54000000, 48, 252, 276, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 26) \ +} + +/* VIC=27 */ +#define V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \ + 54000000, 48, 252, 276, 2, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 27) \ +} + +/* VIC=27 */ +#define V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \ + 54000000, 48, 252, 276, 3, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 27) \ +} + +/* VIC=27 */ +#define V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \ + 54000000, 48, 252, 276, 4, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 27) \ +} + +/* VIC=28 */ +#define V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \ + 54000000, 48, 252, 276, 2, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 28) \ +} + +/* VIC=28 */ +#define V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \ + 54000000, 48, 252, 276, 3, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 28) \ +} + +/* VIC=28 */ +#define V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \ + 54000000, 48, 252, 276, 4, 3, 19, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 28) \ +} + +/* VIC=29 */ +#define V4L2_DV_BT_CEA_1440X576P50_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 576, 0, 0, \ + 54000000, 24, 128, 136, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 29) \ +} + +/* VIC=30 */ +#define V4L2_DV_BT_CEA_1440X576P50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 576, 0, 0, \ + 54000000, 24, 128, 136, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 30) \ +} + +/* VIC=35 */ +#define V4L2_DV_BT_CEA_2880X480P60_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 480, 0, 0, \ + 108000000, 64, 248, 240, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 35) \ +} + +/* VIC=36 */ +#define V4L2_DV_BT_CEA_2880X480P60_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 480, 0, 0, \ + 108000000, 64, 248, 240, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 36) \ +} + +/* VIC=37 */ +#define V4L2_DV_BT_CEA_2880X576P50_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 576, 0, 0, \ + 108000000, 48, 256, 272, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 37) \ +} + +/* VIC=38 */ +#define V4L2_DV_BT_CEA_2880X576P50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2880, 576, 0, 0, \ + 108000000, 48, 256, 272, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 38) \ +} + +/* VIC=39 */ +#define V4L2_DV_BT_CEA_1920X1080I50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 1, V4L2_DV_HSYNC_POS_POL, \ + 72000000, 32, 168, 184, 23, 5, 57, 23, 5, 58, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 39) \ +} + +/* VIC=40 */ +#define V4L2_DV_BT_CEA_1920X1080I100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 40) \ +} + +/* VIC=41 */ +#define V4L2_DV_BT_CEA_1280X720P100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 41) \ +} + +/* VIC=42 */ +#define V4L2_DV_BT_CEA_720X576P100_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ + 54000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 42) \ +} + +/* VIC=43 */ +#define V4L2_DV_BT_CEA_720X576P100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ + 54000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 43) \ +} + +/* VIC=44 */ +#define V4L2_DV_BT_CEA_1440X576I100_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \ + 54000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 44) \ +} + +/* VIC=45 */ +#define V4L2_DV_BT_CEA_1440X576I100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \ + 54000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 45) \ +} + +/* VIC=46 */ +#define V4L2_DV_BT_CEA_1920X1080I120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 46) \ +} + +/* VIC=47 */ +#define V4L2_DV_BT_CEA_1280X720P120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 47) \ +} + +/* VIC=48 */ +#define V4L2_DV_BT_CEA_720X480P120_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ + 54000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 48) \ +} + +/* VIC=49 */ +#define V4L2_DV_BT_CEA_720X480P120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ + 54000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 49) \ +} + +/* VIC=50 */ +#define V4L2_DV_BT_CEA_1440X480I120_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \ + 54000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 50) \ +} + +/* VIC=51 */ +#define V4L2_DV_BT_CEA_1440X480I120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \ + 54000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 51) \ +} + +/* VIC=52 */ +#define V4L2_DV_BT_CEA_720X576P200_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ + 108000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 52) \ +} + +/* VIC=53 */ +#define V4L2_DV_BT_CEA_720X576P200_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ + 108000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 53) \ +} + +/* VIC=54 */ +#define V4L2_DV_BT_CEA_1440X576I200_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \ + 108000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 54) \ +} + +/* VIC=55 */ +#define V4L2_DV_BT_CEA_1440X576I200_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \ + 108000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 55) \ +} + +/* VIC=56 */ +#define V4L2_DV_BT_CEA_720X480P240_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ + 108000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 4, 3 }, 56) \ +} + +/* VIC=57 */ +#define V4L2_DV_BT_CEA_720X480P240_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ + 108000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 57) \ +} + +/* VIC=58 */ +#define V4L2_DV_BT_CEA_1440X480I240_PA4_3 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \ + 108000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 58) \ +} + +/* VIC=59 */ +#define V4L2_DV_BT_CEA_1440X480I240_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \ + 108000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 59) \ +} + +/* VIC=63 */ +#define V4L2_DV_BT_CEA_1920X1080P120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 63) \ +} + +/* VIC=64 */ +#define V4L2_DV_BT_CEA_1920X1080P100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 64) \ +} + +/* VIC=65 */ +#define V4L2_DV_BT_CEA_1280X720P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 65) \ +} + +/* VIC=66 */ +#define V4L2_DV_BT_CEA_1280X720P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 66) \ +} + +/* VIC=67 */ +#define V4L2_DV_BT_CEA_1280X720P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 67) \ +} + +/* VIC=68 */ +#define V4L2_DV_BT_CEA_1280X720P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 68) \ +} + +/* VIC=69 */ +#define V4L2_DV_BT_CEA_1280X720P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 69) \ +} + +/* VIC=70 */ +#define V4L2_DV_BT_CEA_1280X720P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 70) \ +} + +/* VIC=71 */ +#define V4L2_DV_BT_CEA_1280X720P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 71) \ +} + +/* VIC=72 */ +#define V4L2_DV_BT_CEA_1920X1080P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 72) \ +} + +/* VIC=73 */ +#define V4L2_DV_BT_CEA_1920X1080P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 73) \ +} + +/* VIC=74 */ +#define V4L2_DV_BT_CEA_1920X1080P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 74) \ +} + +/* VIC=75 */ +#define V4L2_DV_BT_CEA_1920X1080P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 75) \ +} + +/* VIC=76 */ +#define V4L2_DV_BT_CEA_1920X1080P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 76) \ +} + +/* VIC=77 */ +#define V4L2_DV_BT_CEA_1920X1080P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 77) \ +} + +/* VIC=78 */ +#define V4L2_DV_BT_CEA_1920X1080P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 78) \ +} + +/* VIC=79 */ +#define V4L2_DV_BT_CEA_1680X720P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 59400000, 1360, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 79) \ +} + +/* VIC=80 */ +#define V4L2_DV_BT_CEA_1680X720P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 59400000, 1228, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 80) \ +} + +/* VIC=81 */ +#define V4L2_DV_BT_CEA_1680X720P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 59400000, 700, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 81) \ +} + +/* VIC=82 */ +#define V4L2_DV_BT_CEA_1680X720P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 82500000, 260, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 82) \ +} + +/* VIC=83 */ +#define V4L2_DV_BT_CEA_1680X720P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 99000000, 260, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 83) \ +} + +/* VIC=84 */ +#define V4L2_DV_BT_CEA_1680X720P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 165000000, 60, 40, 220, 5, 5, 95, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 84) \ +} + +/* VIC=85 */ +#define V4L2_DV_BT_CEA_1680X720P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 198000000, 60, 40, 220, 5, 5, 95, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 85) \ +} + +/* VIC=86 */ +#define V4L2_DV_BT_CEA_2560X1080P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 99000000, 998, 44, 148, 4, 5, 11, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 86) \ +} + +/* VIC=87 */ +#define V4L2_DV_BT_CEA_2560X1080P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 90000000, 448, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 87) \ +} + +/* VIC=88 */ +#define V4L2_DV_BT_CEA_2560X1080P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 118800000, 768, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 88) \ +} + +/* VIC=89 */ +#define V4L2_DV_BT_CEA_2560X1080P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 185625000, 548, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 89) \ +} + +/* VIC=90 */ +#define V4L2_DV_BT_CEA_2560X1080P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 198000000, 248, 44, 148, 4, 5, 11, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 90) \ +} + +/* VIC=91 */ +#define V4L2_DV_BT_CEA_2560X1080P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 371250000, 218, 44, 148, 4, 5, 161, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 91) \ +} + +/* VIC=92 */ +#define V4L2_DV_BT_CEA_2560X1080P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 495000000, 548, 44, 148, 4, 5, 161, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 92) \ +} + +/* VIC=103 */ +#define V4L2_DV_BT_CEA_3840X2160P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 103) \ +} + +/* VIC=104 */ +#define V4L2_DV_BT_CEA_3840X2160P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 104) \ +} + +/* VIC=105 */ +#define V4L2_DV_BT_CEA_3840X2160P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 105) \ +} + +/* VIC=106 */ +#define V4L2_DV_BT_CEA_3840X2160P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 106) \ +} + +/* VIC=107 */ +#define V4L2_DV_BT_CEA_3840X2160P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 107) \ +} + +/* VIC=108 */ +#define V4L2_DV_BT_CEA_1280X720P48_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 90000000, 960, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 108) \ +} + +/* VIC=109 */ +#define V4L2_DV_BT_CEA_1280X720P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 90000000, 960, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 109) \ +} + +/* VIC=110 */ +#define V4L2_DV_BT_CEA_1680X720P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1680, 720, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 99000000, 810, 40, 220, 5, 5, 20, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 110) \ +} + +/* VIC=111 */ +#define V4L2_DV_BT_CEA_1920X1080P48_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 111) \ +} + +/* VIC=112 */ +#define V4L2_DV_BT_CEA_1920X1080P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 148500000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 112) \ +} + +/* VIC=114 */ +#define V4L2_DV_BT_CEA_3840X2160P48_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 594000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 114) \ +} + +/* VIC=115 */ +#define V4L2_DV_BT_CEA_4096X2160P48_PA256_135 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 594000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 256, 135 }, 115) \ +} + +/* VIC=116 */ +#define V4L2_DV_BT_CEA_3840X2160P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 594000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 116) \ +} + +/* VIC=117 */ +#define V4L2_DV_BT_CEA_3840X2160P100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 117) \ +} + +/* VIC=118 */ +#define V4L2_DV_BT_CEA_3840X2160P120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 118) \ +} + +/* VIC=119 */ +#define V4L2_DV_BT_CEA_3840X2160P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 119) \ +} + +/* VIC=120 */ +#define V4L2_DV_BT_CEA_3840X2160P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 120) \ +} + +/* VIC=121 */ +#define V4L2_DV_BT_CEA_5120X2160P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 396000000, 1996, 88, 296, 8, 10, 22, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 121) \ +} + +/* VIC=122 */ +#define V4L2_DV_BT_CEA_5120X2160P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 396000000, 1696, 88, 296, 8, 10, 22, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 122) \ +} + +/* VIC=123 */ +#define V4L2_DV_BT_CEA_5120X2160P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 396000000, 664, 88, 296, 8, 10, 22, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 123) \ +} + +/* VIC=124 */ +#define V4L2_DV_BT_CEA_5120X2160P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 742500000, 746, 88, 296, 8, 10, 297, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 124) \ +} + +/* VIC=125 */ +#define V4L2_DV_BT_CEA_5120X2160P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 742500000, 1096, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 125) \ +} + +/* VIC=126 */ +#define V4L2_DV_BT_CEA_5120X2160P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 742500000, 164, 88, 128, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 126) \ +} + +/* VIC=127 */ +#define V4L2_DV_BT_CEA_5120X2160P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1485000000, 1096, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 127) \ +} + +/* VIC=193 */ +#define V4L2_DV_BT_CEA_5120X2160P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1485000000, 154, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 193) \ +} + +/* VIC=194 */ +#define V4L2_DV_BT_CEA_7680X4320P24_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 194) \ +} + +/* VIC=195 */ +#define V4L2_DV_BT_CEA_7680X4320P25_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 195) \ +} + +/* VIC=196 */ +#define V4L2_DV_BT_CEA_7680X4320P30_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 196) \ +} + +/* VIC=197 */ +#define V4L2_DV_BT_CEA_7680X4320P48_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2376000000ULL, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 197) \ +} + +/* VIC=198 */ +#define V4L2_DV_BT_CEA_7680X4320P50_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2376000000ULL, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 198) \ +} + +/* VIC=199 */ +#define V4L2_DV_BT_CEA_7680X4320P60_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2376000000ULL, 552, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 199) \ +} + +/* VIC=200 */ +#define V4L2_DV_BT_CEA_7680X4320P100_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 4752000000ULL, 2112, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 200) \ +} + +/* VIC=201 */ +#define V4L2_DV_BT_CEA_7680X4320P120_PA16_9 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 4752000000ULL, 352, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 16, 9 }, 201) \ +} + +/* VIC=202 */ +#define V4L2_DV_BT_CEA_7680X4320P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 202) \ +} + +/* VIC=203 */ +#define V4L2_DV_BT_CEA_7680X4320P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 203) \ +} + +/* VIC=204 */ +#define V4L2_DV_BT_CEA_7680X4320P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 204) \ +} + +/* VIC=205 */ +#define V4L2_DV_BT_CEA_7680X4320P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2376000000ULL, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 205) \ +} + +/* VIC=206 */ +#define V4L2_DV_BT_CEA_7680X4320P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2376000000ULL, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 206) \ +} + +/* VIC=207 */ +#define V4L2_DV_BT_CEA_7680X4320P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2376000000ULL, 552, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 207) \ +} + +/* VIC=208 */ +#define V4L2_DV_BT_CEA_7680X4320P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 4752000000ULL, 2112, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 208) \ +} + +/* VIC=209 */ +#define V4L2_DV_BT_CEA_7680X4320P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 4752000000ULL, 352, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 209) \ +} + +/* VIC=210 */ +#define V4L2_DV_BT_CEA_10240X4320P24_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1485000000, 1492, 176, 592, 16, 20, 594, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 210) \ +} + +/* VIC=211 */ +#define V4L2_DV_BT_CEA_10240X4320P25_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1485000000, 2492, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 211) \ +} + +/* VIC=212 */ +#define V4L2_DV_BT_CEA_10240X4320P30_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1485000000, 288, 176, 296, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 212) \ +} + +/* VIC=213 */ +#define V4L2_DV_BT_CEA_10240X4320P48_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2970000000ULL, 1492, 176, 592, 16, 20, 594, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 213) \ +} + +/* VIC=214 */ +#define V4L2_DV_BT_CEA_10240X4320P50_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2970000000ULL, 2492, 176, 592, 16, 20, 44, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 214) \ +} + +/* VIC=215 */ +#define V4L2_DV_BT_CEA_10240X4320P60_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 2970000000ULL, 288, 176, 296, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 215) \ +} + +/* VIC=216 */ +#define V4L2_DV_BT_CEA_10240X4320P100_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 5940000000ULL, 2192, 176, 592, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 216) \ +} + +/* VIC=217 */ +#define V4L2_DV_BT_CEA_10240X4320P120_PA64_27 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 5940000000ULL, 288, 176, 296, 16, 20, 144, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 64, 27 }, 217) \ +} + +/* VIC=218 */ +#define V4L2_DV_BT_CEA_4096X2160P100_PA256_135 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 800, 88, 296, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ + V4L2_DV_FL_HAS_CEA861_VIC, { 256, 135 }, 218) \ +} + +/* VIC=219 */ +#define V4L2_DV_BT_CEA_4096X2160P120_PA256_135 { \ + .type = V4L2_DV_BT_656_1120, \ + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ + 1188000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ + V4L2_DV_BT_STD_CEA861, \ + V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ + V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ + { 256, 135 }, 219) \ +} /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ From patchwork Thu May 20 15:48:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Costa X-Patchwork-Id: 443642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75AF4C43460 for ; Thu, 20 May 2021 15:48:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5280A61244 for ; Thu, 20 May 2021 15:48:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242652AbhETPtt (ORCPT ); Thu, 20 May 2021 11:49:49 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:45114 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239761AbhETPtl (ORCPT ); Thu, 20 May 2021 11:49:41 -0400 Received: from mailhost.synopsys.com (mdc-mailhost1.synopsys.com [10.225.0.209]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client CN "mailhost.synopsys.com", Issuer "SNPSica2" (verified OK)) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 6C1E0C06B6; Thu, 20 May 2021 15:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1621525699; bh=rTD31JMNi55W5EN+vD2U8540L+97KY4PSF0qVD2fCLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=eMax7MWtQ5/LhyPbpRXMOd/gUV371/jdXzABZ4jjNVKUiygS5V057v9+Z8NCcd6nt X0QCSd+tndyL7bMJrqhk2cpsq8AUvMDAQHVHJrSW8AQkfjQNbzOyBxl1gyTbpPG8dM VvUJe2o8o4goUWoUDNJFc9jSHsZvWO+n7wsKlchK2yMHEoI7sssmcAf324HtUPiB9H ptRod9FhebmJ8CB2DuKpw49DKQbZ3hz5JIPgYk64gGgF6/zRQYxytFNVNVunUgGBXz 0/Ic0wyiFalqCPDKaJbiXox1zoAv7DgKqPm8Yi+WFCHZPs020FIXT+8qD8ZMnZKzgK 8cUzISU3YMXCw== Received: from de02dwvm009.internal.synopsys.com (de02dwvm009.internal.synopsys.com [10.225.17.73]) by mailhost.synopsys.com (Postfix) with ESMTP id 32EA1A0077; Thu, 20 May 2021 15:48:18 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Nelson Costa To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Mauro Carvalho Chehab , Hans Verkuil , Laurent Pinchart , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Jose Abreu , Nelson Costa , Jose Abreu Subject: [RFC v2 9/9] media: dwc: dw-hdmi-rx: Add support for CEC Date: Thu, 20 May 2021 17:48:03 +0200 Message-Id: <832ad1d939c5b1579029f9ff80cdfea3fbd7cf32.1621524721.git.nelson.costa@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This adds support for the optional HDMI CEC feature for the Synopsys DesignWare HDMI RX Controller. It uses the generic CEC framework interface. Signed-off-by: Jose Abreu Signed-off-by: Nelson Costa --- drivers/media/platform/dwc/Kconfig | 10 ++ drivers/media/platform/dwc/dw-hdmi-rx.c | 259 +++++++++++++++++++++++++++++++- drivers/media/platform/dwc/dw-hdmi-rx.h | 57 +++++++ 3 files changed, 324 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/dwc/Kconfig b/drivers/media/platform/dwc/Kconfig index ef2a6435..4d39be7 100644 --- a/drivers/media/platform/dwc/Kconfig +++ b/drivers/media/platform/dwc/Kconfig @@ -8,3 +8,13 @@ config VIDEO_DWC_HDMI_RX To compile this driver as a module, choose M here. The module will be called dw-hdmi-rx. + +config VIDEO_DWC_HDMI_RX_CEC + bool "Synopsys DesignWare HDMI Receiver CEC support" + depends on VIDEO_DWC_HDMI_RX + select CEC_CORE + help + When selected the Synopsys DesignWare HDMI RX controller + will support the optional HDMI CEC feature. + + It uses the generic CEC framework interface. diff --git a/drivers/media/platform/dwc/dw-hdmi-rx.c b/drivers/media/platform/dwc/dw-hdmi-rx.c index a468a93..5d6b1c0 100644 --- a/drivers/media/platform/dwc/dw-hdmi-rx.c +++ b/drivers/media/platform/dwc/dw-hdmi-rx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #define DW_HDMI_JTAG_TAP_WRITE_CMD 1 #define DW_HDMI_JTAG_TAP_READ_CMD 3 #define DW_HDMI_AUDIO_FREQ_RANGE 1000 +#define DW_HDMI_CEC_MAX_LOG_ADDRS CEC_MAX_LOG_ADDRS /* EDID for HDMI RX */ static u32 dw_hdmi_edid[] = { @@ -164,6 +166,9 @@ struct dw_hdmi_dev { union hdmi_infoframe audioif; union hdmi_infoframe vsif; + /* CEC */ + struct cec_adapter *cec_adap; + /* v4l2 device */ struct v4l2_subdev sd; struct v4l2_ctrl_handler hdl; @@ -365,6 +370,20 @@ static void dw_hdmi_reset(struct dw_hdmi_dev *dw_dev) dw_hdmi_main_reset(dw_dev); dw_hdmi_disable_hpd(dw_dev); + + /* After a main reset try to re-enable the cec adapter in order to + * reconfigure the required cec registers. For this the physical address + * is invalidated and reconfigured, and with CEC_CAP_NEEDS_HPD allowing + * to re-enable the adapter. + */ + if (dw_dev->cec_adap) { + u16 phys_addr = dw_dev->cec_adap->phys_addr; + + cec_phys_addr_invalidate(dw_dev->cec_adap); + cec_s_phys_addr(dw_dev->cec_adap, phys_addr, false); + dev_dbg(dw_dev->dev, "%s: re-enable cec adapter\n", + __func__); + } } static inline bool is_off(struct dw_hdmi_dev *dw_dev) @@ -1460,6 +1479,184 @@ static u32 dw_hdmi_get_int_val(struct dw_hdmi_dev *dw_dev, u32 ists, u32 ien) return hdmi_readl(dw_dev, ists) & hdmi_readl(dw_dev, ien); } +#if IS_ENABLED(CONFIG_VIDEO_DWC_HDMI_RX_CEC) +static void dw_hdmi_cec_enable_ints(struct dw_hdmi_dev *dw_dev) +{ + u32 mask = DW_HDMI_DONE_ISTS | DW_HDMI_EOM_ISTS | + DW_HDMI_NACK_ISTS | DW_HDMI_ARBLST_ISTS | + DW_HDMI_ERROR_INIT_ISTS | DW_HDMI_ERROR_FOLL_ISTS; + + hdmi_writel(dw_dev, mask, DW_HDMI_AUD_CEC_IEN_SET); + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_MASK); +} + +static void dw_hdmi_cec_disable_ints(struct dw_hdmi_dev *dw_dev) +{ + hdmi_writel(dw_dev, ~0x0, DW_HDMI_AUD_CEC_IEN_CLR); + hdmi_writel(dw_dev, ~0x0, DW_HDMI_CEC_MASK); +} + +static void dw_hdmi_cec_clear_ints(struct dw_hdmi_dev *dw_dev) +{ + hdmi_writel(dw_dev, ~0x0, DW_HDMI_AUD_CEC_ICLR); +} + +static void dw_hdmi_cec_tx_raw_status(struct dw_hdmi_dev *dw_dev, u32 stat) +{ + if (hdmi_readl(dw_dev, DW_HDMI_CEC_CTRL) & DW_HDMI_SEND_MASK) { + dev_dbg(dw_dev->dev, "%s: tx is busy\n", __func__); + return; + } + + if (stat & DW_HDMI_ARBLST_ISTS) { + cec_transmit_attempt_done(dw_dev->cec_adap, + CEC_TX_STATUS_ARB_LOST); + return; + } + + if (stat & DW_HDMI_NACK_ISTS) { + cec_transmit_attempt_done(dw_dev->cec_adap, CEC_TX_STATUS_NACK); + return; + } + + if (stat & DW_HDMI_ERROR_INIT_ISTS) { + dev_dbg(dw_dev->dev, "%s: got low drive error\n", __func__); + cec_transmit_attempt_done(dw_dev->cec_adap, + CEC_TX_STATUS_LOW_DRIVE); + return; + } + + if (stat & DW_HDMI_DONE_ISTS) { + cec_transmit_attempt_done(dw_dev->cec_adap, CEC_TX_STATUS_OK); + return; + } +} + +static void dw_hdmi_cec_received_msg(struct dw_hdmi_dev *dw_dev) +{ + struct cec_msg msg; + u8 i; + + msg.len = hdmi_readl(dw_dev, DW_HDMI_CEC_RX_CNT); + if (!msg.len || msg.len > DW_HDMI_CEC_RX_DATA_MAX) + return; /* it's an invalid/non-existent message */ + + for (i = 0; i < msg.len; i++) + msg.msg[i] = hdmi_readl(dw_dev, DW_HDMI_CEC_RX_DATA(i)); + + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_LOCK); + cec_received_msg(dw_dev->cec_adap, &msg); +} + +static int dw_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) +{ + struct dw_hdmi_dev *dw_dev = cec_get_drvdata(adap); + + dev_dbg(dw_dev->dev, "%s: enable=%d\n", __func__, enable); + + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_ADDR_L); + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_ADDR_H); + + if (enable) { + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_LOCK); + dw_hdmi_cec_clear_ints(dw_dev); + dw_hdmi_cec_enable_ints(dw_dev); + } else { + dw_hdmi_cec_disable_ints(dw_dev); + dw_hdmi_cec_clear_ints(dw_dev); + } + + return 0; +} + +static int dw_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) +{ + struct dw_hdmi_dev *dw_dev = cec_get_drvdata(adap); + u32 tmp; + + dev_dbg(dw_dev->dev, "%s: addr=%d\n", __func__, addr); + + if (addr == CEC_LOG_ADDR_INVALID) { + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_ADDR_L); + hdmi_writel(dw_dev, 0x0, DW_HDMI_CEC_ADDR_H); + return 0; + } + + if (addr >= 8) { + tmp = hdmi_readl(dw_dev, DW_HDMI_CEC_ADDR_H); + tmp |= BIT(addr - 8); + hdmi_writel(dw_dev, tmp, DW_HDMI_CEC_ADDR_H); + } else { + tmp = hdmi_readl(dw_dev, DW_HDMI_CEC_ADDR_L); + tmp |= BIT(addr); + hdmi_writel(dw_dev, tmp, DW_HDMI_CEC_ADDR_L); + } + + return 0; +} + +static int dw_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct dw_hdmi_dev *dw_dev = cec_get_drvdata(adap); + u8 len = msg->len; + u32 reg; + u8 i; + + dev_dbg(dw_dev->dev, "%s: len=%d\n", __func__, len); + + if (hdmi_readl(dw_dev, DW_HDMI_CEC_CTRL) & DW_HDMI_SEND_MASK) { + dev_err(dw_dev->dev, "%s: tx is busy\n", __func__); + return -EBUSY; + } + + for (i = 0; i < len; i++) + hdmi_writel(dw_dev, msg->msg[i], DW_HDMI_CEC_TX_DATA(i)); + + switch (signal_free_time) { + case CEC_SIGNAL_FREE_TIME_RETRY: + reg = 0x0; + break; + case CEC_SIGNAL_FREE_TIME_NEXT_XFER: + reg = 0x2; + break; + case CEC_SIGNAL_FREE_TIME_NEW_INITIATOR: + default: + reg = 0x1; + break; + } + + hdmi_writel(dw_dev, len, DW_HDMI_CEC_TX_CNT); + hdmi_mask_writel(dw_dev, reg, DW_HDMI_CEC_CTRL, + DW_HDMI_FRAME_TYP_OFFSET, + DW_HDMI_FRAME_TYP_MASK); + hdmi_mask_writel(dw_dev, 0x1, DW_HDMI_CEC_CTRL, + DW_HDMI_SEND_OFFSET, + DW_HDMI_SEND_MASK); + return 0; +} + +static const struct cec_adap_ops dw_hdmi_cec_adap_ops = { + .adap_enable = dw_hdmi_cec_adap_enable, + .adap_log_addr = dw_hdmi_cec_adap_log_addr, + .adap_transmit = dw_hdmi_cec_adap_transmit, +}; + +static void dw_hdmi_cec_irq_handler(struct dw_hdmi_dev *dw_dev) +{ + u32 cec_ists = dw_hdmi_get_int_val(dw_dev, DW_HDMI_AUD_CEC_ISTS, + DW_HDMI_AUD_CEC_IEN); + + dw_hdmi_cec_clear_ints(dw_dev); + + if (cec_ists) { + dw_hdmi_cec_tx_raw_status(dw_dev, cec_ists); + if (cec_ists & DW_HDMI_EOM_ISTS) + dw_hdmi_cec_received_msg(dw_dev); + } +} +#endif /* CONFIG_VIDEO_DWC_HDMI_RX_CEC */ + static u8 dw_hdmi_get_curr_vic(struct dw_hdmi_dev *dw_dev, bool *is_hdmi_vic) { u8 vic = hdmi_mask_readl(dw_dev, DW_HDMI_PDEC_AVI_PB, @@ -2058,6 +2255,10 @@ static irqreturn_t dw_hdmi_irq_handler(int irq, void *dev_data) } } +#if IS_ENABLED(CONFIG_VIDEO_DWC_HDMI_RX_CEC) + dw_hdmi_cec_irq_handler(dw_dev); +#endif /* CONFIG_VIDEO_DWC_HDMI_RX_CEC */ + return IRQ_HANDLED; } @@ -2556,14 +2757,27 @@ static int dw_hdmi_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) struct dw_hdmi_dev *dw_dev = to_dw_dev(sd); int input_count = dw_dev->config->phy->input_count; int size, ret; + u16 phys_addr; u32 *tmp; memset(edid->reserved, 0, sizeof(edid->reserved)); - if (edid->pad >= input_count || !edid->edid || !edid->blocks) + if (edid->pad >= input_count || !edid->edid) return -EINVAL; if (edid->start_block != 0) return -EINVAL; + if (!edid->blocks) { + phys_addr = CEC_PHYS_ADDR_INVALID; + goto set_phys_addr; + } + + /* get the source physical address (PA) from edid */ + phys_addr = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, + NULL); + /* get the own physical address getting the parent of Source PA */ + ret = v4l2_phys_addr_validate(phys_addr, &phys_addr, NULL); + if (ret) + return ret; /* Clear old EDID */ size = dw_dev->curr_edid_blocks[edid->pad] * 128; @@ -2592,7 +2806,9 @@ static int dw_hdmi_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) if (ret) return ret; +set_phys_addr: dw_dev->curr_edid_blocks[edid->pad] = edid->blocks; + cec_s_phys_addr(dw_dev->cec_adap, phys_addr, false); return 0; } @@ -2825,15 +3041,33 @@ static int dw_hdmi_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, static int dw_hdmi_registered(struct v4l2_subdev *sd) { struct dw_hdmi_dev *dw_dev = to_dw_dev(sd); + int ret; + + ret = cec_register_adapter(dw_dev->cec_adap, dw_dev->dev); + if (ret) { + dev_err(dw_dev->dev, "failed to register CEC adapter\n"); + goto err_adapter; + } + cec_s_phys_addr(dw_dev->cec_adap, 0, false); + if (dw_dev->cec_adap) + dev_info(dw_dev->dev, + "CEC adapter %s registered for HDMI input\n", + dev_name(&dw_dev->cec_adap->devnode.dev)); dw_dev->registered = true; return 0; + +err_adapter: + cec_delete_adapter(dw_dev->cec_adap); + return ret; } static void dw_hdmi_unregistered(struct v4l2_subdev *sd) { struct dw_hdmi_dev *dw_dev = to_dw_dev(sd); + cec_unregister_adapter(dw_dev->cec_adap); + dw_dev->registered = false; } @@ -3194,10 +3428,29 @@ static int dw_hdmi_rx_probe(struct platform_device *pdev) if (ret) goto err_phy_exit; + /* CEC */ +#if IS_ENABLED(CONFIG_VIDEO_DWC_HDMI_RX_CEC) + dw_dev->cec_adap = cec_allocate_adapter(&dw_hdmi_cec_adap_ops, + dw_dev, dev_name(dev), + (CEC_CAP_DEFAULTS | + CEC_CAP_NEEDS_HPD | + CEC_CAP_CONNECTOR_INFO), + DW_HDMI_CEC_MAX_LOG_ADDRS); + ret = PTR_ERR_OR_ZERO(dw_dev->cec_adap); + if (ret) { + dev_err(dev, "failed to allocate CEC adapter\n"); + goto err_cec; + } + + dev_info(dev, "CEC is enabled\n"); +#else + dev_info(dev, "CEC is disabled\n"); +#endif /* CONFIG_VIDEO_DWC_HDMI_RX_CEC */ + ret = v4l2_async_register_subdev(sd); if (ret) { dev_err(dev, "failed to register subdev\n"); - goto err_phy_exit; + goto err_cec; } /* Fill initial format settings */ @@ -3230,6 +3483,8 @@ static int dw_hdmi_rx_probe(struct platform_device *pdev) err_subdev: v4l2_async_unregister_subdev(sd); +err_cec: + cec_delete_adapter(dw_dev->cec_adap); err_phy_exit: dw_hdmi_phy_exit(dw_dev); err_hdl: diff --git a/drivers/media/platform/dwc/dw-hdmi-rx.h b/drivers/media/platform/dwc/dw-hdmi-rx.h index f0ea1d4..775b7a9 100644 --- a/drivers/media/platform/dwc/dw-hdmi-rx.h +++ b/drivers/media/platform/dwc/dw-hdmi-rx.h @@ -325,6 +325,25 @@ #define DW_HDMI_HDCP22_STATUS 0x08fc +/* id_audio_and_cec_interrupt Registers */ +#define DW_HDMI_AUD_CEC_IEN_CLR 0x0f90 +#define DW_HDMI_AUD_CEC_IEN_SET 0x0f94 + +#define DW_HDMI_AUD_CEC_ISTS 0x0f98 +#define DW_HDMI_WAKEUPCTRL_ISTS BIT(22) +#define DW_HDMI_ERROR_FOLL_ISTS BIT(21) +#define DW_HDMI_ERROR_INIT_ISTS BIT(20) +#define DW_HDMI_ARBLST_ISTS BIT(19) +#define DW_HDMI_NACK_ISTS BIT(18) +#define DW_HDMI_EOM_ISTS BIT(17) +#define DW_HDMI_DONE_ISTS BIT(16) +#define DW_HDMI_SCK_STABLE_ISTS BIT(1) +#define DW_HDMI_CTSN_CNT_ISTS BIT(0) + +#define DW_HDMI_AUD_CEC_IEN 0x0f9c +#define DW_HDMI_AUD_CEC_ICLR 0x0fa0 +#define DW_HDMI_AUD_CEC_ISET 0x0fa4 + /* id_mode_detection_interrupt Registers */ #define DW_HDMI_MD_IEN_CLR 0x0fc0 #define DW_HDMI_MD_IEN_SET 0x0fc4 @@ -426,6 +445,44 @@ #define DW_HDMI_HDMI_ENABLE_MASK BIT(2) #define DW_HDMI_HDMI_ENABLE_OFFSET 2 +/* id_cec Registers */ +#define DW_HDMI_CEC_CTRL 0x1f00 +#define DW_HDMI_STANDBY_MASK BIT(4) +#define DW_HDMI_STANDBY_OFFSET 4 +#define DW_HDMI_BC_NACK_MASK BIT(3) +#define DW_HDMI_BC_NACK_OFFSET 3 +#define DW_HDMI_FRAME_TYP_MASK GENMASK(2, 1) +#define DW_HDMI_FRAME_TYP_OFFSET 1 +#define DW_HDMI_SEND_MASK BIT(0) +#define DW_HDMI_SEND_OFFSET 0 + +#define DW_HDMI_CEC_MASK 0x1f08 +#define DW_HDMI_WAKEUP_MASK BIT(6) +#define DW_HDMI_WAKEUP_OFFSET 6 +#define DW_HDMI_ERROR_FLOW_MASK BIT(5) +#define DW_HDMI_ERROR_FLOW_OFFSET 5 +#define DW_HDMI_ERROR_INITITATOR_MASK BIT(4) +#define DW_HDMI_ERROR_INITITATOR_OFFSET 4 +#define DW_HDMI_ARB_LOST_MASK BIT(3) +#define DW_HDMI_ARB_LOST_OFFSET 3 +#define DW_HDMI_NACK_MASK BIT(2) +#define DW_HDMI_NACK_OFFSET 2 +#define DW_HDMI_EOM_MASK BIT(1) +#define DW_HDMI_EOM_OFFSET 1 +#define DW_HDMI_DONE_MASK BIT(0) +#define DW_HDMI_DONE_OFFSET 0 + +#define DW_HDMI_CEC_ADDR_L 0x1f14 +#define DW_HDMI_CEC_ADDR_H 0x1f18 +#define DW_HDMI_CEC_TX_CNT 0x1f1c +#define DW_HDMI_CEC_RX_CNT 0x1f20 +#define DW_HDMI_CEC_TX_DATA(i) (0x1f40 + ((i) * 4)) +#define DW_HDMI_CEC_TX_DATA_MAX 16 +#define DW_HDMI_CEC_RX_DATA(i) (0x1f80 + ((i) * 4)) +#define DW_HDMI_CEC_RX_DATA_MAX 16 +#define DW_HDMI_CEC_LOCK 0x1fc0 +#define DW_HDMI_CEC_WAKEUPCTRL 0x1fc4 + /* id_cbus Registers */ #define DW_HDMI_CBUSIOCTRL 0x3020 #define DW_HDMI_DATAPATH_CBUSZ_MASK BIT(24)