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envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-2-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 68 ++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 31 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index db56a48343..2672e08197 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1276,6 +1276,12 @@ static void gen_illegal_opcode(DisasContext *s) gen_exception(s, EXCP06_ILLOP, s->pc_start - s->cs_base); } +/* Generate #GP for the current instruction. */ +static void gen_exception_gpf(DisasContext *s) +{ + gen_exception(s, EXCP0D_GPF, s->pc_start - s->cs_base); +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -4502,7 +4508,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) s->vex_l = 0; s->vex_v = 0; if (sigsetjmp(s->jmpbuf, 0) != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); return s->pc; } @@ -6567,7 +6573,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) set_cc_op(s, CC_OP_EFLAGS); } else if (s->vm86) { if (s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); set_cc_op(s, CC_OP_EFLAGS); @@ -6689,7 +6695,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x9c: /* pushf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); if (s->vm86 && s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_update_cc_op(s); gen_helper_read_eflags(s->T0, cpu_env); @@ -6699,7 +6705,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x9d: /* popf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); if (s->vm86 && s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { ot = gen_pop_T0(s); if (s->cpl == 0) { @@ -7061,7 +7067,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xcd: /* int N */ val = x86_ldub_code(env, s); if (s->vm86 && s->iopl != 3) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); } @@ -7084,13 +7090,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->cpl <= s->iopl) { gen_helper_cli(cpu_env); } else { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } } else { if (s->iopl == 3) { gen_helper_cli(cpu_env); } else { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } } break; @@ -7101,7 +7107,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_jmp_im(s, s->pc - s->cs_base); gen_eob_inhibit_irq(s, true); } else { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } break; case 0x62: /* bound */ @@ -7194,7 +7200,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x130: /* wrmsr */ case 0x132: /* rdmsr */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); @@ -7226,7 +7232,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_sysenter(cpu_env); gen_eob(s); @@ -7237,7 +7243,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); gen_eob(s); @@ -7256,7 +7262,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x107: /* sysret */ if (!s->pe) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); /* condition codes are modified only in long mode */ @@ -7278,7 +7284,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xf4: /* hlt */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); @@ -7304,7 +7310,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!s->pe || s->vm86) goto illegal_op; if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); @@ -7325,7 +7331,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!s->pe || s->vm86) goto illegal_op; if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); @@ -7441,7 +7447,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], @@ -7458,7 +7464,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7483,7 +7489,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7496,7 +7502,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7511,7 +7517,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7525,7 +7531,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7549,7 +7555,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7559,7 +7565,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_MEM_OP(2): /* lgdt */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE); @@ -7576,7 +7582,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_MEM_OP(3): /* lidt */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE); @@ -7622,7 +7628,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_OP(6): /* lmsw */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); @@ -7634,7 +7640,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) CASE_MODRM_MEM_OP(7): /* invlpg */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); break; } gen_update_cc_op(s); @@ -7649,7 +7655,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #ifdef TARGET_X86_64 if (CODE64(s)) { if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]); tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env, @@ -7685,7 +7691,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x108: /* invd */ case 0x109: /* wbinvd */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ @@ -8009,7 +8015,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). @@ -8063,7 +8069,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { #ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); @@ -8099,7 +8105,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x106: /* clts */ if (s->cpl != 0) { - gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + gen_exception_gpf(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); From patchwork Wed May 19 18:30:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442461 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1580610jac; Wed, 19 May 2021 11:32:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfwncmk5a+aqDHonVkLy6Ymv40d1WN9hdt1444/lLgQvAT6asvCRUI7ugUw7nErWS4bb7d X-Received: by 2002:a02:7fc1:: with SMTP id r184mr345463jac.109.1621449164311; Wed, 19 May 2021 11:32:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449164; cv=none; d=google.com; s=arc-20160816; b=z7M2a3EaaCL5MV+wgMyik0OyAb1myb+z97z98tsgIOQB5bQbNkTZMYKhikU7/4WOh2 IUh9e00TWesU2PJE/Zku9BT5SAoeERpCG6wV9INM3hy5ge1LagccRKciwJVFguXIDKPs DqRDOej9Y6fPief9BTSyt5IlJErF1H8oMzo9557Xa+T0GujGoTsd1AgP+kcrVu7U5bWz tVcGVubtRbk0Uutq7kySuXJIm5pGCumajxviWIybJnV4OIXLxaiRz7P2NYzb0U+5Fi2r L/8pO+dPqFKp18IfLpZluSp/hHTRncGcePb/fl+jn84UJ6ea0ddgMoYAHj+6DsVCjtSa kLkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=smdeYrB4Z2W/gFXPC6b0JTDnXTfTPJyfpJjMMWQ5xW4=; b=Pjhjx7mVjdRLncxyehdQ+FNO7hRclfRm73bpLlWCQ9fmk+Eq8j9OH6XOARMVZdn9XX pUt+Fj72oTCgkkW/FL6oPT5m/Kh2/TyLg9FgTDX+Ffa0Off6nHu41GUft2DhaVDJ7WwL 2wOfsxn/zdu6zLxxKcD/0kjkw+qNSyugBGMXVuPeFVeWt4ctAYaqRrX0JYS5UmfmUptg DvwIvZN5BW+lMHcOFI7phDMyW04lytXxVkiIj9aZ6shsLn6nEUe70LHLwF1Z7LbkNrXe EDu5HFEWqQuhEgAgEc4qp4o5S/ffORRwSXCX3scr2skM2nOKWuHvj44XFyVNiury9pB+ UZKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MVnE/A5N"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-3-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 79 ++++++++++++++----------------------- 1 file changed, 30 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2672e08197..61b30117a3 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1282,6 +1282,16 @@ static void gen_exception_gpf(DisasContext *s) gen_exception(s, EXCP0D_GPF, s->pc_start - s->cs_base); } +/* Check for cpl == 0; if not, raise #GP and return false. */ +static bool check_cpl0(DisasContext *s) +{ + if (s->cpl == 0) { + return true; + } + gen_exception_gpf(s); + return false; +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -7199,9 +7209,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x130: /* wrmsr */ case 0x132: /* rdmsr */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); if (b & 2) { @@ -7283,9 +7291,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_cpuid(cpu_env); break; case 0xf4: /* hlt */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); @@ -7309,9 +7315,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 2: /* lldt */ if (!s->pe || s->vm86) goto illegal_op; - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); @@ -7330,9 +7334,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 3: /* ltr */ if (!s->pe || s->vm86) goto illegal_op; - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); @@ -7446,8 +7448,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) | PREFIX_REPZ | PREFIX_REPNZ))) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], @@ -7463,8 +7464,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7488,8 +7488,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7501,8 +7500,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7516,8 +7514,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7530,8 +7527,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7554,8 +7550,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!(s->flags & HF_SVME_MASK) || !s->pe) { goto illegal_op; } - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7564,8 +7559,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(2): /* lgdt */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE); @@ -7581,8 +7575,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(3): /* lidt */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE); @@ -7627,8 +7620,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64); break; CASE_MODRM_OP(6): /* lmsw */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); @@ -7639,8 +7631,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(7): /* invlpg */ - if (s->cpl != 0) { - gen_exception_gpf(s); + if (!check_cpl0(s)) { break; } gen_update_cc_op(s); @@ -7654,9 +7645,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xf8: /* swapgs */ #ifdef TARGET_X86_64 if (CODE64(s)) { - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]); tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env, offsetof(CPUX86State, kernelgsbase)); @@ -7690,9 +7679,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x108: /* invd */ case 0x109: /* wbinvd */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ } @@ -8014,9 +8001,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of @@ -8068,9 +8053,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { #ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). @@ -8104,9 +8087,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 0x106: /* clts */ - if (s->cpl != 0) { - gen_exception_gpf(s); - } else { + if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); /* abort block because static cpu state changed */ From patchwork Wed May 19 18:30:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442462 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1580615jac; Wed, 19 May 2021 11:32:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwPMJM8wWm3im2cBcJj/BL3pchpM7pUcjaCdzNT12WDI2VM+DBAnYSVyLOsxfekn3Zmzm7 X-Received: by 2002:a5e:cb45:: with SMTP id h5mr815848iok.207.1621449164577; Wed, 19 May 2021 11:32:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449164; cv=none; d=google.com; s=arc-20160816; b=NntdsdYEDzxyyekmH5Zcj9qHtEo3Y9YR2RXdwX3GUujMaojLSx2amkaclIHigbvLEw Cczgxo6yW2WGNKPPOcWZoCD6WhGLyo1nTaed5+cDHt0ZWZQiANlhowZwYE5vaww0nacW HvOnEEqR/EG1oGqjKviYGxIeJ5tbmfPUE7eohpQ2L6KrIhhGXx9F62uCGqFLPn5NYDy2 BFtnT0oZrmI51Lm3MPuhTHG/zlFNN4xIBQ5nsf+y926GBKsRaOGWTxg0LwCRq9jB1d0v Zhn0pzpGomiRS75nUEeuOwTvJnrABuvCp0OaYnh365mU7DSfFf9+8yLii5iAiJYX5rrd W93g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XkpdcvdsMOsMLR49VnhnztK5w7qTf2fMwT/yaQmjNjQ=; b=RsMFP02HD2a9Z61fGUgOntFpcUmm/M+KXv4gHmiCL+gMiNQCtsR4qUwSzjQIYkEwem IA7ZWOxuvEa4Z+YXliLpXZ5xiPvKajErcRlYLzfFgmb8jT3DYaYpNCOjbjqcO5IUrYg7 zLGXnPUYcbVUraUpqrtPUjsXwq5O7N1c2JfkxaeYPlfZHqUQ+VBMpuuG9Dd63VUTGWYN 4OTicOWq27LSwUKe6wM+ZbtiPPxwmYlbA/k1+J5nM2hYiZQe50l/ULp3PvCl2M2wcWe9 M267QutswNYtiq+pcNijs0jd3WW7pO9IRScReL4qBB93cSajnIUX3QJ8SRP+GSTNFmcJ zbEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PGYfwyeE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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All non-exceptional paths set EFLAGS. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-4-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 61b30117a3..0a15662949 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6577,22 +6577,18 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto do_lret; case 0xcf: /* iret */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); - if (!s->pe) { - /* real mode */ - gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); - set_cc_op(s, CC_OP_EFLAGS); - } else if (s->vm86) { - if (s->iopl != 3) { + if (!s->pe || s->vm86) { + /* real mode or vm86 mode */ + if (s->vm86 && s->iopl != 3) { gen_exception_gpf(s); - } else { - gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); - set_cc_op(s, CC_OP_EFLAGS); + break; } + gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); } else { gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1), tcg_const_i32(s->pc - s->cs_base)); - set_cc_op(s, CC_OP_EFLAGS); } + set_cc_op(s, CC_OP_EFLAGS); gen_eob(s); break; case 0xe8: /* call im */ From patchwork Wed May 19 18:30:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442460 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1579661jac; Wed, 19 May 2021 11:31:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznqgIqaD1otMo0KNp/sBcEfStLoYTjFSL1XTYz0TCfuIM9nsh0rT8K2r5ND8A92Ya/iwV/ X-Received: by 2002:a6b:7d03:: with SMTP id c3mr963884ioq.2.1621449098124; Wed, 19 May 2021 11:31:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449098; cv=none; d=google.com; s=arc-20160816; b=vsemU4jaOhsUCnlQYNABRAEJesaDjmSb222EMmy15ftOB9FHcpOuZvQtaf+I3Kn1Fz /AVey+a7FsvBzYoGQZiAA8b/dDeUHeAXQH4DL8+Q+C3ogt8xE4ntCQhNRJiEm2vlZbXw qVDY4vnVciOtQ2RhVSeG8RFSpH48hiBhohk/RIUOvXL4D7v1/lfrLw0WmaKct5yJlbXU 2sUqbd+wHKDlYuGa7vyppLSjzr4YwVruw36UPRwYJIoxb6HfDG1Ac8l4ExWAhjUc477c X7F0HVvyShop4Inpq9ns35ESmXikbboFGpmR6D9vzpSLvxbB52TT8thpYh4SupIMdNjU 2DrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0LXm7FUdAyY78wIi1+bFyfLTZfZQ4+PVm0Qu4rWwa4U=; b=jbGPr3KSMHK5qYAw7gJ6+bwzHl/iT01X9RIZ/m8NfpCpIsyeniCPBhrpK/Jkp2fDgs WNu7Y1VCvj3I/lInty1unRjpT6bjScRmNRUEBHyLz5IBRVGMKE6T3pwXCc0F3CPuKrvU tTlWT417PMZqyMkMcbVdF4KnFziiu1tUTotHywlaJy8QSRKR6fxkVlO6OOIQH3GvLhDA php0e33RimI1mG7QcxwqTnEhs1o/DZBbUCD7Ff6wwqfMsfocLHGqaKBDvMSgJjHAdnfS nJMBePPOEy8K/nCQ+HY9oMvQ4MOYYDeXyMWFuHSQq+zsS36+YncOK7zLVN0az6ALBUe7 UmCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xdAI+HU1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-5-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 0a15662949..74f6024f82 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1292,6 +1292,16 @@ static bool check_cpl0(DisasContext *s) return false; } +/* If vm86, check for iopl == 3; if not, raise #GP and return false. */ +static bool check_vm86_iopl(DisasContext *s) +{ + if (!s->vm86 || s->iopl == 3) { + return true; + } + gen_exception_gpf(s); + return false; +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -6579,8 +6589,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); if (!s->pe || s->vm86) { /* real mode or vm86 mode */ - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); + if (!check_vm86_iopl(s)) { break; } gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); @@ -6700,9 +6709,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* flags */ case 0x9c: /* pushf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); - } else { + if (check_vm86_iopl(s)) { gen_update_cc_op(s); gen_helper_read_eflags(s->T0, cpu_env); gen_push_v(s, s->T0); @@ -6710,9 +6717,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x9d: /* popf */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); - } else { + if (check_vm86_iopl(s)) { ot = gen_pop_T0(s); if (s->cpl == 0) { if (dflag != MO_16) { @@ -7072,9 +7077,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xcd: /* int N */ val = x86_ldub_code(env, s); - if (s->vm86 && s->iopl != 3) { - gen_exception_gpf(s); - } else { + if (check_vm86_iopl(s)) { gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); } break; From patchwork Wed May 19 18:30:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442467 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1582214jac; Wed, 19 May 2021 11:34:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwscE6BB+QirFWVTxleWKeKmy50Y4h0AECKREPSY6EaOkcxqliwyEkmTMQhxGl6aE7LqqCW X-Received: by 2002:a5e:9e4a:: with SMTP id j10mr960373ioq.52.1621449291204; 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[209.51.188.17]) by mx.google.com with ESMTPS id a5si428718ilj.12.2021.05.19.11.34.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:34:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gguHWSEW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljR1u-0000wj-K1 for patch@linaro.org; Wed, 19 May 2021 14:34:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyE-0003Oj-PX for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:02 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]:34735) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyA-0005Y2-QV for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:02 -0400 Received: by mail-oi1-x22f.google.com with SMTP id u11so14004068oiv.1 for ; Wed, 19 May 2021 11:30:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NjWJ8kBHVuAatpMu3NeT86JZz0YPmJ7lsGR0prh67KA=; b=gguHWSEWPLvMsxPzchXoJvvFZeYcHUHDqtX9QMtPDdhZpnCFxsd7MzcUyswvmzmtet 1LvrwewOT6fKYG3iFOSY6AjKa2SzcJZLk51pz3d+H1U4ZogH7LPQ9iWc5RnJbrkc4A3Z 2RPt16hCKbBrZ3xLvk0xVDZqEgkJiMNoeX/Of6epNDc8tKJctZyuBSlyzJY8HKbVH8j5 WRig4TI1Z5r4GE4vfjn6uxsLWARivDyG8uAvfofK2/i5RwR16mGZy1GusO+4jEx69fPR enO4MVZ1Zkqxic189S9+k2/Q6bba+fIXz23mHk+3EgnqkR8Yo0qWzNxmlGg+E8fAb2FV /woQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NjWJ8kBHVuAatpMu3NeT86JZz0YPmJ7lsGR0prh67KA=; b=rZgN4hImHyxuj8u5M7XXKih7D6OIBsJhOvmoHCYzzkeWV5uZnlu46EbHqDFR/2YMYB EQRRxTS2EQt6OeeCcNFrQBAIn3rj1VkoA2FSZGvy6SB81DC7BRwt1K5X4LHhrbTeTlo5 uZx91vNb0Hp+5JaG4tm5Scm6bAbRWAb3bH8tB4kd5SdFydety0njFQjx73bF2h+tXm/+ zqiqMwa2NqdIZxkSZZ4mHmBC2cPEo4T7FiC8FTa3Jz7opqip2InnxzOtcZj7i8hufxSD e4I0UTNtPvV1LnNDiW0Yq20f7N+3P5WHVvxwmUNlq9MXKPDPuH0KDKyJl+61IBx8QOTK 6rpw== X-Gm-Message-State: AOAM530CnA/oBpoMBXg8GbXLfSGkwk3RsFWcLT4j8cS4sbb0AXl4cqbj TFjeZYiOMcfq8r/ZQK9aURrBIIMMAyWUmrDd X-Received: by 2002:aca:280a:: with SMTP id 10mr529541oix.13.1621449057779; Wed, 19 May 2021 11:30:57 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:30:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/50] target/i386: Split out check_iopl Date: Wed, 19 May 2021 13:30:05 -0500 Message-Id: <20210519183050.875453-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-6-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 74f6024f82..873ed00975 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1302,6 +1302,16 @@ static bool check_vm86_iopl(DisasContext *s) return false; } +/* Check for iopl allowing access; if not, raise #GP and return false. */ +static bool check_iopl(DisasContext *s) +{ + if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) { + return true; + } + gen_exception_gpf(s); + return false; +} + /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { @@ -7095,28 +7105,16 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; #endif case 0xfa: /* cli */ - if (!s->vm86) { - if (s->cpl <= s->iopl) { - gen_helper_cli(cpu_env); - } else { - gen_exception_gpf(s); - } - } else { - if (s->iopl == 3) { - gen_helper_cli(cpu_env); - } else { - gen_exception_gpf(s); - } + if (check_iopl(s)) { + gen_helper_cli(cpu_env); } break; case 0xfb: /* sti */ - if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) { + if (check_iopl(s)) { gen_helper_sti(cpu_env); /* interruptions are enabled only the first insn after sti */ gen_jmp_im(s, s->pc - s->cs_base); gen_eob_inhibit_irq(s, true); - } else { - gen_exception_gpf(s); } break; case 0x62: /* bound */ From patchwork Wed May 19 18:30:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442471 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1584197jac; Wed, 19 May 2021 11:37:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzz8z6HYLcCo8EGsXtd7oRjSW7Lj9XBfN939mQCFzotzXBdCVFjG8fQTrnk17oJpxNMjRgU X-Received: by 2002:a02:ca0d:: with SMTP id i13mr402519jak.98.1621449448143; Wed, 19 May 2021 11:37:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449448; cv=none; d=google.com; s=arc-20160816; b=iIu5q1a4ea/KCiS9eSBs3L6cHYGMvU6i7D6Jby8pOqrGN+4ko2hMuWxGveluKjmAH0 SM5umodk8/pyQ74dkEalVR96NWwsFDX4v0M+xIHCNUg55PvenK2p66C/WCEYK690WiAS 6aTJlk67GBV2Lwj6f0Go+lWZNbZHrKQTDz1SrzVD+tcwHRTcInm1uwxd1vGdCsPn/cPZ GDyiVw0zqm3Gj5AHOEZHTuKAOueLfpUd5pdfO79vo1NFhiZ6st3up7fcCH5xWeRU+z76 npCOJazaFjDnZePwVSKrIzy1V+AnFZguVBRy3HqsjqWd4hO49GvkQ5D459OWAng3/rkQ POrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6jPucf3d8QVYiVwYtTgePgn0/KPRZsWR8rPsX9WQDzE=; b=JoKKh42wK9tFTGCE4Tdrt8iPKgvDTTaJ9+Qt4qU1Rs7qk69IQj+WpzPAYs6Zx3bStF dG1HUx0C2mmd361uzcUlKVJ/n7RxZGkGXe7NAM223rbSWQiHjbe4FjMzCy9KrU9RBIry QbywurmXeJprST9O6Kd2/Uic9xMI7snF3yE1reaJDWM7d/jig7uHyRnRf6uIkPOLoO7o ZcIyxHlpR8ieoCLFcE4jd5EbViUtDc6UZ8Slx8zlSC5ZlFPFo3FkxOnW4XcfgftZ+FBR K3JhRNqLlrz23CHbOUjKbMuJu4SOJ+Flm0RWSzvvmF2MUWaNS+XY00/75j+/0WVa9I3V fCHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GOSFBsBu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Since we're adding an accessor macro, pull the value directly out of flags for sysemu. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-7-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 69 +++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 873ed00975..7f3993fccb 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -94,7 +94,6 @@ typedef struct DisasContext { target_ulong pc; /* pc = eip + cs_base */ /* current block context */ target_ulong cs_base; /* base of CS segment */ - int pe; /* protected mode */ int code32; /* 32 bit code segment */ #ifdef TARGET_X86_64 int lma; /* long mode active */ @@ -146,6 +145,13 @@ typedef struct DisasContext { sigjmp_buf jmpbuf; } DisasContext; +/* The environment in which user-only runs is constrained. */ +#ifdef CONFIG_USER_ONLY +#define PE(S) true +#else +#define PE(S) (((S)->flags & HF_PE_MASK) != 0) +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -617,7 +623,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (s->pe && (s->cpl > s->iopl || s->vm86)) { + if (PE(s) && (s->cpl > s->iopl || s->vm86)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -2345,7 +2351,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) call this function with seg_reg == R_CS */ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32); /* abort translation because the addseg value may change or @@ -5108,7 +5114,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_lcall: - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_i32(dflag - 1), @@ -5138,7 +5144,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_ljmp: - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_tl(s->pc - s->cs_base)); @@ -6571,7 +6577,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xca: /* lret im */ val = x86_ldsw_code(env, s); do_lret: - if (s->pe && !s->vm86) { + if (PE(s) && !s->vm86) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), @@ -6597,7 +6603,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto do_lret; case 0xcf: /* iret */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); - if (!s->pe || s->vm86) { + if (!PE(s) || s->vm86) { /* real mode or vm86 mode */ if (!check_vm86_iopl(s)) { break; @@ -7236,7 +7242,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* For Intel SYSENTER is valid on 64-bit */ if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; - if (!s->pe) { + if (!PE(s)) { gen_exception_gpf(s); } else { gen_helper_sysenter(cpu_env); @@ -7247,7 +7253,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* For Intel SYSEXIT is valid on 64-bit */ if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; - if (!s->pe) { + if (!PE(s)) { gen_exception_gpf(s); } else { gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); @@ -7266,7 +7272,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_eob_worker(s, false, true); break; case 0x107: /* sysret */ - if (!s->pe) { + if (!PE(s)) { gen_exception_gpf(s); } else { gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); @@ -7301,7 +7307,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) op = (modrm >> 3) & 7; switch(op) { case 0: /* sldt */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7310,7 +7316,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 2: /* lldt */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); @@ -7320,7 +7326,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 1: /* str */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7329,7 +7335,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 3: /* ltr */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); @@ -7340,7 +7346,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 4: /* verr */ case 5: /* verw */ - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_update_cc_op(s); @@ -7458,7 +7464,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xd8: /* VMRUN */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7482,7 +7488,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xda: /* VMLOAD */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7494,7 +7500,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdb: /* VMSAVE */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7508,7 +7514,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xdc: /* STGI */ if ((!(s->flags & HF_SVME_MASK) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) - || !s->pe) { + || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7521,7 +7527,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdd: /* CLGI */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7535,7 +7541,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xde: /* SKINIT */ if ((!(s->flags & HF_SVME_MASK) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) - || !s->pe) { + || !PE(s)) { goto illegal_op; } gen_update_cc_op(s); @@ -7544,7 +7550,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdf: /* INVLPGA */ - if (!(s->flags & HF_SVME_MASK) || !s->pe) { + if (!(s->flags & HF_SVME_MASK) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7711,7 +7717,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) TCGLabel *label1; TCGv t0, t1, t2, a0; - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; t0 = tcg_temp_local_new(); t1 = tcg_temp_local_new(); @@ -7759,7 +7765,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { TCGLabel *label1; TCGv t0; - if (!s->pe || s->vm86) + if (!PE(s) || s->vm86) goto illegal_op; ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); @@ -8461,9 +8467,13 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUX86State *env = cpu->env_ptr; uint32_t flags = dc->base.tb->flags; - target_ulong cs_base = dc->base.tb->cs_base; - dc->pe = (flags >> HF_PE_SHIFT) & 1; + dc->cs_base = dc->base.tb->cs_base; + dc->flags = flags; + + /* We make some simplifying assumptions; validate they're correct. */ + g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); + dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; @@ -8474,7 +8484,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; - dc->cs_base = cs_base; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8491,7 +8500,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->lma = (flags >> HF_LMA_SHIFT) & 1; dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif - dc->flags = flags; dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because @@ -8505,11 +8513,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) additional step for ecx=0 when icount is enabled. */ dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT); -#if 0 - /* check addseg logic */ - if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) - printf("ERROR addseg\n"); -#endif dc->T0 = tcg_temp_new(); dc->T1 = tcg_temp_new(); From patchwork Wed May 19 18:30:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442466 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1582210jac; Wed, 19 May 2021 11:34:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjocE5dadPrtyCYztChUMbgTAuwbxg1ehPtIAwKKumne85zqFjV6Y7NgwSfU0Aep0jXB65 X-Received: by 2002:a5d:8787:: with SMTP id f7mr933394ion.108.1621449291067; Wed, 19 May 2021 11:34:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449291; cv=none; d=google.com; s=arc-20160816; b=yiamlal5V2xPeCAFs9VM5iML8LHESYbG6qSXYYnnooBvY1ynuQZEqtb8d9/XBV2K20 DmWUTP339zijv2oJU9idSSn3q8QyYikyJ+I3SLUTVS8zfkNVPkl+WnAcJMIfiU8VIMeK Li5LC9dH3DW2sx5nnXY7Vi3n3yDp8qHtDD/F28QsIpSvSqWLu8XXcXoRcOF3WtlJo6KH 3pe2S4R9LVMcbgjfL0PyPsAw9JLKviVnc04C1raCj8XO9W0X2V0q5VCAMb90aExqL1mU f1mFwaJRPGA6MMG/iMXSALWDaTzkrt1mMrY9u2JPYPdNIhpMCmwY4Alpj5uwtidrTYWG 7o+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I9LVl7NkZXjA3C65kTwIIt1lI1AlgmXPdeZo4OH5Iz0=; b=X/M2nXwJImKhUGENf9tFTvGYQdeKKV3zKUDgavyj9vlYfkwcYd34tRRh8znnJ3m/dF /e9E4p6AF5gVMKdnfI6B47U0vQZtpNZep3mzO2eGgDx7m8X8xW1KP87v/yU4+K2Rt/M2 71SP+NC9gbepuwf0P8F73K7BH9JughAtA8q+I83OS5THkdz2F13UM1ScMdWk22J3t1E8 pFqiPqkZeb6EGqYcuBTeCMq5ARAK0hOhkgm5gmhwI38ESsuaojrmBkeDkoemxj7m355i SdgrYpbEbFNB5nt+V7XRSW71kMn+KEVEzr3rnCkZMQLvF3YHfnKEQ01GswDelVSOXzYJ ar0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QM56g6oT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-8-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7f3993fccb..4c9194416d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -94,6 +94,11 @@ typedef struct DisasContext { target_ulong pc; /* pc = eip + cs_base */ /* current block context */ target_ulong cs_base; /* base of CS segment */ + +#ifndef CONFIG_USER_ONLY + uint8_t cpl; /* code priv level */ +#endif + int code32; /* 32 bit code segment */ #ifdef TARGET_X86_64 int lma; /* long mode active */ @@ -111,7 +116,6 @@ typedef struct DisasContext { int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ int vm86; /* vm86 mode */ - int cpl; int iopl; int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ @@ -148,8 +152,10 @@ typedef struct DisasContext { /* The environment in which user-only runs is constrained. */ #ifdef CONFIG_USER_ONLY #define PE(S) true +#define CPL(S) 3 #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) +#define CPL(S) ((S)->cpl) #endif static void gen_eob(DisasContext *s); @@ -623,7 +629,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (PE(s) && (s->cpl > s->iopl || s->vm86)) { + if (PE(s) && (CPL(s) > s->iopl || s->vm86)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -1291,7 +1297,7 @@ static void gen_exception_gpf(DisasContext *s) /* Check for cpl == 0; if not, raise #GP and return false. */ static bool check_cpl0(DisasContext *s) { - if (s->cpl == 0) { + if (CPL(s) == 0) { return true; } gen_exception_gpf(s); @@ -1311,7 +1317,7 @@ static bool check_vm86_iopl(DisasContext *s) /* Check for iopl allowing access; if not, raise #GP and return false. */ static bool check_iopl(DisasContext *s) { - if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) { + if (s->vm86 ? s->iopl == 3 : CPL(s) <= s->iopl) { return true; } gen_exception_gpf(s); @@ -6735,7 +6741,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); if (check_vm86_iopl(s)) { ot = gen_pop_T0(s); - if (s->cpl == 0) { + if (CPL(s) == 0) { if (dflag != MO_16) { gen_helper_write_eflags(cpu_env, s->T0, tcg_const_i32((TF_MASK | AC_MASK | @@ -6750,7 +6756,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) & 0xffff)); } } else { - if (s->cpl <= s->iopl) { + if (CPL(s) <= s->iopl) { if (dflag != MO_16) { gen_helper_write_eflags(cpu_env, s->T0, tcg_const_i32((TF_MASK | @@ -7380,7 +7386,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xc8: /* monitor */ - if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || s->cpl != 0) { + if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) { goto illegal_op; } gen_update_cc_op(s); @@ -7392,7 +7398,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xc9: /* mwait */ - if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || s->cpl != 0) { + if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || CPL(s) != 0) { goto illegal_op; } gen_update_cc_op(s); @@ -7403,7 +7409,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xca: /* clac */ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) - || s->cpl != 0) { + || CPL(s) != 0) { goto illegal_op; } gen_helper_clac(cpu_env); @@ -7413,7 +7419,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xcb: /* stac */ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) - || s->cpl != 0) { + || CPL(s) != 0) { goto illegal_op; } gen_helper_stac(cpu_env); @@ -8467,19 +8473,23 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUX86State *env = cpu->env_ptr; uint32_t flags = dc->base.tb->flags; + int cpl = (flags >> HF_CPL_SHIFT) & 3; dc->cs_base = dc->base.tb->cs_base; dc->flags = flags; +#ifndef CONFIG_USER_ONLY + dc->cpl = cpl; +#endif /* We make some simplifying assumptions; validate they're correct. */ g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); + g_assert(CPL(dc) == cpl); dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->vm86 = (flags >> VM_SHIFT) & 1; - dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; From patchwork Wed May 19 18:30:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442474 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1585619jac; Wed, 19 May 2021 11:39:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjgGZA5lYjTcU1nrlXr3/AbPf5k16uNRAw3Y7CgrHtwU77Xz15L6ouvbzXc6ICvxfxbvy1 X-Received: by 2002:a02:ba08:: with SMTP id z8mr429160jan.74.1621449563738; Wed, 19 May 2021 11:39:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449563; cv=none; d=google.com; s=arc-20160816; b=KHeixJbb/LhaGyYmJoe6to4KYFYnIGnM+mdWOnJKx/QUzGGdJ0cE4sHwV0wnt13wLh S5NDlpKUhsNJn/GAZD0KhF7igKehtrkeekDPw7SJVCwsRXjfIRQWBU94qLK278kSCIE6 itd0Wv+lml7PFSr/HXrl20+Lmev48OLdCd9y57xoioW4yu677OtjbZtUDSfjwTkZIlW4 Z5C3b2k5y9vHmr/iZvzOQvSuPEinSpsRZ1EDaoJ/Kr5osixy6jjqDTvXN+Gxpjg3iiBo eRkpHikmDsF8IQdckW8GSncH3p4oawRMGRu6/Rqhaz890Mlc9fLfiNpUmcTS9Jod8oKn NnCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nrfuvBj4GUNKQqnvsf33MOe2/3eRkVdIcnIjEJTkPfA=; b=AKSAKcG2aYAcWeD6dXcnnwZxa3UxOJ+1bw7W94or2/cPxyHUSl/tCayTld4yEWhhee DcMsxPljUxw8RGBE/1OYVhYt78MnAsHze/kbFOCgymi5yEX8nUE4VjO7IcY6sffDaxqZ ZdknzTeiOJnucpPQjuVyvIw5wB6gm8l9I43ESYq3xuhCiVTWBd8GaEZrzvcABjQnoJLP KrXY4AfFF8eY43biqv3TKTYQSDm3BR3LkhMBWEAaPDkfhCElMPneHQ8+lLBH/GcOazee gK49mqfqQL2qrQy/8sI9ZlIe8clcssaKqJJ9Lr9YXX/llpvz09cE2eI9eJNRqMbl9baG LH+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zkrZJp1U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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However, QEMU cannot and does not implement this syscall, so the IOPL is never changed from 0. Which means that all of the checks vs CPL <= IOPL are false for user-only. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-9-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4c9194416d..b8cb7163ee 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -97,6 +97,7 @@ typedef struct DisasContext { #ifndef CONFIG_USER_ONLY uint8_t cpl; /* code priv level */ + uint8_t iopl; /* i/o priv level */ #endif int code32; /* 32 bit code segment */ @@ -116,7 +117,6 @@ typedef struct DisasContext { int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ int vm86; /* vm86 mode */ - int iopl; int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -153,9 +153,11 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY #define PE(S) true #define CPL(S) 3 +#define IOPL(S) 0 #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) #define CPL(S) ((S)->cpl) +#define IOPL(S) ((S)->iopl) #endif static void gen_eob(DisasContext *s); @@ -629,7 +631,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (PE(s) && (CPL(s) > s->iopl || s->vm86)) { + if (PE(s) && (CPL(s) > IOPL(s) || s->vm86)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -1307,7 +1309,7 @@ static bool check_cpl0(DisasContext *s) /* If vm86, check for iopl == 3; if not, raise #GP and return false. */ static bool check_vm86_iopl(DisasContext *s) { - if (!s->vm86 || s->iopl == 3) { + if (!s->vm86 || IOPL(s) == 3) { return true; } gen_exception_gpf(s); @@ -1317,7 +1319,7 @@ static bool check_vm86_iopl(DisasContext *s) /* Check for iopl allowing access; if not, raise #GP and return false. */ static bool check_iopl(DisasContext *s) { - if (s->vm86 ? s->iopl == 3 : CPL(s) <= s->iopl) { + if (s->vm86 ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) { return true; } gen_exception_gpf(s); @@ -6756,7 +6758,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) & 0xffff)); } } else { - if (CPL(s) <= s->iopl) { + if (CPL(s) <= IOPL(s)) { if (dflag != MO_16) { gen_helper_write_eflags(cpu_env, s->T0, tcg_const_i32((TF_MASK | @@ -8474,23 +8476,25 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) CPUX86State *env = cpu->env_ptr; uint32_t flags = dc->base.tb->flags; int cpl = (flags >> HF_CPL_SHIFT) & 3; + int iopl = (flags >> IOPL_SHIFT) & 3; dc->cs_base = dc->base.tb->cs_base; dc->flags = flags; #ifndef CONFIG_USER_ONLY dc->cpl = cpl; + dc->iopl = iopl; #endif /* We make some simplifying assumptions; validate they're correct. */ g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); g_assert(CPL(dc) == cpl); + g_assert(IOPL(dc) == iopl); dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->vm86 = (flags >> VM_SHIFT) & 1; - dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Wed May 19 18:30:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442470 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1584139jac; Wed, 19 May 2021 11:37:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/hW8J5P6zBOGQirs1We9O0STy3fVB1AIJY0/GXLBZtuVfoPWQJC3pORoGJtjvV/BtgDO5 X-Received: by 2002:a5e:c742:: with SMTP id g2mr959255iop.40.1621449444059; Wed, 19 May 2021 11:37:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449444; cv=none; d=google.com; s=arc-20160816; b=j8W0IkcWQn5jC1eL+yZef1/miRBvtjwx7NcB0aGsJvrufgfxVRM1DEGoQZKDr8nWv1 tB4gNmshxNBMp49RXFzL1MzmCgt2Bl6jdOmY9LWtxQnznfbKwyXm1PEdR2g7LA0YYa0u 20UB+bjEuOqO++DugLAN8I0urmYPggK2iqHlqfKDfRmx/xIsffra8sxJfc5F3Zznm2n/ 3VmjctLGyPcnkjKACdciVTMQJd55KQTBSfncez/MiDuou9JgsFsMJR3gE7N0I8sWSOKn m05I6FUoAPEATYedf4s9T+4tSD0bZGV9K4LgitUQG8dLoLix+MJy9IgC5oGmo2I8f/eH OQRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=H97J/X+gbpTJ/IXxWIClRRLCVFWwmw/HeKJHT9Kyg8U=; b=s1H3E+VMSmm93ax875nzP6FY7/yd21c9olv3hjJVqI47T0DQSnZBYCYi0aM18Q5t83 6rehGs/EbKSRvTzuQTUuUmTR47IlWlS1yglnMSgPHZEFMY4M8DKboXbaEVNnKXKST/vz Fq4o6xM8gie0fEGjUGNtd7gVFfPmieot0WYQnQV7BMK0bqe3TZ/4k3sWxoDPiiQMSD7t 8ouNrXWw4wUNZR3USNeWSokCsPwTKA2mlZAu3HpkjJ1W3063Oxx2exH7zG3+HPOhGLpK zbUWT2sR4q3l8xN9jnJEAOjHaBK7zO0pCOY036jJjAjfogrd/7HaO3F8V9eqXUrnkDqI VZVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/vBJVzF"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That syscall explicitly returns to 32-bit mode, and the syscall does not exist for a 64-bit x86_64 executable. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-10-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 40 ++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b8cb7163ee..27806f35f9 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -116,7 +116,6 @@ typedef struct DisasContext { #endif int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ - int vm86; /* vm86 mode */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -159,6 +158,11 @@ typedef struct DisasContext { #define CPL(S) ((S)->cpl) #define IOPL(S) ((S)->iopl) #endif +#if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) +#define VM86(S) false +#else +#define VM86(S) (((S)->flags & HF_VM_MASK) != 0) +#endif static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); @@ -631,7 +635,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, { target_ulong next_eip; - if (PE(s) && (CPL(s) > IOPL(s) || s->vm86)) { + if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: @@ -1309,7 +1313,7 @@ static bool check_cpl0(DisasContext *s) /* If vm86, check for iopl == 3; if not, raise #GP and return false. */ static bool check_vm86_iopl(DisasContext *s) { - if (!s->vm86 || IOPL(s) == 3) { + if (!VM86(s) || IOPL(s) == 3) { return true; } gen_exception_gpf(s); @@ -1319,7 +1323,7 @@ static bool check_vm86_iopl(DisasContext *s) /* Check for iopl allowing access; if not, raise #GP and return false. */ static bool check_iopl(DisasContext *s) { - if (s->vm86 ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) { + if (VM86(s) ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) { return true; } gen_exception_gpf(s); @@ -2359,7 +2363,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) call this function with seg_reg == R_CS */ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32); /* abort translation because the addseg value may change or @@ -4615,7 +4619,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xc4: /* 3-byte VEX */ /* VEX prefixes cannot be used except in 32-bit mode. Otherwise the instruction is LES or LDS. */ - if (s->code32 && !s->vm86) { + if (s->code32 && !VM86(s)) { static const int pp_prefix[4] = { 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ }; @@ -5122,7 +5126,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_lcall: - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_i32(dflag - 1), @@ -5152,7 +5156,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_add_A0_im(s, 1 << ot); gen_op_ld_v(s, MO_16, s->T0, s->A0); do_ljmp: - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1, tcg_const_tl(s->pc - s->cs_base)); @@ -6585,7 +6589,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xca: /* lret im */ val = x86_ldsw_code(env, s); do_lret: - if (PE(s) && !s->vm86) { + if (PE(s) && !VM86(s)) { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), @@ -6611,7 +6615,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto do_lret; case 0xcf: /* iret */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); - if (!PE(s) || s->vm86) { + if (!PE(s) || VM86(s)) { /* real mode or vm86 mode */ if (!check_vm86_iopl(s)) { break; @@ -7315,7 +7319,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) op = (modrm >> 3) & 7; switch(op) { case 0: /* sldt */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7324,7 +7328,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 2: /* lldt */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); @@ -7334,7 +7338,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 1: /* str */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, @@ -7343,7 +7347,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 3: /* ltr */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); @@ -7354,7 +7358,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 4: /* verr */ case 5: /* verw */ - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_update_cc_op(s); @@ -7725,7 +7729,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) TCGLabel *label1; TCGv t0, t1, t2, a0; - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; t0 = tcg_temp_local_new(); t1 = tcg_temp_local_new(); @@ -7773,7 +7777,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { TCGLabel *label1; TCGv t0; - if (!PE(s) || s->vm86) + if (!PE(s) || VM86(s)) goto illegal_op; ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); @@ -8489,12 +8493,12 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0)); g_assert(CPL(dc) == cpl); g_assert(IOPL(dc) == iopl); + g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; - dc->vm86 = (flags >> VM_SHIFT) & 1; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Wed May 19 18:30:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442476 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1588056jac; Wed, 19 May 2021 11:43:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwcGiaUBmQ1y0sgd2Ttq7Hajxyn1OEPDyMgfMf1LC/2be7JR41JTE8f/Siu/F38oXE9HOJo X-Received: by 2002:a5d:8188:: with SMTP id u8mr959417ion.163.1621449786059; Wed, 19 May 2021 11:43:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449786; cv=none; d=google.com; s=arc-20160816; b=A2MJKYxIeiqvMwcwPHmhy/dqRzMyIzEtEb3XHc1POxEgykG29XcxA5SYWFsbQxpgvp B/3cSm6WG5XoWo5dNadiHjA22larfZcxrwuBlpIMYqrfw7Zh+NWQPrGIAYyv19j/oZS7 MvZfjXKNrZgGDBincsTnLA6vom1ias1YDgNiUnb58fEECH8m9HBQyNgeHY69UbHz2Z2a CX2eiTBepcsZjSwiHaRTn+ccDIQZHAeh6bXp0RMM1T9U/B0C3PTrcw4yoBxok8W4eDyi iwrJm3LXpcFjYajC8duWnPhd3/JirKnMZR5vTQJ3Aghbe5jQQbVL7+E1jmnl+/KUM71H cndw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mZrjIdoHsYv9s/pOgxcbiN0IEOU2edVxfdbfsxChIBE=; b=dCP1BJ6xS3SzXIlcMqsOi4ENwznqUVB/R9aOEozdQZP5IaTAMtN/3bOOOyGAQzbrpG sCevRgF8Tf6jypVYZ4Y6eqGyeAYt9u/z5XNZGFR7JPHB+ksMe71ePNqE0CB5JJmV2e5d ZXt9ZCPtJM2mM9TlnRGtb2VURq+vkJDVrNQ32Foo0gUpGu3u+7JdF7h2u+vsXQVG99qb QYXQS7VJwUQ1JeV8PC3DbGC9KCWCad+4XioRF5jiXBZFCCg6LwR1Dw1dnO5I44XCUIB/ 9dEzW7xy+NQcxTe76aSezz/XvSoEw2nW8YzxWBTFN+RXNx81fcocjNxVc7pYs/a5vB2Y R5oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MTGWI1Dq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z1si447483ilh.23.2021.05.19.11.43.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:43:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MTGWI1Dq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljR9t-0001wJ-E6 for patch@linaro.org; Wed, 19 May 2021 14:43:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyJ-0003Yv-6i for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:07 -0400 Received: from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332]:44947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyF-0005c6-Sy for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:06 -0400 Received: by mail-ot1-x332.google.com with SMTP id r26-20020a056830121ab02902a5ff1c9b81so12602737otp.11 for ; Wed, 19 May 2021 11:31:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mZrjIdoHsYv9s/pOgxcbiN0IEOU2edVxfdbfsxChIBE=; b=MTGWI1Dq1vKic44Aw+HLAxnQ71Qx3QywXc1P7F3tB4u0Hv/6JdKxQ7x2zdcyc7ZB1A waWgmiZT5kqYh1fIjTud+m6ZYb4Ok3KrKGO5qkopqa0I3cMVlttTqrUExSrrYul9tFW+ bPvVvB95LfaqJTePcGoY1X+WoDB0EsYV8Lcy0Y2cwcYMj3RiZbp1ukhMCOiawRxRpY88 M9/1E6OD7DihzOWLhdNUW7BIl5j2dTHWM7Tq0O9K/K9+ns9OzK4uBOVUAAOuPRk6wGhv tYF9PH9l6W21VN54zxPNvuPV638fJcfFvRjWi+RiZT7MCVuIkUby9Lcs4hegNeplgHX/ dO6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mZrjIdoHsYv9s/pOgxcbiN0IEOU2edVxfdbfsxChIBE=; b=PsGK9hvgu1D6sX/533pMVGW+N63Paxc6ukBwvJ1n16PhujOBcnV11mLbdHozPJd1xS gC/WSMFU50d21nAUWSJLq7ogYOv7WT2Iyj56mq76sB+nOS2Sh+96Q3Bs3XLdWVc74ozu +lo/P64zHmCCYOWTrl61erNxykRr1v0gyCoRUmJjuV31dMNUmOSp7zCqk2WF1Do3PKSL 2pjppgd25sepNadIp5oTUQmCVCNZNNn/c7ztTBRY7tc14D1qar42YvwIO1Mij0irDiMv U7vL7RzLMKPvoilvXbZX0BzHiES4amaBlzj+BHNGJ4rLfHWoPrFbC6g2SMfScsYcpWpz inmQ== X-Gm-Message-State: AOAM530GyQ95ZZ4kIuEcHpFJ2gLYMjogL3dkqbwcRtHu4QCO4lG28fyG GeuZ0EIRf5yUJMMhBTZHh2g5+lnxuwcaTjhU X-Received: by 2002:a9d:1d45:: with SMTP id m63mr649692otm.302.1621449062589; Wed, 19 May 2021 11:31:02 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/50] target/i386: Assert CODE32 for x86_64 user-only Date: Wed, 19 May 2021 13:30:10 -0500 Message-Id: <20210519183050.875453-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For user-only, CODE32 == !VM86, because we are never in real-mode. Since we cannot enter vm86 mode for x86_64 user-only, CODE32 is always set. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-11-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 27806f35f9..b570921410 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -100,7 +100,6 @@ typedef struct DisasContext { uint8_t iopl; /* i/o priv level */ #endif - int code32; /* 32 bit code segment */ #ifdef TARGET_X86_64 int lma; /* long mode active */ int code64; /* 64 bit code segment */ @@ -160,8 +159,10 @@ typedef struct DisasContext { #endif #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false +#define CODE32(S) true #else #define VM86(S) (((S)->flags & HF_VM_MASK) != 0) +#define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #endif static void gen_eob(DisasContext *s); @@ -2370,7 +2371,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) { + if (seg_reg == R_SS || (CODE32(s) && seg_reg < R_FS)) { s->base.is_jmp = DISAS_TOO_MANY; } } else { @@ -4619,7 +4620,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xc4: /* 3-byte VEX */ /* VEX prefixes cannot be used except in 32-bit mode. Otherwise the instruction is LES or LDS. */ - if (s->code32 && !VM86(s)) { + if (CODE32(s) && !VM86(s)) { static const int pp_prefix[4] = { 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ }; @@ -4686,13 +4687,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64); } else { /* In 16/32-bit mode, 0x66 selects the opposite data size. */ - if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) { + if (CODE32(s) ^ ((prefixes & PREFIX_DATA) != 0)) { dflag = MO_32; } else { dflag = MO_16; } /* In 16/32-bit mode, 0x67 selects the opposite addressing. */ - if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) { + if (CODE32(s) ^ ((prefixes & PREFIX_ADR) != 0)) { aflag = MO_32; } else { aflag = MO_16; @@ -8494,8 +8495,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(CPL(dc) == cpl); g_assert(IOPL(dc) == iopl); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); + g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); - dc->code32 = (flags >> HF_CS32_SHIFT) & 1; dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; From patchwork Wed May 19 18:30:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442464 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1581823jac; Wed, 19 May 2021 11:34:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxN/Qcnp/nzLMGXwxsYJbYY/mbW/BPCX0MIw3cKpHceEWHhnOUi68QyLAU4+dqR5JwHGZrX X-Received: by 2002:a05:6e02:218a:: with SMTP id j10mr458209ila.264.1621449260701; Wed, 19 May 2021 11:34:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449260; cv=none; d=google.com; s=arc-20160816; b=BqaRpviqVyW54yWnki7YLjhIZGUVLI4t/kOzz60ZYWqiODZ5oT2aFhFbr6xhbhp0Bo UEVGNm5v4YYBg0jPcIIJ84VenibzeqeSruDgBoSzrhi0d4BoookcGEiD4Ay3yJXbAwom QuaN9xy0LvOt6Jj0pRRfN2ziELwTqlwHKiCIoqtG/fkdNc5h+gPEwQINbjA82F5bimUw bUtysoVUEqwctMaWjWgzJFJv80JN+sMFk1wgjeqJfHtr7AuGPe6fCSLRQg9mIVsraGkb 0p2OZf4TXT6/j6D80OX5sOHeSClyLfUTu9fO9eKHWYj3CDJTbXAQnmNsWynIGj4WLlni G+rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WSEAQX4xoDFetSNg7thFVzG9HtsA7xC95w5bxK6vv/Y=; b=krx2KaEEYit41FzILDVfaM1dIcHcT70MpTE29gvmu6diwAYV5WQR2xvg9FWpBy1bec At05+5NPsewjGh2wmM1i1TN+crQKluq/5LpEqogDcSJuJ2ofvbofvxZ79CK6ranMH58d jm7KxxKwAkz8uQYS8aebi+bg5blDpIVbKVjv0AHRBOhHxW8G+w0wP9A+N/Xr1ye/5Zsc A9LAOSc+RO5yWhmdD5ZwskQVC8DkfAySGbghKGOqKRhTfEpMBc/qH6ZizilczIIt9xIa U74cujAGkkcq9w0/0IZ8JI3x9FOf7MwH2H0K6hKKCF0JUtinK2YTIuKUxMYT+pc0mszo 0gcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GNeqFw4t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k5si451365ilv.81.2021.05.19.11.34.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:34:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GNeqFw4t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljR1Q-0000vC-42 for patch@linaro.org; Wed, 19 May 2021 14:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyL-0003gm-Sf for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:09 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]:46766) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyG-0005d5-PA for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:09 -0400 Received: by mail-oi1-x229.google.com with SMTP id x15so13957928oic.13 for ; Wed, 19 May 2021 11:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WSEAQX4xoDFetSNg7thFVzG9HtsA7xC95w5bxK6vv/Y=; b=GNeqFw4tGH2sLzPy8JddiI1DFhZcD7MSEvWZrrn9P1NTimYlBz0jaFqjAwChTaTlw2 mCN9jHHHBpGwDymASedCe9FelXQp3zjlw67ExS8aaTSvGH6MY0uquMySq2ApjSuCr45X lBVkJf6EDYv5oaEYn575VYIutDSSSTDzURnc20UaFHm+GLM0W5tSjveBiHUCDVgLHOQa gSoSvrx0vMlWqD1iE9zVDlSmr31pLOrWJo1teLallOFQwZPKUhgjd8wsf4tjLqomh64u 4ZZ3pizGRxw/eLheHDmfHV3Yux6yh2W1sY3DZSXFz11amQxnGqNYuhMXo1JfuvbXnId8 Ubiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WSEAQX4xoDFetSNg7thFVzG9HtsA7xC95w5bxK6vv/Y=; b=Srq2lYz1y7H7sE9lLwYxV3TTQaJrOcfsCWFc6x/8vN0z9O98rcSeMPvY9gDbqtD50O YlQEdOIiy2t9Ve1IdP35q9kbgTS1ma1/N9wONnKBxb/lqa6oawO7t8Pk3YQng3dMQnXb Zk27/56gmsvX89Kmkd6UL9Wd3dtLiurmuXTD2YnRyN0hbAHbFmDxXD3VsPEdwENK801g dECHjmSjCLx1p6E4XLRq8URRkRyVdtHZH+/TCs3l9ewHc5lzHSWxJkHKO5t5k9c/3Cmy 86C8RjQW1auQrym/hDPwhYiNKMH8s6Yyte9RMepfrQ5U6MWI4HLwHh7K/TVwLMhkn0Wu 98LQ== X-Gm-Message-State: AOAM53179EiR6jhd2naKCjnhgW8YkWcv/dcvc+n+ZHmVTmCCZhNh+6KE h9GpMlYWY53CQrClzhyk4AZM51BMbwdZN7Le X-Received: by 2002:a05:6808:b08:: with SMTP id s8mr503642oij.162.1621449063523; Wed, 19 May 2021 11:31:03 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/50] target/i386: Assert SS32 for x86_64 user-only Date: Wed, 19 May 2021 13:30:11 -0500 Message-Id: <20210519183050.875453-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For user-only, SS32 == !VM86, because we are never in real-mode. Since we cannot enter vm86 mode for x86_64 user-only, SS32 is always set. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-12-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b570921410..7b5031f647 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -107,7 +107,6 @@ typedef struct DisasContext { #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ - int ss32; /* 32 bit stack segment */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; #ifdef TARGET_X86_64 @@ -160,9 +159,11 @@ typedef struct DisasContext { #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false #define CODE32(S) true +#define SS32(S) true #else #define VM86(S) (((S)->flags & HF_VM_MASK) != 0) #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) +#define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) #endif static void gen_eob(DisasContext *s); @@ -352,7 +353,7 @@ static inline MemOp mo_pushpop(DisasContext *s, MemOp ot) /* Select the size of the stack pointer. */ static inline MemOp mo_stacksize(DisasContext *s) { - return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; + return CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16; } /* Select only size 64 else 32. Used for SSE operand sizes. */ @@ -2451,12 +2452,12 @@ static inline void gen_pop_update(DisasContext *s, MemOp ot) static inline void gen_stack_A0(DisasContext *s) { - gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1); + gen_lea_v_seg(s, SS32(s) ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1); } static void gen_pusha(DisasContext *s) { - MemOp s_ot = s->ss32 ? MO_32 : MO_16; + MemOp s_ot = SS32(s) ? MO_32 : MO_16; MemOp d_ot = s->dflag; int size = 1 << d_ot; int i; @@ -2472,7 +2473,7 @@ static void gen_pusha(DisasContext *s) static void gen_popa(DisasContext *s) { - MemOp s_ot = s->ss32 ? MO_32 : MO_16; + MemOp s_ot = SS32(s) ? MO_32 : MO_16; MemOp d_ot = s->dflag; int size = 1 << d_ot; int i; @@ -2494,7 +2495,7 @@ static void gen_popa(DisasContext *s) static void gen_enter(DisasContext *s, int esp_addend, int level) { MemOp d_ot = mo_pushpop(s, s->dflag); - MemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; + MemOp a_ot = CODE64(s) ? MO_64 : SS32(s) ? MO_32 : MO_16; int size = 1 << d_ot; /* Push BP; compute FrameTemp into T1. */ @@ -8496,8 +8497,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(IOPL(dc) == iopl); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); + g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); - dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; From patchwork Wed May 19 18:30:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442469 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1584137jac; Wed, 19 May 2021 11:37:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxmWlg9prAlCePZ3zwrQCZUKjMQqUoswyav+GTDB+nuxIuNm9jzSssa+cSgyX8XvTC9Xki X-Received: by 2002:a02:8787:: with SMTP id t7mr374274jai.53.1621449444012; Wed, 19 May 2021 11:37:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449444; cv=none; d=google.com; s=arc-20160816; b=LuYGmpAF+uEYWQEAhi/EBw6nUt5bGP9a3AcOxNMf9nr1dFVOvUC67WCXvjtUpEqVAQ 5FCJT1fcO2uFRtnDCHBh5qEB5tJt1ch5bPPJx5s49cURAkObWBWlG+48Bjwx8AiZr4I8 cXOxcUTnhU+nHXT66GW34hu7InV1dcnT3q7gAMUcHl+LJfCxuupNSd4pOIxXqa1Bubn1 /LZbUXe7GaWhc0n7+Iu1DNgFUGIpSY5Z7LENLx9diPo21Kbk2YF9DAiTtmo7MPddytv/ 8awBVRttdVSKCpxefgwhxk1bxgffRezzlYNsm+0fvbdrNz3fIUGJoDKS+UrU9mQ7b/34 nUmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rAFQ7hKTntiFTKkEw/GOqW3HmIjaB2DpbwQSPaXZceA=; b=ydxy/UY8v1GlNvzFlmdw2U84pmQItVycZ9v1k6qf6w1QjNrhHj3JY7xO7uvo+65mFD n27VdAy3b+pIPYgKZCk63ombQNlLnZ7GTerj/H9AUoIUWyW90MhP3Z8p6uTkIiaFpI3V QFCT4H14FZFKiGwxZxXdRKDo4xwkdCNSRvmSGdqOzMMmHeSOLhWaG7aT/VJ+8oNE6q+F 978Ks0BBPwaFg6Vx6Hgggj3PC5bVE6CXOVLBY4vc6oIAFqhO2rlT4ckUNSrvqnOGMSkF l3B+uSwaYBUXuaHZw6J98ZoxU078BYJshazfJ2NqoqTybQhsuiZopvumRx9t8dVA+6L2 yHOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rA3o1yq5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k7si42582iok.65.2021.05.19.11.37.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:37:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rA3o1yq5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljR4N-0006lv-BQ for patch@linaro.org; Wed, 19 May 2021 14:37:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyL-0003eJ-B7 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:09 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]:45623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyH-0005dq-Lx for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:08 -0400 Received: by mail-oi1-x230.google.com with SMTP id w127so10158960oig.12 for ; Wed, 19 May 2021 11:31:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rAFQ7hKTntiFTKkEw/GOqW3HmIjaB2DpbwQSPaXZceA=; b=rA3o1yq5/2RJ6R0UY7v/2bL9sXmOfja+OvhAFCVOzntZ62rAWIVUPOr8ugOAV/bYb4 CeihgCcu1ldZFGdis4G24bhLy67valVMdVW8J1trE+Hg3aqtkcRxOg6mKnl9f2hRJda4 TCe0T2MUqLCsFBvMAtkNYCe3O6U/r05jocKhPuOJVUv3Xo9nSSZci2Yv7K1+i3pH9mOM 0BEJMC/FK4QE++KPAiO+VXXRyVG/UvRQ98PRO1qdsvpmqSOYC2f9pEbZvMVZe3a4/nJ1 5JYQufkrpllxyyQtd8osZCfnHBJ1Nxp1rTZmVmoMjSlADm2efS6PktY5ZIHH/M4bQPS5 4fjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rAFQ7hKTntiFTKkEw/GOqW3HmIjaB2DpbwQSPaXZceA=; b=Ntm5Mc+dwedxiiriiyvG2KG1TJX7iYN+3g02gcB7G67OKBvrjTV0yPemEZL643bC8w WWXcCp4q422HjrOd/dcEVBszO/H3EkoefvkxwCn640+vfJ6fvUcRN6Xp+Z2g5YQDxJCs 9ne9XhHALGihfuczjMR4kk4Gm0Wr02js6rH25obs4iSPiFJ64tsK6x4lbWEwwoNOySFv tEbv+5WJHvf1EGYgf0RHf1ZvQyuG6fY+gBLYJdBPig2br5C9HvU5AwdrVtwuTk6y9g27 95DhCbmRVf9zzARePE9PSv7oIfGJqKGp9Avz1adgac6LQzQ3dsAqqS5oKVi9IiOrYNzS 83ig== X-Gm-Message-State: AOAM533+mMDcEhREQjFp+HZkjgE/stT31XnwhBUAgsYxx2NORgPb1Q7B N30gd21zhFt0zcTs0qlclYjEcV3P1NZviwsP X-Received: by 2002:aca:1205:: with SMTP id 5mr545742ois.6.1621449064451; Wed, 19 May 2021 11:31:04 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/50] target/i386: Assert CODE64 for x86_64 user-only Date: Wed, 19 May 2021 13:30:12 -0500 Message-Id: <20210519183050.875453-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For x86_64 user-only, there is no way to leave 64-bit mode. Without x86_64, there is no way to enter 64-bit mode. There is an existing macro to aid with that; simply place it in the right place in the ifdef chain. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-13-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7b5031f647..e3907f9066 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -41,11 +41,9 @@ #define PREFIX_VEX 0x20 #ifdef TARGET_X86_64 -#define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) #else -#define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 #endif @@ -102,7 +100,6 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 int lma; /* long mode active */ - int code64; /* 64 bit code segment */ int rex_x, rex_b; #endif int vex_l; /* vex vector length */ @@ -165,6 +162,13 @@ typedef struct DisasContext { #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) #endif +#if !defined(TARGET_X86_64) +#define CODE64(S) false +#elif defined(CONFIG_USER_ONLY) +#define CODE64(S) true +#else +#define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0) +#endif static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); @@ -8497,6 +8501,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(IOPL(dc) == iopl); g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0)); g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); + g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; @@ -8518,7 +8523,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; #ifdef TARGET_X86_64 dc->lma = (flags >> HF_LMA_SHIFT) & 1; - dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); From patchwork Wed May 19 18:30:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442472 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1585552jac; Wed, 19 May 2021 11:39:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvl6BV01IzYKbBMp6Sx27/TqWF5GdVvUdEJ6F2eAj+bDt8U1AUm7EMgf1hWfMN+eVfwaOm X-Received: by 2002:a05:6e02:b4b:: with SMTP id f11mr418165ilu.253.1621449559162; Wed, 19 May 2021 11:39:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449559; cv=none; d=google.com; s=arc-20160816; b=q3ZFb/zp/q2hiFpVR3srf01NihZpoRtLvMdQeOrI2wqE/o/cGd0HXKIhyNLdjUQW6K hi5v8JmYzbxuqSJEhYTaXbbTTgX8P8qAu4yPdfE498yuPNpX7dfOAY2PMeiLHE6kGmNL aW4vGRroE7Z9VJxleb2Zm/JTyhQP14uu1qvgbCvd6XqPzH/Ik05DwisosYQIDEmo+Axo 8oLMK4JkuHjVROsAEE9zKnd4loJSBlb0xWa7qxKCEyR0qrzKVcg0jV+NAay98TJuf51a ZMNIURpCn6Lb/NMKO+dnTbAOx/efahIn1lybXdAZ57MV/p1nm/eJ0aUI/d7ZvW8CgnUF jfkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cmBZ6ICmQvawj9IO/C++c+UM9QVtAg4OWAJbtUAe9k8=; b=Arx+cFM3NGzbuWP1Q4EVN+bZijqM46jsyzca24aCKVEqFSwEoltPbtxUuYJ9OOONW4 Dpjek8BAGXTtHCo7QpD818DusCatDgUm68c+1kXNr9J17fzF2QCE3r3BRBOGQBImbYZY UD4QkqSeEKG7J/tgyk6TyrTTl086eUTBO5ib838YI2JKKdSapHggAlK3e+WZl+fsC0xP v/r2pMgvFrQmcHNwUQ5XXHgI3nrYTGuxpI0R9hIFkY6SyDbVX2Zbc2FMwNQLEFFWlDXC C4UB4GpFtXuLQ8cgiNwIl/7GN03f6lXWRklSqv10Jc+4ZGIftXkTANWO+DNHNjkidkmX rVMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L+1sVI6b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o8si412681ilu.133.2021.05.19.11.39.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:39:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L+1sVI6b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljR6E-00040M-Bj for patch@linaro.org; Wed, 19 May 2021 14:39:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyM-0003j2-Iw for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:10 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]:34732) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyI-0005eC-KE for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:10 -0400 Received: by mail-oi1-x22a.google.com with SMTP id u11so14004464oiv.1 for ; Wed, 19 May 2021 11:31:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cmBZ6ICmQvawj9IO/C++c+UM9QVtAg4OWAJbtUAe9k8=; b=L+1sVI6bibNADdd15+nCFyYwQYuzAaxH9KBeZg1HMgxrlwCYxFjYUyL9gNA7WAVlRV zOTpHi2HLooH6PxLf2BwKyTFYiojZ4rWzjw6d8ee3bnLM8NrsLZ5S/CBBDVtCPV+OzKJ lQkCZchaJtMwg8IW6DqUrmkQu9DteTwPtMq+pXTLoVcIlK0ldvKKD10OfycJG1JQisRb lRvCw9BPSAst5Q0Yvk8x0l257hgluT0sLzdh1yJaa4offxU+v92W8wvfCn3FIovvLJn/ UQo1TStSX1ji6ffLKijF7q9xbqy7MR6+qIzxcnJJrhRWAbrT3G0sbiZ0tqOEunq92Xab 4rkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cmBZ6ICmQvawj9IO/C++c+UM9QVtAg4OWAJbtUAe9k8=; b=jNZ7choab6KdCirP7wsYl6IgICFdlBLYegiMjm7E4BEBTNAEK/I8Y72pKOYS27/lBf LLy+q3KTcotHbvsgxRqoIauRmHxYvCocfPLP8rqeJE/vvywt3NK1qlG/NWZHse0hmRAk OFCiEQUo+Jrq1+0xVFmio5BBd9aCIvTbXfXqo/kYfBxhBQeRiIWsP83Z3xws0Jve0lAC SUgFdmXj1f5RQEZOH0f0Ev8hl9hAtamLSLZEE9DqCNI3sL1u+ew+t2osCttwAQELQLg0 UohSwijVIekavGZ1UG+JQtmtX3Dsw3j5oy7OGIH9l57kDI4xL0TluuYDfWlzH7IU7GuY ox4Q== X-Gm-Message-State: AOAM531F9B8+43ARLhmxMEkkNExBw7X9UK4YQ8pAP7Z7dOlP8G7PUifJ l855SF8lQpPdfn51Afbqq18gOsffd2g7aYWz X-Received: by 2002:a05:6808:f07:: with SMTP id m7mr423242oiw.98.1621449065388; Wed, 19 May 2021 11:31:05 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/50] target/i386: Assert LMA for x86_64 user-only Date: Wed, 19 May 2021 13:30:13 -0500 Message-Id: <20210519183050.875453-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" LMA is a pre-requisite for CODE64, so there is no way to disable it for x86_64-linux-user, and there is no way to enable it for i386. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-14-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e3907f9066..9c8a405694 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -99,7 +99,6 @@ typedef struct DisasContext { #endif #ifdef TARGET_X86_64 - int lma; /* long mode active */ int rex_x, rex_b; #endif int vex_l; /* vex vector length */ @@ -164,10 +163,13 @@ typedef struct DisasContext { #endif #if !defined(TARGET_X86_64) #define CODE64(S) false +#define LMA(S) false #elif defined(CONFIG_USER_ONLY) #define CODE64(S) true +#define LMA(S) true #else #define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0) +#define LMA(S) (((S)->flags & HF_LMA_MASK) != 0) #endif static void gen_eob(DisasContext *s); @@ -7295,7 +7297,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } else { gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); /* condition codes are modified only in long mode */ - if (s->lma) { + if (LMA(s)) { set_cc_op(s, CC_OP_EFLAGS); } /* TF handling for the sysret insn is different. The TF bit is @@ -8503,6 +8505,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(CODE32(dc) == ((flags & HF_CS32_MASK) != 0)); g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); + g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; @@ -8521,9 +8524,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; -#ifdef TARGET_X86_64 - dc->lma = (flags >> HF_LMA_SHIFT) & 1; -#endif dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because From patchwork Wed May 19 18:30:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442468 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1584129jac; Wed, 19 May 2021 11:37:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyOw1l9h+SowI1Oyk5P3EML2T1j2GH0AB87y/eEJ+1DZDJ3OZoKNHJheRMj7zCC7k4S28SD X-Received: by 2002:a02:7f57:: with SMTP id r84mr429319jac.108.1621449443291; Wed, 19 May 2021 11:37:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449443; cv=none; d=google.com; s=arc-20160816; b=RC5axpFwPnAuNVsq90TiAAh/oYrTyjEVtUGRxP6JuNxeXTnaOFNs9n82V+v+hWzIPB Tq7SeH8aLu4o9G1vW51spEHxc6AJYQ3RSw7R0ullXCr0aNimGnXTexYZyheed797K6mz SmsWlH4RAQefMxncLdr7t5XbyOKjqYipE54pxNMxC0ydm6K92cDTve1eJKYm7Kwayjn8 R9fZpuuCGiP3fufzyu5IBxSnQTgr6rhco+RvGwcqHcT7JXnTPR/PO1Mm7I2Co9D33mGZ I5qKcfIzDm1tGQ1CmrYBSab1HBpzqKol6RKOyZ0d5pi6Q00dXS2ufjlHtn15UibPIJ1R 9PuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=agd4oaV5WPqctmWjrwQb1Gp+h1P4jf2oyWzZFVAY35U=; b=e3KQWqR8XwrD20+lSnfMEZegXHIcsLy8ugpbMEPENJiVaB0U5ztM7Ozq+khPnTe7Kx DgmQR4+dJ3YvSzidPkZ9ZLM100qBt5fLDdoNcSLGChmHlWhj6nvruOwUIP693sjAfxpi LHa18dSEzn8s+Er/nQE2gt6cuvKGaOmkJz5njQgGBrGqiWJPPA4GvpjIhSU3+FLgW4bE ImEbMr4sDqZltrbT+BkWSfbMlSGGynDFcQIpK7IW1uFgOEBO5i+q+nBTURqYT3IPwmz8 xRB2WlCAObjl9bC8vydhgiPLvBqWJs/nngMgHHx8tOrNf8ZAe2uITeBz2fVwsYmVnSFc y13A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tAnjAD3a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This means that ADDSEG is off. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-15-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9c8a405694..7d7ab3e03d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -108,7 +108,6 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 bool x86_64_hregs; #endif - int addseg; /* non zero if either DS/ES/SS have a non zero base */ int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ @@ -156,10 +155,12 @@ typedef struct DisasContext { #define VM86(S) false #define CODE32(S) true #define SS32(S) true +#define ADDSEG(S) false #else #define VM86(S) (((S)->flags & HF_VM_MASK) != 0) #define CODE32(S) (((S)->flags & HF_CS32_MASK) != 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) != 0) +#define ADDSEG(S) (((S)->flags & HF_ADDSEG_MASK) != 0) #endif #if !defined(TARGET_X86_64) #define CODE64(S) false @@ -492,7 +493,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, #endif case MO_32: /* 32 bit address */ - if (ovr_seg < 0 && s->addseg) { + if (ovr_seg < 0 && ADDSEG(s)) { ovr_seg = def_seg; } if (ovr_seg < 0) { @@ -505,7 +506,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, tcg_gen_ext16u_tl(s->A0, a0); a0 = s->A0; if (ovr_seg < 0) { - if (s->addseg) { + if (ADDSEG(s)) { ovr_seg = def_seg; } else { return; @@ -2429,7 +2430,7 @@ static void gen_push_v(DisasContext *s, TCGv val) tcg_gen_subi_tl(s->A0, cpu_regs[R_ESP], size); if (!CODE64(s)) { - if (s->addseg) { + if (ADDSEG(s)) { new_esp = s->tmp4; tcg_gen_mov_tl(new_esp, s->A0); } @@ -8506,8 +8507,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(CODE64(dc) == ((flags & HF_CS64_MASK) != 0)); g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); + g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; From patchwork Wed May 19 18:30:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442489 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1594017jac; Wed, 19 May 2021 11:51:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9mG97v7t6t4UzwCNdM71EtI7u9mEt/47QNBDhOpyAh2mqrFK764K0x7sO5FKnizJMHUMb X-Received: by 2002:a6b:d918:: with SMTP id r24mr964157ioc.25.1621450314564; Wed, 19 May 2021 11:51:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450314; cv=none; d=google.com; s=arc-20160816; b=L0gWTNQkJxBEyd8VGUKWCjGaSRWTNvrRbZAlFA9i88G3Dexe9zXm0AmwxEdNTATI+O yy3Nbl4+8tuSnUbJmTigEuCtHvHIk9qstSrdlFFOcoqNahT7pDdg6pVwRsiOT+rODrjm t9KPISScQ3isTavjB7duf3h3Gr5V/LBPKbmo+8jIj+kuvCLyfbfgUYCFi+UZG1gbPQB0 Ftm2Tk0DNJ4TBLw9lxDkjGEdcAykrjxknB3gPW0tZXWo3MEQcMkqmIP8P3yaxEffd1zZ s6SjtdGSwvuL9ZZPKcZROrC7DaGgEHGVh6636jlVBG6jF+5KWCHY4UdG38FngzoIsDNk S4gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=apFSgGZXwWAqwxDJM0bgwOp5DD1DSEWrQeh+D0YbI6s=; b=NgbM+8b8K3fSDzQHQ3OSOantwNhd3w0RmqHIst8ToiSqhcTxQh3mpQjJd3e+glFgzj P5HWgI4RKh06LBbIs+9AD1ETzdvHyGjEZt2odMapa1kjxnVGi1uAEOKi2WGUMiiPUZtD wQIVB5avk0IKyWgjC7ylDNSOOSxsoxkj3vHQz8LfLy0EUwMuJK4lxv/r0rgcNNLz6ta2 j0iTQRzYh6Y6jwyQatY1YUSFdewWN9G2bGs1YTKoreGO3/LcDD9IzYjLR7sqifYJexSk BeDYwt+T5MfdHJtf/2JnNsvbzX4XWyt6gvFynIUdYcypuCVJYymoeSxdlGUz66fPD5p9 mHdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XUD75oIU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n6si148683jal.41.2021.05.19.11.51.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:51:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XUD75oIU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRIP-00029C-TK for patch@linaro.org; Wed, 19 May 2021 14:51:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyX-0003t1-La for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:22 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]:36633) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyK-0005fW-RR for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:19 -0400 Received: by mail-oi1-x22a.google.com with SMTP id f184so14009037oig.3 for ; Wed, 19 May 2021 11:31:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=apFSgGZXwWAqwxDJM0bgwOp5DD1DSEWrQeh+D0YbI6s=; b=XUD75oIUwLikKs7mPxU5geugEFyJXbhCRG4mrjPSG9hhdDPVPVvLsw8YrFcihP9RnS 4TGEtXkRuTpUvW3FOF4REZjFM3vdT2ldZa9eksjbGwy+GFBooxfKCyya75ABCSsJu27Y T1+R7fpc/J6AU+v7JM33I121YAOm8tae4YGVgW1rCjGeIV4ZRLdohPibYwXmyfb90CSi TJ827Zq30owTrNLkBhPrFpS9Fo5E3mM6ozwVPMQIyghGFJxro698nkyHHzWnsKV4zH4Y p2m7VPSVQX581kPbQBpPooLwPwmvyqOzaJx9cyGuRcVzjASob+wEgtXvmQbE7AEXvuhv /Kkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=apFSgGZXwWAqwxDJM0bgwOp5DD1DSEWrQeh+D0YbI6s=; b=gNkDkCTIrwwEXYMdeqQMaLkyj5u1kBHM2SBj9mLeWe6yQaiDV/frOrvpr94bX0O0oR 1lObqGiaKVvKTuYZOdOClLAwic0Q3/gHEZdxffBAJE0n1QOK5gYrYMzu2Hl4jfPHT5hq ii1F/yavLNUeIwxVRXv7VMMl+alvBp79hwS4cCJvHaGSgkGZzcwn/wM/siueGY7kg/wm QgDtFdb8knABHKdeRDfv1HZVBPk8RQoyS/JRK0X0qUGyxCQ1qsLYN1uKCRqZhB6ANjZx mCe2Oi1d0ZJFJdtyH10gRS1qiyGBamPVjn8NoNJudTTuzmuRqalgXsfykFo+z83G138/ 50EA== X-Gm-Message-State: AOAM530qQD+qW1Bg+jprOJDef/Ie1A5G64z8yvNSvs6D0ySwiExzPXTD eJBvrFR+SgmBXgMSzM8ckU6GQnoGzP6kjSid X-Received: by 2002:a05:6808:13c9:: with SMTP id d9mr537097oiw.142.1621449067292; Wed, 19 May 2021 11:31:07 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/50] target/i386: Introduce REX_PREFIX Date: Wed, 19 May 2021 13:30:15 -0500 Message-Id: <20210519183050.875453-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The existing flag, x86_64_hregs, does not accurately describe its setting. It is true if and only if a REX prefix has been seen. Yes, that affects the "h" regs, but that's secondary. Add PREFIX_REX and include this bit in s->prefix. Add REX_PREFIX so that the check folds away when x86_64 is compiled out. Fold away the reg >= 8 check, because bit 3 of the register number comes from the REX prefix in the first place. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-16-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7d7ab3e03d..79a37fb1a7 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -39,6 +39,7 @@ #define PREFIX_DATA 0x08 #define PREFIX_ADR 0x10 #define PREFIX_VEX 0x20 +#define PREFIX_REX 0x40 #ifdef TARGET_X86_64 #define REX_X(s) ((s)->rex_x) @@ -105,9 +106,6 @@ typedef struct DisasContext { int vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; -#ifdef TARGET_X86_64 - bool x86_64_hregs; -#endif int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ @@ -173,6 +171,12 @@ typedef struct DisasContext { #define LMA(S) (((S)->flags & HF_LMA_MASK) != 0) #endif +#ifdef TARGET_X86_64 +#define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#else +#define REX_PREFIX(S) false +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -336,14 +340,10 @@ static void gen_update_cc_op(DisasContext *s) */ static inline bool byte_reg_is_xH(DisasContext *s, int reg) { - if (reg < 4) { + /* Any time the REX prefix is present, byte registers are uniform */ + if (reg < 4 || REX_PREFIX(s)) { return false; } -#ifdef TARGET_X86_64 - if (reg >= 8 || s->x86_64_hregs) { - return false; - } -#endif return true; } @@ -4559,7 +4559,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #ifdef TARGET_X86_64 s->rex_x = 0; s->rex_b = 0; - s->x86_64_hregs = false; #endif s->rip_offset = 0; /* for relative ip address */ s->vex_l = 0; @@ -4614,12 +4613,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x40 ... 0x4f: if (CODE64(s)) { /* REX prefix */ + prefixes |= PREFIX_REX; rex_w = (b >> 3) & 1; rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; REX_B(s) = (b & 0x1) << 3; - /* select uniform byte register addressing */ - s->x86_64_hregs = true; goto next_byte; } break; @@ -4643,14 +4641,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ - | PREFIX_LOCK | PREFIX_DATA)) { + | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { goto illegal_op; } -#ifdef TARGET_X86_64 - if (s->x86_64_hregs) { - goto illegal_op; - } -#endif rex_r = (~vex2 >> 4) & 8; if (b == 0xc5) { /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ From patchwork Wed May 19 18:30:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442478 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1588329jac; Wed, 19 May 2021 11:43:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwM+Mz+2PGl5XAzh0SeK5wx/ODvl8zk0JRQNEbyeTCnoZDt5WCE1kcqoW2dwOUHeh2iBSxe X-Received: by 2002:a05:6e02:58a:: with SMTP id c10mr497691ils.216.1621449810433; Wed, 19 May 2021 11:43:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449810; cv=none; d=google.com; s=arc-20160816; b=A5LbuPJJJl4Djz/UtiE7sxlVvAfdmGhehOlj8R7TmdUR6oDA51Mh4ogxWEtwm+C5tW q7TgaySmulwaA4M+jD75tCpRnhmXLtezdPOF7MvTDJAl8A5t/+ebgjjnZHlPzWt63TBB eZBoz0aVzhJjhLtnjV58kedk53ZhyMo5VKXik7C/aadDo8VDf+EI+LO6xwTBZFrePc3F /nviVIPoRgtS3oCE19GozypvEJChnLtFpPdFA3LKhXArBmd7jetQ5KJGV7sYmRQk55Sr XIK0QWHXWX/1ywudbnq4TjRr4AgnAysSLUEsl76FIaQrIOJA8EIOYRN7/e5AXm2C/KYY SUsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=apQ7cUSEoG7Sw4F7rOAU3FhzYTNsiwzo7lp42fC1tSs=; b=hpnBJkMR8EOGyuXVHDtoL3/uRkflUNIHJa833xzt0QmPKqywcYpWZeXe3SWNrHDUEr Ym0acJW+0m1+rD0IfpWxNsVeN9xu8RQH5lbFfXJ4EVfYEL6jjq+czdBap507xIjYRwwP JdwDtmRQal0brrwj6N4tpzA5jqYAjeJIs8h9oLG4B94M1nBa7HTp/tV5aDVdAJscYbuS 5y1lu/wVoVUMqpV5/3jpyPey0edOt4faP2QIe7SqnlYvbVKzWlv0+Fivzxi+Bm+Hm0Ac 0DiLfAQimekrZt9lMiVMFhCxpCKMKJ9tGiua8TNIW5zX3m9RAZOMWU08reKkL/W56RyH SSjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i0hb+ltz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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For x86_64 add 0 in the macros to (1) promote the type back to int, and (2) make the macro an rvalue. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-17-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 79a37fb1a7..9bb37215d8 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -41,14 +41,6 @@ #define PREFIX_VEX 0x20 #define PREFIX_REX 0x40 -#ifdef TARGET_X86_64 -#define REX_X(s) ((s)->rex_x) -#define REX_B(s) ((s)->rex_b) -#else -#define REX_X(s) 0 -#define REX_B(s) 0 -#endif - #ifdef TARGET_X86_64 # define ctztl ctz64 # define clztl clz64 @@ -100,7 +92,8 @@ typedef struct DisasContext { #endif #ifdef TARGET_X86_64 - int rex_x, rex_b; + uint8_t rex_x; + uint8_t rex_b; #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ @@ -173,8 +166,12 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#define REX_X(S) ((S)->rex_x + 0) +#define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_X(S) 0 +#define REX_B(S) 0 #endif static void gen_eob(DisasContext *s); @@ -4617,7 +4614,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) rex_w = (b >> 3) & 1; rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; - REX_B(s) = (b & 0x1) << 3; + s->rex_b = (b & 0x1) << 3; goto next_byte; } break; From patchwork Wed May 19 18:30:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442484 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1591918jac; Wed, 19 May 2021 11:48:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqwrNY40c1DWko8cqzc8y2vpnb4tLrIaBgp6n4xa61xQHwGsiDT/clbbLrJvTrZu763i/r X-Received: by 2002:a5b:307:: with SMTP id j7mr1230636ybp.481.1621450124335; Wed, 19 May 2021 11:48:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450124; cv=none; d=google.com; s=arc-20160816; b=U6rXYcEq7kDmV2x1dhTj7TIvtIOV7JVnucSRgdNx/LjqmXmbrsZw55gPiT+K9GxHJj vL6U8SICNHs4zPEQ7yiJk3z7A1RDbhTkTbB5bxnW2KK7oRoWcqaoxkKAsUFcl7E5/8L6 /9EZFeZ3bdeNjGJestbPsHSOPRfIIp8wcChxBuqb5bEIrWI/ZL8+uLfqRjSO26stam/Q BUUAUKDrWTzaoftmxjOmgW4iOIlhK0wQlR5vNd+M6ADI7a7BC+G7S6kBo4X4KJEByO56 vOTSwavuugpx6914bwdPMcBazswIpfrnZr9s8qMZK7EmUc43LoRu+GMXyytenPaZkA35 UNEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D9u+l/BiRLEGpZtusr2xgK4721hFuj8PaGpObGhRGRs=; b=QKb12wbVWA7nS8fyDya0/B60PWb8cx0pJdfW/DAyQ1vALZtLJAttdHeCNgHVawbA96 lZKEpK1yUkCm3WwLqycXltGvawwmV2ETNBMXn3q5xWO1c4ODUsL0X9GRX6qtE103kMM6 Oh6g4hpvGX9ENHKI3pQqUWM4nL5DYpPaUon57MICU7vL2GouVdqH1xAANSeSnzuqWcMC l0HXwgKTO/dmAgnXk8tlZo6GI4BI1msFa472YL1NhenPbObeF1tBAL1nHrMc9e877VlS Qj9gWgnSPGh7iIW0z6Bcw715YCClrBaI5G7n4BfnaKDFnHvAfqvov4ok7shXxq5n9lan UGbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DTsk7dMA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-18-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 84 ++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 39 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9bb37215d8..22175c6628 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -92,6 +92,7 @@ typedef struct DisasContext { #endif #ifdef TARGET_X86_64 + uint8_t rex_r; uint8_t rex_x; uint8_t rex_b; #endif @@ -166,10 +167,12 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#define REX_R(S) ((S)->rex_r + 0) #define REX_X(S) ((S)->rex_x + 0) #define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_R(S) 0 #define REX_X(S) 0 #define REX_B(S) 0 #endif @@ -3094,7 +3097,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { }; static void gen_sse(CPUX86State *env, DisasContext *s, int b, - target_ulong pc_start, int rex_r) + target_ulong pc_start) { int b1, op1_offset, op2_offset, is_xmm, val; int modrm, mod, rm, reg; @@ -3164,8 +3167,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, modrm = x86_ldub_code(env, s); reg = ((modrm >> 3) & 7); - if (is_xmm) - reg |= rex_r; + if (is_xmm) { + reg |= REX_R(s); + } mod = (modrm >> 6) & 3; if (sse_fn_epp == SSE_SPECIAL) { b |= (b1 << 8); @@ -3699,7 +3703,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_ld16u_tl(s->T0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); } - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_op_mov_reg_v(s, ot, reg, s->T0); break; case 0x1d6: /* movq ea, xmm */ @@ -3743,7 +3747,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, fpregs[rm].mmx)); gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, s->ptr0); } - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp2_i32); break; @@ -3755,7 +3759,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } modrm = x86_ldub_code(env, s); rm = modrm & 7; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (b1 >= 2) { goto unknown_op; @@ -3831,7 +3835,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Various integer extensions at 0f 38 f[0-f]. */ b = modrm | (b1 << 8); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); switch (b) { case 0x3f0: /* crc32 Gd,Eb */ @@ -4185,7 +4189,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, b = modrm; modrm = x86_ldub_code(env, s); rm = modrm & 7; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (b1 >= 2) { goto unknown_op; @@ -4205,7 +4209,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = (modrm & 7) | REX_B(s); if (mod != 3) gen_lea_modrm(env, s, modrm); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); val = x86_ldub_code(env, s); switch (b) { case 0x14: /* pextrb */ @@ -4374,7 +4378,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* Various integer extensions at 0f 3a f[0-f]. */ b = modrm | (b1 << 8); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); switch (b) { case 0x3f0: /* rorx Gy,Ey, Ib */ @@ -4548,12 +4552,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - int rex_w, rex_r; + int rex_w; target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; s->override = -1; #ifdef TARGET_X86_64 + s->rex_r = 0; s->rex_x = 0; s->rex_b = 0; #endif @@ -4567,7 +4572,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) prefixes = 0; rex_w = -1; - rex_r = 0; next_byte: b = x86_ldub_code(env, s); @@ -4612,7 +4616,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* REX prefix */ prefixes |= PREFIX_REX; rex_w = (b >> 3) & 1; - rex_r = (b & 0x4) << 1; + s->rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; s->rex_b = (b & 0x1) << 3; goto next_byte; @@ -4641,7 +4645,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { goto illegal_op; } - rex_r = (~vex2 >> 4) & 8; +#ifdef TARGET_X86_64 + s->rex_r = (~vex2 >> 4) & 8; +#endif if (b == 0xc5) { /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ vex3 = vex2; @@ -4731,7 +4737,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) switch(f) { case 0: /* OP Ev, Gv */ modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); if (mod != 3) { @@ -4753,7 +4759,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 1: /* OP Gv, Ev */ modrm = x86_ldub_code(env, s); mod = (modrm >> 6) & 3; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); rm = (modrm & 7) | REX_B(s); if (mod != 3) { gen_lea_modrm(env, s, modrm); @@ -5179,7 +5185,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_v_reg(s, ot, s->T1, reg); @@ -5251,7 +5257,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6b: ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (b == 0x69) s->rip_offset = insn_const_size(ot); else if (b == 0x6b) @@ -5303,7 +5309,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1c1: /* xadd Ev, Gv */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; gen_op_mov_v_reg(s, ot, s->T0, reg); if (mod == 3) { @@ -5335,7 +5341,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; oldv = tcg_temp_new(); newv = tcg_temp_new(); @@ -5557,7 +5563,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x89: /* mov Gv, Ev */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); @@ -5583,7 +5589,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x8b: /* mov Ev, Gv */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_reg_v(s, ot, reg, s->T0); @@ -5633,7 +5639,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) s_ot = b & 8 ? MO_SIGN | ot : ot; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); @@ -5672,7 +5678,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); { AddressParts a = gen_lea_modrm_0(env, s, modrm); TCGv ea = gen_lea_modrm_1(s, a); @@ -5754,7 +5760,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x87: /* xchg Ev, Gv */ ot = mo_b_d(b, dflag); modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (mod == 3) { rm = (modrm & 7) | REX_B(s); @@ -5791,7 +5797,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) do_lxx: ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; @@ -5874,7 +5880,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (mod != 3) { gen_lea_modrm(env, s, modrm); opreg = OR_TMP0; @@ -6728,7 +6734,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_cmovcc1(env, s, ot, b, modrm, reg); break; @@ -6874,7 +6880,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) do_btx: ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); gen_op_mov_v_reg(s, MO_32, s->T1, reg); @@ -6979,7 +6985,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1bd: /* bsr / lzcnt */ ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_extu(ot, s->T0); @@ -7706,7 +7712,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) d_ot = dflag; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); @@ -7780,7 +7786,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; ot = dflag != MO_16 ? MO_32 : MO_16; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); t0 = tcg_temp_local_new(); gen_update_cc_op(s); @@ -7821,7 +7827,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod = (modrm >> 6) & 3; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (prefixes & PREFIX_REPZ) { /* bndcl */ if (reg >= 4 @@ -7911,7 +7917,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod = (modrm >> 6) & 3; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (mod != 3 && (prefixes & PREFIX_REPZ)) { /* bndmk */ if (reg >= 4 @@ -8023,7 +8029,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) * are assumed to be 1's, regardless of actual values. */ rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot = MO_64; else @@ -8076,7 +8082,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) * are assumed to be 1's, regardless of actual values. */ rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot = MO_64; else @@ -8118,7 +8124,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); break; @@ -8350,7 +8356,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; modrm = x86_ldub_code(env, s); - reg = ((modrm >> 3) & 7) | rex_r; + reg = ((modrm >> 3) & 7) | REX_R(s); if (s->prefix & PREFIX_DATA) { ot = MO_16; @@ -8378,7 +8384,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1c2: case 0x1c4 ... 0x1c6: case 0x1d0 ... 0x1fe: - gen_sse(env, s, b, pc_start, rex_r); + gen_sse(env, s, b, pc_start); break; default: goto unknown_op; From patchwork Wed May 19 18:30:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442481 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1590528jac; Wed, 19 May 2021 11:46:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjjG+F3UEIOK+Cn3baKXGgAPa1HRjc8llbSxz3TYfh2sqAzoqk5BDzdhAIiT1eceN5F57+ X-Received: by 2002:a25:add3:: with SMTP id d19mr1431293ybe.101.1621450000802; Wed, 19 May 2021 11:46:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450000; cv=none; d=google.com; s=arc-20160816; b=ym+/kDmrgMk/jy+vDIqY7xvO9jiUgCCYha0/BCXUxgMQA7DX2FlTsm3WgpftCTtyvn myKb1Sxg7CcVF83fuBg2RXewlLtCv6W/XDMVtvOEPFiwigyGfl25FBzZO6faLbT3U+8P pv/ub9NsGcBdxFnYihhZcmbIT79dTU34y9UWL8H9TRNcEPl2hxRE9he4YA1kWhKsT/82 2C00zdMueCKrJUel2tw+Oc51TgXidT15dWgk6oKN8AsQxKfrjqoY2pqbxgv/ofaVfrhu 0Pdknh1X329OORcRvbkf1lHnPmAT4V8wOGOcxZnddxEhW2XbdnZ8mHXCqqI1GfsNZ80f uOEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X/FFxNAJ2f0+Zc5rdCpNj+t2LEQqtzj2zkGTB7lInGQ=; b=zaq3v5eLm9ntLv11AJ6i7FhDoEDYKjSqC3e/vOpkGqoBhNoabY/UvGgyV3lU7OaCHb MoxvgiEfdFjOBBYhcA2cWmGT/8IsSBf/RBBsWo+5zfB+fj3TeP5iuQJ8whfKdEyhZKwo PHis9BNCz0JnPOiTms1vU8auTL8pOXCg1n8H8LdcOfwQJmwNHj/lrLn/UytWWJhgXJDm Py6JrQ1jSped/veVpjqi0Q3abGRfHfV/fJ9SVLLg1PB+4QcrYen/aKoUB0Mx4+HYONZS RF8x2uJAgkc6eTq7LOB1DnG17s02lhGM11WCeQMXAMHYsUXBqXwPFHqoNgUBm/KZzNtN NnsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dSPI+1oS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f187si203516ybb.190.2021.05.19.11.46.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:46:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dSPI+1oS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRDM-0007IP-1X for patch@linaro.org; Wed, 19 May 2021 14:46:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51332) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyV-0003r6-4F for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:19 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]:36636) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyN-0005hg-Dh for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:16 -0400 Received: by mail-oi1-x22c.google.com with SMTP id f184so14009212oig.3 for ; Wed, 19 May 2021 11:31:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X/FFxNAJ2f0+Zc5rdCpNj+t2LEQqtzj2zkGTB7lInGQ=; b=dSPI+1oSgj7IlmfppGBOHSg8/2hCMFtI7ZO3ADTS2WGtaPsKVmlQOEtdEdyosMy1VZ IJajYazkvPbWiC731TGhxDhwXLaMe7kdePfkwTotvqcZB+kh8kGHSYx3enbThH4nE7QH MAibZYFx/0M2NagoCarmXyQGpDWrnIZ7xdSr1iqGBj3KpNoT4JBAaOcq5ynw58Ny205D sYg3PQtyzw8iPKVFyFvPDdhenxP0zL6Tuv4eYEuxj2mjhQcbV/EWuarBXHHMj09F16tw olBQYxdupT/q3b98sMLxbVrC3q+F8EQubO+tRdBzwWR2VnTEAkLQY3EQL3YCYQfcNxB3 P65Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X/FFxNAJ2f0+Zc5rdCpNj+t2LEQqtzj2zkGTB7lInGQ=; b=UvLwj89H3YOf7WoxJwa4BjVjtYHAaSDHr+TS9RNZD1EzHS/7AjmRxVByC7+FfKYV9P /zFisVQBVvs8beBB0JlCf49d0QhYV6B9oUwrAUSOQzuDjGh19FNHJ6/9VEAh6TDSZNMA eTmVhw0BghLK1ehuev1lJB4n1300ViThDwzqgauGQI4EOA/ORKRzQoygc/pV/W1ON1x5 5R5LnY3PDtX/5YNigwvOEadSGZUeGyqmfN9p0VYk9CjCRsmqe+KRw4zLiR12+enbhzLH z0BQ+Xc4f2GI6+gu3LpGeeHEBHWr+iLqgcPRpBt6iMk9CL6xsMsnIKCgL26N/wpGhDsm wNew== X-Gm-Message-State: AOAM532Bzpv669cl8peyDybLxN59/nW88cpsMHIVzQ4Wa92lJ26yu4H0 QK/QSsk0IDjRyvjvkbwAb3BUOfvzDmeM7+Um X-Received: by 2002:aca:44d4:: with SMTP id r203mr514041oia.76.1621449070311; Wed, 19 May 2021 11:31:10 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 18/50] target/i386: Move rex_w into DisasContext Date: Wed, 19 May 2021 13:30:18 -0500 Message-Id: <20210519183050.875453-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Treat this flag exactly like we treat the other rex bits. The -1 initialization is unused; the two tests are > 0 and == 1, so the value can be reduced to a bool. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-19-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 22175c6628..4222f09b6f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -95,6 +95,7 @@ typedef struct DisasContext { uint8_t rex_r; uint8_t rex_x; uint8_t rex_b; + bool rex_w; #endif int vex_l; /* vex vector length */ int vex_v; /* vex vvvv register, without 1's complement. */ @@ -167,11 +168,13 @@ typedef struct DisasContext { #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0) +#define REX_W(S) ((S)->rex_w) #define REX_R(S) ((S)->rex_r + 0) #define REX_X(S) ((S)->rex_x + 0) #define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_W(S) false #define REX_R(S) 0 #define REX_X(S) 0 #define REX_B(S) 0 @@ -4552,12 +4555,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - int rex_w; target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; s->override = -1; #ifdef TARGET_X86_64 + s->rex_w = false; s->rex_r = 0; s->rex_x = 0; s->rex_b = 0; @@ -4571,7 +4574,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } prefixes = 0; - rex_w = -1; next_byte: b = x86_ldub_code(env, s); @@ -4615,7 +4617,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s)) { /* REX prefix */ prefixes |= PREFIX_REX; - rex_w = (b >> 3) & 1; + s->rex_w = (b >> 3) & 1; s->rex_r = (b & 0x4) << 1; s->rex_x = (b & 0x2) << 2; s->rex_b = (b & 0x1) << 3; @@ -4654,12 +4656,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) b = x86_ldub_code(env, s) | 0x100; } else { /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */ + vex3 = x86_ldub_code(env, s); #ifdef TARGET_X86_64 s->rex_x = (~vex2 >> 3) & 8; s->rex_b = (~vex2 >> 2) & 8; + s->rex_w = (vex3 >> 7) & 1; #endif - vex3 = x86_ldub_code(env, s); - rex_w = (vex3 >> 7) & 1; switch (vex2 & 0x1f) { case 0x01: /* Implied 0f leading opcode bytes. */ b = x86_ldub_code(env, s) | 0x100; @@ -4686,7 +4688,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* In 64-bit mode, the default data size is 32-bit. Select 64-bit data with rex_w, and 16-bit data with 0x66; rex_w takes precedence over 0x66 if both are present. */ - dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32); + dflag = (REX_W(s) ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32); /* In 64-bit mode, 0x67 selects 32-bit addressing. */ aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64); } else { @@ -5082,7 +5084,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* operand size for jumps is 64 bit */ ot = MO_64; } else if (op == 3 || op == 5) { - ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16; + ot = dflag != MO_16 ? MO_32 + REX_W(s) : MO_16; } else if (op == 6) { /* default push size is 64 bit */ ot = mo_pushpop(s, dflag); From patchwork Wed May 19 18:30:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442479 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1588383jac; Wed, 19 May 2021 11:43:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxp4/TSvvFDaHCmv1NsdEEg11HWOqBaawT1vfthoDkDkCUbZKedlExWVh/AWhkSIYyGB7d5 X-Received: by 2002:a02:91c1:: with SMTP id s1mr419751jag.61.1621449814685; Wed, 19 May 2021 11:43:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449814; cv=none; d=google.com; s=arc-20160816; b=KkhAMx684gNYjegvkDB8igkE+6TJ+fye6akgr7clOdfkf69CAPfBoF/q+kapb7C2TV C+wEJM3DfpclEkcyRM63ax+BQSc70WSBdGTUs6DggUOUUUSfnjIgrIKD6Lah8mjg0Qop 6pP6Q9jKMTOCD4OLVqjriwfuPWHoXdl/r6EWAkzyQXw2voyVNt0eu93PcfK3YP6EfV5G 5hkQsfSQ9gCYI0ku5vJeThvfSFs2Gbq+6Ztvb5MEgQuePG/9nloTq3kRMFoGgFNPpA4B Kkb4HL75r56uN/yJ2PgFgmJr6kH7O0jXjyBpaMcQ0dHwYNCWD7qfdMj+zCHORgL5sypp 5gVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Fn0fKM7b0/WeEivTWmPBKTYTf/IZtNjtnp7j7fWEKko=; b=U+X48JlqqzZIO/VWe3NF/GzoQVI02R3/Elea/EDDzvbQOTEEngEohLhZMArdH85GoR sg1QS7Dok/AzfAcSBVkDwhUCG1HpOjF97ZviPFrNdh5WPY1b2RgQnqK9yDkG68lfdiEH JMn3xrxD8wloXpUXER0xK90pBgEpaPxx8HiWZJUWn755W4WBNd5zSZm1L/ILAIs3n2u1 vavujrm1ZI4xN8MaVdxCqKUtZZUFGd4qzqvgeoUIkwOBG7yj9TLcV9IbOzBsotkw5TXw XlbRfqInXZWq/zsJLUtpbB25xiZBuw/K7OSsRIh8WVLKGEz0Me864QjVojqo/npqHvEx uObQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMVQAn+d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-20-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 2 -- 1 file changed, 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4222f09b6f..7e296b39f5 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,7 +101,6 @@ typedef struct DisasContext { int vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -8507,7 +8506,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Wed May 19 18:30:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442473 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1585561jac; Wed, 19 May 2021 11:39:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfT7fdomUPwfuo/AfNT3Dr6DQma20N6jXvHgVEoUVbsoTNRkOUY4WQC+4AgX+BzNtFBwMO X-Received: by 2002:a02:9443:: with SMTP id a61mr422653jai.60.1621449560119; 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-21-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e296b39f5..ca7f0a8cf4 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -105,7 +105,7 @@ typedef struct DisasContext { int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ - uint64_t flags; /* all execution flags */ + uint32_t flags; /* all execution flags */ int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; From patchwork Wed May 19 18:30:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442494 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1595197jac; Wed, 19 May 2021 11:53:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2UjMsrNvH6scoxY5EWEwgQqLrco/l35FlJ7v+8JPU1br+clLUuDrlQ9XDN5qjt5LsgxXQ X-Received: by 2002:a05:6e02:ca5:: with SMTP id 5mr506362ilg.207.1621450420273; Wed, 19 May 2021 11:53:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450420; cv=none; d=google.com; s=arc-20160816; b=uSveaokJq/4HRQ/xg7wXOlPY+GzzF8JvEQg7z8xQH9TCjtfNqk0zMn9m+F6Cfh8Q9W AQHrwYR1SlHgbUd8sZL8Gx3RWgezxs8UZ/+5z0oWRcuH4bPcKysKFQg/lrKy3JG7eJ3g yP18PWAlgxtpbjqTKwvgsxtTGyFdr2lNqqaGt0cuTjVcIrET8ojFLhTdJImh9D7xANLr 7Vzzgy+tQrI2orh2tVz6lOrQTaQYLSoZttJDLvfgbylbppMD6GOSTSMSeJO//nLAA+yB JELFolDrr4osceQg+2yQby/q0ABDTn+G46eXmwyZJ0kRwcm/dQPE1j1pyUC2AvrJoNVq itsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ISIsOoWcwTH4BDSJWMIHj/fX6z00Tw3LJoEr5p/Nk/Y=; b=NE/DsoopBaJsukcjPSCP8VUue7ZwHDHBDeJfIokmmvPEkCzuy5diICnxYnXjGA0f8N J3S8+fB5gPrsuyptKUf1Gc9v8Exo+sYh66owUn6HVAZL4KBydoz0zAotlAf3uPZPAhh6 tMyaftOYhNnBRNaCg/OR58aeY5dsSvUHT2nDtvgIqhrtH9WeUiHiuJ6oJboqoO/1Xjs3 FJrNtU8L6NP3girKyzxeVLIPWo/IfsAS4SH7a8D4fulQE45MmobgVlWQ+1PRSS1CbQuc atOcZirlT7z2KYGi3AQq6MGkAyFDVgKLWbajN7pypWzuiSgR2ELa3w4ESQ868lHjCPSp gwSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YL5SJtM5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k10si84372iow.62.2021.05.19.11.53.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:53:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YL5SJtM5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRK7-0007ww-Oj for patch@linaro.org; Wed, 19 May 2021 14:53:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyh-00046J-C5 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:31 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]:35694) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyS-0005jN-2z for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:31 -0400 Received: by mail-oi1-x230.google.com with SMTP id v22so14011044oic.2 for ; Wed, 19 May 2021 11:31:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ISIsOoWcwTH4BDSJWMIHj/fX6z00Tw3LJoEr5p/Nk/Y=; b=YL5SJtM5SLj3V/NXuE/wB9iAay/5y0Wx8R2hSbf46JnpUvv83/T3zf3ceBDSXGFWM2 81RTtkw1aEEuSdtedqp0K4MbnUr5tyAnm6t6iGh7CFwYyfALWDEHgtybqEX9xlfSNXQh aWSzX1bUxlJI1V2/I8QV5VY7CUW9FRzvokKMk2Dwz5sx3O8Z3Qn7XqkeE83wQ4HkMh+Z AECkcWtQOPl8C8Jld/zPydQRFcJ7Z04Wy0ZwZNWN6XteanNy3MpTZRSAxSYYvlTjAyje TqB0gVPznzvykPyB2X/Q1J6T4Mvn2kaJ278d5o+C/HeKja1m6nEBy2iK22DWHrYuFYQ/ NmcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ISIsOoWcwTH4BDSJWMIHj/fX6z00Tw3LJoEr5p/Nk/Y=; b=C5k8gj2xStkufjH0da1QzScQnXwa8aTfONoBiGDpZdUtq4FZm1w0LCOD/O9fpSiusj oW6DvkocsmFPl5DvgE6i8BRHeOFQ2YgDrdKCrDKzG7gEFVG7Z0GbD3A8nnWkw+2OYMBs 6lpMqxyP0kzG0SCK7u1vaPaUKBe6TM+ByW6s3rKXxA8nLHh1UZT6F7l7DNXfFZMSk4F1 wKzir9vM/KlgHfS/Ml/+wnWUndStIvbyQuGLtzlS1xritrssi5LWOWwCan9QXVvw9Mdt zDmXylQfrwQOGsbeyJTedxBLavd7AeiTYx9WSsZO85alrP/dMTZqquP3FgEw+wmyrsbO QXiQ== X-Gm-Message-State: AOAM531IsTVuLfENb9fB7c6y1iaAs1wGJYSSHLlHzGhI/KUydYsHkwke Dw7Ir0VgrAGTQbw/ci/Xr1NfmfMJlVCvi0nd X-Received: by 2002:aca:1b15:: with SMTP id b21mr489787oib.155.1621449073268; Wed, 19 May 2021 11:31:13 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/50] target/i386: Reduce DisasContext.override to int8_t Date: Wed, 19 May 2021 13:30:21 -0500 Message-Id: <20210519183050.875453-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The range of values is -1 (none) to 5 (R_GS). Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-22-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ca7f0a8cf4..44a28858aa 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -77,7 +77,7 @@ typedef struct DisasContext { DisasContextBase base; /* current insn context */ - int override; /* -1 if no override */ + int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ int prefix; MemOp aflag; MemOp dflag; From patchwork Wed May 19 18:30:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442475 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1587353jac; Wed, 19 May 2021 11:42:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhsUKt4nVhWsNxVL9idVrlahaXM1sKXR7wmOFVoGN4Xn6lWt3w54OHLu/cvE9x32dotI2y X-Received: by 2002:a02:688:: with SMTP id 130mr465276jav.48.1621449721996; Wed, 19 May 2021 11:42:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449721; cv=none; d=google.com; s=arc-20160816; b=lAskpyKlKP3go0tLv5FRMkNV2nAmLss6uZqTSSg2FzhMdpqQSmGjEOUQHk6NR2vq3H s5BQESaR71BpMyGnGaVw3jiVGQ5W5+RmvGOPTb5uZJlF0uVve4dzN9UeOCVqYnuAhV7l I/TgNY6w/Ms9pnKhVjgbaXxEv4u03+fg+DSzVhk4gRRBS6GnF1tThgGlgYmXddk3Y1Su eiLTQGtk1/Wfbg9q5DoDtDSkR4eJks6JJFu1Je3oeGJBBgTdHLJAgSicX+tJjxB6ooWA 4jh8XNoBlFqa4sTl62BFHqraFQkmRs+CKYYc1p65I+ya9c7hxgh66r+tykkev9bIA5Ua wAXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L1q+mpwSa9G9Zc5+8vLZr7OPXyD4MHPxLRrUGJAX/p0=; b=AM/iLpXyl5ATWmkRDK7VCID5eunAPY4TaQoEa+gIBlOnwBkXB99GZzKGiTh+yMgsJa xAvU0Sf/ba+SFjb2tDI4xmEJ/CeUSEAWCyXa1lc5SUesBWK4k/JOndWXCy3myDV1fwQ+ DcWxA47iTD4n3/Jl4cCHTybrbVC086Ua0G5FwNT8onOUzC/t2UwYpYjZUXgAiPVF1vqg FkePmytgy5f+wI9aDr+Mp8evQF44clAqH5DkHRT3p8KnOHqqKtCAvIyZ20xoe+VIakEK rbnyecPOnS323vnRTUshc2dZUOs8HfbqyEo9lpDfpPZznI+Lz646r580wsKNbeAn4uRt b4Sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cwbra9EE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k6si70260ion.34.2021.05.19.11.42.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:42:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cwbra9EE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljR8r-00067F-Da for patch@linaro.org; Wed, 19 May 2021 14:42:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyZ-0003ux-Np for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:23 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]:35666) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyS-0005jf-4H for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:23 -0400 Received: by mail-ot1-x329.google.com with SMTP id 69-20020a9d0a4b0000b02902ed42f141e1so12616337otg.2 for ; Wed, 19 May 2021 11:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L1q+mpwSa9G9Zc5+8vLZr7OPXyD4MHPxLRrUGJAX/p0=; b=cwbra9EE0ahqxbcpgSwskeZncyAuIlhmrOzl/MTrw1O/+MDEWkZzV0FSyuF1TTdSnA oWCSn84PK/kfcMcyFiPg+v5jxZm8erjcIfnFRTycU06vRciZTbACzBfDz8MpBQi7JV0p O2JcdkVxmcFSxzQXSggx6XMPkomZMtpiUWcRGg0+/NPRZUB9Gy0OCzu3mlpyv3Dpq3ub 2OE/axJB7S5EvUV9hGcqDWAHVSUjL83YbxE7gLvA8OnurSSi8pcHGhjURoWB6du6KWNU bD0YOnphSzCFHF9rABjv/2V2DkSX5S72pC6/mmoKU7gO5OfocAj1N/tmNLISEQQtF2tf HzVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L1q+mpwSa9G9Zc5+8vLZr7OPXyD4MHPxLRrUGJAX/p0=; b=o+UhvcVD5jLlImLhanxI56efr9BRmDxTB5Tdzwomki55DpXiLb/UrgD8+ws0JB0jNm bFpDn+eevwrpNbMEv+PQrpTJg4lLwFUpnCHw24hGMtmyOusOzZM2LKN+lGC/XBp7LZH3 maF8MRAWe96HyuoHP1mAcmFjTJ7SJiGfHHbnCGN1zIa6nd+js7txmB9QgaUZK140XTC+ tJh9Btvg6IHo4RkymwXHHFyVelob5Gz4/zTgyhuoFBqjew78bL4pyXchRf254jOB7YNt bpzlrSiMOTJlXkdpgo1xY6HDI2xZwrHgOxUTfXx6Jx5o1jhCPUQuC56miEv43XjYFdBZ yluw== X-Gm-Message-State: AOAM5316tqlxIwyvmIdGpdNPwwUjqtikSRR5glPKMN/hl2Brbn4u5TeB kNPTz24AbXMfdYDOYF4gd5j7/vEu9XaCcFy6 X-Received: by 2002:a9d:c64:: with SMTP id 91mr669039otr.130.1621449074246; Wed, 19 May 2021 11:31:14 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/50] target/i386: Reduce DisasContext.prefix to uint8_t Date: Wed, 19 May 2021 13:30:22 -0500 Message-Id: <20210519183050.875453-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The highest bit in this set is 0x40 (PREFIX_REX). Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-23-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 44a28858aa..61c0573c2f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -78,7 +78,7 @@ typedef struct DisasContext { /* current insn context */ int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ - int prefix; + uint8_t prefix; MemOp aflag; MemOp dflag; target_ulong pc_start; From patchwork Wed May 19 18:30:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442483 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1591342jac; Wed, 19 May 2021 11:47:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTxiFjuK+MIgs31m/iSnzCoiGopbrtGxWBV/xaOOXkJ4/MWEZ71T6gWPytV2H2NA6txCw/ X-Received: by 2002:a25:e443:: with SMTP id b64mr1283182ybh.379.1621450069696; Wed, 19 May 2021 11:47:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450069; cv=none; d=google.com; s=arc-20160816; b=jCX6SufwR3PVKPwHMUyAe7xszxZ9Ji8MCiOjIZ5inPF7sXOvAI8nJS9c53zFacs4rg zqCQq84+BPI7I2PJXSz/voo+RbZys85P4oRKUTdAqD4PrEZYmtfU7MltIz0MVwCd6Em4 ITkqOKr1FrUEt5negPMhJWnczH5D63Bys6PmVVz+Lwm84ws4wB34ACTM6yKYyq7m9FSa 1bMjoln47+XTaBx2ZaE6Idrer/Gkh+x1HN941yAmIXR2w8/ANgLhWuIvFmAyv7EwWKB2 36uDklQ0d+TCOWzes/Et0apXhnrOwKG86vElVmI21Zcqe6NQao/b8FpJk6H0iOR+OIbF 3c0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MmALl6+SrAgZGE+y4AHRDA6ukcJz+jYrukcq8t6BAbA=; b=EqOYNe6aw1ZC4lT7pakNZWtuWJDA/vSzjrqXOga5YAYpIDK9zp7yGt6+5z605M75cD /2PlO+704as2TKfn/IxHCKtXhh17qO5iG4Bjp3hiWpKXqPB92FmiR9UF8AqA1kjjlylM 4XoTY9VvC+QXQSb9FY3ANAmXt/SpWK0GcJIlrSCH9c41RM3MHxzYHm887HGo1gH8J6Fp BOiLKRFWrSTykR7y7lXedX7V5siqycQzlmYKKFU9bgdQga8fq6GjID7Mf+gMN/iOIa9/ UO1KqArPEUaNfaFx62FyfTLWpu95GqRoLwL+BItygOzWtUsMma199KtH81uaiin1UsrK nuXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E7Qi3grS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y11si259814ybp.31.2021.05.19.11.47.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:47:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E7Qi3grS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRET-0000xJ-2g for patch@linaro.org; Wed, 19 May 2021 14:47:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQye-00043P-9c for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:28 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]:34688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyV-0005kB-AR for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:27 -0400 Received: by mail-ot1-x32d.google.com with SMTP id u25-20020a0568302319b02902ac3d54c25eso12656592ote.1 for ; Wed, 19 May 2021 11:31:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MmALl6+SrAgZGE+y4AHRDA6ukcJz+jYrukcq8t6BAbA=; b=E7Qi3grS40snfcUegvCNE9Ukgir8DUOneR0HOdM/5u5omYiQUBx7LZcCSxX/vR/4f4 oMoBuCl1B0xNEqfsHb49O7mtmUgrm7jZTvwODPlXZxbS48NvuWWhqtiS7tbs6VlQWX70 Z66N5Lo0CjCSAkVeP0dauTMydVlZlUBL1nK8jNvpP6UJpa+nTfhjA/BN/ATlcwyxMcSz CRWh5lR7j3wlE7EvMkGn8oqO1kzDzcX3K3WRC2/0ulZdDdvVDvAmsQeqrBZU4QHG5TUn 3M11lFfdWqzYKD/JFNIaF0VGX/xFsj54nluKLp4kLsxMhmuoYo+nCqZ3jkcu7RPZLxlx YoOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MmALl6+SrAgZGE+y4AHRDA6ukcJz+jYrukcq8t6BAbA=; b=P8o9EnfsQyGzVWliOgg0BnBBQKvApROq/FQj7+IiEN4ly/2LZ+h80vyZzCfcZBUQ9F iSRRJx1kRhdcoI2FCNptSzijBnqZE/J2HD8bh0X7V12/vi1ZQtTfXyncGODPIVfV4wSk oinp4P3kaUd75I2UHZt/Zg5s6R2WG6Re1up6TpqQ1kh27mCcQOzoEAPo8/JQNYCoeo5V AvWK8Ig27dekXms98lb784HQcoYtFfDPnk9wM/3me1FFSG0xNAAXQa4BA0NTh/OSXaTi w8dTFAGURwvAKxiWaBh0E231V1W8N1vJSCZNkxF8yds9401NVbp/Ar2L0EMdqdHOUQTv UDyA== X-Gm-Message-State: AOAM530xERdEGhx/juKhURmnGv5La5SfvrQ97/kaxVz7njx0DY2xPtqv AhJO2Q4e3OXJXn+I5Mn8C6/FkOzC4gJZ2sXA X-Received: by 2002:a05:6830:1e6e:: with SMTP id m14mr626268otr.215.1621449075289; Wed, 19 May 2021 11:31:15 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/50] target/i386: Reduce DisasContext.vex_[lv] to uint8_t Date: Wed, 19 May 2021 13:30:23 -0500 Message-Id: <20210519183050.875453-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently, vex_l is either {0,1}; if in the future we implement AVX-512, the max value will be 2. In vex_v we store a register number. This is 0-15 for SSE, and 0-31 for AVX-512. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-24-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 61c0573c2f..1367e53e4e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -97,8 +97,8 @@ typedef struct DisasContext { uint8_t rex_b; bool rex_w; #endif - int vex_l; /* vex vector length */ - int vex_v; /* vex vvvv register, without 1's complement. */ + uint8_t vex_l; /* vex vector length */ + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; int tf; /* TF cpu flag */ From patchwork Wed May 19 18:30:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442490 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1594028jac; Wed, 19 May 2021 11:51:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqwJbsttAc4Xsb3CHGc/9ZUxjoIjqGGygy7mrnVuMymSSB6qP1M1bAvcQMgy1WMTtxoEs9 X-Received: by 2002:a05:6638:1482:: with SMTP id j2mr480632jak.63.1621450315339; Wed, 19 May 2021 11:51:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450315; cv=none; d=google.com; s=arc-20160816; b=k11+tPFVHUlcz5QZ35V7ZWpAn/0lZqhaHxP0GRL85XC2rEji7n7/Y/xSXLd3YF+COA +XWU7SbuIm69Z3r8ClnuHpekKoEbuHbTZhYlnOgErs+FQWCw6uBQ2t4k3FX1vslJ8DR+ +zoL9fxsyNqosQ9LlJAFwWvsUopPK5nubAGtLlf9Yf/ebyIJ95DHOXdpKzLCAqqC52jj EeJ3LJu3438n5keBRAeC6xMvZKFvDew3K3NGBeqy/qC5OHbONb67fcfqI8rZI4/twsaO AYh1oPbmwxVTKXZjHUXGsKEpsmUB3Igc1EX+MajItJ77/ymppyoTxOlQwulALgm9q29E pLGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GrHhxNQ2eayYuE4IBP3WlrTHRS6oVMsMWIzwFX+Pnhg=; b=XhRSZAMX8qJOxNwp+uI68iy0SGV3xE/lGjo5CgwB5VJe3Qg92CYgsinlADKQOS9Gwm uvVUQ9jP3DgzoiPbCENN4G5gUhkq/u+Yn5dntCMJqua6xze+vN++f+2vfjMsxtKUiwzz cuI4r/hP1Md3wy3MZsDNibd/wDLZTyp5EPFjiS5ggty8FATQa7CZpzrlw2PjAMWQ1bP1 MQ1uQTREOEuBG3jANqsJkO1sh8Kb4J8SojEsSShDBDW6lel4vmi6Z23NHRCAjAvsy4F1 blVYATqSw4zIerBaRdC1oiRmWb6bwUkbq9h5+e0xq5ruKuiUwXx2OZL4H9jG0XoIQ+CG diFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zkE/VXXP"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-25-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1367e53e4e..847502046f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -106,8 +106,8 @@ typedef struct DisasContext { int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ - int popl_esp_hack; /* for correct popl with esp base handling */ - int rip_offset; /* only used in x86_64, but left for simplicity */ + uint8_t popl_esp_hack; /* for correct popl with esp base handling */ + uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; int cpuid_ext_features; int cpuid_ext2_features; From patchwork Wed May 19 18:30:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442499 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1598410jac; Wed, 19 May 2021 11:57:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIP+EKisRzNzEzaklSrvPqG/zoWocEbWMKEMJP3ZVjLpVOtN3Ar2pUsHQVkuiDBK3vvRWm X-Received: by 2002:a02:ca4b:: with SMTP id i11mr497040jal.77.1621450663142; Wed, 19 May 2021 11:57:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450663; cv=none; d=google.com; s=arc-20160816; b=EHVCtNXxfWaFZi+Qe5hKlf3QjEwk6uWYm/CM5NFLIRAMq5s1EaCAWcKAEg3O8ta5jO dy5MSxVEUTtARmza+NXhzXsprld3eg3kuQ70JXZKVnxb7FGuGCttDhXQJYIgdW0Rx+Ki WZc0tiz6quKEwQ1mYX/muXedPkV3pbanaMDORnvB9GORzVuyaNXL2mtc8VUs7vdewMs7 MiFmHrZ49EDk2E/5MNz+9TSAJOgE/Jdk3VUXzSN04vv0eXOicQwVNGHTCSpCaEbF6TtG 2NqZU2PIGQGGDV82jsi+W2S14QzkrHbAtCxsGGS0QaYo3mhH4gEKZJDre/BWdf3/ifCf voag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ppegi43nBBiUhTlh14mXrYNLMdDVV4yeu967Ro8CEyE=; b=edBWJrGnbj1p/AHVdVTmWzqb1/TKi0QuOB+kda+Oqn2a1AXizbBpgTyA8+AG1zIBXk QSOiH32KhL7fbBb2QmalaYwXXgEkcW+SvuSTRZxxCIrB4Aiy8pWD79l4iYqm28HQCVSy blt2OJUPa2OVq94bC/jRbxT8GGmUzn9CRqk4Fa0rQ2eNwUcN9AUQHt7+SJ2sLzEO4ISG PQy7gSWGZkulp/IHfyKdl9eOFo1MsJnDMfiUo8mWeF6r/2KVFQMWU7hFLKURNpwspqAP X9fVqdCsSJ/t188h7my6TsP/AopzOsil7qnn7Unl3Wctd4RBF42zJ3bmfrOhq78rfhkv GvzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ChABmZJz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r1si459729ilj.100.2021.05.19.11.57.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:57:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ChABmZJz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRO2-0002WK-Dl for patch@linaro.org; Wed, 19 May 2021 14:57:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyk-0004Em-MZ for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:34 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]:33469) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyX-0005kp-AJ for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:34 -0400 Received: by mail-oi1-x230.google.com with SMTP id b25so14061177oic.0 for ; Wed, 19 May 2021 11:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ppegi43nBBiUhTlh14mXrYNLMdDVV4yeu967Ro8CEyE=; b=ChABmZJzZ07FBQMY2bT1o4YjK4a0kjdT9w6RZkx3gsBGSnFngaeC7oGikOXGUqYguP 8WsyzVvFgxk7HwB2+bRZW9rHvXDQviog4xMu+9z11/s5S8jvO9nl7KsfGPZPLaXDH/N2 7qPWxFZ0AtQWExh94mLO8YS5KD5R6H+94xpmUnPBrXBktCZObS0vKlvamgpDjnY30C5n xO30VGopal4QpY+2Vty9j/iufTrnOKaoOeP74Y88oIH4pETEDIrSDoAIY9liqp8b1kLm WCyXOMMaQHPRvd8exbNL9fEuMMpvA8FxGCtz3PE31HfAvwOEj4zAcTcNUFyOnhmaoELf 9yjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ppegi43nBBiUhTlh14mXrYNLMdDVV4yeu967Ro8CEyE=; b=RfKdm8oFes2PtGnY7Oqrtojql7T4PPowfo7uqe3Lkhwcnjm/Nu9p2jI/5z1divneu2 cJbXqsUy4X4u1HCa5mzehwwXze2yakp5KK1xyLpNHw/aUJ2OU11b5AuV//7DsXD5iXkc Hu344eDgxS7/5VeEgthohvyPSeQolBFkThirFiFl/N9yYKqZOwVYyJU77ESJLOK0G8fP gQxxho6CbtGhkMYEZmS00xwmhBh/YAMCBp38+PRsu5Aj1vdgZpsm8LS827wGLuBAKKbM LWMVdklfSdUoIyvNsAidfUJoFza4xzaY5ZaR97FqfDGw4HMG/ki+mLqwH4W9WOsjjAWR Fjyw== X-Gm-Message-State: AOAM5324Se0RDlhIyS+ALx/oE3LOOJ7v4UmnA8fFkwrv/8lo455EopCU iYXRTz13eRHtb0JZyhi0VwwIFZHxEXP2hfKq X-Received: by 2002:a05:6808:d:: with SMTP id u13mr378932oic.103.1621449077251; Wed, 19 May 2021 11:31:17 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 25/50] target/i386: Leave TF in DisasContext.flags Date: Wed, 19 May 2021 13:30:25 -0500 Message-Id: <20210519183050.875453-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It's just as easy to clear the flag with AND than assignment. In two cases the test for the bit can be folded together with the test for HF_INHIBIT_IRQ_MASK. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-26-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 847502046f..3f6214c624 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,7 +101,6 @@ typedef struct DisasContext { uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ @@ -2656,7 +2655,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); tcg_gen_exit_tb(NULL, 0); - } else if (s->tf) { + } else if (s->flags & HF_TF_MASK) { gen_helper_single_step(cpu_env); } else if (jr) { tcg_gen_lookup_and_goto_ptr(); @@ -5540,7 +5539,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->base.is_jmp) { gen_jmp_im(s, s->pc - s->cs_base); if (reg == R_SS) { - s->tf = 0; + s->flags &= ~HF_TF_MASK; gen_eob_inhibit_irq(s, true); } else { gen_eob(s); @@ -5606,7 +5605,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->base.is_jmp) { gen_jmp_im(s, s->pc - s->cs_base); if (reg == R_SS) { - s->tf = 0; + s->flags &= ~HF_TF_MASK; gen_eob_inhibit_irq(s, true); } else { gen_eob(s); @@ -8506,7 +8505,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->popl_esp_hack = 0; @@ -8521,8 +8519,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; - dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)); + dc->jmp_opt = !(dc->base.singlestep_enabled || + (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths in !repz_opt and repz_opt modes. The first one was used @@ -8597,7 +8595,7 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) pc_next = disas_insn(dc, cpu); - if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) { /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear From patchwork Wed May 19 18:30:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442491 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1594075jac; Wed, 19 May 2021 11:52:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzYpEDxXeR8wNODa8f23vgPX8MOE2mRyKiZKdCBuH6cIRdiPZqPqO9cyfAgcAKK4uRzs+5 X-Received: by 2002:a05:6e02:2162:: with SMTP id s2mr458605ilv.237.1621450319938; Wed, 19 May 2021 11:51:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450319; cv=none; d=google.com; s=arc-20160816; b=fzjbieHhVXqaGSX7Q/rfbkffa0etvT77UdMJIWYtNaSuWbCJoBT2jfapr8UPREvdFf +qDaFcMAkXOA5fqfa/wufJ7hlqe0WX3aNW6KJ9Q1yKw3G/NuczKmxu7opPCXQsRkKTMH 56vD6mP10aDoV7NPiwgV1zrDwHgSr99JH3z/jwme+tQJCxkW/IA2nzQ5n5l3FAtkz7xv H7lRFrLZS+jclIyN8mygpw60a8rZk1tRtxd+r4Ju+LBMnENkxa1oawLbfGM1IUk9Gw8X GFJ/QYqL+EWDTLhbaSztv0Pg7RKElvxTH8TChp7NpGOYY41rI3G5aB0CZ2jCq6kH10DD f90w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l7/mZ3OBU1PFkFN8QyiVnXNGXP8bHJzSnl+yFiRCNuE=; b=H2sho1C14wCObHdJiKPnz4ZPUY9uKnhD5LxIgcmXu+WdonSej9+qnYpgrdIFvn/YxW UcNXBObbRPPuqrn5FUvBMhpAHpSENUdQaX4a/WkI3WMIofDnzvBHq8ebH4I7v/mlBarl e33CQajkN/zDPoCS8K6wAZzb1L78vN/BV/IodQdBlsLPh7CHq6kuS5KJ9Y3yQRdxHI0q LVCNX2Z5fLiSQ4Bw6QP2uYbO/KRu1vlGtYjs6h5WogRVhGAUUVRXDvd9Ksi1Bz+vEThl FwK6XXC+cdz2PVvTZ6cg/5BfT5EBkPH6wnzipAZXMrZN/1yzVKoZQRGzvgnJzxErrHru XoWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W7E1tQl9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 19 May 2021 11:31:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/50] target/i386: Reduce DisasContext jmp_opt, repz_opt to bool Date: Wed, 19 May 2021 13:30:26 -0500 Message-Id: <20210519183050.875453-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-27-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 3f6214c624..b9b94f0625 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,8 +101,8 @@ typedef struct DisasContext { uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int jmp_opt; /* use direct block chaining for direct jumps */ - int repz_opt; /* optimize jumps within repz instructions */ + bool jmp_opt; /* use direct block chaining for direct jumps */ + bool repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ uint8_t popl_esp_hack; /* for correct popl with esp base handling */ From patchwork Wed May 19 18:30:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442482 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1590805jac; Wed, 19 May 2021 11:47:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzG6VkLIAxtNryt1Jllaf/pZxtBdkjHtsNqLwinzn0/NF/2c7C3PI8fe1SloIrlESw47r+l X-Received: by 2002:a25:e007:: with SMTP id x7mr1226352ybg.343.1621450025270; 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Signed-off-by: Richard Henderson Message-Id: <20210514151342.384376-28-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b9b94f0625..226fb62ccb 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -8521,15 +8521,10 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; dc->jmp_opt = !(dc->base.singlestep_enabled || (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))); - /* Do not optimize repz jumps at all in icount mode, because - rep movsS instructions are execured with different paths - in !repz_opt and repz_opt modes. The first one was used - always except single step mode. And this setting - disables jumps optimization and control paths become - equivalent in run and single step modes. - Now there will be no jump optimization for repz in - record/replay modes and there will always be an - additional step for ecx=0 when icount is enabled. + /* + * If jmp_opt, we want to handle each string instruction individually. + * For icount also disable repz optimization so that each iteration + * is accounted separately. */ dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT); From patchwork Wed May 19 18:30:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442477 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1588319jac; Wed, 19 May 2021 11:43:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMKRXAHwerYVjTVr3Jzg0JGDxI8aMFy0+mVu2eIoBCUrxUjVyLhy8KEH97tnWxgX2j3FLo X-Received: by 2002:a05:6e02:2192:: with SMTP id j18mr430919ila.223.1621449810068; Wed, 19 May 2021 11:43:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621449810; cv=none; d=google.com; s=arc-20160816; b=l8/2u0AKwz+8M80Nw6Y73+NyYoAsw4OCHQclDPFAQSY8GNjnJ5tvwNr0SH4J/EuGVr Fg/aKNwRRQkMl0kWklbBbdiXe4Ohr9IWpMwnHmpWOJ+50ilQzADA31mgHdA/uSxQ8aYf VYjAQ4NrS4jrNMba46I4q7b6XY08F7szvhaJz1wJlNTbq6VtagAxXZKLwuUuHqoXonPu Sy2esUPtSa7mIIan6ObE6qo2zkIBM6Dg4xlHowE/lIuaHfG5Ny20vNvlXdBvBjf0x2Ne zUIZtRa5Wv8rsBP/YhnW5fUL8ABNq97WqKLsljBdFU7r9QOl6bg07AgOE/UwskOlyC5Q JcjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8VIKm9TP9R9oeV0rPUDGQSAoAin6wclJNR1errvIaDs=; b=mYijuickvXXhoidbsWZgbNMV3po7oj7Oj1vzC33LcoCG1f1/0rujcS32OtQN3k3NT9 XfjX3O4C/dF1tyYTYrH4aXD1Rodl1X3mbxT/YdY1N5/AHz1nPXaWL8vflHB93EwGTdqD fF1+82myobRT4YixyK9Dgjuyr8/hWB9y0/x/1zkQySakhGMVJO3uywaTxDhQsjHNNtyI BPIB7UNYLfSKNgMKA/s7GoTPWHb9ByB3tdRzADalfrh31v5EirE7Ch8KfAtLtBSmEAYp YHhNG0XxcX+gc2DhsKSWi3motDR7FFkB2BuRvGeL25lICcCb0059nfM4S+RjxqApCc0E +oDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=njwVGGVf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-29-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 226fb62ccb..5c321b338e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -76,20 +76,24 @@ static TCGv_i64 cpu_bndu[4]; typedef struct DisasContext { DisasContextBase base; - /* current insn context */ - int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ - uint8_t prefix; + target_ulong pc; /* pc = eip + cs_base */ + target_ulong pc_start; /* pc at TB entry */ + target_ulong cs_base; /* base of CS segment */ + MemOp aflag; MemOp dflag; - target_ulong pc_start; - target_ulong pc; /* pc = eip + cs_base */ - /* current block context */ - target_ulong cs_base; /* base of CS segment */ + + int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ + uint8_t prefix; #ifndef CONFIG_USER_ONLY uint8_t cpl; /* code priv level */ uint8_t iopl; /* i/o priv level */ #endif + uint8_t vex_l; /* vex vector length */ + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ + uint8_t popl_esp_hack; /* for correct popl with esp base handling */ + uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ #ifdef TARGET_X86_64 uint8_t rex_r; @@ -97,16 +101,13 @@ typedef struct DisasContext { uint8_t rex_b; bool rex_w; #endif - uint8_t vex_l; /* vex vector length */ - uint8_t vex_v; /* vex vvvv register, without 1's complement. */ - CCOp cc_op; /* current CC operation */ - bool cc_op_dirty; bool jmp_opt; /* use direct block chaining for direct jumps */ bool repz_opt; /* optimize jumps within repz instructions */ + bool cc_op_dirty; + + CCOp cc_op; /* current CC operation */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ - uint8_t popl_esp_hack; /* for correct popl with esp base handling */ - uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; int cpuid_ext_features; int cpuid_ext2_features; From patchwork Wed May 19 18:30:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442496 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1596141jac; Wed, 19 May 2021 11:55:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzETyVzhZbdB/dTInlXS+o3pMzzd21vXA6LAyu47Ml2e5qCNBrVnki0EKvxrXZ4aE78zktU X-Received: by 2002:a05:6602:189:: with SMTP id m9mr1048228ioo.88.1621450501454; Wed, 19 May 2021 11:55:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450501; cv=none; d=google.com; s=arc-20160816; b=ry8xoCfTAUw1RdIrqYn5f957wDQDBCo9CAQVyJ3Wy8CXdZqDNFHDJISqSGwzbBlIS0 wEzi3nxBS/WohmIVYYo20LQm6fAIlwYtW4Q30NEA7jDf2aVR5A0zTKn9QqrH7BODqwXu NJGe+iFpV+Fbi79HHryttSIOmHJWuvSbqhsBaTvPI8QnjTs/g3TYmaGtyDFd2cJWfXwQ C6A5YHbVq4kzdFuN/sqkajjShwedd+bpCt9M4rn5EDXt2IsAqfyKxDg16/UmiqVtWxp7 mrxZlE4W+1tlB0RIcckidc4GogIxEilLWZaaFRfsqHw4laZFtrGdejiyEw6NuYLpN7fv 4mkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ml4zJu8F2mL1vM6aa47NTwYNU0UFpq7nQwZNWCia1A4=; b=nEeIgoDlvemtM86G0NZiWkUTjBntzRhtRB/YX04oqHeBW/Mj8ime+rsA0lKgry8QTI tu3xdhlrlCChS0pTe5PqbMQPIjb4hzI12BQrpU17rqRqZ7yu6abWmqS/3pdXxNBOGbNk J9AmaduZmxchBCyUZAN19WBp6A3/jSWW94CmJe9Ks4nMG4QB8JOCdnRSM2mjZ24szGYd Ow7vh4wtTNlMdur4ELbekOr1Sf+msNhawT+e/3yT/9mzJYBHUTM6wAAk8dSnia7kMKdu 7LhOSXgPTG2ETJO9+0+UxeHQ3HUYIHHTnabkVROpoeV1fQqCDca9TQzWmnUMquMuVCC0 dxIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ab1gIVwr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k21si159851jad.9.2021.05.19.11.55.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:55:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ab1gIVwr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRLQ-000592-Sv for patch@linaro.org; Wed, 19 May 2021 14:55:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyj-0004C7-GL for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:33 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]:45624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyZ-0005lT-AU for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:33 -0400 Received: by mail-oi1-x22e.google.com with SMTP id w127so10159708oig.12 for ; Wed, 19 May 2021 11:31:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ml4zJu8F2mL1vM6aa47NTwYNU0UFpq7nQwZNWCia1A4=; b=Ab1gIVwrXJnRY4PbLD8umcTkk7p573EO+5uSd5XQW4JbkGWTC1J/9IP+DYlXvmv4QH jHqzvCiEh+9Aes/2FrepBkrFMG4T1coptd1V/okpiP3PxxAGxNecERsf8ab0XlVZittW valXFVeZpoWS+7EO842SeYoUeBd+fEsJ6GSJbO7zlIn3tBnahHeaWwAemdaVW6YfwYeW DXocG2XOmiXIeRm1LvpydHIkwfuxoPyDB3chQqO169CNRIaRA9GPIVCPq47ef4JmX0YA eUn9KFmYqwgm8L6aGGHvu8Mw06JTRzQ/kpcVTNI3dT9qFZ2UibZt71TGmo/cYQuYQ3A1 u5rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ml4zJu8F2mL1vM6aa47NTwYNU0UFpq7nQwZNWCia1A4=; b=FpDQj7TcujE3if1tvsfnHNcUbTPsirMl4rubMHTuMAIEoZFbEyJWl2EFcfajqzBa95 80WsWeOl0PNQXgYuH/gFcPIOvLq25qugJHArUklrY8ovpGa0ka9RDuYfD/gs2/1N+MGI XIUIE0SXfFm4HZc78RaZi5zEgRmGkQiZtolQ5NCf+nkco5Xe4MKngJA9HX53JDe7LqOm 4C/9FsICrLG68rAyKZW3exkbH7IVuZUk5hGcFyOnT+QlvaGwNEh/jzmT/RSwoAUfr09e 4zSEIaCuGTOQ27nmeKGIMWcTsoZn03TQoNlXs9OjS7Qh0oDMzPl4TShkiUKPrP6TChLD WxNQ== X-Gm-Message-State: AOAM533A+XyGkEnn5qCS0G1O3cQHJg6ZRt1nhws4zu2W2B8nhLerPNsW Ye+4N2ry+b37xp37+iFfQIEpZR1n0eor3gSY X-Received: by 2002:a05:6808:1154:: with SMTP id u20mr389559oiu.35.1621449080911; Wed, 19 May 2021 11:31:20 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 29/50] target/i386: Add stub generator for helper_set_dr Date: Wed, 19 May 2021 13:30:29 -0500 Message-Id: <20210519183050.875453-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes an ifdef from the middle of disas_insn, and ensures that the branch is not reachable. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-30-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5c321b338e..28eb0e8adf 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -179,6 +179,19 @@ typedef struct DisasContext { #define REX_B(S) 0 #endif +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { qemu_build_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -8075,7 +8088,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (check_cpl0(s)) { -#ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of @@ -8104,7 +8116,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32); gen_op_mov_reg_v(s, ot, rm, s->T0); } -#endif /* !CONFIG_USER_ONLY */ } break; case 0x106: /* clts */ From patchwork Wed May 19 18:30:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442485 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1591978jac; Wed, 19 May 2021 11:48:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNtkTr+65WEc3TDgp5Me0uCIp9ZywUgjitKt/Xv45dZf25pNDbuYvOI/oOgD2zmJUspy2o X-Received: by 2002:a1f:add0:: with SMTP id w199mr1199071vke.0.1621450130817; Wed, 19 May 2021 11:48:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450130; cv=none; d=google.com; s=arc-20160816; b=oDvu3ys1wowo+bpiLQm5Zb1B3Yw4yEtm7pFpcFDThZE/I1EuIsqn8S2rhH/fuuqMrg /orj7F9d6uHXyAPEMWaw7rEBAjYEfWwQ2BmaM1qnKewIu21+StKACqwQ/9IFlHmde7uv mqOJVr1x0BD9nIznLwavihvuO6a7GG2d6f4OHSIDQwNb/P6Fr/aKDPifjwJtD2lgKa3S rz0pqJ/+0HKN+bNRGCEeepVtbzWA4aUiwN/oJWjWtd4kmsQyCC4abzVxxdEuf/PyE/o4 Tn6m1++cP3BWO+9Mu9vXB2JCq+2jT6YfNNZwVJHyQlxcTzSxs2Hs9WfNS8x1bpN3ZEGa oLDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nqW7XsN57M2hYAJUK6/QOBNZBxSwu2T66IctV1Y0s/A=; b=spVMiAXFzNsvF8l8Csi8YiMRlGNtu6zNp+paJ9N3q1AF7q+hav+0wxm3zP+lgm3/GR amLrNUpUMsX7dUigK+bsBfvJ0sp2OvO3utGdaVTJz+KkOQkFzNvjNbIsEu6WA/wJkrxi e3KmUqg9aGfBXlga3toZPtcFl1Ji1o29hD0cDlnaqdaSMjJrFWShGziM/piLysjK3e2d zRh+U2+53HSOnt0yJbgnudbWL6mPE8qeDU31oBci9B87fGtV+HiYyaOxMxTe+qupKPzS cFkHvq25UhurR4ElW+CZMBtlwRFuzmc2eAFhdy+Z9sfOOxG0Mrd/6Qzi8pVwKLB86uQc w6cQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SnqMeTAj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a186si344729vkc.54.2021.05.19.11.48.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:48:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SnqMeTAj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRFS-0005CC-31 for patch@linaro.org; Wed, 19 May 2021 14:48:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyl-0004Gy-BS for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:35 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]:33465) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyZ-0005m2-Cc for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:35 -0400 Received: by mail-oi1-x22b.google.com with SMTP id b25so14061359oic.0 for ; Wed, 19 May 2021 11:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nqW7XsN57M2hYAJUK6/QOBNZBxSwu2T66IctV1Y0s/A=; b=SnqMeTAjuWrxkMmy3a+oCbs8vSN0TfPhkZuiS4KDL7XXc5/nHizmyNHswCzDOi52xz 5May5pa1u/OsClq0PGP4PPZS4aK/QPrYv9i4UPVTjptuDQ5p8xidsIfEJjzIEajaT4l1 st3GHrfSO2Y5Q/lF+Us0fuhlQAbXEClvr0CK8AR7NSiqw1ppUTAYaljaXCqecRGWxpjE hzywhtrzPYy495RmVaQx33Ryewo7yYO1cY/KxhGpicZk06sT3XY3yHSX9TmtzpWtYdGo SBU0l3CCUZgAOKMu2+wKUPL98ai8CK776Q9YAgKbIiux04GPBV0/85LqYTuLKvJVXWpC BwwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nqW7XsN57M2hYAJUK6/QOBNZBxSwu2T66IctV1Y0s/A=; b=XRvRkHUmGY2KAUf5tpi4+/mSEoibrakuSiUCZANnJx43slLnCKIznyhnHtBUkp3RtF SWUlC+0BtHVazYTowpBvvEWP+wcLUQ2iBkYP6WXdUMkPoq2UrFJ6NFvfee1P1r/SIMWM GztmUEZJubnu1RfjjYqH3ndLCZY9y5Tdgkf/rnp7V2c4iqO2qV+hYIEMeyqh5D4ckPfW 7LEoRzwaJa5tu1BU0E2jPzv8OZFSAjmO8uT0DYrhMbWQ5INXK66aY/MMBTyeaFEWo6II RKTfhuf7fljA28SfGbt8CwUwXC2AyUnk9SYyCoi+wEoZbIr8CHrrooJJgZJRKfnlFfFy EX+A== X-Gm-Message-State: AOAM533dR7jpYYqJ05f4RvfTppgMC1ilVO5OXuOiZTVsXLrGrVzS4X4J z4H4ukgti31t2g6iS+ASfM/1WqGwXR6ri9+V X-Received: by 2002:a54:4396:: with SMTP id u22mr524959oiv.118.1621449081845; Wed, 19 May 2021 11:31:21 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/50] target/i386: Assert !SVME for user-only Date: Wed, 19 May 2021 13:30:30 -0500 Message-Id: <20210519183050.875453-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most of the VMM instructions are already disabled for user-only, by being usable only from ring 0. The spec is intentionally loose for VMMCALL, allowing the VMM to define syscalls for user-only. However, we're not emulating any VMM, so VMMCALL can just raise #UD unconditionally. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson Message-Id: <20210514151342.384376-31-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 28eb0e8adf..235caa247b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -138,10 +138,12 @@ typedef struct DisasContext { #define PE(S) true #define CPL(S) 3 #define IOPL(S) 0 +#define SVME(S) false #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) #define CPL(S) ((S)->cpl) #define IOPL(S) ((S)->iopl) +#define SVME(S) (((S)->flags & HF_SVME_MASK) != 0) #endif #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false @@ -7495,7 +7497,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xd8: /* VMRUN */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7510,7 +7512,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xd9: /* VMMCALL */ - if (!(s->flags & HF_SVME_MASK)) { + if (!SVME(s)) { goto illegal_op; } gen_update_cc_op(s); @@ -7519,7 +7521,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xda: /* VMLOAD */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7531,7 +7533,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdb: /* VMSAVE */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7543,8 +7545,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdc: /* STGI */ - if ((!(s->flags & HF_SVME_MASK) - && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) + if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || !PE(s)) { goto illegal_op; } @@ -7558,7 +7559,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdd: /* CLGI */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -7570,8 +7571,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xde: /* SKINIT */ - if ((!(s->flags & HF_SVME_MASK) - && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) + if ((!SVME(s) && !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || !PE(s)) { goto illegal_op; } @@ -7581,7 +7581,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0xdf: /* INVLPGA */ - if (!(s->flags & HF_SVME_MASK) || !PE(s)) { + if (!SVME(s) || !PE(s)) { goto illegal_op; } if (!check_cpl0(s)) { @@ -8516,6 +8516,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(SS32(dc) == ((flags & HF_SS32_MASK) != 0)); g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); + g_assert(SVME(dc) == ((flags & HF_SVME_MASK) != 0)); dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Wed May 19 18:30:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442480 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1590520jac; Wed, 19 May 2021 11:46:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyFZf5El3i3+A3nbLuPVRf7tsYOotZYKfMKWVkPGg0IHXr83eSfo2u3tQzJY2vHojQpHzV4 X-Received: by 2002:a25:ca92:: with SMTP id a140mr1480600ybg.273.1621450000294; Wed, 19 May 2021 11:46:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450000; cv=none; d=google.com; s=arc-20160816; b=AD6wk2FyTZimJ8PBn/OwLqjS+ZgfzwxHF2poM3kD/g4Zz2H282DMnog1D3kqmImwU2 0SGT4Lb54o/oJlkJMClY4fkX0rd71V2UyBiudkQWB70jaCmLNlDC+ZC03jfuMxrgd9FL 81fZIPTQ+2fkk3bMuiTYhjNpoU26kpDTaPiRdNz9rfBKooyPSD+PAX/MtCAMjcuaL2sP B+VcYLGJ7NdXRylFCSgFN+OCgU7CvIXc6KrAK0LiL/7ouQLW3CFwo+8/BkfUN+M8IEUt 0pSw95nWgyxccVh4cP0q+jje2NytLw0A7Kd7/wBHFKla+dsE6CKBOeVDP8Rnem6sjNCc sFrg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id r142si224612ybc.170.2021.05.19.11.46.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:46:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WWxnrjOY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRDL-0007IF-Lu for patch@linaro.org; Wed, 19 May 2021 14:46:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyn-0004LL-Ir for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:37 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]:34695) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyZ-0005mP-VI for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:37 -0400 Received: by mail-ot1-x333.google.com with SMTP id u25-20020a0568302319b02902ac3d54c25eso12656902ote.1 for ; Wed, 19 May 2021 11:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1DqtU0WV8QcSF4+X7m6wigiX0PReSyvreleY4X8ijYI=; b=WWxnrjOYRyMGRp7PhTvkVpu3miWRLibTfUgyUV/rhQT+M8wEdZ497h7RoZ8xLo5DQu 3hqlKE5fDn0r/ZnlplfgvkdPcudGWeb2CIqzT6zzsH8AvxdY5f2yAazWcj6Q2q7fSRGz U6Y50UCvXyU/hovCVnwZePZ/ZsBOW0M7BUzY0WO9x2P0mf8qQYPmlYhF6PqPvzQJsZrA fWfpKuJhjaNwaCrUXLvh6lmXp5viVA80H1oqDlYjcB1TvimSU2u4S0IbJys6Ntd1s3LK ymO895eWwaRgeBX+pEbOhoKVlEZqHuPWs+hGO4jqeLQef0t5kjPAXp4z1+T2BC8i3O7F JBWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1DqtU0WV8QcSF4+X7m6wigiX0PReSyvreleY4X8ijYI=; b=bniRptcmIHVhW38PelHgrF/Fj2z/UTa+kMDg54F3BR6hKKdbDko42lz9G/Cnabfz+g 8CQNvIiBnRtWmUamv/gCqY+UAo0FfjcBkatRatNkfcHkM9+uKaZ2eOFaVgG+NH7WwAc4 W85puVA2VgPCNgC/xM00EUP6+M+phmnIrP9+1t973ZWh6dDTzZ5IFRlMWioMZzecVUPz or41odxHOph75n/q2vqaex6a4HSUp+HqmY79YgMGWVFNpcdQHRVXZmfKdkd2hOkgIdgi S0tVqktqVvk2BGU6VEm5RyjlREZZnktAjsmHBgMvm2jWAoNW1Jt7cV45q8r1JE84gsuN p0+w== X-Gm-Message-State: AOAM533Ric4rrIn1wTRbJMKel/Bv7y3mGFLi+3FqyFfaOnrginUjhNtG Jt+It3eArxxvSHT2Eosur2DJQA47Cx6AyVdi X-Received: by 2002:a9d:5a7:: with SMTP id 36mr639756otd.321.1621449082775; Wed, 19 May 2021 11:31:22 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 31/50] target/i386: Assert !GUEST for user-only Date: Wed, 19 May 2021 13:30:31 -0500 Message-Id: <20210519183050.875453-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For user-only, we do not need to check for VMM intercept. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-32-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 235caa247b..200d205d7e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -139,11 +139,13 @@ typedef struct DisasContext { #define CPL(S) 3 #define IOPL(S) 0 #define SVME(S) false +#define GUEST(S) false #else #define PE(S) (((S)->flags & HF_PE_MASK) != 0) #define CPL(S) ((S)->cpl) #define IOPL(S) ((S)->iopl) #define SVME(S) (((S)->flags & HF_SVME_MASK) != 0) +#define GUEST(S) (((S)->flags & HF_GUEST_MASK) != 0) #endif #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64) #define VM86(S) false @@ -677,7 +679,7 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, tcg_abort(); } } - if(s->flags & HF_GUEST_MASK) { + if (GUEST(s)) { gen_update_cc_op(s); gen_jmp_im(s, cur_eip); svm_flags |= (1 << (4 + ot)); @@ -2417,8 +2419,9 @@ gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, uint32_t type, uint64_t param) { /* no SVM activated; fast case */ - if (likely(!(s->flags & HF_GUEST_MASK))) + if (likely(!GUEST(s))) { return; + } gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), @@ -8517,6 +8520,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); g_assert(SVME(dc) == ((flags & HF_SVME_MASK) != 0)); + g_assert(GUEST(dc) == ((flags & HF_GUEST_MASK) != 0)); dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; From patchwork Wed May 19 18:30:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442487 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1592313jac; Wed, 19 May 2021 11:49:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4K8Ozrs19JdshaBr35HXNEEsNVeJH+EzoQMdFcJGgf9xkM3Ameb9eqEQ22F+MDdEso+a+ X-Received: by 2002:a1f:c586:: with SMTP id v128mr869672vkf.3.1621450162906; Wed, 19 May 2021 11:49:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450162; cv=none; d=google.com; s=arc-20160816; b=zt7XWAgWsw9Aq43sY10a2PnAHBtkQMkJ44Gq7IvsXAECO7HSPUfazAyojBFYXZcMS1 MykYx6ZKO1P2vPzRdSWsIJvdKbjOjU/5DQ6j+//iJw6s15iGa1f7zR9Zwqngf4nECg5D f8X1ncT3/fK+LfxVfA7yZGp0tn+t8aOlTiSMLNd2XhkAos7sa2dAdFlI7oqb9hKkrKVa ISXkuio/AtLY8RSprPIY2ka4a0sWg0rNlMoZSG9es7s+9Vj/kO0RECYOZnByLFb6nDRK 6NvekvbDFhQJ0HNFAGDMebW4P0gHaETTfBd6eZbwzung6msvTDbKocco2bE11mH5NpQH 90XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oHyJNDPwLv7CDpqATFVKQ26htkoObORPlVS9sJxQt9M=; b=F0RnWKB5vVQDq2KBL85AWd69KA8hEJk6UHLJ9zbhjH66cMCREc+voIpG0Zq2v8YAta YieRpb+S14oAFJWODdK8adcFAxrnaztoI6weWLFjzJQVN5mdeC6vFSD6MCUl29CexHyG 06AnjEKUzTVoFmqyCJBJEpuVPjllm5cFHM9Hj5bBpeoOJkKzQXA6HCy7ejodY20ynhYs CqWsj38RzfMIIZO2w0tFB740etDmzHjmtUZa0hGLuu+FyTmyZGFyqpiYzrPfYWX14Fab /VTjqUuj5jepj/u5QWyBssFmEIFOxsPcXamT9ibnvTOu/+SAVGnBh5goCbB3yPauJHfB CP6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eCJZBmBa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u12si63230vse.337.2021.05.19.11.49.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:49:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eCJZBmBa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRFy-0006fU-64 for patch@linaro.org; Wed, 19 May 2021 14:49:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQym-0004JH-Vp for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:37 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]:38705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyb-0005mg-47 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:36 -0400 Received: by mail-ot1-x32f.google.com with SMTP id i14-20020a9d624e0000b029033683c71999so1434475otk.5 for ; Wed, 19 May 2021 11:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oHyJNDPwLv7CDpqATFVKQ26htkoObORPlVS9sJxQt9M=; b=eCJZBmBaTf45ebK9uSFdapKDqaTUgHY6JuY3IVmJK6/5RXPISNvg8iO1PFmSOVSGJV fzxjfQe3GQpmmra00VjRNhe1TCMyTZ+Pr8VP+0oAsPK74FsJQhEiiEgyrsxUoxs5t+f1 +7IUZWthVlvJK3rD4HgOtJsr7KCmUbuefA/CEXzeT30hvxZS1wkZ/8VT4OQp3Fa2G3xx pR36T9Gdv8utdZJYjwbYmRPWGH7IwfvRvQpfBoB56kd19CN/LOWPYveVCBPp0OQCvv7l 3SSGkQfIROs/l9di3i+vRyQ0jo3dBuyHt5eU4hj2oI9czFiCJAPmMYykzNwiimYHt7HB AIPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oHyJNDPwLv7CDpqATFVKQ26htkoObORPlVS9sJxQt9M=; b=WpSG8XjNuf+3DrD2Bk6feKS94eibRmk/P598I6JEZ2C4JiHO2rMou7DfQSOA31MKUE RpfkesQlZ24/Xupg2kNvRz0H/Ewn/id/DkBkfShmBvPf8l1pw38SKYhmdv/lm2waKF3W z4XDXVBwBKRfev7wCrmUfNJ/DQpqJFaBKBp5Da+OPtJf7WbyXeKKWwv9HWYA5VYa2jhV y3j3pyC44psQHbNO2A1DpmDOFsxnyM3ROtesr1hM92V295Yg8XwJxQyFKNoucA1pCFp1 2ZMgN+Ng0irsoSOc2Yz8RJE89/jRwwfUnNWzJsVrsuE2cY+zwnRxhTWOV7EyWNsFLxoP +7oQ== X-Gm-Message-State: AOAM5302bR/2QAJKqEIO9+TzEWjIAP9jheknh0+HoQMJ6AmGS1ivLdXQ KjsGPx0fmkIA4qTd7nuIV3Oui5/AePVg157W X-Received: by 2002:a9d:a37:: with SMTP id 52mr687003otg.280.1621449083752; Wed, 19 May 2021 11:31:23 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/50] target/i386: Implement skinit in translate.c Date: Wed, 19 May 2021 13:30:32 -0500 Message-Id: <20210519183050.875453-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Our sysemu implementation is a stub. We can already intercept instructions for vmexit, and raising #UD is trivial. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-33-richard.henderson@linaro.org> --- target/i386/helper.h | 1 - target/i386/tcg/sysemu/svm_helper.c | 7 ------- target/i386/tcg/translate.c | 7 +++---- target/i386/tcg/user/svm_stubs.c | 4 ---- 4 files changed, 3 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 095520f81f..7a09efd55b 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -117,7 +117,6 @@ DEF_HELPER_2(vmload, void, env, int) DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) -DEF_HELPER_1(skinit, void, env) DEF_HELPER_2(invlpga, void, env, int) /* x86 FPU */ diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index c4e8e717a9..79c73d67af 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -412,13 +412,6 @@ void helper_clgi(CPUX86State *env) env->hflags2 &= ~HF2_GIF_MASK; } -void helper_skinit(CPUX86State *env) -{ - cpu_svm_check_intercept_param(env, SVM_EXIT_SKINIT, 0, GETPC()); - /* XXX: not implemented */ - raise_exception(env, EXCP06_ILLOP); -} - void helper_invlpga(CPUX86State *env, int aflag) { X86CPU *cpu = env_archcpu(env); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 200d205d7e..f7f84f79fe 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7578,10 +7578,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) || !PE(s)) { goto illegal_op; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_skinit(cpu_env); - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT); + /* If not intercepted, not implemented -- raise #UD. */ + goto illegal_op; case 0xdf: /* INVLPGA */ if (!SVME(s) || !PE(s)) { diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c index 97528b56ad..63b37f0de6 100644 --- a/target/i386/tcg/user/svm_stubs.c +++ b/target/i386/tcg/user/svm_stubs.c @@ -46,10 +46,6 @@ void helper_clgi(CPUX86State *env) { } -void helper_skinit(CPUX86State *env) -{ -} - void helper_invlpga(CPUX86State *env, int aflag) { } From patchwork Wed May 19 18:30:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442486 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1592271jac; Wed, 19 May 2021 11:49:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyX7x2lolcCBclTb5YZWa0w5hnjvJOpsQR6ja6c6bcsbM+/qNT1+WFvGednEkSsG9Y+qXs2 X-Received: by 2002:a25:cc5:: with SMTP id 188mr1333853ybm.59.1621450158980; Wed, 19 May 2021 11:49:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450158; cv=none; d=google.com; s=arc-20160816; b=MThachukbUaDMK/ZTrJxPVpPXJlMFYwB5GGvNPfaG1aeaflirYaC/lVZRpgsgHQZ5i UaPRcE9ywTv4+oBFBzn63m3aC1Uww7dr9mFdn5WMaB8s8bUG8UzbwIwJJ7cOdrHQhVnC g1fP2ftdlzbspjNZ+qmQ7j7A2nq0UxyDNQsrQDRa3y2PEyG61kCpYLgQe7Bw26LFCedu w7g53q+yY2X7XdZ8B1bS9hvRE2Fe1ISUDDDkyYpeKgOksF0Er8uxUWAhuwvcDdaDwJig 41JUkZp2ZvNUfbZGrcSDUmZxyt/10fDEzXitGOPk4HzL1NZPMYIsrKmtFVsOKzOXwN2b ob2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5OwIdHlv3LdKR7MTqV9VCeiU1XRsbRl+uomjXUgH9RM=; b=VByGDGvVnAzHSPZk67ubEGzDpjr45wRk9KrGbTq5q8QdvyOOPf178fsz95SZ4Kbe3V EllvJsvjc4G1vDK8BX5e6KfZv7pmQLd1bEi6n6zPS9b7opKdzAebRN9y4NhwzZRgzJt0 iPneTYw5WhKWMtVLQaPrKnFkc5JU6m12u1DZ4HIdnpy+pIRS2uQU/cRqJL/gx7jhELZC UKc+p1AOYVLo82U6ZxG5md84VgGTMOD9r4CBKwmUmrjRfPe9ABpjwdZ7NFYYSk+DwLSS FUlxGreduKaDQOWf8kh6L6EzoDHQF77G4W0WyQhGkleHrWMNzibimpFhYAxapWrIUtOH I5YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O3Qoa0oP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-34-richard.henderson@linaro.org> --- target/i386/helper.h | 3 +-- target/i386/tcg/translate.c | 9 ++++++++ target/i386/tcg/user/svm_stubs.c | 38 -------------------------------- 3 files changed, 10 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 7a09efd55b..d0f7f07c6c 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -107,8 +107,6 @@ DEF_HELPER_2(inl, tl, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) -#endif /* !CONFIG_USER_ONLY */ - DEF_HELPER_3(svm_check_intercept_param, void, env, i32, i64) DEF_HELPER_4(svm_check_io, void, env, i32, i32, i32) DEF_HELPER_3(vmrun, void, env, int, int) @@ -118,6 +116,7 @@ DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) DEF_HELPER_2(invlpga, void, env, int) +#endif /* !CONFIG_USER_ONLY */ /* x86 FPU */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index f7f84f79fe..b2a997fb30 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -193,7 +193,16 @@ typedef struct DisasContext { { qemu_build_not_reached(); } #ifdef CONFIG_USER_ONLY +STUB_HELPER(clgi, TCGv_env env) +STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) +STUB_HELPER(stgi, TCGv_env env) +STUB_HELPER(svm_check_intercept_param, TCGv_env env, TCGv_i32 t, TCGv_i64 p) +STUB_HELPER(svm_check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 p, TCGv_i32 a) +STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) +STUB_HELPER(vmmcall, TCGv_env env) +STUB_HELPER(vmrun, TCGv_env env, TCGv_i32 aflag, TCGv_i32 pc_ofs) +STUB_HELPER(vmsave, TCGv_env env, TCGv_i32 aflag) #endif static void gen_eob(DisasContext *s); diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c index 63b37f0de6..48a43bdcea 100644 --- a/target/i386/tcg/user/svm_stubs.c +++ b/target/i386/tcg/user/svm_stubs.c @@ -22,51 +22,13 @@ #include "exec/helper-proto.h" #include "tcg/helper-tcg.h" -void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) -{ -} - -void helper_vmmcall(CPUX86State *env) -{ -} - -void helper_vmload(CPUX86State *env, int aflag) -{ -} - -void helper_vmsave(CPUX86State *env, int aflag) -{ -} - -void helper_stgi(CPUX86State *env) -{ -} - -void helper_clgi(CPUX86State *env) -{ -} - -void helper_invlpga(CPUX86State *env, int aflag) -{ -} - void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr) { assert(0); } -void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param) -{ -} - void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { } - -void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, - uint32_t next_eip_addend) -{ -} From patchwork Wed May 19 18:30:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442504 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1601555jac; Wed, 19 May 2021 12:01:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqTpTmNB8L/A+Zxv8iQipeTvMJ4Gsc4uWAEE34fCBSHdmD26DhdCQSF6o3E5XV6tnwSJo7 X-Received: by 2002:a05:6e02:f10:: with SMTP id x16mr480008ilj.65.1621450912787; Wed, 19 May 2021 12:01:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450912; cv=none; d=google.com; s=arc-20160816; b=S7/EARN+0CUr9DWsuKzpo/PBNcGr3Ot7EMFPE/Nc4z6uUy3UBCYRjewtB/FjxYtnkY nTs/JVhPwcidiech7JoSfEvxiK3y6b97dBBPCptaUNzrLNtJrSrsImOpjaIq3uUCZ0jD Mw3UM8DZCherBOhwIn9yKOYiMv1jbIjGDEllBiC41QsMfFbuX7I3T+O7IfAVOISK1zKE g1ZL+iF4SyThTn1Bto48E0QXvz6rvmPFEfaNCVv2YFU751TEz0PplELu+qU0wODCxfrx EZ+LtbuKdYbGYf4oH9dQZGqJKYzm1ARZY089SzqrXYKrK8VmVec+beFuNKlgl16HlGsC rMcg== ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-35-richard.henderson@linaro.org> --- target/i386/helper.h | 18 +++++++++--------- target/i386/tcg/bpt_helper.c | 2 +- target/i386/tcg/excp_helper.c | 18 ++++++++++-------- target/i386/tcg/misc_helper.c | 14 +++++++------- target/i386/tcg/translate.c | 3 ++- 5 files changed, 29 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index d0f7f07c6c..f794d1c7c7 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -60,14 +60,14 @@ DEF_HELPER_2(sysexit, void, env, int) DEF_HELPER_2(syscall, void, env, int) DEF_HELPER_2(sysret, void, env, int) #endif -DEF_HELPER_2(hlt, void, env, int) -DEF_HELPER_2(monitor, void, env, tl) -DEF_HELPER_2(mwait, void, env, int) -DEF_HELPER_2(pause, void, env, int) -DEF_HELPER_1(debug, void, env) +DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(reset_rf, void, env) -DEF_HELPER_3(raise_interrupt, void, env, int, int) -DEF_HELPER_2(raise_exception, void, env, int) +DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_1(cli, void, env) DEF_HELPER_1(sti, void, env) DEF_HELPER_1(clac, void, env) @@ -86,12 +86,12 @@ DEF_HELPER_2(cmpxchg8b, void, env, tl) DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) #endif -DEF_HELPER_1(single_step, void, env) +DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) -DEF_HELPER_1(rdpmc, void, env) +DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rdmsr, void, env) DEF_HELPER_1(wrmsr, void, env) diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index fb2a65ac9c..83cd89581e 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -22,7 +22,7 @@ #include "exec/helper-proto.h" #include "helper-tcg.h" -void helper_single_step(CPUX86State *env) +void QEMU_NORETURN helper_single_step(CPUX86State *env) { #ifndef CONFIG_USER_ONLY check_hw_breakpoints(env, true); diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 0183f3932e..bdae887d0a 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -25,12 +25,13 @@ #include "exec/helper-proto.h" #include "helper-tcg.h" -void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend) +void QEMU_NORETURN helper_raise_interrupt(CPUX86State *env, int intno, + int next_eip_addend) { raise_interrupt(env, intno, 1, 0, next_eip_addend); } -void helper_raise_exception(CPUX86State *env, int exception_index) +void QEMU_NORETURN helper_raise_exception(CPUX86State *env, int exception_index) { raise_exception(env, exception_index); } @@ -116,24 +117,25 @@ void QEMU_NORETURN raise_interrupt(CPUX86State *env, int intno, int is_int, raise_interrupt2(env, intno, is_int, error_code, next_eip_addend, 0); } -void raise_exception_err(CPUX86State *env, int exception_index, - int error_code) +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, + int error_code) { raise_interrupt2(env, exception_index, 0, error_code, 0, 0); } -void raise_exception_err_ra(CPUX86State *env, int exception_index, - int error_code, uintptr_t retaddr) +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, + int error_code, uintptr_t retaddr) { raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr); } -void raise_exception(CPUX86State *env, int exception_index) +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index) { raise_interrupt2(env, exception_index, 0, 0, 0, 0); } -void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr) +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, + uintptr_t retaddr) { raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index a30379283e..0e9a4f0bfc 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -96,7 +96,7 @@ void helper_rdtscp(CPUX86State *env) env->regs[R_ECX] = (uint32_t)(env->tsc_aux); } -void helper_rdpmc(CPUX86State *env) +void QEMU_NORETURN helper_rdpmc(CPUX86State *env) { if (((env->cr[4] & CR4_PCE_MASK) == 0 ) && ((env->hflags & HF_CPL_MASK) != 0)) { @@ -109,7 +109,7 @@ void helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } -static void do_pause(X86CPU *cpu) +static QEMU_NORETURN void do_pause(X86CPU *cpu) { CPUState *cs = CPU(cpu); @@ -118,7 +118,7 @@ static void do_pause(X86CPU *cpu) cpu_loop_exit(cs); } -static void do_hlt(X86CPU *cpu) +static QEMU_NORETURN void do_hlt(X86CPU *cpu) { CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; @@ -129,7 +129,7 @@ static void do_hlt(X86CPU *cpu) cpu_loop_exit(cs); } -void helper_hlt(CPUX86State *env, int next_eip_addend) +void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) { X86CPU *cpu = env_archcpu(env); @@ -148,7 +148,7 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); } -void helper_mwait(CPUX86State *env, int next_eip_addend) +void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) { CPUState *cs = env_cpu(env); X86CPU *cpu = env_archcpu(env); @@ -167,7 +167,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) } } -void helper_pause(CPUX86State *env, int next_eip_addend) +void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) { X86CPU *cpu = env_archcpu(env); @@ -177,7 +177,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend) do_pause(cpu); } -void helper_debug(CPUX86State *env) +void QEMU_NORETURN helper_debug(CPUX86State *env) { CPUState *cs = env_cpu(env); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b2a997fb30..c1d4d58c61 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7282,6 +7282,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_rdpmc(cpu_env); + s->base.is_jmp = DISAS_NORETURN; break; case 0x134: /* sysenter */ /* For Intel SYSENTER is valid on 64-bit */ @@ -7443,7 +7444,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); - gen_eob(s); + s->base.is_jmp = DISAS_NORETURN; break; case 0xca: /* clac */ From patchwork Wed May 19 18:30:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442495 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1595262jac; Wed, 19 May 2021 11:53:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0y64OCqso2qRvfUOfihOaLWWa9AVT58WuW4e2D1c4gyrc6NqCWlAeLcTLhj+tNCym2YFp X-Received: by 2002:a02:a19c:: with SMTP id n28mr491651jah.117.1621450425297; Wed, 19 May 2021 11:53:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450425; cv=none; d=google.com; s=arc-20160816; b=iI++WrMuSfOS40ybKKQcrDToxHFmnuvgFVoMHHZC49fEWoStUp10gUNmy1TjOAkuAA vYR+ytn6QGzOmnj1VMzFB8U6rj3+KtNeDEXP37h7qxRYTTaLiAkO1H0FcQ8vXvmnYfOA GJ8mQvI+5jGKAiEpYplTrN0Th4fR0ZyEIUFeytjV2ML5oRR2aSnhMPw/L4+sD2W/elCn EMSBPRSgNsfhx8HpLgkR53CyHK8wmIwBkQFYsYjZ17WGT8ARVJlLdZDKqL1E0b/tav6C JNJLEq6GinqomuQokyTwEAE4oXvrEr2HScvLEFu8VI7yP/EcsurQso+XiZsB2NNDAsZK LRKA== ARC-Message-Signature: i=1; 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The function sets is_jmp, so we can eliminate a second setting. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-36-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c1d4d58c61..36e38ebebf 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2614,10 +2614,10 @@ static void gen_interrupt(DisasContext *s, int intno, s->base.is_jmp = DISAS_NORETURN; } -static void gen_debug(DisasContext *s, target_ulong cur_eip) +static void gen_debug(DisasContext *s) { gen_update_cc_op(s); - gen_jmp_im(s, cur_eip); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_debug(cpu_env); s->base.is_jmp = DISAS_NORETURN; } @@ -7152,7 +7152,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); - gen_debug(s, pc_start - s->cs_base); + gen_debug(s); break; #endif case 0xfa: /* cli */ @@ -8586,8 +8586,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, /* If RF is set, suppress an internally generated breakpoint. */ int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; if (bp->flags & flags) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - dc->base.is_jmp = DISAS_NORETURN; + gen_debug(dc); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that From patchwork Wed May 19 18:30:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442498 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1597756jac; Wed, 19 May 2021 11:56:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWi8sThjGVk3Tz2ZxPMX5ERrtDLNZuBoK0uZrXTMBioLI0wdqDp17XIk3R6sNMEGa0AKtL X-Received: by 2002:a05:6e02:19ce:: with SMTP id r14mr583387ill.4.1621450614853; Wed, 19 May 2021 11:56:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450614; cv=none; d=google.com; s=arc-20160816; b=sZqElYbBTW8Gksyk9GBdZnNRS4YgNIfpW9QlRtdGFTRIfX6BskPCi0mthCMtzi+h69 rZ8LkW5DqD6Da0CMhDMLdCc5rRYUc1CGQTdVDOormtNyZyfCJu2RgXC1anlJPsM7guTS DAQDrFr/+ZUPaadkjSz1a7PePUA38XE07bKu8kyulyrwurFBuePISqx6yeNAGt11L7z9 3GPmV6VYW7lJFV8Yo3LH9ZxUFgja2gY/6bOzeocWJJ3XZXLWpawHxVqbXf7sWEuOmnwL NtpFTY4OaixT9B7QLcI+WLvHPimycZyblWDk4axmzRZFYg8C5Dt99HPx/XvjKwV+EvrS P7YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=o+bSpPqvUS5hXLbtWM0XfAjDH/PGAEYXlkUYshXGyEo=; b=Q59I7n+aER2apiUAw1LIQ3LrDB9fA2lOaS29zWFKHMvmH6kMclBRebm2LtWixA1R+w 8skkTco0o+zvFz28kY9RgD3s5am94JYzw0QBCrCcxxKpsvFLJfHb79wkCY29hqLMRqc5 SppF7xpzrVuk+QoKlH7G+3x0VwR53I1NHP/UU42i6VzF9HL+JM13PEwoOvA5a0Qq9g6m ybXAdrMogScgeC9OL/TuMwHkNBMQ6Gg1QrUZswZJu/q9fFKrY+7bl/FMI694NcxaSkU2 iQv1IicQwCtY62tv2Rw+U7O1RarY5fmGLGOMd3GzA4AaJSwTXvUeRaj38DuxmYu+IcW6 fSEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mj9CiSl3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fold gen_svm_check_intercept_param into gen_svm_check_intercept. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-37-richard.henderson@linaro.org> --- target/i386/helper.h | 2 +- target/i386/tcg/sysemu/svm_helper.c | 5 ++--- target/i386/tcg/translate.c | 16 ++++------------ 3 files changed, 7 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index f794d1c7c7..86484a4ec4 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -107,7 +107,7 @@ DEF_HELPER_2(inl, tl, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) -DEF_HELPER_3(svm_check_intercept_param, void, env, i32, i64) +DEF_HELPER_2(svm_check_intercept, void, env, i32) DEF_HELPER_4(svm_check_io, void, env, i32, i32, i32) DEF_HELPER_3(vmrun, void, env, int, int) DEF_HELPER_1(vmmcall, void, env) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 79c73d67af..b431016e72 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -506,10 +506,9 @@ void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, } } -void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param) +void helper_svm_check_intercept(CPUX86State *env, uint32_t type) { - cpu_svm_check_intercept_param(env, type, param, GETPC()); + cpu_svm_check_intercept_param(env, type, 0, GETPC()); } void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 36e38ebebf..ad2e6cdd8c 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -197,7 +197,7 @@ STUB_HELPER(clgi, TCGv_env env) STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) -STUB_HELPER(svm_check_intercept_param, TCGv_env env, TCGv_i32 t, TCGv_i64 p) +STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) STUB_HELPER(svm_check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 p, TCGv_i32 a) STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(vmmcall, TCGv_env env) @@ -2423,9 +2423,8 @@ static inline int svm_is_rep(int prefixes) return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); } -static inline void -gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, - uint32_t type, uint64_t param) +static void gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, + uint32_t type) { /* no SVM activated; fast case */ if (likely(!GUEST(s))) { @@ -2433,14 +2432,7 @@ gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, } gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), - tcg_const_i64(param)); -} - -static inline void -gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) -{ - gen_svm_check_intercept_param(s, pc_start, type, 0); + gen_helper_svm_check_intercept(cpu_env, tcg_constant_i32(type)); } static inline void gen_stack_update(DisasContext *s, int addend) From patchwork Wed May 19 18:30:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442497 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1597135jac; Wed, 19 May 2021 11:56:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykJoXFogFLDPRab3uLqjy8hS4fOiwygps8CvdxfXis/V4RQiIC8x/NOp2VWtLI0wrmKkD+ X-Received: by 2002:a02:92cc:: with SMTP id c12mr544190jah.30.1621450573228; Wed, 19 May 2021 11:56:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450573; cv=none; d=google.com; s=arc-20160816; b=QLHpwAuXoG6jPHPLAFFUJuc3cB8jG51p6i66cOH1xYGhPnSec/j6s4fqTSbxXj0E1I RoYIYxNL5lcilyUmcvc4v9YXFAgqP+fbHqBAvDxF1SVhy99L+qHkzMch9p6WyWM0m5b7 wwUG3yw71qAYHriTsTWCov9ldrx1AeADZcBHy38EEy1l1Gpeg/fptYw4LD1+hVRj49v+ kIDsKWN1VyiupnBxFXDHSzRVEXi73DN2Ihxv9be+Rxf7ZDlAfCyDBWB43ROIi6+zOLMB pAY68Rg5o7aDzNWdTG/G693KyvO6dE7gi0mUZ7NgAR1BLo582sdKzszgEQPJtgta094M jupQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wGPkMnHncYPRjpbgxeSiThUfzvY8NqHBArvTydIYpa0=; b=Uv45rL1fyOV4geOG7tHGEgZFu9op+mhdxAW/ZCSMTTPwjrbNmdZR5dvq3VJBL7ro8M hMG7uGSWPJic54ukVaKNx+gW9t7zgix5Qh+98WNgB9oaUX6kivxu9CdFFEpdZRb4Uarw 2If7E84dz7JDxAs3WoAmn3Ck4XKaYQqfHaKpzrd2xnd3jmRTBbfM46RkTpPdVzNUk2iN zKA9CnYqbKxbi0Bqc/mRo8tWekcIb11y0pmaTutpzoeP83ZX7uHGXaW09ipSWXmKbN3W bFnk0aN6JLSe4yXvJcX6pvXIyt/Nlwlxlg7ud+B4SeQtgSljMyk5FBFbQCo7bwPMDUB8 0sEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VxCbeBaD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s6si129186jao.56.2021.05.19.11.56.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:56:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VxCbeBaD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRMa-0005nS-LW for patch@linaro.org; Wed, 19 May 2021 14:56:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyx-0004hp-E3 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:47 -0400 Received: from mail-oo1-xc33.google.com ([2607:f8b0:4864:20::c33]:45967) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyh-0005q9-49 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:46 -0400 Received: by mail-oo1-xc33.google.com with SMTP id s1-20020a4ac1010000b02901cfd9170ce2so3212007oop.12 for ; Wed, 19 May 2021 11:31:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wGPkMnHncYPRjpbgxeSiThUfzvY8NqHBArvTydIYpa0=; b=VxCbeBaDAVJea+pkF4JkaDCYaqpgeCJBA3Aq9kzqV+D4O6Fa0CNzjW0x+7GLOHBF6P T3HWED9YR0n2qoBxHenV69cAKCFXvLHFBEkpvq2oIt4c58A3qQehRvvrmFd+YY9P/SIo 4ohoCOQyDfjadtM/miTvxt8ciDpFiw9wdULfK6ND7P3qupLwvihGeRvY9bGfALwfaWnN grVqXOxUk5rVHZQ6VQE4z6K9yc1qLIqdVolsHM9Rp3QM6/qfKo4HAH88YFIrPio88HO9 HOFua9bFMcABcd2Zz9Ls42XGxdm9YYTtQmON+GlDe700CM9jD3JzgS5IumJXxrYgEW/8 blnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wGPkMnHncYPRjpbgxeSiThUfzvY8NqHBArvTydIYpa0=; b=UVUYugKbfPSDkCEDocurHwiAkwefahZR1ksHlzgOGy0w+efEqlQ8h7wKD0ai9AE06C OmCQhOhP59qGktV1i01JH+zLCXxA6Nw+7eIQb+U6uhfgoWyiPK+wDWEejtJxe/Vqwct0 La/lGmf2BcB+qzTUTrz1RJOWRqbnhf5gdcd2rXt/c68VbcfkpAe8GCv316Gbr0D5E9VA UAX1II1Q9dk3hvh3WAeP40ILeNgAiU96uzRIU0EFUJjXIJoxXJFuyJsh6MArJU+1iRRr LCRWJ1BXZQgSjMNvZjsx7UNFHMUdmphphTT4lCaMPyyQRUCH64hIcUotDo8JBj824mWY QG/Q== X-Gm-Message-State: AOAM533kuKo0p72Mc9fjz0hHw+jvzfcawhlmpipIUUx6Ibn++QNL0DW5 hZdveqAIH52JOE2NLkOU4W8kzwZKaZb+Yfk1 X-Received: by 2002:a4a:49c8:: with SMTP id z191mr553771ooa.62.1621449088759; Wed, 19 May 2021 11:31:28 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 37/50] target/i386: Remove pc_start argument to gen_svm_check_intercept Date: Wed, 19 May 2021 13:30:37 -0500 Message-Id: <20210519183050.875453-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When exiting helper_svm_check_intercept via exception, cpu_vmexit calls cpu_restore_state, which will recover eip and cc_op via unwind. Therefore we do not need to store eip or cc_op before the call. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-38-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 45 +++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ad2e6cdd8c..3844c0342e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2423,15 +2423,12 @@ static inline int svm_is_rep(int prefixes) return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); } -static void gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, - uint32_t type) +static void gen_svm_check_intercept(DisasContext *s, uint32_t type) { /* no SVM activated; fast case */ if (likely(!GUEST(s))) { return; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); gen_helper_svm_check_intercept(cpu_env, tcg_constant_i32(type)); } @@ -6639,7 +6636,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) val = 0; goto do_lret; case 0xcf: /* iret */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); + gen_svm_check_intercept(s, SVM_EXIT_IRET); if (!PE(s) || VM86(s)) { /* real mode or vm86 mode */ if (!check_vm86_iopl(s)) { @@ -6761,7 +6758,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /************************/ /* flags */ case 0x9c: /* pushf */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); + gen_svm_check_intercept(s, SVM_EXIT_PUSHF); if (check_vm86_iopl(s)) { gen_update_cc_op(s); gen_helper_read_eflags(s->T0, cpu_env); @@ -6769,7 +6766,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } break; case 0x9d: /* popf */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); + gen_svm_check_intercept(s, SVM_EXIT_POPF); if (check_vm86_iopl(s)) { ot = gen_pop_T0(s); if (CPL(s) == 0) { @@ -7143,7 +7140,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); + gen_svm_check_intercept(s, SVM_EXIT_ICEBP); gen_debug(s); break; #endif @@ -7347,7 +7344,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0: /* sldt */ if (!PE(s) || VM86(s)) goto illegal_op; - gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); + gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, ldt.selector)); ot = mod == 3 ? dflag : MO_16; @@ -7357,7 +7354,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lldt(cpu_env, s->tmp2_i32); @@ -7366,7 +7363,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 1: /* str */ if (!PE(s) || VM86(s)) goto illegal_op; - gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); + gen_svm_check_intercept(s, SVM_EXIT_TR_READ); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, tr.selector)); ot = mod == 3 ? dflag : MO_16; @@ -7376,7 +7373,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ltr(cpu_env, s->tmp2_i32); @@ -7404,7 +7401,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); switch (modrm) { CASE_MODRM_MEM_OP(0): /* sgdt */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); + gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.limit)); @@ -7460,7 +7457,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_MEM_OP(1): /* sidt */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); + gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.limit)); gen_op_st_v(s, MO_16, s->T0, s->A0); @@ -7580,7 +7577,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) || !PE(s)) { goto illegal_op; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT); + gen_svm_check_intercept(s, SVM_EXIT_SKINIT); /* If not intercepted, not implemented -- raise #UD. */ goto illegal_op; @@ -7600,7 +7597,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_GDTR_WRITE); gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, MO_16, s->T1, s->A0); gen_add_A0_im(s, 2); @@ -7616,7 +7613,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_WRITE); + gen_svm_check_intercept(s, SVM_EXIT_IDTR_WRITE); gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, MO_16, s->T1, s->A0); gen_add_A0_im(s, 2); @@ -7629,7 +7626,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; CASE_MODRM_OP(4): /* smsw */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); + gen_svm_check_intercept(s, SVM_EXIT_READ_CR0); tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0])); /* * In 32-bit mode, the higher 16 bits of the destination @@ -7661,7 +7658,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); + gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_helper_lmsw(cpu_env, s->T0); gen_jmp_im(s, s->pc - s->cs_base); @@ -7718,7 +7715,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x108: /* invd */ case 0x109: /* wbinvd */ if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); + gen_svm_check_intercept(s, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ } break; @@ -8108,14 +8105,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (b & 2) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); + gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); tcg_gen_movi_i32(s->tmp2_i32, reg); gen_helper_set_dr(cpu_env, s->tmp2_i32, s->T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); } else { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); + gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg); tcg_gen_movi_i32(s->tmp2_i32, reg); gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32); gen_op_mov_reg_v(s, ot, rm, s->T0); @@ -8124,7 +8121,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x106: /* clts */ if (check_cpl0(s)) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); + gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); /* abort block because static cpu state changed */ gen_jmp_im(s, s->pc - s->cs_base); @@ -8351,7 +8348,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_nop_modrm(env, s, modrm); break; case 0x1aa: /* rsm */ - gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); + gen_svm_check_intercept(s, SVM_EXIT_RSM); if (!(s->flags & HF_SMM_MASK)) goto illegal_op; #ifdef CONFIG_USER_ONLY From patchwork Wed May 19 18:30:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442501 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1599015jac; Wed, 19 May 2021 11:58:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgWVPuIAOnchQ79OYZJddmqKq+MbUuFT8FWEzDfzstoMe+93kN84LBvv1qXD+5yWSobpTT X-Received: by 2002:a05:6e02:1067:: with SMTP id q7mr501849ilj.75.1621450725376; Wed, 19 May 2021 11:58:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450725; cv=none; d=google.com; s=arc-20160816; b=ZmGtdC1Uz/AhgY1U/Qa1S1WFVG20dJJfQ/lOlo3Qv/o64yFnHmz3GoL5hmfcfhjIcS ScVPcD7u1Kck6gle/xu74cJZ//OxqHhA4RJIUMJqm8If866e9ipXE1dyv+lW0uIBdksV qe4mH3ePPskjDYUG1e4T/nbOPFYgNfL/+FMU3kg9TjqGjSQe+ymz2iHxx1vfLmsFgZEE O4BD06zmDiZb3dsyfj9txYVOmgpsj/G3GB+Gbj4IP96oZ+mmGj/ONuqUW1ns+t7zTQFH qITeeN6KsNDfoFGheKuXJAHrPPnYdSSWfg/Mx2wednTUiEcex2vi/SehYMAXnGKaGLFb 3JoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iPj+icuYk1Db82ELWhN0FuTsJx+Xd+A4Cv7yhnX7+A8=; b=T1jGNt2aFh/iPoGzxZduQ5jrz0GvWbpdMHm4ElmVgVc9DTnwIcYMXQ+c1YjsCCTozD P0jXlbtusw9+NjntRh0t4EAWhl4a2YmQUWf4XCbNde1WUbeRuqyFW9CDlc6MPnao1ZL+ /vO6/h9NzH09HRPPb0KSlwxsUH5B8StQkos3rWO6bKQ6QB0Q4gQDp4lvJKg5P0PTUm6V epVS7iAwTepwRPvR/1GpbP1K7SLzh9jx1JeUxLZoCdl/PZvaWeQ8bUd7McMSdGJrRGjx RgIao0ayPFmJl6SHyJ2OsqlmUEfR73YtoPSmA+LH3yn3ADrI8jucD807mvzfgkjpBop/ CMhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X2b32TWZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g11si550605ilf.108.2021.05.19.11.58.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:58:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X2b32TWZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRP2-0004NQ-Qz for patch@linaro.org; Wed, 19 May 2021 14:58:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyw-0004f6-Ih for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:46 -0400 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]:42738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyh-0005qb-4k for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:46 -0400 Received: by mail-ot1-x32e.google.com with SMTP id g7-20020a9d12870000b0290328b1342b73so4776826otg.9 for ; Wed, 19 May 2021 11:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iPj+icuYk1Db82ELWhN0FuTsJx+Xd+A4Cv7yhnX7+A8=; b=X2b32TWZOWujfKRu9u11k3kJKGad/2wEHUu30Y8D5LkyLX4DnD9yefPsnbJyMq2jyz Ipz9yBM5v+39pQeXWF53Sf+XMLMSDkPajJMPB1gxmD+HqbwXKGVLSy70CvsYzUfrk1vb ckv1M+V0uJK7R3B77Ii9p1HrUBWSQmixlVAJEU/MtUX6kue1GpHTNZVMjSeIWzlTfM58 ip1Pczf4w1gKiuigjQJqG33o2aZ/adbHChtaZyW4gq01YHkxwhZvUYWCzzxXjFs2xv/L YU6E6DvRbb3qvo3FIct2QZToUwkJGQYEYTHDssiXkd0lMecTX7ypGTphqyns9zE7wvml l0PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iPj+icuYk1Db82ELWhN0FuTsJx+Xd+A4Cv7yhnX7+A8=; b=oC4Wnoczn8dDFOcRfHapWJmXyvrEolZa+ky6SjhKkFvD/zN2or/AuqywhAoDmDMtwE r6Uq+S0CIa2vgsA0+gY1c7kSazsZ/hit4IDBy1vX7s6lQNsJbFIwFJ7+aY2FjkD57ePt av8y5N9xOpRAPIRj8hcF0xU/tuWa2ienNzAXOqSKztlT4al8Ir6GIcNYyGegfPI9Yh7x 31Dk6YAQmbi6HhPZWVbcJ8LzCb0xuzChoQMlPX+JS5J5wmovmTNDbxBY8IaCx+uYWVh2 YG+HuCEklgeNg6c8XE6YuYQb65vZujuVpEMCrJ27dxTovXt+AkPrTdAkTISjeSXNT9wY uKMA== X-Gm-Message-State: AOAM53097wpkcK9tyj4VWl53ooiBnd6PBEJg/5ZS+M7qxRC039zaCh/h 8RPmjl6S9a+vh8PY0f+QsWtuCXoB5l5To5Nl X-Received: by 2002:a9d:5a12:: with SMTP id v18mr636651oth.306.1621449089699; Wed, 19 May 2021 11:31:29 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 38/50] target/i386: Remove user stub for cpu_vmexit Date: Wed, 19 May 2021 13:30:38 -0500 Message-Id: <20210519183050.875453-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is only called from tcg/sysemu/. There is no need for a stub in tcg/user/. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-39-richard.henderson@linaro.org> --- target/i386/tcg/helper-tcg.h | 4 +++- target/i386/tcg/user/svm_stubs.c | 6 ------ 2 files changed, 3 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 97fb7a226a..85a8b0ebd6 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -77,10 +77,12 @@ extern const uint8_t parity_table[256]; /* misc_helper.c */ void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask); -/* svm_helper.c */ +/* sysemu/svm_helper.c */ +#ifndef CONFIG_USER_ONLY void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr); void do_vmexit(CPUX86State *env); +#endif /* seg_helper.c */ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c index 48a43bdcea..db818f89a8 100644 --- a/target/i386/tcg/user/svm_stubs.c +++ b/target/i386/tcg/user/svm_stubs.c @@ -22,12 +22,6 @@ #include "exec/helper-proto.h" #include "tcg/helper-tcg.h" -void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, - uintptr_t retaddr) -{ - assert(0); -} - void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { From patchwork Wed May 19 18:30:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442493 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1594916jac; Wed, 19 May 2021 11:53:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJya3g602QKlK8O1b8ZcLg/TtgcX7331Ryr/TlXUJnf3UYkDEQvokYpU9LpTVKgqV5DAe1Ho X-Received: by 2002:a05:6602:2002:: with SMTP id y2mr1000671iod.70.1621450398126; Wed, 19 May 2021 11:53:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450398; cv=none; d=google.com; s=arc-20160816; b=WqzWgWXN1ai9lVES/RvVD7lGEVAZasRarDnd8VEMYBXpyeuVezCZ9ZLZoR53yTaCgZ wWTTofF/Y82L/Jfio8Cn1x0svxVDhB+F1sukOe/Z3KNKpKJE/X7MzjiWdA3lSGvmDkOC Zn8YGEOEN0zefaq+jfycrkyj5sVz7EFtBLl66xLXJFB4WJq7/jcU8+41oogl+A/sBYjZ 5FkAmjzIR8e69QLNtBY9VUiaxIr7bniTmOa8MgZFqO9ShBWzteZm6j3uY9d4GU2PXaW/ r0ikWeHM/Zwyr+BAluyiaOXAkpurAUrqWjGTkAZAMAXgpNmTH8NlIWPJFWXBGuUcM1KI /z+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uACQlfQ1L4lJXOLq7mztjHzJAGN3TYb66yJkvd3rBv4=; b=WEaBJyYy02f68DXuNRzsMiUBLEOdf0uZIYSvywFMl3WvKMtV3CuNVzF0xwt2kss+Mc 2udwnoPaqlyWX+nYlJmlWfPAfJFz/VPSw8hRWN9PZuhIXalpoJHtwfSYhUp198QpTsYZ 8DHSBBTYgaBRAGxnXr/UKk0QsSJht+jA1vf/wWe0UJ4DTBVcPxfKdi4wDCHmD9oqC9RF 4lCR5vailzVeKHroSREBvACoF0yty57LGJO6z3xWIk8AyKody2l1iVm17+JVZdkFdZ2E U4zsqPy/Hs3temm6kaHuJD6wajjnImQoLkcKwImiavIxRADn8clmbqXWutjx1yvq95XF G0aQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P0wCPtX+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b15si155277jat.59.2021.05.19.11.53.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:53:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P0wCPtX+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRJl-0008TI-Fi for patch@linaro.org; Wed, 19 May 2021 14:53:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQyv-0004cu-W0 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:46 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]:37413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljQyh-0005ql-On for qemu-devel@nongnu.org; Wed, 19 May 2021 14:31:45 -0400 Received: by mail-ot1-x32c.google.com with SMTP id v19-20020a0568301413b0290304f00e3d88so12620353otp.4 for ; Wed, 19 May 2021 11:31:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uACQlfQ1L4lJXOLq7mztjHzJAGN3TYb66yJkvd3rBv4=; b=P0wCPtX+ts8CT7tpL5nc1xWLPnbkjkgc6quRJQXHgZI85puFlJq7LzTYR3XPgvQv10 CNselL13FORw5hAl1EMFp+EmvBrF+zcaKTnHhFqRirHmzVRqWesbl1aHGEjjbvKP/Vsn SE6nYHTnv4CK2/utRFC5rE+66ibqbqiGAWbQUeGcDw7ORihlD3XHoadoLdFxKaZ7MsKS Tl8lIDaznEftfiYuxcfNvNLaNG77eUbNvhn48doicZtYOcUy4qDwPIt7FMPBX6LI/iTl KkwGyok/O+Ge5yCGAN7vDdVohuxNmYvEIvC/xjPGGE9Qyc4EyLXfkKLp69+fxz/6QWN8 V+qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uACQlfQ1L4lJXOLq7mztjHzJAGN3TYb66yJkvd3rBv4=; b=rdfBGpxOBxrJIDog5mwkCBsnbAUc1VrI7XJrW6cjaZNzF/HENdyXTVx2XM/76P/Zat mSAaGBCWDGHg0hvIWJcW4X5usjtDyNNbJcHwz+E+27iQRfJ27pOyw+5nwfV8o99JmCTh v9RN35s8aEGLkrwITpMFXgyO987Spsgi/fYdwg5pvg0ZDQvpeNvB22+CF4JzPs6nSu/Y ALA/FabOMW98Smu+dqCZk0NKA6wj2iO9iW2DhR6cnG4D4wCA/7gq79R+ooahh0jaEEIU u5P5gOvnGM/q8H/fdEFpMaNnYvke2dFjKnzLN6LcMklggz/QPKDS7L7B1pD8OXkpGP4C uDUQ== X-Gm-Message-State: AOAM532EnYUPREPNehJ/cWWLaS30L8gbO6vUz2tjck2YUnDmK3gubE2N cLKgkco2AP4/xHTgxobNFFQC5vUyzwneNIoH X-Received: by 2002:a9d:be2:: with SMTP id 89mr633099oth.269.1621449090650; Wed, 19 May 2021 11:31:30 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id l9sm28428oou.43.2021.05.19.11.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:31:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 39/50] target/i386: Cleanup read_crN, write_crN, lmsw Date: Wed, 19 May 2021 13:30:39 -0500 Message-Id: <20210519183050.875453-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pull the svm intercept check into the translator. Pull the entire implementation of lmsw into the translator. Push the check for CR8LEG into the regno validation switch. Unify the gen_io_start check between read/write. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson Message-Id: <20210514151342.384376-40-richard.henderson@linaro.org> --- target/i386/helper.h | 5 +- target/i386/tcg/misc_helper.c | 8 --- target/i386/tcg/sysemu/misc_helper.c | 2 - target/i386/tcg/translate.c | 97 +++++++++++++++------------- 4 files changed, 54 insertions(+), 58 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 86484a4ec4..ebfaca66dd 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -42,9 +42,8 @@ DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl) DEF_HELPER_2(iret_real, void, env, int) DEF_HELPER_3(iret_protected, void, env, int, int) DEF_HELPER_3(lret_protected, void, env, int, int) -DEF_HELPER_2(read_crN, tl, env, int) -DEF_HELPER_3(write_crN, void, env, int, tl) -DEF_HELPER_2(lmsw, void, env, tl) +DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int) +DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl) DEF_HELPER_1(clts, void, env) #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 0e9a4f0bfc..931dbd9db0 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -60,14 +60,6 @@ void helper_cpuid(CPUX86State *env) env->regs[R_EDX] = edx; } -void helper_lmsw(CPUX86State *env, target_ulong t0) -{ - /* only 4 lower bits of CR0 are modified. PE cannot be set to zero - if already set to one. */ - t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); - helper_write_crN(env, 0, t0); -} - void helper_invlpg(CPUX86State *env, target_ulong addr) { X86CPU *cpu = env_archcpu(env); diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 66e7939537..c7381ef7e8 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -65,7 +65,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) { target_ulong val; - cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC()); switch (reg) { default: val = env->cr[reg]; @@ -83,7 +82,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { - cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC()); switch (reg) { case 0: cpu_x86_update_cr0(env, t0); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 3844c0342e..14a44a00ca 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7654,13 +7654,22 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64); break; + CASE_MODRM_OP(6): /* lmsw */ if (!check_cpl0(s)) { break; } gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); - gen_helper_lmsw(cpu_env, s->T0); + /* + * Only the 4 lower bits of CR0 are modified. + * PE cannot be set to zero if already set to one. + */ + tcg_gen_ld_tl(s->T1, cpu_env, offsetof(CPUX86State, cr[0])); + tcg_gen_andi_tl(s->T0, s->T0, 0xf); + tcg_gen_andi_tl(s->T1, s->T1, ~0xe); + tcg_gen_or_tl(s->T0, s->T0, s->T1); + gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); break; @@ -8034,58 +8043,56 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) modrm = x86_ldub_code(env, s); gen_nop_modrm(env, s, modrm); break; + case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ - if (check_cpl0(s)) { - modrm = x86_ldub_code(env, s); - /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). - * AMD documentation (24594.pdf) and testing of - * intel 386 and 486 processors all show that the mod bits - * are assumed to be 1's, regardless of actual values. - */ - rm = (modrm & 7) | REX_B(s); - reg = ((modrm >> 3) & 7) | REX_R(s); - if (CODE64(s)) - ot = MO_64; - else - ot = MO_32; - if ((prefixes & PREFIX_LOCK) && (reg == 0) && + if (!check_cpl0(s)) { + break; + } + modrm = x86_ldub_code(env, s); + /* + * Ignore the mod bits (assume (modrm&0xc0)==0xc0). + * AMD documentation (24594.pdf) and testing of Intel 386 and 486 + * processors all show that the mod bits are assumed to be 1's, + * regardless of actual values. + */ + rm = (modrm & 7) | REX_B(s); + reg = ((modrm >> 3) & 7) | REX_R(s); + switch (reg) { + case 0: + if ((prefixes & PREFIX_LOCK) && (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { reg = 8; } - switch(reg) { - case 0: - case 2: - case 3: - case 4: - case 8: - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - if (b & 2) { - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_op_mov_v_reg(s, ot, s->T0, rm); - gen_helper_write_crN(cpu_env, tcg_const_i32(reg), - s->T0); - gen_jmp_im(s, s->pc - s->cs_base); - gen_eob(s); - } else { - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_read_crN(s->T0, cpu_env, tcg_const_i32(reg)); - gen_op_mov_reg_v(s, ot, rm, s->T0); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } - } - break; - default: - goto unknown_op; + break; + case 2: + case 3: + case 4: + break; + default: + goto unknown_op; + } + ot = (CODE64(s) ? MO_64 : MO_32); + + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + if (b & 2) { + gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); + gen_op_mov_v_reg(s, ot, s->T0, rm); + gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0); + gen_jmp_im(s, s->pc - s->cs_base); + gen_eob(s); + } else { + gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); + gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg)); + gen_op_mov_reg_v(s, ot, rm, s->T0); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_jmp(s, s->pc - s->cs_base); } } break; + case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (check_cpl0(s)) { From patchwork Wed May 19 18:30:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442503 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1600106jac; Wed, 19 May 2021 12:00:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzi8/N6xPtAizklEyToI2L4yl7sJPeW64oZNsXVSauYmpvBFxCEEl4NElW76668NE8exVuH X-Received: by 2002:a9f:3d8e:: with SMTP id c14mr1235308uai.56.1621450810531; Wed, 19 May 2021 12:00:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450810; cv=none; d=google.com; s=arc-20160816; b=sRiWVFQgV1EdAAzaG/T39sTKVQzN9J/iEL0eC6QfdA6HtoXlw5iVGXXV4JcUwf0CCT roLYgAtvgVLMiKOu0PHdX9v+8K6yQWNjKSBbk2DP/8RWkn37EoqZ2WQBATIhtNryMzq2 f3lgYH5Q/PYayYmS8jlyIRbXS2kr4aRLDZN8//4zgMuVNQ/gIagKVHaW9jHJkUphTSY9 yberUWgOrCX3Uh1IqcqVBnial3JmUUH+pjjXBhiX7mMO6qY3ocxGIj5sZ0xdLWFKm/b1 UCpQ6v9QpEQxTe/M0mwLuHtikIV6AsO20gUF7cupxjDbes3sShNn7EpoXHurlvbTebk5 hmFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MxaVFDhOR/2P7mRJMj9Ww3Gxrm+V2fvm6YpN2MZVwIE=; b=WcxTrQ8AiEVsSbB6Mt+8reGbfpm9JHifPzjq0uu+ddteNlQ+WvZjRbH1N+0c3yhNX2 kLG1k2+2iQXfm5aw+rCD6mrQIjLmLaTt1JkFukA31FJpN2GpuRyprYH1ksFiaGMFt+gq o8HU/2nZU0vqtizXH30wfGMxrX5z1ALzSU5d3c6yMgO7uKRe/skKLp7XovI0q/mJ3xGD jySLooDsU6KzHbLQhEAd3qwygAE8B8co3jVuA+8qwuKU7OwCDvElBHJVw1NMokf4YC52 kpZzsqo8ah5yBeyWytuKVwF/C21O2yzgMNqlteh94jsW9cM4OQ/AMn+q2GxSQ7UQ8uks QeSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WIqlYSoa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d2si138621vsh.22.2021.05.19.12.00.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 12:00:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WIqlYSoa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRQP-0001lc-Rk for patch@linaro.org; Wed, 19 May 2021 15:00:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1f-0002iB-K4 for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:35 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]:44657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1d-0007OE-Op for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:35 -0400 Received: by mail-oi1-x22e.google.com with SMTP id d21so13972394oic.11 for ; Wed, 19 May 2021 11:34:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MxaVFDhOR/2P7mRJMj9Ww3Gxrm+V2fvm6YpN2MZVwIE=; b=WIqlYSoaWmrH4nFkAtEJPo/VcDqFVEAACacHxoRClLekcEfh/SDXX1vhJZFRtd6Wxv N5G7O96AJ/H4HkLshGpCav5Awoe03ngwkeIerm89RwchYgdxrRPpFTMoNfTOkAneYnZo 8514O7MQcVSL6wYpcdbyLieJqWmaoad+O8O4Hg5+raqUNQdZKhbwteexxyjoihCRAlOQ hjIQ7BFdNMD+q4Ft0f3W0pu3jxzyAi6MeVGgKLWRrkuLgrstHwSRjnf5bqGG1/+GxJ67 02VoY+uT8AT076VuV+t4M1Uw3vP5zG5WHBSu4wdrVmz0Hw48k+N1S7fxUIBeiBoNY17q Qkxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MxaVFDhOR/2P7mRJMj9Ww3Gxrm+V2fvm6YpN2MZVwIE=; b=GAcm0yAggkqEzaZ4z7Xy/1hQGHeC3id7aHlB6DtzxA9GZmBWdimRtlfXkL830O3rng 7gmf5cQBRm+vNHYzlFqI9Abu4+BU63cNQFajOrm8hfW0Gypq9a0S8c3XV1ZFfiqsRR+z uWcxCOiTbH4e9XbzPVe36kuNHlWffXzfMqoSo6q4LhZSj255RUsfU2MCyb7MgvGIvyyL FgDm00clGXOC0aUVCo1TQ8l0tH2ctM3AYc564WvE1kEe0C6/UQIafYeV1KdK4suOHm/W j5cVe1c6QIhcSXrobzZpDcx9a7/jUXSrevkd5QQ/FNkcVEvx7vyZKNAbyuvk6iy+kE5T 0aNQ== X-Gm-Message-State: AOAM5331rWDrEFiF+suxHldV2Jy031p/z1aEWwcexvFTeeMttUUIfRPG etIFkk1H449b/BpRemT4+riOGdZHyD81ApIE X-Received: by 2002:aca:aa12:: with SMTP id t18mr547947oie.16.1621449272775; Wed, 19 May 2021 11:34:32 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 40/50] target/i386: Pass env to do_pause and do_hlt Date: Wed, 19 May 2021 13:30:40 -0500 Message-Id: <20210519183050.875453-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having the callers upcast to X86CPU is a waste, since we don't need it. We even have to recover env in do_hlt. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-41-richard.henderson@linaro.org> --- target/i386/tcg/misc_helper.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 931dbd9db0..23287b330e 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -101,19 +101,18 @@ void QEMU_NORETURN helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } -static QEMU_NORETURN void do_pause(X86CPU *cpu) +static void QEMU_NORETURN do_pause(CPUX86State *env) { - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); /* Just let another CPU run. */ cs->exception_index = EXCP_INTERRUPT; cpu_loop_exit(cs); } -static QEMU_NORETURN void do_hlt(X86CPU *cpu) +static void QEMU_NORETURN do_hlt(CPUX86State *env) { - CPUState *cs = CPU(cpu); - CPUX86State *env = &cpu->env; + CPUState *cs = env_cpu(env); env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; @@ -123,12 +122,10 @@ static QEMU_NORETURN void do_hlt(X86CPU *cpu) void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu = env_archcpu(env); - cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); env->eip += next_eip_addend; - do_hlt(cpu); + do_hlt(env); } void helper_monitor(CPUX86State *env, target_ulong ptr) @@ -143,7 +140,6 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) { CPUState *cs = env_cpu(env); - X86CPU *cpu = env_archcpu(env); if ((uint32_t)env->regs[R_ECX] != 0) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); @@ -153,20 +149,18 @@ void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) /* XXX: not complete but not completely erroneous */ if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { - do_pause(cpu); + do_pause(env); } else { - do_hlt(cpu); + do_hlt(env); } } void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu = env_archcpu(env); - cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); env->eip += next_eip_addend; - do_pause(cpu); + do_pause(env); } void QEMU_NORETURN helper_debug(CPUX86State *env) From patchwork Wed May 19 18:30:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442507 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1604798jac; Wed, 19 May 2021 12:05:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3GgLNtktVWrEwuzZaU1QMwfom48u03uCRGAQ/TMSW2d0wg8SZbnzHUmNviAS/jDpDv/cX X-Received: by 2002:a05:6638:3395:: with SMTP id h21mr614827jav.44.1621451130343; Wed, 19 May 2021 12:05:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621451130; cv=none; d=google.com; s=arc-20160816; b=cHvxIAQDjH+djjRlfKPfHkqPAiVXB6fPDSNbMtv66EVjAyeB6vP3g3kOhfIOeDQ9lD uC+bms47tGgEfpXYbVCh+yIHnbshFy/4qjjOxQlS58tnojMw9wcAC+5wt/I7pm29jt38 y1u0IibdfTeeGehipD3YS8adUe1XpzYjk++GgMd7861zGZiRYhDjr0++DcomcJMv1Q+O vQu/GjB2lmvbesV49iqKO5AaVSjavVoCDSMg085fJc1xtiexG4bgebwghCoHZtXz5qUE Ki2w+K7jOBXzDT2M2Tu5DZwqV20yu6LYdGFlcPxPUFZKeE5WRNqQHh+4F/fEP4N6j472 a1sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=klTWXaUSPDXpDuYjtqmoOjms0PHU2tWWOTJOUfsWPG4=; b=YYwOHoWTl3gdu24igtSdRXREXkhDLIOR3MT9O3vObxFrpckIf4er2iOBLX8HZcEhZw KQZhnimOIt7riyk6uL4NeLI/31MxUiiR0/89o+C0huxtEhaK4qgYviBkDW7ep+aYUms6 eh09nk4+hWpYC+r0TQmkUynQ4aKn6HZmxJKf6G2W7elBdU1tv3VigmdtydpoWVHBIzmw tcqGiGb69gBb0zxSHJ/uqD2WRUTO3Pxwu1BE34gaVBBlq6RfXoLflI2q6fERRk65SxNZ Yv5/kimBw3Y3WXHgQQ3sR0hePEP6vxxMLUTNNg4MUT0g73Vs0Kvbhk9MjW0ClejLJaj+ O73A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6tMDS5K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z89si165917jah.125.2021.05.19.12.05.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 12:05:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6tMDS5K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRVZ-0008T5-Pn for patch@linaro.org; Wed, 19 May 2021 15:05:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1h-0002o2-7x for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:37 -0400 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]:46811) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1e-0007Od-VV for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:36 -0400 Received: by mail-oi1-x235.google.com with SMTP id x15so13967791oic.13 for ; Wed, 19 May 2021 11:34:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=klTWXaUSPDXpDuYjtqmoOjms0PHU2tWWOTJOUfsWPG4=; b=g6tMDS5KMFejpwHK5Q5lFtH2qaJ8iBDdCKwRP0hoQ6hs4cUOGgHu2M9qGuN/0DF0xE lwg7z8jqQix7omXfaQr3OGfbIXlyRhqJEoiTBWyPHFDqC1T3uhCTXtwRoY2ZePJ7dH+t 2BeMZ+1wfUJznLWzS5VCyb8kwNLEeingjN+lPoAiMSXlIJ635nLG2xDiQPIRdRPXTB8o kLTeEIKueUm9X0hEIOSzzwD5J5LLFBOtaJ/BhTFJir6a2y7k+602Nj+gI8GRZ8oRlB8h SHfwUDbQAZxl+24G74hmJFvtFETD/4rvfqKk7sHn/byLbV1CnZELZfof6JmWzHnoQuSf 2v/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=klTWXaUSPDXpDuYjtqmoOjms0PHU2tWWOTJOUfsWPG4=; b=DzRlYQueJ22s3F1y+vYMaR/KcQtnN/NQ00kcF5sPmxOEns44r/50oq5ok8hwOK1QaB zPmIvjWCpHguoLcfDJpOdy2X5cSFlUsSRPz3Vmdn2hpBJkLNIuAxjghYtgeH7S5qW3qL bOJkmHvyXmFg5aQMOXSY8xQNEoyEk8NpT84q3pr9lmDo18Ajp38YJUC4ttcs6+L9h6jI /w3ZQ28pM1AIxr3Fr/XRcZqCqgG8/fM4lT9+QdLF3vnk+I1szNRcqsVjeC/slP8JIip6 ny0gvHPKRcLebHQgUvDO5CqFTuo5uBSPbLINsM4l8H3sC5d69ELfOahwvWnHT1yNurKQ TCrA== X-Gm-Message-State: AOAM532YiU8XR4pSzXb9M6zO9P2ZjgiN6If7USevkbLEGWM0lfM/NtZL YOkJtbapfE344owoed+XycjfiLAylLP9Fh8c X-Received: by 2002:aca:5c04:: with SMTP id q4mr394929oib.11.1621449273688; Wed, 19 May 2021 11:34:33 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 41/50] target/i386: Move invlpg, hlt, monitor, mwait to sysemu Date: Wed, 19 May 2021 13:30:41 -0500 Message-Id: <20210519183050.875453-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These instructions are all privileged. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-42-richard.henderson@linaro.org> --- target/i386/helper.h | 8 ++-- target/i386/tcg/helper-tcg.h | 1 + target/i386/tcg/misc_helper.c | 55 +--------------------------- target/i386/tcg/sysemu/misc_helper.c | 53 +++++++++++++++++++++++++++ target/i386/tcg/translate.c | 4 ++ 5 files changed, 63 insertions(+), 58 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index ebfaca66dd..ab72eba52a 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -51,7 +51,6 @@ DEF_HELPER_FLAGS_3(set_dr, TCG_CALL_NO_WG, void, env, int, tl) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int) -DEF_HELPER_2(invlpg, void, env, tl) DEF_HELPER_1(sysenter, void, env) DEF_HELPER_2(sysexit, void, env, int) @@ -59,9 +58,6 @@ DEF_HELPER_2(sysexit, void, env, int) DEF_HELPER_2(syscall, void, env, int) DEF_HELPER_2(sysret, void, env, int) #endif -DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) -DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(reset_rf, void, env) @@ -115,6 +111,10 @@ DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) DEF_HELPER_2(invlpga, void, env, int) +DEF_HELPER_2(invlpg, void, env, tl) +DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) #endif /* !CONFIG_USER_ONLY */ /* x86 FPU */ diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 85a8b0ebd6..2510cc244e 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -76,6 +76,7 @@ extern const uint8_t parity_table[256]; /* misc_helper.c */ void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask); +void do_pause(CPUX86State *env) QEMU_NORETURN; /* sysemu/svm_helper.c */ #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 23287b330e..baffa5d7ba 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -60,14 +60,6 @@ void helper_cpuid(CPUX86State *env) env->regs[R_EDX] = edx; } -void helper_invlpg(CPUX86State *env, target_ulong addr) -{ - X86CPU *cpu = env_archcpu(env); - - cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); - tlb_flush_page(CPU(cpu), addr); -} - void helper_rdtsc(CPUX86State *env) { uint64_t val; @@ -101,7 +93,7 @@ void QEMU_NORETURN helper_rdpmc(CPUX86State *env) raise_exception_err(env, EXCP06_ILLOP, 0); } -static void QEMU_NORETURN do_pause(CPUX86State *env) +void QEMU_NORETURN do_pause(CPUX86State *env) { CPUState *cs = env_cpu(env); @@ -110,51 +102,6 @@ static void QEMU_NORETURN do_pause(CPUX86State *env) cpu_loop_exit(cs); } -static void QEMU_NORETURN do_hlt(CPUX86State *env) -{ - CPUState *cs = env_cpu(env); - - env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ - cs->halted = 1; - cs->exception_index = EXCP_HLT; - cpu_loop_exit(cs); -} - -void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) -{ - cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); - env->eip += next_eip_addend; - - do_hlt(env); -} - -void helper_monitor(CPUX86State *env, target_ulong ptr) -{ - if ((uint32_t)env->regs[R_ECX] != 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - /* XXX: store address? */ - cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); -} - -void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) -{ - CPUState *cs = env_cpu(env); - - if ((uint32_t)env->regs[R_ECX] != 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); - env->eip += next_eip_addend; - - /* XXX: not complete but not completely erroneous */ - if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { - do_pause(env); - } else { - do_hlt(env); - } -} - void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) { cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index c7381ef7e8..803c39e2fb 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -438,3 +438,56 @@ void helper_rdmsr(CPUX86State *env) env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EDX] = (uint32_t)(val >> 32); } + +void helper_invlpg(CPUX86State *env, target_ulong addr) +{ + X86CPU *cpu = env_archcpu(env); + + cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); + tlb_flush_page(CPU(cpu), addr); +} + +static void QEMU_NORETURN do_hlt(CPUX86State *env) +{ + CPUState *cs = env_cpu(env); + + env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ + cs->halted = 1; + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); +} + +void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend) +{ + cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); + env->eip += next_eip_addend; + + do_hlt(env); +} + +void helper_monitor(CPUX86State *env, target_ulong ptr) +{ + if ((uint32_t)env->regs[R_ECX] != 0) { + raise_exception_ra(env, EXCP0D_GPF, GETPC()); + } + /* XXX: store address? */ + cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC()); +} + +void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend) +{ + CPUState *cs = env_cpu(env); + + if ((uint32_t)env->regs[R_ECX] != 0) { + raise_exception_ra(env, EXCP0D_GPF, GETPC()); + } + cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); + env->eip += next_eip_addend; + + /* XXX: not complete but not completely erroneous */ + if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { + do_pause(env); + } else { + do_hlt(env); + } +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 14a44a00ca..39af147a87 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -194,7 +194,11 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY STUB_HELPER(clgi, TCGv_env env) +STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) +STUB_HELPER(invlpg, TCGv_env env, TCGv addr) +STUB_HELPER(monitor, TCGv_env env, TCGv addr) +STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) From patchwork Wed May 19 18:30:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442506 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1604098jac; Wed, 19 May 2021 12:04:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKd+dCDl5D/eScoVJP9TRk/9ZwjRS2dbIhq6WX7X6X+6W8bIyioZd27MPXDKxa0UAxZBys X-Received: by 2002:a02:cf32:: with SMTP id s18mr560830jar.31.1621451079261; Wed, 19 May 2021 12:04:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621451079; cv=none; d=google.com; s=arc-20160816; b=oAJtHqYaky9FPIyuJqL70H292TCBN5jy/xwoo7hYJQGEvWsG7woumSJCvAUL1SKB4K 9/gZa5XXlMTj1sxR3W7aL319/2F91ZZ1WK+KDqy2uHUmaj2vWa6+pfupEOi/Mz7z8yor e2lHWq0JIL31zjccFue4oFiI7wAf/SJPHL6fsW4urMiyjFhxZsaURq/PS8WwSGNYTv8+ Zw0weyMitUd6MLDJv7GeiZtmpuDGGRuawukTRPf6Gh1K9WsMxyhauWe+fl9Hsfk6tXkv iq8QCw9u9+0aSyo/Px8kP32WZePQmV8jk5k1xnBFr81/aTVmL1owmkcieAXb3o50n2L8 0NUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qedixzyYh5iaufNZBAKxPaR/qjTosX24RNXw6yX0DSU=; b=uCyy323UVEipsJVO4HoNgqyaryevGFuTFAB4GB5qt8o4bycT/9rU//5EdG08DQTkKe +pX85+JiLVsybNaEhFbTnwnYToFem7W1JsNdWWnIs3UV5sHn8iiwuzxntzOMwxsAMFmL 0jTKe8GSbv4pxhTmZiE+QfRL4OUq/2QhNxwSCanvGzybrnY+yu013aPETfFHijbxTMcN DclnvY/qoBf52ao/GRNIWEh31Oh6uArbfOhVjRBN8THnLvuItZPrgDWVG+UCJ6ugjHD5 dbVcJ4V8KLTwL35LPKMftkrHxHtT8Gf8YjsiMGV4+EAX5gV5Fq7Q9Q66pLWaUWCqIoZr 48qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KQ9ITebU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w8si115726iou.72.2021.05.19.12.04.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 12:04:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KQ9ITebU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRUj-0007SV-Vo for patch@linaro.org; Wed, 19 May 2021 15:04:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1i-0002rA-0L for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:38 -0400 Received: from mail-ot1-x336.google.com ([2607:f8b0:4864:20::336]:42771) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1f-0007P1-Vm for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:37 -0400 Received: by mail-ot1-x336.google.com with SMTP id g7-20020a9d12870000b0290328b1342b73so4784928otg.9 for ; Wed, 19 May 2021 11:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qedixzyYh5iaufNZBAKxPaR/qjTosX24RNXw6yX0DSU=; b=KQ9ITebUGUh4+9o4JBgxns0Q5NIWXY6FwRHGSNy0ggkeASd5R3NxAPpLG0rVcJHtJH iPRu7VEgL5AXT3KZZ4aubUBe+SfCbo/l3lfBTIal1C2tXldulUqAAF3IQgIPONdOuD1C XewMf6/1u4yk5m/i6tp7FnYk7zdJF2SojwU0w2tvhzS7M7rKE5cHjT1MEbT/WIaOc5Oq z7Vm2ipUaWKtySv58AvoYwA0cxIhC5NS+6BEK1GJ/oP2XOd2l3KZHNr1FBNDu4AmjD0O rK/wyxpSzlr/d3UpGKT7tEPhHv07mTp029HQrY8EA+YHDeHoaf+lNwWI/htNfHB1mPVN 5PWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qedixzyYh5iaufNZBAKxPaR/qjTosX24RNXw6yX0DSU=; b=bZVqyEIvSULlQ7eJ8DmQ9Yf39CaxbQt7iCFK462IJMCS+qw4lgQlkK00nrWfh5dgGL oH5m3rSQXvXY0yKsMKuxJXNdZvzn0+SItSX56WIhxdVBoHLr3VmfkCwKy+YzFbJlyDKm I6kXNKX/5zWQLhiCR3zZQe/RIl9+trpnwLwKc++FThn4tTAGBv095Bu4vBtKUw9oGzif W4TAz8tSLYsAbgCxhHVz5addXqD1sPEQY2Yxb6hKy1N2D36X5pkf+6jdfknRFyu/H87S 4UZw9Cm/j98pi25NjI3Ne8jlcUpcwfaR9SMkNkqZXEN4uootbsNVdu3yQGbGb09sQOQO HnwA== X-Gm-Message-State: AOAM530f7+CBD4f6wasgS0Hk0KT22KYnPgJzi4lVubwrejBawiWQAOIk EjFC7jTrQUtgj4bHb72PvDOu6jfASqfwdSqd X-Received: by 2002:a9d:1918:: with SMTP id j24mr619519ota.329.1621449274636; Wed, 19 May 2021 11:34:34 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 42/50] target/i386: Unify invlpg, invlpga Date: Wed, 19 May 2021 13:30:42 -0500 Message-Id: <20210519183050.875453-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use a single helper, flush_page, to do the work. Use gen_svm_check_intercept. Perform the zero-extension for invlpga inline. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-43-richard.henderson@linaro.org> --- target/i386/helper.h | 3 +-- target/i386/tcg/sysemu/misc_helper.c | 7 ++----- target/i386/tcg/sysemu/svm_helper.c | 18 ------------------ target/i386/tcg/translate.c | 20 ++++++++++++-------- 4 files changed, 15 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index ab72eba52a..0264fba335 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -110,8 +110,7 @@ DEF_HELPER_2(vmload, void, env, int) DEF_HELPER_2(vmsave, void, env, int) DEF_HELPER_1(stgi, void, env) DEF_HELPER_1(clgi, void, env) -DEF_HELPER_2(invlpga, void, env, int) -DEF_HELPER_2(invlpg, void, env, tl) +DEF_HELPER_FLAGS_2(flush_page, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 803c39e2fb..0cef2f1a4c 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -439,12 +439,9 @@ void helper_rdmsr(CPUX86State *env) env->regs[R_EDX] = (uint32_t)(val >> 32); } -void helper_invlpg(CPUX86State *env, target_ulong addr) +void helper_flush_page(CPUX86State *env, target_ulong addr) { - X86CPU *cpu = env_archcpu(env); - - cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); - tlb_flush_page(CPU(cpu), addr); + tlb_flush_page(env_cpu(env), addr); } static void QEMU_NORETURN do_hlt(CPUX86State *env) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index b431016e72..9d671297cf 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -412,24 +412,6 @@ void helper_clgi(CPUX86State *env) env->hflags2 &= ~HF2_GIF_MASK; } -void helper_invlpga(CPUX86State *env, int aflag) -{ - X86CPU *cpu = env_archcpu(env); - target_ulong addr; - - cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC()); - - if (aflag == 2) { - addr = env->regs[R_EAX]; - } else { - addr = (uint32_t)env->regs[R_EAX]; - } - - /* XXX: could use the ASID to see if it is needed to do the - flush */ - tlb_flush_page(CPU(cpu), addr); -} - void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 39af147a87..eb11a75e86 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -194,9 +194,8 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY STUB_HELPER(clgi, TCGv_env env) +STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) -STUB_HELPER(invlpga, TCGv_env env, TCGv_i32 aflag) -STUB_HELPER(invlpg, TCGv_env env, TCGv addr) STUB_HELPER(monitor, TCGv_env env, TCGv addr) STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) @@ -7592,9 +7591,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag - 1)); + gen_svm_check_intercept(s, SVM_EXIT_INVLPGA); + if (s->aflag == MO_64) { + tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]); + } else { + tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]); + } + gen_helper_flush_page(cpu_env, s->A0); + gen_jmp_im(s, s->pc - s->cs_base); + gen_eob(s); break; CASE_MODRM_MEM_OP(2): /* lgdt */ @@ -7682,10 +7687,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (!check_cpl0(s)) { break; } - gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_svm_check_intercept(s, SVM_EXIT_INVLPG); gen_lea_modrm(env, s, modrm); - gen_helper_invlpg(cpu_env, s->A0); + gen_helper_flush_page(cpu_env, s->A0); gen_jmp_im(s, s->pc - s->cs_base); gen_eob(s); break; From patchwork Wed May 19 18:30:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442488 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1593980jac; Wed, 19 May 2021 11:51:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeuvLo33ENyHycrvYxy9+Y0jWB731qmLaUpX11yA0wakbe8f1aAiRvL00MC3bWbX3f/0Gl X-Received: by 2002:a92:c564:: with SMTP id b4mr460342ilj.257.1621450311413; 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[209.51.188.17]) by mx.google.com with ESMTPS id k25si128031jap.38.2021.05.19.11.51.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:51:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hZnP/N1D"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRIM-0001tn-QN for patch@linaro.org; Wed, 19 May 2021 14:51:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1j-0002ux-1F for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:39 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]:33326) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1g-0007Py-Md for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:38 -0400 Received: by mail-ot1-x334.google.com with SMTP id i23-20020a9d68d70000b02902dc19ed4c15so12670527oto.0 for ; Wed, 19 May 2021 11:34:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NyRgc+Gn7oqqf/QHFgizxweLPsqaDiM3F1V+G4Xmf04=; b=hZnP/N1Dt2eLr/hb2J5uhosXENVCy+o6S3b2z3hByRkbVu6ucDwLyyCZjrJmOGYHgY fIa7Q6IkoiEBF34HqgFzfWFTIMH8jiW755uj8eEccO8DMM/PzZ61p2guHKqtzuVg2vXH OsdZ+VMz9UhiCocKLjPhrwVx0MRp6xz0cyDPSGYYu/JU/GKIjMmLEmGoThXfrNC/K/lD kaZ4FOoTMlnKtm2cX/ktPNOuDUHCKvCjka2EBCL6Vra0Dr5C16Ydtl+xKSO5HCOeiPqf IdXP5p4RK+yEsaRdLXV5XYY3Z4sWpt6DoHsT/oU0WBLO1ZCzX83v02vGXpOUY9CB63no L9LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NyRgc+Gn7oqqf/QHFgizxweLPsqaDiM3F1V+G4Xmf04=; b=AT7KDF2b2Hh1NKl75lWkQMCBfrQ17Hd95ymLcblUJw/qWlcxlxrSAX9VCYHFIJdd8f BiIW0UzYOAOMukQM/wa9XNcPTYMS2sgFet+dMK4e8c8olHIqngV1QYu9uzW7F2vOLbaB hpNEHv2OkA3dG8Biapg4pcK5TECypKKoOBOD0QGbGZh8blJFSzyiiVo0E8+D0huVoTdv ijFXdXq3GpDhyNSmVtoEBLeYYc2/gSRTEoSoyXlR7xD95sKGMYJNCLCUGW3QkABi4kY4 9bh4bohZnpNdi2qHPANFxtvl+QkjsoJD2Gv9rD+wqcY57oTcZsVc5kyFoejdZDvHUHdn pt2g== X-Gm-Message-State: AOAM531Ww8r9V+UaP1jCr3EauZwYGd8Rc2E8/GkGAVRR0zjqfXc5Iz5g UvDyA1OTioyAxraTb+Cm+tmipRkIjSIIPPCw X-Received: by 2002:a9d:5c08:: with SMTP id o8mr651089otk.261.1621449275543; Wed, 19 May 2021 11:34:35 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/50] target/i386: Inline user cpu_svm_check_intercept_param Date: Wed, 19 May 2021 13:30:43 -0500 Message-Id: <20210519183050.875453-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The user-version is a no-op. This lets us completely remove tcg/user/svm_stubs.c. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-44-richard.henderson@linaro.org> --- target/i386/cpu.h | 8 ++++++++ target/i386/tcg/user/svm_stubs.c | 28 ---------------------------- target/i386/tcg/user/meson.build | 1 - 3 files changed, 8 insertions(+), 29 deletions(-) delete mode 100644 target/i386/tcg/user/svm_stubs.c -- 2.25.1 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 324ef92beb..e6836393f7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2146,8 +2146,16 @@ static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) void helper_lock_init(void); /* svm_helper.c */ +#ifdef CONFIG_USER_ONLY +static inline void +cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, + uint64_t param, uintptr_t retaddr) +{ /* no-op */ } +#else void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); +#endif + /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, diff --git a/target/i386/tcg/user/svm_stubs.c b/target/i386/tcg/user/svm_stubs.c deleted file mode 100644 index db818f89a8..0000000000 --- a/target/i386/tcg/user/svm_stubs.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * x86 SVM helpers (user-mode) - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" -#include "tcg/helper-tcg.h" - -void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, - uint64_t param, uintptr_t retaddr) -{ -} diff --git a/target/i386/tcg/user/meson.build b/target/i386/tcg/user/meson.build index 9eac0e69ca..3555b15bdd 100644 --- a/target/i386/tcg/user/meson.build +++ b/target/i386/tcg/user/meson.build @@ -1,6 +1,5 @@ i386_user_ss.add(when: ['CONFIG_TCG', 'CONFIG_USER_ONLY'], if_true: files( 'excp_helper.c', 'misc_stubs.c', - 'svm_stubs.c', 'seg_helper.c', )) From patchwork Wed May 19 18:30:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442500 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1598844jac; Wed, 19 May 2021 11:58:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjcQ+4pWkFe6hBpiPhRiZnOuLvGsuSKQpBuybneyytlGmzX5mYpt8JtrZ50p2mCgfKI8hm X-Received: by 2002:a92:1901:: with SMTP id 1mr559126ilz.153.1621450707450; Wed, 19 May 2021 11:58:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450707; cv=none; d=google.com; s=arc-20160816; b=KFi3xXtfcTQSJE3ZACt+U7lXbYeEBSUuS8leUgkMCw1iKEiRqSEsjGUnxPUIpSgsKH 9cIflh2uFvJBBZDrABvLbRFc/bjCYZJwsVGtez+d6oTTOGQuHsb+EOiFGBedgVPnACOj dv1QzjdO/XXep8T3sFFfbBvLBxzC96fN+2h+dAET2yE8FI7THEbNJBt/dzDtK5AWZSET ow6gtymepOnZ3WiFhC2VpDGc3BpX9xI8ZKEJUjGJo18Mo6nTRQ+bkPvMK+tdReBqReQL 9baKvK5wmzj12W6kL12+hCaZT5+t98/o9tcAMa7zKU+S6Uw9/WXYb1H7Usf7FabF+Uq3 DgMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5FZEkPjS4wJtxJ82VN/fE6regNmzsPr0FO89DJYk2Ek=; b=xdT3hGXaVEm9Z1fcHS176ek1pj+Yp4DEhPfp34u+QPafNcgOc+OTW97Fc/+Ijpj6F7 xt7waz9/pU2W3c1zhXwwRC+Rd6A6bKv1jS1qYW2AvQbCSJXrZpiinJgFufUUCz6FlnjY 2RYJpmdyHEfBUc6uJh3FTCqOUBiAq78obp4w8tfBaTpS06ei3ox0b8bjTc6GjJSGv4K/ OL4kj2p4six/E8BMMKMMhYsR8/DBRSbX4fz2BHTZFbwt3fWG34HKpvLwgqo2QGwzl2Xf fqJx7aWUi1ynkhRLS1p8VcTnzR+XVfPhacQ2qoi6wkT2f/EHH03MWLSR1dYKVj4AiADG O57w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DM32tm/9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-45-richard.henderson@linaro.org> --- target/i386/helper.h | 8 ++++---- target/i386/tcg/translate.c | 4 ++++ target/i386/tcg/user/misc_stubs.c | 20 -------------------- 3 files changed, 8 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 0264fba335..1d85f033df 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -42,8 +42,6 @@ DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl) DEF_HELPER_2(iret_real, void, env, int) DEF_HELPER_3(iret_protected, void, env, int, int) DEF_HELPER_3(lret_protected, void, env, int, int) -DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int) -DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl) DEF_HELPER_1(clts, void, env) #ifndef CONFIG_USER_ONLY @@ -87,8 +85,6 @@ DEF_HELPER_1(cpuid, void, env) DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) -DEF_HELPER_1(rdmsr, void, env) -DEF_HELPER_1(wrmsr, void, env) DEF_HELPER_2(check_iob, void, env, i32) DEF_HELPER_2(check_iow, void, env, i32) @@ -114,6 +110,10 @@ DEF_HELPER_FLAGS_2(flush_page, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(hlt, TCG_CALL_NO_WG, noreturn, env, int) DEF_HELPER_FLAGS_2(monitor, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(mwait, TCG_CALL_NO_WG, noreturn, env, int) +DEF_HELPER_1(rdmsr, void, env) +DEF_HELPER_1(wrmsr, void, env) +DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int) +DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl) #endif /* !CONFIG_USER_ONLY */ /* x86 FPU */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index eb11a75e86..9501089861 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -198,6 +198,8 @@ STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) STUB_HELPER(monitor, TCGv_env env, TCGv addr) STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) +STUB_HELPER(rdmsr, TCGv_env env) +STUB_HELPER(read_crN, TCGv ret, TCGv_env env, TCGv_i32 reg) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) @@ -206,6 +208,8 @@ STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(vmmcall, TCGv_env env) STUB_HELPER(vmrun, TCGv_env env, TCGv_i32 aflag, TCGv_i32 pc_ofs) STUB_HELPER(vmsave, TCGv_env env, TCGv_i32 aflag) +STUB_HELPER(write_crN, TCGv_env env, TCGv_i32 reg, TCGv val) +STUB_HELPER(wrmsr, TCGv_env env) #endif static void gen_eob(DisasContext *s); diff --git a/target/i386/tcg/user/misc_stubs.c b/target/i386/tcg/user/misc_stubs.c index 84df4e65ff..df38b44d6e 100644 --- a/target/i386/tcg/user/misc_stubs.c +++ b/target/i386/tcg/user/misc_stubs.c @@ -53,23 +53,3 @@ target_ulong helper_inl(CPUX86State *env, uint32_t port) g_assert_not_reached(); return 0; } - -target_ulong helper_read_crN(CPUX86State *env, int reg) -{ - g_assert_not_reached(); -} - -void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) -{ - g_assert_not_reached(); -} - -void helper_wrmsr(CPUX86State *env) -{ - g_assert_not_reached(); -} - -void helper_rdmsr(CPUX86State *env) -{ - g_assert_not_reached(); -} From patchwork Wed May 19 18:30:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442508 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1606793jac; Wed, 19 May 2021 12:07:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFZsJNVYzUdSkdzqcJ/7q4dUoG6S0kmPGvxMhbo4t7MrTTJmQEUfOcbLw8igI4aHH/9nrD X-Received: by 2002:a6b:d615:: with SMTP id w21mr1084900ioa.74.1621451269579; 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Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-46-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9501089861..ef0ba822e1 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7260,6 +7260,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_rdmsr(cpu_env); } else { gen_helper_wrmsr(cpu_env); + gen_jmp_im(s, s->pc - s->cs_base); + gen_eob(s); } } break; From patchwork Wed May 19 18:30:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442510 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1609906jac; Wed, 19 May 2021 12:11:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz17lFRD7GEr+VkUjxHGhrlnXwxHroTHAqEFmRHc8gJaSSX8CfRV+ENPdfMqeMQQRx1ShRI X-Received: by 2002:a6b:d103:: with SMTP id l3mr998772iob.159.1621451500350; Wed, 19 May 2021 12:11:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621451500; cv=none; d=google.com; s=arc-20160816; b=T4VLYZe4NZDThpnnwm4C6EV3+qP0vA/DaD1wWcw6315IOw3SQOGyUoFvcVyutB3pb7 eBe5tv4cWGKw2pHPh8FKqdlgdhWehgGvp1dZgA1iXpCSnCiZs7zDXyJ02drShFgRxZFw xTB1F8xnLb1g4vSXas4HfSs988fqzH0vkQwuSYMbucsLEh96CWwTgQzo9hdbUTSztGWD 9kEQbV7XhkEPf53BSzguL9n+ksiMIuP2Smud8GQiKE3pCmtzCPVDacJTkHm5hn+ac0fH smfYqQRZgpFewu4cPOVgGiGSRCx9FSN0X4Uc8mkeay7r0tuWpW/2TrjlqKd1JFnR7Mxp Faug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qnZV0wX95VAsWpNoAvBiFixvkFrekitqEJ+f9enV/uM=; b=lNb+CCpFPhQK0KNC2HMVxKYnpmDVHoX+q4ScASIjIwCT+MMn2bbxtJiWS7VPcVntA0 3VJoDjcYHZiW8IQMfWBWpouQBVOLlRItLxn+Ho8znRQ5Z+c6B2/tnC1sQtWy6852J0mv STBGbCscxcoIHAYSAPCvd6tVIlPllWjNlnMrPuWpoYiXZ7ZDNF7tWlkhuzkbY790BQnQ kDIUyzl9W8bB2EwY288pgYi1x3ORletuUgl/O5HU1HrYuNP6c+pxZcYMCodhpqxfb+Ph +Jn1xyCwD93lSye4of2U59uCLrhdEB7jFnokQhioeBwEQRkURATw20UzzxcvjUY9Srdn 716g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tzs6fR9H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e25si150789iol.49.2021.05.19.12.11.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 12:11:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tzs6fR9H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRbX-00034S-OO for patch@linaro.org; Wed, 19 May 2021 15:11:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1o-00038s-ND for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:44 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]:37449) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1j-0007S6-Im for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:44 -0400 Received: by mail-ot1-x334.google.com with SMTP id v19-20020a0568301413b0290304f00e3d88so12628720otp.4 for ; Wed, 19 May 2021 11:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qnZV0wX95VAsWpNoAvBiFixvkFrekitqEJ+f9enV/uM=; b=tzs6fR9HuT5Ot6KIndiOlsq580qc4nj8kZdx4WwfaMk1u0obzIpr5uFCzCqTrmUfgZ /1AMB/5gbL4qcmfT71UL+o8uNor6i26dPgyWEr8gk7kyOyud/K9woHqCDdWba3ie/53V aaPgZi2CcfSMd0gsb2WdnmpLBPpNnHLHnP2GZbAY2AGlLzHGLG2rd1VOrdZ9YM6RunsD o+bEgJ+mEepfFGDnl9qPTrUZ1T7IMyDJeNBvYBBdlXGjDbuC1Z1b+jJT314zWw2kyBQE 8s8+Tp2ByvymprlJOGX8d3OzD89AFdC4UkCGxnjLuhHVwRLDvvD3RHc9X+dxYUpTrLQB ZTRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qnZV0wX95VAsWpNoAvBiFixvkFrekitqEJ+f9enV/uM=; b=nl02A+9xRMZ1LTygK+F/XTdn0JBer7iHAw65NzNKrkg2EfS7Ll70hYW+Oq0WMWWKoJ rnJTH6YjXZaQpQDBDChhMhnsyEw+VZYbB0ZFilcfYeSt3+NvZteoqGC9KhuYrfE0a5O8 NPPqI6a2qVXxcy+s99Ye6T6d+uKGM87PxkyqyuxX5v28BxPUcF5BansBNf2ZrF8cYmBR W5N2IptMJu6EkLIAi7EIM4Vo3OcF1k/1qRfJTs7I6nWsR112x4nberLMfZycHLLX4P8P QnqzHzV+XTXRZXqCWoWOfTpKMrHogRW1zo53VgYixBAZ+0c/ilNdeNqnF1YnfHBLZ9+e WQTA== X-Gm-Message-State: AOAM531X3ju7lxSdiNHql1dBs5BaDPxxQE6NUOVno7fUzDjLnBeLgsIX MaNKiaPHFaYYxfZkYUY259fwUL5MFaBJCPuc X-Received: by 2002:a05:6830:33c7:: with SMTP id q7mr666332ott.308.1621449278475; Wed, 19 May 2021 11:34:38 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 46/50] target/i386: Tidy gen_check_io Date: Wed, 19 May 2021 13:30:46 -0500 Message-Id: <20210519183050.875453-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Get cur_eip from DisasContext. Do not require the caller to use svm_is_rep; get prefix from DisasContext. Use the proper symbolic constants for SVM_IOIO_*. While we're touching all call sites, return bool in preparation for gen_check_io raising #GP. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-47-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 57 +++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ef0ba822e1..2282c3598c 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -674,13 +674,10 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) } } -static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, - uint32_t svm_flags) +static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags) { - target_ulong next_eip; - + tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); switch (ot) { case MO_8: gen_helper_check_iob(cpu_env, s->tmp2_i32); @@ -696,15 +693,20 @@ static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, } } if (GUEST(s)) { + target_ulong cur_eip = s->base.pc_next - s->cs_base; + target_ulong next_eip = s->pc - s->cs_base; + gen_update_cc_op(s); gen_jmp_im(s, cur_eip); - svm_flags |= (1 << (4 + ot)); - next_eip = s->pc - s->cs_base; - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); + if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { + svm_flags |= SVM_IOIO_REP_MASK; + } + svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot); gen_helper_svm_check_io(cpu_env, s->tmp2_i32, - tcg_const_i32(svm_flags), - tcg_const_i32(next_eip - cur_eip)); + tcg_constant_i32(svm_flags), + tcg_constant_i32(next_eip - cur_eip)); } + return true; } static inline void gen_movs(DisasContext *s, MemOp ot) @@ -2425,11 +2427,6 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) } } -static inline int svm_is_rep(int prefixes) -{ - return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); -} - static void gen_svm_check_intercept(DisasContext *s, uint32_t type) { /* no SVM activated; fast case */ @@ -6483,8 +6480,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6d: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); + if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6502,8 +6500,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6f: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - svm_is_rep(prefixes) | 4); + if (!gen_check_io(s, ot, SVM_IOIO_STR_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6526,8 +6525,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); tcg_gen_movi_tl(s->T0, val); - gen_check_io(s, ot, pc_start - s->cs_base, - SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6544,8 +6544,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); tcg_gen_movi_tl(s->T0, val); - gen_check_io(s, ot, pc_start - s->cs_base, - svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, 0)) { + break; + } gen_op_mov_v_reg(s, ot, s->T1, R_EAX); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -6563,8 +6564,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xed: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + break; + } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6580,8 +6582,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xef: ot = mo_b_d32(b, dflag); tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - gen_check_io(s, ot, pc_start - s->cs_base, - svm_is_rep(prefixes)); + if (!gen_check_io(s, ot, 0)) { + break; + } gen_op_mov_v_reg(s, ot, s->T1, R_EAX); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { From patchwork Wed May 19 18:30:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442509 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1607310jac; Wed, 19 May 2021 12:08:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuNiRnBz/YQMTTtyzxyHK/8mjLqCr24SngjnN13kvyP3+ViFq+C04ozlcr5xdpAdJpFSus X-Received: by 2002:a05:6e02:ce:: with SMTP id r14mr556238ilq.27.1621451314229; Wed, 19 May 2021 12:08:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621451314; cv=none; d=google.com; s=arc-20160816; b=QfOzirrM+9U0JYJnXaivsUlJPSVqwL8zgwdzOAsB5SJ/5rhn+mYgMK50ebiMgo3Qnh wwDd0CVmNGj4bh0Ae6BjQ0AFBPXX7algjUDN2tu05o6cTYn5f9Gr6wZCELJl2ZboPju8 pyQEOq4HljvESUy5/MSrIaNPQxIDIR9ztPYw5gS6kYHNP1xa3cBe2bxzLdUfRES38VXk MElHyrA9tiiOA/OZYejkja74GpOy2BHZCkfJRLY+LynB6mjVBRgNFiEnhUEGJUaA3Avp 3QtszmJkuak5KE3bfNlskFheos6kVx41VoR9QtPp7OT8R0mjTuIbLtBD+0ddrTppoQpn C6hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MRsJOtWLsUiQQv1TYIL+rqHnyRD8cRIptjpT1vVaFRM=; b=mwFVI/nwfIthJ+gA6bI7kWTCzAusvEiTzwQrMmWQ/az8N6FW+gp1mZ1yXkZUDrKwk6 KSScHUbkN+eNg93PRz8TQwccq6FuOHQnBSjW5qne7U4Eb2jLECepeshDVj24qpH12ZXL 0McXbirGW3K1EUaQGX6kz1p7WnP0la4b443Zsyz3cd/9rlhaTGAzb683D8JyBi0QQn0+ NUTJSxNhjGamIPdOr+fu2IAwdrBpzAv6cmD9f386j2e0mWy0o3/Or826dOFKP2FdeYfW S1syjM2Maij+zf7epowPLBKVrLeVyGHDJ/TpZ3+m0zg2a0+2tsRzccAZKE+wUuk5KAjI EEMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hfKff/cv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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We were doing the truncation of EDX in multiple places, now only once per insn. While all callers use s->tmp2_i32, for cleanliness of the subroutine, use a parameter anyway. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-48-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 55 +++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2282c3598c..94193a8e00 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -674,19 +674,23 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) } } -static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags) +/* + * Validate that access to [port, port + 1<tmp2_i32, s->T0); if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { switch (ot) { case MO_8: - gen_helper_check_iob(cpu_env, s->tmp2_i32); + gen_helper_check_iob(cpu_env, port); break; case MO_16: - gen_helper_check_iow(cpu_env, s->tmp2_i32); + gen_helper_check_iow(cpu_env, port); break; case MO_32: - gen_helper_check_iol(cpu_env, s->tmp2_i32); + gen_helper_check_iol(cpu_env, port); break; default: tcg_abort(); @@ -702,7 +706,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, uint32_t svm_flags) svm_flags |= SVM_IOIO_REP_MASK; } svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot); - gen_helper_svm_check_io(cpu_env, s->tmp2_i32, + gen_helper_svm_check_io(cpu_env, port, tcg_constant_i32(svm_flags), tcg_constant_i32(next_eip - cur_eip)); } @@ -6479,8 +6483,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6c: /* insS */ case 0x6d: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, + SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -6499,8 +6505,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x6e: /* outsS */ case 0x6f: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, SVM_IOIO_STR_MASK)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -6524,14 +6531,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xe5: ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); - tcg_gen_movi_tl(s->T0, val); - if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + tcg_gen_movi_i32(s->tmp2_i32, val); + if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_movi_i32(s->tmp2_i32, val); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -6543,16 +6549,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xe7: ot = mo_b_d32(b, dflag); val = x86_ldub_code(env, s); - tcg_gen_movi_tl(s->T0, val); - if (!gen_check_io(s, ot, 0)) { + tcg_gen_movi_i32(s->tmp2_i32, val); + if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - gen_op_mov_v_reg(s, ot, s->T1, R_EAX); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_movi_i32(s->tmp2_i32, val); + gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); gen_bpt_io(s, s->tmp2_i32, ot); @@ -6563,14 +6567,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xec: case 0xed: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, SVM_IOIO_TYPE_MASK)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -6581,16 +6585,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xee: case 0xef: ot = mo_b_d32(b, dflag); - tcg_gen_ext16u_tl(s->T0, cpu_regs[R_EDX]); - if (!gen_check_io(s, ot, 0)) { + tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_EDX]); + tcg_gen_ext16u_i32(s->tmp2_i32, s->tmp2_i32); + if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - gen_op_mov_v_reg(s, ot, s->T1, R_EAX); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); + gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); gen_bpt_io(s, s->tmp2_i32, ot); From patchwork Wed May 19 18:30:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442502 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1599758jac; 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[209.51.188.17]) by mx.google.com with ESMTPS id w126si229661ybg.271.2021.05.19.11.59.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:59:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UfvTlxwp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRPy-0000f5-EJ for patch@linaro.org; Wed, 19 May 2021 14:59:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1p-0003AM-DL for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:45 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]:45890) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1l-0007Uz-Fd for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:45 -0400 Received: by mail-ot1-x32f.google.com with SMTP id t10-20020a05683022eab0290304ed8bc759so12598047otc.12 for ; Wed, 19 May 2021 11:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vrBlr05OPyOsTxUcBIownyAACzTpgn59yE8tdL4D5Hs=; b=UfvTlxwp+Ccmg+lvKKBZhUfQhnFHQIZ5ZjNDNbuj2XvrmAJ91X4mD7nHLfK3FnfJlT Cwdez5OBeYqCfHPYByprKAV6pJHZrEt5g+JPQCiZdf3xkWuIu25auymkbEhnWLb6vyBr DzYWRR9CvGt/pFmTbz8LivGGlGYPR88MHoRxJfa/LYQO0pIuga4aJj9XkxZ7crJQ12fY +TbC0hDMqpTmAjghFMU4N29SsXLtL62j1wwu1pLiM4XaBjQ+UTGHCOc8DfYgYw5MWgwk odkAsbX7p1Zzch9xIUvQuZtoO+zFYsmWwd1rLQ43Mw4lp8ip2AvKBvM7+HjwcOTv9+Bt zsWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vrBlr05OPyOsTxUcBIownyAACzTpgn59yE8tdL4D5Hs=; b=LbLyw+3i8OyVJ+v2dEEHwuvzS4JjxFORCSVx4vASLl+EjSTHHYkymvV7gG1ZsVBem+ jAbAe0S0tGuKqvuWJ4elrFvZcTIwmNE9NmcZm99YTigtVDC10AEyM2EZbdKL7aAuMWOY veInmDivC1PsZY1UZ54R+/7nsYCcjhhIn7deVcPSFdufeo1nR9JcRN1QgbcaESbo18pf 2pHgAwNHcZZU4O+y2q439VRemLzIwbay23mDJEf83RDg7/uaEfvwHRq4qrTNXrdmAXSB J3czPGiXIiVgfvoi0XZhM8I7c8Gw155SVNMbl22R2jPSXuWSyk3r6sMYfrrGB6a2Fmsc TRTA== X-Gm-Message-State: AOAM531yfkKlInbL6zACkeBxjVi5UMq3xSzRUoEZd3ZSkesaPNz39AX/ vGtl9c0UAgyTCe3q6EQ5HxokDhamDKtSxlk5 X-Received: by 2002:a9d:61cb:: with SMTP id h11mr638072otk.19.1621449280393; Wed, 19 May 2021 11:34:40 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 48/50] target/i386: Create helper_check_io Date: Wed, 19 May 2021 13:30:48 -0500 Message-Id: <20210519183050.875453-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Drop helper_check_io[bwl] and expose their common subroutine to tcg directly. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210514151342.384376-49-richard.henderson@linaro.org> --- target/i386/helper.h | 4 +--- target/i386/tcg/seg_helper.c | 21 +++------------------ target/i386/tcg/translate.c | 14 +------------- 3 files changed, 5 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 1d85f033df..47d0d67699 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -86,9 +86,7 @@ DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) -DEF_HELPER_2(check_iob, void, env, i32) -DEF_HELPER_2(check_iow, void, env, i32) -DEF_HELPER_2(check_iol, void, env, i32) +DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_3(outb, void, env, i32, i32) DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(outw, void, env, i32, i32) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index cf3f051524..69d6e8f602 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -2418,10 +2418,10 @@ void helper_verw(CPUX86State *env, target_ulong selector1) } /* check if Port I/O is allowed in TSS */ -static inline void check_io(CPUX86State *env, int addr, int size, - uintptr_t retaddr) +void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) { - int io_offset, val, mask; + uintptr_t retaddr = GETPC(); + uint32_t io_offset, val, mask; /* TSS must be a valid 32 bit one */ if (!(env->tr.flags & DESC_P_MASK) || @@ -2444,18 +2444,3 @@ static inline void check_io(CPUX86State *env, int addr, int size, raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); } } - -void helper_check_iob(CPUX86State *env, uint32_t t0) -{ - check_io(env, t0, 1, GETPC()); -} - -void helper_check_iow(CPUX86State *env, uint32_t t0) -{ - check_io(env, t0, 2, GETPC()); -} - -void helper_check_iol(CPUX86State *env, uint32_t t0) -{ - check_io(env, t0, 4, GETPC()); -} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 94193a8e00..68ae9b0798 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -682,19 +682,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, uint32_t svm_flags) { if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { - switch (ot) { - case MO_8: - gen_helper_check_iob(cpu_env, port); - break; - case MO_16: - gen_helper_check_iow(cpu_env, port); - break; - case MO_32: - gen_helper_check_iol(cpu_env, port); - break; - default: - tcg_abort(); - } + gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); } if (GUEST(s)) { target_ulong cur_eip = s->base.pc_next - s->cs_base; From patchwork Wed May 19 18:30:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 442492 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1594806jac; Wed, 19 May 2021 11:53:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwP81kZAO+nbEXFMV2Vv2XZp9i0uAXL9vZn53OgVqXmi1TtZ7gF975uUkq5Ab8oJ6pPPlRc X-Received: by 2002:a05:6e02:92c:: with SMTP id o12mr534957ilt.256.1621450387112; Wed, 19 May 2021 11:53:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621450387; cv=none; d=google.com; s=arc-20160816; b=Zx+SP6QGvGeWgReWzjNAP+OG742CUaykuWwRFhyzPftvrIX4/GtvHzhQ5hQ+hUNzRW /vx4dW4XAonzLUUk5+dyTSRX/P/QIJSEGg3EXmRuxxJMgpnHu7CenZEfxtauX6AHQAk+ 69tlnmS1DAsZepgEMcXV2WntxFgEW3M/LQK4JhdD0sCk3PCq4SYm91eHhV6XTAAp0QcO juv421vk7K8RjoCZzUNTboJxeTs9Dda+OPCE46r5LfPqt+0n8ztCixMrqgxQ6Vyf3qJy 3/OF8n6DOW2sX/1wAHzuoa5TW2E1ghooYYYEsKRTmkWH73ccE6+3IRqi26UbrusIRrbR hEQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xGkZKZlGCLChYg0dV/p2rUqpj5XLQrJ/JmdPF5hhyvY=; b=0zolH/SrNip8Oy4zDH1uLe/vu9Ia+iYUERkcIspH7cCDRr1PaAWaDWLw5r0tFy0L4H VPJCNrE/0Y2smCrSJsRwozYp4Op1JJmI6GVl4iFwrfAi6Dx8kUkAL1CtwKEtCbbEqStE 4b4mpgq87CiVeRvWptirYGSZtBcid7v2SHzWayoNwJKRSD6a72MyfraM5QZUnMbtzgLr 3SEJ8zYVL4e4WCgF9g+Kiqke+GqBk6k/FgmlyfpuPQeIozDDLABuOjDDxgn09ed9lUid f6hScEsWgowc7vFE/ceQNQu6L4QBWuoYKkYn4l1kv7hu+sbnyvb5TuhzLc0MypW2mo1Y cXwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wdjyj2XL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f12si136961jas.31.2021.05.19.11.53.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 May 2021 11:53:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wdjyj2XL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljRJa-0007j3-Fy for patch@linaro.org; Wed, 19 May 2021 14:53:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljR1r-0003DX-5q for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:47 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]:46803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ljR1m-0007W1-HA for qemu-devel@nongnu.org; Wed, 19 May 2021 14:34:46 -0400 Received: by mail-oi1-x22b.google.com with SMTP id x15so13968184oic.13 for ; Wed, 19 May 2021 11:34:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xGkZKZlGCLChYg0dV/p2rUqpj5XLQrJ/JmdPF5hhyvY=; b=Wdjyj2XL/w+RwnSN/M47iLTY4ijeV6ECZpKlHCmaSPJ/ptNlr+2f47bOdCmT+nDPN4 YNazk+NxGPRx/HGveRJ1gipNnLUmBVMMs7dPVXPLhW+zlAqb+v+hiCgOkeo6CzKdS84b fohxmGIh1VpeE3TBR91R0N+EfIovhuu6lTMgLlaURbuRwf7yecHFKfhykddgUPV+I3vy 6ayuQazAVT7O7cvA3pXV/ZzDVTQKYkB4FDyJtw8jOi2nYNg8z6kDv0ANPi5wxNAx5Oy5 XFJhpCPxY7c/e5hMC/jEf1SKYHjS1Kw+wwZn5LKGrWrvW0WUzu/tW/8qeQQWc3pkSsSH SRuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xGkZKZlGCLChYg0dV/p2rUqpj5XLQrJ/JmdPF5hhyvY=; b=drFfjxCzG7Er2To3w0gL5vlISGvpcyqSir34gUsQFbUfBZigwdTh4P/lieUCUcnJL6 raai0wbMkEHcmTC7MTFw0glE/IbDJe4qcU9Fg6ptIevB8yvs5nH8AFF3McveGfZfqUQN GbXThyUiGbJ6N3Fa1VG7QHm1O+b30I+FWLbhTRZc8VbZ8byz0H7dOBz4LVf2H0A/PfqS JEp0jz5Z8huBPR8GwxtVRbonDppLKL7kyOj51WuGnfrfoPoTOZwIs95LAoABHNYuePoE 8rukX2c1bjYGBjSC2ar+JxwzQ6AyR8NIGKyCpjCJYAvgP3lswr+QEB34V6E4hEu54EfF L6fA== X-Gm-Message-State: AOAM530cHtRVEuWugA/MiyF7sKK+eK3u8Yj6+tbWtJIqY5el6fF9Yf0b O543CG08E1Kc7Qxq3tp+fY/GiTfaw0RByz9A X-Received: by 2002:aca:a98a:: with SMTP id s132mr419486oie.164.1621449281385; Wed, 19 May 2021 11:34:41 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id i9sm38642oog.17.2021.05.19.11.34.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 11:34:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 49/50] target/i386: Move helper_check_io to sysemu Date: Wed, 19 May 2021 13:30:49 -0500 Message-Id: <20210519183050.875453-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org> References: <20210519183050.875453-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The we never allow i/o from user-only, and the tss check that helper_check_io does will always fail. Use an ifdef within gen_check_io and return false, indicating that an exception is known to be raised. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-50-richard.henderson@linaro.org> Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 +- target/i386/tcg/seg_helper.c | 28 ---------------------------- target/i386/tcg/sysemu/seg_helper.c | 29 +++++++++++++++++++++++++++++ target/i386/tcg/translate.c | 11 ++++++++++- 4 files changed, 40 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 47d0d67699..3fd0253298 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -86,7 +86,6 @@ DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) -DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_3(outb, void, env, i32, i32) DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(outw, void, env, i32, i32) @@ -95,6 +94,7 @@ DEF_HELPER_3(outl, void, env, i32, i32) DEF_HELPER_2(inl, tl, env, i32) #ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) DEF_HELPER_2(svm_check_intercept, void, env, i32) DEF_HELPER_4(svm_check_io, void, env, i32, i32, i32) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 69d6e8f602..2f6cdc8239 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -2416,31 +2416,3 @@ void helper_verw(CPUX86State *env, target_ulong selector1) } CC_SRC = eflags | CC_Z; } - -/* check if Port I/O is allowed in TSS */ -void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) -{ - uintptr_t retaddr = GETPC(); - uint32_t io_offset, val, mask; - - /* TSS must be a valid 32 bit one */ - if (!(env->tr.flags & DESC_P_MASK) || - ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || - env->tr.limit < 103) { - goto fail; - } - io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr); - io_offset += (addr >> 3); - /* Note: the check needs two bytes */ - if ((io_offset + 1) > env->tr.limit) { - goto fail; - } - val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr); - val >>= (addr & 7); - mask = (1 << size) - 1; - /* all bits must be zero to allow the I/O */ - if ((val & mask) != 0) { - fail: - raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); - } -} diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c index e0d7b32b82..82c0856c41 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" +#include "../seg_helper.h" #ifdef TARGET_X86_64 void helper_syscall(CPUX86State *env, int next_eip_addend) @@ -123,3 +124,31 @@ void x86_cpu_do_interrupt(CPUState *cs) env->old_exception = -1; } } + +/* check if Port I/O is allowed in TSS */ +void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) +{ + uintptr_t retaddr = GETPC(); + uint32_t io_offset, val, mask; + + /* TSS must be a valid 32 bit one */ + if (!(env->tr.flags & DESC_P_MASK) || + ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || + env->tr.limit < 103) { + goto fail; + } + io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr); + io_offset += (addr >> 3); + /* Note: the check needs two bytes */ + if ((io_offset + 1) > env->tr.limit) { + goto fail; + } + val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr); + val >>= (addr & 7); + mask = (1 << size) - 1; + /* all bits must be zero to allow the I/O */ + if ((val & mask) != 0) { + fail: + raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); + } +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 68ae9b0798..86b93a010d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -203,7 +203,6 @@ STUB_HELPER(read_crN, TCGv ret, TCGv_env env, TCGv_i32 reg) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) -STUB_HELPER(svm_check_io, TCGv_env env, TCGv_i32 port, TCGv_i32 p, TCGv_i32 a) STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) STUB_HELPER(vmmcall, TCGv_env env) STUB_HELPER(vmrun, TCGv_env env, TCGv_i32 aflag, TCGv_i32 pc_ofs) @@ -217,6 +216,7 @@ static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); static void gen_op(DisasContext *s1, int op, MemOp ot, int d); +static void gen_exception_gpf(DisasContext *s); /* i386 arith/logic operations */ enum { @@ -681,6 +681,14 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, uint32_t svm_flags) { +#ifdef CONFIG_USER_ONLY + /* + * We do not implement the ioperm(2) syscall, so the TSS check + * will always fail. + */ + gen_exception_gpf(s); + return false; +#else if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); } @@ -699,6 +707,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, tcg_constant_i32(next_eip - cur_eip)); } return true; +#endif } static inline void gen_movs(DisasContext *s, MemOp ot) From patchwork Wed May 19 18:30:50 2021 Content-Type: text/plain; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-51-richard.henderson@linaro.org> --- target/i386/helper.h | 3 +- target/i386/tcg/translate.c | 6 ++++ target/i386/tcg/user/misc_stubs.c | 55 ------------------------------- target/i386/tcg/user/meson.build | 1 - 4 files changed, 7 insertions(+), 58 deletions(-) delete mode 100644 target/i386/tcg/user/misc_stubs.c -- 2.25.1 diff --git a/target/i386/helper.h b/target/i386/helper.h index 3fd0253298..f3d8c3f949 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -86,14 +86,13 @@ DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env) +#ifndef CONFIG_USER_ONLY DEF_HELPER_3(outb, void, env, i32, i32) DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(outw, void, env, i32, i32) DEF_HELPER_2(inw, tl, env, i32) DEF_HELPER_3(outl, void, env, i32, i32) DEF_HELPER_2(inl, tl, env, i32) - -#ifndef CONFIG_USER_ONLY DEF_HELPER_FLAGS_3(check_io, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl) DEF_HELPER_2(svm_check_intercept, void, env, i32) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 86b93a010d..051b6dff18 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -196,8 +196,14 @@ typedef struct DisasContext { STUB_HELPER(clgi, TCGv_env env) STUB_HELPER(flush_page, TCGv_env env, TCGv addr) STUB_HELPER(hlt, TCGv_env env, TCGv_i32 pc_ofs) +STUB_HELPER(inb, TCGv ret, TCGv_env env, TCGv_i32 port) +STUB_HELPER(inw, TCGv ret, TCGv_env env, TCGv_i32 port) +STUB_HELPER(inl, TCGv ret, TCGv_env env, TCGv_i32 port) STUB_HELPER(monitor, TCGv_env env, TCGv addr) STUB_HELPER(mwait, TCGv_env env, TCGv_i32 pc_ofs) +STUB_HELPER(outb, TCGv_env env, TCGv_i32 port, TCGv_i32 val) +STUB_HELPER(outw, TCGv_env env, TCGv_i32 port, TCGv_i32 val) +STUB_HELPER(outl, TCGv_env env, TCGv_i32 port, TCGv_i32 val) STUB_HELPER(rdmsr, TCGv_env env) STUB_HELPER(read_crN, TCGv ret, TCGv_env env, TCGv_i32 reg) STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) diff --git a/target/i386/tcg/user/misc_stubs.c b/target/i386/tcg/user/misc_stubs.c deleted file mode 100644 index df38b44d6e..0000000000 --- a/target/i386/tcg/user/misc_stubs.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * x86 misc helpers - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/helper-proto.h" - -void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) -{ - g_assert_not_reached(); -} - -target_ulong helper_inb(CPUX86State *env, uint32_t port) -{ - g_assert_not_reached(); - return 0; -} - -void helper_outw(CPUX86State *env, uint32_t port, uint32_t data) -{ - g_assert_not_reached(); -} - -target_ulong helper_inw(CPUX86State *env, uint32_t port) -{ - g_assert_not_reached(); - return 0; -} - -void helper_outl(CPUX86State *env, uint32_t port, uint32_t data) -{ - g_assert_not_reached(); -} - -target_ulong helper_inl(CPUX86State *env, uint32_t port) -{ - g_assert_not_reached(); - return 0; -} diff --git a/target/i386/tcg/user/meson.build b/target/i386/tcg/user/meson.build index 3555b15bdd..1df6bc4343 100644 --- a/target/i386/tcg/user/meson.build +++ b/target/i386/tcg/user/meson.build @@ -1,5 +1,4 @@ i386_user_ss.add(when: ['CONFIG_TCG', 'CONFIG_USER_ONLY'], if_true: files( 'excp_helper.c', - 'misc_stubs.c', 'seg_helper.c', ))