From patchwork Wed May 19 14:36:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442441 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1385417jac; Wed, 19 May 2021 07:37:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyHvXNCvnQ3M4OI3c1SWXen1OkO7g+9vjCm3Igi4HHnnwfjMbNmn6kNeM8Ty+Ja2yCOO77T X-Received: by 2002:a6b:630b:: with SMTP id p11mr10363417iog.133.1621435059066; Wed, 19 May 2021 07:37:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435059; cv=none; d=google.com; s=arc-20160816; b=YcS6vlA5+ajM6daf995hf4DbG/vqK4L00nwRfeeJ79LPaJwmgYqXoZOOHPRRHY381c pLhXI8wBbcHDNaT+soZ9LqIBFf+Ul7ozb2zsb3wS7IbZ4nfLvRkWxOCsliaYjlxD/HX1 rJtkwfYVXSIqU7Zs3b+rbaJD8IfgNXAH184Vf43RElZxZ94Sg6VuXFM/W0ZEcO1jNes0 uL8sJlmg4xp7Oyq1udjWZHBaj8ouYM9ozlTj0F1Ar2XhaI6QcCoPFbsuRB8VIbUNARJ6 rCoBIx1TchFUncANuifm1tkDFwUyNWCbAfKblqf1dFewN7dkoi9tyqIIiivPQB2r7Z7y E4dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zG635xOID1k2/MXq+MKZASd8MAgolK42+7VgFHWsBrE=; b=L2hKr+Fau9ND0Ar63CL9I2QDrrq2L+bxRlYfl3lwW4ZTsBXrPsTqV0I1UggmkItl2+ xY2N0NsOt2S1JZrhKjrU1/KzkDyCoSmJ6mJldufVEMX+FZGhY0nJzaepkM3eNBDU8zbV WwBFFTWO41uuuVEEUN7EI9oIVQgVlmVU9nhTjcc25pU2vTEJlsL7FNVAbFTufwWh0AvL IdE0Mr8UiVBje7Vj8bg+onFg+mqFVGtKH+ippTqzYQRiwVaBbthBiI9+t6fdguwweg/W t9VE4eDeHICyzdIoOoZWh3VbyCNOVs9BIR8x4pxnArYkw+yQLM3ezpAw/w98L85Dlpms Efuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BDOAaFFy; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g8si15830513ilk.127.2021.05.19.07.37.38; Wed, 19 May 2021 07:37:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BDOAaFFy; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354170AbhESOi4 (ORCPT + 3 others); Wed, 19 May 2021 10:38:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354206AbhESOiy (ORCPT ); Wed, 19 May 2021 10:38:54 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACC21C06138B for ; Wed, 19 May 2021 07:37:31 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id t11so7445908pjm.0 for ; Wed, 19 May 2021 07:37:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zG635xOID1k2/MXq+MKZASd8MAgolK42+7VgFHWsBrE=; b=BDOAaFFyisX6ZcapOca80pchy7MV6pvuLTVoq7tL9hVe78g3mtHX1u4KcxR+KS/l1F s0ICui7AisYvcrgn5Fq3pNlSOVTcwayGp0yzPvx0bsooNlS0I0qdQGX2pQ2m002mOxUd o7UY7FPxwVR20ym/34ykY6NYLAa4OBA1wmd56MPNLXZftzIajJSaJMz6Azog5/bb8gwW KFDGK2isep+R1PyWKl46dxch6UL+j2psBGeth0GeUAr0A/zN3owFojNwIGoQNaOLwBNc 1yOlz+3iK/JtsVFBzNxTavo49bCr6crtZe0p8oGda7GXKp/m23Tt/FyHNsmfawzBrkY5 XDAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zG635xOID1k2/MXq+MKZASd8MAgolK42+7VgFHWsBrE=; b=qG4WpPtPYIyHLk9TTohER2mPqrgcz9ONAXR4o03PsMewXEB+cRSN6ZqCBZAyMM7Smc nOqiamNiccWKZTLRY6IVWimjBrkA1m0RKzmbe6QVa99PfJduPI/SO9saH4kPOK0lc5vH X9987l+SXCXoFr7GqkOld4Lq1UPL21YJRZWoORcCJxD9KB2z/eMCtdvIxE3SSL6vOmvN e7iwAWvNV4hGR0x64tQjksfsJ6ruG/x0nhAeeNfTd2pWxsZcL0yX/N7FzNDySdtujyuR 248ayRvr13HvTfIBEpJPBSwmThAOENI3+B/eH/LXkE3XW60hYC9XGsM8NE6ZLltWPJOm kmQA== X-Gm-Message-State: AOAM531x5803EDIZyUnenCCqqV8OzAKV+FT/PukzVwpREGGzrtedIS+z uIelvBNWrXTPwCGLa+6dJ6mGWg== X-Received: by 2002:a17:902:8505:b029:ec:b451:71cd with SMTP id bj5-20020a1709028505b02900ecb45171cdmr11390479plb.23.1621435051224; Wed, 19 May 2021 07:37:31 -0700 (PDT) Received: from localhost.localdomain.name ([122.177.135.250]) by smtp.gmail.com with ESMTPSA id o24sm9239515pgl.55.2021.05.19.07.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 07:37:30 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML Date: Wed, 19 May 2021 20:06:44 +0530 Message-Id: <20210519143700.27392-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Convert Qualcomm BAM DMA devicetree binding to YAML. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ---------- .../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++ 2 files changed, 91 insertions(+), 50 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml -- 2.31.1 diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt deleted file mode 100644 index cf5b9e44432c..000000000000 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ /dev/null @@ -1,50 +0,0 @@ -QCOM BAM DMA controller - -Required properties: -- compatible: must be one of the following: - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084 - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960 - * "qcom,bam-v1.7.0" for MSM8916 -- reg: Address range for DMA registers -- interrupts: Should contain the one interrupt shared by all channels -- #dma-cells: must be <1>, the cell in the dmas property of the client device - represents the channel number -- clocks: required clock -- clock-names: must contain "bam_clk" entry -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in - the secure world. -- qcom,controlled-remotely : optional, indicates that the bam is controlled by - remote proccessor i.e. execution environment. -- num-channels : optional, indicates supported number of DMA channels in a - remotely controlled bam. -- qcom,num-ees : optional, indicates supported number of Execution Environments - in a remotely controlled bam. - -Example: - - uart-bam: dma@f9984000 = { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9984000 0x15000>; - interrupts = <0 94 0>; - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - -DMA clients must use the format described in the dma.txt file, using a two cell -specifier for each channel. - -Example: - serial@f991e000 { - compatible = "qcom,msm-uart"; - reg = <0xf991e000 0x1000> - <0xf9944000 0x19000>; - interrupts = <0 108 0>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - - dmas = <&uart-bam 0>, <&uart-bam 1>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml new file mode 100644 index 000000000000..173e4d7508a6 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM BAM DMA controller binding + +maintainers: + - Bhupesh Sharma + +description: | + This document defines the binding for the BAM DMA controller + found on Qualcomm parts. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - qcom,bam-v1.4.0 + - qcom,bam-v1.3.0 + - qcom,bam-v1.7.0 + + reg: + maxItems: 1 + description: Address range of the DMA registers. + + clocks: + minItems: 1 + maxItems: 8 + + clock-names: + const: bam_clk + + interrupts: + maxItems: 1 + description: Single interrupt line shared by all channels. + + num-channels: + maxItems: 31 + description: | + Indicates supported number of DMA channels in a remotely controlled bam. + + "#dma-cells": + const: 1 + description: The single cell represents the channel index. + + qcom,ee: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + Indicates the active Execution Environment identifier (0-7) + used in the secure world. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,controlled-remotely: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicates that the bam is controlled by remote proccessor i.e. + execution environment. + + qcom,num-ees: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Indicates supported number of Execution Environments in a + remotely controlled bam. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#dma-cells" + - qcom,ee + +additionalProperties: false + +examples: + - | + #include + dma-controller@f9984000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xf9984000 0x15000>; + interrupts = <0 94 0>; + clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = /bits/ 8 <0>; + }; From patchwork Wed May 19 14:36:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442442 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1385478jac; Wed, 19 May 2021 07:37:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwcSxJHLZM94FB/adw375NVDcLMH4d5EZU3/elUHM1cmJBhyWOGcCq2ayBpklg8ou8tOVSJ X-Received: by 2002:a02:7702:: with SMTP id g2mr13199949jac.111.1621435064937; Wed, 19 May 2021 07:37:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435064; cv=none; d=google.com; s=arc-20160816; b=hFeZApzHX1nRQqvirwZey/absV11mdXfv0soE2KA5ysdy/M8Ag8DsNrbZXRSLjurk8 zrt/S2o/pTYSeIbhB7Fc62tItQOBAnhRKqL1A6JCZQzcEu6xFRe2X2imeO7muiQ+Sq/I zJqTOkJbiYrQItWRBrUu8n+mqIFnoSAO8FS6sgQwKOhGJviYjasYgfwREPLbyvZGeJ06 QqnTK4enJeqwYaQOdmc6yiN6xD5Nj4dOpImfazWHyavoX9yZ1/L5Vlv6tbQ0AFtsNTuJ 68FfqoUewZ+W7h6leoGoEodBI9BS+047l2iKi6c3BW4PjqQIpez7RWy/Aki8vHOL+yCE X6Ag== ARC-Message-Signature: i=1; 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 02/17] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Date: Wed, 19 May 2021 20:06:45 +0530 Message-Id: <20210519143700.27392-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add new optional properties - 'interconnects' and 'interconnect-names' to the device-tree binding documentation for qcom-bam DMA IP. These properties describe the interconnect path between bam and main memory and the interconnect type respectively. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.31.1 diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml index 173e4d7508a6..d2900616006c 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml @@ -47,6 +47,14 @@ properties: const: 1 description: The single cell represents the channel index. + interconnects: + maxItems: 1 + description: | + Interconnect path between bam and main memory. + + interconnect-names: + const: memory + qcom,ee: $ref: /schemas/types.yaml#/definitions/uint8 description: From patchwork Wed May 19 14:36:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442443 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1385740jac; Wed, 19 May 2021 07:38:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMr362+wCvXC+5pCVs8nwUmyOa/SjCr8eDKHqx0rdC3mMSWzU2vLxepkAPJipy7lyPeB2P X-Received: by 2002:a05:6e02:190f:: with SMTP id w15mr11032958ilu.13.1621435086926; Wed, 19 May 2021 07:38:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435086; cv=none; d=google.com; s=arc-20160816; b=cuAJAAfrN+0+5eREjjXjD/PVix6Dumnfiqe59HoHmuNSYIJYe2Ur7rJpgqT4/RS/fk 1V7gCr16LVo4+FAOwcTPARj1l5+H+91OAqbWp8dqGkNJkaM/ccYYZUsaVrnGfgCeEgG+ OoETq0wEbRuyiKHraFQUdd2TiDxrEx6jSVQnsDcsMG0TLBwsnjhUlMpjq8P0d/loblbB rs+RrwyRYuHb09sI8Q3F95zgi/LWwcHE2orWt8opdOfEwBDDNROBuPRHhMIhVqmn68Fz J/ir9NFbuEYvslP0rYgJyMomuO60NTM+6qWr+ge78BfqmVJYPLFEPCuVD53m8lqW9FD8 8uKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tfYY0SynHLUvKImA0WJS6vFoZYpwQQ4sgm9paKqwl54=; b=sNx36JjVaYMsWjTHNY0LwYcc19+58677HTlIHJHyFJwl2u4npVyKpNYHr/bbQE4jH0 7PJGQLc+2C1cpkn7aazhkbpVPfHuqrTj2Wu165mTFi0cNTnD38TceKNsFEXvBn/5nm+z dieG/Qzoa1JhKMhleVoyzTLpH7srHdOBIEhnTb6kQsE8Qix6sciE9K0ATR4xX5sRjUgb el3qiLroMBApoPmKOh0YVO/rB+rhjmZMxEY9L1Vey9dkZOCwAe5RfZP4y6QMiiC/EkHm Oqueoxwp4Ts8wbtMGT16N76yyS+TW177Ftn/qpRms5yOerW9r9+S8fsxe1HIVkwbnohz fe5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LMDyQ/zu"; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties Date: Wed, 19 May 2021 20:06:46 +0530 Message-Id: <20210519143700.27392-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add the missing required property - 'iommus' to the device-tree binding documentation for qcom-bam DMA IP. This property describes the phandle(s) to apps_smmu node with sid mask. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/dma/qcom_bam_dma.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.31.1 diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml index d2900616006c..2479862a3654 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml @@ -55,6 +55,12 @@ properties: interconnect-names: const: memory + iommus: + minItems: 1 + maxItems: 8 + description: | + phandle to apps_smmu node with sid mask. + qcom,ee: $ref: /schemas/types.yaml#/definitions/uint8 description: @@ -81,6 +87,7 @@ required: - clocks - clock-names - "#dma-cells" + - iommus - qcom,ee additionalProperties: false @@ -96,4 +103,8 @@ examples: clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = /bits/ 8 <0>; + iommus = <&apps_smmu 0x584 0x0011>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; }; From patchwork Wed May 19 14:36:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442444 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1385796jac; Wed, 19 May 2021 07:38:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzcCfqhSc5/05nE44kRMuHXjc1WofXgfr51VyUvWA0KmDb5R+loE6zuY0SEU5kJvb2zpDRe X-Received: by 2002:a05:6638:155:: with SMTP id y21mr13747548jao.62.1621435092129; Wed, 19 May 2021 07:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435092; cv=none; d=google.com; s=arc-20160816; b=s0DQC3VpLauxd/hyNzpPe41/T0Cpo8tbRw9PUPYzr8iGQSIxc+0G31AQ4g8nI6BUYo 7lRe8q6ed4DBTAzQRSjJmv39t6MYh/XihoMFXJy2iwhdLHoEKn6z8KP61ldW8FMqUSvw XU7OPYMPU3gw5h06VNRYfTh/cDYrVpriFMRT8lN0DrDXaaGu8yBd0y6SAROEV78t/l5y 7s9RuaHfAHer8QYsh9iJCYXqk6PNJH5mE5dac7Y+uxJ2eLMFPQPDmTF3p47ZzGmhZC+8 Y3ILP6MZMhAL+CXgWyKoNks4vMWC4/Du6SSZb6Tcz5IXhaouG/Caw+c2xUChIm5gNP3j gezg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZOrjrBtPIyQIufzW+o4HH7ug0OM7ZtmcrQX7KbEW7to=; b=k6ODn10+K64PeMjoattOChbMJcqp1H/g9SakWnVTE6r+EkpwQxBdODJ1WTdJQTryGl sllRFZ4BDC9BjHiww98oLOIpN/WMMlCI8HzYH8tzMpbRmRNxDiGgq0iXYzAKdu9S+sB7 2Z1nsnQLs1fW6QIK5+bOGGfyeKolpgF4EbnYocBk5tXThw9w2NE1aHYx0+oVLQyUlUxe pyw6tJfyKdAMef9JUmlWtifiLrelxeoYdfA1oHyLHT1TH1MXjPmFcSGknwtgAO31S15U BdG8uHhOXZFIffTsOMU5xVl6dGEYWa4nODFswWVwYlK46rtPWs6vssnT6eF28j+5wk+n vN3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M545Dwsq; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml Date: Wed, 19 May 2021 20:06:47 +0530 Message-Id: <20210519143700.27392-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Convert Qualcomm QCE crypto devicetree binding to YAML. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/crypto/qcom-qce.txt | 25 ------- .../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++ 2 files changed, 69 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml -- 2.31.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt deleted file mode 100644 index fdd53b184ba8..000000000000 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt +++ /dev/null @@ -1,25 +0,0 @@ -Qualcomm crypto engine driver - -Required properties: - -- compatible : should be "qcom,crypto-v5.1" -- reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "iface" clocks register interface - "bus" clocks data transfer interface - "core" clocks rest of the crypto block -- dmas : DMA specifiers for tx and rx dma channels. For more see - Documentation/devicetree/bindings/dma/dma.txt -- dma-names : DMA request names should be "rx" and "tx" - -Example: - crypto@fd45a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0xfd45a000 0x6000>; - clocks = <&gcc GCC_CE2_AHB_CLK>, - <&gcc GCC_CE2_AXI_CLK>, - <&gcc GCC_CE2_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml new file mode 100644 index 000000000000..a691cd08f372 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm crypto engine driver + +maintainers: + - Bhupesh Sharma + +description: | + This document defines the binding for the QCE crypto + controller found on Qualcomm parts. + +properties: + compatible: + const: qcom,crypto-v5.1 + + reg: + maxItems: 1 + description: | + Specifies base physical address and size of the registers map. + + clocks: + items: + - description: iface clocks register interface. + - description: bus clocks data transfer interface. + - description: core clocks rest of the crypto block. + + clock-names: + items: + - const: iface + - const: bus + - const: core + + dmas: + items: + - description: DMA specifiers for tx dma channel. + - description: DMA specifiers for rx dma channel. + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include + crypto-engine@fd45a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0xfd45a000 0x6000>; + clocks = <&gcc GCC_CE2_AHB_CLK>, + <&gcc GCC_CE2_AXI_CLK>, + <&gcc GCC_CE2_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + }; From patchwork Wed May 19 14:36:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442445 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1385807jac; Wed, 19 May 2021 07:38:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFcd7WTaKsNv4brTSUaTIuG7+VGvlGoq1sEazNPsUqOu/TzHa3NnLB8bq6q2uj4p6qNwNd X-Received: by 2002:a05:6e02:156d:: with SMTP id k13mr10765867ilu.149.1621435092938; Wed, 19 May 2021 07:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435092; cv=none; d=google.com; s=arc-20160816; b=F4zK2gp89CnM16kXyrkjxyE089y6wBEaSu6V6lSgU/6YKb8KsM/tHQoO3mvl7WfL6J 5eZ047XvHghHFn2SMjCUyuPlIuvGWHNNop2gBnWidtkYZ/Cl9sDdsE6Qk7EQi+wB0+OS m7sPCz0YQM3fdGTzrL9szaX/sNoMGbL+gt1v+E8Qvv9OWqmtamNSpNl0muzHu8hwz1Sf krhK1M9ZtwK1CnM7PcNNkD3Wwml64tiRdyhDtUG2Mk2sbjYe24J+Bd/GXWQoqPo7NeuF 834RD2iCZPGeNFrvs31HSn7ozat1HUdriM5NjrjsjcpD1n7bBdDfz0TMpMz+Oda+rIVs VOGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gLAnCBqQqsONCjJBDJE0yrv+GAq9KPhwa4QXZbYyuMc=; b=S0R6YiHq9rEwtXcNdjuIQa9OuRuZuxKTNc1qTkg2B/+JZccimtwq0C5RxWIN50OQFN 7WYDjQRDATzcLxIVoBDHw0QPPZn/Gqhg3AXc+RcL+lXjOdwRE9yHM8fu5XRQWi+o9bF0 xtlNlqXKh/K0QiHoPCJWYeDRNNKjKCn6eX07IAtAhnG+ZHnEYzpq/jMywzTMIv0lnjRa 1TEQLgR56VF4kP9HIvGSvGfr9zpjHzcI//BMmpSIqnwL3YnKL2uy3HnFSjBchJf1xzoa sOvVn2rfgANZgLPEgayCRgQZAbne/RWywpWfj0uQHSA086Eka+U1J4Y5KuoJD7ukzLm0 itdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c9bg2n3a; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 05/17] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Date: Wed, 19 May 2021 20:06:48 +0530 Message-Id: <20210519143700.27392-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add 'interconnects' and 'interconnect-names' to the device-tree binding documentation for qcom crypto IP. These properties describe the interconnect path between crypto and main memory and the interconnect type respectively. While at it also move 'clocks' to the optional properties sections, as crypto IPs on SoCs like sm8150, sm8250, sm8350 (and so on), don't require linux to setup the clocks (this is already done by the secure firmware running before linux). Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index a691cd08f372..f8d3ea8b0d08 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -34,6 +34,14 @@ properties: - const: bus - const: core + interconnects: + maxItems: 1 + description: | + Interconnect path between qce crypto and main memory. + + interconnect-names: + const: memory + dmas: items: - description: DMA specifiers for tx dma channel. @@ -47,8 +55,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - dmas - dma-names From patchwork Wed May 19 14:36:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442447 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1385900jac; Wed, 19 May 2021 07:38:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyNu3KiQ6J+wDmbX3KRg9vvOMEDOsBHN0TF31nnFTzU673B96GvszKA0NpIhlialqZCfXp5 X-Received: by 2002:a02:688:: with SMTP id 130mr13604578jav.48.1621435097363; Wed, 19 May 2021 07:38:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435097; cv=none; d=google.com; s=arc-20160816; b=VJtM3El2UezngbAnaI75DrcHsYRgnvre0t09I19RU4Ry75SaDXdDedbPwSAGyS47R7 552IJnS+KXutVRRanMlfAUCYzRZI5PPMlnLvs+6kwp60Soc63fQBO9JsErMBkalcLLGX pKEM8C56s8rhcu/KfhLMsKjq0f/nLInuR8PQm22lx+d4VMza3LMBj98qV7o2L13VnnYd we+QJgXswidTL6e5uYQVz0re/YSZs6SwaQ3+9pjqegcnbmcxYunEcm+hhSiJzFgAXvNT i9wl7jQ6Fj/FYMByEQJGT+LULHWUtpwtNlsW2UwZi2WQgU6X7V2SZEJhapNPh4WgOmAO qoYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/W6azUUE1Twja3FY7bt61gqSPj92cSqiD8Un8maDnxA=; b=tGrXP2Ounj8ogrfOBq6ehqcUEecpzVW1G6H6EVJJ0R+hU3esjJLMXT/0IKiwfgo4u5 qMhAAEpURHubje/ro44BZQApEqOzNEZ/92hZjJumbyI40PC/847EWpRG2p5BYnkUEGn5 /WyQqi8Q39ChWaYzKQamppIrMTSvovVMHiNrLS/8P4kRYyPZ/IYyhpq4HIZRDdnPsiaj 3zacB/jRkJqV9Iz+iEeI60evU3PYz8Md3pVyBhStRDpN+e0ve2EZrrOWQY1J91qVTJsr lCtTU/4jBXhv/gBhNgm4Fd4U2KnVGIfbh+bOWzwQzuLBGFZHSKt1MZYUkdNJmJj7G6CL j2kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kCyBhJZG; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 07/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Date: Wed, 19 May 2021 20:06:50 +0530 Message-Id: <20210519143700.27392-8-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine."), we decided to use the value indicated by constant RPMH_CE_CLK rather than using it directly. Now that the same RPMH clock value might be used for other SoCs (in addition to sdm845), let's use the constant RPMH_CE_CLK to make sure that this dtsi is compatible with the other qcom ones. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.31.1 Reviewed-by: Thara Gopinath diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d..2ec4be930fd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2316,7 +2316,7 @@ cryptobam: dma@1dc4000 { compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; - clocks = <&rpmhcc 15>; + clocks = <&rpmhcc RPMH_CE_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; @@ -2332,7 +2332,7 @@ crypto: crypto@1dfa000 { reg = <0 0x01dfa000 0 0x6000>; clocks = <&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AHB_CLK>, - <&rpmhcc 15>; + <&rpmhcc RPMH_CE_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 6>, <&cryptobam 7>; dma-names = "rx", "tx"; From patchwork Wed May 19 14:36:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01048C43460 for ; Wed, 19 May 2021 14:39:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D833761244 for ; Wed, 19 May 2021 14:39:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354402AbhESOkR (ORCPT ); Wed, 19 May 2021 10:40:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354314AbhESOj7 (ORCPT ); Wed, 19 May 2021 10:39:59 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FD7EC06138B for ; Wed, 19 May 2021 07:38:19 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id 22so9649282pfv.11 for ; Wed, 19 May 2021 07:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N4+Pmvy+Kn++u+tJ4TtTc+C+SSq9T8K7CwVNxOIPf08=; b=x2HRCTgG0GipiWBQV07MrWomyjGTmV7e4awp8zrWM08SFfCgZhcczG3pxZ8iD2a1/d kAyVzuq69LQyP0DH5u32JgTO48NM0M4agymuMF3Y9akEUjkPGSnpqualcBZl5Ue3lLvr h2+udxNYvoW8ZM9ymO8oRwyLaJkasizAM7pMMZLyQJzZoVO8lpaitttXtcVF+I5FLH89 WN1gbQo2LRRpT5OPvqlATjjUahEWcsUSi99+xxRd9LEynK5VUH/lCulfveJozVyPs5OA uFgEO51te7ziVGkJRdeKwxlRDLlhzFDQX3T5VDhwxhCq8bjJ6PbcXW5aCW/02q4cidEr ISIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N4+Pmvy+Kn++u+tJ4TtTc+C+SSq9T8K7CwVNxOIPf08=; b=Wlrmrjize2VqpQ0owEaEbuC3z6zAHCXMsTiIM1/v4w7c7Pke8tjmoL0HRb9NcatiVT USPfTfmssd+gHz9p1NsGhhDBNP61+AcLJtxmnp9cT6oVTGZOG/6UotAZL7UPNThKJZNN RCaIVWs0oVZQQCkzg2/C9jgMlznVfzrwu+w5xB9bKJWSj0/ePqbXgNRWWPWQeM/JbJVc fpbzGMEWm8sWBBSPetC670ySzN4FEPVhV0U0e596oNgkeNNxRBc1FigMjyWC4pPQDDYS 2lFdBuXK4IiHH+EJAjpbb29cZHQnPLhMivuHhD8Mr3QlyKqJ6vJuux8d0aW/5xhDMMla ymdw== X-Gm-Message-State: AOAM530mcdyj+hCcfOBHLjgtsijACE6dBffr/JqxN3em9eegJMvcIAq9 jHEFRyo5+QKsAaCMss786HnnSg== X-Google-Smtp-Source: ABdhPJwQ8L+n4Xe7Qq4tu9SJumb4UjS8KaJ/uz1/vXqSGC2KvOezTn5DRRaQ0RPlEN0HrPsxQ4PLvA== X-Received: by 2002:a63:bf4a:: with SMTP id i10mr10994699pgo.200.1621435099126; Wed, 19 May 2021 07:38:19 -0700 (PDT) Received: from localhost.localdomain.name ([122.177.135.250]) by smtp.gmail.com with ESMTPSA id o24sm9239515pgl.55.2021.05.19.07.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 07:38:18 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce Date: Wed, 19 May 2021 20:06:51 +0530 Message-Id: <20210519143700.27392-9-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Newer qcom chips support newer versions of the qce crypto IP, so add soc specific compatible strings for qcom-qce instead of using crypto IP version specific ones. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 4be9ce697123..7722ac9529bf 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -15,7 +15,12 @@ description: | properties: compatible: - const: qcom,crypto-v5.1 + enum: + - qcom,ipq6018-qce + - qcom,sdm845-qce + - qcom,sm8150-qce + - qcom,sm8250-qce + - qcom,sm8350-qce reg: maxItems: 1 @@ -71,7 +76,7 @@ examples: - | #include crypto-engine@fd45a000 { - compatible = "qcom,crypto-v5.1"; + compatible = "qcom,ipq6018-qce"; reg = <0xfd45a000 0x6000>; clocks = <&gcc GCC_CE2_AHB_CLK>, <&gcc GCC_CE2_AXI_CLK>, From patchwork Wed May 19 14:36:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442449 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1386704jac; Wed, 19 May 2021 07:39:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxy+/a8I9t8nxvkwOtZ/pkiW2S3TyP1AqzXWbmXmq5xjU3U+FHvdPXl0DeMNHBttBByDknR X-Received: by 2002:a05:6e02:df2:: with SMTP id m18mr10545903ilj.77.1621435154009; Wed, 19 May 2021 07:39:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435154; cv=none; d=google.com; s=arc-20160816; b=wAzti9bgiHGlTsfWF1HWXVGP8URpah2+Mvx563qBuW4WWqOqBm0ovwkE6es1vELqJw znkH+5/Sjz0ONDGo9JyHAm1I76AA44iKwzvoUeL4ZmTGED7gBkfPS1mkCPXH0eoSgTsD ObxcwU/iwItMoaSoOKQOC8oiniHaGPKF7H9y5FjzhlFvFfx/89moAeVZkdgV54xGNHpN cz+bzKa7EaJM0va6lXB7WOJGRAHro8n1Gm+pGrShAMtUp6JvBxg0OsX/D59Zo0zAcP7+ kXXC7pDhlbS7KaIIVyI44QONcwn2NNptu66OwVvKX2TpYDDopD+45AXeQn/+N3+rxVIX KUeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IaOgy5E/D/bWKnSjfGh3VxC5Z9iVmzAmqxR9MxuONrg=; b=SVgmGExhLToY0xHQkcKPecPyfUlNLswDd1ObbJxhgSjTVt7jp00h4VoTsnjxaQcLWA 8vb0JV1ph+UlWkJwETCiwIHL3isr4ePdhFcng3+ccOQoKWtqGxwSCtJnt2X/YHQDCioP LILAuQEatn1SmtJNvv1zqnH+h6g3eyJDqHhbfyDLVojO9BwKtEbPCEyYB7RUHX3gEn7v D+6hnH8GVaKRBjRgoqRW1eXRWLBWvwnlldIX8EVjrT6CfV0GijTy4Xoo6vg56vEEO1AE 8g8PiY/kh/RpI8erqlh4aZwLodv2Ge9EN9XlkEGWrPdFXXE9zcIRe5hJzdDYR7PnUt9m s47Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vvm5HPOn; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 09/17] arm64/dts: qcom: Use new compatibles for crypto nodes Date: Wed, 19 May 2021 20:06:52 +0530 Message-Id: <20210519143700.27392-10-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Since we are using soc specific qce crypto IP compatibles in the bindings now, use the same in the device tree files which include the crypto nodes. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9fa5b028e4f3..978c34f176de 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -205,7 +205,7 @@ cryptobam: dma-controller@704000 { }; crypto: crypto@73a000 { - compatible = "qcom,crypto-v5.1"; + compatible = "qcom,ipq6018-qce"; reg = <0x0 0x0073a000 0x0 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2ec4be930fd6..6423991fa303 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2328,7 +2328,7 @@ cryptobam: dma@1dc4000 { }; crypto: crypto@1dfa000 { - compatible = "qcom,crypto-v5.4"; + compatible = "qcom,sdm845-qce"; reg = <0 0x01dfa000 0 0x6000>; clocks = <&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AHB_CLK>, From patchwork Wed May 19 14:36:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442450 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1386794jac; Wed, 19 May 2021 07:39:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZwpj+Sak3l6A28g16MwO5Ou8IKqowONW20nyzZOb8KSoOsRyO+/twZ63kGSbmDbB3HEZb X-Received: by 2002:a92:c26f:: with SMTP id h15mr10155830ild.298.1621435160990; Wed, 19 May 2021 07:39:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435160; cv=none; d=google.com; s=arc-20160816; b=JdJYWc6MzZ+UFxv1p58ZDcmBcphQ11upkudD2ZXb+Ni4l4kZLKLx4H0eWJ/RuI4Q/7 nM0R72efk4gKtXeHZ68EeH5XQ6L+vXJgp9PouFPMtRD+8+KkJ/oEDd9GCJAWA2zYHIoX Uoeu+TKJklSjvE9TBkGF0lojgo9BakR5Ohe/Zgwk+RMjcQzbZsGJagsY1bWE5fLg246K i//YtHuqkKAjis5GKCB7yBYPQSvQ0GFC5i0Pr6HX8baLvj7IUVU2qxGUH+CeQkqAOfy/ HyZgBSPP/3MqxWnCVWsA28sJqOhVcaQncXS2tU4tnpTiAWlDL8JMk6/+Um6VWodYkcqs ji3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9/tRHikibb3VDcl2hDfDt+wuIOHwmbk3mgz2i/PihKw=; b=yuD/u6KG4uXXBWI5AQ5xhe4edB5Lo2+4E1XAbEilACRO6XIi8o9sDOtZP8qbvwekFJ /3E77o3AJBr6Bxv5D8Sk8Wc+1jJS2Ycg2wKj0jqWxc7AE5qo48NZnVpWXy1pdjGUIFi1 eqwCAx2YLSGoSfxaNYyy8BK3Pim42yw1Bv8vCCmXK/ByBt5MLgt4ADpL+RBWGhPxOTBi YvCR6unl/r7vsGqljOIiUQfH4/9Ync4YZN45+IkJFxrElEAJPSs/2LQBsK87HqNRi/Y4 X3HGKESKSsV1/KrJLAsSQbjsnOxHJc3urvBjtkUSscEXWRo0d5WXuu0wm8XuCC6Qe5MB VmSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u7a89WZV; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 10/17] dma: qcom: bam_dma: Add support to initialize interconnect path Date: Wed, 19 May 2021 20:06:53 +0530 Message-Id: <20210519143700.27392-11-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Thara Gopinath BAM dma engine associated with certain hardware blocks could require relevant interconnect pieces be initialized prior to the dma engine initialization. For e.g. crypto bam dma engine on sm8250. Such requirement is passed on to the bam dma driver from dt via the "interconnects" property. Add support in bam_dma driver to check whether the interconnect path is accessible/enabled prior to attempting driver intializations. Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Thara Gopinath [ bhupesh.sharma@linaro.org: Make header file inclusion alphabetical and use devm_of_icc_get() ] Signed-off-by: Bhupesh Sharma --- drivers/dma/qcom/bam_dma.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.31.1 diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index c8a77b428b52..4b03415b8183 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -392,6 +393,7 @@ struct bam_device { const struct reg_offset_data *layout; struct clk *bamclk; + struct icc_path *mem_path; int irq; /* dma start transaction tasklet */ @@ -1284,6 +1286,14 @@ static int bam_dma_probe(struct platform_device *pdev) return ret; } + /* Ensure that interconnects are initialized */ + bdev->mem_path = devm_of_icc_get(bdev->dev, "memory"); + if (IS_ERR(bdev->mem_path)) { + ret = PTR_ERR(bdev->mem_path); + dev_err(bdev->dev, "failed to acquire icc path %d\n", ret); + goto err_disable_clk; + } + ret = bam_init(bdev); if (ret) goto err_disable_clk; From patchwork Wed May 19 14:36:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442451 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1386835jac; Wed, 19 May 2021 07:39:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyh5OYLR2t/7n/5ffAgkekfdCGzclFR/+COGEetvLBV/SqW0hd+cq5eebvTJ0aMTtIJK0gp X-Received: by 2002:a05:6e02:ec7:: with SMTP id i7mr10950551ilk.147.1621435162833; Wed, 19 May 2021 07:39:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435162; cv=none; d=google.com; s=arc-20160816; b=tIGYdMGEbdHvXF4eyZZREwHH3bhMR4FfqidoO6zfvQzouJwIf3n2Rd3GS7TL+dfL8E ZBbAwWw3SWf7mgYS/+cqyqmIr1x/YJFQTexPcPQkDxWQJNErangWdLH4YgP0R2v+NZOr sf33F7SyfDnOVRuRGm+uiUPErL088H3aWConqM0aXoL9orxViCmNTsS+FheT9a+h3MKl 1kMsdzp+RDeXxSovK4uZ7eETO/DtbqASAAVioUzbcVbHPZTA/ojyvW4EzNNbIdP2BH+/ RWfsPS9MXWGOAHXnKBgkwUs+N7gNcd13zSuMZ29rQ78Sw415FNDVygN2jo/IYTozOnR5 noUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PDydCz783kyI7jNgitJR8zCb8Ar4M6klN2ivXhhgevM=; b=vhK6TZReqERgsgj53otrex6Ha+J6ZOLWK2iJNBx5p13MYX0aE2asKB+macZcgVcosL CYWw74hRzPMelpKVRJsVxFaWhf8YgMTuCIOzw+d5VV5ntkMdkwYYVPMG2/n8ZHFoxexM gkp46gRbmh04AJe1RsKmqcRVY+l6UFPpcGYPS3zhjRzV6faZ0dOuoipaoGqRi9cpkyEw ZKl+faAI2ruWODlahg1/PvSYW0ILXXLJTXpbAEwsBKxqTLVyeZT+S8TccjGX9gGOBRRv qDnejVGH5BD5/PmXOZpAPwj6B0QjgINGrNdDp3a/JKGocy1XJU3tEdUNI3havdA09V8/ NDoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xDVjMuiR; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 11/17] crypto: qce: core: Add support to initialize interconnect path Date: Wed, 19 May 2021 20:06:54 +0530 Message-Id: <20210519143700.27392-12-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Thara Gopinath Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 etc. requires interconnect path between the engine and memory to be explicitly enabled and bandwidth set prior to any operations. Add support in the qce core to enable the interconnect path appropriately. Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Thara Gopinath [ bhupesh.sharma@linaro.org: Make header file inclusion alphabetical and use devm_of_icc_get() ] Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 12 ++++++++++++ drivers/crypto/qce/core.h | 1 + 2 files changed, 13 insertions(+) -- 2.31.1 diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 80b75085c265..89a17b677607 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -21,6 +22,8 @@ #define QCE_MAJOR_VERSION5 0x05 #define QCE_QUEUE_LENGTH 1 +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 + static const struct qce_algo_ops *qce_ops[] = { #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER &skcipher_ops, @@ -202,6 +205,11 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret < 0) return ret; + qce->mem_path = devm_of_icc_get(qce->dev, "memory"); + if (IS_ERR(qce->mem_path)) + return dev_err_probe(dev, PTR_ERR(qce->mem_path), + "Failed to get mem path\n"); + qce->core = devm_clk_get(qce->dev, "core"); if (IS_ERR(qce->core)) return PTR_ERR(qce->core); @@ -214,6 +222,10 @@ static int qce_crypto_probe(struct platform_device *pdev) if (IS_ERR(qce->bus)) return PTR_ERR(qce->bus); + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); + if (ret) + return ret; + ret = clk_prepare_enable(qce->core); if (ret) return ret; diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 085774cdf641..228fcd69ec51 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -35,6 +35,7 @@ struct qce_device { void __iomem *base; struct device *dev; struct clk *core, *iface, *bus; + struct icc_path *mem_path; struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; From patchwork Wed May 19 14:36:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442452 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1387012jac; Wed, 19 May 2021 07:39:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJypkXe9su3kXFHK261BqRe2rXrlLj5bm4DI9Koo0FmwdhbRj/EZgBzpom+vvItdUGEJwmy7 X-Received: by 2002:a05:6638:138e:: with SMTP id w14mr13313124jad.33.1621435175972; Wed, 19 May 2021 07:39:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435175; cv=none; d=google.com; s=arc-20160816; b=Oe0fGZknArQrPHVz8GAY08xhwU2O51quJM2zVw+3KP0tZPDPRlkdU3wyguX7xGew0C B3NrMp93HKB92YcBhxCwT/ncLnFhN5vjTx5rSA0ZLqJ0DO5KJddB4GtcOiKpoGw/m6e6 8FaxN2qA820XfRu6MM7dDJyb3D8rfIa8oOCRWCdxdF5hJaoDAbbLYx6zq5zpeuuGJALw 2cpk0I1oHk3B1iE+L8jjMM1KGkMi+c0eQDzdbtX/fjTEgoZnJ8IfYKkQJDKmGHxboiv6 WXzZ+hXainq/nTPkzluBdRdI0djG+xgYBPMGLoARI4PCsIBHr9EGdXO7a0mG3z2ZM3Tf PJaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TY0eJSU95uLiOCWXW1DYk1X5OH/Ime0PUPY+J48rkIg=; b=pBtO/5EO4mnEFeTT40PyummjHJhAJAahBuai0iZ8FjXT2U2l6DeiRV5XH8ekfdyTxk f/Hk3yC5HbQEC+VwWOzkxnUsDs6lOD0U+uXBsLrCCwoavV1TvdM9V1RYKaqVLGsHjUiQ ex/4AMN8dxhshFvYDv8/TEySvbkyecvmNp3bVK5bBzO4PCHlasbiRvyJ6zjDlvCQywv5 ildTzutQWLFgLrGqIQOvztz94tVWTaMt4EMoZio05FTeZNOQvksBRECY99BdhKbC8r8j 4C+eiDiMZIj1NSg/8TbtP4jrnHAjhj3P7Rd6Pa6oAFv1+MjV3lsAHp4nL7dsEa+WtK39 NEoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F3d7wUPy; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 12/17] crypto: qce: Add new compatibles for qce crypto driver Date: Wed, 19 May 2021 20:06:55 +0530 Message-Id: <20210519143700.27392-13-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Since we decided to use soc specific compatibles for describing the qce crypto IP nodes in the device-trees, adapt the driver now to handle the same. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 89a17b677607..905378906ac7 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -285,8 +285,8 @@ static int qce_crypto_remove(struct platform_device *pdev) } static const struct of_device_id qce_crypto_of_match[] = { - { .compatible = "qcom,crypto-v5.1", }, - { .compatible = "qcom,crypto-v5.4", }, + { .compatible = "qcom,ipq6018-qce", }, + { .compatible = "qcom,sdm845-qce", }, {} }; MODULE_DEVICE_TABLE(of, qce_crypto_of_match); From patchwork Wed May 19 14:36:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442454 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1387167jac; Wed, 19 May 2021 07:39:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFAzyVLcy/xbXEnYKra810AxZof2SKOj5mNk3ioJTeGy5BewnDOL4bw+mPyC1r5rQFAi+a X-Received: by 2002:a05:6602:2d0a:: with SMTP id c10mr5920696iow.12.1621435187644; Wed, 19 May 2021 07:39:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435187; cv=none; d=google.com; s=arc-20160816; b=THYtsYHwdSa3DmIEyJKN3KXGx77sBt3uhkn3s33qVz8wagWWthuNVvoEaA16pBvSyo WR7qaUW8jMUlKlCH0Cth8SGNI5pVMmk6pNmVFJnbQFp/UNG3qyi3tQ51jz1uePP+sNzl SxWr9vz1EAMySKFmBlA0j3EbIKBrE9lUVEHbcVXQT3S5ReYveaH+4Oj9yJagbYo+jmSt 5A/Bz9JGAmXBcGq2inuK/6x9DFQ9Rm30XgYB+N58/6mbcoQHcmg0CSVe9i3VlL87u17A WPbd7kyBgBtc78s/kHRrVnjYw8pVqLdked6PwZgkBlNS4MEdgBKDmmHdV3DCSKm/8674 UGHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DJ0dnnuzoeTgYR3s2q2rVPLNWq3NbJZWo1BzkyjqRwk=; b=tX9kryCVCj3ssrQa7+BakA46GRl4VepqWr0A8+aWEjvFxEIk6FX1LKJAyk6NhMWZY7 b94hZniFbS+ui8bLUP3d+s/PbjHGNArWFb6n8VM9l6gkt3MMJz+HLc7F+htE2mtPafCx Nma0drfGAN949G/EfXBpE28NM4kgQ52Iv0C5QTAnwo9Po2Osr7fpRuOjLgqfVnt3hsR0 vIIQWozEixSMB9cjZW8n7gyPG7FgJVoYv6Co9u7fyBy5Hxfug7neOybCDwe+xEjfvZw7 0CVOn+WgH440LIDo8g35y0CkK8J9PRXyiMzvQjaVZBkx6Uk7ZHzP1Y2rayPbnoxU/L6e LsoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m/uNEaF4"; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 14/17] crypto: qce: Print a failure msg in case probe() fails Date: Wed, 19 May 2021 20:06:57 +0530 Message-Id: <20210519143700.27392-15-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Print a failure message (dev_err) in case the qcom qce crypto driver probe() fails. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 1 + 1 file changed, 1 insertion(+) -- 2.31.1 Reviewed-by: Thara Gopinath diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 8c3c68ba579e..aecb2cdd79e5 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -300,6 +300,7 @@ static int qce_crypto_probe(struct platform_device *pdev) err_clks_core: clk_disable_unprepare(qce->core); err_out: + dev_err(dev, "%s failed : %d\n", __func__, ret); return ret; } From patchwork Wed May 19 14:36:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442455 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1387345jac; Wed, 19 May 2021 07:40:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzDFS9dz/gNu/R5Z0R78MQvamGgYMWzrtjumwxdomkcQfR0HWtIEuJLKMk1oYdH8XaZuCR6 X-Received: by 2002:a05:6602:2d0a:: with SMTP id c10mr5921429iow.12.1621435201404; Wed, 19 May 2021 07:40:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435201; cv=none; d=google.com; s=arc-20160816; b=j9GFwB+WUFuH1w03MFVsX7/ITUfONnVFXPmNxbM9RqvdyicWwT7kgfYr09OeBP4wq0 pHV7acN6RlWGgUNpMpIue9Oq3/mgxx+NdCMEYLDYXuxS87MEWxdkiGCCvm0jWPbwwrYh 0bAQe3GXczYCOPJ78iV1PS/b8QBiDmhunDNd2XW5gO7WpHo/IhtVGzz2hqdaFryfJfz7 jqx1OG+NBfAoHNCVcaQrKehzs+yLac8G9JjTHF4H2XDTlhb76FghheTeAZNUUiS+MsQZ juV8Ly3gvmZqnKvZSugSjhSUgdQ4yYWHuj/wAMtdMuz3bTE2XqwyaIMfnpcwzqAE4tj2 lg4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GuVgCqdDVbpVqTxpQsc56DvhHyMstWv4OtUHtXIMiUo=; b=fbBza/QoE7aTpu9DvrDO7UULniY2uijgSRPSqADxBh18B3451+Q/mhcJ+3r3mcp/1D 7WDM3Dypl9EgeqqwZqFuMF9vUE0YvQol2GOgKAtz2XPUeWd1WEPjAzWKI+RUZPXUI3QW ZDMT9QmKUoqG0/aAiP9lObQXEjrWXlCX3J5waysm60es70ufWxjuy4t7kIqrxTowtMat FDen/nyjLaPzsLIgYGbyoLPmNBvKXGdRvg6Pv6MJKx+rwUH2SAEBYNGtirch3UeN4HwN V2s2yOAIFlMmE16v3UKQDkUR4piOjTnBNncEmnemf5HZOCvUb2l5aeevhQju6iXBXtLk dntA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KMuY5RNL; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info() Date: Wed, 19 May 2021 20:06:58 +0530 Message-Id: <20210519143700.27392-16-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org QCE crypto driver is right now too silent even if the probe() is ok and a valid crypto IP version is found. Convert the dev_dbg() message to a dev_info() instead. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.31.1 Reviewed-by: Thara Gopinath diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index aecb2cdd79e5..8b3e2b4580c2 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -179,7 +179,7 @@ static int qce_check_version(struct qce_device *qce) */ qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1; - dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", + dev_info(qce->dev, "Crypto device found, version %d.%d.%d\n", major, minor, step); return 0; From patchwork Wed May 19 14:36:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442456 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1387451jac; Wed, 19 May 2021 07:40:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTU759uLOXX06UrSCwdYD6qu4/e2WiRRba7OsrGZWTXIy80M4KtKOOU1VHAMVRkEm57bV+ X-Received: by 2002:a92:dd89:: with SMTP id g9mr11594269iln.209.1621435208161; Wed, 19 May 2021 07:40:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435208; cv=none; d=google.com; s=arc-20160816; b=zMUF0pCZdQ4MLsrv/Jv8OT3rb8/amRfJ7CJXf2pak81JOsLDP0gy4sbXJomAq8wNYZ EC2hmIV7DP4AL3pk5NXcxqVxDIH7mbeoSug89zEv/gB5lJtx6k0TlKfBlh1gT39u5wtg cHDPMtf2h7BO+CyVurwZJFWmzoTWoXTaPorTeFjgEZFqtFzf1DQ8dLl+SdLn+jDAryAK FHztFusxHdR1Hq9+NhMxgmB+rr9Fqzi+PyQqlXA1XiR5s5e9SezHZplNz/j6eF/GL07t Dcj2dXBRlbzMg8a7vlwEIT4D/jyC55+lDEFdyncbVYg5fOMLC7C+5PIRVV+GtvxMp590 UYZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tMCI6bMNXfsVdvjl30Isl8zmWzmOUOT+UPEict+OVps=; b=ZtUEq5CvGATWgojZ257P1asg/q9D/rmHXJV/PDZYFD+2zm/UJMPbClbeoVdxdw35zv Vl8o+CdMptN93KFweTrHhy5nN3mmbaz28NYVfLj8FtDoaOKaMs9B4T/icw9qI/f8k6gQ NTvTtBoPRHsLF/F2cz2bOREOUsBbM+x5hPCTY98lbvfVpsZVTxB3oKvy3r0B/jmzy+hq o12HQALzx6QxfXYAft36NpTKqI8lQhudDC22W1dSclz9kss4O/q4tzt6UuMB4V0w/n5d dYc+WgL5wYICVAqVBaN4CrZcYrLJmtRi5cdOGLIbGbIMVapgiLc7/KOuU0YRUS0JdjXB aYFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rdgnDhvw; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized Date: Wed, 19 May 2021 20:06:59 +0530 Message-Id: <20210519143700.27392-17-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Since the Qualcomm qce crypto driver needs the BAM dma driver to be setup first (to allow crypto operations), it makes sense to defer the qce crypto driver probing in case the BAM dma driver is not yet probed. Move the code leg requesting dma channels earlier in the probe() flow. This fixes the qce probe failure issues when both qce and BMA dma are compiled as static part of the kernel. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.31.1 diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 8b3e2b4580c2..207221d5b996 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -218,6 +218,14 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret < 0) goto err_out; + /* qce driver requires BAM dma driver to be setup first. + * In case the dma channel are not set yet, this check + * helps use to return -EPROBE_DEFER earlier. + */ + ret = qce_dma_request(qce->dev, &qce->dma); + if (ret) + return ret; + qce->mem_path = devm_of_icc_get(qce->dev, "memory"); if (IS_ERR(qce->mem_path)) return dev_err_probe(dev, PTR_ERR(qce->mem_path), @@ -269,10 +277,6 @@ static int qce_crypto_probe(struct platform_device *pdev) goto err_clks_iface; } - ret = qce_dma_request(qce->dev, &qce->dma); - if (ret) - goto err_clks; - ret = qce_check_version(qce); if (ret) goto err_clks; @@ -287,12 +291,10 @@ static int qce_crypto_probe(struct platform_device *pdev) ret = qce_register_algs(qce); if (ret) - goto err_dma; + goto err_clks; return 0; -err_dma: - qce_dma_release(&qce->dma); err_clks: clk_disable_unprepare(qce->bus); err_clks_iface: From patchwork Wed May 19 14:37:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 442457 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1387794jac; Wed, 19 May 2021 07:40:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfzJLzzNtcUfjErtBMm5Uia/ALQuyuj5ueYDyoYrdw6paALtxv+vcgiDTkP6pi7txnC3Tl X-Received: by 2002:a02:5b85:: with SMTP id g127mr13544132jab.80.1621435234350; Wed, 19 May 2021 07:40:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621435234; cv=none; d=google.com; s=arc-20160816; b=wWudnM15Ug1nmJv4KYE3+bN26cfrSF1pGe+3PoKQ8d+Z0dA90MUO1uH59hI/xT+jHc /NGsDdUhAS7Dnb0OngbyClZRivnXC/fSQXILC8JRkEvEZxhCqXMCxZi/9UOsgsOtJVC/ rR3JZV2yhKTb/pM/rhhsTFVWfzV8YYNr/gkuuJiWMzwLfFZPMDFwcTH3QusMdWodtVdf WD9GV5HV1ounyAcStyjx2FiHfzfqfYhnDH598WtzjvHBnuooOanaaawzZqGZmNHy2d1A i3ItO3HiHsCu4iZ1lMyMS8zn/oRr1m1uBzQWm8nh45kQKaP6ukztcNNFGqJfP/HDusDk Twkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ha/LaDJaWqJqGFUOZ/CIIY7Ny0kkYMvLA61pIJyDFZ0=; b=dFn4iMl0fNyMLxoMi0CVtZPygknVJMp2qmM+zbMaCbwGYSjDs/6fX72qJgQRRelRYw tkvxcDLbwL1V9QZs2XPU9Vw6khBO97Bvgl/tYGGl67lhKWQwG8aXmbzA54ZCRR/YGw5J GgkHQy8r4BPtp+hf/NCbcENY7XptHvSYMu5IDB/rvB3qWnZs3yiNunZHHi2iqL9m+PGr DT/Nkg/WsOLzRxLJiZVWuFvc5r1vLWpD1iVUd0ZcBVxr1C/62s/b4rXOgZUu2p8qXQIJ Vez01QxHlbKxszGxo63BTI/u+U+OLuSrZGJpr9sKHM4SkzEwJmyN3xxuVneET9V71zq1 LETA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WLOYc+Zw; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v3 17/17] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine. Date: Wed, 19 May 2021 20:07:00 +0530 Message-Id: <20210519143700.27392-18-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210519143700.27392-1-bhupesh.sharma@linaro.org> References: <20210519143700.27392-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add crypto engine (CE) and CE BAM related nodes and definitions to "sm8250.dtsi". Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma Signed-off-by: Thara Gopinath --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.31.1 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..6700d609a7b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3796,6 +3796,34 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + + cryptobam: dma@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely = <1>; + iommus = <&apps_smmu 0x584 0x0011>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8250-qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x584 0x0011>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; }; timer {