From patchwork Thu Jul 5 11:37:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 141116 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1829907ljj; Thu, 5 Jul 2018 04:37:24 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeyayrtYk5QV49UVuxeNx61en3mfqDtCHH3x6lFDwOSPj6fKk98m/qdoqnxFN5p+O0FRuNU X-Received: by 2002:a62:6698:: with SMTP id s24-v6mr6046496pfj.243.1530790644175; Thu, 05 Jul 2018 04:37:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530790644; cv=none; d=google.com; s=arc-20160816; b=PDSeKDwAOG790r0hMDwGLpO6eiIyPn1vuAmBZ1ZvDV9eUB8HeeD4cgTK6IQZI4iJpI VCPYEvySmU9mgW2H3YSwc3LNDAHoJ4S9v/zpwNDE/Nt1oCVMQIO5juSAo+Jrscku/khV k8pbXo22IYna1B6PDH4LLOJG5OFVm1VLzLrSrKygTW1bR+jfCHPzfT2TfMIEq8A63hdB MnGeaM04i+6X/oeGkgT0EOFyHkAjL35twF1m3e9YWnUWGDfhLFjFeR6J2PeqZazoBBK5 9uvUxdJB8W4RnasQSUNo+7K589cdc0n8EyVvQTJIF/u2sDYKxcdvWFRXdOBdqfVyT2C+ KUSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=KVj9xJIzhO/IcU6IPlAHCE07XwFIGt6T4jiDc/RRxVY=; b=vycVYf0oDfu3w/6ck2gAGad9w9nERhm8hKbRGfjPhShvL+XU+HVuTls6UNHyh92Iwb rwwhTM06nCjzn8KQNnf3NvDIHP6PigfKcsAPZ/Sc+EfXgxVnQN3kOljFKvMkvk00ZB7e kZuKUZoeqO4c4AZb2gtRNtMPVFxcRlBKS1Pv/q82vrVlLG9Vk6vKpaBmc11NGl1CcJsa gHTUXgVcm1FoKzahgTpI+TGq2IwTNV59A7226yV4P3eoD7f6lakpd+Sm17VZN9fy8VNv vGnRvBeS2zYA2H4H/kH2sXqstYIPTJZDixkwtlRlz0QcVkiGBZ+1mczd3CGZRFFxuDiO bJ/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=w9oBE1kR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a4-v6si5594704pgl.9.2018.07.05.04.37.23; Thu, 05 Jul 2018 04:37:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=w9oBE1kR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753718AbeGELhX (ORCPT + 5 others); Thu, 5 Jul 2018 07:37:23 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36228 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753680AbeGELhW (ORCPT ); Thu, 5 Jul 2018 07:37:22 -0400 Received: by mail-wm0-f68.google.com with SMTP id s14-v6so10320293wmc.1 for ; Thu, 05 Jul 2018 04:37:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=qku/T/pR5C6YXO7lG6OESExkwmaRoJeCJ/Pf+ChRuAQ=; b=w9oBE1kRV6TMmeR2bR/w02wye+irGNyKfQM5C9wfbiHMaailgUBKV/97qOg9WSkRml P+F6WC3VZ3w4LfJ0DgqgNpHs65zGvi3eMsfqwjg4Uyx5NMpcCUPCBAQEJvp1du2kuHD2 7VvbmpboXKgc7mTX5P4wo+QaKDUjN1vBKPEDYqt2iB7Y/pLNDSPSfL1gPBkQfyyegzEU DqmV3Z26hytyaDyZGH5xDEJDFTDXjA9fCpiQDa0FnQsaDnRuljpxSWrUep9eDfXVAbXY xGfac7fv9lISQnfYWeaXLlpJheKdUNxhj23P/GJVw91M+AfoVdQI+OCPpqIChawuOUSA uKxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=qku/T/pR5C6YXO7lG6OESExkwmaRoJeCJ/Pf+ChRuAQ=; b=sYAJZG0jWxs0NlwYXk3uJxjDiI6eo5Lrv2CaBY0r789STfd3Qo5km+ouU5XslNbPc6 haHUrbrHc+VyW24LUl3EKpLRkK1BZykVp2yTfNrjRNm6q8YI6wr5GbffF5TYAICICEpw APokKXlj1w2uu31G6qk9a8/HT996zmMX94h/5fiK+jnr1lCvqJVDCTKrPkKN7429YSyx aKv14IiW1ZPeegfLhlJs39Wk+dWfda2scs/bCV7QpQtZjBR9srCz3Svb6beuVNHVDB7f vAUTQAEq0//aW+mYQc/bSrxcBH7UqLQwBC3EWTRmI/svMcwdKL9L3MpCHqPC81mBHe1x 64tQ== X-Gm-Message-State: APt69E2RDa/NIoo7JRBrAQqbf1ja/tk83dqTmWe10xjRlgTWqBr7vscB i2q/HFwlCljZVj9xbTIAgO3XXg== X-Received: by 2002:a1c:8312:: with SMTP id f18-v6mr4036892wmd.127.1530790640978; Thu, 05 Jul 2018 04:37:20 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id q8-v6sm11408030wmb.3.2018.07.05.04.37.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 05 Jul 2018 04:37:20 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman , Carlo Caione Cc: Jerome Brunet , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM64: dts: meson-axg: add the audio clock controller Date: Thu, 5 Jul 2018 13:37:13 +0200 Message-Id: <20180705113713.15267-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the audio clock controller which is part of the audio bus This controller takes 8 input plls, and the usual clock gate, from the main clock controller. It provides for the all the devices of the audio subsystem, such as tdms, spdif, pdm, etc. Signed-off-by: Jerome Brunet --- Kevin, Please note that this change depends on the axg audio clock bindings [0]. It will be part of our PR to clock in this cycle. As usual, I've prepared a topic branch with the DT changes for you. Please, let me know when you need a tag on it. Cheers Jerome [0]: https://lkml.kernel.org/r/20180522163457.13834-6-jbrunet@baylibre.com arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 36 ++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.14.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index aa1a42407466..56d334be9f85 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -155,6 +156,41 @@ }; }; + audio: bus@ff642000 { + compatible = "simple-bus"; + reg = <0x0 0xff642000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + }; + cbus: bus@ffd00000 { compatible = "simple-bus"; reg = <0x0 0xffd00000 0x0 0x25000>;