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[209.51.188.17]) by mx.google.com with ESMTPS id d9si23159670ioh.18.2021.05.18.13.13.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 May 2021 13:13:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bKZiMZqH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lj65W-0000ph-Sn for patch@linaro.org; Tue, 18 May 2021 16:13:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lj64H-0008Mo-5p for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:53 -0400 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]:45709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lj64E-00060d-8w for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:52 -0400 Received: by mail-oi1-x235.google.com with SMTP id w127so7139950oig.12 for ; Tue, 18 May 2021 13:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BKH8RkMUVg0BQHkEeqxp4YAUN+HZAVJ9V/XbNB3bw2s=; b=bKZiMZqHOp5rBo5K2mqCuLd4Yh/JrX/x30gTWb/0Rw++wtg7q5MaE+Qv6zOMSC38TQ vdqqdAg7/R7PC1MX5FNbmsoXSfAxl4hSeGviaPPR3ZjyLIes6+3kZqMxglY98/v1gR19 /Q9ANJaSriIj4lWD+K2rdJNAXmt570ZVdkwOh77ZeHUnDFIto4HeSxHlOFSkPHoAN2n4 WYVgo3S3R8tRodRQL8H0CT0relzorDcuYT+TfLiWSFStKgwewsy3NR6UctSG/BnRisaT ++PLhTawb7Q9YGA+kOfwVkaB34gLLPvrYvoFMbUhwU97qwMK8RIwXJUyq+fZj2YQ21pw Wvhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BKH8RkMUVg0BQHkEeqxp4YAUN+HZAVJ9V/XbNB3bw2s=; b=RIRbIIc+4u0pPjiHk9dQFIyZKySTYfM8Z2/U3MxEWu2DDTjHZWQqpg98nXyMKOmi4n GvjWHcAdTcrAd3PYYLOiNA0siAlGRLW5uqvefveUUapddfPwHIoIBxm6niwde15/Wy72 rChdKFCpn80k/E9uDUdilmQOfqEDMAg9HIkHWfuppahfd/ojmKEADSNzT5Y99oCfRKJb d0EwKuBKiUJXamFoXBILjanlyIFGTw8+6b0qdVRV2swi/JbCRPJCtWOBiApepGRrPUyC M73g4JpKG93IMc4anNnq1UAWkZ1YOhhGaqyIbitbATG6YD7enseIC63HBo1LwtDCrLMG RhWw== X-Gm-Message-State: AOAM532dahPQ/26J8HNfjRAN9R3yix0Imv4PGT193ucTsRAPDzR+nCRL gsxHO+EKyNFCzfrPhqtxLosixLPEJm9yJTPu X-Received: by 2002:aca:dd89:: with SMTP id u131mr4774845oig.145.1621368709178; Tue, 18 May 2021 13:11:49 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id u27sm3953204oof.38.2021.05.18.13.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 13:11:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/24] target/ppc: Introduce prot_for_access_type Date: Tue, 18 May 2021 15:11:23 -0500 Message-Id: <20210518201146.794854-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518201146.794854-1-richard.henderson@linaro.org> References: <20210518201146.794854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use this in the three places we currently have a local array indexed by rwx (which happens to have the same values). The types will match up correctly with additional changes. Signed-off-by: Richard Henderson --- target/ppc/internal.h | 19 +++++++++++++++++++ target/ppc/mmu-hash32.c | 8 +++++--- target/ppc/mmu-hash64.c | 10 ++++++---- target/ppc/mmu-radix64.c | 6 ++++-- 4 files changed, 34 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 184ba6d6b3..2b4b06eb76 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -228,4 +228,23 @@ void destroy_ppc_opcodes(PowerPCCPU *cpu); void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc); gchar *ppc_gdb_arch_name(CPUState *cs); +/** + * prot_for_access_type: + * @access_type: Access type + * + * Return the protection bit required for the given access type. + */ +static inline int prot_for_access_type(MMUAccessType access_type) +{ + switch (access_type) { + case MMU_INST_FETCH: + return PAGE_EXEC; + case MMU_DATA_LOAD: + return PAGE_READ; + case MMU_DATA_STORE: + return PAGE_WRITE; + } + g_assert_not_reached(); +} + #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 178cf090b7..233a66658e 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" +#include "internal.h" #include "mmu-hash32.h" #include "exec/log.h" @@ -421,10 +422,11 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, hwaddr pte_offset; ppc_hash_pte32_t pte; int prot; - const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; + int need_prot; hwaddr raddr; assert((rwx == 0) || (rwx == 1) || (rwx == 2)); + need_prot = prot_for_access_type(rwx); /* 1. Handle real mode accesses */ if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { @@ -440,7 +442,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, if (env->nb_BATs != 0) { raddr = ppc_hash32_bat_lookup(cpu, eaddr, rwx, &prot); if (raddr != -1) { - if (need_prot[rwx] & ~prot) { + if (need_prot & ~prot) { if (rwx == 2) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; @@ -513,7 +515,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, prot = ppc_hash32_pte_prot(cpu, sr, pte); - if (need_prot[rwx] & ~prot) { + if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (rwx == 2) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c4a4bc7cd2..d5b70ddc9c 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -29,6 +29,7 @@ #include "mmu-hash64.h" #include "exec/log.h" #include "hw/hw.h" +#include "internal.h" #include "mmu-book3s-v3.h" #include "helper_regs.h" @@ -876,7 +877,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, hwaddr ptex; ppc_hash_pte64_t pte; int exec_prot, pp_prot, amr_prot, prot; - const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; + int need_prot; hwaddr raddr; assert((rwx == 0) || (rwx == 1) || (rwx == 2)); @@ -996,7 +997,8 @@ skip_slb_search: amr_prot = ppc_hash64_amr_prot(cpu, pte); prot = exec_prot & pp_prot & amr_prot; - if ((need_prot[rwx] & ~prot) != 0) { + need_prot = prot_for_access_type(rwx); + if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (rwx == 2) { @@ -1012,13 +1014,13 @@ skip_slb_search: ppc_hash64_set_isi(cs, srr1); } else { int dsisr = 0; - if (need_prot[rwx] & ~pp_prot) { + if (need_prot & ~pp_prot) { dsisr |= DSISR_PROTFAULT; } if (rwx == 1) { dsisr |= DSISR_ISSTORE; } - if (need_prot[rwx] & ~amr_prot) { + if (need_prot & ~amr_prot) { dsisr |= DSISR_AMR; } ppc_hash64_set_dsi(cs, eaddr, dsisr); diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 30fcfcf11f..646b9afb7b 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -25,6 +25,7 @@ #include "sysemu/kvm.h" #include "kvm_ppc.h" #include "exec/log.h" +#include "internal.h" #include "mmu-radix64.h" #include "mmu-book3s-v3.h" @@ -135,7 +136,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte, bool partition_scoped) { CPUPPCState *env = &cpu->env; - const int need_prot[] = { PAGE_READ, PAGE_WRITE, PAGE_EXEC }; + int need_prot; /* Check Page Attributes (pte58:59) */ if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) { @@ -158,7 +159,8 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte, } /* Check if requested access type is allowed */ - if (need_prot[rwx] & ~(*prot)) { /* Page Protected for that Access */ + need_prot = prot_for_access_type(rwx); + if (need_prot & ~*prot) { /* Page Protected for that Access */ *fault_cause |= DSISR_PROTFAULT; return true; } From patchwork Tue May 18 20:11:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441223 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp576756jac; Tue, 18 May 2021 13:13:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgUvu6TJZc4h8v/zj6xNRRyvE9e4npyLt8py+8jzV2Ze+1P8c9XQZ77ExmnO3ORZHuJ7Kq X-Received: by 2002:a05:6e02:1a04:: with SMTP id s4mr2614387ild.125.1621368790030; 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Signed-off-by: Richard Henderson --- target/ppc/mmu-radix64.c | 119 ++++++++++++++++++++++++--------------- 1 file changed, 74 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 646b9afb7b..7972153f23 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -75,71 +75,94 @@ static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env, return true; } -static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr) +static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_type, + vaddr eaddr) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - if (rwx == 2) { /* Instruction Segment Interrupt */ + switch (access_type) { + case MMU_INST_FETCH: + /* Instruction Segment Interrupt */ cs->exception_index = POWERPC_EXCP_ISEG; - } else { /* Data Segment Interrupt */ + break; + case MMU_DATA_STORE: + case MMU_DATA_LOAD: + /* Data Segment Interrupt */ cs->exception_index = POWERPC_EXCP_DSEG; env->spr[SPR_DAR] = eaddr; + break; + default: + g_assert_not_reached(); } env->error_code = 0; } -static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr, - uint32_t cause) +static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type, + vaddr eaddr, uint32_t cause) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - if (rwx == 2) { /* Instruction Storage Interrupt */ + switch (access_type) { + case MMU_INST_FETCH: + /* Instruction Storage Interrupt */ cs->exception_index = POWERPC_EXCP_ISI; env->error_code = cause; - } else { /* Data Storage Interrupt */ + break; + case MMU_DATA_STORE: + cause |= DSISR_ISSTORE; + /* fall through */ + case MMU_DATA_LOAD: + /* Data Storage Interrupt */ cs->exception_index = POWERPC_EXCP_DSI; - if (rwx == 1) { /* Write -> Store */ - cause |= DSISR_ISSTORE; - } env->spr[SPR_DSISR] = cause; env->spr[SPR_DAR] = eaddr; env->error_code = 0; + break; + default: + g_assert_not_reached(); } } -static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr, - hwaddr g_raddr, uint32_t cause) +static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type, + vaddr eaddr, hwaddr g_raddr, uint32_t cause) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - if (rwx == 2) { /* H Instruction Storage Interrupt */ + switch (access_type) { + case MMU_INST_FETCH: + /* H Instruction Storage Interrupt */ cs->exception_index = POWERPC_EXCP_HISI; env->spr[SPR_ASDR] = g_raddr; env->error_code = cause; - } else { /* H Data Storage Interrupt */ + break; + case MMU_DATA_STORE: + cause |= DSISR_ISSTORE; + /* fall through */ + case MMU_DATA_LOAD: + /* H Data Storage Interrupt */ cs->exception_index = POWERPC_EXCP_HDSI; - if (rwx == 1) { /* Write -> Store */ - cause |= DSISR_ISSTORE; - } env->spr[SPR_HDSISR] = cause; env->spr[SPR_HDAR] = eaddr; env->spr[SPR_ASDR] = g_raddr; env->error_code = 0; + break; + default: + g_assert_not_reached(); } } -static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte, - int *fault_cause, int *prot, +static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type, + uint64_t pte, int *fault_cause, int *prot, bool partition_scoped) { CPUPPCState *env = &cpu->env; int need_prot; /* Check Page Attributes (pte58:59) */ - if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) { + if ((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO && access_type == MMU_INST_FETCH) { /* * Radix PTE entries with the non-idempotent I/O attribute are treated * as guarded storage @@ -159,7 +182,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte, } /* Check if requested access type is allowed */ - need_prot = prot_for_access_type(rwx); + need_prot = prot_for_access_type(access_type); if (need_prot & ~*prot) { /* Page Protected for that Access */ *fault_cause |= DSISR_PROTFAULT; return true; @@ -168,15 +191,15 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte, return false; } -static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte, - hwaddr pte_addr, int *prot) +static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type, + uint64_t pte, hwaddr pte_addr, int *prot) { CPUState *cs = CPU(cpu); uint64_t npte; npte = pte | R_PTE_R; /* Always set reference bit */ - if (rwx == 1) { /* Store/Write */ + if (access_type == MMU_DATA_STORE) { /* Store/Write */ npte |= R_PTE_C; /* Set change bit */ } else { /* @@ -271,7 +294,8 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate) return true; } -static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx, +static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, + MMUAccessType access_type, vaddr eaddr, hwaddr g_raddr, ppc_v3_pate_t pate, hwaddr *h_raddr, int *h_prot, @@ -287,24 +311,25 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx, if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB, pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size, &pte, &fault_cause, &pte_addr) || - ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true)) { + ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, h_prot, true)) { if (pde_addr) { /* address being translated was that of a guest pde */ fault_cause |= DSISR_PRTABLE_FAULT; } if (guest_visible) { - ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause); + ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, fault_cause); } return 1; } if (guest_visible) { - ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot); + ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot); } return 0; } -static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, +static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, + MMUAccessType access_type, vaddr eaddr, uint64_t pid, ppc_v3_pate_t pate, hwaddr *g_raddr, int *g_prot, int *g_page_size, @@ -323,7 +348,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, if (offset >= size) { /* offset exceeds size of the process table */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE); + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); } return 1; } @@ -364,7 +389,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, if (ret) { /* No valid PTE */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause); + ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); } return ret; } @@ -393,7 +418,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, if (ret) { /* No valid pte */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause); + ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); } return ret; } @@ -407,16 +432,16 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, *g_raddr = (rpn & ~mask) | (eaddr & mask); } - if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) { + if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, g_prot, false)) { /* Access denied due to protection */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause); + ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); } return 1; } if (guest_visible) { - ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot); + ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot); } return 0; @@ -439,7 +464,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, * | = On | Process Scoped | Scoped | * +-------------+----------------+---------------+ */ -static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx, +static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, bool relocation, hwaddr *raddr, int *psizep, int *protp, bool guest_visible) @@ -453,7 +479,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx, /* Virtual Mode Access - get the fully qualified address */ if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) { if (guest_visible) { - ppc_radix64_raise_segi(cpu, rwx, eaddr); + ppc_radix64_raise_segi(cpu, access_type, eaddr); } return 1; } @@ -466,13 +492,13 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx, } else { if (!ppc64_v3_get_pate(cpu, lpid, &pate)) { if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE); + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); } return 1; } if (!validate_pate(cpu, lpid, &pate)) { if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG); + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG); } return 1; } @@ -490,7 +516,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx, * - Translates an effective address to a guest real address. */ if (relocation) { - int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid, + int ret = ppc_radix64_process_scoped_xlate(cpu, access_type, eaddr, pid, pate, &g_raddr, &prot, &psize, guest_visible); if (ret) { @@ -513,9 +539,10 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx, if (lpid || !msr_hv) { int ret; - ret = ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_raddr, - pate, raddr, &prot, &psize, - false, guest_visible); + ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr, + g_raddr, pate, raddr, + &prot, &psize, false, + guest_visible); if (ret) { return ret; } @@ -536,12 +563,14 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, CPUPPCState *env = &cpu->env; int page_size, prot; bool relocation; + MMUAccessType access_type; hwaddr raddr; assert(!(msr_hv && cpu->vhyp)); assert((rwx == 0) || (rwx == 1) || (rwx == 2)); + access_type = rwx; - relocation = ((rwx == 2) && (msr_ir == 1)) || ((rwx != 2) && (msr_dr == 1)); + relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr); /* HV or virtual hypervisor Real Mode Access */ if (!relocation && (msr_hv || cpu->vhyp)) { /* In real mode top 4 effective addr bits (mostly) ignored */ @@ -570,7 +599,7 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, } /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ - if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr, + if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr, &page_size, &prot, true)) { return 1; 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[209.51.188.17]) by mx.google.com with ESMTPS id j23si20333435ioo.31.2021.05.18.13.15.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 May 2021 13:15:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="XFz7n/Mm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lj686-0005sd-6Z for patch@linaro.org; Tue, 18 May 2021 16:15:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lj64J-0008VR-Em for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:55 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]:42964) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lj64G-00062v-QZ for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:55 -0400 Received: by mail-ot1-x329.google.com with SMTP id g7-20020a9d12870000b0290328b1342b73so1919801otg.9 for ; Tue, 18 May 2021 13:11:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QcPI5lPBCexP89rT0HV5a1mPydi7khfc1j2g/chIoCU=; b=XFz7n/Mm89ots8MrQGecLNMXer0TBVCvXZgnrYjgsodkQxJTB9djCDuwc2nfyW5Oy/ ndiwV1u/9mGwQeX82yCK5v7uG1imJMXWx8Sr7DPKvsGWyzzdpIrfEBY2aEA7CTRluJxC IU9271/c79/zF5b085yqvDN6c5Bno/croVf7JRIzuWAXuT0KtO6PLbFsLA6nf7HEOe+G a6JN5jxQwvchc+qs7vhwEWQRH8VbsVdUdm+DubbvrIev2+Qj27Z4mCAqBTH+k69+96dM 6yq77WyNyzec7fVzBstaITATkR02ElrS0VED0lh27hiuJVMKvtjXDQhfttyiOx5VC4SG o9iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QcPI5lPBCexP89rT0HV5a1mPydi7khfc1j2g/chIoCU=; b=c/aYwq7Rq+SULofxSzx/du9S19+leQCpHB85Btb/bk5DYLZid+u8ZYj610B3d/nN17 Xk6op5rtRxi0m8aC0pwtbR9/LTj7fXfWPp2Gpy8k1yrJJaH7MUQGs6qjZsaJ7yLJzDHj TvD7jZDfdvWnmz+8oehQsyVMkz8giZrSDiAYtWZ9UR28E7zETicHVFMTnUVOzo0VcAlR QCtflyEz3pAmVSgEJFOpJ3b7B5rGRPGa11FdascD5BHuSFmVM3RLjagkb4dn34JJDzBq zhsoQctzauhAKy5AF/6S9WQCx/8GrRAukWYrwCfMDnuQqmqhtj1byiOI1zqodWl4YHuq N/dw== X-Gm-Message-State: AOAM532AQsw9Yq0F6Zhz1PfDgAdKrAsUhVleVGvQI3Da6JsxHmQb3euM 9wltvPW2ZWqeCwquMdEbX1ScPVr4SvUSmLFD X-Received: by 2002:a05:6830:15c9:: with SMTP id j9mr5429111otr.73.1621368711612; Tue, 18 May 2021 13:11:51 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id u27sm3953204oof.38.2021.05.18.13.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 13:11:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/24] target/ppc: Use MMUAccessType in mmu-hash64.c Date: Tue, 18 May 2021 15:11:25 -0500 Message-Id: <20210518201146.794854-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518201146.794854-1-richard.henderson@linaro.org> References: <20210518201146.794854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, Ricgard Henderson , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must leave the 'int rwx' parameter to ppc_hash64_handle_mmu_fault for now, but will clean that up later. Signed-off-by: Ricgard Henderson --- target/ppc/mmu-hash64.c | 61 ++++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d5b70ddc9c..f48b625f48 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -877,10 +877,12 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, hwaddr ptex; ppc_hash_pte64_t pte; int exec_prot, pp_prot, amr_prot, prot; + MMUAccessType access_type; int need_prot; hwaddr raddr; assert((rwx == 0) || (rwx == 1) || (rwx == 2)); + access_type = rwx; /* * Note on LPCR usage: 970 uses HID4, but our special variant of @@ -891,7 +893,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, */ /* 1. Handle real mode accesses */ - if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { + if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) { /* * Translation is supposedly "off", but in real mode the top 4 * effective address bits are (mostly) ignored @@ -924,14 +926,19 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, /* Emulated old-style RMO mode, bounds check against RMLS */ if (raddr >= limit) { - if (rwx == 2) { + switch (access_type) { + case MMU_INST_FETCH: ppc_hash64_set_isi(cs, SRR1_PROTFAULT); - } else { - int dsisr = DSISR_PROTFAULT; - if (rwx == 1) { - dsisr |= DSISR_ISSTORE; - } - ppc_hash64_set_dsi(cs, eaddr, dsisr); + break; + case MMU_DATA_LOAD: + ppc_hash64_set_dsi(cs, eaddr, DSISR_PROTFAULT); + break; + case MMU_DATA_STORE: + ppc_hash64_set_dsi(cs, eaddr, + DSISR_PROTFAULT | DSISR_ISSTORE); + break; + default: + g_assert_not_reached(); } return 1; } @@ -954,13 +961,19 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, exit(1); } /* Segment still not found, generate the appropriate interrupt */ - if (rwx == 2) { + switch (access_type) { + case MMU_INST_FETCH: cs->exception_index = POWERPC_EXCP_ISEG; env->error_code = 0; - } else { + break; + case MMU_DATA_LOAD: + case MMU_DATA_STORE: cs->exception_index = POWERPC_EXCP_DSEG; env->error_code = 0; env->spr[SPR_DAR] = eaddr; + break; + default: + g_assert_not_reached(); } return 1; } @@ -968,7 +981,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, skip_slb_search: /* 3. Check for segment level no-execute violation */ - if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { + if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) { ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); return 1; } @@ -976,14 +989,18 @@ skip_slb_search: /* 4. Locate the PTE in the hash table */ ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); if (ptex == -1) { - if (rwx == 2) { + switch (access_type) { + case MMU_INST_FETCH: ppc_hash64_set_isi(cs, SRR1_NOPTE); - } else { - int dsisr = DSISR_NOPTE; - if (rwx == 1) { - dsisr |= DSISR_ISSTORE; - } - ppc_hash64_set_dsi(cs, eaddr, dsisr); + break; + case MMU_DATA_LOAD: + ppc_hash64_set_dsi(cs, eaddr, DSISR_NOPTE); + break; + case MMU_DATA_STORE: + ppc_hash64_set_dsi(cs, eaddr, DSISR_NOPTE | DSISR_ISSTORE); + break; + default: + g_assert_not_reached(); } return 1; } @@ -997,11 +1014,11 @@ skip_slb_search: amr_prot = ppc_hash64_amr_prot(cpu, pte); prot = exec_prot & pp_prot & amr_prot; - need_prot = prot_for_access_type(rwx); + need_prot = prot_for_access_type(access_type); if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); - if (rwx == 2) { + if (access_type == MMU_INST_FETCH) { int srr1 = 0; if (PAGE_EXEC & ~exec_prot) { srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */ @@ -1017,7 +1034,7 @@ skip_slb_search: if (need_prot & ~pp_prot) { dsisr |= DSISR_PROTFAULT; } - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { dsisr |= DSISR_ISSTORE; } if (need_prot & ~amr_prot) { @@ -1036,7 +1053,7 @@ skip_slb_search: ppc_hash64_set_r(cpu, ptex, pte.pte1); } if (!(pte.pte1 & HPTE64_R_C)) { - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { ppc_hash64_set_c(cpu, ptex, pte.pte1); } else { /* From patchwork Tue May 18 20:11:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441229 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp579007jac; Tue, 18 May 2021 13:16:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuOKH6LRkHFiewfAM5t6m8dqFMfIrS1OQmKNgOUjcQ+iOUnwf36S/cyChKBRDDXfFctlxh X-Received: by 2002:a05:6638:388e:: with SMTP id b14mr8005326jav.73.1621368976482; Tue, 18 May 2021 13:16:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621368976; cv=none; d=google.com; s=arc-20160816; b=AdiQqiK19k36oD4SfBMw32iJ6oR51hKKmJ1fGfDi48y4nGCSEov+Oym14TCT5OFRZ9 jF1OAmpXFk9/IIV96CCtQWx5NBdKXB5u0hN+jHPsORQ+IuJIh06dTTd/x35PKcApkyAY Oj+Xu3Z63DnTxO7CfeafqnyYct0AhwdeYblXUCwDZoFpz3I9foGfF+fzCG3B2JRO3dnN fykhE5YUywBfISlLD90xnjtnYiY4d1cgw+iQAVFtVMcNTnjLIkAjjpTKLL3KW4Dqo44e 2DmlCWK5di3FOWATf/QbC/CLUJQDf/XnUUimZLDV4JZvdPfo9gvHh3nwASk0o/M4IRpU lKuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lKawVPBQQdm6e2iMTq2MuR+NVmqvtSsCh3JY1jQme8I=; b=VMzgBH5eK5e6dlcKUrVnR5cGtUlAzUcy4h5moOZ73SK4myYa5/F0RDrTf5Z8VHoVcA Vj9RGZztIU0gJtakxRr5N4qWFgBxD+gRLZB/NPBxfkjlRexjIDB7+AFFxCDZjd7a6ncF yRmRtW7Yh7Hdr7wXI3vPAcR9wFuEZCUPgz6X8wUNsZjgB/hxS/ZxVWGvk1cG4YA0r/AZ 7TIWF8xUw+DMnR9NHXRyNqcuD/j6UBChFbccC6wtekHbL6pa6aYZNNg0K+TWeOIFGu93 M3FmDHffadT/GWZLJk7U5wQt7+JKsAHKpOuNMib+BR17NLPeVF0XdhP09HqCrOvBZllH PbHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DolfjpCy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t1si22349202jap.32.2021.05.18.13.16.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 May 2021 13:16:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DolfjpCy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lj68V-0007PX-Qx for patch@linaro.org; Tue, 18 May 2021 16:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lj64K-00005z-1F for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:56 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]:33571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lj64H-00064t-Ml for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:55 -0400 Received: by mail-oi1-x22a.google.com with SMTP id b25so11034174oic.0 for ; Tue, 18 May 2021 13:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lKawVPBQQdm6e2iMTq2MuR+NVmqvtSsCh3JY1jQme8I=; b=DolfjpCyZd6/gQ1zv1T0p0EL1uXa419Kfjo/IwR1AwotcIbqdgKR0woRgoLyWHOFPb /jUS8Sq9D6RehdW6Rin+QP9r571EW5AL+upsgq12yJ48qYggeYbEkYrn2c6Tt6JHyzqt qv+ptuC4TDYxSsmsz2hrjXwatsTwxd3+TPJZzCh82P533oOnwnE2IysxQrcBTHWffPzK W2DQ8x4uPCbICKRqe3pc4dYAbdL5i/QuS1FUDyHeBOULF96kji8MCVY97w/JcNqmpOby fM/qPAbvXTn0NlY4IgAejDG7frrkExaGRBZMbs/+MflMq0pjr21oGHJ4Bi014qpmeHXj 52yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lKawVPBQQdm6e2iMTq2MuR+NVmqvtSsCh3JY1jQme8I=; b=YujJvJaAGeNmaNnB+B1byBCUEGZoUVdYb8GOOxw4/+K5qdz7A95mn6ko1b15vS4D6p 6VaZUKKvlTb0MduGtgc5OHbuIGAjHTK2kGrhtHJOMPf0RXbfhXEFTrlTubOqIrOuR9oL oimlkmfp/ct8Y4TcQGcfzRRDfeWGyxY0+GCOrqBUkbkWscxCQDBAP8unioTW2pPhLFck NxTdqtpvMawKdCO5xojjpU8jNPBm+Zs5nmpz5DNTSHmYEZ4Mofwuk2DiPJTysVLL4ery hYThjauSLjXgZiSz1yV1rg2WBdYgKa6RIvKnNXO8hzdwv9r8sL+t99KddeXHpSbliAef F/2g== X-Gm-Message-State: AOAM533n8FN07kNJHdpAdtSW3CtdJUoQVBlY0/Z0bMwVLaDnwGCEQoGM +mqy5XgiVUd19O/mCRox3YC6ZN4mpfZR8zQv X-Received: by 2002:aca:c714:: with SMTP id x20mr5164048oif.85.1621368712606; Tue, 18 May 2021 13:11:52 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id u27sm3953204oof.38.2021.05.18.13.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 13:11:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/24] target/ppc: Use MMUAccessType in mmu-hash32.c Date: Tue, 18 May 2021 15:11:26 -0500 Message-Id: <20210518201146.794854-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518201146.794854-1-richard.henderson@linaro.org> References: <20210518201146.794854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must leave the 'int rwx' parameter to ppc_hash32_handle_mmu_fault for now, but will clean that up later. Signed-off-by: Richard Henderson --- target/ppc/mmu-hash32.c | 53 ++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 233a66658e..744a763f44 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -153,16 +153,17 @@ static int hash32_bat_601_prot(PowerPCCPU *cpu, return ppc_hash32_pp_prot(key, pp, 0); } -static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx, - int *prot) +static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, + MMUAccessType access_type, int *prot) { CPUPPCState *env = &cpu->env; target_ulong *BATlt, *BATut; + bool ifetch = access_type == MMU_INST_FETCH; int i; LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, - rwx == 2 ? 'I' : 'D', ea); - if (rwx == 2) { + ifetch ? 'I' : 'D', ea); + if (ifetch) { BATlt = env->IBAT[1]; BATut = env->IBAT[0]; } else { @@ -181,7 +182,7 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx, } LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__, - type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl); + ifetch ? 'I' : 'D', i, ea, batu, batl); if (mask && ((ea & mask) == (batu & BATU32_BEPI))) { hwaddr raddr = (batl & mask) | (ea & ~mask); @@ -209,7 +210,7 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx, LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx "\n", - __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea, + __func__, ifetch ? 'I' : 'D', i, ea, *BATu, *BATl, BEPIu, BEPIl, bl); } } @@ -219,7 +220,8 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx, } static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, - target_ulong eaddr, int rwx, + target_ulong eaddr, + MMUAccessType access_type, hwaddr *raddr, int *prot) { CPUState *cs = CPU(cpu); @@ -240,7 +242,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, return 0; } - if (rwx == 2) { + if (access_type == MMU_INST_FETCH) { /* No code fetch is allowed in direct-store areas */ cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; @@ -261,7 +263,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, /* lwarx, ldarx or srwcx. */ env->error_code = 0; env->spr[SPR_DAR] = eaddr; - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x06000000; } else { env->spr[SPR_DSISR] = 0x04000000; @@ -281,7 +283,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x06100000; } else { env->spr[SPR_DSISR] = 0x04100000; @@ -291,14 +293,15 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, cpu_abort(cs, "ERROR: instruction should not need " "address translation\n"); } - if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) { + if ((access_type == MMU_DATA_STORE || key != 1) && + (access_type == MMU_DATA_LOAD || key != 0)) { *raddr = eaddr; return 0; } else { cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x0a000000; } else { env->spr[SPR_DSISR] = 0x08000000; @@ -423,13 +426,15 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, ppc_hash_pte32_t pte; int prot; int need_prot; + MMUAccessType access_type; hwaddr raddr; assert((rwx == 0) || (rwx == 1) || (rwx == 2)); - need_prot = prot_for_access_type(rwx); + access_type = rwx; + need_prot = prot_for_access_type(access_type); /* 1. Handle real mode accesses */ - if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { + if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) { /* Translation is off */ raddr = eaddr; tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, @@ -440,17 +445,17 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, /* 2. Check Block Address Translation entries (BATs) */ if (env->nb_BATs != 0) { - raddr = ppc_hash32_bat_lookup(cpu, eaddr, rwx, &prot); + raddr = ppc_hash32_bat_lookup(cpu, eaddr, access_type, &prot); if (raddr != -1) { if (need_prot & ~prot) { - if (rwx == 2) { + if (access_type == MMU_INST_FETCH) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x0a000000; } else { env->spr[SPR_DSISR] = 0x08000000; @@ -471,7 +476,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, /* 4. Handle direct store segments */ if (sr & SR32_T) { - if (ppc_hash32_direct_store(cpu, sr, eaddr, rwx, + if (ppc_hash32_direct_store(cpu, sr, eaddr, access_type, &raddr, &prot) == 0) { tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, @@ -483,7 +488,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, } /* 5. Check for segment level no-execute violation */ - if ((rwx == 2) && (sr & SR32_NX)) { + if (access_type == MMU_INST_FETCH && (sr & SR32_NX)) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; @@ -492,14 +497,14 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, /* 6. Locate the PTE in the hash table */ pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); if (pte_offset == -1) { - if (rwx == 2) { + if (access_type == MMU_INST_FETCH) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x42000000; } else { env->spr[SPR_DSISR] = 0x40000000; @@ -518,14 +523,14 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); - if (rwx == 2) { + if (access_type == MMU_INST_FETCH) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x0a000000; } else { env->spr[SPR_DSISR] = 0x08000000; @@ -542,7 +547,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, ppc_hash32_set_r(cpu, pte_offset, pte.pte1); } if (!(pte.pte1 & HPTE32_R_C)) { - if (rwx == 1) { + if (access_type == MMU_DATA_STORE) { ppc_hash32_set_c(cpu, pte_offset, pte.pte1); } else { /* From patchwork Tue May 18 20:11:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441227 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp578765jac; Tue, 18 May 2021 13:15:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwACgW1qTJD7vxTcc3+YlnjoBd0keg1ZeVmROQHqEJD88LAV57AEkYFh23KVGSnxpXGpcXY X-Received: by 2002:a05:6638:1382:: with SMTP id w2mr7967906jad.78.1621368957668; Tue, 18 May 2021 13:15:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621368957; cv=none; d=google.com; s=arc-20160816; b=Tfyerd2Ii3LLpza67QQfal+Qe5/y1Gj4EE2WA3AN8/Zdcv+rcw+Aol0rCZJwCNKF10 nCXMH7zgySe0+GZ3qq4Livy6fDhyf4KzdWieWlwWlusAYCJxNj1AXh0eLmKx/GcATAim z2WpDK7Z/3EMHq8rHBFiBz4Nh2btakI5dVJd2VhypGeVSwVYlQiMSuVAcGtqqa/ronuh LkpOFrZlMmo35yCKL3ST+AkIsgJtWLcKQ/Pu/cY2J2lSYgCQy/t3oWdO32BvX00UdRSj 0Sw9Q+STFzZJCpuj7FKETU0ILjXztVfvTvsFqXjIWbs6y9QoX1fnFEqIeSmrnpcjClQX gwXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YNFsFphXVzLhExC+2yxVmbdVN0mwFY9+hq9TnweqrT0=; b=aw+P0zFv2LioNqvWsLXVqndbMycSWRcdGraIb4Eu4MJ4Xe3bAgj9jvEbXOgOIekS1e pB5nxXAK2bCXhuAMPH31WahOWlVuSGiPm3bpYJNAQ627ydEEVE6Ny2IRs4LvzOPm9oO9 ukGDJFKWbPhableB4ypiPwlTd14cWWy2V9L6/exb+Y5v533mqIn1K2p/j4w+gR30bN9d maMmbELcy3uLjHTH6Ynv9Or7mOro6fkt5ynmmDdpEoSgf8cPluyw48PuY0dc4QcH+8v4 5GOXrEy7878GCpXtcf9mgQB4AlwuZUjyA4BXyixHt+HeC33Hl3/j987963rulPrXJCK3 X00A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DCcAJ6+u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q10si24853850ilu.60.2021.05.18.13.15.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 May 2021 13:15:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DCcAJ6+u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lj68C-00082R-Sf for patch@linaro.org; Tue, 18 May 2021 16:15:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lj64L-0000Cf-CI for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:57 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]:44706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lj64I-00065u-Oh for qemu-devel@nongnu.org; Tue, 18 May 2021 16:11:57 -0400 Received: by mail-ot1-x32c.google.com with SMTP id r26-20020a056830121ab02902a5ff1c9b81so9747547otp.11 for ; Tue, 18 May 2021 13:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YNFsFphXVzLhExC+2yxVmbdVN0mwFY9+hq9TnweqrT0=; b=DCcAJ6+uRb9vxbEjg5+Vpc9PcPKCkgA/iBDGYUbvb4azTeb4cJqM8p9EWU6DRmODt0 FtkzXK5TmX0EigDM9OPAsF5++4AXEnxoY5SbRhuWKbTzf1wbM+GxWH9kjs8Z5YaC8e+E PuGJhX/OQDIhSxX6JSutsTR6IpfEBLxOUjY9L5IlLHa88fcLIC3S9DgtHKpm3LnCsDyT xuTKrL264+adhAWERglG2Nus1wmjNF9T//HdZ81UAZYx9KnqEDdjwMmMctpVrWNqSceZ Tkgdj4PyplXa9M2i1xS42tLm+9UxzpgJdVEaUL16vhm5VcGLfV5OO81S+kyk3iDs4OCC chdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YNFsFphXVzLhExC+2yxVmbdVN0mwFY9+hq9TnweqrT0=; b=l3DSL6p1Rj2Gq2PU9rdAV8JJmoNdr7soBAeiRlN+I8TWYZ09GAJ30e/8YrZRyXsZn2 KPNhr1FeIaol0AKoW5ZIitAv9nc12LRABPPL21BnerqrHCsMv69odvWvdnmkgZkK5IQd 8MfqiyvxBnSUCpiRoiU4rT19IL30dAV2+fx0XLrSgir+0JlRPw1NuxcU8jHPMdrU5G4J v9soRPENRiXFIiPE8ojbZmeRStT10yyr7Lw91H8meBDTQKV7A5gSp5oa8+c6juHL6TPw dgnL44x5x4Y24p6N8vUam6Yyhj5rdgfQW+61oer0QuMtyLfbaaM9+QUjngwQqajcJ80s Ua2g== X-Gm-Message-State: AOAM530HlsJdJeJYMe0a7Rxx/1Tf1GCzJzTlAyo0Dk+W+j63bTqyIcXp 4lBiUN3E0PXpuTTIY/zjkBUSgApFf2Xbvl5J X-Received: by 2002:a9d:69da:: with SMTP id v26mr5787260oto.338.1621368713647; Tue, 18 May 2021 13:11:53 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id u27sm3953204oof.38.2021.05.18.13.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 13:11:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/24] target/ppc: Rename access_type to type in mmu_helper.c Date: Tue, 18 May 2021 15:11:27 -0500 Message-Id: <20210518201146.794854-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518201146.794854-1-richard.henderson@linaro.org> References: <20210518201146.794854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The variable that holds ACCESS_INT, ACCESS_FLOAT, etc is variously called 'int type' or 'int access_type' within this file. Standardize on 'int type' throughout. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 64 ++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 32 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 06e1ebdcbc..dd2f1e2a90 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -126,11 +126,11 @@ static int pp_check(int key, int pp, int nx) return access; } -static int check_prot(int prot, int rw, int access_type) +static int check_prot(int prot, int rw, int type) { int ret; - if (access_type == ACCESS_CODE) { + if (type == ACCESS_CODE) { if (prot & PAGE_EXEC) { ret = 0; } else { @@ -309,7 +309,7 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way, } static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type) + target_ulong eaddr, int rw, int type) { ppc6xx_tlb_t *tlb; int nr, best, way; @@ -319,7 +319,7 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, ret = -1; /* No TLB found */ for (way = 0; way < env->nb_ways; way++) { nr = ppc6xx_tlb_getnum(env, eaddr, way, - access_type == ACCESS_CODE ? 1 : 0); + type == ACCESS_CODE ? 1 : 0); tlb = &env->tlb.tlb6[nr]; /* This test "emulates" the PTE index match for hardware TLBs */ if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { @@ -333,9 +333,9 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb, pte_is_valid(tlb->pte0) ? "valid" : "inval", tlb->EPN, eaddr, tlb->pte1, - rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); + rw ? 'S' : 'L', type == ACCESS_CODE ? 'I' : 'D'); switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, - 0, rw, access_type)) { + 0, rw, type)) { case -3: /* TLB inconsistency */ return -1; @@ -683,7 +683,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong address, int rw, - int access_type) + int type) { ppcemb_tlb_t *tlb; hwaddr raddr; @@ -727,7 +727,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, check_perms: /* Check from TLB entry */ ctx->prot = tlb->prot; - ret = check_prot(ctx->prot, rw, access_type); + ret = check_prot(ctx->prot, rw, type); if (ret == -2) { env->spr[SPR_40x_ESR] = 0; } @@ -760,7 +760,7 @@ void store_40x_sler(CPUPPCState *env, uint32_t val) static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb, hwaddr *raddr, int *prot, target_ulong address, int rw, - int access_type, int i) + int type, int i) { int ret, prot2; @@ -794,7 +794,7 @@ found_tlb: } /* Check the address space */ - if (access_type == ACCESS_CODE) { + if (type == ACCESS_CODE) { if (msr_ir != (tlb->attr & 1)) { LOG_SWTLB("%s: AS doesn't match\n", __func__); return -1; @@ -829,7 +829,7 @@ found_tlb: static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong address, int rw, - int access_type) + int type) { ppcemb_tlb_t *tlb; hwaddr raddr; @@ -840,7 +840,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, for (i = 0; i < env->nb_tlb; i++) { tlb = &env->tlb.tlbe[i]; ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw, - access_type, i); + type, i); if (ret != -1) { break; } @@ -984,7 +984,7 @@ static bool mmubooke206_get_as(CPUPPCState *env, static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddr, int *prot, target_ulong address, int rw, - int access_type, int mmu_idx) + int type, int mmu_idx) { int ret; int prot2 = 0; @@ -1043,7 +1043,7 @@ found_tlb: } /* Check the address space and permissions */ - if (access_type == ACCESS_CODE) { + if (type == ACCESS_CODE) { /* There is no way to fetch code using epid load */ assert(!use_epid); if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { @@ -1080,7 +1080,7 @@ found_tlb: static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong address, int rw, - int access_type, int mmu_idx) + int type, int mmu_idx) { ppcmas_tlb_t *tlb; hwaddr raddr; @@ -1098,7 +1098,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, continue; } ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address, - rw, access_type, mmu_idx); + rw, type, mmu_idx); if (ret != -1) { goto found_tlb; } @@ -1415,12 +1415,12 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, static int get_physical_address_wtlb( CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type, + target_ulong eaddr, int rw, int type, int mmu_idx) { int ret = -1; - bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) - || (access_type != ACCESS_CODE && msr_dr == 0); + bool real_mode = (type == ACCESS_CODE && msr_ir == 0) + || (type != ACCESS_CODE && msr_dr == 0); switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: @@ -1430,11 +1430,11 @@ static int get_physical_address_wtlb( } else { /* Try to find a BAT */ if (env->nb_BATs != 0) { - ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, access_type); + ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, type); } if (ret < 0) { /* We didn't match any BAT entry or don't have BATs */ - ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type); + ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, type); } } break; @@ -1445,16 +1445,16 @@ static int get_physical_address_wtlb( ret = check_physical(env, ctx, eaddr, rw); } else { ret = mmu40x_get_physical_address(env, ctx, eaddr, - rw, access_type); + rw, type); } break; case POWERPC_MMU_BOOKE: ret = mmubooke_get_physical_address(env, ctx, eaddr, - rw, access_type); + rw, type); break; case POWERPC_MMU_BOOKE206: ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw, - access_type, mmu_idx); + type, mmu_idx); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ @@ -1478,9 +1478,9 @@ static int get_physical_address_wtlb( static int get_physical_address( CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type) + target_ulong eaddr, int rw, int type) { - return get_physical_address_wtlb(env, ctx, eaddr, rw, access_type, 0); + return get_physical_address_wtlb(env, ctx, eaddr, rw, type, 0); } hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1584,19 +1584,19 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, CPUState *cs = env_cpu(env); PowerPCCPU *cpu = POWERPC_CPU(cs); mmu_ctx_t ctx; - int access_type; + int type; int ret = 0; if (rw == 2) { /* code access */ rw = 0; - access_type = ACCESS_CODE; + type = ACCESS_CODE; } else { /* data access */ - access_type = env->access_type; + type = env->access_type; } ret = get_physical_address_wtlb(env, &ctx, address, rw, - access_type, mmu_idx); + type, mmu_idx); if (ret == 0) { tlb_set_page(cs, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, @@ -1604,7 +1604,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, ret = 0; } else if (ret < 0) { LOG_MMU_STATE(cs); - if (access_type == ACCESS_CODE) { + if (type == ACCESS_CODE) { switch (ret) { case -1: /* No matches in page tables or TLB */ @@ -1761,7 +1761,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case -4: /* Direct store exception */ - switch (access_type) { + switch (type) { case ACCESS_FLOAT: /* Floating point load/store */ cs->exception_index = POWERPC_EXCP_ALIGN; From patchwork Tue May 18 20:11:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441234 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp582882jac; Tue, 18 May 2021 13:21:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGXzAKY9WoMx0BlAs/f6LcnciJ3Pf4zaP20ECfHT2lm0GXRIuGKW7iqdiPPmaMNpGbO+bI X-Received: by 2002:a92:2a0a:: with SMTP id r10mr6237687ile.274.1621369318660; Tue, 18 May 2021 13:21:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369318; cv=none; d=google.com; s=arc-20160816; b=V+B7d9no9QoPJSYrH40tGxbiS2/mapk/rj18rt/cbd4HkxM5sFLWBDLh3bFen/ssJN dcINec0zIa8Rann7VaCdaTJS08arzzE3OcYO37Owi4BDK4+X/V6Sb6uMDSrDO4d8Q7yO m3giIjdXPthWlHd1GrCYxQfbKm++TftCLS4dwvyJzwT0wnxhV19tAiUsKUwrn31AMD7R 4bXnlrQjnF2ulVti3WwptHsXEFHMC4wtaj7WudZ6AdoJn2fPsvkJz48JywbjIGPj1Y61 gf3MNhIavogtqTKunnRUDBeOkdzawgjSJLc10aObGVfcrm6vCLuG6nTxzNZNuyYvPGAR CBhA== ARC-Message-Signature: i=1; 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Comparisons vs zero become either MMU_DATA_LOAD or MMU_DATA_STORE, since we had previously squashed rw to 0 for code access. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 161 +++++++++++++++++++++------------------- 1 file changed, 85 insertions(+), 76 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index dd2f1e2a90..2aa1b777de 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -126,7 +126,7 @@ static int pp_check(int key, int pp, int nx) return access; } -static int check_prot(int prot, int rw, int type) +static int check_prot(int prot, MMUAccessType access_type, int type) { int ret; @@ -136,7 +136,7 @@ static int check_prot(int prot, int rw, int type) } else { ret = -2; } - } else if (rw) { + } else if (access_type == MMU_DATA_STORE) { if (prot & PAGE_WRITE) { ret = 0; } else { @@ -153,9 +153,9 @@ static int check_prot(int prot, int rw, int type) return ret; } -static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, - target_ulong pte1, int h, - int rw, int type) +static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, + target_ulong pte1, int h, + MMUAccessType access_type, int type) { target_ulong ptem, mmask; int access, ret, pteh, ptev, pp; @@ -182,7 +182,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, /* Keep the matching PTE information */ ctx->raddr = pte1; ctx->prot = access; - ret = check_prot(ctx->prot, rw, type); + ret = check_prot(ctx->prot, access_type, type); if (ret == 0) { /* Access granted */ qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -197,7 +197,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, } static int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, - int ret, int rw) + int ret, MMUAccessType access_type) { int store = 0; @@ -208,7 +208,7 @@ static int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, store = 1; } if (!(*pte1p & 0x00000080)) { - if (rw == 1 && ret == 0) { + if (access_type == MMU_DATA_STORE && ret == 0) { /* Update changed flag */ *pte1p |= 0x00000080; store = 1; @@ -308,8 +308,9 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way, env->last_way = way; } -static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int type) +static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, + MMUAccessType access_type, int type) { ppc6xx_tlb_t *tlb; int nr, best, way; @@ -333,9 +334,10 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb, pte_is_valid(tlb->pte0) ? "valid" : "inval", tlb->EPN, eaddr, tlb->pte1, - rw ? 'S' : 'L', type == ACCESS_CODE ? 'I' : 'D'); + access_type == MMU_DATA_STORE ? 'S' : 'L', + type == ACCESS_CODE ? 'I' : 'D'); switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, - 0, rw, type)) { + 0, access_type, type)) { case -3: /* TLB inconsistency */ return -1; @@ -366,7 +368,7 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n", ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); /* Update page flags */ - pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, rw); + pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, access_type); } return ret; @@ -400,7 +402,8 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp, } static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong virtual, int rw, int type) + target_ulong virtual, MMUAccessType access_type, + int type) { target_ulong *BATlt, *BATut, *BATu, *BATl; target_ulong BEPIl, BEPIu, bl; @@ -438,7 +441,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, (virtual & 0x0001F000); /* Compute access rights */ ctx->prot = prot; - ret = check_prot(ctx->prot, rw, type); + ret = check_prot(ctx->prot, access_type, type); if (ret == 0) { LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', @@ -472,8 +475,9 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, } /* Perform segment based translation */ -static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int type) +static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, MMUAccessType access_type, + int type) { PowerPCCPU *cpu = env_archcpu(env); hwaddr hash; @@ -497,7 +501,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, " nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx " ir=%d dr=%d pr=%d %d t=%d\n", eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, - (int)msr_dr, pr != 0 ? 1 : 0, rw, type); + (int)msr_dr, pr != 0 ? 1 : 0, access_type == MMU_DATA_STORE, type); pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits; hash = vsid ^ pgidx; ctx->ptem = (vsid << 7) | (pgidx >> 10); @@ -520,7 +524,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* Initialize real address with an invalid value */ ctx->raddr = (hwaddr)-1ULL; /* Software TLB search */ - ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); + ret = ppc6xx_tlb_check(env, ctx, eaddr, access_type, type); #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { CPUState *cs = env_cpu(env); @@ -603,7 +607,8 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, "address translation\n"); return -4; } - if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { + if ((access_type == MMU_DATA_STORE || ctx->key != 1) && + (access_type == MMU_DATA_LOAD || ctx->key != 0)) { ctx->raddr = eaddr; ret = 2; } else { @@ -682,7 +687,8 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) } static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong address, int rw, + target_ulong address, + MMUAccessType access_type, int type) { ppcemb_tlb_t *tlb; @@ -700,8 +706,8 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, } zsel = (tlb->attr >> 4) & 0xF; zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3; - LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", - __func__, i, zsel, zpr, rw, tlb->attr); + LOG_SWTLB("%s: TLB %d zsel %d zpr %d ty %d attr %08x\n", + __func__, i, zsel, zpr, access_type, tlb->attr); /* Check execute enable bit */ switch (zpr) { case 0x2: @@ -727,7 +733,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, check_perms: /* Check from TLB entry */ ctx->prot = tlb->prot; - ret = check_prot(ctx->prot, rw, type); + ret = check_prot(ctx->prot, access_type, type); if (ret == -2) { env->spr[SPR_40x_ESR] = 0; } @@ -757,10 +763,9 @@ void store_40x_sler(CPUPPCState *env, uint32_t val) env->spr[SPR_405_SLER] = val; } -static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb, - hwaddr *raddr, int *prot, - target_ulong address, int rw, - int type, int i) +static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb, + hwaddr *raddr, int *prot, target_ulong address, + MMUAccessType access_type, int type, int i) { int ret, prot2; @@ -815,7 +820,7 @@ found_tlb: } *prot = prot2; - if ((!rw && prot2 & PAGE_READ) || (rw && (prot2 & PAGE_WRITE))) { + if (prot2 & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE)) { LOG_SWTLB("%s: found TLB!\n", __func__); return 0; } @@ -828,7 +833,8 @@ found_tlb: } static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong address, int rw, + target_ulong address, + MMUAccessType access_type, int type) { ppcemb_tlb_t *tlb; @@ -839,8 +845,8 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, raddr = (hwaddr)-1ULL; for (i = 0; i < env->nb_tlb; i++) { tlb = &env->tlb.tlbe[i]; - ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw, - type, i); + ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, + access_type, type, i); if (ret != -1) { break; } @@ -938,10 +944,10 @@ static bool is_epid_mmu(int mmu_idx) return mmu_idx == PPC_TLB_EPID_STORE || mmu_idx == PPC_TLB_EPID_LOAD; } -static uint32_t mmubooke206_esr(int mmu_idx, bool rw) +static uint32_t mmubooke206_esr(int mmu_idx, MMUAccessType access_type) { uint32_t esr = 0; - if (rw) { + if (access_type == MMU_DATA_STORE) { esr |= ESR_ST; } if (is_epid_mmu(mmu_idx)) { @@ -983,7 +989,8 @@ static bool mmubooke206_get_as(CPUPPCState *env, /* Check if the tlb found by hashing really matches */ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddr, int *prot, - target_ulong address, int rw, + target_ulong address, + MMUAccessType access_type, int type, int mmu_idx) { int ret; @@ -1066,7 +1073,7 @@ found_tlb: } *prot = prot2; - if ((!rw && prot2 & PAGE_READ) || (rw && (prot2 & PAGE_WRITE))) { + if (prot2 & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE)) { LOG_SWTLB("%s: found TLB!\n", __func__); return 0; } @@ -1079,7 +1086,8 @@ found_tlb: } static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong address, int rw, + target_ulong address, + MMUAccessType access_type, int type, int mmu_idx) { ppcmas_tlb_t *tlb; @@ -1098,7 +1106,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, continue; } ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address, - rw, type, mmu_idx); + access_type, type, mmu_idx); if (ret != -1) { goto found_tlb; } @@ -1361,8 +1369,8 @@ void dump_mmu(CPUPPCState *env) } } -static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw) +static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, + MMUAccessType access_type) { int in_plb, ret; @@ -1393,7 +1401,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; if (in_plb ^ msr_px) { /* Access in protected area */ - if (rw == 1) { + if (access_type == MMU_DATA_STORE) { /* Access is not allowed */ ret = -2; } @@ -1413,10 +1421,10 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, return ret; } -static int get_physical_address_wtlb( - CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int type, - int mmu_idx) +static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, + MMUAccessType access_type, int type, + int mmu_idx) { int ret = -1; bool real_mode = (type == ACCESS_CODE && msr_ir == 0) @@ -1426,15 +1434,15 @@ static int get_physical_address_wtlb( case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: if (real_mode) { - ret = check_physical(env, ctx, eaddr, rw); + ret = check_physical(env, ctx, eaddr, access_type); } else { /* Try to find a BAT */ if (env->nb_BATs != 0) { - ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, type); + ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type, type); } if (ret < 0) { /* We didn't match any BAT entry or don't have BATs */ - ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, type); + ret = get_segment_6xx_tlb(env, ctx, eaddr, access_type, type); } } break; @@ -1442,18 +1450,18 @@ static int get_physical_address_wtlb( case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: if (real_mode) { - ret = check_physical(env, ctx, eaddr, rw); + ret = check_physical(env, ctx, eaddr, access_type); } else { ret = mmu40x_get_physical_address(env, ctx, eaddr, - rw, type); + access_type, type); } break; case POWERPC_MMU_BOOKE: ret = mmubooke_get_physical_address(env, ctx, eaddr, - rw, type); + access_type, type); break; case POWERPC_MMU_BOOKE206: - ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw, + ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type, type, mmu_idx); break; case POWERPC_MMU_MPC8xx: @@ -1462,7 +1470,7 @@ static int get_physical_address_wtlb( break; case POWERPC_MMU_REAL: if (real_mode) { - ret = check_physical(env, ctx, eaddr, rw); + ret = check_physical(env, ctx, eaddr, access_type); } else { cpu_abort(env_cpu(env), "PowerPC in real mode do not do any translation\n"); @@ -1476,11 +1484,11 @@ static int get_physical_address_wtlb( return ret; } -static int get_physical_address( - CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int type) +static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, MMUAccessType access_type, + int type) { - return get_physical_address_wtlb(env, ctx, eaddr, rw, type, 0); + return get_physical_address_wtlb(env, ctx, eaddr, access_type, type, 0); } hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1508,14 +1516,15 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) ; } - if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) { + if (unlikely(get_physical_address(env, &ctx, addr, MMU_DATA_LOAD, + ACCESS_INT) != 0)) { /* * Some MMUs have separate TLBs for code and data. If we only * try an ACCESS_INT, we may not be able to read instructions * mapped by code TLBs, so we also try a ACCESS_CODE. */ - if (unlikely(get_physical_address(env, &ctx, addr, 0, + if (unlikely(get_physical_address(env, &ctx, addr, MMU_INST_FETCH, ACCESS_CODE) != 0)) { return -1; } @@ -1525,13 +1534,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, - int rw, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { uint32_t epid; bool as, pr; uint32_t missed_tid = 0; bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr); - if (rw == 2) { + + if (access_type == MMU_INST_FETCH) { as = msr_ir; } env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK; @@ -1579,7 +1589,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, /* Perform address translation */ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, - int rw, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { CPUState *cs = env_cpu(env); PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -1587,15 +1597,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int type; int ret = 0; - if (rw == 2) { + if (access_type == MMU_INST_FETCH) { /* code access */ - rw = 0; type = ACCESS_CODE; } else { /* data access */ type = env->access_type; } - ret = get_physical_address_wtlb(env, &ctx, address, rw, + ret = get_physical_address_wtlb(env, &ctx, address, access_type, type, mmu_idx); if (ret == 0) { tlb_set_page(cs, address & TARGET_PAGE_MASK, @@ -1632,7 +1641,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, 0); + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD); return -1; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ @@ -1674,7 +1683,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - if (rw == 1) { + if (access_type == MMU_DATA_STORE) { cs->exception_index = POWERPC_EXCP_DSTLB; env->error_code = 1 << 16; } else { @@ -1691,7 +1700,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, get_pteg_offset32(cpu, ctx.hash[1]); break; case POWERPC_MMU_SOFT_74xx: - if (rw == 1) { + if (access_type == MMU_DATA_STORE) { cs->exception_index = POWERPC_EXCP_DSTLB; } else { cs->exception_index = POWERPC_EXCP_DLTLB; @@ -1708,7 +1717,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; - if (rw) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_40x_ESR] = 0x00800000; } else { env->spr[SPR_40x_ESR] = 0x00000000; @@ -1719,13 +1728,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, address, rw, mmu_idx); + booke206_update_mas_tlb_miss(env, address, access_type, mmu_idx); /* fall through */ case POWERPC_MMU_BOOKE: cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, rw); + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type); return -1; case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise " @@ -1743,16 +1752,16 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, if (env->mmu_model == POWERPC_MMU_SOFT_4xx || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { env->spr[SPR_40x_DEAR] = address; - if (rw) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_40x_ESR] |= 0x00800000; } } else if ((env->mmu_model == POWERPC_MMU_BOOKE) || (env->mmu_model == POWERPC_MMU_BOOKE206)) { env->spr[SPR_BOOKE_DEAR] = address; - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, rw); + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type); } else { env->spr[SPR_DAR] = address; - if (rw == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x0A000000; } else { env->spr[SPR_DSISR] = 0x08000000; @@ -1773,7 +1782,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; - if (rw == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x06000000; } else { env->spr[SPR_DSISR] = 0x04000000; @@ -1784,7 +1793,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; - if (rw == 1) { + if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x06100000; } else { env->spr[SPR_DSISR] = 0x04100000; From patchwork Tue May 18 20:11:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441225 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp577427jac; Tue, 18 May 2021 13:14:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgbWQ+2TUsKXQ3PPP9JGwa+fK2Huhl63C9sALbqL1zhC6M5z4tQxpKEvcHm//72bW/d7xL X-Received: by 2002:a92:700a:: with SMTP id l10mr6138813ilc.44.1621368850510; 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Use prot_for_access_type to simplify everything. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 35 +++++++---------------------------- 1 file changed, 7 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2aa1b777de..e3912e4094 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/qemu-print.h" +#include "internal.h" #include "mmu-book3s-v3.h" #include "mmu-radix64.h" @@ -126,33 +127,11 @@ static int pp_check(int key, int pp, int nx) return access; } -static int check_prot(int prot, MMUAccessType access_type, int type) +static int check_prot(int prot, MMUAccessType access_type) { - int ret; - - if (type == ACCESS_CODE) { - if (prot & PAGE_EXEC) { - ret = 0; - } else { - ret = -2; - } - } else if (access_type == MMU_DATA_STORE) { - if (prot & PAGE_WRITE) { - ret = 0; - } else { - ret = -2; - } - } else { - if (prot & PAGE_READ) { - ret = 0; - } else { - ret = -2; - } - } - - return ret; + return prot & prot_for_access_type(access_type) ? 0 : -2; } - + static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1, int h, MMUAccessType access_type, int type) @@ -182,7 +161,7 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, /* Keep the matching PTE information */ ctx->raddr = pte1; ctx->prot = access; - ret = check_prot(ctx->prot, access_type, type); + ret = check_prot(ctx->prot, access_type); if (ret == 0) { /* Access granted */ qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -441,7 +420,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, (virtual & 0x0001F000); /* Compute access rights */ ctx->prot = prot; - ret = check_prot(ctx->prot, access_type, type); + ret = check_prot(ctx->prot, access_type); if (ret == 0) { LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', @@ -733,7 +712,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, check_perms: /* Check from TLB entry */ ctx->prot = tlb->prot; - ret = check_prot(ctx->prot, access_type, type); + ret = check_prot(ctx->prot, access_type); if (ret == -2) { env->spr[SPR_40x_ESR] = 0; } From patchwork Tue May 18 20:11:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441228 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp578988jac; Tue, 18 May 2021 13:16:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyFo6NfWQLFZmHR3nicbmU0wxwGj3FOFYTnfEIzks2EUCkrxlkXwrYen6greRfkXETwMfKH X-Received: by 2002:a92:cda4:: with SMTP id g4mr4173059ild.47.1621368974816; Tue, 18 May 2021 13:16:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621368974; cv=none; d=google.com; s=arc-20160816; b=d/g/AHk837IApO6krRPQroGX2DqkzERLYr7hldG1dK+2BhLRXm+2LMRgp2gx32fJD9 r3UZAzqhh0wLpCvyRQNhufrNt7VeaPhj+u6QF9F03buub+FP8/KODCrLWdzC731ieHTT vaKLPCkYarhM0m2+lIKlVB99zaVwhAcZc9DDv6EYS1GE+yRMcfwIoDVvgVbFkdfGTgiE U5HlU8HeWxxa7mCAdYF+nO4SOvojacA3knl84wGs5L4u7mkzF1jYjRD7oIN/3TNluRia Y7+Z/iBG3c6HVVm1z+oRmTC9XgNsYfb/yeeme66vyaYL6Edqs6KLDkSKCiOmouck3Usf Np7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BX4YtBUOZyW7G2aF5M0ywa7Ji9jq6BV29m78RiFM3Wg=; b=ohDug9rRvwjp4vzEymObreZLNIxgIcDS/Yid0i0F3c2tfShFN28fEYu0MZOhOFygn8 iQWS/i4IvleR44ml0utnY5xQlwFKK9f3EVjhAPSEht2gsZkkGthR4zbg82CCQTerbUJY 8/wmBxECYfma2Nj4eij0PVaIRJB+3BwXrlpOanI3kWr0wIASYsbw2u054TnwdVgMC0z8 /qnpUpZhfpqtiW8t/DZcixJ02xFZvZJqmX5uWKi4TYMVNHN2F4orYdtiNREcoz04P3JA IsMcZ8Av7UO9PVmVBuu59LRThq7RgcWqMdwf/+fpZW1/toYxryUkgm987/6rE6bkOo4x JKcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="i/pYn/vT"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e3912e4094..197a75c9e3 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -134,7 +134,7 @@ static int check_prot(int prot, MMUAccessType access_type) static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1, int h, - MMUAccessType access_type, int type) + MMUAccessType access_type) { target_ulong ptem, mmask; int access, ret, pteh, ptev, pp; @@ -316,7 +316,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, access_type == MMU_DATA_STORE ? 'S' : 'L', type == ACCESS_CODE ? 'I' : 'D'); switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, - 0, access_type, type)) { + 0, access_type)) { case -3: /* TLB inconsistency */ return -1; From patchwork Tue May 18 20:11:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441233 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp581652jac; Tue, 18 May 2021 13:20:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwF/2fK8jMjjchn+cpa83+sOMNoCncE5Mm/ic2wID0wpIzJMc8uPJOulLn/fzmaxUh1yXKS X-Received: by 2002:a5d:9a97:: with SMTP id c23mr2553634iom.38.1621369208450; Tue, 18 May 2021 13:20:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369208; cv=none; d=google.com; s=arc-20160816; b=aFVEWTBp4g1a7b3R9VJTDi2T8DrysRiXDrkhTshXmq0ojQ7SZEQRu9Oa/LCw44GOtk NQHsRLj/2exQ0XJur8sftOHEhVAKMXC4M1IU6yk/n/uVq9APOFDiWX2g4atFbrDu6dej maOUXzClrtU/k1Eiu9YoGUF9qbylFFThOgLXSZc7bP8jPvvl6PMCZl5MB2EgxGZ8o2+4 CRaTVrx51H7wjpJL7BitoQoU3LOpY6WPcPx0rSL3YZHSEN5cfnlPS/ZU/RD+vKL1zGBA ehsiQ3yI+9yTy7tLwb+SZJ23tiUNBeifjMV/nV+jkZNsP3ut8F2hv6izMbfuPJ3jUEyh wPqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fpTZIbiP/0pzPjkmxIM6zBQYIsThwc1ZZvTr7Pkvn4Q=; b=l9uhnCoP09Os8EwsNwkfGmexJw1VaLj2/HvumVQHr7AyS5nNjM6oC45aqefzo/hKl1 vPXf1Tom0clr2YTXMYOWzoJosyHsg/Vx/rMhON3O9/Ve5+iJzRG3Y4QD3DkPAGfMgE5s Re+EMuIjaZ/do4J/ush2PhOlo6CGr7v+qi4YTjbfj5k414bY/c2cJnnmIFwZKsiMAlUg zJ789K4S38YFLNM5rZM1p8/O3mzKfnPEMsbjqiSvJcXBZ2ZC5zcihy9XNZ9dZxQvCNoF EXivB1OQLlfh7i5UOcwAdyCMuuyDUDme1KzACLRkc0cYc1j9U72LdGcMSbkdImjo90ew 1lwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="BXLDH/Hb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 197a75c9e3..506b0e4d90 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -288,8 +288,7 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way, } static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, - MMUAccessType access_type, int type) + target_ulong eaddr, MMUAccessType access_type) { ppc6xx_tlb_t *tlb; int nr, best, way; @@ -298,8 +297,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, best = -1; ret = -1; /* No TLB found */ for (way = 0; way < env->nb_ways; way++) { - nr = ppc6xx_tlb_getnum(env, eaddr, way, - type == ACCESS_CODE ? 1 : 0); + nr = ppc6xx_tlb_getnum(env, eaddr, way, access_type == MMU_INST_FETCH); tlb = &env->tlb.tlb6[nr]; /* This test "emulates" the PTE index match for hardware TLBs */ if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { @@ -314,7 +312,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, pte_is_valid(tlb->pte0) ? "valid" : "inval", tlb->EPN, eaddr, tlb->pte1, access_type == MMU_DATA_STORE ? 'S' : 'L', - type == ACCESS_CODE ? 'I' : 'D'); + access_type == MMU_INST_FETCH ? 'I' : 'D'); switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, 0, access_type)) { case -3: @@ -503,7 +501,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* Initialize real address with an invalid value */ ctx->raddr = (hwaddr)-1ULL; /* Software TLB search */ - ret = ppc6xx_tlb_check(env, ctx, eaddr, access_type, type); + ret = ppc6xx_tlb_check(env, ctx, eaddr, access_type); #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { CPUState *cs = env_cpu(env); From patchwork Tue May 18 20:11:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441232 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp581323jac; Tue, 18 May 2021 13:19:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPRmb0NUFbd2kSttDD0g9KIuBd8GRGpVOfpiZ7plk3Jdz/UgcTAub8r0Uxiyh5b0ygKqp6 X-Received: by 2002:a92:b746:: with SMTP id c6mr6612877ilm.240.1621369180042; Tue, 18 May 2021 13:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369180; cv=none; d=google.com; s=arc-20160816; b=XtbLWt79KDACKuzaaTkyQ6aIB06ssA/kSKWXDws2nafMf0UJpEUXUA1m9p5TI8hf3E e6wj0m7Gt8gdze1LNRzQ12SbimNTBHip9y0ZrpBct5Q/4l0lgRraPlz2QHz3Y/c3Ok/9 uXhzZRHHV3BXwDCe71HAbgdnsxXkPkbxMPo7jKpSykDxXnj2CikGDNqcud3C2kK0aKdO LiDa8KOONQaIca1go2Mhgd5blObXGW0p8hrYeRhwoSz0lejgYhuGRDNNVOsIrD0NSB7P Iw7ccK1jMLzfrGp0pMRgNAx7RgySvKwRBlOG00FVxGkpVRVHdvQJbP/vQX47BEDbT03V Tqfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iRIwmv/u97xPnpJtsivAqnqvUPyTpMn8dKYh7FflpCs=; b=lZCqpp56oFzazjTt8UjrT48zpcWAtuU9PlSqog5tabUps6sW5TOhoC+8bDCYdImKPv U8SZA49AhPNVn31w/aLgP/n1adpVer2pLuvgtzCwj1X7fx6pWBXg9oO7KSxN60p+dFZR 8kqL1iWMMe9mT1Dv/LBBNhQkgxxXTPnE7UCtIEzbRe2S30goT/wAUXEIrtw02XXSuW8h GJjJofSfWFBQAXRRcO9O2CmwuHwUND9w7fIa34t0jgxnm7IqCjro7HhFpzKFM4MzrRSP Kw7oQ5YIWQGWEnmluW1HOXjvECLRgklMO7ps/AX1/eWb6Iu+KnTCxQoUT8b1yNd552Bm DaDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RweNGdj9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 506b0e4d90..0809210d3b 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -379,25 +379,22 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp, } static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong virtual, MMUAccessType access_type, - int type) + target_ulong virtual, MMUAccessType access_type) { target_ulong *BATlt, *BATut, *BATu, *BATl; target_ulong BEPIl, BEPIu, bl; int i, valid, prot; int ret = -1; + bool ifetch = access_type == MMU_INST_FETCH; LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, - type == ACCESS_CODE ? 'I' : 'D', virtual); - switch (type) { - case ACCESS_CODE: + ifetch ? 'I' : 'D', virtual); + if (ifetch) { BATlt = env->IBAT[1]; BATut = env->IBAT[0]; - break; - default: + } else { BATlt = env->DBAT[1]; BATut = env->DBAT[0]; - break; } for (i = 0; i < env->nb_BATs; i++) { BATu = &BATut[i]; @@ -407,7 +404,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__, - type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); + ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl); if ((virtual & 0xF0000000) == BEPIu && ((virtual & 0x0FFE0000) & ~bl) == BEPIl) { /* BAT matches */ @@ -441,7 +438,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx "\n", - __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, + __func__, ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl, BEPIu, BEPIl, bl); } } @@ -1415,7 +1412,7 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, } else { /* Try to find a BAT */ if (env->nb_BATs != 0) { - ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type, type); + ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type); } if (ret < 0) { /* We didn't match any BAT entry or don't have BATs */ From patchwork Tue May 18 20:11:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441231 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp580333jac; Tue, 18 May 2021 13:18:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxklgrzo3NEKK+F9WUhsvoDNBg3u+0ZHCy/PmIM8SxxzrU8aKAuk6sWjFWpvf/NbyA1X0CJ X-Received: by 2002:a6b:3119:: with SMTP id j25mr2404327ioa.64.1621369097079; Tue, 18 May 2021 13:18:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369097; cv=none; d=google.com; s=arc-20160816; b=cBuhpv3mrV8nlXHsgV7BFDQu5XpHIv8PM6qINAAlAhnQ0WuLBjZcbCukFuD8xEcwfR jCs1kbNz5oxSTkm5TS+4T8knCv0gryFLiVTExvnbeYu3XKxfbdxL5pFillrdZHylXYhA U8HnTgNXHj/E2BvuNYcrWIsz4fzUQozE+znw6lzUpumPV4qRUkQ//oSEx1SVKJrYQGAa 2+OdfGfdFoX8GZvY8qkBMrMYZbrruxLq/gkBO8ZDmThbbvofvCaqwBaxoBrkBAGpysS9 UFIIoDdQiAfYsJdswdUWKYdNPAvDj0b+i5/J9kBu8cb0t1n9mzd095lOAzri+y9qAbvo Vf5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qp5VjSCeaT10WMmzJ0whXnqim/gDuoCvf6zAj9wZwT4=; b=H6qAQlp3URQhH7zbcEXHdt31FSmBvABjyXeRidz+dJxRNXobYAuOz9VwwyXiot3lX3 uNm3a0eO83QfyST2XEGWpLMSzy3YY0bRpED++iMpnCUMy9nEIQoNgckINz/w4atbqF7q Y1E8+aSxAVTNS6O+z+0flSQF4fNw7I9/+u82ovGMF+t4ZkNBxxETeQIkJAHlQjK5YUC/ fERmJ77em5DtecJnqeR9BMYRWFzzWR3cRkLC+PT7V1dt51PiXeEXLRDdGycSIXK2E+6t 2LpAyMWwZcyWhQCbbwGb/I7k9tPxuvTgn5D0x0mrqn6kawt/g/mtsj6TK6dAaoenCVb4 sklA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GmIT0E9d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 0809210d3b..6860a2aea0 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -662,8 +662,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong address, - MMUAccessType access_type, - int type) + MMUAccessType access_type) { ppcemb_tlb_t *tlb; hwaddr raddr; @@ -1426,8 +1425,7 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, if (real_mode) { ret = check_physical(env, ctx, eaddr, access_type); } else { - ret = mmu40x_get_physical_address(env, ctx, eaddr, - access_type, type); + ret = mmu40x_get_physical_address(env, ctx, eaddr, access_type); } break; case POWERPC_MMU_BOOKE: From patchwork Tue May 18 20:11:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441236 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp583761jac; Tue, 18 May 2021 13:23:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7PkCnNNvM8u9aetsnZT0Y1IyRpSv2k7K8ttgBVJ/E6stHmi8cZeLFli/8rENUqqdZmIrM X-Received: by 2002:a92:cd85:: with SMTP id r5mr6206493ilb.294.1621369381532; Tue, 18 May 2021 13:23:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369381; cv=none; d=google.com; s=arc-20160816; b=rU1Z2wAes/xpBrYD+Ye/ORMm0zIJ3QYakMyQw595o0F0iEopJMOZ1pslW7++FSQBel Num25+w6DCOCx+LeMZ+jeCZq5pz+zmtDFCxXpORhcbnCq1EXCJXifoQoEk1aKJ1ETpaC aHo2pS+Ic/qV3BWfI8+Ha6OSwJRH6TP+yAGUN+HhQlzs+D3aW4rYk0Od6mO+nA/iTjHc WsO3MZ6QKnvFisvk0xSvPH1GR77Bb3bkkC4Jl3XR/W4ACP2HldpIiH57jzjTAB0CUBzn v4/Xb1+1M2X4gEIGhqamg44rPFOWTMVtKp6dCF9/qf3ehOGrzZBYQON/sk/Uqk1mKQGP Jzjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XCI8pCW9Sv6UEY79hKdFH08fK4Rjq+LJfm07d74fiMU=; b=iDKokcmSFjNpJTr+ZvamStouij1LeRpLWPcAt0hyaRAnpbL+kmYnMa2SObdghoCzwV XdXPN+4SU/RcnRBBXgzCq2BPf7WnU5htM2G0pcjihvUNe/wzi0PqVicaCjNPEhEQcJts /fBSKimSFTMw/MZ5o3ZxcrR/jtxH6FUTLvS+cS3lXSUkilSxjdQHLlFo9MxRkfhLlaV4 LYZI/55V+zRMOw25ojDMvPQfMThj41J/xVj7Pyfb+ZqG6rXWzddlXXplNeLQo2xlXp78 jB521eYI+/kWrKaLj1a8zdrqirTngqtoh2HSTS1PQMmrOk4fzwaO7SnxY6wwvGVoSv83 4GYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pj3d9+cP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Unify the I/D code paths, making use of prot_for_access_type. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 46 +++++++++++++---------------------------- 1 file changed, 14 insertions(+), 32 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 6860a2aea0..83e7e0dd13 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -738,9 +738,9 @@ void store_40x_sler(CPUPPCState *env, uint32_t val) static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb, hwaddr *raddr, int *prot, target_ulong address, - MMUAccessType access_type, int type, int i) + MMUAccessType access_type, int i) { - int ret, prot2; + int prot2; if (ppcemb_tlb_check(env, tlb, raddr, address, env->spr[SPR_BOOKE_PID], @@ -772,37 +772,19 @@ found_tlb: } /* Check the address space */ - if (type == ACCESS_CODE) { - if (msr_ir != (tlb->attr & 1)) { - LOG_SWTLB("%s: AS doesn't match\n", __func__); - return -1; - } - - *prot = prot2; - if (prot2 & PAGE_EXEC) { - LOG_SWTLB("%s: good TLB!\n", __func__); - return 0; - } - - LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2); - ret = -3; - } else { - if (msr_dr != (tlb->attr & 1)) { - LOG_SWTLB("%s: AS doesn't match\n", __func__); - return -1; - } - - *prot = prot2; - if (prot2 & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE)) { - LOG_SWTLB("%s: found TLB!\n", __func__); - return 0; - } - - LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, prot2); - ret = -2; + if ((access_type == MMU_INST_FETCH ? msr_ir : msr_dr) != (tlb->attr & 1)) { + LOG_SWTLB("%s: AS doesn't match\n", __func__); + return -1; } - return ret; + *prot = prot2; + if (prot2 & prot_for_access_type(access_type)) { + LOG_SWTLB("%s: good TLB!\n", __func__); + return 0; + } + + LOG_SWTLB("%s: no prot match: %x\n", __func__, prot2); + return access_type == MMU_INST_FETCH ? -3 : -2; } static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, @@ -819,7 +801,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, for (i = 0; i < env->nb_tlb; i++) { tlb = &env->tlb.tlbe[i]; ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, - access_type, type, i); + access_type, i); if (ret != -1) { break; } From patchwork Tue May 18 20:11:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441241 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp586093jac; Tue, 18 May 2021 13:26:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2mfHW+hEKWf74zNEtGgYnkT8wUo4RROMT1XX1GMyEO4+nP1tAqAEtmplVMHLzCytjkWXm X-Received: by 2002:a92:c74b:: with SMTP id y11mr6489143ilp.302.1621369569054; Tue, 18 May 2021 13:26:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369569; cv=none; d=google.com; s=arc-20160816; b=zy0QAdP4quflfuoxbffAHKzULTkxD8Kuc2c4/wJTAewW2HPR7JNZmkbSyBL7Ev7zwH V9HZPaqdl4/Hdfed8FXTObrr6kc7nLS0XEibVcpliGsR7Gr9AyEp0lKoqasl0mIt176M kymKO4xPEU3beuXFR5RL9fU3r75P0OTs9pNf+1Hi/DPMdzlR0FEYKjwXRV76LCLMtIQv MTd1vs/dQpAcJ1h1ACIvy1dPKdD2euuz/oezqyCh+zhydEc/lMlE9S3ueaHqLEeJfMXU Lk6HGXZzLEKDx2jC7zBOmNYpcNRL7odOdH7BVsbqBhl3mDUDurL21ts7CBgcToEc1C8X /cBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uCYHwJd3aHPp89iGRxDBfWMsI6JKv06e4ILxtJtVTfA=; b=wKPjvp5QNb3yjxlbFlwfYgCUkzuKVNCJgmNCMmdANhKfV3d4sVWql8kL10/YBxoXaO JT/iLqWyEiE2zdlsJAqeZKeGNNGe2Wg3lUrOnPRzn3qIWScmkvxfNJmUAximE0d3pV+v jw9WFuc+3CSs+KIiuPzZK3w3LXl7TPXgsvuRhqx52Fa8JD4DKRvmzhDRt5mBbNKDGQql EYWqUt1mXlNaTIcSEGNTPwv2A/T1Y4zYvHOnhdLNJdIgKaqCuY9KVUNggOVxrxQhCbCq ckdvf5Jn6QZ2VfuQhdjBPsFK8L4N2Te7My7vxJMHWJRq4Tt2MVJFiOqIJM240T585js5 gtdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UdWIE5oP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 83e7e0dd13..bf0fcca9be 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -789,8 +789,7 @@ found_tlb: static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong address, - MMUAccessType access_type, - int type) + MMUAccessType access_type) { ppcemb_tlb_t *tlb; hwaddr raddr; @@ -1411,8 +1410,7 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, } break; case POWERPC_MMU_BOOKE: - ret = mmubooke_get_physical_address(env, ctx, eaddr, - access_type, type); + ret = mmubooke_get_physical_address(env, ctx, eaddr, access_type); break; case POWERPC_MMU_BOOKE206: ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type, From patchwork Tue May 18 20:11:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441237 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp584196jac; Tue, 18 May 2021 13:23:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+JQeNnLzDQ7tUkzbQlEKBydWy2FRMwOz3BnAcDweR1MXcTIaynvwuro5v1Gm98uqbVc+c X-Received: by 2002:a05:6e02:b47:: with SMTP id f7mr6538047ilu.261.1621369411620; Tue, 18 May 2021 13:23:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369411; cv=none; d=google.com; s=arc-20160816; b=UUWDr+Ki3wul0uaiuz6CYHh7RJydxGp3K9RtbbLPhwy5I6ftMgJFMgUvZFze1wX4KN aw12cY5jFGPZUMKzvQdwh483k7XOozTx/wFOwMvUKRwGzwbuEEh/efsjn8ryyuwz8eFL AFad+hFoc63uyEaVM7OYDk/vImQAafgzuFFqIaYp71IWXdcKcMniW7HaljaC+XMXLfJX DAUQD192znp4CAqOXuXq7KsjS61oOI3da3XRiyMKwdzerMfD6SozEdUG2SiuEXwaigzY 6iCg/XwxTly/CWudM0c50y5u5xUy3rfSdWKOv/qCwoWRKHWrSh0TIqveQE1fiNy7P47s lTsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iRYIXTh9YtTWQKT/ZBagL9R5DPvobu3+3oVqu1iYRUI=; b=kHpkJizpjc2lrfg6i5socgnpolhAS9m+1zRCAA5dqMMEsuRdpz84rJBduhDPiqosB7 LSxUh0iuromMsQhtjub/6kHZyv7G7xwiE/NGCOwZP31JX6NXYt2X7Oax+v7gCaIMyTZh RlypCL2Sr50bYi06/0G9Aeg8MlHrDE8XyExG7siPb6iR7Tmr9NUGzbBz4vBaVjfWUi6Y F94IStcvFS4IokimvwUUEamQPywoeZbbyrXJulK9gsqBRXeKec3RXQoNQ7IKoVxfaw2H WdMUKuhGQ6kNCv0565NOrlElqdUuTy9PsctgepBqIb5p0AclYE5MJvE76gPCFIVGqEOW wgAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VLzbPSNv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u13si13100733jak.126.2021.05.18.13.23.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 May 2021 13:23:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VLzbPSNv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lj6FX-0006vU-2P for patch@linaro.org; Tue, 18 May 2021 16:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lj64f-0000ov-4S for qemu-devel@nongnu.org; Tue, 18 May 2021 16:12:17 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]:40550) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lj64S-0006HD-7U for qemu-devel@nongnu.org; Tue, 18 May 2021 16:12:16 -0400 Received: by mail-oi1-x22e.google.com with SMTP id s19so10957105oic.7 for ; Tue, 18 May 2021 13:12:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iRYIXTh9YtTWQKT/ZBagL9R5DPvobu3+3oVqu1iYRUI=; b=VLzbPSNvuooJ31snhYW5fOHMqvXooMOLxuQrHUb5o+Pxs1xr8ha7l1v/gV9ksqnHW6 1GzMxDRlNwA7aYMXOcFzczOewhte1y7TcTfVsbR9EY0CygofTcCa17Iie7mpWnMf2uy0 MvgQ1Qbs7yIXCGQSpVxU74rBBScguwY0PZVGjCi7pUOBQbVLYnFHP/AvlTDWMfPVDtOB +ygkXQakddLUFutxRKh+TYvTgn4R01//tjP/+CuViHMgJeOxSSE5RkeYRUsvcc5ikwtt S58hVoiRUCWMV5z4JZWNlLJAsXcnVpmCjBH8RBzT7YGV8hL4dDPta0yDDfUhyuNDs+wo SQBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iRYIXTh9YtTWQKT/ZBagL9R5DPvobu3+3oVqu1iYRUI=; b=CbOaO+PXsPqwPTMS0oYNJ50S3/gCYfrF4OgOY0M81yuHC+VESCcSa+yWDdccMcW/wH J0k13ZNbzjpHgyAyUwDSvQeVw/8Y8JXbv+hJm+Q5OKBlAB5wbC8hiaXBVKngLv6UumWW gnu8AnlPLOUZ6lF86vqzZhsCBLKXTjey6ziqBoQwIxmwQO/5UJJLJhemgufHisttXmac sGJLWRiM3YdgTKTXuJLFO/XpGjU9NuatxquFRzpxEj/LIrmRbRwkUHqER6knTQk5MOJ1 m/dO5gj4jqOlW7D6tnzCJq5uJFso+6VlSxS1XeXKRk0CRVu4R/fYks9/5NAioNJUUBRQ DxgQ== X-Gm-Message-State: AOAM53029+rvy1eIMoulfEFd2M2ul+5ggEjRihxZ0V9i//bWkzGPcQtw h9KGDiCKNhws+aSED/QTkt6qGABh2dWfsix8 X-Received: by 2002:a05:6808:14cc:: with SMTP id f12mr5280196oiw.115.1621368722292; Tue, 18 May 2021 13:12:02 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id u27sm3953204oof.38.2021.05.18.13.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 13:12:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/24] target/ppc: Remove type argument from mmubooke206_check_tlb Date: Tue, 18 May 2021 15:11:36 -0500 Message-Id: <20210518201146.794854-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518201146.794854-1-richard.henderson@linaro.org> References: <20210518201146.794854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can now use MMU_INST_FETCH from access_type for this. Unify the I/D code paths, making use of prot_for_access_type. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 50 ++++++++++++++--------------------------- 1 file changed, 17 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index bf0fcca9be..90038e3e76 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -944,10 +944,8 @@ static bool mmubooke206_get_as(CPUPPCState *env, static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddr, int *prot, target_ulong address, - MMUAccessType access_type, - int type, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { - int ret; int prot2 = 0; uint32_t epid; bool as, pr; @@ -1004,39 +1002,25 @@ found_tlb: } /* Check the address space and permissions */ - if (type == ACCESS_CODE) { + if (access_type == MMU_INST_FETCH) { /* There is no way to fetch code using epid load */ assert(!use_epid); - if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { - LOG_SWTLB("%s: AS doesn't match\n", __func__); - return -1; - } - - *prot = prot2; - if (prot2 & PAGE_EXEC) { - LOG_SWTLB("%s: good TLB!\n", __func__); - return 0; - } - - LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2); - ret = -3; - } else { - if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { - LOG_SWTLB("%s: AS doesn't match\n", __func__); - return -1; - } - - *prot = prot2; - if (prot2 & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE)) { - LOG_SWTLB("%s: found TLB!\n", __func__); - return 0; - } - - LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, prot2); - ret = -2; + as = msr_ir; } - return ret; + if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) { + LOG_SWTLB("%s: AS doesn't match\n", __func__); + return -1; + } + + *prot = prot2; + if (prot2 & prot_for_access_type(access_type)) { + LOG_SWTLB("%s: good TLB!\n", __func__); + return 0; + } + + LOG_SWTLB("%s: no prot match: %x\n", __func__, prot2); + return access_type == MMU_INST_FETCH ? -3 : -2; } static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, @@ -1060,7 +1044,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, continue; } ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address, - access_type, type, mmu_idx); + access_type, mmu_idx); if (ret != -1) { goto found_tlb; } From patchwork Tue May 18 20:11:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441235 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp583727jac; Tue, 18 May 2021 13:22:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwb8B5a8/DH7TCB/vyBwnokB0zLGyVL73rEynoA7jsa2+plJxQ3gRc3XWhYCC34+PK6VPcY X-Received: by 2002:a05:6e02:1a04:: with SMTP id s4mr2656957ild.125.1621369379516; Tue, 18 May 2021 13:22:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369379; cv=none; d=google.com; s=arc-20160816; b=nP6Wn5wNqq6rQ9VLAcDcuwgFXrwkGqqnYDjSM55g7jNTffmc9SD2Z218XZ/MqhPzRY i5HbyeQDsBuPBMVqwmwhzPrSU7L6xgMv1B15PCqyLxNwWBKtzixrOHyS93nxYFi7xJU0 sZu4opyCFdeCMmHAmPdDsbHeCQvcuzw+SKHzRoTl/FUfqc/mJRZs6HSEx4kv14p/w3CX de7epJPnHNxgiB/akjDQrOiZB6vZyHw/dZsreTpj33QKBav+/d020txjB37ESp+Fc7DI vrCRLJbBy86vd+nzEozdZfBKpfOMLXbDpQPw19HqkmJirEQjsCSNCgh2dX7wU1ITiu8C +f5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LMdpCRKULuXEwtYc9AZQuEF4Jiu7c6b4ewgl9c0X7gU=; b=N2+vKjmlfpG5DMr3jspfabF2foEh+f2gkuGqfrkolPDp5Wn1DS3L7fwpDARjzn6Jz1 9dWqhpPB4gKrog9wjg0CeNPLyCvdmoqAWrto7ZAgwX+qk2YWmOPfJOJQe8Lo/hd0MvU3 7cl+TJHlu8i6Iuo1Y43mFDqeB0ITRI8i6ysGRDI6pQvxQJxx+xSNUse4G71Q26mKnvVG KpyoNTX60RlCsn3Tz0Gj8a+1rvKqaMrcRavS1sGb/dYsOayPRww03MHPS2PF9o7Eipgt xvUiRjFTwPh9cmHWHy68Fuu5sfzxkgodbo0C4iyW2WGpIV0o988s3/qX/8p9+Rk3YBwu ZZqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Bt8bz4hi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 90038e3e76..ef634fcb33 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1026,7 +1026,7 @@ found_tlb: static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong address, MMUAccessType access_type, - int type, int mmu_idx) + int mmu_idx) { ppcmas_tlb_t *tlb; hwaddr raddr; @@ -1398,7 +1398,7 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, break; case POWERPC_MMU_BOOKE206: ret = mmubooke206_get_physical_address(env, ctx, eaddr, access_type, - type, mmu_idx); + mmu_idx); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ From patchwork Tue May 18 20:11:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441238 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp585700jac; Tue, 18 May 2021 13:25:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgrsprProTGqFc+bqr9imX2TkF+ZGivwHJSTqQKHsc6Rwl+1lvdUQwUKqtvKVA/5zSU4hH X-Received: by 2002:a05:6e02:504:: with SMTP id d4mr6459513ils.178.1621369532396; Tue, 18 May 2021 13:25:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369532; cv=none; d=google.com; s=arc-20160816; b=idmHsTzIEXun5SNym6ATFEWrDf8CPqWFMHmsKga4W23JC039OWm8qp4klHW4T38XHg mTXqk6r+2FdvpVrN8SVJLsmYIrcF09ff+EmrY+ErFaAoaxYE+SqWQBGK2Vo8drOfzIZX TPPAaBlj6NS+HkirfORqL4xbhrOLdOl/Eqwb7tQI7bnVEK06be95emncTS2Ryx9EZ9Vk 7lHvqK8Tc2pchQlPGD3JRkvrsq2l+X8MEHaxx+HZiYC46Fbj4/20K9KEMoTdFJETEyCJ tWlWaYvXRuzknvlp43onBrZQvnlEbVVxCKiUF1pNF+Zb6oI7sRG91kosUPJqW+6JHE6O 7Umw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=t1r0lLSqHjjKE2pLj2JipZ/ZLiJZUx0FOO0kIdrgSBM=; b=SPOOQAICuQP6iaVdlJfs/S7KIUaVaxbNgmD36ELJeosqRNB8/ZZtctsFE+ssXWFvu6 fADB+6aG5b6hact75KR/RdaB4FePpA5LmIKQijdNQ6u1ulF66o906F3/2aGrkhGQL8IP JmYRWU7w5YB8cSNkw+J+X6HWJ5uodQ5rLFMZmnxosoxI35X4mtJqQulIi8iYSkLqecyH FCrvtnFtmeNrT6LSarL8NAn3mTSZnYSFIsLofyq2M3eoMrzZlFc4jjrhs5470pVj43L2 CacnX0noqiK7+42Pw3Le7Qsnzjcnt+pd3bZwn4SuvyddwQxRPYbpNQMFy6AuM+DxXQGO A6lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="VY+/hYeb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This avoids some replicated information in cpu setup. Signed-off-by: Richard Henderson --- target/ppc/cpu-qom.h | 1 - target/ppc/cpu_init.c | 45 ----------------------------------------- target/ppc/mmu_helper.c | 24 ++++++++++++++++++---- 3 files changed, 20 insertions(+), 50 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 06b6571bc9..3b14d2f134 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -198,7 +198,6 @@ struct PowerPCCPUClass { int n_host_threads; void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); - int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); bool (*interrupts_big_endian)(PowerPCCPU *cpu); }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d0fa219880..d33aded7cf 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -4580,9 +4580,6 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data) (1ull << MSR_IR) | (1ull << MSR_DR); pcc->mmu_model = POWERPC_MMU_601; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_601; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; @@ -4625,9 +4622,6 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) (1ull << MSR_IR) | (1ull << MSR_DR); pcc->mmu_model = POWERPC_MMU_601; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; @@ -4891,9 +4885,6 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_604; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_604; @@ -4975,9 +4966,6 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_604; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_604; @@ -5046,9 +5034,6 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_7x0; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_750; @@ -5126,9 +5111,6 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_7x0; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_750; @@ -5329,9 +5311,6 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_7x0; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_750; @@ -5412,9 +5391,6 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_7x0; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_750; @@ -5500,9 +5476,6 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_7x0; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_750; @@ -5588,9 +5561,6 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_7x0; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_750; @@ -5830,9 +5800,6 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -5916,9 +5883,6 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6745,9 +6709,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -7507,7 +7468,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) (1ull << MSR_RI); pcc->mmu_model = POWERPC_MMU_64B; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; pcc->hash64_opts = &ppc_hash64_opts_basic; #endif pcc->excp_model = POWERPC_EXCP_970; @@ -7585,7 +7545,6 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) LPCR_RMI | LPCR_HDICE; pcc->mmu_model = POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; pcc->hash64_opts = &ppc_hash64_opts_basic; pcc->lrg_decr_bits = 32; #endif @@ -7729,7 +7688,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits = 32; #endif @@ -7906,7 +7864,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits = 32; pcc->n_host_threads = 8; @@ -8122,7 +8079,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; /* segment page size remain the same */ pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->radix_page_info = &POWER9_radix_page_info; @@ -8334,7 +8290,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; /* segment page size remain the same */ pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->radix_page_info = &POWER10_radix_page_info; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ef634fcb33..863e556a22 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2963,14 +2963,30 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, bool probe, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); CPUPPCState *env = &cpu->env; int ret; - if (pcc->handle_mmu_fault) { - ret = pcc->handle_mmu_fault(cpu, addr, access_type, mmu_idx); - } else { + switch (env->mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: + ret = ppc_hash64_handle_mmu_fault(cpu, addr, access_type, mmu_idx); + break; + case POWERPC_MMU_3_00: + ret = ppc64_v3_handle_mmu_fault(cpu, addr, access_type, mmu_idx); + break; +#endif + + case POWERPC_MMU_32B: + case POWERPC_MMU_601: + ret = ppc_hash32_handle_mmu_fault(cpu, addr, access_type, mmu_idx); + break; + + default: ret = cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); + break; } if (unlikely(ret != 0)) { if (probe) { From patchwork Tue May 18 20:11:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441239 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp585764jac; Tue, 18 May 2021 13:25:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyENyVXrofZVzbs291KVWk0Y4iWQl/TVT0gkj+F8DCqsxzROwzdE0d5Byhj1gJ/pgruyTKO X-Received: by 2002:a05:6e02:1d18:: with SMTP id i24mr6435071ila.157.1621369538828; Tue, 18 May 2021 13:25:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369538; cv=none; d=google.com; s=arc-20160816; b=OQc/CevbKh3Wwt+DiNvF0lNheHH0zg5Uz4uAWZHAJSR0ZhZ8+/uK1mBNIJ78j4EfZF qpQjLJN+AENW+f0zFDt6+M4y657SmgOp62Wq4f842nUt+QZkvw4iqms3v+s/1q8KbhUY 4rojRZlHvl9OdR35EvJaxKf1CcvbdZRq5YE84spKQk4w/OVrgkn6UwxeVWaW5lK/gmm5 jGLs8pWGJMg7+VCHNHiTZIzL0g+U2+LCNljt30MbdWVXEQU43ajSP5MetUvC5yMB5kR0 ufZ2vZ5Fji+9Gp+v5+7Sxgi5VjP9WQDAheE39AqT/Owis6MOqqtnSDy6m26CZaNBEiMj 3g2Q== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id h1si774790ilo.16.2021.05.18.13.25.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 May 2021 13:25:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=srWYLrfk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lj6Ha-0002yv-6f for patch@linaro.org; Tue, 18 May 2021 16:25:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lj64g-0000ws-Uk for qemu-devel@nongnu.org; Tue, 18 May 2021 16:12:18 -0400 Received: from mail-oo1-xc2d.google.com ([2607:f8b0:4864:20::c2d]:36534) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lj64V-0006KH-R5 for qemu-devel@nongnu.org; Tue, 18 May 2021 16:12:18 -0400 Received: by mail-oo1-xc2d.google.com with SMTP id v13-20020a4aa40d0000b02902052145a469so2516314ool.3 for ; Tue, 18 May 2021 13:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=usq8qtlgC3o9/Uyj8zLYVbmtA5cNJErk7QF+4PTr5tk=; b=srWYLrfkHQfgg64i83c1scQHJ8OrygxvKb+9keuebuY/z81CMSCTX1l6hkoJSODHYt JScjxARpUp2X6DqNCfWVd7G4CxV47f5kc0P0Ym7K+hsxJoigfhQKKmRRf5fzVxhynflh mzbnN07C7jFdrAnPuZ5JjezrILIvB1tBNGqVpeBinrv7+dhl1PHlBtpP5e8rBPBfb6Fo pKq31+Ouz7GEUnayBAjDAVxD2u5pW5e3gwIIrE0Jyf/0qqKKX+bBc6PvOgIN/4rJyS4w IAFzQBDescDGL9gv+i+BP12dh/vlzWhhftYJbfdSjQRNHyCNKR6JUJ4XvKH56upnLkuO ILbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=usq8qtlgC3o9/Uyj8zLYVbmtA5cNJErk7QF+4PTr5tk=; b=rd3COzzjpwU9RXN95oss321J2NaqkmJCZDa9R3X9BvI1VaMxuLhfNMxtdM/7SWriZ6 bWnzh/qqsI8KUDM/wWCExJIy+lRMVybecJHobt4FXEB6QAehmjKVyT2bECxc9dWud5/a NSsLTDgYw910BmiDZ6YjrASOC6XU/F+JmhCx+tFHY+yrLxJwsbdUwAvbleyZPrP/sgW6 haARnNduQoURdU75y3+E2I86zECkRvKdwjfdB0iry/Tgnjgpk/e8KESmcdiBtYUtaOSV i+snRmVNY3jhb0dn6R3orGImjQM91P76r2OYElcRRHRLne+jGo2m5l5TbqdV0kuB7lO0 MHVg== X-Gm-Message-State: AOAM533THAQfxPREt4qsQxPqVvhcIoSFqGLqSn+1srZ3r0ndc/44mwvT MUuwooeBWaDoGo2YsZWqmJFVxkb2tyNNVumj X-Received: by 2002:a4a:625c:: with SMTP id y28mr5727630oog.45.1621368725224; Tue, 18 May 2021 13:12:05 -0700 (PDT) Received: from localhost.localdomain ([45.235.253.15]) by smtp.gmail.com with ESMTPSA id u27sm3953204oof.38.2021.05.18.13.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 13:12:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/24] target/ppc: Use MMUAccessType with *_handle_mmu_fault Date: Tue, 18 May 2021 15:11:39 -0500 Message-Id: <20210518201146.794854-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210518201146.794854-1-richard.henderson@linaro.org> References: <20210518201146.794854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These changes were waiting until we didn't need to match the function type of PowerPCCPUClass.handle_mmu_fault. Signed-off-by: Richard Henderson --- target/ppc/mmu-hash32.h | 4 ++-- target/ppc/mmu-hash64.h | 4 ++-- target/ppc/mmu-radix64.h | 4 ++-- target/ppc/mmu-hash32.c | 7 ++----- target/ppc/mmu-hash64.c | 6 +----- target/ppc/mmu-radix64.c | 7 ++----- 6 files changed, 11 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 898021f0d8..30e35718a7 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -5,8 +5,8 @@ hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, - int mmu_idx); +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, + MMUAccessType access_type, int mmu_idx); /* * Segment register definitions diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 4b8b8e7950..3e8a8eec1f 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -8,8 +8,8 @@ void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, - int mmu_idx); +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, + MMUAccessType access_type, int mmu_idx); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1); diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index f28c5794d0..94bd72cb38 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -44,8 +44,8 @@ #ifdef TARGET_PPC64 -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx); +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx); hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); static inline int ppc_radix64_get_prot_eaa(uint64_t pte) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 744a763f44..d51be59f95 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -416,8 +416,8 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx) +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -426,11 +426,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, ppc_hash_pte32_t pte; int prot; int need_prot; - MMUAccessType access_type; hwaddr raddr; - assert((rwx == 0) || (rwx == 1) || (rwx == 2)); - access_type = rwx; need_prot = prot_for_access_type(access_type); /* 1. Handle real mode accesses */ diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index f48b625f48..877a01a296 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -867,7 +867,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) } int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - int rwx, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -877,13 +877,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, hwaddr ptex; ppc_hash_pte64_t pte; int exec_prot, pp_prot, amr_prot, prot; - MMUAccessType access_type; int need_prot; hwaddr raddr; - assert((rwx == 0) || (rwx == 1) || (rwx == 2)); - access_type = rwx; - /* * Note on LPCR usage: 970 uses HID4, but our special variant of * store_spr copies relevant fields into env->spr[SPR_LPCR]. diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 7972153f23..f6d96f73b2 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -556,19 +556,16 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, return 0; } -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx) +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; int page_size, prot; bool relocation; - MMUAccessType access_type; hwaddr raddr; assert(!(msr_hv && cpu->vhyp)); - assert((rwx == 0) || (rwx == 1) || (rwx == 2)); - access_type = rwx; relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr); /* HV or virtual hypervisor Real Mode Access */ From patchwork Tue May 18 20:11:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441240 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp585935jac; Tue, 18 May 2021 13:25:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRiGV16nArcVznyXtSFLeEpvkl8YIMt0dISNVHZU1ssHTO9B6Vf7Xck2VX/qs5BtLk37ZE X-Received: by 2002:a92:cda7:: with SMTP id g7mr5730391ild.50.1621369553100; Tue, 18 May 2021 13:25:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369553; cv=none; d=google.com; s=arc-20160816; b=f7TSN8Szt6UNz+qbqPOvRKU4ihlHFghGD9mZeSlYHRQw31JEe65tF9+MNRKLPE4+9I YOqQ7c33VX3IIZyYjZxPNjgr6bH7PvMvAIeKKdHpwKvurlS6jImOJOfCNyfpI2i2mck/ fRnEy46OBmfVZA1zCD2TS1kjoCKi92FTX9jV/8OuM5gp/gsVfdOjx4rQZ22L2UQhq+HZ VuRcVZ6m362Ap10fwCJZpElyBUyLsQCnIZrVw+eOwtGA+FESuBf4L/Cyl91k+n11ODHs nCVrsmTzBGEQ0++49aJQMSFQVIECxqcAsEUb6pyMDRumlj27zit/z0LhXqSWF1/Jh3fE Pqog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yiIWnhh+AhXMOoA+lyy+GgIYPIOtyeBfLpA90XRjnLE=; b=Cb494GxD8qBwZdTcI5pCV9PzKJbFVeZWY7o+i7cDuC/SWMirohagoeqqt5CPNabYcb xtd8IlWnJw7dWvYYiyx8RGB1IHSIRpZcF4g4ybzN9Ht7BZSjkqhj8oEmHtcyVUWrJzJe wHt5coyuiSPAqa4hER5zfkSyJjXJaoIY+3ineDdpJF92z/HsWYQ9Gs7/XlYQ5q4uQa89 jixN+QPTDn1A9kD3eihxYxaBHf5sYFJ7G0pkTZDPvomRsllk0uOuzwT41jODrrgwypmK ll1P5xjpLWnIHM1oiwb36p6FHPI4NQrQzsxztREtSsLWOrROYeuyYoQVLeepDM7fFQKT t6jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K80mY28b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The former was correct wrt SPR_HRMOR and the latter was not. Signed-off-by: Richard Henderson --- target/ppc/mmu-radix64.c | 77 ++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 43 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index f6d96f73b2..76a5cc8cdb 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -466,7 +466,6 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, */ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, - bool relocation, hwaddr *raddr, int *psizep, int *protp, bool guest_visible) { @@ -475,6 +474,37 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, ppc_v3_pate_t pate; int psize, prot; hwaddr g_raddr; + bool relocation; + + assert(!(msr_hv && cpu->vhyp)); + + relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr); + + /* HV or virtual hypervisor Real Mode Access */ + if (!relocation && (msr_hv || cpu->vhyp)) { + /* In real mode top 4 effective addr bits (mostly) ignored */ + *raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; + + /* In HV mode, add HRMOR if top EA bit is clear */ + if (msr_hv || !env->has_hv_mode) { + if (!(eaddr >> 63)) { + *raddr |= env->spr[SPR_HRMOR]; + } + } + *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *psizep = TARGET_PAGE_BITS; + return 0; + } + + /* + * Check UPRT (we avoid the check in real mode to deal with + * transitional states during kexec. + */ + if (guest_visible && !ppc64_use_proc_tbl(cpu)) { + qemu_log_mask(LOG_GUEST_ERROR, + "LPCR:UPRT not set in radix mode ! LPCR=" + TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); + } /* Virtual Mode Access - get the fully qualified address */ if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) { @@ -560,43 +590,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, int mmu_idx) { CPUState *cs = CPU(cpu); - CPUPPCState *env = &cpu->env; int page_size, prot; - bool relocation; hwaddr raddr; - assert(!(msr_hv && cpu->vhyp)); - - relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr); - /* HV or virtual hypervisor Real Mode Access */ - if (!relocation && (msr_hv || cpu->vhyp)) { - /* In real mode top 4 effective addr bits (mostly) ignored */ - raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - - /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { - if (!(eaddr >> 63)) { - raddr |= env->spr[SPR_HRMOR]; - } - } - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; - } - - /* - * Check UPRT (we avoid the check in real mode to deal with - * transitional states during kexec. - */ - if (!ppc64_use_proc_tbl(cpu)) { - qemu_log_mask(LOG_GUEST_ERROR, - "LPCR:UPRT not set in radix mode ! LPCR=" - TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); - } - /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ - if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr, + if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, true)) { return 1; } @@ -608,18 +606,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) { - CPUPPCState *env = &cpu->env; int psize, prot; hwaddr raddr; - /* Handle Real Mode */ - if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) { - /* In real mode top 4 effective addr bits (mostly) ignored */ - return eaddr & 0x0FFFFFFFFFFFFFFFULL; - } - - if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize, - &prot, false)) { + if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } From patchwork Tue May 18 20:11:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441242 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp587678jac; Tue, 18 May 2021 13:28:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyzcahj9BZUju0cRwX+My3tkWpI0pX7a05dglXOhybY9rqckd2M9O3uDO6WaEYW5Aw4kqtw X-Received: by 2002:a6b:4f07:: with SMTP id d7mr5810488iob.160.1621369723337; Tue, 18 May 2021 13:28:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369723; cv=none; d=google.com; s=arc-20160816; b=H2D9DvyXmdUQhqzTwg/NzuaMbv1ppmUqdtj6Q5dTY9Ll0FvKYFkqwDAgD5U9rHF+QG qvBgoJX8x2kQaS51J3wKV2rKqt32F15CuNsWi1tn2Bj2UCyyg6Gv1k3bXJxuipP1KIqo tz3K3rgvGdwP2+dsYWvZTLaL9fn5+2d4mYexz9zK9GMGXuSI/1ffRRC23iP0cBbj5h6S P+K0tatBal6+TWvmEoligU8QoB16ZlhVdxCSlJjBlfqhYYXU9+CCQqs2/DWe7IretrPM XH1bUKZReo6IP2CLorqcE0nuPmNh5MJnu1Z3dDGmxeti6nu/CmbHdHubCYLK59ayXWzD KPDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ga6+PvszREjIhxPzZ4wKB8ru0YkaJYB0oJlgtxa3ZkM=; b=hiGnoteTecIV6Ozl7SC6CCoNMdHnrJxO1V6ehwNsJ/OBQiCfOVUI84zfIZqm2gRNfU WMtlNA3JzM4rYKtrHycr/eBn16judnB16pILcqg5tKtVjGMdoyFx3DfNLgT/fF6DNDGf XQI2rOPkEG9/m+8Lw1vy4G/8metYGfy+nHkIOnn3EhmuMRpI2NcZxE1byVMj/6AsMSmd o5wZ5nriE7IKnTJ+q1irZNiNOZpYmSpfbxjGbONC797pp3EMKjcMUdkCU8fwkHlF4ICN aE4Qg5QXfpbwdOEPfj2/b9xjQudljIJ98KOa6bbaF2se+o8f+MZrdzl3hb00Gf37HeyA gXsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FqjVjxK7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu-radix64.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 76a5cc8cdb..7af3e697b2 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -464,10 +464,10 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, * | = On | Process Scoped | Scoped | * +-------------+----------------+---------------+ */ -static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *psizep, int *protp, - bool guest_visible) +static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddr, int *psizep, int *protp, + bool guest_visible) { CPUPPCState *env = &cpu->env; uint64_t lpid, pid; @@ -493,7 +493,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, } *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; *psizep = TARGET_PAGE_BITS; - return 0; + return true; } /* @@ -511,7 +511,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, if (guest_visible) { ppc_radix64_raise_segi(cpu, access_type, eaddr); } - return 1; + return false; } /* Get Process Table */ @@ -524,13 +524,13 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, if (guest_visible) { ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); } - return 1; + return false; } if (!validate_pate(cpu, lpid, &pate)) { if (guest_visible) { ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG); } - return 1; + return false; } } @@ -550,7 +550,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, pate, &g_raddr, &prot, &psize, guest_visible); if (ret) { - return ret; + return false; } *psizep = MIN(*psizep, psize); *protp &= prot; @@ -574,7 +574,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, &prot, &psize, false, guest_visible); if (ret) { - return ret; + return false; } *psizep = MIN(*psizep, psize); *protp &= prot; @@ -583,7 +583,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, } } - return 0; + return true; } int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, @@ -594,8 +594,8 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, hwaddr raddr; /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ - if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { + if (!ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { return 1; } @@ -609,8 +609,8 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) int psize, prot; hwaddr raddr; - if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { + if (!ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } From patchwork Tue May 18 20:11:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441244 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp589461jac; 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Signed-off-by: Richard Henderson --- target/ppc/mmu-hash64.c | 125 +++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 66 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 877a01a296..3024dd1e8c 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -866,8 +866,10 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) return -1; } -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -911,9 +913,11 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, slb = &vrma_slbe; if (build_vrma_slbe(cpu, slb) != 0) { /* Invalid VRMA setup, machine check */ - cs->exception_index = POWERPC_EXCP_MCHECK; - env->error_code = 0; - return 1; + if (guest_visible) { + cs->exception_index = POWERPC_EXCP_MCHECK; + env->error_code = 0; + } + return false; } goto skip_slb_search; @@ -922,6 +926,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, /* Emulated old-style RMO mode, bounds check against RMLS */ if (raddr >= limit) { + if (!guest_visible) { + return false; + } switch (access_type) { case MMU_INST_FETCH: ppc_hash64_set_isi(cs, SRR1_PROTFAULT); @@ -936,15 +943,16 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, default: g_assert_not_reached(); } - return 1; + return false; } raddr |= env->spr[SPR_RMOR]; } - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + + *raddrp = raddr; + *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *psizep = TARGET_PAGE_BITS; + return true; } /* 2. Translation is on, so look up the SLB */ @@ -957,6 +965,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, exit(1); } /* Segment still not found, generate the appropriate interrupt */ + if (!guest_visible) { + return false; + } switch (access_type) { case MMU_INST_FETCH: cs->exception_index = POWERPC_EXCP_ISEG; @@ -971,20 +982,25 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, default: g_assert_not_reached(); } - return 1; + return false; } -skip_slb_search: + skip_slb_search: /* 3. Check for segment level no-execute violation */ if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) { - ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); - return 1; + if (guest_visible) { + ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); + } + return false; } /* 4. Locate the PTE in the hash table */ ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); if (ptex == -1) { + if (!guest_visible) { + return false; + } switch (access_type) { case MMU_INST_FETCH: ppc_hash64_set_isi(cs, SRR1_NOPTE); @@ -998,7 +1014,7 @@ skip_slb_search: default: g_assert_not_reached(); } - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "found PTE at index %08" HWADDR_PRIx "\n", ptex); @@ -1014,6 +1030,9 @@ skip_slb_search: if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); + if (!guest_visible) { + return false; + } if (access_type == MMU_INST_FETCH) { int srr1 = 0; if (PAGE_EXEC & ~exec_prot) { @@ -1038,7 +1057,7 @@ skip_slb_search: } ppc_hash64_set_dsi(cs, eaddr, dsisr); } - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -1062,66 +1081,40 @@ skip_slb_search: /* 7. Determine the real address from the PTE */ - raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); + *raddrp = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); + *protp = prot; + *psizep = apshift; + return true; +} + +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) +{ + CPUState *cs = CPU(cpu); + int page_size, prot; + hwaddr raddr; + + if (!ppc_hash64_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { + return 1; + } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1ULL << apshift); - + prot, mmu_idx, 1UL << page_size); return 0; } -hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) +hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) { - CPUPPCState *env = &cpu->env; - ppc_slb_t vrma_slbe; - ppc_slb_t *slb; - hwaddr ptex, raddr; - ppc_hash_pte64_t pte; - unsigned apshift; + int psize, prot; + hwaddr raddr; - /* Handle real mode */ - if (msr_dr == 0) { - /* In real mode the top 4 effective address bits are ignored */ - raddr = addr & 0x0FFFFFFFFFFFFFFFULL; - - if (cpu->vhyp) { - /* - * In virtual hypervisor mode, there's nothing to do: - * EA == GPA == qemu guest address - */ - return raddr; - } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { - /* In HV mode, add HRMOR if top EA bit is clear */ - return raddr | env->spr[SPR_HRMOR]; - } else if (ppc_hash64_use_vrma(env)) { - /* Emulated VRMA mode */ - slb = &vrma_slbe; - if (build_vrma_slbe(cpu, slb) != 0) { - return -1; - } - } else { - target_ulong limit = rmls_limit(cpu); - - /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >= limit) { - return -1; - } - return raddr | env->spr[SPR_RMOR]; - } - } else { - slb = slb_lookup(cpu, addr); - if (!slb) { - return -1; - } - } - - ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); - if (ptex == -1) { + if (!ppc_hash64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } - return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) - & TARGET_PAGE_MASK; + return raddr & TARGET_PAGE_MASK; } void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, From patchwork Tue May 18 20:11:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441243 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp587741jac; Tue, 18 May 2021 13:28:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjGlEXFziTHpkcKNCoynj3kcOvxIfoKJ4YCnCkPFGhwiU2twCAOJoq88ASx4H6/3/n54c1 X-Received: by 2002:a05:6e02:118b:: with SMTP id y11mr6701476ili.241.1621369732369; Tue, 18 May 2021 13:28:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369732; cv=none; d=google.com; s=arc-20160816; b=izgAPcpo1xe+MxoWBClK/IRIghNectlidhSbiUyNesGomRi75sPskWUJJHh7wu2uRM h3H3nYx9efaa5iL3aiTda6B2bx0I+jmoZ5mApe7Xz8+IcitLii3Cqxvu0WTRSpU05HfT 6scUmXvDGUsNQu2txanZitC80hEv6+4tCbFlMJSOCbh2lIr8UXl6EAVwBwYkcDnQqwd3 3Hebw5aH2kOnNtL16UXZ5ljGVhDiT6LUg9R0J3TBbqIEBnjEA/UidZq2HbX6NiQMCY84 hHgxXaPJxx7Xcak4wjhW+bhb7sYDyNY2WqI5E0PkKr0SPa78JzWaAix9CARbstKWf84f CjzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dI0TcqqVur7KeZZ864aPqiTFlL/jbhkC3bypNwh4QZk=; b=lFfPtDZnZQRX/1iSElwuK/+O2NpbKXW3mzHnm5MH2xjzSGKUaeUzKHOWiznRrtKhc3 t3XNt3a4rTaa4csyNANnRj7+gmCMdthfttk7ktepUnG9oMjaqYKrbqklL2y74qZuVU0I Ag5O9KT/vPO+pbtIV/xGa6ivmrx4TCpi0kRZ38b2vWpoK/peD+QAB+RILkJ20Wr5WNBF nYYxyqJGAlO1uFngBXJOPZehEaL6fUK/KRZUYE6oUdmKRmMe6x7KmKsIDhQJUyncJQvy iFyeM9treCGbSplyx/8gyuTJsB2DhegwSX9Hh+QHPRBUGR+4IQk+PZYrB4xMl+j6MI+K s/dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="cQUg/zee"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu-hash32.c | 224 ++++++++++++++++++++-------------------- 1 file changed, 113 insertions(+), 111 deletions(-) -- 2.25.1 Acked-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index d51be59f95..959dc2ab53 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -219,10 +219,11 @@ static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, return -1; } -static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, - target_ulong eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *prot) +static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, + target_ulong eaddr, + MMUAccessType access_type, + hwaddr *raddr, int *prot, + bool guest_visible) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -239,17 +240,23 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, */ *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return 0; + return true; } if (access_type == MMU_INST_FETCH) { /* No code fetch is allowed in direct-store areas */ - cs->exception_index = POWERPC_EXCP_ISI; - env->error_code = 0x10000000; - return 1; + if (guest_visible) { + cs->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x10000000; + } + return false; } - switch (env->access_type) { + /* + * From ppc_cpu_get_phys_page_debug, env->access_type is not set. + * Assume ACCESS_INT for that case. + */ + switch (guest_visible ? env->access_type : ACCESS_INT) { case ACCESS_INT: /* Integer load/store : only access allowed */ break; @@ -258,7 +265,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = eaddr; - return 1; + return false; case ACCESS_RES: /* lwarx, ldarx or srwcx. */ env->error_code = 0; @@ -268,7 +275,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, } else { env->spr[SPR_DSISR] = 0x04000000; } - return 1; + return false; case ACCESS_CACHE: /* * dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi @@ -277,7 +284,7 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, * no-op, it's quite easy :-) */ *raddr = eaddr; - return 0; + return true; case ACCESS_EXT: /* eciwx or ecowx */ cs->exception_index = POWERPC_EXCP_DSI; @@ -288,16 +295,18 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, } else { env->spr[SPR_DSISR] = 0x04100000; } - return 1; + return false; default: - cpu_abort(cs, "ERROR: instruction should not need " - "address translation\n"); + cpu_abort(cs, "ERROR: insn should not need address translation\n"); } - if ((access_type == MMU_DATA_STORE || key != 1) && - (access_type == MMU_DATA_LOAD || key != 0)) { + + *prot = key ? PAGE_READ | PAGE_WRITE : PAGE_READ; + if (*prot & prot_for_access_type(access_type)) { *raddr = eaddr; - return 0; - } else { + return true; + } + + if (guest_visible) { cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; @@ -306,8 +315,8 @@ static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, } else { env->spr[SPR_DSISR] = 0x08000000; } - return 1; } + return false; } hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash) @@ -416,8 +425,10 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -428,43 +439,43 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int need_prot; hwaddr raddr; - need_prot = prot_for_access_type(access_type); + /* There are no hash32 large pages. */ + *psizep = TARGET_PAGE_BITS; /* 1. Handle real mode accesses */ if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) { /* Translation is off */ - raddr = eaddr; - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + *raddrp = eaddr; + *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return true; } + need_prot = prot_for_access_type(access_type); + /* 2. Check Block Address Translation entries (BATs) */ if (env->nb_BATs != 0) { - raddr = ppc_hash32_bat_lookup(cpu, eaddr, access_type, &prot); + raddr = ppc_hash32_bat_lookup(cpu, eaddr, access_type, protp); if (raddr != -1) { - if (need_prot & ~prot) { - if (access_type == MMU_INST_FETCH) { - cs->exception_index = POWERPC_EXCP_ISI; - env->error_code = 0x08000000; - } else { - cs->exception_index = POWERPC_EXCP_DSI; - env->error_code = 0; - env->spr[SPR_DAR] = eaddr; - if (access_type == MMU_DATA_STORE) { - env->spr[SPR_DSISR] = 0x0a000000; + if (need_prot & ~*protp) { + if (guest_visible) { + if (access_type == MMU_INST_FETCH) { + cs->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x08000000; } else { - env->spr[SPR_DSISR] = 0x08000000; + cs->exception_index = POWERPC_EXCP_DSI; + env->error_code = 0; + env->spr[SPR_DAR] = eaddr; + if (access_type == MMU_DATA_STORE) { + env->spr[SPR_DSISR] = 0x0a000000; + } else { + env->spr[SPR_DSISR] = 0x08000000; + } } } - return 1; + return false; } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, - raddr & TARGET_PAGE_MASK, prot, mmu_idx, - TARGET_PAGE_SIZE); - return 0; + *raddrp = raddr; + return true; } } @@ -473,42 +484,38 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, /* 4. Handle direct store segments */ if (sr & SR32_T) { - if (ppc_hash32_direct_store(cpu, sr, eaddr, access_type, - &raddr, &prot) == 0) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, - raddr & TARGET_PAGE_MASK, prot, mmu_idx, - TARGET_PAGE_SIZE); - return 0; - } else { - return 1; - } + return ppc_hash32_direct_store(cpu, sr, eaddr, access_type, + raddrp, protp, guest_visible); } /* 5. Check for segment level no-execute violation */ if (access_type == MMU_INST_FETCH && (sr & SR32_NX)) { - cs->exception_index = POWERPC_EXCP_ISI; - env->error_code = 0x10000000; - return 1; + if (guest_visible) { + cs->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x10000000; + } + return false; } /* 6. Locate the PTE in the hash table */ pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); if (pte_offset == -1) { - if (access_type == MMU_INST_FETCH) { - cs->exception_index = POWERPC_EXCP_ISI; - env->error_code = 0x40000000; - } else { - cs->exception_index = POWERPC_EXCP_DSI; - env->error_code = 0; - env->spr[SPR_DAR] = eaddr; - if (access_type == MMU_DATA_STORE) { - env->spr[SPR_DSISR] = 0x42000000; + if (guest_visible) { + if (access_type == MMU_INST_FETCH) { + cs->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x40000000; } else { - env->spr[SPR_DSISR] = 0x40000000; + cs->exception_index = POWERPC_EXCP_DSI; + env->error_code = 0; + env->spr[SPR_DAR] = eaddr; + if (access_type == MMU_DATA_STORE) { + env->spr[SPR_DSISR] = 0x42000000; + } else { + env->spr[SPR_DSISR] = 0x40000000; + } } } - - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); @@ -520,20 +527,22 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); - if (access_type == MMU_INST_FETCH) { - cs->exception_index = POWERPC_EXCP_ISI; - env->error_code = 0x08000000; - } else { - cs->exception_index = POWERPC_EXCP_DSI; - env->error_code = 0; - env->spr[SPR_DAR] = eaddr; - if (access_type == MMU_DATA_STORE) { - env->spr[SPR_DSISR] = 0x0a000000; + if (guest_visible) { + if (access_type == MMU_INST_FETCH) { + cs->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x08000000; } else { - env->spr[SPR_DSISR] = 0x08000000; + cs->exception_index = POWERPC_EXCP_DSI; + env->error_code = 0; + env->spr[SPR_DAR] = eaddr; + if (access_type == MMU_DATA_STORE) { + env->spr[SPR_DSISR] = 0x0a000000; + } else { + env->spr[SPR_DSISR] = 0x08000000; + } } } - return 1; + return false; } qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); @@ -557,45 +566,38 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, /* 9. Determine the real address from the PTE */ - raddr = ppc_hash32_pte_raddr(sr, pte, eaddr); + *raddrp = ppc_hash32_pte_raddr(sr, pte, eaddr); + *protp = prot; + return true; +} + +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) +{ + CPUState *cs = CPU(cpu); + int page_size, prot; + hwaddr raddr; + + /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ + if (!ppc_hash32_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, true)) { + return 1; + } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - + prot, mmu_idx, 1UL << page_size); return 0; } hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) { - CPUPPCState *env = &cpu->env; - target_ulong sr; - hwaddr pte_offset; - ppc_hash_pte32_t pte; - int prot; + int psize, prot; + hwaddr raddr; - if (msr_dr == 0) { - /* Translation is off */ - return eaddr; - } - - if (env->nb_BATs != 0) { - hwaddr raddr = ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot); - if (raddr != -1) { - return raddr; - } - } - - sr = env->sr[eaddr >> 28]; - - if (sr & SR32_T) { - /* FIXME: Add suitable debug support for Direct Store segments */ + if (!ppc_hash32_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, + &psize, &prot, false)) { return -1; } - pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); - if (pte_offset == -1) { - return -1; - } - - return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK; + return raddr & TARGET_PAGE_MASK; } From patchwork Tue May 18 20:11:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441245 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp590441jac; Tue, 18 May 2021 13:32:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7ze8lyUxgmm2rVqEr8XGLvPUkSihAdpgiu4Xr9oNQ+xP2h1ONpItn1I/7InH1R2uBFsYl X-Received: by 2002:a05:6602:1584:: with SMTP id e4mr5866524iow.4.1621369939108; Tue, 18 May 2021 13:32:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621369939; cv=none; d=google.com; s=arc-20160816; b=o64qzlfXFbCPTp/3yjnM/mO6lohwCKG7pnnTQ3MbHqJpOh7BwWw4gbirwO3L0Ge4ls HPTSL7pcAfQmMsvP+z/ISjcfQXFaq6E5utb8eMZtOkOqzcyXONSRO/l8/4GJa1KOPN6Y uaxo+2xC3ZNEM10EojuGreVBEic7Ryj8qrhmBuCGAmHOVPtPTDTCsLwvFJTrQD4Z/wQn cV2wSsez4PPyAbsc/dbjVw9ume9F2nIY2Id0TYkIBKWpB5enpjrA/XOXX83iHqR49M0U Am2CBY5VjcZQhtIFMEN0NwS8p+g7IhgzQecTOtklptvADVcqP3T8svKym8G6DR/VwdL+ v1+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XxfpRJ55P2u9EsKXLcMRIGneufI4Rcjd8SfZDbT199k=; b=F4xq6unhu2aE+1T5xv2S8S7uWva/y30itEap4hVMtYBEE/Me6fQGHnG/YjMvGc8FlI 0Dpy23q9eVZeBffiQClS+LFbzPh31cEpSItTa8ReXMhAmMC4w1AaWyLEgV1sMGrWw/jT oqTTf0Z0g1a8bQul4nbZ5qVv0v5T8VwNSQlCDPtfFpQ6pw6hg50cWjWcwFrdU+RLqNxP pV/XU/8q3sSRDLNRNwNKN/NRYqve5fEXyhUZiN40+7ZY52PlS8Fe3bCwmozANWOWQUTU cjRsts/xqGCUb4JFLmZZcc9AEIkfDXEPJvhykUIMnJ4CnW/JPn1WlkqfBhZ2Ze9oeZii 60oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=r0uqFJBP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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For booke, we need to add mmu_idx to the xlate-style interface. Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 181 +++++++++++++++++++++------------------- 1 file changed, 97 insertions(+), 84 deletions(-) -- 2.25.1 Acked-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 863e556a22..68c2e59238 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1427,48 +1427,6 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, return get_physical_address_wtlb(env, ctx, eaddr, access_type, type, 0); } -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - mmu_ctx_t ctx; - - switch (env->mmu_model) { -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_07: - return ppc_hash64_get_phys_page_debug(cpu, addr); - case POWERPC_MMU_3_00: - return ppc64_v3_get_phys_page_debug(cpu, addr); -#endif - - case POWERPC_MMU_32B: - case POWERPC_MMU_601: - return ppc_hash32_get_phys_page_debug(cpu, addr); - - default: - ; - } - - if (unlikely(get_physical_address(env, &ctx, addr, MMU_DATA_LOAD, - ACCESS_INT) != 0)) { - - /* - * Some MMUs have separate TLBs for code and data. If we only - * try an ACCESS_INT, we may not be able to read instructions - * mapped by code TLBs, so we also try a ACCESS_CODE. - */ - if (unlikely(get_physical_address(env, &ctx, addr, MMU_INST_FETCH, - ACCESS_CODE) != 0)) { - return -1; - } - } - - return ctx.raddr & TARGET_PAGE_MASK; -} - static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, MMUAccessType access_type, int mmu_idx) { @@ -1524,30 +1482,38 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, } /* Perform address translation */ -static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, - MMUAccessType access_type, int mmu_idx) +/* TODO: Split this by mmu_model. */ +static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + int mmu_idx, bool guest_visible) { - CPUState *cs = env_cpu(env); - PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; mmu_ctx_t ctx; int type; - int ret = 0; + int ret; if (access_type == MMU_INST_FETCH) { /* code access */ type = ACCESS_CODE; - } else { + } else if (guest_visible) { /* data access */ type = env->access_type; + } else { + type = ACCESS_INT; } - ret = get_physical_address_wtlb(env, &ctx, address, access_type, + + ret = get_physical_address_wtlb(env, &ctx, eaddr, access_type, type, mmu_idx); if (ret == 0) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - ctx.raddr & TARGET_PAGE_MASK, ctx.prot, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) { + *raddrp = ctx.raddr; + *protp = ctx.prot; + *psizep = TARGET_PAGE_BITS; + return true; + } + + if (guest_visible) { LOG_MMU_STATE(cs); if (type == ACCESS_CODE) { switch (ret) { @@ -1557,7 +1523,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, case POWERPC_MMU_SOFT_6xx: cs->exception_index = POWERPC_EXCP_IFTLB; env->error_code = 1 << 18; - env->spr[SPR_IMISS] = address; + env->spr[SPR_IMISS] = eaddr; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_74xx: @@ -1567,29 +1533,25 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; - env->spr[SPR_40x_DEAR] = address; + env->spr[SPR_40x_DEAR] = eaddr; env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, address, 2, mmu_idx); + booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx); /* fall through */ case POWERPC_MMU_BOOKE: cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; - env->spr[SPR_BOOKE_DEAR] = address; + env->spr[SPR_BOOKE_DEAR] = eaddr; env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, MMU_DATA_LOAD); - return -1; - case POWERPC_MMU_MPC8xx: - /* XXX: TODO */ - cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; + case POWERPC_MMU_MPC8xx: + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); - return -1; default: cpu_abort(cs, "Unknown or invalid MMU model\n"); - return -1; } break; case -2: @@ -1626,7 +1588,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cs->exception_index = POWERPC_EXCP_DLTLB; env->error_code = 0; } - env->spr[SPR_DMISS] = address; + env->spr[SPR_DMISS] = eaddr; env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; tlb_miss: env->error_code |= ctx.key << 19; @@ -1644,7 +1606,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, tlb_miss_74xx: /* Implement LRU algorithm */ env->error_code = ctx.key << 19; - env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) | + env->spr[SPR_TLBMISS] = (eaddr & ~((target_ulong)0x3)) | ((env->last_way + 1) & (env->nb_ways - 1)); env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; break; @@ -1652,7 +1614,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; - env->spr[SPR_40x_DEAR] = address; + env->spr[SPR_40x_DEAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_40x_ESR] = 0x00800000; } else { @@ -1662,23 +1624,20 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, case POWERPC_MMU_MPC8xx: /* XXX: TODO */ cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); - break; case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, address, access_type, mmu_idx); + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx); /* fall through */ case POWERPC_MMU_BOOKE: cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; - env->spr[SPR_BOOKE_DEAR] = address; + env->spr[SPR_BOOKE_DEAR] = eaddr; env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type); - return -1; + break; case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); - return -1; default: cpu_abort(cs, "Unknown or invalid MMU model\n"); - return -1; } break; case -2: @@ -1687,16 +1646,16 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, env->error_code = 0; if (env->mmu_model == POWERPC_MMU_SOFT_4xx || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { - env->spr[SPR_40x_DEAR] = address; + env->spr[SPR_40x_DEAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_40x_ESR] |= 0x00800000; } } else if ((env->mmu_model == POWERPC_MMU_BOOKE) || (env->mmu_model == POWERPC_MMU_BOOKE206)) { - env->spr[SPR_BOOKE_DEAR] = address; + env->spr[SPR_BOOKE_DEAR] = eaddr; env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type); } else { - env->spr[SPR_DAR] = address; + env->spr[SPR_DAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x0A000000; } else { @@ -1711,13 +1670,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, /* Floating point load/store */ cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; - env->spr[SPR_DAR] = address; + env->spr[SPR_DAR] = eaddr; break; case ACCESS_RES: /* lwarx, ldarx or stwcx. */ cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; - env->spr[SPR_DAR] = address; + env->spr[SPR_DAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x06000000; } else { @@ -1728,7 +1687,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, /* eciwx or ecowx */ cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; - env->spr[SPR_DAR] = address; + env->spr[SPR_DAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_DSISR] = 0x06100000; } else { @@ -1740,16 +1699,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; - env->spr[SPR_DAR] = address; + env->spr[SPR_DAR] = eaddr; break; } break; } } - ret = 1; } - - return ret; + return false; } /*****************************************************************************/ @@ -2958,6 +2915,62 @@ void helper_check_tlb_flush_global(CPUPPCState *env) /*****************************************************************************/ +static int cpu_ppc_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, int mmu_idx) +{ + CPUState *cs = CPU(cpu); + int page_size, prot; + hwaddr raddr; + + if (!ppc_jumbo_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, mmu_idx, true)) { + return 1; + } + + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + prot, mmu_idx, 1UL << page_size); + return 0; +} + +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + hwaddr raddr; + int s, p; + + switch (env->mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: + return ppc_hash64_get_phys_page_debug(cpu, addr); + case POWERPC_MMU_3_00: + return ppc64_v3_get_phys_page_debug(cpu, addr); +#endif + + case POWERPC_MMU_32B: + case POWERPC_MMU_601: + return ppc_hash32_get_phys_page_debug(cpu, addr); + + default: + ; + } + + /* + * Some MMUs have separate TLBs for code and data. If we only + * try an MMU_DATA_LOAD, we may not be able to read instructions + * mapped by code TLBs, so we also try a MMU_INST_FETCH. + */ + if (ppc_jumbo_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false) || + ppc_jumbo_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, false)) { + return raddr & TARGET_PAGE_MASK; + } + return -1; +} + + bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -2985,7 +2998,7 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; default: - ret = cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); + ret = cpu_ppc_handle_mmu_fault(cpu, addr, access_type, mmu_idx); break; } if (unlikely(ret != 0)) { From patchwork Tue May 18 20:11:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441246 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp593248jac; Tue, 18 May 2021 13:36:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxO7Xa2W/5uCoVYJQzjhl7r2d1L0uJoeXF/MntobsLE03m0P8QgNdGVPGJMVSl47C1695yY X-Received: by 2002:a05:6602:70d:: with SMTP id f13mr6286205iox.16.1621370194377; Tue, 18 May 2021 13:36:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621370194; cv=none; d=google.com; s=arc-20160816; b=ctav64Bh9FhlrE+Al0SpjLSLoYhVXrXFgkTEen0Qm3x5cin2OomGGYpwEY7Ek+T0IB EDt581jacFv2YkxEL+pK7uFJdZJtLzy3CIVMpWa9eLa7laMY3Evd8A7UtM1l9o5ZxaOB D0RA6RGuo1Kq11YecYk0eCWF04Yc4DS1OhfwsEwlTFYLi4o/5crE+P94emHd9YvKM1uq V5z/8zs7Payd6vT9AuHj540xG46izMEfbjA8heXk9RnjUN1X+ZmJVzR63iAShUghew9v GItiR/4tNVuADo0FOw19yD1US0n+WYrko4mpsP4GvHOvpDqFww+Nn9xisfbjiwL7eH6k mYNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nVabIlHd+1O8w9MxTet9IEJq8n9egPdXmu6+V9UGjDE=; b=bdVCWk885X7hFVhvE167zOEspih4Me7SB8ZcfTyTVpqxTgW1e4/JIr7CqzmnXBz64F 9T/Fqk/Sf8XxerpUoV9gI6RoQAWfEMzV53oEDeFV8Q8snxgvTpXywC9g1jbQNnlI6Y8O lQLAGz5jP6EwobJdK7aHG7vNu47tpHiRUyBkkpS7+H18Wl3m0wsYl9XQxfHXbMAiNkGG 358x+h5U0GifftQdPa+u5OlNGo5r2IsNaxjAqt8BT0wmnbp+ObmsahGliJUTy25gCljY OWt4aCGsHt2VMUAkU0rFrUevfUYpdg1wi8X4O5d+f5oRE0yU4/3p35JvuYA1D85gFh5L mLkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aD9V1SUs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use ppc64_v3_radix to directly dispatch between ppc_radix64_xlate and ppc_hash64_xlate. Remove the separate *_handle_mmu_fault and *_get_phys_page_debug functions, using common code for ppc_cpu_tlb_fill and ppc_cpu_get_phys_page_debug. Signed-off-by: Richard Henderson --- target/ppc/mmu-book3s-v3.h | 5 -- target/ppc/mmu-hash32.h | 6 +-- target/ppc/mmu-hash64.h | 6 +-- target/ppc/mmu-radix64.h | 6 +-- target/ppc/mmu-book3s-v3.c | 19 ------- target/ppc/mmu-hash32.c | 38 ++----------- target/ppc/mmu-hash64.c | 37 ++----------- target/ppc/mmu-radix64.c | 38 ++----------- target/ppc/mmu_helper.c | 106 ++++++++++++++----------------------- 9 files changed, 58 insertions(+), 203 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h index 7b89be54b8..a1326df969 100644 --- a/target/ppc/mmu-book3s-v3.h +++ b/target/ppc/mmu-book3s-v3.h @@ -67,11 +67,6 @@ static inline bool ppc64_v3_radix(PowerPCCPU *cpu) return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR); } -hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr); - -int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx); - static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu) { uint64_t base; diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 30e35718a7..8694eccabd 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -4,9 +4,9 @@ #ifndef CONFIG_USER_ONLY hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); -hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx); +bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible); /* * Segment register definitions diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 3e8a8eec1f..9f338e1fe9 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -7,9 +7,9 @@ void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); -hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx); +bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1); diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 94bd72cb38..6b13b89b64 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -44,9 +44,9 @@ #ifdef TARGET_PPC64 -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx); -hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); +bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddr, int *psizep, int *protp, + bool guest_visible); static inline int ppc_radix64_get_prot_eaa(uint64_t pte) { diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c index c78fd8dc0e..f4985bae78 100644 --- a/target/ppc/mmu-book3s-v3.c +++ b/target/ppc/mmu-book3s-v3.c @@ -23,25 +23,6 @@ #include "mmu-book3s-v3.h" #include "mmu-radix64.h" -int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, - int mmu_idx) -{ - if (ppc64_v3_radix(cpu)) { /* Guest uses radix */ - return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); - } else { /* Guest uses hash */ - return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); - } -} - -hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr) -{ - if (ppc64_v3_radix(cpu)) { - return ppc_radix64_get_phys_page_debug(cpu, eaddr); - } else { - return ppc_hash64_get_phys_page_debug(cpu, eaddr); - } -} - bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) { uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB; diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 959dc2ab53..32d1f4a954 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -425,10 +425,9 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } -static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, - bool guest_visible) +bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -570,34 +569,3 @@ static bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, *protp = prot; return true; } - -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) -{ - CPUState *cs = CPU(cpu); - int page_size, prot; - hwaddr raddr; - - /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ - if (!ppc_hash32_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) -{ - int psize, prot; - hwaddr raddr; - - if (!ppc_hash32_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { - return -1; - } - - return raddr & TARGET_PAGE_MASK; -} diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 3024dd1e8c..ce0068590f 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -866,10 +866,9 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) return -1; } -static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddrp, int *psizep, int *protp, - bool guest_visible) +bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + bool guest_visible) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -1087,36 +1086,6 @@ static bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, return true; } -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) -{ - CPUState *cs = CPU(cpu); - int page_size, prot; - hwaddr raddr; - - if (!ppc_hash64_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) -{ - int psize, prot; - hwaddr raddr; - - if (!ppc_hash64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { - return -1; - } - - return raddr & TARGET_PAGE_MASK; -} - void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, target_ulong pte0, target_ulong pte1) { diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 7af3e697b2..eabfe4e261 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -464,10 +464,9 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, * | = On | Process Scoped | Scoped | * +-------------+----------------+---------------+ */ -static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, - hwaddr *raddr, int *psizep, int *protp, - bool guest_visible) +bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddr, int *psizep, int *protp, + bool guest_visible) { CPUPPCState *env = &cpu->env; uint64_t lpid, pid; @@ -585,34 +584,3 @@ static bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, return true; } - -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) -{ - CPUState *cs = CPU(cpu); - int page_size, prot; - hwaddr raddr; - - /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */ - if (!ppc_radix64_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, true)) { - return 1; - } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; -} - -hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr) -{ - int psize, prot; - hwaddr raddr; - - if (!ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr, - &psize, &prot, false)) { - return -1; - } - - return raddr & TARGET_PAGE_MASK; -} diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 68c2e59238..2535ea1836 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2915,98 +2915,72 @@ void helper_check_tlb_flush_global(CPUPPCState *env) /*****************************************************************************/ -static int cpu_ppc_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, - MMUAccessType access_type, int mmu_idx) +static bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + int mmu_idx, bool guest_visible) { - CPUState *cs = CPU(cpu); - int page_size, prot; - hwaddr raddr; + switch (cpu->env.mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_3_00: + if (ppc64_v3_radix(cpu)) { + return ppc_radix64_xlate(cpu, eaddr, access_type, + raddrp, psizep, protp, guest_visible); + } + /* fall through */ + case POWERPC_MMU_64B: + case POWERPC_MMU_2_03: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_07: + return ppc_hash64_xlate(cpu, eaddr, access_type, + raddrp, psizep, protp, guest_visible); +#endif - if (!ppc_jumbo_xlate(cpu, eaddr, access_type, &raddr, - &page_size, &prot, mmu_idx, true)) { - return 1; + case POWERPC_MMU_32B: + case POWERPC_MMU_601: + return ppc_hash32_xlate(cpu, eaddr, access_type, + raddrp, psizep, protp, guest_visible); + + default: + return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp, + psizep, protp, mmu_idx, guest_visible); } - - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, - prot, mmu_idx, 1UL << page_size); - return 0; } hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; hwaddr raddr; int s, p; - switch (env->mmu_model) { -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_07: - return ppc_hash64_get_phys_page_debug(cpu, addr); - case POWERPC_MMU_3_00: - return ppc64_v3_get_phys_page_debug(cpu, addr); -#endif - - case POWERPC_MMU_32B: - case POWERPC_MMU_601: - return ppc_hash32_get_phys_page_debug(cpu, addr); - - default: - ; - } - /* * Some MMUs have separate TLBs for code and data. If we only * try an MMU_DATA_LOAD, we may not be able to read instructions * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ - if (ppc_jumbo_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false) || - ppc_jumbo_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, false)) { + if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, 0, false) || + ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, 0, false)) { return raddr & TARGET_PAGE_MASK; } return -1; } - -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - int ret; + hwaddr raddr; + int page_size, prot; - switch (env->mmu_model) { -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_07: - ret = ppc_hash64_handle_mmu_fault(cpu, addr, access_type, mmu_idx); - break; - case POWERPC_MMU_3_00: - ret = ppc64_v3_handle_mmu_fault(cpu, addr, access_type, mmu_idx); - break; -#endif - - case POWERPC_MMU_32B: - case POWERPC_MMU_601: - ret = ppc_hash32_handle_mmu_fault(cpu, addr, access_type, mmu_idx); - break; - - default: - ret = cpu_ppc_handle_mmu_fault(cpu, addr, access_type, mmu_idx); - break; + if (ppc_xlate(cpu, eaddr, access_type, &raddr, + &page_size, &prot, mmu_idx, !probe)) { + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, + prot, mmu_idx, 1UL << page_size); + return true; } - if (unlikely(ret != 0)) { - if (probe) { - return false; - } - raise_exception_err_ra(env, cs->exception_index, env->error_code, - retaddr); + if (probe) { + return false; } - return true; + raise_exception_err_ra(&cpu->env, cs->exception_index, + cpu->env.error_code, retaddr); } From patchwork Tue May 18 20:11:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 441247 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp593436jac; Tue, 18 May 2021 13:36:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyy9gW07rnhQCt4300TuoM8KAbwzM2iEjRunZER0K3e0ImS7N8rI4CQyMv6ob6B2ksDqKq0 X-Received: by 2002:a6b:8dd5:: with SMTP id p204mr5886682iod.195.1621370213173; Tue, 18 May 2021 13:36:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621370213; cv=none; d=google.com; s=arc-20160816; b=TB5dnvdq4ZY3myiVA7sLjOuckCp7KPjjZ2QUdScQhIlk/ScSeU8Gc2jCHiVPAdcqvK Dh6/90Y00HzqjF0RG7ohSQa+oAP5iru7q45O5KoO+NbNYUbSnjz39m2sh5srXKLcJFaE GOWMOgjjrnzUfIo/Ii4VNresG8qS7XOfO3vPGqwDkq258c7TMd5Xxqn7nXFdjKSG9/i0 wCHSILtAEey6Ro4SMG+YqynT5/pLEQcEbbM7e4ORc9imergJeKMQmW7cAzQ+ILIk87A0 v+2Iw7YGuM+TJD/IGzOqQgat1TnqVi1jfwKa4boAsE8ES/EU7nMcwxOVDNBTa9D5tcz+ Lupg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=erERm2mmVaEtH9AdU8K/vbETws9BWMudx/m/0BInVk4=; b=nR4Nnbmf/0bpArE81s4d23H2dtepAhpCJed/kuZZZ//tFRLYXKyVzQlNb7H/mtmAgG Msu12RRp/nQ2A9iNXAzAtlDnXmHuAn4ooGPTd0VqJYRtEbwL8i4WrkOYMMUaZAbSMLcF fee9NXsG3gGWC6clsTz3KaQmW6BtbU0O79dtA3xAgkV6cxqBTDqAmTPxycl+CCGMEFR7 V9Oz/dIdVKvWti+ZArzAaKo0AScI9u4Alc+bwuZ5xMkgQDNE0KeIMH4mR28oFHOR5i+z GV+XMaZnOOea48dUXLNjUR1T6uc7zdNB6a3V2yap0KZ3QXCt5iue1pKtcwMpAPB+JbnV lZ7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=z2rVvZiw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/mmu_helper.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2535ea1836..78e6f7496b 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2964,6 +2964,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return -1; } +#ifdef CONFIG_TCG bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -2984,3 +2985,4 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, raise_exception_err_ra(&cpu->env, cs->exception_index, cpu->env.error_code, retaddr); } +#endif