From patchwork Sun May 16 16:30:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 439958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6149AC43462 for ; Sun, 16 May 2021 16:31:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4529461177 for ; Sun, 16 May 2021 16:31:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231792AbhEPQcS (ORCPT ); Sun, 16 May 2021 12:32:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231336AbhEPQcR (ORCPT ); Sun, 16 May 2021 12:32:17 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D422C06174A; Sun, 16 May 2021 09:31:01 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id e11so4306410ljn.13; Sun, 16 May 2021 09:31:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ofiUnTNVmdhSCPXFUakdrcB5fFxVu8qvsddsoETV6Zo=; b=LozPzTKaSETaV2rdnkYpWYgMnAkusxmk1ax5YqRdzSOsgQJ+xAAZlte+WqlE0dm8Go YtTQBlxKCUMMfVDNMV76ozKpL8+UH2vVzmuV/Hfkdhc+XQsj/2i3gWWaj2imGfR4tEqs aR2XlScJGnHUMGg/ygd7g5ehiWtwsARAr5rMZxgTKqZ7QnAbbQoXGBi5M+vBPU0Smv+Y nloN3c1o49odom4dX8FKZRjsSuQ5pmJz5LjtVoqyXr9NLMT8Y86IQITY0A6Ett7BEyfH nkbXSZJgpX6kybSrcEYPAfLIUFRiMQcJGTYkPf8R3XZ8MX9xVRz7zFoZOBO2EnU4To4q PvQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ofiUnTNVmdhSCPXFUakdrcB5fFxVu8qvsddsoETV6Zo=; b=lZW3E+fgCXCqLbdqrLHJsxyEosemoAl914Fv/fwOUfxg+j5TvLGJ201/ecvYE3cImP 33oZZ+mLZXJVXyUIWsxshiFMlUE6m7DgdbNfYlc4os0LvJH9c0eKMXUeSZDIEAsazWVO e1O7s1doy+IOeMGTTHx8glm5LILZcvYe3ebr0edzq0LYx6JXDTAiHFevtBoVvdNRrsLj SCMGQV62uSb7OmS3k48G6avhS/t2mmB+ZxNM8psh5phI1nWP5knOcHghORzpPak6PfQZ cfsUqYH30JTWDPEIKeVz8JEfNPRZztQUkxlD0TkueRyxs607n13ABYDokEtPKor/lkr9 57LA== X-Gm-Message-State: AOAM531FBr/NORV1HulxFwUnPvw63wuslIEVF0pZZGmSmCZlmng5eCQT IhljPMkjhGxbaIOF/F7iLpRG67vMeKM= X-Google-Smtp-Source: ABdhPJyMul4ZGWFZ3EMqr31xb6H/CbK3Paw79JP+gLyln/HdhZB0ZyHai3g5/AqgYITT3GG+Ytw+Xw== X-Received: by 2002:a2e:b892:: with SMTP id r18mr3324743ljp.402.1621182659952; Sun, 16 May 2021 09:30:59 -0700 (PDT) Received: from localhost.localdomain (109-252-193-91.dynamic.spd-mgts.ru. [109.252.193.91]) by smtp.gmail.com with ESMTPSA id m2sm1704548lfo.23.2021.05.16.09.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 09:30:59 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 1/9] clk: tegra30: Use 300MHz for video decoder by default Date: Sun, 16 May 2021 19:30:33 +0300 Message-Id: <20210516163041.12818-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210516163041.12818-1-digetx@gmail.com> References: <20210516163041.12818-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions. Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 16dbf83d2f62..a33688b2359e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1245,7 +1245,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, From patchwork Sun May 16 16:30:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 439957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A07CCC43617 for ; Sun, 16 May 2021 16:31:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80B3061074 for ; Sun, 16 May 2021 16:31:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232273AbhEPQcU (ORCPT ); Sun, 16 May 2021 12:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231590AbhEPQcR (ORCPT ); Sun, 16 May 2021 12:32:17 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE24BC06175F; Sun, 16 May 2021 09:31:02 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id c15so4327396ljr.7; Sun, 16 May 2021 09:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=99TMTkahJ4QCgWUEiSLbnT5JfgAic6E8hP6s4tmViRw=; b=YI4TPdlKM5GeI4naXWaXkV54rqr2x5yThRcxcnFiYDQmlffwzoCdG3YRzL3wUxjrMx uXDsLXDbMasoz68QVesEoGrL6lBZTyDLfHqCjYtb5GSGt7ozw44uT7S9W0VbkK2HBxK+ ru8fEnqo8var6KabGNFwk04137aB0c9v2KY7iu5djX7TWYnGYrXkhiaFl6IRw+4Gt1vT 5ggUJlCHDoc7hqdrk16486RFd+KbjSI4ipcrxZaRDYo8gv70R/F0ZGIX10GE/xD1RF0i 9LDEIoCN3QPTsb90zXSD9sGE4gH9L0FJMMD/wrMntaIvm7PkyG07y63jODpOvdO5vP2H oy3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=99TMTkahJ4QCgWUEiSLbnT5JfgAic6E8hP6s4tmViRw=; b=Fo0hh3sQQ+jMH/qj7kCSUk5IkLKP3KiwyoGR3SsgiyGSYYlTqbUcu67AzKCdX8LAny iLEId7Y2Z6qk7S0joIWFdFyWUwBJTlPeBB87GXS3JaXAP3Hq8Mq3eLgUZUbAofyquE4u JugwVqoKrVY7n3ZgB8PhatVl5vTUTkl3UsH7EhyZYoql+qtpMIZfu0jlY4cPa3uYQeKQ bwgRDRmQJ1Aoqh0Ix6+j7U+g9XGbDC8jHSzXKKCZXFiYxcj63V61qre27ytHHKCDcd+O UNi+HnAp/GOYPT+X9vaAautyT0RXPc9HMrmFsqh3DEOKmmW06q27j3nYAe+r7KBqgmMW mSOA== X-Gm-Message-State: AOAM531aERpP3OM4YTV9ll8ls9QpbetuZ1vs8klgT4UJ0uDgKiNtcBaG EuDcBRP+NzgC0Dji3BCCeXI= X-Google-Smtp-Source: ABdhPJzRZGeZ3SQYeuSacr6aWc7bzfsbE2McV8zcCgsJbjRSw7hHlf97aRVJxHTTEoc0ng2wI5Z+ig== X-Received: by 2002:a2e:5342:: with SMTP id t2mr39064234ljd.321.1621182661367; Sun, 16 May 2021 09:31:01 -0700 (PDT) Received: from localhost.localdomain (109-252-193-91.dynamic.spd-mgts.ru. [109.252.193.91]) by smtp.gmail.com with ESMTPSA id m2sm1704548lfo.23.2021.05.16.09.31.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 09:31:01 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 3/9] clk: tegra: Ensure that PLLU configuration is applied properly Date: Sun, 16 May 2021 19:30:35 +0300 Message-Id: <20210516163041.12818-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210516163041.12818-1-digetx@gmail.com> References: <20210516163041.12818-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PLLU (USB) consists of the PLL configuration itself and configuration of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, where T114 immediately bails out if PLLU is enabled and T30 re-enables a potentially already enabled PLL (left after bootloader) and then fully reprograms it, which could be unsafe to do. The correct way should be to skip enabling of the PLL if it's already enabled and then apply configuration to the outputs. This patch doesn't fix any known problems, it's a minor improvement. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 0193cebe8c5a..823a567f2adc 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1131,7 +1131,8 @@ static int clk_pllu_enable(struct clk_hw *hw) if (pll->lock) spin_lock_irqsave(pll->lock, flags); - _clk_pll_enable(hw); + if (!clk_pll_is_enabled(hw)) + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); if (ret < 0) @@ -1748,15 +1749,13 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) return -EINVAL; } - if (clk_pll_is_enabled(hw)) - return 0; - input_rate = clk_hw_get_rate(__clk_get_hw(osc)); if (pll->lock) spin_lock_irqsave(pll->lock, flags); - _clk_pll_enable(hw); + if (!clk_pll_is_enabled(hw)) + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); if (ret < 0) From patchwork Sun May 16 16:30:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 439956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A1EDC43461 for ; Sun, 16 May 2021 16:31:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3BB66610CA for ; Sun, 16 May 2021 16:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232983AbhEPQcW (ORCPT ); Sun, 16 May 2021 12:32:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232532AbhEPQcU (ORCPT ); Sun, 16 May 2021 12:32:20 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF765C061756; Sun, 16 May 2021 09:31:04 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id w4so4321741ljw.9; Sun, 16 May 2021 09:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1RqC6a+NZMuHcUfGq6LxuBL+QnW+oPmIqETkbY0cfZw=; b=eJgFxWANPyZ28kO3ZDxEInp4DxExvrjr9xbbEv2SB481W0ndSezPksTmbZCs2B41I9 nUDbM6DBEsnerQS758pONq0HEH9pmzRFFh92o+Z3CbUY4RZI1+b+LTUgXEDZgvxk323C CSYKP33I2PMOf1/yM7tFbGuj9qQkFO0qcwngTPZkpOnYYox3530Rxvcp85LoQ8p6jTS+ S/73bvdnqZyr+4hiPvc5LzC6xvhvYJXGxm+8DG/lHdhme6UZuWen2TAiom54NC7EoRe6 3sylaIvuijxz/KrVeR7lhK7Xbrhf72KiTXX65VtSTSdvgMBzEWeo5dYwuNJiNI8DUn1/ 4nBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1RqC6a+NZMuHcUfGq6LxuBL+QnW+oPmIqETkbY0cfZw=; b=UDogRy5Z06+FquNyh1sUSEcz2H4DL6i8ax4GqcSYS/TjpKF/aCSv9VBE+xWeYG07PL RrBJw+xM+LPX0FvBevQXtWAIIwRvinEDvWWWfKLpBA30G6JIsH6QsbitJWbjOph5cf7h hMwCvyVR4YR41Eze4ymJP0x/OVFUV1SGtx9zvz3XDgjojoznh+0hA1eaBOIsKjNI+DfU nGiRVJwgD8omUjDAEa84oSGZsS0hpzLcb/Ix53X0uzyRQtdlqww3vOmI0a9R0S/bpVmm lvpyapzno9NqZ632b6Wxp5LhzMQiIZi+Rc2mcB2KCV/wgAALNB9F/UGBMisyIjukjFQ7 /IFg== X-Gm-Message-State: AOAM5327IkSwpTyVKteXK1HVJRTdMTT2SF7LNX+ZKwVb40D18kVWrSAD uQo5PT61T2vVirhoXRhvuFY= X-Google-Smtp-Source: ABdhPJzlmUMG4qGBtOldAsBml+5bry1JrKAKGxYoPq3S53eQEGzqeDwi2Xty3FISDVu5oNZjgYdMPA== X-Received: by 2002:a2e:b5b0:: with SMTP id f16mr46031988ljn.52.1621182663383; Sun, 16 May 2021 09:31:03 -0700 (PDT) Received: from localhost.localdomain (109-252-193-91.dynamic.spd-mgts.ru. [109.252.193.91]) by smtp.gmail.com with ESMTPSA id m2sm1704548lfo.23.2021.05.16.09.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 09:31:03 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 6/9] clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling Date: Sun, 16 May 2021 19:30:38 +0300 Message-Id: <20210516163041.12818-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210516163041.12818-1-digetx@gmail.com> References: <20210516163041.12818-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index a03119c30456..68d7bcd5fc8a 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,8 @@ #define SUPER_CDIV_ENB BIT(31) +#define TSENSOR_SLOWDOWN BIT(23) + static struct tegra_clk_super_mux *cclk_super; static bool cclk_on_pllx; @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + u32 val = readl_relaxed(super->reg); + unsigned int div2; + + /* check whether thermal throttling is active */ + if (val & TSENSOR_SLOWDOWN) + div2 = 1; + else + div2 = 0; + if (cclk_super_get_parent(hw) == PLLX_INDEX) - return parent_rate; + return parent_rate >> div2; - return tegra_clk_super_ops.recalc_rate(hw, parent_rate); + return tegra_clk_super_ops.recalc_rate(hw, parent_rate) >> div2; } static int cclk_super_determine_rate(struct clk_hw *hw, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index a33688b2359e..5b6bd138be84 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -930,7 +930,7 @@ static void __init tegra30_super_clk_init(void) /* CCLKG */ clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), - CLK_SET_RATE_PARENT, + CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, clk_base + CCLKG_BURST_POLICY, 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; From patchwork Sun May 16 16:30:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 439955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A761CC2B9F2 for ; Sun, 16 May 2021 16:31:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 883FA611B0 for ; Sun, 16 May 2021 16:31:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233745AbhEPQcZ (ORCPT ); Sun, 16 May 2021 12:32:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232952AbhEPQcW (ORCPT ); Sun, 16 May 2021 12:32:22 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74348C061573; Sun, 16 May 2021 09:31:05 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id w4so4321767ljw.9; Sun, 16 May 2021 09:31:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ezXWLawRH6/xu46ft4pBR8YUb7TW3xNdsazrSx37qjs=; b=BooafrtXEIJuPHyQdoTgr58j2Mpwj2Win2PfqJu51JvxHlDLliiAesGRGmH4x8wNQw QQgcqgqf/HfZTthYLXmtzhavOmlS47DL1wmJYLFfV7j2cfGC6+B+FIXlCUK8gzH6H9Xx aBV0UN7l7512qeoiouSIU4cz2B6LdTrKviaVSb0ALGLGSvVamIgP58cJGph1MWpJmdPm LkiJmsLJTFxju5NmmilV/HG58adxeu5G1PpwFmjvRga0y4FTXjcJMjMGxmWVhIhre2hR 7Chhz/S6Aqxl39NGX4VG2I8cLLelz/06wfT9FM5VcDHkKGBAt46IdVuzK65uXJQAiywV LijQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ezXWLawRH6/xu46ft4pBR8YUb7TW3xNdsazrSx37qjs=; b=rcfcsZB6YhourKelBG00nITlYHqrLpCr3fST1gxSTjo7aXLcJQGTEq6CkE0cRyXIi0 MW+eQ/uzVGagn9pBl4qdw3qi92388QNs9FAyvHAShtWN0dmL36Xgm74RfAhESoxddvCr rB8MZ0hrO6lmfz9cMoFj/2k7HS1yH4x0nsgnf0XJPOsupeDzk3rpEd06B5Jq/4Vt1EXP ePuIgC2SZuAAm14SPszFgoHHDP7FLmdsyCuNr5YUagPkXpp3HihKBfiqOldcI5OqjSa/ rT+SC5OdxIEgClZPNedQKTjPxEC6ahsQWpcAwetulp2h/IsUTOFwMCxbTo6yndMlAd1e VmWw== X-Gm-Message-State: AOAM532q8IujS7I4pZXIuXTZ2M/tC1nqw57WNvfW9EDZbXut3chn1ly4 0gGs5w7IYC9X7r30qdbVyIQ= X-Google-Smtp-Source: ABdhPJwsQphF/ZigoMRPRMYBC8WvPmWZcC12iStBiNdB7lZhOjLLUzY14ncuU91We3rOPNnc07Sx/w== X-Received: by 2002:a2e:9195:: with SMTP id f21mr45107036ljg.43.1621182664009; Sun, 16 May 2021 09:31:04 -0700 (PDT) Received: from localhost.localdomain (109-252-193-91.dynamic.spd-mgts.ru. [109.252.193.91]) by smtp.gmail.com with ESMTPSA id m2sm1704548lfo.23.2021.05.16.09.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 09:31:03 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 7/9] clk: tegra: Mark external clocks as not having reset control Date: Sun, 16 May 2021 19:30:39 +0300 Message-Id: <20210516163041.12818-8-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210516163041.12818-1-digetx@gmail.com> References: <20210516163041.12818-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The external clocks don't have reset bits as they don't belong to any specific hardware unit. Mark them as not having reset control for consistency. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-periph.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 60cc34f90cb9..292d6269daf1 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -712,9 +712,9 @@ static struct tegra_periph_init_data periph_clks[] = { MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), - MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1), - MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), - MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), + MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, TEGRA_PERIPH_NO_RESET, tegra_clk_extern1), + MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, TEGRA_PERIPH_NO_RESET, tegra_clk_extern2), + MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, TEGRA_PERIPH_NO_RESET, tegra_clk_extern3), MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8), MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), From patchwork Sun May 16 16:30:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 439954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D375C2B9F8 for ; Sun, 16 May 2021 16:31:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B51761183 for ; Sun, 16 May 2021 16:31:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233831AbhEPQc0 (ORCPT ); Sun, 16 May 2021 12:32:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233139AbhEPQcX (ORCPT ); Sun, 16 May 2021 12:32:23 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08B8DC061761; Sun, 16 May 2021 09:31:07 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id v9so3921944lfa.4; Sun, 16 May 2021 09:31:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NBvx3ZRoDgl80K9VVvdFB7JT6nJ28gioNqV0ZRb/4Jk=; b=Zn1sBPo1QQA58bgKFSE3Dq88d8sFZ5NEf9LEBMn2GDDGW5ktJuGqou00CZ3aVCXp6z T1dlO/ZMgUP+vC8oWk82QxCrI6gt6Sg+HJkYYkO2SWl6FaRIDB6eR2oCbO8sbRBXmmiZ TWpU/0errtGBobPKscwVDi0m5mfsJNZyrbsSldfCb33ahnrWuwl/L77CsdU3ctIAoj53 QMsIHO5GBvKmL6V0yN05do8RhfjYEd5qJPBinzEea++C0b73y17c/+yi+BUmiHSi98lT dSGrpMcTAin1hEMlKwf2gEiCC+qiK2d29pURPMR0UNaZwJqSkP+0OPO/1vIQXCl5r5kY ylBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NBvx3ZRoDgl80K9VVvdFB7JT6nJ28gioNqV0ZRb/4Jk=; b=B6NrtTTWBoGTmXt4J0STB4YKQK4VAV07WCpfhgFkX/VcuwhN3ohQjPDw0mdopvqq9s k+0I2RIzrWv6S7G7QexzXPoPk4Kttm0n6gdLMYpWaPymU8gE50KkDLbylj1320zpiY+Z wfD2F6TBNwMa4YEOaC/D76LPYVIWpIuSEh4OahrWCjNHyPm1gJetI5uHHQiJwj2IyhIy aZ79eZv91lfUHjqAGzv12c0SxJz++MhL8VQRLljWZtBikPQ0ucs4C8y0wC40MoYdkq13 xU0gJ+PSukZHDzCUuTTibvkHh6u+b+7wMbVf1p4CLUhI8WAnDMtP9lEZSj7j0p5TLS4V PeZA== X-Gm-Message-State: AOAM530wJmV8YF/ZR05IUznU/5eRuSIEwL5Qd9nMqI0UK6o6flobIGcP z8EEn4MSWjkDPoWcXud0Zik= X-Google-Smtp-Source: ABdhPJzywX90FF0+95kROLOeVZqbNr2xOTCoFoErMRzf/B2nLgbasUndud0qpKOGOjhJCMNYTO1U9w== X-Received: by 2002:ac2:5967:: with SMTP id h7mr20518534lfp.20.1621182665359; Sun, 16 May 2021 09:31:05 -0700 (PDT) Received: from localhost.localdomain (109-252-193-91.dynamic.spd-mgts.ru. [109.252.193.91]) by smtp.gmail.com with ESMTPSA id m2sm1704548lfo.23.2021.05.16.09.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 09:31:05 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Cc: Rob Herring , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 9/9] dt-bindings: clock: tegra: Convert to schema Date: Sun, 16 May 2021 19:30:41 +0300 Message-Id: <20210516163041.12818-10-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210516163041.12818-1-digetx@gmail.com> References: <20210516163041.12818-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert NVIDIA Tegra clock bindings to schema. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- 7 files changed, 184 insertions(+), 352 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index 9acea9d93160..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA114_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt deleted file mode 100644 index 7f02fb4ca4ad..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra124 and Tegra132 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in the header files - (which covers IDs common - to Tegra124 and Tegra132) and - (for Tegra124-specific clocks). -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. -- nvidia,external-memory-controller : phandle of the EMC driver. - -The node should contain a "emc-timings" subnode for each supported RAM type (see -field RAM_CODE in register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set - is used for. - -Each "emc-timings" node should contain a "timing" subnode for every supported -EMC clock rate. - -Required properties for "timing" nodes : -- clock-frequency : Should contain the memory clock rate to which this timing -relates. -- nvidia,parent-clock-frequency : Should contain the rate at which the current -parent of the EMC clock should be running at this timing. -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - emc-parent : the clock that should be the parent of the EMC clock at this -timing. - -Example SoC include file: - -/ { - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA124_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <112400000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; - - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml new file mode 100644 index 000000000000..ec7ab1483652 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + const: nvidia,tegra124-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + + nvidia,external-memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the external memory controller node + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that + this timing set is used for + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + external memory clock rate in Hz + minimum: 1000000 + maximum: 1000000000 + + nvidia,parent-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + rate of parent clock in Hz + minimum: 1000000 + maximum: 1000000000 + + clocks: + items: + - description: parent clock of EMC + + clock-names: + items: + - const: emc-parent + + required: + - clock-frequency + - nvidia,parent-clock-frequency + - clocks + - clock-names + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + + car: clock-controller@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb-controller@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + clocks = <&car TEGRA124_CLK_USB2>; + resets = <&car TEGRA124_CLK_USB2>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted file mode 100644 index 6c5901b503d0..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra20 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra20-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA20_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml new file mode 100644 index 000000000000..459d2a525393 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + enum: + - nvidia,tegra20-car + - nvidia,tegra30-car + - nvidia,tegra114-car + - nvidia,tegra210-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + + car: clock-controller@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb-controller@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + clocks = <&car TEGRA20_CLK_USB2>; + resets = <&car TEGRA20_CLK_USB2>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt deleted file mode 100644 index 26f237f641b7..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt +++ /dev/null @@ -1,56 +0,0 @@ -NVIDIA Tegra210 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra210-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra210-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA210_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt deleted file mode 100644 index 63618cde12df..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra30 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra30-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA30_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -};