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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 27-v6si5233198qkt.153.2018.06.28.17.20.45 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 28 Jun 2018 17:20:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NpFTEKNg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh9Y-00075e-TZ for patch@linaro.org; Thu, 28 Jun 2018 20:20:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4k-00041N-0g for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4h-0006dI-Km for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:45 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:42625) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4h-0006bo-F7 for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:43 -0400 Received: by mail-pf0-x22a.google.com with SMTP id v9-v6so2217450pff.9 for ; Thu, 28 Jun 2018 17:15:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qCoeOPRxfqBzz9U1Vv3Tu63bMTIpVPlkzyb0DKca5aA=; b=NpFTEKNgXJFVxapcFnnRhZb8ww9RZZBAxkES07rf7QGi3ZXnJCBb+1k0l79ycQqzch w6eUL+kY7WMWtLY3+kwFXJ0WJDIaS1/QyrYpWwCoN6qCu/2BuMnUz78/q/wZTUnk63b3 6EVe9KE1S9Eva1vQ5taGd70hY/GdMxaYQeMAI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qCoeOPRxfqBzz9U1Vv3Tu63bMTIpVPlkzyb0DKca5aA=; b=k6mc539irYc4ABqoDzDpaDU1n5V30EaU/KcisV8eAyjt1ziwIlXPpCtZfJHfuA883k UWsoD1WKIciStJQqwlTid+HPTSc4N/sFpxdoraj05Bz+ZtDhdgyd1Of1IXU4jlBjM0zD 7gAS5k02q/TAwxNOQv77kHs3SRZ0Gviuw9DCsE+8lCGA6X0i45yvsfWs/BXnLK5IKPiF zPCPZjl4C6UUUHuVxzfdDHp/KM5rY6mnDQ/paAuBS6SOCvqwART7cpbUPG6XS2/6e73j rxrHohU+ce9BDvmAkgcYE9UGCQn9EPEScbYtWGxE3/byRXm6so0QU6ovJtzS//SZSR65 zc0Q== X-Gm-Message-State: APt69E0tgXcaFMidSGPmgVqy1dD9JRwxTghG6oc1AAiNSfVoXuQTsXoZ w+H7Ac85JzD0WKE59Hc4u4zdKFZPFPc= X-Received: by 2002:a65:6699:: with SMTP id b25-v6mr10723196pgw.426.1530231342298; Thu, 28 Jun 2018 17:15:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:33 -0700 Message-Id: <20180629001538.11415-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH 1/6] target/arm: Fix SVE signed division vs x86 overflow exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already check for the same condition within the normal integer sdiv and sdiv64 helpers. Use a slightly different formation that does not require deducing the expression type. Fixes: f97cfd596ed Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 790cbacd14..7d7fc90566 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -369,7 +369,13 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) #define DO_MUL(N, M) (N * M) -#define DO_DIV(N, M) (M ? N / M : 0) + +/* The zero divisor case is architectural; the -1 divisor case works + * around the x86 INT_MIN / -1 overflow exception without having to + * deduce the minimum integer for the type of the expression. + */ +#define DO_SDIV(N, M) (unlikely(M == 0) ? 0 : unlikely(M == -1) ? -N : N / M) +#define DO_UDIV(N, M) (unlikely(M == 0) ? 0 : N / M) DO_ZPZZ(sve_and_zpzz_b, uint8_t, H1, DO_AND) DO_ZPZZ(sve_and_zpzz_h, uint16_t, H1_2, DO_AND) @@ -477,11 +483,11 @@ DO_ZPZZ(sve_umulh_zpzz_h, uint16_t, H1_2, do_mulh_h) DO_ZPZZ(sve_umulh_zpzz_s, uint32_t, H1_4, do_mulh_s) DO_ZPZZ_D(sve_umulh_zpzz_d, uint64_t, do_umulh_d) -DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_DIV) -DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV) +DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_SDIV) +DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_SDIV) -DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV) -DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV) +DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_UDIV) +DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_UDIV) /* Note that all bits of the shift are significant and not modulo the element size. */ From patchwork Fri Jun 29 00:15:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140484 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp197160ljj; Thu, 28 Jun 2018 17:16:15 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdDVUMr1yNSbV30teWNOCZXsxiQQkPHwbs5xahCyBSCZNbEoc4infdOWkmfA6kjp/xEjfUY X-Received: by 2002:aed:3f5d:: with SMTP id q29-v6mr11069257qtf.403.1530231375374; Thu, 28 Jun 2018 17:16:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530231375; cv=none; d=google.com; s=arc-20160816; b=uFcdQcPDRDiMwDtC2VepEt45N2S22vaFJe8Bv2Q/fdSr+l50sbwT233ydw6NvJCu8c tI6q09Lma3wb0gx1gYJUyOBpvV/lkyzFHMa2m8yTixq+sEZmKC2Yha4fwCHkIU2xloen jiJfgQBb1logaeLpPix0wSHrpwJUSanqIfoZVKdEKUkTsde8WMLlS3fb+0gDjTiAkjFg KHRveNeGDOKc6hTnPkZ5N0RmFEzhY2f2FJIxxPH7bTAd6sNq28n33jOEbsXpC552EGxE hEMSipshmLYaMj4/Z2uQN/UgE+kUF3kLfab2SuGnfJ7yrBO4+1WnS4QossyhM74G8TPZ 9dmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=bDxeI45M3+Sw5t2d9J5a8/XWQwI0hxpwq9USCSGZuao=; b=KgdYJEdnxrNVfkYw406ayhpBsEJlRxlB5WW3KwgW2+tsmAlhVc35LIetuqhl+cKjPY SldgmRL6IkRGrRmN4OOQL8EP9MJdLkfzS9kt+SOS8QoCGJvChpcrULbRjr9MJglc4HST OSGc0E1Mx48bP0bnoA+W5/f7AK6OboZVJzaE93rMYfBgdGM4JyOsAl/bZuLhkhmcwoIQ 7TMv9pDyDx468bZM7sgtWXSIL5D/eereeTASjr8ajpC2+Yt3EBksQEACkOo6ruQNQWmc cuVCSeRqGlbClAPA7u71SwR9hZMVg90AmEjLjnQoY9GidnyM6EE+dlAQ1sbgdxghipC6 kzXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b1CydImQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:34 -0700 Message-Id: <20180629001538.11415-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22b Subject: [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check produced by the flag already includes fp_access_check. If we also check ARM_CP_FPU the double fp_access_check asserts. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 ++++---- target/arm/translate-a64.c | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues diff --git a/target/arm/helper.c b/target/arm/helper.c index b19c7ace78..a855da045b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4393,7 +4393,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo zcr_el1_reginfo = { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, - .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU, + .access = PL1_RW, .type = ARM_CP_SVE, .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), .writefn = zcr_write, .raw_writefn = raw_write }; @@ -4401,7 +4401,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = { static const ARMCPRegInfo zcr_el2_reginfo = { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, - .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU, + .access = PL2_RW, .type = ARM_CP_SVE, .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), .writefn = zcr_write, .raw_writefn = raw_write }; @@ -4409,14 +4409,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = { static const ARMCPRegInfo zcr_no_el2_reginfo = { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, - .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU, + .access = PL2_RW, .type = ARM_CP_SVE, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }; static const ARMCPRegInfo zcr_el3_reginfo = { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, - .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU, + .access = PL3_RW, .type = ARM_CP_SVE, .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), .writefn = zcr_write, .raw_writefn = raw_write }; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f986340832..45a6c2a3aa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, default: break; } - if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - return; - } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; } if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { From patchwork Fri Jun 29 00:15:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140485 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp197189ljj; Thu, 28 Jun 2018 17:16:17 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeCTYI9u1C1xO1roleARTvlzTRYuJs0TlYYDeFSDzwhCqvj2lUBTIXBLAsOTaN+vJP1irC3 X-Received: by 2002:ac8:3a64:: with SMTP id w91-v6mr11452640qte.88.1530231377125; Thu, 28 Jun 2018 17:16:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530231377; cv=none; d=google.com; s=arc-20160816; b=gO2T5nJIucwZ3lRJd9uhbVJdV1mL4AzN9GC7QcscgeNkD7bw78hBowScQgTTr799WM VrIRIaxzHin82S7z/A2X/Ew+a1ZQJBhV9is+efqYdnSlwM1y9N5JmtxyrL+92gwWO0KB fVrMX73aGzrl6WvTQ6s6DUmOmp8O0Knp6i5vO0iDD3TJ/JA0F0C0P+Kfzqn66oiAZAEr qfN4MHfrlQ6nHkA4AifITQj0OcvieHxa1/CiqxcT9NTpTyTzi4i5QRvbhZ4oD2aHv1RU 6FuQ+Pz1UA8vnmZlKMwv/3ucBhn0txEciF95m8LBXWpqWSlcQwNad50jxAZHUjNxAlUN QZRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aIqsOu2TjX3ToM1uKZUQ3z3HkuGStyywZKhiXfkMdBY=; b=IecqUjjsIzCrvwNMBEOqO8tOEZd/aqQtvhwXp0ENaKBuZkoGQToAFfaS9PxMfKYZXl jjWX0kFN8Su2rn8A+WawyVqm2jgtQ1sLifwkwc1QaLjtaivoufkF+cdlQjasJTzQ7fGN DW32gax8tfiNyo/P8txkx2aNUHFftBJhhfb6BwzeStB//NhDeokQRqoJjF5xBzDgAIBI FaCJCaEYbJOcjLibAyfD3PzQUgNGBOJcMRWknuf35kTN83ZgUai+f/bACvGJHEo+W+ki gEW4u8WiXLRZbif0aykYUAMh1vux5GNUxVqH+nEvO8vynpD7Qtxz/C0IaPH2eCA6XIar p29A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JjAqTkjL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:35 -0700 Message-Id: <20180629001538.11415-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 3/6] target/arm: Prune a57 features from max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no need to re-set these 9 features already implied by the call to aarch64_a57_initfn. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 9 --------- 1 file changed, 9 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3b4bc73ffa..8040493d5c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -235,19 +235,10 @@ static void aarch64_max_initfn(Object *obj) * whereas the architecture requires them to be present in both if * present in either. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); set_feature(&cpu->env, ARM_FEATURE_V8_SM3); set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); set_feature(&cpu->env, ARM_FEATURE_V8_RDM); set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); From patchwork Fri Jun 29 00:15:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140489 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp200715ljj; Thu, 28 Jun 2018 17:20:59 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfUseGjjo6GzM3ney/X23bzvFHrJ4QHKl+Iy2iXo8JBfCa/Dmu6WaP/loNCNZH03GRhWRsT X-Received: by 2002:ac8:8c3:: with SMTP id y3-v6mr11661417qth.150.1530231659312; Thu, 28 Jun 2018 17:20:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530231659; cv=none; d=google.com; s=arc-20160816; b=j1ROIoVr29PF0gPg7SAm5amTArLAgxXraXHftfyolfm4MGA/WrrpmNhPGhzK0e5EqQ srzKGGBhSnxubX7VGMaLTUqeDfiLFQR3yKfwItCAliKT3veRYWeXUUDjpOgCTW1fHiIW 8vJ/wiv/evZp49xlraH8GOeG6T/ybMkP9aFfJN50Tn+Tms0H8tuPDHJkqDnt/1YXNadk YPzc4AxvT6aq+SUKyhOqWB7rliSy/3kFkhCiLkpMKkI4Io/VZ7YTGv8HNSjTyQVxRrAK 5UOa4rmaM3DG4VY2ByuoIfbrWBREuyw24dOUmwOTO7hQfwHplT2MErYU2z3krUAym7gJ 1UCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mHBz3+eq9kbfyBEjgaxotqiA3EmZG97H4thceVsKJNg=; b=NU1QrZE6NRiyFl42n/UVi0nox5XY1q6T2tUud+PN1l45/2qeWPxs8rfSoLKaWFpw5Y u8uKWfeDgtzLkwylNuMisHOPU/T1GunZfQiQNIzTZKtwfLPy1UAflx9K0kJizJfypi8/ yJS40Vlv+Dje4+GdiC75zg+GErroui2b2/3Jjv+6RZXo9mAYsv50A2ChQ4czJyjafMGF wGHRIlFQ/iVpQgn9pzKLuPlhodbDou1Cu4sihu7L5o9dDz6+Zyam+mdGNha0drMVRG88 RbWt89lf+r5KslHuK6uo8JlJNTmdXZI1JX1lbyqGH+EROuY+K4rQH0dh1u6sRPk13+ER Q4Ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AauG+fHx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 126-v6si5692056qkg.243.2018.06.28.17.20.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 28 Jun 2018 17:20:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AauG+fHx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39257 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh9m-0007lN-Rs for patch@linaro.org; Thu, 28 Jun 2018 20:20:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYh4m-000426-HT for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYh4l-0006gl-LO for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:48 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:39642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYh4l-0006gO-El for qemu-devel@nongnu.org; Thu, 28 Jun 2018 20:15:47 -0400 Received: by mail-pf0-x22a.google.com with SMTP id s21-v6so3344370pfm.6 for ; Thu, 28 Jun 2018 17:15:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mHBz3+eq9kbfyBEjgaxotqiA3EmZG97H4thceVsKJNg=; b=AauG+fHxNAtp03tYCnJEzXbi/WIcpu/hZJEylI26SIRcQjqTt+2zKZ1kvCH6Olq8Uq rGPYcpSOIj+w5F3u3DGkrxDQxNe5EUOWxS60BACx9DNqSttLDlHfvwztAPJUgYBOBpCn Ke+g6Wf3jh9JVMSsskcMR1H2VyqY0d3GswFeM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mHBz3+eq9kbfyBEjgaxotqiA3EmZG97H4thceVsKJNg=; b=aVxVzolDptYKn+r5b1dcp7WiMdA1mhZGf3yxg8GfZ+AXvOTjtPcl3s1oGHt8guVz+E Fg7kBefx0Cag5RdCOG2z7hpd/FpdFTunMTC61ySpzX6s6ECuDrerMro7T2YJTqxFnx5U wzBJgTTrqLHqKOq0avYcsOAXmOfsSo5dRt3YGfhuMismi5XiAVoCievj63PHqat//GKp EL6SWH1ttsfSDUoWRROAdu9cgNsBrRE3Rc9Ui+pPyzYemf8C2FSkKdN3D6iinNn0p4T/ Yy6Bo6OAQkSnePXz22WroWkQxfWo/DrO8Vgf+Is5gfFea7BsBA0IKZbyLCfkOAeAXzFW +BbQ== X-Gm-Message-State: APt69E1UB/T+utOZaR5reodOGm6/9YmRZlVDBPM+vthV2BVlU8h9a1b3 yzRpQJQAtOBxIvVsUs8iGNbhtZu9D98= X-Received: by 2002:a62:ed13:: with SMTP id u19-v6mr12128699pfh.125.1530231346317; Thu, 28 Jun 2018 17:15:46 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:36 -0700 Message-Id: <20180629001538.11415-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH 4/6] target/arm: Prune a15 features from max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no need to re-set these 3 features already implied by the call to aarch64_a15_initfn. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 --- 1 file changed, 3 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index aa62315cea..878cc6c7e8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1796,9 +1796,6 @@ static void arm_max_initfn(Object *obj) * since we don't correctly set the ID registers to advertise them, */ set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); From patchwork Fri Jun 29 00:15:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140487 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp199364ljj; Thu, 28 Jun 2018 17:19:17 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdWNt2n18xMNHU33QdpRjvS8bBiW+TYAsmG10+fCVdQFy9TlLdFvdr+qMlfcZohgsYZWtua X-Received: by 2002:ac8:36f0:: with SMTP id b45-v6mr11319126qtc.249.1530231557457; Thu, 28 Jun 2018 17:19:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530231557; cv=none; d=google.com; s=arc-20160816; b=VVbChmxXo1JGEUD4MSB2UgNy4iwkAOxa8uui8TtLFdjFvwBkdZuEuZhQYVES231UmO JfEb0MBY/pdx55MuURlJxUJKQestk33gFeBwJiP8F3PxcOQCPweZKNHrKE6bSR1CwceK uxMfvBj4ePZIJNwAdr8LWXB7OVBcsaiEQs4fROEtWiV4eWMcLv+C4v0Mez8M1coTHmEB mCxwACTGSMsXLMtaa1lBPIOfW4TIM6E9jxjWAk9OcxfHXZ6KAf3rrVn3omQ49WbNCKO6 wAs2jjEnnf8+Qk5BNAMyHDMuhzt0G722lo1StBzg43vx59e39yXMgnMBFAaXESSI9wMH S12A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=zcgc074MhgPb88dn8j3LBz2LriQUpfV1TTmj3EVQ6yA=; b=zvEGXb/nWAMxjLgVn3TESfs5zbk3KmKhq/koCuEAd8ZiJHWWWYQ3Q2IEsuwTSq0Ows Xk7mj/Es3O86SAdXy+bhVP3OBgMISxHNx4rvvwfEntuNu9u+Z9h+VmoMvRF0GF7kW9Dq Lu1/JXPLv/OpKf88KScCjZH6DJhcao7iT6B3skvxoy3NwbniEDvaLwgBEdB6c5VAkTZc w86biocHJlXaPqVEG5wI/nJ6mAU1OhoiSZQKLH9fQoGXLeqpg8dBZNe3vPe8SBubdiia bvktwLlur9NlgXG+ULgWzJYGryotLGfwZGjR6Wxe9/o0Rz1eglTVTzoJeVsHW4iRzruG Eqtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IcyAqCX9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:37 -0700 Message-Id: <20180629001538.11415-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22c Subject: [Qemu-devel] [PATCH 5/6] target/arm: Add ID_ISAR6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This register was added to aa32 state by ARMv8.2. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 2 ++ target/arm/helper.c | 5 ++--- 4 files changed, 9 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a8441c2dd..1505ac936e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -813,6 +813,7 @@ struct ARMCPU { uint32_t id_isar3; uint32_t id_isar4; uint32_t id_isar5; + uint32_t id_isar6; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64dfr0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 878cc6c7e8..de1a07a9f1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1262,6 +1262,7 @@ static void cortex_m3_initfn(Object *obj) cpu->id_isar3 = 0x01111110; cpu->id_isar4 = 0x01310102; cpu->id_isar5 = 0x00000000; + cpu->id_isar6 = 0x00000000; } static void cortex_m4_initfn(Object *obj) @@ -1288,6 +1289,7 @@ static void cortex_m4_initfn(Object *obj) cpu->id_isar3 = 0x01111110; cpu->id_isar4 = 0x01310102; cpu->id_isar5 = 0x00000000; + cpu->id_isar6 = 0x00000000; } static void cortex_m33_initfn(Object *obj) @@ -1316,6 +1318,7 @@ static void cortex_m33_initfn(Object *obj) cpu->id_isar3 = 0x01111131; cpu->id_isar4 = 0x01310132; cpu->id_isar5 = 0x00000000; + cpu->id_isar6 = 0x00000000; cpu->clidr = 0x00000000; cpu->ctr = 0x8000c000; } @@ -1366,6 +1369,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_isar3 = 0x01112131; cpu->id_isar4 = 0x0010142; cpu->id_isar5 = 0x0; + cpu->id_isar6 = 0x0; cpu->mp_is_up = true; cpu->pmsav7_dregion = 16; define_arm_cp_regs(cpu, cortexr5_cp_reginfo); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8040493d5c..d0581d59d8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -139,6 +139,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_isar3 = 0x01112131; cpu->id_isar4 = 0x00011142; cpu->id_isar5 = 0x00011121; + cpu->id_isar6 = 0; cpu->id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; cpu->pmceid0 = 0x00000000; @@ -199,6 +200,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->id_isar3 = 0x01112131; cpu->id_isar4 = 0x00011142; cpu->id_isar5 = 0x00011121; + cpu->id_isar6 = 0; cpu->id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; cpu->id_aa64isar0 = 0x00011120; diff --git a/target/arm/helper.c b/target/arm/helper.c index a855da045b..e62f02d4e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4851,11 +4851,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_mmfr4 }, - /* 7 is as yet unallocated and must RAZ */ - { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, + { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = 0 }, + .resetvalue = cpu->id_isar6 }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v6_idregs); From patchwork Fri Jun 29 00:15:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140486 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp197292ljj; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id j3-v6sm11687618pff.35.2018.06.28.17.15.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 17:15:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 17:15:38 -0700 Message-Id: <20180629001538.11415-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180629001538.11415-1-richard.henderson@linaro.org> References: <20180629001538.11415-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 6/6] target/arm: Set ISAR bits for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the supported extensions, fill in the appropriate bits in ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 24 +++++++++++++++++------- target/arm/cpu64.c | 36 ++++++++++++++++++++++++++++-------- 2 files changed, 45 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de1a07a9f1..943c589445 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1795,19 +1795,29 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + cpu->id_isar5 = deposit32(cpu->id_isar5, 4, 4, 2); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + cpu->id_isar5 = deposit32(cpu->id_isar5, 8, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + cpu->id_isar5 = deposit32(cpu->id_isar5, 12, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->id_isar5 = deposit32(cpu->id_isar5, 16, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + cpu->id_isar5 = deposit32(cpu->id_isar5, 24, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + cpu->id_isar5 = deposit32(cpu->id_isar5, 28, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); + cpu->id_isar6 = deposit32(cpu->id_isar6, 4, 4, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, */ set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); #endif } } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0581d59d8..b24fee45e3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -230,6 +230,34 @@ static void aarch64_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { aarch64_a57_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 12, 4, 2); + + set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 20, 4, 2); + + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 28, 4, 1); + cpu->id_isar5 = deposit32(cpu->id_isar5, 24, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 32, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 36, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 40, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); + cpu->id_aa64isar0 = deposit64(cpu->id_aa64isar0, 44, 4, 1); + cpu->id_isar6 = deposit32(cpu->id_isar6, 4, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + cpu->id_aa64isar1 = deposit64(cpu->id_aa64isar1, 16, 4, 1); + cpu->id_isar5 = deposit32(cpu->id_isar5, 28, 4, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, @@ -237,15 +265,7 @@ static void aarch64_max_initfn(Object *obj) * whereas the architecture requires them to be present in both if * present in either. */ - set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does.