From patchwork Thu Jun 28 18:10:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 140470 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2494249ljj; Thu, 28 Jun 2018 11:12:17 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfB2h521aZ3fbmAQ+0uKxcB7+CNFVGG+xj/FbTNVmRd38LYGrQW8EXsTe+oYzn6Lku+rhWV X-Received: by 2002:a62:129a:: with SMTP id 26-v6mr9974201pfs.102.1530209537480; Thu, 28 Jun 2018 11:12:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530209537; cv=none; d=google.com; s=arc-20160816; b=Tff8Q6GVx06F3JttgPxG5YcgEF3QI9exFIfwIFsbT2kYIudkW4vWPIDgx3l8Fp6Idc nqKZsBHeVqehqC64Aboj41kLnubNgvtoP1x4ZdRs4yGUFq9/kYDglfKyGVUrGDRHlRsL OezX0y3ru4pgbiGWd+0Fyml1mwLU6VbShuWHcGrunLulu/2zg+fMMsNJlydKYYx25p8Z NyNpLWfvKv0WbhFjM8JH58+hNHKPgPqMSpe77rG+xNSmOiCF4zAmFMg0eOENt6aRrjlZ yhANVwaNhdjVE0eEodqSsr8XBAbS+B0lPwIerzze/r80LptP813AhGl9n5DFIwJw+wND 2s5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lyThY3JcGjNBnO+ReNP/irIxhSH65Nk/lsrkpXUda8k=; b=K7s3hTfiilt9UEOZz0iRLYIRyZD4+FAFwRWICTcyfehwZ4hCc3O7i1ZmiuNNACmbh1 7CIJZi0Wyp0QUliw7wRb09VYwuEv/0JNkElsjgOXJnsxj/YvBlQAB3Yo5lexooAQRFBo GtwWvDW7YiEjfzscUa5v6FLCmGmKHBqrpvoG3ksO6X7QkLeLfcPuC5slH/ZLjPi1KJQ8 8WVZN5JC/f+tvINgCBJkWP1BKBEjoA6vqPndfzvidxtVN7IeYGEAbAMIkJEoOGMcUJzr L0ARfKn5BDXR56m+iYe0hKkYdvlbT719oSG/NPIC8/TYgVMJGOuzl2D8PN7LC7NFR4c+ 7+2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g3ouznjk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y78-v6si6470096pfj.159.2018.06.28.11.12.17; Thu, 28 Jun 2018 11:12:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g3ouznjk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030370AbeF1SMP (ORCPT + 31 others); Thu, 28 Jun 2018 14:12:15 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:37948 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030372AbeF1SMK (ORCPT ); Thu, 28 Jun 2018 14:12:10 -0400 Received: by mail-pg0-f65.google.com with SMTP id c9-v6so2815442pgf.5 for ; Thu, 28 Jun 2018 11:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lyThY3JcGjNBnO+ReNP/irIxhSH65Nk/lsrkpXUda8k=; b=g3ouznjklWPZBbvmAyfrg5Y9KNRcCU7d+E1Az0Xu8Uks0RiSjLfwRPMGjH5ztikR64 OekdtDexa5DYVRyJX09evNTIHcJ7utN3w8FwAIqnMnM6ptYWnKs2vFNhjvRSqHNe8tOE ulNKcF5bz2zFtoIvoTjOp1p/rpwnUHD1TP/AU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lyThY3JcGjNBnO+ReNP/irIxhSH65Nk/lsrkpXUda8k=; b=AXkn9UlMMZ5XmjKGfTfWyLzJtJ7wqHgDLmkMfpEuEVojssHbH83KYw6es+jC8v1vwM C9qtdai5BzZFEawZ1QAqLXzW4tBWRHRGtKpWSLmllvA0FUQU7lOq0TpoYosiK2kjKMxj brXiQrRgH4qXf2mHS0cb9iFq8kyOSgWq1xRTD3xJyOewpXB1aTnTOVebnmSdzE9up3S3 Jb22F3k7rfKhT5gZ0eLLnM2A5usQQEqFEnMMkr28Fr7G3CbLo953LdfqinCNwoPw5iQr 8OC0D58tsPIojDN5Ja994PYHd3sm4zVRGuZNglY2oFlYBd2v2ZnYW5k0hjJ4HfFu/vry ZIhA== X-Gm-Message-State: APt69E1EeWrNmOqn88PMm3O3xLsIKTVU7EHxXOW1rddOf3Iq+XWq6X1N r44FR9isnVgVWJ2C8QS2A7Vs X-Received: by 2002:a62:c882:: with SMTP id i2-v6mr10884247pfk.13.1530209529729; Thu, 28 Jun 2018 11:12:09 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7141:9f8e:c1c3:7dd1:e694:9dc2]) by smtp.gmail.com with ESMTPSA id o13-v6sm13293132pgn.93.2018.06.28.11.11.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Jun 2018 11:12:09 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v2 2/6] arm64: dts: actions: Add Actions Semi S900 I2C controller nodes Date: Thu, 28 Jun 2018 23:40:38 +0530 Message-Id: <20180628181042.2239-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628181042.2239-1-manivannan.sadhasivam@linaro.org> References: <20180628181042.2239-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add I2C controller nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 7ae8b931f000..6f7b89edbe4d 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -174,6 +174,66 @@ #clock-cells = <1>; }; + i2c0: i2c@e0170000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0170000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + }; + + i2c1: i2c@e0172000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0172000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + }; + + i2c2: i2c@e0174000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0174000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default>; + }; + + i2c3: i2c@e0176000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0176000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e0178000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0178000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e017a000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe017a000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl@e01b0000 { compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; From patchwork Thu Jun 28 18:10:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 140471 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2494401ljj; Thu, 28 Jun 2018 11:12:27 -0700 (PDT) X-Google-Smtp-Source: ADUXVKL11PdWmUUqXM/aak3Xm/taWBZKfEWQMh8lPM21kztvAP1rQIece1mFksvSrKfZyBA7ycBl X-Received: by 2002:a63:6e08:: with SMTP id j8-v6mr9737302pgc.428.1530209547150; Thu, 28 Jun 2018 11:12:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530209547; cv=none; d=google.com; s=arc-20160816; b=vpygE0TX1Id0zdirxzx+aXQP5z5kiuI24hbimL3KIPDhVwHsnMQ8VT0ZWlk3lCAE83 V8so/IVaE0GCQNu0WzBqmgXMPNMAHkYlEYwJvFVXxDTQKK1glSx8LC6T2gPL8yKglm3S 21FIVZWcy5fSdcgbxekSkBD4uhFs+G6zfCfwlnf05sukypLfTSJQCFMoqEHc9dMWlFWa btI9pZe5umMmu53p+z1yezbC71cd5NP4MniOAZ3Cf/SFceKl/mQm5pWdY6ZmSM739Dw8 yjBJJ7g9oHK2Nz7b4ZU690Jd5UmRdWJK2QxeoEgg0jh8mfd3Nn6ABy0SE9qBHS51rNUs Cexw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=jKaIsRyzKhkDg6J6wTu4UQOBDgSWw0ctIoQUWUurWRc=; b=Kj1xNdHWt/LSveUfGKyGpcOGjrX7ua1rAXukT25bPlbz8r08+mjg8y2Nejm/bSheIo 0Qnr6lfYJWT4lVbehqX8eTEvf6aCBj0HhEWImTuCQC79ccJEly9LHk2ODyw3bGDkjPyX TvX31uF1m3KGhhA20XQCTGlFnPDaH8scs1CVJR3gUuccwHUNlUw0QmwVxs7/3dWEAT6S S3zbl3QuGHEJpFfV20GMuVanv8lM8Qyd1WgGa6lKnh/vzTaate9srXNdJt99qzDNMhKZ j8ARiemY46ocUkDuLRLAuHCS31jM6Tq1iftl9CaOYNDosl2wHpWMXGezxGd5lKZ4vKIC t0hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ji7xVmIF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z75-v6si1299202pfk.340.2018.06.28.11.12.26; Thu, 28 Jun 2018 11:12:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ji7xVmIF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030393AbeF1SMY (ORCPT + 31 others); Thu, 28 Jun 2018 14:12:24 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:42104 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030379AbeF1SMV (ORCPT ); Thu, 28 Jun 2018 14:12:21 -0400 Received: by mail-pg0-f65.google.com with SMTP id c10-v6so2812491pgu.9 for ; Thu, 28 Jun 2018 11:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jKaIsRyzKhkDg6J6wTu4UQOBDgSWw0ctIoQUWUurWRc=; b=ji7xVmIFpaBfSXoP22cxp8bXZPqOWBonglvDMbdV7VGjMPYTt6gNpSmrnI1MqdGzn+ PiEe5xE6h4U4z9SgwtXuLMu86ZTxQjWcnKEGuttIGyZ5YOw9L7d55Res/BGRNOFTKBSd sHPTFEQOrxA29jezCY/E9XSAqJInIRSusLkP0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jKaIsRyzKhkDg6J6wTu4UQOBDgSWw0ctIoQUWUurWRc=; b=Cgsb8MB7UJDXx7cxfbY1wMfLLiyptEKUqIj6yfjY5ibKUuEh0i8vx2A9JpnCWnAHQJ UTqZxZ8RxFUJQHvhlMDlN0bW9dLDgjhIHSVWQXZ6LWgxMwJAkJEHVo8eivUGcyaNRNZg mHUatSUiYnuZlxWBBkhPU3v1edBCJuKP8RYepWtYSTQ6nLvIO1yeZ9M7NR6kDpPHli2p 7TEgfvJ9mWy2Lr3dawtKhMU3+4buzBP/77I1Aqy1gySYJJ+fsR5wqC8ykO1OxCmbCLNZ 9EDKLwgAGASQP2rX3CxGsLWimlK9GDYb1Y5q4gDiOPhHlhllaibkDSCcusX9QpWlQFtl zy8A== X-Gm-Message-State: APt69E20aKq8Sa2Oyhh0ZPsOnJuGmIJtR9/WcoDKJlDDG5tlANKcYyUd uNJpvibsx4zLmIZhKDLbMtVI X-Received: by 2002:a63:3f05:: with SMTP id m5-v6mr9578133pga.51.1530209540867; Thu, 28 Jun 2018 11:12:20 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7141:9f8e:c1c3:7dd1:e694:9dc2]) by smtp.gmail.com with ESMTPSA id o13-v6sm13293132pgn.93.2018.06.28.11.12.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Jun 2018 11:12:20 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v2 3/6] arm64: dts: actions: Add pinctrl definition for S900 I2C controller Date: Thu, 28 Jun 2018 23:40:39 +0530 Message-Id: <20180628181042.2239-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628181042.2239-1-manivannan.sadhasivam@linaro.org> References: <20180628181042.2239-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinctrl definition for Actions Semi S900 I2C controller. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Signed-off-by: Manivannan Sadhasivam --- .../dts/actions/s900-bubblegum-96-pins.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi -- 2.17.1 diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi new file mode 100644 index 000000000000..95e8b31071f9 --- /dev/null +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pinctrl { + + i2c0_default: i2c0_default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; +}; From patchwork Thu Jun 28 18:10:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 140473 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2494802ljj; Thu, 28 Jun 2018 11:12:51 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeflnId2ADX620Opl7BG6aAYmU+XFlyA8b0pQouZmExeXpc6aV2bKhy4dnCj0+iYpei95yL X-Received: by 2002:a62:f5da:: with SMTP id b87-v6mr11205851pfm.113.1530209571604; Thu, 28 Jun 2018 11:12:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530209571; cv=none; d=google.com; s=arc-20160816; b=BxXYPZDMDjRGiYxw7g64HCZiLQLBQ56oIppIPIjj3Dx67TQrF9asocVG6WoNTVl0Ug lK3fgJn9K4mdyG+Kkytz+lt9rGOY+ze4uU7MxwmuS6fm3YCUCzeE/apvkBPQhzHmOk+n wtVs71ekf+mPsEqwNKER1MwPuQf61BWbdK295VZZZsHXR8kNay52HPzrpW2jUEIa0f5X 3OcqS7GB2kzE3tJNjJTP3sZJ2imuDetshikikYkNlGnv7GN+hqcKemwLYjJ1C6FzIDiB HcrbCFYNSqo1JcG0DwKGxVBJHlUQDCB3xUk8fn2kusOibVyadX+8bQ9c/Go5gDeYJ5jT p2kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=yNmaopPRpcmha9S+4hb0aqDnI2rHP+ICZJpoUCznOR0=; b=jH095FdCw8Enz7I3zq+Qu/MUDVeBRLzIKLCUTssGX86NNLFjnZr0MDVF/J6f0rY/My FpLqfbp81LYJ34qXla7z1Rda4ol4NVVeZZkvgj9CTZs9zsuktazVZgyUGSF53VYBNwrV iwxdH4TgqOAWq+/k8aoV+KfnBjTk+Im1BwcIKp0RZvHmWiLKMF7GCrtgEz1V/4JD9+aW Gz6V/O2EcozwarW6f1vcGhT/Y1CT6/0aXE9WudJvpTBoMxshl6mTWqLQD4x4LTcBgtJG EjdLUZFI3YllhYO6uIKYdgYV6Ua2jC4VA1KS5hbUScSPRshWEnJO3dATl2xeL3b1wwK2 QEdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hRHqDHTE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- drivers/i2c/busses/Kconfig | 7 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-owl.c | 471 +++++++++++++++++++++++++++++++++++ 3 files changed, 479 insertions(+) create mode 100644 drivers/i2c/busses/i2c-owl.c -- 2.17.1 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 4f8df2ec87b1..2062da17e33b 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -762,6 +762,13 @@ config I2C_OMAP Like OMAP1510/1610/1710/5912 and OMAP242x. For details see http://www.ti.com/omap. +config I2C_OWL + tristate "OWL I2C Controller" + depends on ARCH_ACTIONS || COMPILE_TEST + help + Say Y here if you want to use the I2C bus controller on + the Actions Semi OWL SoCs. + config I2C_PASEMI tristate "PA Semi SMBus interface" depends on PPC_PASEMI && PCI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 5a869144a0c5..b71618f77880 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o +obj-$(CONFIG_I2C_OWL) += i2c-owl.o obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c new file mode 100644 index 000000000000..12320fca6755 --- /dev/null +++ b/drivers/i2c/busses/i2c-owl.c @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OWL SoC's I2C driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +/* I2C registers */ +#define OWL_I2C_REG_CTL 0x0000 +#define OWL_I2C_REG_CLKDIV 0x0004 +#define OWL_I2C_REG_STAT 0x0008 +#define OWL_I2C_REG_ADDR 0x000C +#define OWL_I2C_REG_TXDAT 0x0010 +#define OWL_I2C_REG_RXDAT 0x0014 +#define OWL_I2C_REG_CMD 0x0018 +#define OWL_I2C_REG_FIFOCTL 0x001C +#define OWL_I2C_REG_FIFOSTAT 0x0020 +#define OWL_I2C_REG_DATCNT 0x0024 +#define OWL_I2C_REG_RCNT 0x0028 + +/* I2Cx_CTL Bit Mask */ +#define OWL_I2C_CTL_RB BIT(1) +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) +#define OWL_I2C_CTL_IRQE BIT(5) +#define OWL_I2C_CTL_EN BIT(7) +#define OWL_I2C_CTL_AE BIT(8) +#define OWL_I2C_CTL_SHSM BIT(10) + +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) + +/* I2Cx_STAT Bit Mask */ +#define OWL_I2C_STAT_RACK BIT(0) +#define OWL_I2C_STAT_BEB BIT(1) +#define OWL_I2C_STAT_IRQP BIT(2) +#define OWL_I2C_STAT_LAB BIT(3) +#define OWL_I2C_STAT_STPD BIT(4) +#define OWL_I2C_STAT_STAD BIT(5) +#define OWL_I2C_STAT_BBB BIT(6) +#define OWL_I2C_STAT_TCB BIT(7) +#define OWL_I2C_STAT_LBST BIT(8) +#define OWL_I2C_STAT_SAMB BIT(9) +#define OWL_I2C_STAT_SRGC BIT(10) + +/* I2Cx_CMD Bit Mask */ +#define OWL_I2C_CMD_SBE BIT(0) +#define OWL_I2C_CMD_RBE BIT(4) +#define OWL_I2C_CMD_DE BIT(8) +#define OWL_I2C_CMD_NS BIT(9) +#define OWL_I2C_CMD_SE BIT(10) +#define OWL_I2C_CMD_MSS BIT(11) +#define OWL_I2C_CMD_WRS BIT(12) +#define OWL_I2C_CMD_SECL BIT(15) + +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) + +/* I2Cx_FIFOCTL Bit Mask */ +#define OWL_I2C_FIFOCTL_NIB BIT(0) +#define OWL_I2C_FIFOCTL_RFR BIT(1) +#define OWL_I2C_FIFOCTL_TFR BIT(2) + +/* I2Cc_FIFOSTAT Bit Mask */ +#define OWL_I2C_FIFOSTAT_RNB BIT(1) +#define OWL_I2C_FIFOSTAT_RFE BIT(2) +#define OWL_I2C_FIFOSTAT_TFF BIT(5) +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) + +/* I2C bus timeout */ +#define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) + +#define OWL_I2C_MAX_RETRIES 50 + +#define OWL_I2C_DEFAULT_SPEED 100000 +#define OWL_I2C_MAX_SPEED 400000 + +struct owl_i2c_dev { + struct i2c_adapter adap; + struct i2c_msg *msg; + struct completion msg_complete; + struct clk *clk; + void __iomem *base; + unsigned long clk_rate; + u32 bus_freq; + u32 msg_ptr; +}; + +static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state) +{ + unsigned int regval; + + regval = readl(base); + + if (state) + regval |= val; + else + regval &= ~val; + + writel(regval, base); +} + +static int owl_i2c_reset(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val, timeout = 0; + + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + mdelay(1); + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, true); + + /* Reset FIFO */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, + true); + + /* Wait 50ms for FIFO reset complete */ + do { + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) + break; + mdelay(1); + } while (timeout++ < OWL_I2C_MAX_RETRIES); + + if (timeout > OWL_I2C_MAX_RETRIES) { + dev_err(&i2c_dev->adap.dev, "FIFO reset timeout"); + return -ETIMEDOUT; + } + + /* Clear status registers */ + writel(0, i2c_dev->base + OWL_I2C_REG_STAT); + + return 0; +} + +static int owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val; + + val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) / + (i2c_dev->bus_freq * 16); + + /* Set clock divider factor */ + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); + + return 0; +} + +static int owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev) +{ + int ret; + + /* Reset I2C controller */ + ret = owl_i2c_reset(i2c_dev); + if (ret) + return ret; + + /* Set bus frequency */ + return owl_i2c_set_freq(i2c_dev); +} + +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) +{ + struct owl_i2c_dev *i2c_dev = _dev; + struct i2c_msg *msg = i2c_dev->msg; + unsigned int stat, fifostat; + + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); + if (fifostat & OWL_I2C_FIFOSTAT_RNB) { + dev_dbg(&i2c_dev->adap.dev, "received NACK from device"); + owl_i2c_reset(i2c_dev); + goto stop; + } + + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (stat & OWL_I2C_STAT_BEB) { + dev_dbg(&i2c_dev->adap.dev, "bus error"); + owl_i2c_reset(i2c_dev); + goto stop; + } + + /* Handle FIFO read */ + if (msg->flags & I2C_M_RD) { + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_RFE) && + (i2c_dev->msg_ptr < msg->len)) { + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + + OWL_I2C_REG_RXDAT); + } + } else { + /* Handle the remaining bytes which were not sent */ + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_TFF) && + i2c_dev->msg_ptr < msg->len) { + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base + + OWL_I2C_REG_TXDAT); + } + } + +stop: + /* Clear pending interrupts */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, + OWL_I2C_STAT_IRQP, true); + + complete_all(&i2c_dev->msg_complete); + + return IRQ_HANDLED; +} + +static u32 owl_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + unsigned long timeout; + unsigned int val; + + /* Check for Arbitration lost */ + val = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (val & OWL_I2C_STAT_LAB) { + val &= ~OWL_I2C_STAT_LAB; + writel(val, i2c_dev->base + OWL_I2C_REG_STAT); + return -EAGAIN; + } + + /* Check for Bus busy */ + timeout = jiffies + OWL_I2C_TIMEOUT; + while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { + if (time_after(jiffies, timeout)) { + dev_err(&adap->dev, "Bus busy timeout"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + struct i2c_msg *msg; + unsigned long time_left; + unsigned int i2c_cmd; + unsigned int addr; + int ret = 0, idx; + + ret = owl_i2c_hw_init(i2c_dev); + if (ret) + return ret; + + ret = owl_i2c_check_bus_busy(adap); + if (ret) + return ret; + + reinit_completion(&i2c_dev->msg_complete); + + /* Enable I2C controller interrupt */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_IRQE, true); + + /* + * Select: FIFO enable, Master mode, Stop enable, Data count enable, + * Send start bit + */ + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE); + + /* Handle repeated start condition */ + if (num > 1) { + /* Set internal address length and enable repeated start */ + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1) + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE); + + /* Write slave address */ + addr = i2c_8bit_addr_from_msg(&msgs[0]); + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + /* Write internal register address */ + for (idx = 0; idx < msgs[0].len; idx++) + writel(msgs[0].buf[idx], i2c_dev->base + + OWL_I2C_REG_TXDAT); + + msg = &msgs[1]; + } else { + /* Set address length */ + i2c_cmd |= OWL_I2C_CMD_AS(1); + msg = &msgs[0]; + } + + i2c_dev->msg = msg; + i2c_dev->msg_ptr = 0; + + /* Set data count for the message */ + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); + + addr = i2c_8bit_addr_from_msg(msg); + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + if (!(msg->flags & I2C_M_RD)) { + /* Write data to FIFO */ + for (idx = 0; idx < msg->len; idx++) { + /* Check for FIFO full */ + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) + & OWL_I2C_FIFOSTAT_TFF) + break; + + writel(msg->buf[idx], + i2c_dev->base + OWL_I2C_REG_TXDAT); + } + + i2c_dev->msg_ptr = idx; + } + + /* Ignore the NACK if needed */ + if (msg->flags & I2C_M_IGNORE_NAK) + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, true); + else + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, false); + + /* Start the transfer */ + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); + + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, + adap->timeout); + if (time_left == 0) { + dev_err(&adap->dev, "Transaction timed out"); + /* Send stop condition and release the bus */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true); + ret = -ETIMEDOUT; + } + + /* Disable I2C controller */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + + return i2c_dev->msg_ptr ? num : i2c_dev->msg_ptr; +} + +static const struct i2c_algorithm owl_i2c_algorithm = { + .master_xfer = owl_i2c_master_xfer, + .functionality = owl_i2c_func +}; + +static const struct i2c_adapter_quirks owl_i2c_quirks = { + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, + .max_read_len = 240, + .max_write_len = 240, + .max_comb_1st_msg_len = 6, + .max_comb_2nd_msg_len = 240 +}; + +static int owl_i2c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct owl_i2c_dev *i2c_dev; + struct resource *res; + int ret, irq; + + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get IRQ number\n"); + return irq; + } + + if (of_property_read_u32(dev->of_node, "clock-frequency", + &i2c_dev->bus_freq)) + i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED; + + /* We support only frequencies of 100k and 400k for now */ + if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED && + i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) { + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); + return -EINVAL; + } + + i2c_dev->clk = devm_clk_get(dev, NULL); + if (IS_ERR(i2c_dev->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(i2c_dev->clk); + } + + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) + return ret; + + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); + if (!i2c_dev->clk_rate) { + dev_err(dev, "input clock rate should not be zero\n"); + ret = -EINVAL; + goto disable_clk; + } + + init_completion(&i2c_dev->msg_complete); + i2c_dev->adap.owner = THIS_MODULE; + i2c_dev->adap.algo = &owl_i2c_algorithm; + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; + i2c_dev->adap.quirks = &owl_i2c_quirks; + i2c_dev->adap.dev.parent = dev; + i2c_dev->adap.dev.of_node = dev->of_node; + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), + "%s", "OWL I2C adapter"); + i2c_set_adapdata(&i2c_dev->adap, i2c_dev); + + platform_set_drvdata(pdev, i2c_dev); + + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, + i2c_dev); + if (ret) { + dev_err(dev, "failed to request irq %d\n", irq); + goto disable_clk; + } + + return i2c_add_adapter(&i2c_dev->adap); + +disable_clk: + clk_disable_unprepare(i2c_dev->clk); + + return ret; +} + +static const struct of_device_id owl_i2c_of_match[] = { + {.compatible = "actions,s900-i2c"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, owl_i2c_of_match); + +static struct platform_driver owl_i2c_driver = { + .probe = owl_i2c_probe, + .driver = { + .name = "owl-i2c", + .of_match_table = of_match_ptr(owl_i2c_of_match), + }, +}; +module_platform_driver(owl_i2c_driver); + +MODULE_AUTHOR("David Liu "); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver"); +MODULE_LICENSE("GPL");