From patchwork Tue May 11 02:04:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30C56C43462 for ; Tue, 11 May 2021 02:07:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E3AE61622 for ; Tue, 11 May 2021 02:07:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230493AbhEKCIh (ORCPT ); Mon, 10 May 2021 22:08:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230421AbhEKCIa (ORCPT ); Mon, 10 May 2021 22:08:30 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C017CC06175F; Mon, 10 May 2021 19:07:24 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id i128so10178609wma.5; Mon, 10 May 2021 19:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ywmj3IHTQkkVsQ7wEgbE7GBFALDJcNZKZ3QK56WN2IY=; b=nBehbyh2zjuhB+fNjiosUbYppcwD3LZ1fAe2mRyPSN4wUCzjP/qcR2ZfwKbZmmr6cE Lef52ffl/lupseFToi/KOGqP5vJN6UoZlEcm03CRgvYcscZImHuhiJ1oQ2Q1axnhiRZ0 Qct8itEosQZIqgsjVj3+O8Ch/9CbfJEONK0GGmcvNH8P2I6zLAwEQMZYJNJdWmN+Krwl iFrKsUFy/FlVTOPAJKidp9gDWjQ3MiE5drQzoyySm2EN8iw5TvdwVf3WIF62O+xOygP0 rEyl+EjmIP/+Se1FfQVTXrd7AAu46Hl40N1XxRaDr+DHYtO6LW160Zcv360/PreaZ10P Xabg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ywmj3IHTQkkVsQ7wEgbE7GBFALDJcNZKZ3QK56WN2IY=; b=QfOc757YNjeR78r9WAGPGch2N7NUhN2MHow/OtUIdkPAr/Krsy5YXxHYd/YYNHkxqM tqffOQdauQZU+eWjaFn4P5rp05XqbWf6VKcMgWV3vFTjXPcGluOndcOHQe0NLNVUaO// JVetXANbggnWV0t/AIUrsBfvunkTyW5MVp7BzSwflNX6MNwqgwq56ROvj2EabFC3QjV6 a5y7coKEQ4xu2MYJO5qYybL0Erg0G9eKp3pr1MJyTWcuypO92/giddlQDmX+/3XEwcp4 VyuIi9VF2bWpwNemMOq/jBy03zb03TCW8nXFyFKML7zPJaT8REw7o8GDzDLqNCpxfVO9 6Ehg== X-Gm-Message-State: AOAM532KUNgV3TyApCSgYOFcO5DyLDI/fZQ4/OYRFoTfCwo4zrsKayR2 K2K3jtmWj83yaPLDobv06Qzl212S1nZRkg== X-Google-Smtp-Source: ABdhPJxtLj9L+yaOiSizSDIbz5Yo8ZhlBpma5s2px2/FW0He6tXjn2gGl1STGRTXqRbslPfn+LYkrg== X-Received: by 2002:a1c:401:: with SMTP id 1mr2349258wme.138.1620698843383; Mon, 10 May 2021 19:07:23 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:23 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 01/25] net: dsa: qca8k: change simple print to dev variant Date: Tue, 11 May 2021 04:04:36 +0200 Message-Id: <20210511020500.17269-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Change pr_err and pr_warn to dev variant. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli Reviewed-by: Andrew Lunn --- drivers/net/dsa/qca8k.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index cdaf9f85a2cb..0b295da6c356 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -701,7 +701,7 @@ qca8k_setup(struct dsa_switch *ds) /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { - pr_err("port 0 is not the CPU port\n"); + dev_err(priv->dev, "port 0 is not the CPU port"); return -EINVAL; } @@ -711,7 +711,7 @@ qca8k_setup(struct dsa_switch *ds) priv->regmap = devm_regmap_init(ds->dev, NULL, priv, &qca8k_regmap_config); if (IS_ERR(priv->regmap)) - pr_warn("regmap initialization failed"); + dev_warn(priv->dev, "regmap initialization failed"); ret = qca8k_setup_mdio_bus(priv); if (ret) From patchwork Tue May 11 02:04:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93983C433B4 for ; Tue, 11 May 2021 02:07:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E62E61622 for ; Tue, 11 May 2021 02:07:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231175AbhEKCIv (ORCPT ); Mon, 10 May 2021 22:08:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230467AbhEKCIe (ORCPT ); Mon, 10 May 2021 22:08:34 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA2C4C061760; Mon, 10 May 2021 19:07:27 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id o6-20020a05600c4fc6b029015ec06d5269so371098wmq.0; Mon, 10 May 2021 19:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lOhZtmXqoRB7AbKYw3B3ViWwWTWCEQNKhNHuzYiWBKQ=; b=Z7DVqFr6vUqNoLQbRWHtgaM31u1Jd5UsklU2u5hrRm4SfbnGAPGMVxe4t92LLCa2Uj SfEoxu8zK1B9qPdS2bOCiDC5VNJ1VdoFTpWrsUVhrDpYbs42h0n0YvkZSGJyi6T7mnXJ SJxINngF2TGh5AEwvvGh9yIfuIxKC1kdN9HVFnRWOvuU/HmnAcp/vfXAKf9/NSEMV1jY 6J+3ks+GR5B3vWQ+wT3olYX6vAmW36pm1lbo9hGe4b+F8kCJ4TJrTnxyNGU/pk1j2/Em wZMRT6aTEMMylG3Dv7+jzKn6MSSG24vkFET1v5jwpcSWt0WR7tQuVcwLZgi0rqxAeVaT vR3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lOhZtmXqoRB7AbKYw3B3ViWwWTWCEQNKhNHuzYiWBKQ=; b=AeL5O2pWZsTAXjeXhwT1mJkUnlUMyW75JAAF9dG8Rb1hUylkDW3IgfiDtyVK0xRtjY pHHDpdbQ99xY2pIMfDNyOoDvrOS7XabaAeU6l4Anw6/7tA3Elf8KrUzzfuSTf8wfDTDa EpCtaRNTfldozZVitIk+CE9MEC5Hr83mYBuqCyAFSfex8W7vYykjM7jPLid9mUTTSMBG iYNluMz2CiBbcSYgi4ZrIog48t+KIzQephuY0jLYQrOk+CqGQjvf0PDLp9Nu9aTqKfLY GIY9JCgS3oYIVbiCj7655+2z3XK2kHr1oPBbk5vlfK77G/CI7uOUiIVnVZsTi/8gwElb pvQw== X-Gm-Message-State: AOAM532Bx7PS/3tMZffiW8USmO0uCToi+CL8wYPGL59Ne0J8/I5ePzkY SinNod9uK8Qn2hgx1DHlgtk= X-Google-Smtp-Source: ABdhPJycOkHe1MkE/UKKktWJ4oRTGdQBCnYZ7x5W/y59WmNWjS7K1RJ0SGM+OVYBgGqbBX3OxVWkcA== X-Received: by 2002:a1c:1982:: with SMTP id 124mr30253383wmz.148.1620698846267; Mon, 10 May 2021 19:07:26 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:25 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 04/25] net: dsa: qca8k: handle qca8k_set_page errors Date: Tue, 11 May 2021 04:04:39 +0200 Message-Id: <20210511020500.17269-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org With a remote possibility, the set_page function can fail. Since this is a critical part of the write/read qca8k regs, propagate the error and terminate any read/write operation. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/dsa/qca8k.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 3c882d325fdf..c9830286fd6d 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -127,16 +127,23 @@ qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) "failed to write qca8k 32bit register\n"); } -static void +static int qca8k_set_page(struct mii_bus *bus, u16 page) { + int ret; + if (page == qca8k_current_page) - return; + return 0; - if (bus->write(bus, 0x18, 0, page) < 0) + ret = bus->write(bus, 0x18, 0, page); + if (ret < 0) { dev_err_ratelimited(&bus->dev, "failed to set qca8k page\n"); + return ret; + } + qca8k_current_page = page; + return 0; } static u32 @@ -150,11 +157,14 @@ qca8k_read(struct qca8k_priv *priv, u32 reg) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(bus, page); + val = qca8k_set_page(bus, page); + if (val < 0) + goto exit; + val = qca8k_mii_read32(bus, 0x10 | r2, r1); +exit: mutex_unlock(&bus->mdio_lock); - return val; } @@ -163,14 +173,19 @@ qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) { struct mii_bus *bus = priv->bus; u16 r1, r2, page; + int ret; qca8k_split_addr(reg, &r1, &r2, &page); mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(bus, page); + ret = qca8k_set_page(bus, page); + if (ret < 0) + goto exit; + qca8k_mii_write32(bus, 0x10 | r2, r1, val); +exit: mutex_unlock(&bus->mdio_lock); } @@ -185,12 +200,16 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(bus, page); + ret = qca8k_set_page(bus, page); + if (ret < 0) + goto exit; + ret = qca8k_mii_read32(bus, 0x10 | r2, r1); ret &= ~mask; ret |= val; qca8k_mii_write32(bus, 0x10 | r2, r1, ret); +exit: mutex_unlock(&bus->mdio_lock); return ret; From patchwork Tue May 11 02:04:40 2021 Content-Type: text/plain; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:27 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 05/25] net: dsa: qca8k: handle error with qca8k_read operation Date: Tue, 11 May 2021 04:04:40 +0200 Message-Id: <20210511020500.17269-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k_read can fail. Rework any user to handle error values and correctly return. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/dsa/qca8k.c | 73 ++++++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index c9830286fd6d..5eb4d13fe0ba 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -231,8 +231,13 @@ static int qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) { struct qca8k_priv *priv = (struct qca8k_priv *)ctx; + int ret; + + ret = qca8k_read(priv, reg); + if (ret < 0) + return ret; - *val = qca8k_read(priv, reg); + *val = ret; return 0; } @@ -300,15 +305,20 @@ qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) return ret; } -static void +static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) { - u32 reg[4]; + u32 reg[4], val; int i; /* load the ARL table into an array */ - for (i = 0; i < 4; i++) - reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); + for (i = 0; i < 4; i++) { + val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); + if (val < 0) + return val; + + reg[i] = val; + } /* vid - 83:72 */ fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; @@ -323,6 +333,8 @@ qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; fdb->mac[5] = reg[0] & 0xff; + + return 0; } static void @@ -374,6 +386,8 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) /* Check for table full violation when adding an entry */ if (cmd == QCA8K_FDB_LOAD) { reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC); + if (reg < 0) + return reg; if (reg & QCA8K_ATU_FUNC_FULL) return -1; } @@ -388,10 +402,10 @@ qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port) qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); - if (ret >= 0) - qca8k_fdb_read(priv, fdb); + if (ret < 0) + return ret; - return ret; + return qca8k_fdb_read(priv, fdb); } static int @@ -449,6 +463,8 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) /* Check for table full violation when adding an entry */ if (cmd == QCA8K_VLAN_LOAD) { reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1); + if (reg < 0) + return reg; if (reg & QCA8K_VTU_FUNC1_FULL) return -ENOMEM; } @@ -475,6 +491,8 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) goto out; reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); + if (reg < 0) + return reg; reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); if (untagged) @@ -506,6 +524,8 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) goto out; reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); + if (reg < 0) + return reg; reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_S(port); @@ -621,8 +641,11 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_BUSY)) return -ETIMEDOUT; - val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & - QCA8K_MDIO_MASTER_DATA_MASK); + val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); + if (val < 0) + return val; + + val &= QCA8K_MDIO_MASTER_DATA_MASK; return val; } @@ -978,6 +1001,8 @@ qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port, u32 reg; reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port)); + if (reg < 0) + return reg; state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); state->an_complete = state->link; @@ -1078,18 +1103,26 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; const struct qca8k_mib_desc *mib; - u32 reg, i; + u32 reg, i, val; u64 hi; for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { mib = &ar8327_mib[i]; reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - data[i] = qca8k_read(priv, reg); + val = qca8k_read(priv, reg); + if (val < 0) + continue; + if (mib->size == 2) { hi = qca8k_read(priv, reg + 4); - data[i] |= hi << 32; + if (hi < 0) + continue; } + + data[i] = val; + if (mib->size == 2) + data[i] |= hi << 32; } } @@ -1107,18 +1140,25 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); + int ret = 0; u32 reg; mutex_lock(&priv->reg_mutex); reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); + if (reg < 0) { + ret = reg; + goto exit; + } + if (eee->eee_enabled) reg |= lpi_en; else reg &= ~lpi_en; qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - mutex_unlock(&priv->reg_mutex); - return 0; +exit: + mutex_unlock(&priv->reg_mutex); + return ret; } static int @@ -1443,6 +1483,9 @@ qca8k_sw_probe(struct mdio_device *mdiodev) /* read the switches ID register */ id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + if (id < 0) + return id; + id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; if (id != QCA8K_ID_QCA8337) From patchwork Tue May 11 02:04:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FE64C43462 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:28 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 07/25] net: dsa: qca8k: handle error with qca8k_rmw operation Date: Tue, 11 May 2021 04:04:42 +0200 Message-Id: <20210511020500.17269-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k_rmw can fail. Rework any user to handle error values and correctly return. Change qca8k_rmw to return the error code or 0 instead of the reg value. The reg returned by qca8k_rmw wasn't used anywhere, so this doesn't cause any functional change. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/dsa/qca8k.c | 133 +++++++++++++++++++++++++--------------- 1 file changed, 83 insertions(+), 50 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 2fdd7c2e74d5..409f6592048a 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -190,12 +190,13 @@ qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) return ret; } -static u32 -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) +static int +qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) { struct mii_bus *bus = priv->bus; u16 r1, r2, page; - u32 ret; + u32 val; + int ret; qca8k_split_addr(reg, &r1, &r2, &page); @@ -205,10 +206,15 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) if (ret < 0) goto exit; - ret = qca8k_mii_read32(bus, 0x10 | r2, r1); - ret &= ~mask; - ret |= val; - qca8k_mii_write32(bus, 0x10 | r2, r1, ret); + val = qca8k_mii_read32(bus, 0x10 | r2, r1); + if (val < 0) { + ret = val; + goto exit; + } + + val &= ~mask; + val |= write_val; + qca8k_mii_write32(bus, 0x10 | r2, r1, val); exit: mutex_unlock(&bus->mdio_lock); @@ -216,16 +222,16 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) return ret; } -static void +static int qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) { - qca8k_rmw(priv, reg, 0, val); + return qca8k_rmw(priv, reg, 0, val); } -static void +static int qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) { - qca8k_rmw(priv, reg, val, 0); + return qca8k_rmw(priv, reg, val, 0); } static int @@ -570,12 +576,19 @@ qca8k_mib_init(struct qca8k_priv *priv) int ret; mutex_lock(&priv->reg_mutex); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); + ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); + if (ret) + goto exit; + qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); + + ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); + if (ret) + goto exit; ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); +exit: mutex_unlock(&priv->reg_mutex); return ret; } @@ -747,9 +760,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) * a dt-overlay and driver reload changed the configuration */ - qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_EN); - return 0; + return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); } priv->ops.phy_read = qca8k_phy_read; @@ -782,8 +794,12 @@ qca8k_setup(struct dsa_switch *ds) return ret; /* Enable CPU Port */ - qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); + ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, + QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); + if (ret) { + dev_err(priv->dev, "failed enabling CPU port"); + return ret; + } /* Enable MIB counters */ ret = qca8k_mib_init(priv); @@ -800,9 +816,12 @@ qca8k_setup(struct dsa_switch *ds) } /* Disable forwarding by default on all ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, 0); + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_MEMBER, 0); + if (ret) + return ret; + } /* Disable MAC by default on all ports */ for (i = 1; i < QCA8K_NUM_PORTS; i++) @@ -821,28 +840,37 @@ qca8k_setup(struct dsa_switch *ds) for (i = 0; i < QCA8K_NUM_PORTS; i++) { /* CPU port gets connected to all user ports of the switch */ if (dsa_is_cpu_port(ds, i)) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), + QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); + if (ret) + return ret; } /* Individual user ports get connected to CPU port only */ if (dsa_is_user_port(ds, i)) { int shift = 16 * (i % 2); - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_MEMBER, + BIT(QCA8K_CPU_PORT)); + if (ret) + return ret; /* Enable ARP Auto-learning by default */ - qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_LEARN); + ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_LEARN); + if (ret) + return ret; /* For port based vlans to work we need to set the * default egress vid */ - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), - 0xfff << shift, - QCA8K_PORT_VID_DEF << shift); + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), + 0xfff << shift, + QCA8K_PORT_VID_DEF << shift); + if (ret) + return ret; + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); @@ -1234,7 +1262,7 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int port_mask = BIT(QCA8K_CPU_PORT); - int i; + int i, ret; for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) @@ -1242,17 +1270,20 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) /* Add this port to the portvlan mask of the other ports * in the bridge */ - qca8k_reg_set(priv, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); + ret = qca8k_reg_set(priv, + QCA8K_PORT_LOOKUP_CTRL(i), + BIT(port)); + if (ret) + return ret; if (i != port) port_mask |= BIT(i); } + /* Add all other ports to this ports portvlan mask */ - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, port_mask); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_MEMBER, port_mask); - return 0; + return ret; } static void @@ -1389,18 +1420,19 @@ qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { struct qca8k_priv *priv = ds->priv; + int ret; if (vlan_filtering) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE, + QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); } else { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE, + QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); } - return 0; + return ret; } static int @@ -1422,16 +1454,17 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, if (pvid) { int shift = 16 * (port % 2); - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), - 0xfff << shift, vlan->vid << shift); + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), + 0xfff << shift, vlan->vid << shift); + if (ret) + return ret; + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), QCA8K_PORT_VLAN_CVID(vlan->vid) | QCA8K_PORT_VLAN_SVID(vlan->vid)); - if (ret) - return ret; } - return 0; + return ret; } static int From patchwork Tue May 11 02:04:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2E29C433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:31 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 09/25] net: dsa: qca8k: add support for qca8327 switch Date: Tue, 11 May 2021 04:04:44 +0200 Message-Id: <20210511020500.17269-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8327 switch is a low tier version of the more recent qca8337. It does share the same regs used by the qca8k driver and can be supported with minimal change. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++--- drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index d4e3f81576ec..693bd9fd532b 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1524,6 +1524,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { static int qca8k_sw_probe(struct mdio_device *mdiodev) { + const struct qca8k_match_data *data; struct qca8k_priv *priv; u32 id; @@ -1551,6 +1552,11 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } + /* get the switches ID from the compatible */ + data = of_device_get_match_data(&mdiodev->dev); + if (!data) + return -ENODEV; + /* read the switches ID register */ id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); if (id < 0) @@ -1558,8 +1564,10 @@ qca8k_sw_probe(struct mdio_device *mdiodev) id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; - if (id != QCA8K_ID_QCA8337) + if (id != data->id) { + dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); return -ENODEV; + } priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) @@ -1624,9 +1632,18 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); +static const struct qca8k_match_data qca832x = { + .id = QCA8K_ID_QCA8327, +}; + +static const struct qca8k_match_data qca833x = { + .id = QCA8K_ID_QCA8337, +}; + static const struct of_device_id qca8k_of_match[] = { - { .compatible = "qca,qca8334" }, - { .compatible = "qca,qca8337" }, + { .compatible = "qca,qca8327", .data = &qca832x }, + { .compatible = "qca,qca8334", .data = &qca833x }, + { .compatible = "qca,qca8337", .data = &qca833x }, { /* sentinel */ }, }; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 86c585b7ec4a..87a8b10459c6 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -15,6 +15,8 @@ #define QCA8K_NUM_PORTS 7 #define QCA8K_MAX_MTU 9000 +#define PHY_ID_QCA8327 0x004dd034 +#define QCA8K_ID_QCA8327 0x12 #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 @@ -213,6 +215,10 @@ struct ar8xxx_port_status { int enabled; }; +struct qca8k_match_data { + u8 id; +}; + struct qca8k_priv { struct regmap *regmap; struct mii_bus *bus; From patchwork Tue May 11 02:04:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55A0FC433ED for ; Tue, 11 May 2021 02:08:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38650616E9 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:32 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith , Rob Herring Subject: [RFC PATCH net-next v5 10/25] devicetree: net: dsa: qca8k: Document new compatible qca8327 Date: Tue, 11 May 2021 04:04:45 +0200 Message-Id: <20210511020500.17269-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for qca8327 in the compatible list. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn Acked-by: Rob Herring Reviewed-by: Florian Fainelli --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index ccbc6d89325d..1daf68e7ae19 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,6 +3,7 @@ Required properties: - compatible: should be one of: + "qca,qca8327" "qca,qca8334" "qca,qca8337" From patchwork Tue May 11 02:04:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB9FEC433B4 for ; Tue, 11 May 2021 02:08:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFE1A61622 for ; Tue, 11 May 2021 02:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231432AbhEKCKC (ORCPT ); Mon, 10 May 2021 22:10:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231241AbhEKCJH (ORCPT ); Mon, 10 May 2021 22:09:07 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90FEAC061353; Mon, 10 May 2021 19:07:37 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id v12so18465866wrq.6; Mon, 10 May 2021 19:07:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JG08upf6UrkrE9/6eQmYrVuXphDJ1Y+Z5Abl1+0TU5o=; b=U4rnYZkftp0bF0e8Wuq9y4bb3KAnYwhp4044LskA3WaT0Qvr7c6YMkQM++3GdgfY/h Ch7nd3mRa8oIDtygJitb0vXtwACEuJWQrO8gpsaur73pw+7hnYXIGjHTOj7ZljMq/FRi 7rkMjXcCdcHzR1k+AofIKfJop8czbZangyXv4uB2sjRB+LNfQBWjpCNrkDWIhjlE900Z qd2XdMHQfgqxsM1YPcHrvbWjP2iPaTagCJ9tlbBpESjnXhScGOTDVBP7xQZw6FjkhQOF vRhjbc4eTodIUzK3VFgU+AqBJKvVGxXvaRWbj/IEqCnZRP6hfGA4/LxdJvMen8oEmSMq mYDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JG08upf6UrkrE9/6eQmYrVuXphDJ1Y+Z5Abl1+0TU5o=; b=cFfKujHDLWfPPlxkhvpAwCy3QS4NjBF5bMxXEIxYNkveIr9+CKIrEf2qf4GNAPZ+cJ sdODwY4Ae0+mKCBEb1dQFzCFKaXYpuWzC4+dYlHL7PM0HLrwjZhU+LAIJb1bO8Kd1omD fj0BAGlFwtCVWlKr1IbXEuj6U/DMk06JErRaCa0NX6McLmFYgpSlNvPT7ctsMls6+6G7 4fb1jsZXzhPHOjFBTSw9zzShUHXubMjCO8OyACP5O/JKPMC3BQT0EERvjaX8d93GSumQ GYKiG+2jXXZQCYXaKXjLOdjz0jYM5iWLYK5y6+CjFisBX9FuFza/TQQVwR5NdoCWcRJZ f5Bg== X-Gm-Message-State: AOAM530MXbvoQzJMyq1098JfT488FMNe8M0td1bUqjUInZz4ZOzUdVT1 cOV6Fh7eFUkaRLkD4RlCJgE= X-Google-Smtp-Source: ABdhPJyfWGhGzx99A0nSMPpcro3bOK4qaCtjFhRyvcUi5OBeuZUcCBxDSLG+GLCHaOSUVIN16qHA1A== X-Received: by 2002:a5d:4649:: with SMTP id j9mr1480161wrs.360.1620698856250; Mon, 10 May 2021 19:07:36 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:36 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 14/25] net: dsa: qca8k: add support for switch rev Date: Tue, 11 May 2021 04:04:49 +0200 Message-Id: <20210511020500.17269-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k internal phy driver require some special debug value to be set based on the switch revision. Rework the switch id read function to also read the chip revision. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 53 ++++++++++++++++++++++++++--------------- drivers/net/dsa/qca8k.h | 7 ++++-- 2 files changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 10e3e1ca7e95..35ff4cf08786 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1579,12 +1579,40 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_link_up = qca8k_phylink_mac_link_up, }; +static int qca8k_read_switch_id(struct qca8k_priv *priv) +{ + const struct qca8k_match_data *data; + u32 val; + u8 id; + + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + if (!data) + return -ENODEV; + + val = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + if (val < 0) + return -ENODEV; + + id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); + if (id != data->id) { + dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id); + return -ENODEV; + } + + priv->switch_id = id; + + /* Save revision to communicate to the internal PHY driver */ + priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); + + return 0; +} + static int qca8k_sw_probe(struct mdio_device *mdiodev) { - const struct qca8k_match_data *data; struct qca8k_priv *priv; - u32 id; + int ret; /* allocate the private data struct so that we can probe the switches * ID register @@ -1610,24 +1638,11 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } - /* get the switches ID from the compatible */ - data = of_device_get_match_data(&mdiodev->dev); - if (!data) - return -ENODEV; - - /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); - if (id < 0) - return id; - - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; - if (id != data->id) { - dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); - return -ENODEV; - } + /* Check the detected switch id */ + ret = qca8k_read_switch_id(priv); + if (ret) + return ret; - priv->switch_id = id; priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) return -ENOMEM; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index eceeacfe2c5d..338277978ec0 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -30,8 +30,10 @@ /* Global control registers */ #define QCA8K_REG_MASK_CTRL 0x000 -#define QCA8K_MASK_CTRL_ID_M 0xff -#define QCA8K_MASK_CTRL_ID_S 8 +#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) +#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) +#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) +#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c @@ -251,6 +253,7 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_id; + u8 switch_revision; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Tue May 11 02:04:51 2021 Content-Type: text/plain; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:37 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 16/25] net: dsa: qca8k: make rgmii delay configurable Date: Tue, 11 May 2021 04:04:51 +0200 Message-Id: <20210511020500.17269-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The legacy qsdk code used a different delay instead of the max value. Qsdk use 1 ms for rx and 2 ms for tx. Make these values configurable using the standard rx/tx-internal-delay-ps ethernet binding and apply qsdk values by default. The connected gmac doesn't add any delay so no additional delay is added to tx/rx. On this switch the delay is actually in ms so value should be in the 1000 order. Any value converted from ps to ms by deviding it by 1000 as the switch max value for delay is 3ms. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 82 ++++++++++++++++++++++++++++++++++++++++- drivers/net/dsa/qca8k.h | 11 +++--- 2 files changed, 86 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index cc9ab35f8b17..ff46d253e345 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -777,6 +777,68 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return 0; } +static int +qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) +{ + struct device_node *port_dn; + phy_interface_t mode; + struct dsa_port *dp; + u32 val; + + /* CPU port is already checked */ + dp = dsa_to_port(priv->ds, 0); + + port_dn = dp->dn; + + /* Check if port 0 is set to the correct type */ + of_get_phy_mode(port_dn, &mode); + if (mode != PHY_INTERFACE_MODE_RGMII_ID && + mode != PHY_INTERFACE_MODE_RGMII_RXID && + mode != PHY_INTERFACE_MODE_RGMII_TXID) { + return 0; + } + + switch (mode) { + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val)) + val = 2; + else + /* Switch regs accept value in ms, convert ps to ms */ + val = val / 1000; + + if (val > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ms, setting to the max value"); + val = 3; + } + + priv->rgmii_rx_delay = val; + /* Stop here if we need to check only for rx delay */ + if (mode != PHY_INTERFACE_MODE_RGMII_ID) + break; + + fallthrough; + case PHY_INTERFACE_MODE_RGMII_TXID: + if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val)) + val = 1; + else + /* Switch regs accept value in ms, convert ps to ms */ + val = val / 1000; + + if (val > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ms, setting to the max value"); + val = 3; + } + + priv->rgmii_tx_delay = val; + break; + default: + return 0; + } + + return 0; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -802,6 +864,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_of_rgmii_delay(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); @@ -970,6 +1036,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case 0: /* 1st CPU port */ if (state->interface != PHY_INTERFACE_MODE_RGMII && state->interface != PHY_INTERFACE_MODE_RGMII_ID && + state->interface != PHY_INTERFACE_MODE_RGMII_TXID && + state->interface != PHY_INTERFACE_MODE_RGMII_RXID && state->interface != PHY_INTERFACE_MODE_SGMII) return; @@ -985,6 +1053,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case 6: /* 2nd CPU port / external PHY */ if (state->interface != PHY_INTERFACE_MODE_RGMII && state->interface != PHY_INTERFACE_MODE_RGMII_ID && + state->interface != PHY_INTERFACE_MODE_RGMII_TXID && + state->interface != PHY_INTERFACE_MODE_RGMII_RXID && state->interface != PHY_INTERFACE_MODE_SGMII && state->interface != PHY_INTERFACE_MODE_1000BASEX) return; @@ -1008,14 +1078,18 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); break; case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: /* RGMII_ID needs internal delay. This is enabled through * PORT5_PAD_CTRL for all ports, rather than individual port * registers */ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); + QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | + QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); /* QCA8337 requires to set rgmii rx delay */ if (priv->switch_id == QCA8K_ID_QCA8337) qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, @@ -1073,6 +1147,8 @@ qca8k_phylink_validate(struct dsa_switch *ds, int port, if (state->interface != PHY_INTERFACE_MODE_NA && state->interface != PHY_INTERFACE_MODE_RGMII && state->interface != PHY_INTERFACE_MODE_RGMII_ID && + state->interface != PHY_INTERFACE_MODE_RGMII_TXID && + state->interface != PHY_INTERFACE_MODE_RGMII_RXID && state->interface != PHY_INTERFACE_MODE_SGMII) goto unsupported; break; @@ -1090,6 +1166,8 @@ qca8k_phylink_validate(struct dsa_switch *ds, int port, if (state->interface != PHY_INTERFACE_MODE_NA && state->interface != PHY_INTERFACE_MODE_RGMII && state->interface != PHY_INTERFACE_MODE_RGMII_ID && + state->interface != PHY_INTERFACE_MODE_RGMII_TXID && + state->interface != PHY_INTERFACE_MODE_RGMII_RXID && state->interface != PHY_INTERFACE_MODE_SGMII && state->interface != PHY_INTERFACE_MODE_1000BASEX) goto unsupported; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 338277978ec0..a878486d9bcd 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -38,12 +38,11 @@ #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ - ((0x8 + (x & 0x3)) << 22) -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ - ((0x10 + (x & 0x3)) << 20) -#define QCA8K_MAX_DELAY 3 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) +#define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) @@ -254,6 +253,8 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_id; u8 switch_revision; + u8 rgmii_tx_delay; + u8 rgmii_rx_delay; struct regmap *regmap; struct mii_bus *bus; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:38 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 17/25] net: dsa: qca8k: clear MASTER_EN after phy read/write Date: Tue, 11 May 2021 04:04:52 +0200 Message-Id: <20210511020500.17269-18-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write operation. The MDIO_MASTER_EN bit is not reset after read/write operation and the next operation can be wrongly interpreted by the switch as a mdio operation. This cause a production of wrong/garbage data from the switch and underfined bheavior. (random port drop, unplugged port flagged with link up, wrong port speed) Also on driver remove the MASTER_CTRL can be left set and cause the malfunction of any next driver using the mdio device. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index ff46d253e345..6f713289703b 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -649,8 +649,14 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) if (ret) return ret; - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + + /* even if the busy_wait timeouts try to clear the MASTER_EN */ + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + + return ret; } static int @@ -685,6 +691,10 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) val &= QCA8K_MDIO_MASTER_DATA_MASK; + /* even if the busy_wait timeouts try to clear the MASTER_EN */ + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + return val; } From patchwork Tue May 11 02:04:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9171EC43460 for ; Tue, 11 May 2021 02:09:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75BE36162B for ; Tue, 11 May 2021 02:09:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231259AbhEKCKg (ORCPT ); Mon, 10 May 2021 22:10:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231303AbhEKCJR (ORCPT ); Mon, 10 May 2021 22:09:17 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89040C061355; Mon, 10 May 2021 19:07:42 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id o6-20020a05600c4fc6b029015ec06d5269so371299wmq.0; Mon, 10 May 2021 19:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GZcsI50W8fZKEEfpBDfMPpDBGNdHj0jl0+ZTd0U5FBw=; b=VDzhcTIaM9g51JWG54lURSfd5MyIaGh+jpazUrBLzCWO5WEIjfkMRWPf02+kQ5zvP9 hMccorxbo337dGEKwJ6mLZrb5yoyEBETwi63HnBGukcDwYAuuMOK+ITwm8rcCPto3ntN z6DzqQ1YqKGJeCemsBZVl/DCD7vi+5KNVlL4adWHm4ZKc5OaK6STbzVDuhxZ2sX60puR saEZMWvWoUVrSKKCsXOF0RpVKJavMZX+l6sCqlEcWQinvwBgz27RWK7txnQZ37iHjKUU wRMiaQZHrq03N4d/3FzO8LV/pSmEF1pQYipOrb265JJPAjVp8DHeANSofUuJSkXCMdIm 5bwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GZcsI50W8fZKEEfpBDfMPpDBGNdHj0jl0+ZTd0U5FBw=; b=FPmEQb7x7dIRKTYkQCMVnNKFpi+QUaFHGHXqpg/NKtYlY2JSdXS1JVAHi7xU2QrnGk qXsLV4hOnO9uIh8JZLN+ejWsPjXPU2XVWSBE8DsedkYmco6Z3YIyroJvskTBniJlamHt 89+dvGQvksKbfp6Kx9FtKxNtQPCcyLQO/jLMS6+ohCOEe/mUT8IvwVRo2YcIn6kdedcv Ick1RuEG11ZnaDQkJvDuUj50mOickMYZk7TLbMkGiMw1Of9Yk+IXtvnouYRPMoVvscST z0aYtYxXCSibpfF2A3dYXBZcujL9zwrWbNQSD8Jq6ZA94x5cGY1gCuXKfDErRGWLwGTG +9Hw== X-Gm-Message-State: AOAM533o/88GT8mvwMNjcn8qspq766B2scsNk7tRSAdcKw37/7WdyDxM yCIoSCmvYDLb5TssFAOexF7d32uKD2H/9A== X-Google-Smtp-Source: ABdhPJxA7ZnGEu6rf1EaWqkGkJRpWBRMeiG/yervGHRm2UPn/gKvlMJfJX/iZl/BMG6Kx2/Vvpt4Dw== X-Received: by 2002:a7b:cd01:: with SMTP id f1mr2347583wmj.177.1620698861135; Mon, 10 May 2021 19:07:41 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:40 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 19/25] net: dsa: qca8k: enlarge mdio delay and timeout Date: Tue, 11 May 2021 04:04:54 +0200 Message-Id: <20210511020500.17269-20-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The witch require some extra delay after setting page or the next read/write can use still use the old page. Add a delay after the set_page function to address this as it's done in QSDK legacy driver. Some timeouts were notice with VLAN and phy function, enlarge the mdio busy wait timeout to fix these problems. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 1 + drivers/net/dsa/qca8k.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index fd74fcaf815f..381c0e340c09 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -143,6 +143,7 @@ qca8k_set_page(struct mii_bus *bus, u16 page) } qca8k_current_page = page; + usleep_range(1000, 2000); return 0; } diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index a878486d9bcd..d365f85ab34f 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -20,7 +20,7 @@ #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 -#define QCA8K_BUSY_WAIT_TIMEOUT 20 +#define QCA8K_BUSY_WAIT_TIMEOUT 2000 #define QCA8K_NUM_FDB_RECORDS 2048 From patchwork Tue May 11 02:04:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC11C43460 for ; Tue, 11 May 2021 02:09:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9B86461622 for ; Tue, 11 May 2021 02:09:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230493AbhEKCKv (ORCPT ); Mon, 10 May 2021 22:10:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231317AbhEKCJZ (ORCPT ); Mon, 10 May 2021 22:09:25 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 673FBC06135B; Mon, 10 May 2021 19:07:44 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id m9so18491680wrx.3; Mon, 10 May 2021 19:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AvmCOiUNL/J1Z55AamjlG9ZqLZyqiT6b00mxThZzYLg=; b=ivJQh3q/DDvzpo1Oq69+kgli2nrFXYzISJnHIXJ8WDH1S7aogzm/9r2xYWvg+Y1vAg JEQWJrCAeWzVmcT+I6iotXp/OvP2B+eKPAOyk7dBAutBAeSQHHpC0R+VxU9Mq8CX4HFN /JfuNGtgSsnrN/1pLHB6iiBBpW2lWG8ShGY1MCZWZ9m6WYx/5lrtNLxAWq55pn/32OXM woDB8OCFOzSwRBROiq49LplOFnHbUH8VUN+78tSL9SjAOBYPsPOpfH9+09hxWJqUXnK8 +yRl3wkTEjFo20BtOZEFacV31QWiTG9dWbVh4pVKrSuEve6BFud3ABuKSOzv/NXnmyll 7ADA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AvmCOiUNL/J1Z55AamjlG9ZqLZyqiT6b00mxThZzYLg=; b=fQQcLYKtaTNv7gsw7Ffz6Mq/xSXvimWCyQ2ErXsO6qMRyJ5lRdJvtttBlt7jXGSolA LHbqM3LCy90Spvw6V5DbI1GWoyChRbmq7HcIwkOhXQqD0C0MoxQThUJiX1oiLrg/55vA YMKdZ/h8+rvQs/FSPGYkd6+GsdN5eUEWykEofsak8HeHZ3l9hbBUSwe5BcYiEDd3GPlK I/XVmM+JTMp/GpCdUz1G3bYHyEswAIWHyM7hwSdj4T4L+bsRrLDeehJtuT1xdf/4yZWy qtW8IsuZ565cCUPgEvUow+7PiutZFx/i7UcSV2uuOBvvP8zC9tQfT2vY6DPhvvw6NFOJ 4Lhw== X-Gm-Message-State: AOAM531eTNwgbisx3/SYrX6pqACXh+KKksnU0g2Ee57coUR+SZHNVgKa 6AnHI4XK7JuGdoPAeEDBN4Y= X-Google-Smtp-Source: ABdhPJxvP9hwMWXlXCj/uiagioo2payquVWLbu8S1bsjrESvx83zcnmy0zLDqcVaSwsn2GwG24Q/mQ== X-Received: by 2002:adf:f192:: with SMTP id h18mr33300328wro.270.1620698863073; Mon, 10 May 2021 19:07:43 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:42 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 21/25] devicetree: bindings: dsa: qca8k: Document internal mdio definition Date: Tue, 11 May 2021 04:04:56 +0200 Message-Id: <20210511020500.17269-22-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document new way of declare mapping of internal PHY to port. The new implementation directly declare the PHY connected to the port by adding a node in the switch node. The driver detect this and register an internal mdiobus using the mapping defined in the mdio node. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- .../devicetree/bindings/net/dsa/qca8k.txt | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 1daf68e7ae19..3973a9d3e426 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -21,6 +21,10 @@ described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external mdio-bus each subnode describing a port needs to have a valid phandle referencing the internal PHY it is connected to. This is because there's no N:N mapping of port and PHY id. +To declare the internal mdio-bus configuration, declare a mdio node in the +switch node and declare the phandle for the port referencing the internal +PHY is connected to. In this config a internal mdio-bus is registred and +the mdio MASTER is used as communication. Don't use mixed external and internal mdio-bus configurations, as this is not supported by the hardware. @@ -150,26 +154,61 @@ for the internal master mdio-bus configuration: port@1 { reg = <1>; label = "lan1"; + phy-mode = "internal"; + phy-handle = <&phy_port1>; }; port@2 { reg = <2>; label = "lan2"; + phy-mode = "internal"; + phy-handle = <&phy_port2>; }; port@3 { reg = <3>; label = "lan3"; + phy-mode = "internal"; + phy-handle = <&phy_port3>; }; port@4 { reg = <4>; label = "lan4"; + phy-mode = "internal"; + phy-handle = <&phy_port4>; }; port@5 { reg = <5>; label = "wan"; + phy-mode = "internal"; + phy-handle = <&phy_port5>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; }; }; }; From patchwork Tue May 11 02:04:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B9A9C433B4 for ; Tue, 11 May 2021 02:09:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8107B61622 for ; Tue, 11 May 2021 02:09:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231177AbhEKCK5 (ORCPT ); Mon, 10 May 2021 22:10:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231163AbhEKCJ1 (ORCPT ); Mon, 10 May 2021 22:09:27 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F830C061360; Mon, 10 May 2021 19:07:46 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id n2so18537629wrm.0; Mon, 10 May 2021 19:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DJf85nxR69z/IKM3e9jg3hcn7qldqV13DtN14Eg44tU=; b=Si1gonHqAV9KSijXAQKyMyRSkq8azzaeqXz/E/taqjYlarT8QL+9p/mmXlZkiCgdeW i55vTPrMVIADXTPiwc3V26bZcuPsqRN0z3f2icANjfiTh3H+rYNo8r0J4iZqki3/u7ig IRpXzZVXdNEI/fHlP8LUEi3eMmC6rCXDORU0CMw05+/AyUIwv1y1TSoE5ellgFNODU1b +R8WcRIfUtkLystMDi4/hVcEHPIx5jwLJfLCqDgvt7qZbMDSTuv9hjBXU77PfWAmmOXB 9jQWPs800HgSK36JjKnLcoVy7H08BZ4FYNCl9ijbJD0x30LSj+YkNDTCvmKPyILLjsMp v/sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DJf85nxR69z/IKM3e9jg3hcn7qldqV13DtN14Eg44tU=; b=ovAB/m+zcqqMCsl+ub7fNIt91KtjLPq228KcOFrhynlx0Oa58ksoRHCqS74QCyexZZ ErWkmy+edE/R9mFa7jKay8U6YabpF1g48p6rVRacVawBDflctEJj565wwN0mCWSxXklr 3833rnBPb24t/7nWn2ootvqqIQ0d9tbm3TbhVpNJO+WsWJymxye8hQZO7hNFVVb74Vfl xunvAr92UxeWM3ywFiW2SqjEFr245tY9Ab6YScD94l3jeel+Txuo0Zsspe8PGz5sHFbm bG1PEV7EGLStulV/P09gG0WKzV4dRfRlC6Dz+bw2VGz6+OBXphDfdhbdHhVYJY6rYSQS H/hA== X-Gm-Message-State: AOAM533IjbnYKCYacRFruBrTgBnavJHGPyai8GhLz8yO+OlYxMzpdPJm IuzjMMZrVREv3Z7H3l7wn10= X-Google-Smtp-Source: ABdhPJxPKiDcLt04X5gfYU/QdVa+Qc3Bm+N1/auesDeSj2+Y5lit5NlrK4kI5G6mZvBIiyYyxnagBw== X-Received: by 2002:a05:6000:508:: with SMTP id a8mr34298376wrf.315.1620698865027; Mon, 10 May 2021 19:07:45 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:44 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 23/25] net: dsa: qca8k: pass switch_revision info to phy dev_flags Date: Tue, 11 May 2021 04:04:58 +0200 Message-Id: <20210511020500.17269-24-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Define get_phy_flags to pass switch_Revision needed to tweak the internal PHY with debug values based on the revision. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 920cdb1ff2b9..9da7eccfa558 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1732,6 +1732,22 @@ qca8k_port_vlan_del(struct dsa_switch *ds, int port, return ret; } +static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) +{ + struct qca8k_priv *priv = ds->priv; + + /* Communicate to the phy internal driver the switch revision. + * Based on the switch revision different values needs to be + * set to the dbg and mmd reg on the phy. + * The first 2 bit are used to communicate the switch revision + * to the phy driver. + */ + if (port > 0 && port < 6) + return priv->switch_revision; + + return 0; +} + static enum dsa_tag_protocol qca8k_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) @@ -1765,6 +1781,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_config = qca8k_phylink_mac_config, .phylink_mac_link_down = qca8k_phylink_mac_link_down, .phylink_mac_link_up = qca8k_phylink_mac_link_up, + .get_phy_flags = qca8k_get_phy_flags, }; static int qca8k_read_switch_id(struct qca8k_priv *priv) From patchwork Tue May 11 02:05:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 434753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5B9FC433ED for ; Tue, 11 May 2021 02:10:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA625615FF for ; Tue, 11 May 2021 02:10:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231410AbhEKCMD (ORCPT ); Mon, 10 May 2021 22:12:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231510AbhEKCKT (ORCPT ); Mon, 10 May 2021 22:10:19 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 688BAC061374; Mon, 10 May 2021 19:07:48 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id l14so18489900wrx.5; Mon, 10 May 2021 19:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yrouvi/9fMa7pZwwu1IYTzVcHv3akTB20OT7DgY4UJw=; b=URjXRd67v76jugQ5NLtW/3bdEkKsceIJJ6kY/ZzdXwVMzesK5A6/Y533Elk7BRaAVd 4vUWjOGLFqnEld7kRkew1x7VB+57HVGN0pVSdikYrUlxEW9kvzjALj2sZsjCfRVLvloW H/+NBFXbXdgiJNUWHN9tNlMOQ9ISiPrRUW8hHQCJlGLani+YNuXZ4/AscJgQyCo6rvu3 6gHB5jB/maTRKSqJV6texmJMVOqUrlhl6A4rv7Y0GmlTK38UsNkCDJ6zl+rhvo4SaSxQ 62PKjU6qnlYGs8nyffqhH61hclzju3Ii4Hvc3jNMuDeKqWJFKyL9r2aemd6jZY9BmfBS +7Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yrouvi/9fMa7pZwwu1IYTzVcHv3akTB20OT7DgY4UJw=; b=MxrZSJTZnp8EWjJMPkeY/G7Bu5aGcjV8zyvvAyPhKccdgi0BeES4Yb3VLdyFYCnpjb XM2I/dOl6k4ZvWtFfXzFp0V1Mikw6GO0+6QGKUxmvAbwm/txzy3k+31VMzRNjcZBM8sU Dq5yL9j9VNxkssKvAZqq3Ct6tTfiNfwN9AwSW3hrWFRnwpX2DRoHGYcOJ58CQU98+zN4 2dQjqB0MMDdx5gvVu+Mn+WUuk6EanehTlDK7bq+Acr0XSmIBYotBCY8eLDfOnPiVWFJ3 xshi5frykVSD7QO6XkMH2/1Y+9/+zuXdjLkWEfgJ2Cuwn/Q5IxdzrIz2ki3t25Oz9CI7 /yaw== X-Gm-Message-State: AOAM530CsSez17TuBg7ame4glfxbdXSJcPBHEfJzM+g7+5p4EipZRu32 JB31aR6krGSYnoQOCgJW4gM= X-Google-Smtp-Source: ABdhPJy23hZ+2ryMsXYmPa/0Vy6tUAawnU5dVdY81yK+9SSWXR7E/+1JfoQ6kr91eAvScJ49a97Jig== X-Received: by 2002:a5d:4521:: with SMTP id j1mr33690911wra.116.1620698867019; Mon, 10 May 2021 19:07:47 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id q20sm2607436wmq.2.2021.05.10.19.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 19:07:46 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org (open list:NETWORKING DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: Ansuel Smith Subject: [RFC PATCH net-next v5 25/25] net: phy: add support for qca8k switch internal PHY in at803x Date: Tue, 11 May 2021 04:05:00 +0200 Message-Id: <20210511020500.17269-26-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511020500.17269-1-ansuelsmth@gmail.com> References: <20210511020500.17269-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since the at803x share the same regs, it's assumed they are based on the same implementation. Make it part of the at803x PHY driver to skip having redudant code. Add initial support for qca8k internal PHYs. The internal PHYs requires special mmd and debug values to be set based on the switch revision passwd using the dev_flags. Supports output of idle, receive and eee_wake errors stats. Some debug values sets can't be translated as the documentation lacks any reference about them. Signed-off-by: Ansuel Smith --- drivers/net/phy/Kconfig | 5 +- drivers/net/phy/at803x.c | 132 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 134 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 288bf405ebdb..25511f39b01f 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -247,10 +247,11 @@ config NXP_TJA11XX_PHY Currently supports the NXP TJA1100 and TJA1101 PHY. config AT803X_PHY - tristate "Qualcomm Atheros AR803X PHYs" + tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" depends on REGULATOR help - Currently supports the AR8030, AR8031, AR8033 and AR8035 model + Currently supports the AR8030, AR8031, AR8033, AR8035 and internal + QCA8337(Internal qca8k PHY) model config QSEMI_PHY tristate "Quality Semiconductor PHYs" diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index d2378a73de6f..6697c9368b40 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -92,10 +92,16 @@ #define AT803X_DEBUG_REG_5 0x05 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) +#define AT803X_DEBUG_REG_3C 0x3C + +#define AT803X_DEBUG_REG_3D 0x3D + #define AT803X_DEBUG_REG_1F 0x1F #define AT803X_DEBUG_PLL_ON BIT(2) #define AT803X_DEBUG_RGMII_1V8 BIT(3) +#define MDIO_AZ_DEBUG 0x800D + /* AT803x supports either the XTAL input pad, an internal PLL or the * DSP as clock reference for the clock output pad. The XTAL reference * is only used for 25 MHz output, all other frequencies need the PLL. @@ -144,6 +150,12 @@ #define ATH8035_PHY_ID 0x004dd072 #define AT8030_PHY_ID_MASK 0xffffffef +#define QCA8327_PHY_ID 0x004dd034 +#define QCA8337_PHY_ID 0x004dd036 +#define QCA8K_PHY_ID_MASK 0xffffffff + +#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) + #define AT803X_PAGE_FIBER 0 #define AT803X_PAGE_COPPER 1 @@ -155,6 +167,24 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); +enum stat_access_type { + PHY, + MMD +}; + +struct at803x_hw_stat { + const char *string; + u8 reg; + u32 mask; + enum stat_access_type access_type; +}; + +static struct at803x_hw_stat at803x_hw_stats[] = { + { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, + { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, + { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, +}; + struct at803x_priv { int flags; u16 clk_25m_reg; @@ -164,6 +194,7 @@ struct at803x_priv { struct regulator_dev *vddio_rdev; struct regulator_dev *vddh_rdev; struct regulator *vddio; + u64 stats[ARRAY_SIZE(at803x_hw_stats)]; }; struct at803x_context { @@ -175,6 +206,17 @@ struct at803x_context { u16 led_control; }; +static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) +{ + int ret; + + ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); + if (ret < 0) + return ret; + + return phy_write(phydev, AT803X_DEBUG_DATA, data); +} + static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) { int ret; @@ -337,6 +379,53 @@ static void at803x_get_wol(struct phy_device *phydev, wol->wolopts |= WAKE_MAGIC; } +static int at803x_get_sset_count(struct phy_device *phydev) +{ + return ARRAY_SIZE(at803x_hw_stats); +} + +static void at803x_get_strings(struct phy_device *phydev, u8 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { + strscpy(data + i * ETH_GSTRING_LEN, + at803x_hw_stats[i].string, ETH_GSTRING_LEN); + } +} + +static u64 at803x_get_stat(struct phy_device *phydev, int i) +{ + struct at803x_hw_stat stat = at803x_hw_stats[i]; + struct at803x_priv *priv = phydev->priv; + int val; + u64 ret; + + if (stat.access_type == MMD) + val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); + else + val = phy_read(phydev, stat.reg); + + if (val < 0) { + ret = U64_MAX; + } else { + val = val & stat.mask; + priv->stats[i] += val; + ret = priv->stats[i]; + } + + return ret; +} + +static void at803x_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, u64 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) + data[i] = at803x_get_stat(phydev, i); +} + static int at803x_suspend(struct phy_device *phydev) { int value; @@ -1172,6 +1261,34 @@ static int at803x_cable_test_start(struct phy_device *phydev) return 0; } +static int qca83xx_config_init(struct phy_device *phydev) +{ + u8 switch_revision; + + switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; + + switch (switch_revision) { + case 1: + /* For 100M waveform */ + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea); + /* Turn on Gigabit clock */ + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0); + break; + + case 2: + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); + fallthrough; + case 4: + phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860); + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46); + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); + break; + } + + return 0; +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -1268,7 +1385,20 @@ static struct phy_driver at803x_driver[] = { .read_status = at803x_read_status, .soft_reset = genphy_soft_reset, .config_aneg = at803x_config_aneg, -} }; +}, { + /* QCA8337 */ + .phy_id = QCA8337_PHY_ID, + .phy_id_mask = QCA8K_PHY_ID_MASK, + .name = "QCA PHY 8337", + /* PHY_GBIT_FEATURES */ + .probe = at803x_probe, + .flags = PHY_IS_INTERNAL, + .config_init = qca83xx_config_init, + .soft_reset = genphy_soft_reset, + .get_sset_count = at803x_get_sset_count, + .get_strings = at803x_get_strings, + .get_stats = at803x_get_stats, +}, }; module_phy_driver(at803x_driver);