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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id m4sm3699740ljc.20.2021.05.11.06.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 May 2021 06:29:35 -0700 (PDT) From: Linus Walleij To: Matt Mackall , Herbert Xu , Deepak Saxena Cc: linux-crypto@vger.kernel.org, Arnd Bergmann , Linus Walleij Subject: [PATCH 1/5] hw_random: ixp4xx: enable compile-testing Date: Tue, 11 May 2021 15:29:24 +0200 Message-Id: <20210511132928.814697-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Arnd Bergmann The driver is almost portable already, it just needs to include the new header for the cpu definition. Cc: Deepak Saxena Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- The idea is to apply this through the ARM SoC tree along with other IXP4xx refactorings. Please tell me if you prefer another solution. --- drivers/char/hw_random/Kconfig | 2 +- drivers/char/hw_random/ixp4xx-rng.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.30.2 Acked-by: Herbert Xu diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 1fe006f3f12f..f033a11cc90d 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -152,7 +152,7 @@ config HW_RANDOM_VIA config HW_RANDOM_IXP4XX tristate "Intel IXP4xx NPU HW Pseudo-Random Number Generator support" - depends on ARCH_IXP4XX + depends on ARCH_IXP4XX || COMPILE_TEST default HW_RANDOM help This driver provides kernel-side support for the Pseudo-Random diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c index beec1627db3c..34781028caec 100644 --- a/drivers/char/hw_random/ixp4xx-rng.c +++ b/drivers/char/hw_random/ixp4xx-rng.c @@ -21,10 +21,9 @@ #include #include #include +#include #include -#include - static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer) { From patchwork Tue May 11 13:29:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 434206 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3831797jao; Tue, 11 May 2021 06:29:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzE+r02ouBBiF4bZ2OwPNJUb5n371qFhKHh2oSza9V9iJ/LLUVORwI76oTwnzrZqpZwhps X-Received: by 2002:a05:6512:3487:: with SMTP id v7mr21341780lfr.544.1620739781218; Tue, 11 May 2021 06:29:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620739781; cv=none; d=google.com; s=arc-20160816; b=ECXkrOi32CY54tZKs3FeWGXQ0qdZB50BCZehcc5aqAjQSsdTyfC9gEpZXA743z9snJ mAZJArII91BmQtTK6bJ7LBFpOw/Wqa0XijhldHqj+C+Gy4t5orf136AMLtemkNqcvT/V x970maaTpgQrh9a53Q1vmbxS+LctNzsQYwGi2tiUDJZ4ae2CKzYboDsiF4GPKS3xuRG8 /XrOV5UnL5IUuzUsj065xjbZ8iUG1iVIH/pQUsvAPPbBFP8U031p5AkbecdkKDhgy9u/ z2O+8kfaGHrATky9fKPsY9VTMluz3M2wlM9aIgP0upWXFEyxKnwIZZjJEI41XH0GUAMj JWOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BOC1UntVrV5zpNlzc6ixNauCfquIt1wUm//U5RB1WOI=; b=gRVDL8zQEG/pivkaLvcqn7AGuwyI5U90IhsdXeOj68hkv+LFgtdv7bh7w3WqCGoERa ldG7ge7m2EsKT77pVVBLOImyZzdM6Mp3WXQiK5kKr/V6JLPXIZ+KFboCAiUj6Dz0VQJm EeVeUL3CwknV8YEdwHMZv1DWG1VKUXB277FeeMesO068DpY6VsLVUHutp9XYzwYO3fp0 ii/GX5IF3E42DwMonvuCFYIpQZZp/j0uV37GXKuUa3RbiywoOippsbEIqg+OtU3uHxyL fswqyEv1UjRNTWcim0h3WOKQHVElontu/G4oSu3yt4ohcmqq6kFLJvm3cqjXKviC2+m0 ZXgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TM7CX+82; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id m4sm3699740ljc.20.2021.05.11.06.29.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 May 2021 06:29:38 -0700 (PDT) From: Linus Walleij To: Matt Mackall , Herbert Xu , Deepak Saxena Cc: linux-crypto@vger.kernel.org, Arnd Bergmann , Linus Walleij Subject: [PATCH 2/5] hw_random: ixp4xx: Use SPDX license tag Date: Tue, 11 May 2021 15:29:25 +0200 Message-Id: <20210511132928.814697-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511132928.814697-1-linus.walleij@linaro.org> References: <20210511132928.814697-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This switches the IXP4xx hardware random driver to use the SPDX type license tag. Cc: Deepak Saxena Signed-off-by: Linus Walleij --- The idea is to apply this through the ARM SoC tree along with other IXP4xx refactorings. Please tell me if you prefer another solution. --- drivers/char/hw_random/ixp4xx-rng.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.30.2 Acked-by: Herbert Xu diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c index 34781028caec..defd8176cb68 100644 --- a/drivers/char/hw_random/ixp4xx-rng.c +++ b/drivers/char/hw_random/ixp4xx-rng.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * drivers/char/hw_random/ixp4xx-rng.c * @@ -8,10 +9,6 @@ * Copyright 2005 (c) MontaVista Software, Inc. * * Fixes by Michael Buesch - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include From patchwork Tue May 11 13:29:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 434207 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3831881jao; Tue, 11 May 2021 06:29:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx86Pmto4GveoHKakfZzf2EUzjMJJ5mRJq5UvTL5PeTCRFw+oIcyyiah36BXurCw/ckT4VJ X-Received: by 2002:a2e:87cb:: with SMTP id v11mr6405794ljj.113.1620739786968; Tue, 11 May 2021 06:29:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620739786; cv=none; d=google.com; s=arc-20160816; b=EgysnLxqcLqh7+kDQsFIFSz1C9jTWzpqqrifMAeGcLPd3mNMjkuxk2eelHYcY1L4Aj 5iQz5tsBxMbpBAXMu13ABxbSNRvFos8euAOfri3kjoNfnqp++MA63rB35x0BSypbKowK 4iC5Z+hXuG/twtt5qf2gt7DYezaFJHAgzD1QTqH3CIjNxdsBVdTwnjh9lEVp2BsbuyrI hr+vuws3Y/W5rid4dj8bKwA6TdZGwKa07prD6lT3lbkvs4vCWffVxAy9jB1vA5cFcETi DQfzRIOozM/A1rGqxqhL7vzaxn9wNeqXrgMPX+IvFC+HZNiqVgzQrlI4uD6xcuNoCbJQ 4uBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0kH9GejFwRKEAZVnNqAOcSajeuUIKWFZ2mSCj9ztQJ4=; b=gJMNcKtnrIzW3kk/7FYAH1n8lB2FDu/RvhUBopLvqa96ioJqfHcPjBJwpCPqxosJeU 7qMqwDtlkw72JTF6WMq3oaxXfPwsggWCjq2aVcT3XZ1JO0JCZPiLN/eFN+aMN1jShgZE Oa+IdschLZQtfwjkKMe96W6o/AqZTPeV5jCIaxT+YnpeVUSxoCEfkv8ErfJIlDTZbW/T qPApB3l7oPl1eyH5sNIuq1DyTtgsGy/OY7dGaFNNkWl/U4Yy1hbZRfw5qjJ5635BX2p6 2j+HyOQlc1zAUUq4gadbAqhKY6B8njLbFobSZhcea+qkS8h/44YnPWwqme5xFXHn1ucQ 9hhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uAGW7Wix; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id m4sm3699740ljc.20.2021.05.11.06.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 May 2021 06:29:39 -0700 (PDT) From: Linus Walleij To: Matt Mackall , Herbert Xu , Deepak Saxena Cc: linux-crypto@vger.kernel.org, Arnd Bergmann , Linus Walleij Subject: [PATCH 3/5] hw_random: ixp4xx: Turn into a module Date: Tue, 11 May 2021 15:29:26 +0200 Message-Id: <20210511132928.814697-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511132928.814697-1-linus.walleij@linaro.org> References: <20210511132928.814697-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Instead of just initializing always, which will invariably create problems on multiplatform builds, turn this driver into a module and pass a resource with the memory location. The device only exist on the IXP46x so we only register the device for the IXP46x SoC. Cc: Deepak Saxena Signed-off-by: Linus Walleij --- The idea is to apply this through the ARM SoC tree along with other IXP4xx refactorings. Please tell me if you prefer another solution. --- arch/arm/mach-ixp4xx/common.c | 24 ++++++++++++++++++- drivers/char/hw_random/ixp4xx-rng.c | 37 +++++++++++++---------------- 2 files changed, 40 insertions(+), 21 deletions(-) -- 2.30.2 Acked-by: Herbert Xu diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index f86c1bf34eea..a10aa14d09b1 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -237,6 +237,27 @@ static struct resource ixp46x_i2c_resources[] = { } }; +/* A single 32-bit register on IXP46x */ +#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100 + +static struct resource ixp46x_hwrandom_resource[] = { + { + .start = IXP4XX_HWRANDOM_BASE_PHYS, + .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ixp46x_hwrandom_device = { + .name = "ixp4xx-hwrandom", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = ixp46x_hwrandom_resource, + .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource), +}; + /* * I2C controller. The IXP46x uses the same block as the IOP3xx, so * we just use the same device name. @@ -249,7 +270,8 @@ static struct platform_device ixp46x_i2c_controller = { }; static struct platform_device *ixp46x_devices[] __initdata = { - &ixp46x_i2c_controller + &ixp46x_hwrandom_device, + &ixp46x_i2c_controller, }; unsigned long ixp4xx_exp_bus_size; diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c index defd8176cb68..8b59aeefd4a4 100644 --- a/drivers/char/hw_random/ixp4xx-rng.c +++ b/drivers/char/hw_random/ixp4xx-rng.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -36,35 +37,31 @@ static struct hwrng ixp4xx_rng_ops = { .data_read = ixp4xx_rng_data_read, }; -static int __init ixp4xx_rng_init(void) +static int ixp4xx_rng_probe(struct platform_device *pdev) { void __iomem * rng_base; - int err; + struct device *dev = &pdev->dev; + struct resource *res; if (!cpu_is_ixp46x()) /* includes IXP455 */ return -ENOSYS; - rng_base = ioremap(0x70002100, 4); - if (!rng_base) - return -ENOMEM; - ixp4xx_rng_ops.priv = (unsigned long)rng_base; - err = hwrng_register(&ixp4xx_rng_ops); - if (err) - iounmap(rng_base); - - return err; -} + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rng_base = devm_ioremap_resource(dev, res); + if (IS_ERR(rng_base)) + return PTR_ERR(rng_base); -static void __exit ixp4xx_rng_exit(void) -{ - void __iomem * rng_base = (void __iomem *)ixp4xx_rng_ops.priv; - - hwrng_unregister(&ixp4xx_rng_ops); - iounmap(rng_base); + ixp4xx_rng_ops.priv = (unsigned long)rng_base; + return devm_hwrng_register(dev, &ixp4xx_rng_ops); } -module_init(ixp4xx_rng_init); -module_exit(ixp4xx_rng_exit); +static struct platform_driver ixp4xx_rng_driver = { + .driver = { + .name = "ixp4xx-hwrandom", + }, + .probe = ixp4xx_rng_probe, +}; +module_platform_driver(ixp4xx_rng_driver); MODULE_AUTHOR("Deepak Saxena "); MODULE_DESCRIPTION("H/W Pseudo-Random Number Generator (RNG) driver for IXP45x/46x"); From patchwork Tue May 11 13:29:27 2021 Content-Type: text/plain; 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id m4sm3699740ljc.20.2021.05.11.06.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 May 2021 06:29:42 -0700 (PDT) From: Linus Walleij To: Matt Mackall , Herbert Xu , Deepak Saxena Cc: linux-crypto@vger.kernel.org, Arnd Bergmann , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 4/5] hw_random: ixp4xx: Add DT bindings Date: Tue, 11 May 2021 15:29:27 +0200 Message-Id: <20210511132928.814697-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511132928.814697-1-linus.walleij@linaro.org> References: <20210511132928.814697-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This adds device tree bindings for the simple random number generator found in the IXP46x SoCs. Cc: Deepak Saxena Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Reviewed-by: Rob Herring --- The idea is to apply this through the ARM SoC tree along with other IXP4xx refactorings. Please tell me if you prefer another solution. --- .../bindings/rng/intel,ixp46x-rng.yaml | 36 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml diff --git a/Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml b/Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml new file mode 100644 index 000000000000..61963fa9347e --- /dev/null +++ b/Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/intel,ixp46x-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP46x RNG bindings + +description: | + The Intel IXP46x has a random number generator at a fixed physical + location in memory. Each read is guaranteed to provide a unique + 32 bit random number. + +maintainers: + - Linus Walleij + +properties: + compatible: + const: intel,ixp46x-rng + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rng@70002100 { + compatible = "intel,ixp46x-rng"; + reg = <0x70002100 4>; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index bd7aff0c120f..cc4bb4e75f04 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9248,6 +9248,7 @@ F: include/linux/soc/ixp4xx/qmgr.h INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT M: Deepak Saxena S: Maintained +F: Documentation/devicetree/bindings/display/intel,ixp46x-rng.yaml F: drivers/char/hw_random/ixp4xx-rng.c INTEL KEEM BAY DRM DRIVER From patchwork Tue May 11 13:29:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 434208 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3831888jao; Tue, 11 May 2021 06:29:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzGEosvbTC3A3t5uTShUWhtBkm6fCMLfEwINN3j21l+wIQzlmwzkvAeGqnsDYX9z2UTiR+U X-Received: by 2002:a19:771b:: with SMTP id s27mr21524981lfc.111.1620739787416; Tue, 11 May 2021 06:29:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620739787; cv=none; d=google.com; s=arc-20160816; b=AgNKSvEh3farwBY61oYXhWn+HFv7v1oLT1FoAbf40eZQI7NO2xr+UUPOTbXCqn/2po 2kHlKG1a3wm3xVRXVh1nonmd5t8FmKK3eH2G1ozUpLDhIwsBBYWe3chWwDQTUolAGSlJ GqHXx4k1pnXT1PLPZ0LD7swNC1Z7mzmfY3v8iBzBhi5vbsMHK6bNpIWvvz88/ucHC8eX 7+4irEjZQoQ3NdN0+NKcKn154j65TJt15ddunjUCPZdzdOK2suOiXpT8Za/clRi+iI8p HFr9Ui62QjeuU3Ml45t0+3eubndnEvvOnU6xsvfgDOYD0as/ANM5PQtSkFMJiIBj75M6 /YiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=X1K7rwa/77HQwchJ9fJE8GZcfgMpgknk71cF9VgYv1o=; b=S/lQzxEQtQWPfZObP+g8RCAQLGJmebU82YAHO1Nepd4RC8xZoVFQ35ER7NxTiT9BCG n5rrCzwKdCzh1uyxQCPrJB8iGNLU9n8vfMlC8noiQN2gJ3Ui2ySjMrITUwvMReDNEjgm 6Tf4oilYrK29TSFfWqyB62ouS/FXF/6Kxk+mSAHf16p8X7C4TTSoovXDC0g2I7TPLzr2 A+iEoGcov/Duw7fU3gCOGi9YhEp54WKMbVnGRbWa5E4L6Ov80ZE92TQGVpuOxvzagQ69 3IdM58uqJrDfeENfaUHX5Dea2GfehNeUximCmPSW9eiFCy8mv+tfPG4rZwqnucIQHSa8 7zFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xlDW7nnB; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id m4sm3699740ljc.20.2021.05.11.06.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 May 2021 06:29:43 -0700 (PDT) From: Linus Walleij To: Matt Mackall , Herbert Xu , Deepak Saxena Cc: linux-crypto@vger.kernel.org, Arnd Bergmann , Linus Walleij Subject: [PATCH 5/5] hw_random: ixp4xx: Add OF support Date: Tue, 11 May 2021 15:29:28 +0200 Message-Id: <20210511132928.814697-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210511132928.814697-1-linus.walleij@linaro.org> References: <20210511132928.814697-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This makes the hardware random number generator found in the IXP46x SoCs probe from the device tree. Cc: Deepak Saxena Signed-off-by: Linus Walleij --- The idea is to apply this through the ARM SoC tree along with other IXP4xx refactorings. Please tell me if you prefer another solution. --- drivers/char/hw_random/ixp4xx-rng.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.30.2 Acked-by: Herbert Xu diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c index 8b59aeefd4a4..188854dd16a9 100644 --- a/drivers/char/hw_random/ixp4xx-rng.c +++ b/drivers/char/hw_random/ixp4xx-rng.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -55,9 +56,18 @@ static int ixp4xx_rng_probe(struct platform_device *pdev) return devm_hwrng_register(dev, &ixp4xx_rng_ops); } +static const struct of_device_id ixp4xx_rng_of_match[] = { + { + .compatible = "intel,ixp46x-rng", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ixp4xx_rng_of_match); + static struct platform_driver ixp4xx_rng_driver = { .driver = { .name = "ixp4xx-hwrandom", + .of_match_table = ixp4xx_rng_of_match, }, .probe = ixp4xx_rng_probe, };